Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:41:03.705111 lava-dispatcher, installed at version: 2024.01
2 01:41:03.705898 start: 0 validate
3 01:41:03.706378 Start time: 2024-10-10 01:41:03.706348+00:00 (UTC)
4 01:41:03.706933 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:41:03.707487 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:41:03.743318 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:41:03.743836 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-74-gd3d1556696c1a%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:41:03.772852 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:41:03.773470 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-74-gd3d1556696c1a%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:41:04.822158 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:41:04.822685 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-74-gd3d1556696c1a%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:41:04.865789 validate duration: 1.16
14 01:41:04.866632 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:41:04.866971 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:41:04.867278 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:41:04.867865 Not decompressing ramdisk as can be used compressed.
18 01:41:04.868332 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:41:04.868578 saving as /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/ramdisk/rootfs.cpio.gz
20 01:41:04.868835 total size: 8181887 (7 MB)
21 01:41:04.904352 progress 0 % (0 MB)
22 01:41:04.910139 progress 5 % (0 MB)
23 01:41:04.915493 progress 10 % (0 MB)
24 01:41:04.921303 progress 15 % (1 MB)
25 01:41:04.926642 progress 20 % (1 MB)
26 01:41:04.932412 progress 25 % (1 MB)
27 01:41:04.937678 progress 30 % (2 MB)
28 01:41:04.943406 progress 35 % (2 MB)
29 01:41:04.948660 progress 40 % (3 MB)
30 01:41:04.954294 progress 45 % (3 MB)
31 01:41:04.959680 progress 50 % (3 MB)
32 01:41:04.965399 progress 55 % (4 MB)
33 01:41:04.970675 progress 60 % (4 MB)
34 01:41:04.976329 progress 65 % (5 MB)
35 01:41:04.981613 progress 70 % (5 MB)
36 01:41:04.987187 progress 75 % (5 MB)
37 01:41:04.992376 progress 80 % (6 MB)
38 01:41:04.998025 progress 85 % (6 MB)
39 01:41:05.003354 progress 90 % (7 MB)
40 01:41:05.009070 progress 95 % (7 MB)
41 01:41:05.013775 progress 100 % (7 MB)
42 01:41:05.014416 7 MB downloaded in 0.15 s (53.61 MB/s)
43 01:41:05.014963 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:41:05.015850 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:41:05.016172 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:41:05.016446 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:41:05.016934 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/kernel/Image
49 01:41:05.017190 saving as /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/kernel/Image
50 01:41:05.017401 total size: 45713920 (43 MB)
51 01:41:05.017612 No compression specified
52 01:41:05.054030 progress 0 % (0 MB)
53 01:41:05.084368 progress 5 % (2 MB)
54 01:41:05.117894 progress 10 % (4 MB)
55 01:41:05.147852 progress 15 % (6 MB)
56 01:41:05.177013 progress 20 % (8 MB)
57 01:41:05.205651 progress 25 % (10 MB)
58 01:41:05.234872 progress 30 % (13 MB)
59 01:41:05.264042 progress 35 % (15 MB)
60 01:41:05.293020 progress 40 % (17 MB)
61 01:41:05.321934 progress 45 % (19 MB)
62 01:41:05.351429 progress 50 % (21 MB)
63 01:41:05.380772 progress 55 % (24 MB)
64 01:41:05.410038 progress 60 % (26 MB)
65 01:41:05.439086 progress 65 % (28 MB)
66 01:41:05.468683 progress 70 % (30 MB)
67 01:41:05.498029 progress 75 % (32 MB)
68 01:41:05.527128 progress 80 % (34 MB)
69 01:41:05.556208 progress 85 % (37 MB)
70 01:41:05.585332 progress 90 % (39 MB)
71 01:41:05.614387 progress 95 % (41 MB)
72 01:41:05.642907 progress 100 % (43 MB)
73 01:41:05.643424 43 MB downloaded in 0.63 s (69.64 MB/s)
74 01:41:05.643911 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:41:05.644777 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:41:05.645050 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:41:05.645314 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:41:05.645956 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:41:05.646255 saving as /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:41:05.646469 total size: 54703 (0 MB)
82 01:41:05.646683 No compression specified
83 01:41:05.684485 progress 59 % (0 MB)
84 01:41:05.685342 progress 100 % (0 MB)
85 01:41:05.685894 0 MB downloaded in 0.04 s (1.32 MB/s)
86 01:41:05.686390 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:41:05.687205 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:41:05.687468 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:41:05.687733 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:41:05.688219 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/modules.tar.xz
92 01:41:05.688479 saving as /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/modules/modules.tar
93 01:41:05.688686 total size: 11595820 (11 MB)
94 01:41:05.688896 Using unxz to decompress xz
95 01:41:05.726882 progress 0 % (0 MB)
96 01:41:05.793461 progress 5 % (0 MB)
97 01:41:05.868691 progress 10 % (1 MB)
98 01:41:05.950612 progress 15 % (1 MB)
99 01:41:06.026688 progress 20 % (2 MB)
100 01:41:06.102647 progress 25 % (2 MB)
101 01:41:06.182462 progress 30 % (3 MB)
102 01:41:06.255153 progress 35 % (3 MB)
103 01:41:06.334826 progress 40 % (4 MB)
104 01:41:06.421030 progress 45 % (5 MB)
105 01:41:06.497658 progress 50 % (5 MB)
106 01:41:06.580678 progress 55 % (6 MB)
107 01:41:06.662539 progress 60 % (6 MB)
108 01:41:06.746969 progress 65 % (7 MB)
109 01:41:06.822590 progress 70 % (7 MB)
110 01:41:06.906674 progress 75 % (8 MB)
111 01:41:06.989147 progress 80 % (8 MB)
112 01:41:07.065059 progress 85 % (9 MB)
113 01:41:07.139084 progress 90 % (9 MB)
114 01:41:07.239388 progress 95 % (10 MB)
115 01:41:07.331889 progress 100 % (11 MB)
116 01:41:07.346293 11 MB downloaded in 1.66 s (6.67 MB/s)
117 01:41:07.346907 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:41:07.347753 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:41:07.348151 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 01:41:07.348700 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 01:41:07.349219 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:41:07.349725 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 01:41:07.350719 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6
125 01:41:07.351581 makedir: /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin
126 01:41:07.352330 makedir: /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/tests
127 01:41:07.352971 makedir: /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/results
128 01:41:07.353596 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-add-keys
129 01:41:07.354549 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-add-sources
130 01:41:07.355498 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-background-process-start
131 01:41:07.356481 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-background-process-stop
132 01:41:07.357481 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-common-functions
133 01:41:07.358406 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-echo-ipv4
134 01:41:07.359466 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-install-packages
135 01:41:07.360463 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-installed-packages
136 01:41:07.361405 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-os-build
137 01:41:07.362317 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-probe-channel
138 01:41:07.363214 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-probe-ip
139 01:41:07.364148 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-target-ip
140 01:41:07.365058 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-target-mac
141 01:41:07.365951 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-target-storage
142 01:41:07.366863 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-case
143 01:41:07.367783 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-event
144 01:41:07.368736 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-feedback
145 01:41:07.369638 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-raise
146 01:41:07.370531 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-reference
147 01:41:07.371415 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-runner
148 01:41:07.372386 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-set
149 01:41:07.373309 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-test-shell
150 01:41:07.374240 Updating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-install-packages (oe)
151 01:41:07.375301 Updating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/bin/lava-installed-packages (oe)
152 01:41:07.376184 Creating /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/environment
153 01:41:07.376939 LAVA metadata
154 01:41:07.377455 - LAVA_JOB_ID=830738
155 01:41:07.377885 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:41:07.378551 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:41:07.380386 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:41:07.381001 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:41:07.381411 skipped lava-vland-overlay
160 01:41:07.381897 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:41:07.382403 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:41:07.382827 skipped lava-multinode-overlay
163 01:41:07.383311 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:41:07.383812 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:41:07.384337 Loading test definitions
166 01:41:07.384891 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:41:07.385333 Using /lava-830738 at stage 0
168 01:41:07.387494 uuid=830738_1.5.2.4.1 testdef=None
169 01:41:07.388118 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:41:07.388414 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:41:07.390287 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:41:07.391126 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:41:07.393528 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:41:07.394436 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:41:07.396691 runner path: /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/0/tests/0_dmesg test_uuid 830738_1.5.2.4.1
178 01:41:07.397298 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:41:07.398111 Creating lava-test-runner.conf files
181 01:41:07.398317 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/830738/lava-overlay-2rtl8km6/lava-830738/0 for stage 0
182 01:41:07.398659 - 0_dmesg
183 01:41:07.399026 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:41:07.399319 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:41:07.423141 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:41:07.423556 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:41:07.423824 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:41:07.424128 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:41:07.424402 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:41:08.343188 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:41:08.343635 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 01:41:08.343887 extracting modules file /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk
193 01:41:09.668710 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:41:09.669227 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 01:41:09.669497 [common] Applying overlay /var/lib/lava/dispatcher/tmp/830738/compress-overlay-3d87i5tq/overlay-1.5.2.5.tar.gz to ramdisk
196 01:41:09.669709 [common] Applying overlay /var/lib/lava/dispatcher/tmp/830738/compress-overlay-3d87i5tq/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk
197 01:41:09.699924 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:41:09.700384 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 01:41:09.700661 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 01:41:09.700889 Converting downloaded kernel to a uImage
201 01:41:09.701198 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/kernel/Image /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/kernel/uImage
202 01:41:10.169758 output: Image Name:
203 01:41:10.170179 output: Created: Thu Oct 10 01:41:09 2024
204 01:41:10.170409 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:41:10.170628 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 01:41:10.170839 output: Load Address: 01080000
207 01:41:10.171074 output: Entry Point: 01080000
208 01:41:10.171317 output:
209 01:41:10.171693 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:41:10.172049 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:41:10.172389 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 01:41:10.172703 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:41:10.173018 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 01:41:10.173322 Building ramdisk /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk
215 01:41:12.563824 >> 181557 blocks
216 01:41:21.040452 Adding RAMdisk u-boot header.
217 01:41:21.041104 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk.cpio.gz.uboot
218 01:41:21.319072 output: Image Name:
219 01:41:21.319494 output: Created: Thu Oct 10 01:41:21 2024
220 01:41:21.319703 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:41:21.319908 output: Data Size: 26054853 Bytes = 25444.19 KiB = 24.85 MiB
222 01:41:21.320261 output: Load Address: 00000000
223 01:41:21.320661 output: Entry Point: 00000000
224 01:41:21.321052 output:
225 01:41:21.322017 rename /var/lib/lava/dispatcher/tmp/830738/extract-overlay-ramdisk-4iz_yvmj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot
226 01:41:21.322713 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 01:41:21.323244 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 01:41:21.323760 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 01:41:21.324241 No LXC device requested
230 01:41:21.324735 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:41:21.325236 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 01:41:21.325718 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:41:21.326124 Checking files for TFTP limit of 4294967296 bytes.
234 01:41:21.328841 end: 1 tftp-deploy (duration 00:00:16) [common]
235 01:41:21.329424 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:41:21.329937 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:41:21.330426 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:41:21.330918 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:41:21.331439 Using kernel file from prepare-kernel: 830738/tftp-deploy-8yc8yatz/kernel/uImage
240 01:41:21.332084 substitutions:
241 01:41:21.332507 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:41:21.332906 - {DTB_ADDR}: 0x01070000
243 01:41:21.333302 - {DTB}: 830738/tftp-deploy-8yc8yatz/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:41:21.333695 - {INITRD}: 830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot
245 01:41:21.334089 - {KERNEL_ADDR}: 0x01080000
246 01:41:21.334476 - {KERNEL}: 830738/tftp-deploy-8yc8yatz/kernel/uImage
247 01:41:21.334866 - {LAVA_MAC}: None
248 01:41:21.335293 - {PRESEED_CONFIG}: None
249 01:41:21.335683 - {PRESEED_LOCAL}: None
250 01:41:21.336091 - {RAMDISK_ADDR}: 0x08000000
251 01:41:21.336478 - {RAMDISK}: 830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot
252 01:41:21.336868 - {ROOT_PART}: None
253 01:41:21.337254 - {ROOT}: None
254 01:41:21.337636 - {SERVER_IP}: 192.168.6.2
255 01:41:21.338022 - {TEE_ADDR}: 0x83000000
256 01:41:21.338407 - {TEE}: None
257 01:41:21.338790 Parsed boot commands:
258 01:41:21.339162 - setenv autoload no
259 01:41:21.339545 - setenv initrd_high 0xffffffff
260 01:41:21.339927 - setenv fdt_high 0xffffffff
261 01:41:21.340331 - dhcp
262 01:41:21.340714 - setenv serverip 192.168.6.2
263 01:41:21.341095 - tftpboot 0x01080000 830738/tftp-deploy-8yc8yatz/kernel/uImage
264 01:41:21.341479 - tftpboot 0x08000000 830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot
265 01:41:21.341864 - tftpboot 0x01070000 830738/tftp-deploy-8yc8yatz/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:41:21.342248 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:41:21.342638 - bootm 0x01080000 0x08000000 0x01070000
268 01:41:21.343124 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:41:21.344612 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:41:21.345049 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:41:21.359885 Setting prompt string to ['lava-test: # ']
273 01:41:21.361369 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:41:21.361962 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:41:21.362488 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:41:21.363005 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:41:21.364159 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:41:21.399872 >> OK - accepted request
279 01:41:21.401720 Returned 0 in 0 seconds
280 01:41:21.502848 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:41:21.504549 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:41:21.505108 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:41:21.505605 Setting prompt string to ['Hit any key to stop autoboot']
285 01:41:21.506059 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:41:21.507641 Trying 192.168.56.21...
287 01:41:21.508154 Connected to conserv1.
288 01:41:21.508618 Escape character is '^]'.
289 01:41:21.509059
290 01:41:21.509483 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:41:21.509903
292 01:41:32.756297 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:41:32.756752 bl2_stage_init 0x01
294 01:41:32.756991 bl2_stage_init 0x81
295 01:41:32.761772 hw id: 0x0000 - pwm id 0x01
296 01:41:32.762181 bl2_stage_init 0xc1
297 01:41:32.762408 bl2_stage_init 0x02
298 01:41:32.762632
299 01:41:32.767383 L0:00000000
300 01:41:32.767731 L1:20000703
301 01:41:32.767947 L2:00008067
302 01:41:32.768363 L3:14000000
303 01:41:32.770479 B2:00402000
304 01:41:32.771017 B1:e0f83180
305 01:41:32.771449
306 01:41:32.771879 TE: 58124
307 01:41:32.772349
308 01:41:32.781556 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:41:32.782140
310 01:41:32.782581 Board ID = 1
311 01:41:32.783009 Set A53 clk to 24M
312 01:41:32.783439 Set A73 clk to 24M
313 01:41:32.788192 Set clk81 to 24M
314 01:41:32.788799 A53 clk: 1200 MHz
315 01:41:32.789259 A73 clk: 1200 MHz
316 01:41:32.791741 CLK81: 166.6M
317 01:41:32.792119 smccc: 00012a92
318 01:41:32.796222 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:41:32.801714 board id: 1
320 01:41:32.806733 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:41:32.817479 fw parse done
322 01:41:32.823327 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:41:32.866174 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:41:32.876800 PIEI prepare done
325 01:41:32.877210 fastboot data load
326 01:41:32.877492 fastboot data verify
327 01:41:32.882406 verify result: 266
328 01:41:32.888059 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:41:32.888480 LPDDR4 probe
330 01:41:32.888759 ddr clk to 1584MHz
331 01:41:32.895970 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:41:32.933821
333 01:41:32.934258 dmc_version 0001
334 01:41:32.940399 Check phy result
335 01:41:32.946675 INFO : End of CA training
336 01:41:32.947125 INFO : End of initialization
337 01:41:32.952123 INFO : Training has run successfully!
338 01:41:32.952547 Check phy result
339 01:41:32.957676 INFO : End of initialization
340 01:41:32.958102 INFO : End of read enable training
341 01:41:32.962669 INFO : End of fine write leveling
342 01:41:32.968423 INFO : End of Write leveling coarse delay
343 01:41:32.968843 INFO : Training has run successfully!
344 01:41:32.969123 Check phy result
345 01:41:32.973914 INFO : End of initialization
346 01:41:32.974360 INFO : End of read dq deskew training
347 01:41:32.980090 INFO : End of MPR read delay center optimization
348 01:41:32.985408 INFO : End of write delay center optimization
349 01:41:32.990740 INFO : End of read delay center optimization
350 01:41:32.991173 INFO : End of max read latency training
351 01:41:32.997367 INFO : Training has run successfully!
352 01:41:32.997808 1D training succeed
353 01:41:33.006155 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:41:33.056456 Check phy result
355 01:41:33.056934 INFO : End of initialization
356 01:41:33.075055 INFO : End of 2D read delay Voltage center optimization
357 01:41:33.095504 INFO : End of 2D read delay Voltage center optimization
358 01:41:33.147337 INFO : End of 2D write delay Voltage center optimization
359 01:41:33.196578 INFO : End of 2D write delay Voltage center optimization
360 01:41:33.202072 INFO : Training has run successfully!
361 01:41:33.202492
362 01:41:33.202720 channel==0
363 01:41:33.207561 RxClkDly_Margin_A0==88 ps 9
364 01:41:33.208005 TxDqDly_Margin_A0==98 ps 10
365 01:41:33.213374 RxClkDly_Margin_A1==88 ps 9
366 01:41:33.213706 TxDqDly_Margin_A1==88 ps 9
367 01:41:33.213926 TrainedVREFDQ_A0==74
368 01:41:33.218781 TrainedVREFDQ_A1==74
369 01:41:33.219121 VrefDac_Margin_A0==25
370 01:41:33.219343 DeviceVref_Margin_A0==40
371 01:41:33.224390 VrefDac_Margin_A1==25
372 01:41:33.224724 DeviceVref_Margin_A1==40
373 01:41:33.224945
374 01:41:33.225163
375 01:41:33.225371 channel==1
376 01:41:33.229963 RxClkDly_Margin_A0==98 ps 10
377 01:41:33.230399 TxDqDly_Margin_A0==98 ps 10
378 01:41:33.235568 RxClkDly_Margin_A1==88 ps 9
379 01:41:33.236039 TxDqDly_Margin_A1==98 ps 10
380 01:41:33.241122 TrainedVREFDQ_A0==77
381 01:41:33.241433 TrainedVREFDQ_A1==77
382 01:41:33.241660 VrefDac_Margin_A0==22
383 01:41:33.246852 DeviceVref_Margin_A0==37
384 01:41:33.247296 VrefDac_Margin_A1==24
385 01:41:33.252374 DeviceVref_Margin_A1==37
386 01:41:33.252828
387 01:41:33.253096 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:41:33.253318
389 01:41:33.285961 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 01:41:33.286591 2D training succeed
391 01:41:33.291543 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:41:33.297102 auto size-- 65535DDR cs0 size: 2048MB
393 01:41:33.297451 DDR cs1 size: 2048MB
394 01:41:33.302680 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:41:33.303153 cs0 DataBus test pass
396 01:41:33.308416 cs1 DataBus test pass
397 01:41:33.308772 cs0 AddrBus test pass
398 01:41:33.309000 cs1 AddrBus test pass
399 01:41:33.309210
400 01:41:33.313870 100bdlr_step_size ps== 420
401 01:41:33.314328 result report
402 01:41:33.319494 boot times 0Enable ddr reg access
403 01:41:33.324829 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:41:33.338380 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:41:33.912229 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:41:33.912673 MVN_1=0x00000000
407 01:41:33.917530 MVN_2=0x00000000
408 01:41:33.923278 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:41:33.923763 OPS=0x10
410 01:41:33.924041 ring efuse init
411 01:41:33.924256 chipver efuse init
412 01:41:33.928861 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:41:33.934543 [0.018961 Inits done]
414 01:41:33.935108 secure task start!
415 01:41:33.935449 high task start!
416 01:41:33.939042 low task start!
417 01:41:33.939372 run into bl31
418 01:41:33.945914 NOTICE: BL31: v1.3(release):4fc40b1
419 01:41:33.953589 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:41:33.954074 NOTICE: BL31: G12A normal boot!
421 01:41:33.978877 NOTICE: BL31: BL33 decompress pass
422 01:41:33.984571 ERROR: Error initializing runtime service opteed_fast
423 01:41:35.217524
424 01:41:35.217959
425 01:41:35.225711 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:41:35.226119
427 01:41:35.226434 Model: Libre Computer AML-A311D-CC Alta
428 01:41:35.434185 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:41:35.457622 DRAM: 2 GiB (effective 3.8 GiB)
430 01:41:35.600798 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:41:35.607883 WDT: Not starting watchdog@f0d0
432 01:41:35.638742 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:41:35.651128 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:41:35.656179 ** Bad device specification mmc 0 **
435 01:41:35.666519 Card did not respond to voltage select! : -110
436 01:41:35.674155 ** Bad device specification mmc 0 **
437 01:41:35.674433 Couldn't find partition mmc 0
438 01:41:35.682504 Card did not respond to voltage select! : -110
439 01:41:35.688008 ** Bad device specification mmc 0 **
440 01:41:35.688282 Couldn't find partition mmc 0
441 01:41:35.693056 Error: could not access storage.
442 01:41:36.956517 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 01:41:36.956936 bl2_stage_init 0x01
444 01:41:36.957154 bl2_stage_init 0x81
445 01:41:36.961990 hw id: 0x0000 - pwm id 0x01
446 01:41:36.962352 bl2_stage_init 0xc1
447 01:41:36.962668 bl2_stage_init 0x02
448 01:41:36.962971
449 01:41:36.967565 L0:00000000
450 01:41:36.967913 L1:20000703
451 01:41:36.968178 L2:00008067
452 01:41:36.968385 L3:14000000
453 01:41:36.973187 B2:00402000
454 01:41:36.973547 B1:e0f83180
455 01:41:36.973869
456 01:41:36.974181 TE: 58124
457 01:41:36.974489
458 01:41:36.978815 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 01:41:36.979071
460 01:41:36.979280 Board ID = 1
461 01:41:36.984355 Set A53 clk to 24M
462 01:41:36.984710 Set A73 clk to 24M
463 01:41:36.985023 Set clk81 to 24M
464 01:41:36.989963 A53 clk: 1200 MHz
465 01:41:36.990316 A73 clk: 1200 MHz
466 01:41:36.990629 CLK81: 166.6M
467 01:41:36.990862 smccc: 00012a91
468 01:41:36.995546 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 01:41:37.001213 board id: 1
470 01:41:37.007048 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 01:41:37.017710 fw parse done
472 01:41:37.023677 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 01:41:37.066325 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 01:41:37.077277 PIEI prepare done
475 01:41:37.077606 fastboot data load
476 01:41:37.077825 fastboot data verify
477 01:41:37.082853 verify result: 266
478 01:41:37.088408 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 01:41:37.088760 LPDDR4 probe
480 01:41:37.089084 ddr clk to 1584MHz
481 01:41:37.096352 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 01:41:37.133657
483 01:41:37.133975 dmc_version 0001
484 01:41:37.140294 Check phy result
485 01:41:37.146170 INFO : End of CA training
486 01:41:37.146524 INFO : End of initialization
487 01:41:37.151898 INFO : Training has run successfully!
488 01:41:37.152183 Check phy result
489 01:41:37.157379 INFO : End of initialization
490 01:41:37.157634 INFO : End of read enable training
491 01:41:37.160720 INFO : End of fine write leveling
492 01:41:37.166318 INFO : End of Write leveling coarse delay
493 01:41:37.171910 INFO : Training has run successfully!
494 01:41:37.172184 Check phy result
495 01:41:37.172395 INFO : End of initialization
496 01:41:37.177509 INFO : End of read dq deskew training
497 01:41:37.183131 INFO : End of MPR read delay center optimization
498 01:41:37.183505 INFO : End of write delay center optimization
499 01:41:37.188730 INFO : End of read delay center optimization
500 01:41:37.194300 INFO : End of max read latency training
501 01:41:37.194646 INFO : Training has run successfully!
502 01:41:37.199927 1D training succeed
503 01:41:37.205806 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 01:41:37.253438 Check phy result
505 01:41:37.253750 INFO : End of initialization
506 01:41:37.275005 INFO : End of 2D read delay Voltage center optimization
507 01:41:37.295134 INFO : End of 2D read delay Voltage center optimization
508 01:41:37.347088 INFO : End of 2D write delay Voltage center optimization
509 01:41:37.396298 INFO : End of 2D write delay Voltage center optimization
510 01:41:37.401902 INFO : Training has run successfully!
511 01:41:37.402170
512 01:41:37.402381 channel==0
513 01:41:37.407389 RxClkDly_Margin_A0==88 ps 9
514 01:41:37.407744 TxDqDly_Margin_A0==98 ps 10
515 01:41:37.412980 RxClkDly_Margin_A1==88 ps 9
516 01:41:37.413329 TxDqDly_Margin_A1==98 ps 10
517 01:41:37.413650 TrainedVREFDQ_A0==74
518 01:41:37.418601 TrainedVREFDQ_A1==74
519 01:41:37.418862 VrefDac_Margin_A0==25
520 01:41:37.419069 DeviceVref_Margin_A0==40
521 01:41:37.424256 VrefDac_Margin_A1==25
522 01:41:37.424613 DeviceVref_Margin_A1==40
523 01:41:37.424923
524 01:41:37.425236
525 01:41:37.429896 channel==1
526 01:41:37.430236 RxClkDly_Margin_A0==98 ps 10
527 01:41:37.430466 TxDqDly_Margin_A0==88 ps 9
528 01:41:37.435392 RxClkDly_Margin_A1==98 ps 10
529 01:41:37.435643 TxDqDly_Margin_A1==88 ps 9
530 01:41:37.440982 TrainedVREFDQ_A0==77
531 01:41:37.441235 TrainedVREFDQ_A1==77
532 01:41:37.441441 VrefDac_Margin_A0==22
533 01:41:37.446594 DeviceVref_Margin_A0==37
534 01:41:37.446932 VrefDac_Margin_A1==22
535 01:41:37.452198 DeviceVref_Margin_A1==37
536 01:41:37.452569
537 01:41:37.452889 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 01:41:37.453202
539 01:41:37.485789 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
540 01:41:37.486106 2D training succeed
541 01:41:37.491398 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 01:41:37.496961 auto size-- 65535DDR cs0 size: 2048MB
543 01:41:37.497322 DDR cs1 size: 2048MB
544 01:41:37.502585 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 01:41:37.502844 cs0 DataBus test pass
546 01:41:37.508193 cs1 DataBus test pass
547 01:41:37.508468 cs0 AddrBus test pass
548 01:41:37.508680 cs1 AddrBus test pass
549 01:41:37.508884
550 01:41:37.513760 100bdlr_step_size ps== 420
551 01:41:37.514124 result report
552 01:41:37.519345 boot times 0Enable ddr reg access
553 01:41:37.524712 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 01:41:37.538231 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 01:41:38.110363 0.0;M3 CHK:0;cm4_sp_mode 0
556 01:41:38.112097 MVN_1=0x00000000
557 01:41:38.115826 MVN_2=0x00000000
558 01:41:38.121537 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 01:41:38.122030 OPS=0x10
560 01:41:38.122477 ring efuse init
561 01:41:38.122908 chipver efuse init
562 01:41:38.127145 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 01:41:38.132739 [0.018961 Inits done]
564 01:41:38.133211 secure task start!
565 01:41:38.133644 high task start!
566 01:41:38.137293 low task start!
567 01:41:38.137760 run into bl31
568 01:41:38.144046 NOTICE: BL31: v1.3(release):4fc40b1
569 01:41:38.151791 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 01:41:38.152298 NOTICE: BL31: G12A normal boot!
571 01:41:38.177200 NOTICE: BL31: BL33 decompress pass
572 01:41:38.183043 ERROR: Error initializing runtime service opteed_fast
573 01:41:39.416138
574 01:41:39.416570
575 01:41:39.424427 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 01:41:39.424772
577 01:41:39.425000 Model: Libre Computer AML-A311D-CC Alta
578 01:41:39.632889 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 01:41:39.656151 DRAM: 2 GiB (effective 3.8 GiB)
580 01:41:39.799200 Core: 408 devices, 31 uclasses, devicetree: separate
581 01:41:39.805117 WDT: Not starting watchdog@f0d0
582 01:41:39.837410 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 01:41:39.849855 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 01:41:39.854850 ** Bad device specification mmc 0 **
585 01:41:39.864944 Card did not respond to voltage select! : -110
586 01:41:39.872664 ** Bad device specification mmc 0 **
587 01:41:39.872991 Couldn't find partition mmc 0
588 01:41:39.880991 Card did not respond to voltage select! : -110
589 01:41:39.886520 ** Bad device specification mmc 0 **
590 01:41:39.886973 Couldn't find partition mmc 0
591 01:41:39.891585 Error: could not access storage.
592 01:41:40.235243 Net: eth0: ethernet@ff3f0000
593 01:41:40.235660 starting USB...
594 01:41:40.487077 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 01:41:40.487654 Starting the controller
596 01:41:40.494056 USB XHCI 1.10
597 01:41:42.205390 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 01:41:42.205811 bl2_stage_init 0x01
599 01:41:42.206038 bl2_stage_init 0x81
600 01:41:42.211114 hw id: 0x0000 - pwm id 0x01
601 01:41:42.211550 bl2_stage_init 0xc1
602 01:41:42.211900 bl2_stage_init 0x02
603 01:41:42.212270
604 01:41:42.216627 L0:00000000
605 01:41:42.217051 L1:20000703
606 01:41:42.217311 L2:00008067
607 01:41:42.217525 L3:14000000
608 01:41:42.219517 B2:00402000
609 01:41:42.219939 B1:e0f83180
610 01:41:42.220307
611 01:41:42.220661 TE: 58167
612 01:41:42.220999
613 01:41:42.230733 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 01:41:42.231047
615 01:41:42.231266 Board ID = 1
616 01:41:42.231472 Set A53 clk to 24M
617 01:41:42.231673 Set A73 clk to 24M
618 01:41:42.236274 Set clk81 to 24M
619 01:41:42.236695 A53 clk: 1200 MHz
620 01:41:42.237036 A73 clk: 1200 MHz
621 01:41:42.241880 CLK81: 166.6M
622 01:41:42.242300 smccc: 00012abd
623 01:41:42.247384 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 01:41:42.247803 board id: 1
625 01:41:42.256184 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 01:41:42.266849 fw parse done
627 01:41:42.272767 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 01:41:42.315182 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 01:41:42.326113 PIEI prepare done
630 01:41:42.326645 fastboot data load
631 01:41:42.327127 fastboot data verify
632 01:41:42.331693 verify result: 266
633 01:41:42.337280 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 01:41:42.337788 LPDDR4 probe
635 01:41:42.338252 ddr clk to 1584MHz
636 01:41:42.345259 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 01:41:42.382569
638 01:41:42.383068 dmc_version 0001
639 01:41:42.389205 Check phy result
640 01:41:42.395035 INFO : End of CA training
641 01:41:42.395526 INFO : End of initialization
642 01:41:42.400698 INFO : Training has run successfully!
643 01:41:42.401207 Check phy result
644 01:41:42.406283 INFO : End of initialization
645 01:41:42.406776 INFO : End of read enable training
646 01:41:42.409687 INFO : End of fine write leveling
647 01:41:42.415211 INFO : End of Write leveling coarse delay
648 01:41:42.420844 INFO : Training has run successfully!
649 01:41:42.421341 Check phy result
650 01:41:42.421800 INFO : End of initialization
651 01:41:42.426426 INFO : End of read dq deskew training
652 01:41:42.432027 INFO : End of MPR read delay center optimization
653 01:41:42.432530 INFO : End of write delay center optimization
654 01:41:42.437667 INFO : End of read delay center optimization
655 01:41:42.443219 INFO : End of max read latency training
656 01:41:42.443713 INFO : Training has run successfully!
657 01:41:42.448827 1D training succeed
658 01:41:42.454830 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 01:41:42.502305 Check phy result
660 01:41:42.502831 INFO : End of initialization
661 01:41:42.523903 INFO : End of 2D read delay Voltage center optimization
662 01:41:42.544082 INFO : End of 2D read delay Voltage center optimization
663 01:41:42.595934 INFO : End of 2D write delay Voltage center optimization
664 01:41:42.645221 INFO : End of 2D write delay Voltage center optimization
665 01:41:42.650864 INFO : Training has run successfully!
666 01:41:42.651369
667 01:41:42.651855 channel==0
668 01:41:42.656350 RxClkDly_Margin_A0==88 ps 9
669 01:41:42.656862 TxDqDly_Margin_A0==98 ps 10
670 01:41:42.659683 RxClkDly_Margin_A1==88 ps 9
671 01:41:42.660184 TxDqDly_Margin_A1==88 ps 9
672 01:41:42.665165 TrainedVREFDQ_A0==74
673 01:41:42.665685 TrainedVREFDQ_A1==74
674 01:41:42.666155 VrefDac_Margin_A0==25
675 01:41:42.670785 DeviceVref_Margin_A0==40
676 01:41:42.671285 VrefDac_Margin_A1==25
677 01:41:42.676392 DeviceVref_Margin_A1==40
678 01:41:42.676909
679 01:41:42.677375
680 01:41:42.677828 channel==1
681 01:41:42.678278 RxClkDly_Margin_A0==98 ps 10
682 01:41:42.679901 TxDqDly_Margin_A0==98 ps 10
683 01:41:42.685416 RxClkDly_Margin_A1==88 ps 9
684 01:41:42.685929 TxDqDly_Margin_A1==88 ps 9
685 01:41:42.686395 TrainedVREFDQ_A0==77
686 01:41:42.691019 TrainedVREFDQ_A1==77
687 01:41:42.691521 VrefDac_Margin_A0==22
688 01:41:42.696596 DeviceVref_Margin_A0==37
689 01:41:42.697104 VrefDac_Margin_A1==24
690 01:41:42.697563 DeviceVref_Margin_A1==37
691 01:41:42.698009
692 01:41:42.702247 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 01:41:42.702748
694 01:41:42.735741 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 01:41:42.736313 2D training succeed
696 01:41:42.741329 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 01:41:42.746986 auto size-- 65535DDR cs0 size: 2048MB
698 01:41:42.747483 DDR cs1 size: 2048MB
699 01:41:42.752539 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 01:41:42.753046 cs0 DataBus test pass
701 01:41:42.753512 cs1 DataBus test pass
702 01:41:42.758135 cs0 AddrBus test pass
703 01:41:42.758629 cs1 AddrBus test pass
704 01:41:42.759083
705 01:41:42.763725 100bdlr_step_size ps== 420
706 01:41:42.764287 result report
707 01:41:42.764742 boot times 0Enable ddr reg access
708 01:41:42.773435 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 01:41:42.786923 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 01:41:43.359052 0.0;M3 CHK:0;cm4_sp_mode 0
711 01:41:43.359489 MVN_1=0x00000000
712 01:41:43.364568 MVN_2=0x00000000
713 01:41:43.370234 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 01:41:43.370576 OPS=0x10
715 01:41:43.370794 ring efuse init
716 01:41:43.370999 chipver efuse init
717 01:41:43.375821 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 01:41:43.381385 [0.018961 Inits done]
719 01:41:43.381726 secure task start!
720 01:41:43.381938 high task start!
721 01:41:43.385952 low task start!
722 01:41:43.386272 run into bl31
723 01:41:43.392722 NOTICE: BL31: v1.3(release):4fc40b1
724 01:41:43.400473 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 01:41:43.400827 NOTICE: BL31: G12A normal boot!
726 01:41:43.425980 NOTICE: BL31: BL33 decompress pass
727 01:41:43.431624 ERROR: Error initializing runtime service opteed_fast
728 01:41:44.664638
729 01:41:44.665261
730 01:41:44.672987 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 01:41:44.673465
732 01:41:44.673890 Model: Libre Computer AML-A311D-CC Alta
733 01:41:44.881477 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 01:41:44.904757 DRAM: 2 GiB (effective 3.8 GiB)
735 01:41:45.047935 Core: 408 devices, 31 uclasses, devicetree: separate
736 01:41:45.053651 WDT: Not starting watchdog@f0d0
737 01:41:45.085937 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 01:41:45.098417 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 01:41:45.103454 ** Bad device specification mmc 0 **
740 01:41:45.113787 Card did not respond to voltage select! : -110
741 01:41:45.121403 ** Bad device specification mmc 0 **
742 01:41:45.121955 Couldn't find partition mmc 0
743 01:41:45.129761 Card did not respond to voltage select! : -110
744 01:41:45.135281 ** Bad device specification mmc 0 **
745 01:41:45.135833 Couldn't find partition mmc 0
746 01:41:45.140359 Error: could not access storage.
747 01:41:45.483824 Net: eth0: ethernet@ff3f0000
748 01:41:45.484481 starting USB...
749 01:41:45.735655 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 01:41:45.736080 Starting the controller
751 01:41:45.742517 USB XHCI 1.10
752 01:41:47.905589 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
753 01:41:47.906053 bl2_stage_init 0x81
754 01:41:47.910987 hw id: 0x0000 - pwm id 0x01
755 01:41:47.911441 bl2_stage_init 0xc1
756 01:41:47.911815 bl2_stage_init 0x02
757 01:41:47.912227
758 01:41:47.916541 L0:00000000
759 01:41:47.916857 L1:20000703
760 01:41:47.917086 L2:00008067
761 01:41:47.917299 L3:14000000
762 01:41:47.917509 B2:00402000
763 01:41:47.919535 B1:e0f83180
764 01:41:47.919948
765 01:41:47.920341 TE: 58150
766 01:41:47.920691
767 01:41:47.930612 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 01:41:47.931057
769 01:41:47.931420 Board ID = 1
770 01:41:47.931768 Set A53 clk to 24M
771 01:41:47.932135 Set A73 clk to 24M
772 01:41:47.936186 Set clk81 to 24M
773 01:41:47.936495 A53 clk: 1200 MHz
774 01:41:47.936721 A73 clk: 1200 MHz
775 01:41:47.939742 CLK81: 166.6M
776 01:41:47.940171 smccc: 00012aab
777 01:41:47.945270 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 01:41:47.950921 board id: 1
779 01:41:47.955107 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 01:41:47.966709 fw parse done
781 01:41:47.972682 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 01:41:48.015182 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 01:41:48.026068 PIEI prepare done
784 01:41:48.026407 fastboot data load
785 01:41:48.026645 fastboot data verify
786 01:41:48.031658 verify result: 266
787 01:41:48.037258 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 01:41:48.037688 LPDDR4 probe
789 01:41:48.038048 ddr clk to 1584MHz
790 01:41:48.045258 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 01:41:48.082505
792 01:41:48.082870 dmc_version 0001
793 01:41:48.089352 Check phy result
794 01:41:48.095077 INFO : End of CA training
795 01:41:48.095522 INFO : End of initialization
796 01:41:48.100653 INFO : Training has run successfully!
797 01:41:48.100978 Check phy result
798 01:41:48.106266 INFO : End of initialization
799 01:41:48.106709 INFO : End of read enable training
800 01:41:48.109555 INFO : End of fine write leveling
801 01:41:48.115098 INFO : End of Write leveling coarse delay
802 01:41:48.120695 INFO : Training has run successfully!
803 01:41:48.121021 Check phy result
804 01:41:48.121255 INFO : End of initialization
805 01:41:48.126287 INFO : End of read dq deskew training
806 01:41:48.131912 INFO : End of MPR read delay center optimization
807 01:41:48.132381 INFO : End of write delay center optimization
808 01:41:48.137530 INFO : End of read delay center optimization
809 01:41:48.143134 INFO : End of max read latency training
810 01:41:48.143452 INFO : Training has run successfully!
811 01:41:48.148709 1D training succeed
812 01:41:48.154701 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 01:41:48.202176 Check phy result
814 01:41:48.202550 INFO : End of initialization
815 01:41:48.224651 INFO : End of 2D read delay Voltage center optimization
816 01:41:48.244800 INFO : End of 2D read delay Voltage center optimization
817 01:41:48.296694 INFO : End of 2D write delay Voltage center optimization
818 01:41:48.345902 INFO : End of 2D write delay Voltage center optimization
819 01:41:48.351450 INFO : Training has run successfully!
820 01:41:48.351770
821 01:41:48.352025 channel==0
822 01:41:48.357122 RxClkDly_Margin_A0==88 ps 9
823 01:41:48.357428 TxDqDly_Margin_A0==98 ps 10
824 01:41:48.360464 RxClkDly_Margin_A1==88 ps 9
825 01:41:48.364109 TxDqDly_Margin_A1==98 ps 10
826 01:41:48.365914 TrainedVREFDQ_A0==74
827 01:41:48.366420 TrainedVREFDQ_A1==74
828 01:41:48.371637 VrefDac_Margin_A0==25
829 01:41:48.372152 DeviceVref_Margin_A0==40
830 01:41:48.372593 VrefDac_Margin_A1==24
831 01:41:48.377219 DeviceVref_Margin_A1==40
832 01:41:48.377696
833 01:41:48.378133
834 01:41:48.378566 channel==1
835 01:41:48.378997 RxClkDly_Margin_A0==98 ps 10
836 01:41:48.382782 TxDqDly_Margin_A0==98 ps 10
837 01:41:48.383261 RxClkDly_Margin_A1==98 ps 10
838 01:41:48.388376 TxDqDly_Margin_A1==88 ps 9
839 01:41:48.388856 TrainedVREFDQ_A0==77
840 01:41:48.389297 TrainedVREFDQ_A1==77
841 01:41:48.394004 VrefDac_Margin_A0==22
842 01:41:48.394472 DeviceVref_Margin_A0==37
843 01:41:48.399685 VrefDac_Margin_A1==22
844 01:41:48.400177 DeviceVref_Margin_A1==37
845 01:41:48.400608
846 01:41:48.405203 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 01:41:48.405673
848 01:41:48.433871 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
849 01:41:48.439083 2D training succeed
850 01:41:48.444255 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 01:41:48.444736 auto size-- 65535DDR cs0 size: 2048MB
852 01:41:48.449908 DDR cs1 size: 2048MB
853 01:41:48.450503 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 01:41:48.455535 cs0 DataBus test pass
855 01:41:48.456069 cs1 DataBus test pass
856 01:41:48.456519 cs0 AddrBus test pass
857 01:41:48.461076 cs1 AddrBus test pass
858 01:41:48.461561
859 01:41:48.462003 100bdlr_step_size ps== 420
860 01:41:48.462445 result report
861 01:41:48.466665 boot times 0Enable ddr reg access
862 01:41:48.474492 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 01:41:48.487933 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 01:41:49.060119 0.0;M3 CHK:0;cm4_sp_mode 0
865 01:41:49.060783 MVN_1=0x00000000
866 01:41:49.065514 MVN_2=0x00000000
867 01:41:49.071184 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 01:41:49.071725 OPS=0x10
869 01:41:49.072242 ring efuse init
870 01:41:49.072705 chipver efuse init
871 01:41:49.076805 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 01:41:49.082393 [0.018961 Inits done]
873 01:41:49.082902 secure task start!
874 01:41:49.083365 high task start!
875 01:41:49.086989 low task start!
876 01:41:49.087506 run into bl31
877 01:41:49.093674 NOTICE: BL31: v1.3(release):4fc40b1
878 01:41:49.101436 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 01:41:49.101957 NOTICE: BL31: G12A normal boot!
880 01:41:49.126874 NOTICE: BL31: BL33 decompress pass
881 01:41:49.132589 ERROR: Error initializing runtime service opteed_fast
882 01:41:50.365544
883 01:41:50.365981
884 01:41:50.373888 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 01:41:50.374335
886 01:41:50.374696 Model: Libre Computer AML-A311D-CC Alta
887 01:41:50.582210 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 01:41:50.605600 DRAM: 2 GiB (effective 3.8 GiB)
889 01:41:50.748622 Core: 408 devices, 31 uclasses, devicetree: separate
890 01:41:50.754432 WDT: Not starting watchdog@f0d0
891 01:41:50.786751 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 01:41:50.799170 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 01:41:50.804144 ** Bad device specification mmc 0 **
894 01:41:50.814467 Card did not respond to voltage select! : -110
895 01:41:50.822106 ** Bad device specification mmc 0 **
896 01:41:50.822417 Couldn't find partition mmc 0
897 01:41:50.830486 Card did not respond to voltage select! : -110
898 01:41:50.835967 ** Bad device specification mmc 0 **
899 01:41:50.836421 Couldn't find partition mmc 0
900 01:41:50.841056 Error: could not access storage.
901 01:41:51.184615 Net: eth0: ethernet@ff3f0000
902 01:41:51.185038 starting USB...
903 01:41:51.436422 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 01:41:51.436961 Starting the controller
905 01:41:51.443315 USB XHCI 1.10
906 01:41:52.997613 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 01:41:53.005791 scanning usb for storage devices... 0 Storage Device(s) found
909 01:41:53.057468 Hit any key to stop autoboot: 1
910 01:41:53.058298 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 01:41:53.058951 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 01:41:53.059483 Setting prompt string to ['=>']
913 01:41:53.060059 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 01:41:53.073317 0
915 01:41:53.074240 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 01:41:53.074781 Sending with 10 millisecond of delay
918 01:41:54.209274 => setenv autoload no
919 01:41:54.220043 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 01:41:54.222609 setenv autoload no
921 01:41:54.223097 Sending with 10 millisecond of delay
923 01:41:56.019563 => setenv initrd_high 0xffffffff
924 01:41:56.030602 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 01:41:56.031703 setenv initrd_high 0xffffffff
926 01:41:56.032544 Sending with 10 millisecond of delay
928 01:41:57.649028 => setenv fdt_high 0xffffffff
929 01:41:57.659783 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
930 01:41:57.660594 setenv fdt_high 0xffffffff
931 01:41:57.661302 Sending with 10 millisecond of delay
933 01:41:57.953040 => dhcp
934 01:41:57.963931 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 01:41:57.964768 dhcp
936 01:41:57.965206 Speed: 1000, full duplex
937 01:41:57.965612 BOOTP broadcast 1
938 01:41:58.212143 BOOTP broadcast 2
939 01:41:58.282723 DHCP client bound to address 192.168.6.33 (318 ms)
940 01:41:58.283444 Sending with 10 millisecond of delay
942 01:41:59.959892 => setenv serverip 192.168.6.2
943 01:41:59.970538 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 01:41:59.972256 setenv serverip 192.168.6.2
945 01:41:59.973569 Sending with 10 millisecond of delay
947 01:42:03.696770 => tftpboot 0x01080000 830738/tftp-deploy-8yc8yatz/kernel/uImage
948 01:42:03.707330 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 01:42:03.707834 tftpboot 0x01080000 830738/tftp-deploy-8yc8yatz/kernel/uImage
950 01:42:03.708134 Speed: 1000, full duplex
951 01:42:03.708371 Using ethernet@ff3f0000 device
952 01:42:03.710406 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 01:42:03.716045 Filename '830738/tftp-deploy-8yc8yatz/kernel/uImage'.
954 01:42:03.719564 Load address: 0x1080000
955 01:42:07.674337 Loading: *################################################## 43.6 MiB
956 01:42:07.675087 11 MiB/s
957 01:42:07.675601 done
958 01:42:07.678459 Bytes transferred = 45713984 (2b98a40 hex)
959 01:42:07.679356 Sending with 10 millisecond of delay
961 01:42:12.366885 => tftpboot 0x08000000 830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot
962 01:42:12.377500 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
963 01:42:12.378653 tftpboot 0x08000000 830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot
964 01:42:12.378881 Speed: 1000, full duplex
965 01:42:12.379084 Using ethernet@ff3f0000 device
966 01:42:12.380152 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
967 01:42:12.391842 Filename '830738/tftp-deploy-8yc8yatz/ramdisk/ramdisk.cpio.gz.uboot'.
968 01:42:12.392416 Load address: 0x8000000
969 01:42:14.386932 Loading: *################################################# UDP wrong checksum 00000005 000001ad
970 01:42:19.388336 T UDP wrong checksum 00000005 000001ad
971 01:42:29.390202 T T UDP wrong checksum 00000005 000001ad
972 01:42:49.393155 T T T UDP wrong checksum 00000005 000001ad
973 01:42:59.606895 T T T UDP wrong checksum 000000ff 0000011d
974 01:42:59.636328 UDP wrong checksum 000000ff 0000990f
975 01:43:03.766070 UDP wrong checksum 000000ff 0000f29e
976 01:43:03.797370 UDP wrong checksum 000000ff 00008c91
977 01:43:09.398451 T
978 01:43:09.398914 Retry count exceeded; starting again
980 01:43:09.400080 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
983 01:43:09.401429 end: 2.4 uboot-commands (duration 00:01:48) [common]
985 01:43:09.402200 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 01:43:09.402803 end: 2 uboot-action (duration 00:01:48) [common]
989 01:43:09.403878 Cleaning after the job
990 01:43:09.404244 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/ramdisk
991 01:43:09.405136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/kernel
992 01:43:09.432180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/dtb
993 01:43:09.433065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830738/tftp-deploy-8yc8yatz/modules
994 01:43:09.452660 start: 4.1 power-off (timeout 00:00:30) [common]
995 01:43:09.453353 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 01:43:09.486928 >> OK - accepted request
997 01:43:09.489361 Returned 0 in 0 seconds
998 01:43:09.590338 end: 4.1 power-off (duration 00:00:00) [common]
1000 01:43:09.591420 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 01:43:09.592162 Listened to connection for namespace 'common' for up to 1s
1002 01:43:10.593526 Finalising connection for namespace 'common'
1003 01:43:10.594024 Disconnecting from shell: Finalise
1004 01:43:10.594327 =>
1005 01:43:10.695035 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 01:43:10.695532 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/830738
1007 01:43:10.981861 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/830738
1008 01:43:10.982496 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.