Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 02:46:45.958176 lava-dispatcher, installed at version: 2024.01
2 02:46:45.959045 start: 0 validate
3 02:46:45.959528 Start time: 2024-10-10 02:46:45.959496+00:00 (UTC)
4 02:46:45.960107 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:46:45.960679 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:46:46.006124 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:46:46.006695 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-74-gd3d1556696c1a%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:46:46.035871 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:46:46.036542 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-74-gd3d1556696c1a%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:46:46.068299 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:46:46.068816 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:46:46.099506 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:46:46.100082 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-74-gd3d1556696c1a%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:46:46.134448 validate duration: 0.18
16 02:46:46.135337 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:46:46.135658 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:46:46.135997 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:46:46.136609 Not decompressing ramdisk as can be used compressed.
20 02:46:46.137091 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:46:46.137366 saving as /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/ramdisk/initrd.cpio.gz
22 02:46:46.137632 total size: 5628169 (5 MB)
23 02:46:46.178377 progress 0 % (0 MB)
24 02:46:46.183119 progress 5 % (0 MB)
25 02:46:46.189724 progress 10 % (0 MB)
26 02:46:46.193630 progress 15 % (0 MB)
27 02:46:46.197892 progress 20 % (1 MB)
28 02:46:46.201702 progress 25 % (1 MB)
29 02:46:46.206042 progress 30 % (1 MB)
30 02:46:46.210161 progress 35 % (1 MB)
31 02:46:46.213806 progress 40 % (2 MB)
32 02:46:46.217908 progress 45 % (2 MB)
33 02:46:46.221625 progress 50 % (2 MB)
34 02:46:46.225680 progress 55 % (2 MB)
35 02:46:46.229774 progress 60 % (3 MB)
36 02:46:46.233431 progress 65 % (3 MB)
37 02:46:46.237568 progress 70 % (3 MB)
38 02:46:46.241287 progress 75 % (4 MB)
39 02:46:46.245336 progress 80 % (4 MB)
40 02:46:46.249072 progress 85 % (4 MB)
41 02:46:46.253087 progress 90 % (4 MB)
42 02:46:46.257049 progress 95 % (5 MB)
43 02:46:46.260407 progress 100 % (5 MB)
44 02:46:46.261069 5 MB downloaded in 0.12 s (43.49 MB/s)
45 02:46:46.261610 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:46:46.262505 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:46:46.262806 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:46:46.263087 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:46:46.263640 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/kernel/Image
51 02:46:46.263926 saving as /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/kernel/Image
52 02:46:46.264188 total size: 45713920 (43 MB)
53 02:46:46.264406 No compression specified
54 02:46:46.299428 progress 0 % (0 MB)
55 02:46:46.329790 progress 5 % (2 MB)
56 02:46:46.360769 progress 10 % (4 MB)
57 02:46:46.391205 progress 15 % (6 MB)
58 02:46:46.421265 progress 20 % (8 MB)
59 02:46:46.451392 progress 25 % (10 MB)
60 02:46:46.483335 progress 30 % (13 MB)
61 02:46:46.512852 progress 35 % (15 MB)
62 02:46:46.542068 progress 40 % (17 MB)
63 02:46:46.570945 progress 45 % (19 MB)
64 02:46:46.600586 progress 50 % (21 MB)
65 02:46:46.630560 progress 55 % (24 MB)
66 02:46:46.660349 progress 60 % (26 MB)
67 02:46:46.689817 progress 65 % (28 MB)
68 02:46:46.720727 progress 70 % (30 MB)
69 02:46:46.750286 progress 75 % (32 MB)
70 02:46:46.779927 progress 80 % (34 MB)
71 02:46:46.808913 progress 85 % (37 MB)
72 02:46:46.838413 progress 90 % (39 MB)
73 02:46:46.867846 progress 95 % (41 MB)
74 02:46:46.897014 progress 100 % (43 MB)
75 02:46:46.897546 43 MB downloaded in 0.63 s (68.83 MB/s)
76 02:46:46.898011 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:46:46.898815 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:46:46.899084 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:46:46.899346 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:46:46.899827 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:46:46.900151 saving as /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:46:46.900359 total size: 54703 (0 MB)
84 02:46:46.900566 No compression specified
85 02:46:46.937322 progress 59 % (0 MB)
86 02:46:46.938175 progress 100 % (0 MB)
87 02:46:46.939054 0 MB downloaded in 0.04 s (1.35 MB/s)
88 02:46:46.939560 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:46:46.940406 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:46:46.940671 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:46:46.940931 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:46:46.941404 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:46:46.941637 saving as /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/nfsrootfs/full.rootfs.tar
95 02:46:46.941838 total size: 120894716 (115 MB)
96 02:46:46.942044 Using unxz to decompress xz
97 02:46:46.975525 progress 0 % (0 MB)
98 02:46:47.784822 progress 5 % (5 MB)
99 02:46:48.639521 progress 10 % (11 MB)
100 02:46:49.439937 progress 15 % (17 MB)
101 02:46:50.181648 progress 20 % (23 MB)
102 02:46:50.786304 progress 25 % (28 MB)
103 02:46:51.723609 progress 30 % (34 MB)
104 02:46:52.670224 progress 35 % (40 MB)
105 02:46:53.067285 progress 40 % (46 MB)
106 02:46:53.444261 progress 45 % (51 MB)
107 02:46:54.190509 progress 50 % (57 MB)
108 02:46:55.086580 progress 55 % (63 MB)
109 02:46:55.894315 progress 60 % (69 MB)
110 02:46:56.662063 progress 65 % (74 MB)
111 02:46:57.448433 progress 70 % (80 MB)
112 02:46:58.281608 progress 75 % (86 MB)
113 02:46:59.079867 progress 80 % (92 MB)
114 02:46:59.850567 progress 85 % (98 MB)
115 02:47:00.715658 progress 90 % (103 MB)
116 02:47:01.505885 progress 95 % (109 MB)
117 02:47:02.361822 progress 100 % (115 MB)
118 02:47:02.375466 115 MB downloaded in 15.43 s (7.47 MB/s)
119 02:47:02.376310 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:47:02.378129 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:47:02.378707 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:47:02.379274 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:47:02.380306 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/modules.tar.xz
125 02:47:02.380840 saving as /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/modules/modules.tar
126 02:47:02.381299 total size: 11595820 (11 MB)
127 02:47:02.381760 Using unxz to decompress xz
128 02:47:02.420801 progress 0 % (0 MB)
129 02:47:02.497247 progress 5 % (0 MB)
130 02:47:02.580337 progress 10 % (1 MB)
131 02:47:02.662654 progress 15 % (1 MB)
132 02:47:02.738496 progress 20 % (2 MB)
133 02:47:02.814450 progress 25 % (2 MB)
134 02:47:02.893107 progress 30 % (3 MB)
135 02:47:02.965620 progress 35 % (3 MB)
136 02:47:03.044680 progress 40 % (4 MB)
137 02:47:03.129813 progress 45 % (5 MB)
138 02:47:03.206196 progress 50 % (5 MB)
139 02:47:03.288757 progress 55 % (6 MB)
140 02:47:03.369487 progress 60 % (6 MB)
141 02:47:03.453549 progress 65 % (7 MB)
142 02:47:03.529227 progress 70 % (7 MB)
143 02:47:03.611097 progress 75 % (8 MB)
144 02:47:03.695388 progress 80 % (8 MB)
145 02:47:03.771715 progress 85 % (9 MB)
146 02:47:03.849319 progress 90 % (9 MB)
147 02:47:03.950422 progress 95 % (10 MB)
148 02:47:04.049993 progress 100 % (11 MB)
149 02:47:04.065388 11 MB downloaded in 1.68 s (6.57 MB/s)
150 02:47:04.066072 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:47:04.066908 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:47:04.067175 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 02:47:04.067440 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 02:47:21.602340 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3
156 02:47:21.602951 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 02:47:21.603276 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 02:47:21.604051 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7
159 02:47:21.604556 makedir: /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin
160 02:47:21.604962 makedir: /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/tests
161 02:47:21.605354 makedir: /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/results
162 02:47:21.605727 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-add-keys
163 02:47:21.606306 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-add-sources
164 02:47:21.606922 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-background-process-start
165 02:47:21.607456 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-background-process-stop
166 02:47:21.608027 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-common-functions
167 02:47:21.608559 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-echo-ipv4
168 02:47:21.609075 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-install-packages
169 02:47:21.609588 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-installed-packages
170 02:47:21.610090 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-os-build
171 02:47:21.610635 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-probe-channel
172 02:47:21.611145 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-probe-ip
173 02:47:21.611626 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-target-ip
174 02:47:21.612129 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-target-mac
175 02:47:21.612644 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-target-storage
176 02:47:21.613130 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-case
177 02:47:21.613602 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-event
178 02:47:21.614063 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-feedback
179 02:47:21.614520 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-raise
180 02:47:21.614976 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-reference
181 02:47:21.615464 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-runner
182 02:47:21.616004 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-set
183 02:47:21.616517 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-test-shell
184 02:47:21.617007 Updating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-add-keys (debian)
185 02:47:21.617565 Updating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-add-sources (debian)
186 02:47:21.618108 Updating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-install-packages (debian)
187 02:47:21.618628 Updating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-installed-packages (debian)
188 02:47:21.619113 Updating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/bin/lava-os-build (debian)
189 02:47:21.619547 Creating /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/environment
190 02:47:21.619954 LAVA metadata
191 02:47:21.620258 - LAVA_JOB_ID=830727
192 02:47:21.620476 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:47:21.620862 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 02:47:21.621886 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:47:21.622225 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 02:47:21.622432 skipped lava-vland-overlay
197 02:47:21.622672 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:47:21.622925 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 02:47:21.623145 skipped lava-multinode-overlay
200 02:47:21.623387 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:47:21.623636 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 02:47:21.623887 Loading test definitions
203 02:47:21.624215 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 02:47:21.624440 Using /lava-830727 at stage 0
205 02:47:21.625618 uuid=830727_1.6.2.4.1 testdef=None
206 02:47:21.625946 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:47:21.626213 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 02:47:21.627806 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:47:21.628646 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 02:47:21.630788 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:47:21.631639 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 02:47:21.633610 runner path: /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/0/tests/0_timesync-off test_uuid 830727_1.6.2.4.1
215 02:47:21.634191 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:47:21.635017 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 02:47:21.635245 Using /lava-830727 at stage 0
219 02:47:21.635622 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:47:21.635924 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/0/tests/1_kselftest-alsa'
221 02:47:25.126383 Running '/usr/bin/git checkout kernelci.org
222 02:47:25.294127 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 02:47:25.295576 uuid=830727_1.6.2.4.5 testdef=None
224 02:47:25.295919 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:47:25.296737 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 02:47:25.299563 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:47:25.300402 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 02:47:25.304107 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:47:25.304966 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 02:47:25.308566 runner path: /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/0/tests/1_kselftest-alsa test_uuid 830727_1.6.2.4.5
234 02:47:25.308853 BOARD='meson-g12b-a311d-libretech-cc'
235 02:47:25.309058 BRANCH='mainline'
236 02:47:25.309253 SKIPFILE='/dev/null'
237 02:47:25.309446 SKIP_INSTALL='True'
238 02:47:25.309640 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:47:25.309837 TST_CASENAME=''
240 02:47:25.310029 TST_CMDFILES='alsa'
241 02:47:25.310586 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:47:25.311368 Creating lava-test-runner.conf files
244 02:47:25.311570 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/830727/lava-overlay-d9kf07p7/lava-830727/0 for stage 0
245 02:47:25.311914 - 0_timesync-off
246 02:47:25.312178 - 1_kselftest-alsa
247 02:47:25.312515 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:47:25.312791 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 02:47:48.631366 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:47:48.631787 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 02:47:48.632073 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:47:48.632417 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:47:48.632682 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 02:47:49.296458 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:47:49.296912 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 02:47:49.297160 extracting modules file /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3
257 02:47:50.658940 extracting modules file /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/830727/extract-overlay-ramdisk-xdslcjuo/ramdisk
258 02:47:52.158893 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:47:52.159337 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 02:47:52.159615 [common] Applying overlay to NFS
261 02:47:52.159829 [common] Applying overlay /var/lib/lava/dispatcher/tmp/830727/compress-overlay-1mppivt1/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3
262 02:47:54.898127 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:47:54.898572 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 02:47:54.898847 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 02:47:54.899077 Converting downloaded kernel to a uImage
266 02:47:54.899384 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/kernel/Image /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/kernel/uImage
267 02:47:55.370145 output: Image Name:
268 02:47:55.370554 output: Created: Thu Oct 10 02:47:54 2024
269 02:47:55.370762 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:47:55.370967 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 02:47:55.371166 output: Load Address: 01080000
272 02:47:55.371370 output: Entry Point: 01080000
273 02:47:55.371567 output:
274 02:47:55.371894 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:47:55.372223 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:47:55.372496 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 02:47:55.372752 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:47:55.373007 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 02:47:55.373258 Building ramdisk /var/lib/lava/dispatcher/tmp/830727/extract-overlay-ramdisk-xdslcjuo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/830727/extract-overlay-ramdisk-xdslcjuo/ramdisk
280 02:47:57.591776 >> 166774 blocks
281 02:48:05.621619 Adding RAMdisk u-boot header.
282 02:48:05.622274 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/830727/extract-overlay-ramdisk-xdslcjuo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/830727/extract-overlay-ramdisk-xdslcjuo/ramdisk.cpio.gz.uboot
283 02:48:05.860123 output: Image Name:
284 02:48:05.860732 output: Created: Thu Oct 10 02:48:05 2024
285 02:48:05.861140 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:48:05.861539 output: Data Size: 23425844 Bytes = 22876.80 KiB = 22.34 MiB
287 02:48:05.861933 output: Load Address: 00000000
288 02:48:05.862325 output: Entry Point: 00000000
289 02:48:05.862717 output:
290 02:48:05.863806 rename /var/lib/lava/dispatcher/tmp/830727/extract-overlay-ramdisk-xdslcjuo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot
291 02:48:05.864540 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:48:05.865077 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 02:48:05.865595 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 02:48:05.866042 No LXC device requested
295 02:48:05.866536 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:48:05.867036 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 02:48:05.867524 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:48:05.867930 Checking files for TFTP limit of 4294967296 bytes.
299 02:48:05.870593 end: 1 tftp-deploy (duration 00:01:20) [common]
300 02:48:05.871154 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:48:05.871664 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:48:05.872188 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:48:05.872686 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:48:05.873201 Using kernel file from prepare-kernel: 830727/tftp-deploy-2tyca09k/kernel/uImage
305 02:48:05.873815 substitutions:
306 02:48:05.874216 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:48:05.874613 - {DTB_ADDR}: 0x01070000
308 02:48:05.875010 - {DTB}: 830727/tftp-deploy-2tyca09k/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:48:05.875407 - {INITRD}: 830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot
310 02:48:05.875800 - {KERNEL_ADDR}: 0x01080000
311 02:48:05.876225 - {KERNEL}: 830727/tftp-deploy-2tyca09k/kernel/uImage
312 02:48:05.876633 - {LAVA_MAC}: None
313 02:48:05.877065 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3
314 02:48:05.877459 - {NFS_SERVER_IP}: 192.168.6.2
315 02:48:05.877845 - {PRESEED_CONFIG}: None
316 02:48:05.878231 - {PRESEED_LOCAL}: None
317 02:48:05.878617 - {RAMDISK_ADDR}: 0x08000000
318 02:48:05.878997 - {RAMDISK}: 830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot
319 02:48:05.879381 - {ROOT_PART}: None
320 02:48:05.879761 - {ROOT}: None
321 02:48:05.880172 - {SERVER_IP}: 192.168.6.2
322 02:48:05.880555 - {TEE_ADDR}: 0x83000000
323 02:48:05.880935 - {TEE}: None
324 02:48:05.881318 Parsed boot commands:
325 02:48:05.881687 - setenv autoload no
326 02:48:05.882064 - setenv initrd_high 0xffffffff
327 02:48:05.882442 - setenv fdt_high 0xffffffff
328 02:48:05.882818 - dhcp
329 02:48:05.883194 - setenv serverip 192.168.6.2
330 02:48:05.883576 - tftpboot 0x01080000 830727/tftp-deploy-2tyca09k/kernel/uImage
331 02:48:05.883957 - tftpboot 0x08000000 830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot
332 02:48:05.884363 - tftpboot 0x01070000 830727/tftp-deploy-2tyca09k/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:48:05.884747 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:48:05.885140 - bootm 0x01080000 0x08000000 0x01070000
335 02:48:05.885624 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:48:05.887085 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:48:05.887499 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:48:05.902587 Setting prompt string to ['lava-test: # ']
340 02:48:05.904105 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:48:05.904721 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:48:05.905289 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:48:05.905805 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:48:05.906936 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:48:05.942315 >> OK - accepted request
346 02:48:05.944513 Returned 0 in 0 seconds
347 02:48:06.045616 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:48:06.047199 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:48:06.047743 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:48:06.048288 Setting prompt string to ['Hit any key to stop autoboot']
352 02:48:06.048727 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:48:06.050241 Trying 192.168.56.21...
354 02:48:06.050704 Connected to conserv1.
355 02:48:06.051109 Escape character is '^]'.
356 02:48:06.051513
357 02:48:06.051923 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 02:48:06.052372
359 02:48:17.239018 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 02:48:17.239612 bl2_stage_init 0x81
361 02:48:17.244597 hw id: 0x0000 - pwm id 0x01
362 02:48:17.245091 bl2_stage_init 0xc1
363 02:48:17.245502 bl2_stage_init 0x02
364 02:48:17.245903
365 02:48:17.250132 L0:00000000
366 02:48:17.250584 L1:20000703
367 02:48:17.250996 L2:00008067
368 02:48:17.251396 L3:14000000
369 02:48:17.251801 B2:00402000
370 02:48:17.253459 B1:e0f83180
371 02:48:17.253898
372 02:48:17.254308 TE: 58150
373 02:48:17.254695
374 02:48:17.264143 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 02:48:17.264578
376 02:48:17.264973 Board ID = 1
377 02:48:17.265358 Set A53 clk to 24M
378 02:48:17.265738 Set A73 clk to 24M
379 02:48:17.269686 Set clk81 to 24M
380 02:48:17.270101 A53 clk: 1200 MHz
381 02:48:17.270484 A73 clk: 1200 MHz
382 02:48:17.273115 CLK81: 166.6M
383 02:48:17.273536 smccc: 00012aac
384 02:48:17.278746 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 02:48:17.284237 board id: 1
386 02:48:17.289453 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 02:48:17.300077 fw parse done
388 02:48:17.306274 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 02:48:17.348653 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 02:48:17.359614 PIEI prepare done
391 02:48:17.360056 fastboot data load
392 02:48:17.360446 fastboot data verify
393 02:48:17.365176 verify result: 266
394 02:48:17.370783 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 02:48:17.371199 LPDDR4 probe
396 02:48:17.371581 ddr clk to 1584MHz
397 02:48:17.378771 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 02:48:17.416125
399 02:48:17.416606 dmc_version 0001
400 02:48:17.422693 Check phy result
401 02:48:17.428550 INFO : End of CA training
402 02:48:17.428976 INFO : End of initialization
403 02:48:17.434433 INFO : Training has run successfully!
404 02:48:17.434842 Check phy result
405 02:48:17.439743 INFO : End of initialization
406 02:48:17.440193 INFO : End of read enable training
407 02:48:17.443052 INFO : End of fine write leveling
408 02:48:17.448618 INFO : End of Write leveling coarse delay
409 02:48:17.454218 INFO : Training has run successfully!
410 02:48:17.454633 Check phy result
411 02:48:17.455019 INFO : End of initialization
412 02:48:17.459814 INFO : End of read dq deskew training
413 02:48:17.463249 INFO : End of MPR read delay center optimization
414 02:48:17.468836 INFO : End of write delay center optimization
415 02:48:17.474586 INFO : End of read delay center optimization
416 02:48:17.475017 INFO : End of max read latency training
417 02:48:17.480074 INFO : Training has run successfully!
418 02:48:17.480498 1D training succeed
419 02:48:17.488194 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 02:48:17.535841 Check phy result
421 02:48:17.536309 INFO : End of initialization
422 02:48:17.557522 INFO : End of 2D read delay Voltage center optimization
423 02:48:17.577760 INFO : End of 2D read delay Voltage center optimization
424 02:48:17.629829 INFO : End of 2D write delay Voltage center optimization
425 02:48:17.679186 INFO : End of 2D write delay Voltage center optimization
426 02:48:17.684824 INFO : Training has run successfully!
427 02:48:17.685243
428 02:48:17.685637 channel==0
429 02:48:17.690384 RxClkDly_Margin_A0==88 ps 9
430 02:48:17.690835 TxDqDly_Margin_A0==98 ps 10
431 02:48:17.693735 RxClkDly_Margin_A1==88 ps 9
432 02:48:17.694192 TxDqDly_Margin_A1==98 ps 10
433 02:48:17.699442 TrainedVREFDQ_A0==74
434 02:48:17.699884 TrainedVREFDQ_A1==74
435 02:48:17.700321 VrefDac_Margin_A0==25
436 02:48:17.705287 DeviceVref_Margin_A0==40
437 02:48:17.705860 VrefDac_Margin_A1==25
438 02:48:17.710449 DeviceVref_Margin_A1==40
439 02:48:17.710982
440 02:48:17.711459
441 02:48:17.711924 channel==1
442 02:48:17.712410 RxClkDly_Margin_A0==98 ps 10
443 02:48:17.714000 TxDqDly_Margin_A0==98 ps 10
444 02:48:17.719463 RxClkDly_Margin_A1==98 ps 10
445 02:48:17.719969 TxDqDly_Margin_A1==88 ps 9
446 02:48:17.720447 TrainedVREFDQ_A0==77
447 02:48:17.725090 TrainedVREFDQ_A1==77
448 02:48:17.725587 VrefDac_Margin_A0==22
449 02:48:17.730718 DeviceVref_Margin_A0==37
450 02:48:17.731211 VrefDac_Margin_A1==22
451 02:48:17.731647 DeviceVref_Margin_A1==37
452 02:48:17.732134
453 02:48:17.736328 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 02:48:17.736837
455 02:48:17.769863 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
456 02:48:17.770439 2D training succeed
457 02:48:17.775525 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 02:48:17.781001 auto size-- 65535DDR cs0 size: 2048MB
459 02:48:17.781513 DDR cs1 size: 2048MB
460 02:48:17.786703 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 02:48:17.787288 cs0 DataBus test pass
462 02:48:17.787740 cs1 DataBus test pass
463 02:48:17.792296 cs0 AddrBus test pass
464 02:48:17.792772 cs1 AddrBus test pass
465 02:48:17.793302
466 02:48:17.797948 100bdlr_step_size ps== 420
467 02:48:17.798524 result report
468 02:48:17.799038 boot times 0Enable ddr reg access
469 02:48:17.807670 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 02:48:17.820399 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 02:48:18.394827 0.0;M3 CHK:0;cm4_sp_mode 0
472 02:48:18.395410 MVN_1=0x00000000
473 02:48:18.400329 MVN_2=0x00000000
474 02:48:18.406178 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 02:48:18.406700 OPS=0x10
476 02:48:18.407255 ring efuse init
477 02:48:18.407773 chipver efuse init
478 02:48:18.414329 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 02:48:18.414861 [0.018960 Inits done]
480 02:48:18.421011 secure task start!
481 02:48:18.421514 high task start!
482 02:48:18.421933 low task start!
483 02:48:18.422339 run into bl31
484 02:48:18.428636 NOTICE: BL31: v1.3(release):4fc40b1
485 02:48:18.436409 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 02:48:18.437016 NOTICE: BL31: G12A normal boot!
487 02:48:18.462310 NOTICE: BL31: BL33 decompress pass
488 02:48:18.467041 ERROR: Error initializing runtime service opteed_fast
489 02:48:19.700714
490 02:48:19.701098
491 02:48:19.708154 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 02:48:19.708451
493 02:48:19.708664 Model: Libre Computer AML-A311D-CC Alta
494 02:48:19.917642 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 02:48:19.940974 DRAM: 2 GiB (effective 3.8 GiB)
496 02:48:20.084080 Core: 408 devices, 31 uclasses, devicetree: separate
497 02:48:20.089025 WDT: Not starting watchdog@f0d0
498 02:48:20.122242 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 02:48:20.134674 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 02:48:20.138733 ** Bad device specification mmc 0 **
501 02:48:20.150017 Card did not respond to voltage select! : -110
502 02:48:20.156887 ** Bad device specification mmc 0 **
503 02:48:20.157429 Couldn't find partition mmc 0
504 02:48:20.165976 Card did not respond to voltage select! : -110
505 02:48:20.171503 ** Bad device specification mmc 0 **
506 02:48:20.172055 Couldn't find partition mmc 0
507 02:48:20.175637 Error: could not access storage.
508 02:48:21.439247 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 02:48:21.439872 bl2_stage_init 0x01
510 02:48:21.440406 bl2_stage_init 0x81
511 02:48:21.444917 hw id: 0x0000 - pwm id 0x01
512 02:48:21.445448 bl2_stage_init 0xc1
513 02:48:21.445909 bl2_stage_init 0x02
514 02:48:21.446358
515 02:48:21.450577 L0:00000000
516 02:48:21.451094 L1:20000703
517 02:48:21.451545 L2:00008067
518 02:48:21.452017 L3:14000000
519 02:48:21.456076 B2:00402000
520 02:48:21.456597 B1:e0f83180
521 02:48:21.457052
522 02:48:21.457644 TE: 58124
523 02:48:21.458147
524 02:48:21.461692 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 02:48:21.462213
526 02:48:21.462667 Board ID = 1
527 02:48:21.467279 Set A53 clk to 24M
528 02:48:21.467797 Set A73 clk to 24M
529 02:48:21.468285 Set clk81 to 24M
530 02:48:21.472892 A53 clk: 1200 MHz
531 02:48:21.473406 A73 clk: 1200 MHz
532 02:48:21.473856 CLK81: 166.6M
533 02:48:21.474295 smccc: 00012a91
534 02:48:21.478461 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 02:48:21.484132 board id: 1
536 02:48:21.489951 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 02:48:21.500621 fw parse done
538 02:48:21.505899 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 02:48:21.549218 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 02:48:21.560197 PIEI prepare done
541 02:48:21.560734 fastboot data load
542 02:48:21.561194 fastboot data verify
543 02:48:21.565811 verify result: 266
544 02:48:21.571384 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 02:48:21.571908 LPDDR4 probe
546 02:48:21.572410 ddr clk to 1584MHz
547 02:48:21.579400 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 02:48:21.615701
549 02:48:21.616267 dmc_version 0001
550 02:48:21.623150 Check phy result
551 02:48:21.629179 INFO : End of CA training
552 02:48:21.629701 INFO : End of initialization
553 02:48:21.634833 INFO : Training has run successfully!
554 02:48:21.635348 Check phy result
555 02:48:21.640396 INFO : End of initialization
556 02:48:21.640908 INFO : End of read enable training
557 02:48:21.645912 INFO : End of fine write leveling
558 02:48:21.651549 INFO : End of Write leveling coarse delay
559 02:48:21.652125 INFO : Training has run successfully!
560 02:48:21.652582 Check phy result
561 02:48:21.657194 INFO : End of initialization
562 02:48:21.657716 INFO : End of read dq deskew training
563 02:48:21.662834 INFO : End of MPR read delay center optimization
564 02:48:21.668365 INFO : End of write delay center optimization
565 02:48:21.673985 INFO : End of read delay center optimization
566 02:48:21.674613 INFO : End of max read latency training
567 02:48:21.679698 INFO : Training has run successfully!
568 02:48:21.680260 1D training succeed
569 02:48:21.688709 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 02:48:21.736376 Check phy result
571 02:48:21.736904 INFO : End of initialization
572 02:48:21.757954 INFO : End of 2D read delay Voltage center optimization
573 02:48:21.777125 INFO : End of 2D read delay Voltage center optimization
574 02:48:21.829953 INFO : End of 2D write delay Voltage center optimization
575 02:48:21.879277 INFO : End of 2D write delay Voltage center optimization
576 02:48:21.884855 INFO : Training has run successfully!
577 02:48:21.885376
578 02:48:21.885833 channel==0
579 02:48:21.890354 RxClkDly_Margin_A0==88 ps 9
580 02:48:21.890863 TxDqDly_Margin_A0==98 ps 10
581 02:48:21.896050 RxClkDly_Margin_A1==88 ps 9
582 02:48:21.896562 TxDqDly_Margin_A1==98 ps 10
583 02:48:21.897017 TrainedVREFDQ_A0==74
584 02:48:21.902040 TrainedVREFDQ_A1==74
585 02:48:21.902552 VrefDac_Margin_A0==25
586 02:48:21.903001 DeviceVref_Margin_A0==40
587 02:48:21.907155 VrefDac_Margin_A1==25
588 02:48:21.907662 DeviceVref_Margin_A1==40
589 02:48:21.908148
590 02:48:21.908593
591 02:48:21.912787 channel==1
592 02:48:21.913309 RxClkDly_Margin_A0==98 ps 10
593 02:48:21.913763 TxDqDly_Margin_A0==88 ps 9
594 02:48:21.918378 RxClkDly_Margin_A1==98 ps 10
595 02:48:21.918901 TxDqDly_Margin_A1==88 ps 9
596 02:48:21.923958 TrainedVREFDQ_A0==77
597 02:48:21.924505 TrainedVREFDQ_A1==77
598 02:48:21.924960 VrefDac_Margin_A0==22
599 02:48:21.929539 DeviceVref_Margin_A0==37
600 02:48:21.930058 VrefDac_Margin_A1==24
601 02:48:21.935145 DeviceVref_Margin_A1==37
602 02:48:21.935658
603 02:48:21.936149 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 02:48:21.936596
605 02:48:21.968803 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
606 02:48:21.969370 2D training succeed
607 02:48:21.974420 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 02:48:21.979921 auto size-- 65535DDR cs0 size: 2048MB
609 02:48:21.980478 DDR cs1 size: 2048MB
610 02:48:21.985635 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 02:48:21.986157 cs0 DataBus test pass
612 02:48:21.991230 cs1 DataBus test pass
613 02:48:21.991740 cs0 AddrBus test pass
614 02:48:21.992232 cs1 AddrBus test pass
615 02:48:21.992672
616 02:48:21.996863 100bdlr_step_size ps== 420
617 02:48:21.997383 result report
618 02:48:22.002465 boot times 0Enable ddr reg access
619 02:48:22.006724 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 02:48:22.021217 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 02:48:22.593137 0.0;M3 CHK:0;cm4_sp_mode 0
622 02:48:22.593786 MVN_1=0x00000000
623 02:48:22.598703 MVN_2=0x00000000
624 02:48:22.604459 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 02:48:22.604916 OPS=0x10
626 02:48:22.605313 ring efuse init
627 02:48:22.605875 chipver efuse init
628 02:48:22.610115 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 02:48:22.615677 [0.018960 Inits done]
630 02:48:22.616221 secure task start!
631 02:48:22.616656 high task start!
632 02:48:22.620370 low task start!
633 02:48:22.620862 run into bl31
634 02:48:22.626886 NOTICE: BL31: v1.3(release):4fc40b1
635 02:48:22.633734 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 02:48:22.634243 NOTICE: BL31: G12A normal boot!
637 02:48:22.660054 NOTICE: BL31: BL33 decompress pass
638 02:48:22.665763 ERROR: Error initializing runtime service opteed_fast
639 02:48:23.899141
640 02:48:23.899821
641 02:48:23.906846 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 02:48:23.907497
643 02:48:23.908023 Model: Libre Computer AML-A311D-CC Alta
644 02:48:24.115503 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 02:48:24.138990 DRAM: 2 GiB (effective 3.8 GiB)
646 02:48:24.281830 Core: 408 devices, 31 uclasses, devicetree: separate
647 02:48:24.287763 WDT: Not starting watchdog@f0d0
648 02:48:24.320041 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 02:48:24.332456 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 02:48:24.337415 ** Bad device specification mmc 0 **
651 02:48:24.347783 Card did not respond to voltage select! : -110
652 02:48:24.355398 ** Bad device specification mmc 0 **
653 02:48:24.355958 Couldn't find partition mmc 0
654 02:48:24.363792 Card did not respond to voltage select! : -110
655 02:48:24.369245 ** Bad device specification mmc 0 **
656 02:48:24.369754 Couldn't find partition mmc 0
657 02:48:24.374488 Error: could not access storage.
658 02:48:24.716693 Net: eth0: ethernet@ff3f0000
659 02:48:24.717092 starting USB...
660 02:48:24.968711 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 02:48:24.969355 Starting the controller
662 02:48:24.975653 USB XHCI 1.10
663 02:48:26.689442 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 02:48:26.690119 bl2_stage_init 0x01
665 02:48:26.690590 bl2_stage_init 0x81
666 02:48:26.694998 hw id: 0x0000 - pwm id 0x01
667 02:48:26.695525 bl2_stage_init 0xc1
668 02:48:26.696021 bl2_stage_init 0x02
669 02:48:26.696474
670 02:48:26.700568 L0:00000000
671 02:48:26.701074 L1:20000703
672 02:48:26.701517 L2:00008067
673 02:48:26.701953 L3:14000000
674 02:48:26.706175 B2:00402000
675 02:48:26.706691 B1:e0f83180
676 02:48:26.707136
677 02:48:26.707573 TE: 58167
678 02:48:26.708043
679 02:48:26.711851 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 02:48:26.712418
681 02:48:26.712871 Board ID = 1
682 02:48:26.717388 Set A53 clk to 24M
683 02:48:26.717890 Set A73 clk to 24M
684 02:48:26.718335 Set clk81 to 24M
685 02:48:26.722974 A53 clk: 1200 MHz
686 02:48:26.723466 A73 clk: 1200 MHz
687 02:48:26.723906 CLK81: 166.6M
688 02:48:26.724386 smccc: 00012abe
689 02:48:26.728588 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 02:48:26.734176 board id: 1
691 02:48:26.740061 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 02:48:26.750804 fw parse done
693 02:48:26.756667 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 02:48:26.799326 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 02:48:26.810237 PIEI prepare done
696 02:48:26.810846 fastboot data load
697 02:48:26.811296 fastboot data verify
698 02:48:26.816081 verify result: 266
699 02:48:26.821567 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 02:48:26.822135 LPDDR4 probe
701 02:48:26.822568 ddr clk to 1584MHz
702 02:48:26.829534 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 02:48:26.866852
704 02:48:26.867480 dmc_version 0001
705 02:48:26.873506 Check phy result
706 02:48:26.879332 INFO : End of CA training
707 02:48:26.879929 INFO : End of initialization
708 02:48:26.884946 INFO : Training has run successfully!
709 02:48:26.885270 Check phy result
710 02:48:26.890503 INFO : End of initialization
711 02:48:26.890832 INFO : End of read enable training
712 02:48:26.896150 INFO : End of fine write leveling
713 02:48:26.901600 INFO : End of Write leveling coarse delay
714 02:48:26.901871 INFO : Training has run successfully!
715 02:48:26.902075 Check phy result
716 02:48:26.907114 INFO : End of initialization
717 02:48:26.907373 INFO : End of read dq deskew training
718 02:48:26.912828 INFO : End of MPR read delay center optimization
719 02:48:26.918370 INFO : End of write delay center optimization
720 02:48:26.923907 INFO : End of read delay center optimization
721 02:48:26.924188 INFO : End of max read latency training
722 02:48:26.929653 INFO : Training has run successfully!
723 02:48:26.930006 1D training succeed
724 02:48:26.938755 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 02:48:26.985727 Check phy result
726 02:48:26.986316 INFO : End of initialization
727 02:48:27.008299 INFO : End of 2D read delay Voltage center optimization
728 02:48:27.028510 INFO : End of 2D read delay Voltage center optimization
729 02:48:27.080547 INFO : End of 2D write delay Voltage center optimization
730 02:48:27.129957 INFO : End of 2D write delay Voltage center optimization
731 02:48:27.135420 INFO : Training has run successfully!
732 02:48:27.135944
733 02:48:27.136452 channel==0
734 02:48:27.140991 RxClkDly_Margin_A0==88 ps 9
735 02:48:27.141530 TxDqDly_Margin_A0==98 ps 10
736 02:48:27.146637 RxClkDly_Margin_A1==88 ps 9
737 02:48:27.147188 TxDqDly_Margin_A1==98 ps 10
738 02:48:27.147651 TrainedVREFDQ_A0==74
739 02:48:27.152237 TrainedVREFDQ_A1==74
740 02:48:27.152782 VrefDac_Margin_A0==25
741 02:48:27.153238 DeviceVref_Margin_A0==40
742 02:48:27.157932 VrefDac_Margin_A1==25
743 02:48:27.158479 DeviceVref_Margin_A1==40
744 02:48:27.158934
745 02:48:27.159383
746 02:48:27.163394 channel==1
747 02:48:27.163928 RxClkDly_Margin_A0==98 ps 10
748 02:48:27.164437 TxDqDly_Margin_A0==98 ps 10
749 02:48:27.169016 RxClkDly_Margin_A1==98 ps 10
750 02:48:27.169560 TxDqDly_Margin_A1==98 ps 10
751 02:48:27.174568 TrainedVREFDQ_A0==77
752 02:48:27.175117 TrainedVREFDQ_A1==77
753 02:48:27.175573 VrefDac_Margin_A0==22
754 02:48:27.180218 DeviceVref_Margin_A0==37
755 02:48:27.180749 VrefDac_Margin_A1==22
756 02:48:27.185914 DeviceVref_Margin_A1==37
757 02:48:27.186441
758 02:48:27.186892 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 02:48:27.191437
760 02:48:27.219341 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
761 02:48:27.219956 2D training succeed
762 02:48:27.224987 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 02:48:27.230578 auto size-- 65535DDR cs0 size: 2048MB
764 02:48:27.231119 DDR cs1 size: 2048MB
765 02:48:27.236147 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 02:48:27.236675 cs0 DataBus test pass
767 02:48:27.241896 cs1 DataBus test pass
768 02:48:27.242415 cs0 AddrBus test pass
769 02:48:27.242862 cs1 AddrBus test pass
770 02:48:27.243298
771 02:48:27.247407 100bdlr_step_size ps== 420
772 02:48:27.247947 result report
773 02:48:27.252933 boot times 0Enable ddr reg access
774 02:48:27.258476 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 02:48:27.270976 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 02:48:27.845737 0.0;M3 CHK:0;cm4_sp_mode 0
777 02:48:27.846432 MVN_1=0x00000000
778 02:48:27.851190 MVN_2=0x00000000
779 02:48:27.857003 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 02:48:27.857651 OPS=0x10
781 02:48:27.858105 ring efuse init
782 02:48:27.858540 chipver efuse init
783 02:48:27.862501 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 02:48:27.868093 [0.018961 Inits done]
785 02:48:27.868615 secure task start!
786 02:48:27.869046 high task start!
787 02:48:27.872675 low task start!
788 02:48:27.873197 run into bl31
789 02:48:27.879494 NOTICE: BL31: v1.3(release):4fc40b1
790 02:48:27.886210 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 02:48:27.886694 NOTICE: BL31: G12A normal boot!
792 02:48:27.912407 NOTICE: BL31: BL33 decompress pass
793 02:48:27.918056 ERROR: Error initializing runtime service opteed_fast
794 02:48:29.150997
795 02:48:29.151621
796 02:48:29.159397 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 02:48:29.159887
798 02:48:29.160375 Model: Libre Computer AML-A311D-CC Alta
799 02:48:29.366801 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 02:48:29.390693 DRAM: 2 GiB (effective 3.8 GiB)
801 02:48:29.534391 Core: 408 devices, 31 uclasses, devicetree: separate
802 02:48:29.539215 WDT: Not starting watchdog@f0d0
803 02:48:29.572594 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 02:48:29.584975 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 02:48:29.588830 ** Bad device specification mmc 0 **
806 02:48:29.600395 Card did not respond to voltage select! : -110
807 02:48:29.607932 ** Bad device specification mmc 0 **
808 02:48:29.608501 Couldn't find partition mmc 0
809 02:48:29.616345 Card did not respond to voltage select! : -110
810 02:48:29.621821 ** Bad device specification mmc 0 **
811 02:48:29.622369 Couldn't find partition mmc 0
812 02:48:29.625841 Error: could not access storage.
813 02:48:29.968582 Net: eth0: ethernet@ff3f0000
814 02:48:29.969233 starting USB...
815 02:48:30.221002 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 02:48:30.221650 Starting the controller
817 02:48:30.228073 USB XHCI 1.10
818 02:48:32.389446 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
819 02:48:32.389859 bl2_stage_init 0x81
820 02:48:32.394952 hw id: 0x0000 - pwm id 0x01
821 02:48:32.395240 bl2_stage_init 0xc1
822 02:48:32.395447 bl2_stage_init 0x02
823 02:48:32.395707
824 02:48:32.400503 L0:00000000
825 02:48:32.401494 L1:20000703
826 02:48:32.402095 L2:00008067
827 02:48:32.402300 L3:14000000
828 02:48:32.402604 B2:00402000
829 02:48:32.406387 B1:e0f83180
830 02:48:32.406754
831 02:48:32.407028 TE: 58150
832 02:48:32.407280
833 02:48:32.411808 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
834 02:48:32.412465
835 02:48:32.413044 Board ID = 1
836 02:48:32.417511 Set A53 clk to 24M
837 02:48:32.417805 Set A73 clk to 24M
838 02:48:32.418084 Set clk81 to 24M
839 02:48:32.422968 A53 clk: 1200 MHz
840 02:48:32.423289 A73 clk: 1200 MHz
841 02:48:32.423556 CLK81: 166.6M
842 02:48:32.423770 smccc: 00012aac
843 02:48:32.428511 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
844 02:48:32.434177 board id: 1
845 02:48:32.440055 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
846 02:48:32.450656 fw parse done
847 02:48:32.456559 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
848 02:48:32.499291 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
849 02:48:32.510149 PIEI prepare done
850 02:48:32.510921 fastboot data load
851 02:48:32.511529 fastboot data verify
852 02:48:32.515854 verify result: 266
853 02:48:32.521397 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
854 02:48:32.521957 LPDDR4 probe
855 02:48:32.522466 ddr clk to 1584MHz
856 02:48:32.529372 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
857 02:48:32.566737
858 02:48:32.567327 dmc_version 0001
859 02:48:32.573336 Check phy result
860 02:48:32.579208 INFO : End of CA training
861 02:48:32.579770 INFO : End of initialization
862 02:48:32.584785 INFO : Training has run successfully!
863 02:48:32.585401 Check phy result
864 02:48:32.590383 INFO : End of initialization
865 02:48:32.591010 INFO : End of read enable training
866 02:48:32.596041 INFO : End of fine write leveling
867 02:48:32.601626 INFO : End of Write leveling coarse delay
868 02:48:32.602185 INFO : Training has run successfully!
869 02:48:32.602753 Check phy result
870 02:48:32.607220 INFO : End of initialization
871 02:48:32.607785 INFO : End of read dq deskew training
872 02:48:32.612822 INFO : End of MPR read delay center optimization
873 02:48:32.618381 INFO : End of write delay center optimization
874 02:48:32.624032 INFO : End of read delay center optimization
875 02:48:32.624653 INFO : End of max read latency training
876 02:48:32.629623 INFO : Training has run successfully!
877 02:48:32.630176 1D training succeed
878 02:48:32.638794 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
879 02:48:32.686371 Check phy result
880 02:48:32.687005 INFO : End of initialization
881 02:48:32.708164 INFO : End of 2D read delay Voltage center optimization
882 02:48:32.728429 INFO : End of 2D read delay Voltage center optimization
883 02:48:32.781011 INFO : End of 2D write delay Voltage center optimization
884 02:48:32.829786 INFO : End of 2D write delay Voltage center optimization
885 02:48:32.835381 INFO : Training has run successfully!
886 02:48:32.835936
887 02:48:32.836429 channel==0
888 02:48:32.840957 RxClkDly_Margin_A0==88 ps 9
889 02:48:32.841512 TxDqDly_Margin_A0==98 ps 10
890 02:48:32.846693 RxClkDly_Margin_A1==88 ps 9
891 02:48:32.847251 TxDqDly_Margin_A1==98 ps 10
892 02:48:32.847697 TrainedVREFDQ_A0==74
893 02:48:32.852185 TrainedVREFDQ_A1==74
894 02:48:32.852739 VrefDac_Margin_A0==25
895 02:48:32.853175 DeviceVref_Margin_A0==40
896 02:48:32.857843 VrefDac_Margin_A1==25
897 02:48:32.858382 DeviceVref_Margin_A1==40
898 02:48:32.858810
899 02:48:32.859239
900 02:48:32.863428 channel==1
901 02:48:32.864009 RxClkDly_Margin_A0==98 ps 10
902 02:48:32.864470 TxDqDly_Margin_A0==98 ps 10
903 02:48:32.869002 RxClkDly_Margin_A1==98 ps 10
904 02:48:32.869554 TxDqDly_Margin_A1==88 ps 9
905 02:48:32.874686 TrainedVREFDQ_A0==77
906 02:48:32.875232 TrainedVREFDQ_A1==77
907 02:48:32.875669 VrefDac_Margin_A0==22
908 02:48:32.880219 DeviceVref_Margin_A0==37
909 02:48:32.880758 VrefDac_Margin_A1==22
910 02:48:32.885800 DeviceVref_Margin_A1==37
911 02:48:32.886349
912 02:48:32.886781 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
913 02:48:32.891411
914 02:48:32.919386 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
915 02:48:32.920006 2D training succeed
916 02:48:32.924974 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
917 02:48:32.930661 auto size-- 65535DDR cs0 size: 2048MB
918 02:48:32.931308 DDR cs1 size: 2048MB
919 02:48:32.936248 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
920 02:48:32.936788 cs0 DataBus test pass
921 02:48:32.941777 cs1 DataBus test pass
922 02:48:32.942316 cs0 AddrBus test pass
923 02:48:32.942889 cs1 AddrBus test pass
924 02:48:32.943336
925 02:48:32.947355 100bdlr_step_size ps== 420
926 02:48:32.948032 result report
927 02:48:32.952953 boot times 0Enable ddr reg access
928 02:48:32.958395 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
929 02:48:32.971864 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
930 02:48:33.544829 0.0;M3 CHK:0;cm4_sp_mode 0
931 02:48:33.545601 MVN_1=0x00000000
932 02:48:33.551110 MVN_2=0x00000000
933 02:48:33.556198 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
934 02:48:33.556773 OPS=0x10
935 02:48:33.557226 ring efuse init
936 02:48:33.557716 chipver efuse init
937 02:48:33.561783 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
938 02:48:33.567391 [0.018961 Inits done]
939 02:48:33.567922 secure task start!
940 02:48:33.568413 high task start!
941 02:48:33.571916 low task start!
942 02:48:33.572479 run into bl31
943 02:48:33.578583 NOTICE: BL31: v1.3(release):4fc40b1
944 02:48:33.586421 NOTICE: BL31: Built : 15:58:17, May 22 2019
945 02:48:33.586976 NOTICE: BL31: G12A normal boot!
946 02:48:33.611705 NOTICE: BL31: BL33 decompress pass
947 02:48:33.617456 ERROR: Error initializing runtime service opteed_fast
948 02:48:34.850415
949 02:48:34.851172
950 02:48:34.858914 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
951 02:48:34.859449
952 02:48:34.859894 Model: Libre Computer AML-A311D-CC Alta
953 02:48:35.067149 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
954 02:48:35.090685 DRAM: 2 GiB (effective 3.8 GiB)
955 02:48:35.233577 Core: 408 devices, 31 uclasses, devicetree: separate
956 02:48:35.239555 WDT: Not starting watchdog@f0d0
957 02:48:35.271795 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
958 02:48:35.284276 Loading Environment from FAT... Card did not respond to voltage select! : -110
959 02:48:35.289254 ** Bad device specification mmc 0 **
960 02:48:35.299539 Card did not respond to voltage select! : -110
961 02:48:35.307401 ** Bad device specification mmc 0 **
962 02:48:35.307937 Couldn't find partition mmc 0
963 02:48:35.315520 Card did not respond to voltage select! : -110
964 02:48:35.321050 ** Bad device specification mmc 0 **
965 02:48:35.321563 Couldn't find partition mmc 0
966 02:48:35.326089 Error: could not access storage.
967 02:48:35.668801 Net: eth0: ethernet@ff3f0000
968 02:48:35.669384 starting USB...
969 02:48:35.921231 Bus usb@ff500000: Register 3000140 NbrPorts 3
970 02:48:35.921799 Starting the controller
971 02:48:35.928252 USB XHCI 1.10
972 02:48:37.482045 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
973 02:48:37.490437 scanning usb for storage devices... 0 Storage Device(s) found
975 02:48:37.542520 Hit any key to stop autoboot: 1
976 02:48:37.543847 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
977 02:48:37.544784 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
978 02:48:37.545040 Setting prompt string to ['=>']
979 02:48:37.545335 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
980 02:48:37.556933 0
981 02:48:37.558310 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
982 02:48:37.558579 Sending with 10 millisecond of delay
984 02:48:38.692889 => setenv autoload no
985 02:48:38.703729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
986 02:48:38.709236 setenv autoload no
987 02:48:38.710036 Sending with 10 millisecond of delay
989 02:48:40.508047 => setenv initrd_high 0xffffffff
990 02:48:40.518862 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
991 02:48:40.519795 setenv initrd_high 0xffffffff
992 02:48:40.520596 Sending with 10 millisecond of delay
994 02:48:42.136810 => setenv fdt_high 0xffffffff
995 02:48:42.147621 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
996 02:48:42.148568 setenv fdt_high 0xffffffff
997 02:48:42.149334 Sending with 10 millisecond of delay
999 02:48:42.441451 => dhcp
1000 02:48:42.452260 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1001 02:48:42.453189 dhcp
1002 02:48:42.453670 Speed: 1000, full duplex
1003 02:48:42.454147 BOOTP broadcast 1
1004 02:48:42.700967 BOOTP broadcast 2
1005 02:48:42.785654 DHCP client bound to address 192.168.6.33 (333 ms)
1006 02:48:42.786519 Sending with 10 millisecond of delay
1008 02:48:44.464122 => setenv serverip 192.168.6.2
1009 02:48:44.474994 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1010 02:48:44.475889 setenv serverip 192.168.6.2
1011 02:48:44.476679 Sending with 10 millisecond of delay
1013 02:48:48.200895 => tftpboot 0x01080000 830727/tftp-deploy-2tyca09k/kernel/uImage
1014 02:48:48.211669 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 02:48:48.212207 tftpboot 0x01080000 830727/tftp-deploy-2tyca09k/kernel/uImage
1016 02:48:48.212459 Speed: 1000, full duplex
1017 02:48:48.212667 Using ethernet@ff3f0000 device
1018 02:48:48.214333 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1019 02:48:48.219908 Filename '830727/tftp-deploy-2tyca09k/kernel/uImage'.
1020 02:48:48.223918 Load address: 0x1080000
1021 02:48:49.545148 Loading: *################## UDP wrong checksum 000000ff 0000e534
1022 02:48:49.583348 # UDP wrong checksum 000000ff 00007f27
1023 02:48:52.419713 ############################### 43.6 MiB
1024 02:48:52.420396 10.4 MiB/s
1025 02:48:52.420871 done
1026 02:48:52.423456 Bytes transferred = 45713984 (2b98a40 hex)
1027 02:48:52.424346 Sending with 10 millisecond of delay
1029 02:48:57.112485 => tftpboot 0x08000000 830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot
1030 02:48:57.123280 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1031 02:48:57.124222 tftpboot 0x08000000 830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot
1032 02:48:57.124700 Speed: 1000, full duplex
1033 02:48:57.125137 Using ethernet@ff3f0000 device
1034 02:48:57.126156 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1035 02:48:57.134702 Filename '830727/tftp-deploy-2tyca09k/ramdisk/ramdisk.cpio.gz.uboot'.
1036 02:48:57.135236 Load address: 0x8000000
1037 02:48:59.022034 Loading: *################################################## 22.3 MiB
1038 02:48:59.022756 11.9 MiB/s
1039 02:48:59.023227 done
1040 02:48:59.026370 Bytes transferred = 23425908 (1657374 hex)
1041 02:48:59.027184 Sending with 10 millisecond of delay
1043 02:49:04.198781 => tftpboot 0x01070000 830727/tftp-deploy-2tyca09k/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 02:49:04.209935 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
1045 02:49:04.211084 tftpboot 0x01070000 830727/tftp-deploy-2tyca09k/dtb/meson-g12b-a311d-libretech-cc.dtb
1046 02:49:04.211666 Speed: 1000, full duplex
1047 02:49:04.212378 Using ethernet@ff3f0000 device
1048 02:49:04.215374 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1049 02:49:04.222736 Filename '830727/tftp-deploy-2tyca09k/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1050 02:49:04.234484 Load address: 0x1070000
1051 02:49:04.246370 Loading: *################################################## 53.4 KiB
1052 02:49:04.246948 2.7 MiB/s
1053 02:49:04.247450 done
1054 02:49:04.251112 Bytes transferred = 54703 (d5af hex)
1055 02:49:04.251930 Sending with 10 millisecond of delay
1057 02:49:17.559757 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 02:49:17.570678 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:48)
1059 02:49:17.571626 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1060 02:49:17.572431 Sending with 10 millisecond of delay
1062 02:49:19.914468 => bootm 0x01080000 0x08000000 0x01070000
1063 02:49:19.925107 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1064 02:49:19.926186 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:46)
1065 02:49:19.927805 bootm 0x01080000 0x08000000 0x01070000
1066 02:49:19.928073 ## Booting kernel from Legacy Image at 01080000 ...
1067 02:49:19.929928 Image Name:
1068 02:49:19.935296 Image Type: AArch64 Linux Kernel Image (uncompressed)
1069 02:49:19.935574 Data Size: 45713920 Bytes = 43.6 MiB
1070 02:49:19.937586 Load Address: 01080000
1071 02:49:19.944154 Entry Point: 01080000
1072 02:49:20.136478 Verifying Checksum ... OK
1073 02:49:20.137147 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1074 02:49:20.141760 Image Name:
1075 02:49:20.147205 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1076 02:49:20.147692 Data Size: 23425844 Bytes = 22.3 MiB
1077 02:49:20.149561 Load Address: 00000000
1078 02:49:20.156749 Entry Point: 00000000
1079 02:49:20.255088 Verifying Checksum ... OK
1080 02:49:20.255698 ## Flattened Device Tree blob at 01070000
1081 02:49:20.260339 Booting using the fdt blob at 0x1070000
1082 02:49:20.260830 Working FDT set to 1070000
1083 02:49:20.264835 Loading Kernel Image
1084 02:49:20.416339 Loading Ramdisk to 7e9a8000, end 7ffff334 ... OK
1085 02:49:20.424594 Loading Device Tree to 000000007e997000, end 000000007e9a75ae ... OK
1086 02:49:20.425106 Working FDT set to 7e997000
1087 02:49:20.425556
1088 02:49:20.426517 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
1089 02:49:20.427157 start: 2.4.4 auto-login-action (timeout 00:03:45) [common]
1090 02:49:20.427664 Setting prompt string to ['Linux version [0-9]']
1091 02:49:20.428277 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1092 02:49:20.428844 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1093 02:49:20.430243 Starting kernel ...
1094 02:49:20.430764
1095 02:49:20.465011 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1096 02:49:20.466024 start: 2.4.4.1 login-action (timeout 00:03:45) [common]
1097 02:49:20.466599 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1098 02:49:20.467103 Setting prompt string to []
1099 02:49:20.467631 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1100 02:49:20.468168 Using line separator: #'\n'#
1101 02:49:20.468624 No login prompt set.
1102 02:49:20.469099 Parsing kernel messages
1103 02:49:20.469532 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1104 02:49:20.470398 [login-action] Waiting for messages, (timeout 00:03:45)
1105 02:49:20.470891 Waiting using forced prompt support (timeout 00:01:53)
1106 02:49:20.485045 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j339498-arm64-gcc-12-defconfig-zmgzj) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Oct 10 01:19:59 UTC 2024
1107 02:49:20.485639 [ 0.000000] KASLR disabled due to lack of seed
1108 02:49:20.490555 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1109 02:49:20.494194 [ 0.000000] efi: UEFI not found.
1110 02:49:20.505184 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1111 02:49:20.510700 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1112 02:49:20.519930 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1113 02:49:20.531059 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1114 02:49:20.536368 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1115 02:49:20.547400 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1116 02:49:20.558481 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1117 02:49:20.563859 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1118 02:49:20.569375 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1119 02:49:20.574993 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1120 02:49:20.575480 [ 0.000000] Zone ranges:
1121 02:49:20.580602 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1122 02:49:20.586021 [ 0.000000] DMA32 empty
1123 02:49:20.586499 [ 0.000000] Normal empty
1124 02:49:20.591562 [ 0.000000] Movable zone start for each node
1125 02:49:20.597082 [ 0.000000] Early memory node ranges
1126 02:49:20.602651 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1127 02:49:20.608114 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1128 02:49:20.613663 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1129 02:49:20.622386 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1130 02:49:20.646748 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1131 02:49:20.652261 [ 0.000000] psci: probing for conduit method from DT.
1132 02:49:20.652760 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1133 02:49:20.657919 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1134 02:49:20.663286 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1135 02:49:20.668916 [ 0.000000] psci: SMC Calling Convention v1.1
1136 02:49:20.674335 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1137 02:49:20.679955 [ 0.000000] Detected VIPT I-cache on CPU0
1138 02:49:20.685386 [ 0.000000] CPU features: detected: ARM erratum 845719
1139 02:49:20.690926 [ 0.000000] alternatives: applying boot alternatives
1140 02:49:20.707456 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1141 02:49:20.718509 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1142 02:49:20.724058 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1143 02:49:20.729568 <6>[ 0.000000] Fallback order for Node 0: 0
1144 02:49:20.735153 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1145 02:49:20.740652 <6>[ 0.000000] Policy zone: DMA
1146 02:49:20.746201 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1147 02:49:20.751695 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1148 02:49:20.757157 <6>[ 0.000000] software IO TLB: area num 8.
1149 02:49:20.766131 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1150 02:49:20.812594 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1151 02:49:20.818080 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1152 02:49:20.821609 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1153 02:49:20.827037 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1154 02:49:20.832575 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1155 02:49:20.838078 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1156 02:49:20.849106 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1157 02:49:20.854640 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1158 02:49:20.860170 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 02:49:20.871206 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1160 02:49:20.876850 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1161 02:49:20.882289 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1162 02:49:20.887837 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1163 02:49:20.894264 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1164 02:49:20.907009 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1165 02:49:20.918006 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1166 02:49:20.923513 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1167 02:49:20.929034 <6>[ 0.008796] Console: colour dummy device 80x25
1168 02:49:20.940185 <6>[ 0.012938] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1169 02:49:20.945687 <6>[ 0.023293] pid_max: default: 32768 minimum: 301
1170 02:49:20.951191 <6>[ 0.028189] LSM: initializing lsm=capability
1171 02:49:20.956816 <6>[ 0.032728] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 02:49:20.962139 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 02:49:20.967650 <6>[ 0.052300] rcu: Hierarchical SRCU implementation.
1174 02:49:20.973248 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1175 02:49:20.984376 <6>[ 0.058874] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1176 02:49:20.992660 <6>[ 0.071554] EFI services will not be available.
1177 02:49:20.992903 <6>[ 0.075209] smp: Bringing up secondary CPUs ...
1178 02:49:21.005091 <6>[ 0.077128] Detected VIPT I-cache on CPU1
1179 02:49:21.010546 <6>[ 0.077246] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1180 02:49:21.016121 <6>[ 0.078584] CPU features: detected: Spectre-v2
1181 02:49:21.021589 <6>[ 0.078599] CPU features: detected: Spectre-v4
1182 02:49:21.027140 <6>[ 0.078604] CPU features: detected: Spectre-BHB
1183 02:49:21.032625 <6>[ 0.078610] CPU features: detected: ARM erratum 858921
1184 02:49:21.038155 <6>[ 0.078618] Detected VIPT I-cache on CPU2
1185 02:49:21.043703 <6>[ 0.078689] arch_timer: Enabling local workaround for ARM erratum 858921
1186 02:49:21.049184 <6>[ 0.078707] arch_timer: CPU2: Trapping CNTVCT access
1187 02:49:21.054816 <6>[ 0.078716] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1188 02:49:21.060328 <6>[ 0.083557] Detected VIPT I-cache on CPU3
1189 02:49:21.065781 <6>[ 0.083602] arch_timer: Enabling local workaround for ARM erratum 858921
1190 02:49:21.071249 <6>[ 0.083612] arch_timer: CPU3: Trapping CNTVCT access
1191 02:49:21.076877 <6>[ 0.083619] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1192 02:49:21.082361 <6>[ 0.087595] Detected VIPT I-cache on CPU4
1193 02:49:21.087873 <6>[ 0.087641] arch_timer: Enabling local workaround for ARM erratum 858921
1194 02:49:21.093370 <6>[ 0.087651] arch_timer: CPU4: Trapping CNTVCT access
1195 02:49:21.104351 <6>[ 0.087658] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1196 02:49:21.104947 <6>[ 0.091592] Detected VIPT I-cache on CPU5
1197 02:49:21.115570 <6>[ 0.091639] arch_timer: Enabling local workaround for ARM erratum 858921
1198 02:49:21.116200 <6>[ 0.091649] arch_timer: CPU5: Trapping CNTVCT access
1199 02:49:21.126453 <6>[ 0.091656] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1200 02:49:21.127041 <6>[ 0.091769] smp: Brought up 1 node, 6 CPUs
1201 02:49:21.132114 <6>[ 0.213003] SMP: Total of 6 processors activated.
1202 02:49:21.137550 <6>[ 0.217908] CPU: All CPU(s) started at EL2
1203 02:49:21.143148 <6>[ 0.222259] CPU features: detected: 32-bit EL0 Support
1204 02:49:21.148536 <6>[ 0.227570] CPU features: detected: 32-bit EL1 Support
1205 02:49:21.154133 <6>[ 0.232915] CPU features: detected: CRC32 instructions
1206 02:49:21.159575 <6>[ 0.238320] alternatives: applying system-wide alternatives
1207 02:49:21.177557 <6>[ 0.245497] Memory: 3557440K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187792K reserved, 262144K cma-reserved)
1208 02:49:21.178162 <6>[ 0.259849] devtmpfs: initialized
1209 02:49:21.188566 <6>[ 0.269000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1210 02:49:21.194078 <6>[ 0.273359] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1211 02:49:21.199587 <6>[ 0.284151] 21392 pages in range for non-PLT usage
1212 02:49:21.205126 <6>[ 0.284159] 512912 pages in range for PLT usage
1213 02:49:21.210587 <6>[ 0.285711] pinctrl core: initialized pinctrl subsystem
1214 02:49:21.216185 <6>[ 0.297791] DMI not present or invalid.
1215 02:49:21.221652 <6>[ 0.302079] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1216 02:49:21.227206 <6>[ 0.306825] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1217 02:49:21.238257 <6>[ 0.313595] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1218 02:49:21.243756 <6>[ 0.321695] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1219 02:49:21.249272 <6>[ 0.329190] audit: initializing netlink subsys (disabled)
1220 02:49:21.260275 <5>[ 0.334916] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1221 02:49:21.265804 <6>[ 0.336331] thermal_sys: Registered thermal governor 'step_wise'
1222 02:49:21.271252 <6>[ 0.342697] thermal_sys: Registered thermal governor 'power_allocator'
1223 02:49:21.276766 <6>[ 0.348958] cpuidle: using governor menu
1224 02:49:21.282377 <6>[ 0.359984] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1225 02:49:21.287844 <6>[ 0.366874] ASID allocator initialised with 65536 entries
1226 02:49:21.296116 <6>[ 0.374423] Serial: AMBA PL011 UART driver
1227 02:49:21.303906 <6>[ 0.384942] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 02:49:21.319254 <6>[ 0.400363] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 02:49:21.328235 <6>[ 0.403026] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1230 02:49:21.333734 <6>[ 0.416183] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1231 02:49:21.344680 <6>[ 0.419405] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1232 02:49:21.350431 <6>[ 0.427837] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1233 02:49:21.361263 <6>[ 0.435454] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1234 02:49:21.366880 <6>[ 0.449017] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1235 02:49:21.372353 <6>[ 0.451274] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1236 02:49:21.383404 <6>[ 0.457754] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1237 02:49:21.388926 <6>[ 0.464732] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1238 02:49:21.394408 <6>[ 0.471201] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1239 02:49:21.399970 <6>[ 0.478187] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1240 02:49:21.405467 <6>[ 0.484656] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1241 02:49:21.416454 <6>[ 0.491641] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1242 02:49:21.417047 <6>[ 0.499659] ACPI: Interpreter disabled.
1243 02:49:21.422150 <6>[ 0.505112] iommu: Default domain type: Translated
1244 02:49:21.427540 <6>[ 0.507174] iommu: DMA domain TLB invalidation policy: strict mode
1245 02:49:21.433135 <5>[ 0.513856] SCSI subsystem initialized
1246 02:49:21.438555 <6>[ 0.517748] usbcore: registered new interface driver usbfs
1247 02:49:21.444147 <6>[ 0.523232] usbcore: registered new interface driver hub
1248 02:49:21.449864 <6>[ 0.528755] usbcore: registered new device driver usb
1249 02:49:21.455240 <6>[ 0.535007] pps_core: LinuxPPS API ver. 1 registered
1250 02:49:21.466170 <6>[ 0.539168] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1251 02:49:21.467122 <6>[ 0.548487] PTP clock support registered
1252 02:49:21.471798 <6>[ 0.552725] EDAC MC: Ver: 3.0.0
1253 02:49:21.477231 <6>[ 0.556376] scmi_core: SCMI protocol bus registered
1254 02:49:21.482834 <6>[ 0.561976] FPGA manager framework
1255 02:49:21.488327 <6>[ 0.564749] Advanced Linux Sound Architecture Driver Initialized.
1256 02:49:21.489074 <6>[ 0.571707] vgaarb: loaded
1257 02:49:21.493753 <6>[ 0.574257] clocksource: Switched to clocksource arch_sys_counter
1258 02:49:21.499254 <5>[ 0.580399] VFS: Disk quotas dquot_6.6.0
1259 02:49:21.504794 <6>[ 0.584383] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1260 02:49:21.510412 <6>[ 0.591590] pnp: PnP ACPI: disabled
1261 02:49:21.515924 <6>[ 0.599972] NET: Registered PF_INET protocol family
1262 02:49:21.521427 <6>[ 0.600412] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1263 02:49:21.532503 <6>[ 0.610581] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1264 02:49:21.538080 <6>[ 0.616582] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1265 02:49:21.549176 <6>[ 0.624483] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1266 02:49:21.554564 <6>[ 0.632715] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1267 02:49:21.565559 <6>[ 0.640517] TCP: Hash tables configured (established 32768 bind 32768)
1268 02:49:21.571189 <6>[ 0.646987] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 02:49:21.576604 <6>[ 0.653846] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 02:49:21.582220 <6>[ 0.661260] NET: Registered PF_UNIX/PF_LOCAL protocol family
1271 02:49:21.587696 <6>[ 0.667351] RPC: Registered named UNIX socket transport module.
1272 02:49:21.593183 <6>[ 0.673127] RPC: Registered udp transport module.
1273 02:49:21.598814 <6>[ 0.678031] RPC: Registered tcp transport module.
1274 02:49:21.604349 <6>[ 0.682946] RPC: Registered tcp-with-tls transport module.
1275 02:49:21.609950 <6>[ 0.688639] RPC: Registered tcp NFSv4.1 backchannel transport module.
1276 02:49:21.615231 <6>[ 0.695286] PCI: CLS 0 bytes, default 64
1277 02:49:21.621197 <6>[ 0.699605] Unpacking initramfs...
1278 02:49:21.626599 <6>[ 0.708928] kvm [1]: nv: 554 coarse grained trap handlers
1279 02:49:21.632202 <6>[ 0.709227] kvm [1]: IPA Size Limit: 40 bits
1280 02:49:21.633092 <6>[ 0.714915] kvm [1]: vgic interrupt IRQ9
1281 02:49:21.637641 <6>[ 0.717609] kvm [1]: Hyp nVHE mode initialized successfully
1282 02:49:21.643210 <5>[ 0.724920] Initialise system trusted keyrings
1283 02:49:21.648699 <6>[ 0.728224] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1284 02:49:21.654273 <6>[ 0.734967] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1285 02:49:21.659830 <5>[ 0.740961] NFS: Registering the id_resolver key type
1286 02:49:21.665234 <5>[ 0.745999] Key type id_resolver registered
1287 02:49:21.670731 <5>[ 0.750362] Key type id_legacy registered
1288 02:49:21.676294 <6>[ 0.754612] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1289 02:49:21.687378 <6>[ 0.761487] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1290 02:49:21.691262 <6>[ 0.769265] 9p: Installing v9fs 9p2000 file system support
1291 02:49:21.729146 <5>[ 0.815708] Key type asymmetric registered
1292 02:49:21.734534 <5>[ 0.815751] Asymmetric key parser 'x509' registered
1293 02:49:21.745502 <6>[ 0.819607] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1294 02:49:21.746081 <6>[ 0.827132] io scheduler mq-deadline registered
1295 02:49:21.751050 <6>[ 0.831872] io scheduler kyber registered
1296 02:49:21.756564 <6>[ 0.836139] io scheduler bfq registered
1297 02:49:21.762989 <6>[ 0.842009] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1298 02:49:21.779263 <6>[ 0.862242] ledtrig-cpu: registered to indicate activity on CPUs
1299 02:49:21.811898 <6>[ 0.893625] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1300 02:49:21.831575 <6>[ 0.907164] Serial: 8250/16550 driver, 4 ports<6>[ 0.911738] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1301 02:49:21.837206 <6>[ 0.921363] printk: legacy console [ttyAML0] enabled
1302 02:49:21.842757 <6>[ 0.921363] printk: legacy console [ttyAML0] enabled
1303 02:49:21.848273 <6>[ 0.926161] printk: legacy bootconsole [meson0] disabled
1304 02:49:21.853773 <6>[ 0.926161] printk: legacy bootconsole [meson0] disabled
1305 02:49:21.859318 <6>[ 0.939097] msm_serial: driver initialized
1306 02:49:21.864947 <6>[ 0.942130] SuperH (H)SCI(F) driver initialized
1307 02:49:21.865490 <6>[ 0.946630] STM32 USART driver initialized
1308 02:49:21.870391 <5>[ 0.952784] random: crng init done
1309 02:49:21.877390 <6>[ 0.958308] loop: module loaded
1310 02:49:21.877937 <6>[ 0.959575] megasas: 07.727.03.00-rc1
1311 02:49:21.882934 <6>[ 0.968652] tun: Universal TUN/TAP device driver, 1.6
1312 02:49:21.888574 <6>[ 0.969862] thunder_xcv, ver 1.0
1313 02:49:21.894144 <6>[ 0.971830] thunder_bgx, ver 1.0
1314 02:49:21.894712 <6>[ 0.975294] nicpf, ver 1.0
1315 02:49:21.899589 <6>[ 0.979859] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1316 02:49:21.905242 <6>[ 0.985670] hns3: Copyright (c) 2017 Huawei Corporation.
1317 02:49:21.910735 <6>[ 0.991256] hclge is initializing
1318 02:49:21.916275 <6>[ 0.994797] e1000: Intel(R) PRO/1000 Network Driver
1319 02:49:21.921795 <6>[ 0.999877] e1000: Copyright (c) 1999-2006 Intel Corporation.
1320 02:49:21.927365 <6>[ 1.005900] e1000e: Intel(R) PRO/1000 Network Driver
1321 02:49:21.932971 <6>[ 1.011058] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1322 02:49:21.938473 <6>[ 1.017250] igb: Intel(R) Gigabit Ethernet Network Driver
1323 02:49:21.943976 <6>[ 1.022844] igb: Copyright (c) 2007-2014 Intel Corporation.
1324 02:49:21.949521 <6>[ 1.028675] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1325 02:49:21.955211 <6>[ 1.035151] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1326 02:49:21.960671 <6>[ 1.041906] sky2: driver version 1.30
1327 02:49:21.966244 <6>[ 1.046979] VFIO - User Level meta-driver version: 0.3
1328 02:49:21.971728 <6>[ 1.054484] usbcore: registered new interface driver usb-storage
1329 02:49:21.977714 <6>[ 1.060763] i2c_dev: i2c /dev entries driver
1330 02:49:21.990400 <6>[ 1.071718] sdhci: Secure Digital Host Controller Interface driver
1331 02:49:21.990770 <6>[ 1.072524] sdhci: Copyright(c) Pierre Ossman
1332 02:49:22.001743 <6>[ 1.078269] Synopsys Designware Multimedia Card Interface Driver
1333 02:49:22.007160 <6>[ 1.084763] sdhci-pltfm: SDHCI platform and OF driver helper
1334 02:49:22.007589 <6>[ 1.092456] meson-sm: secure-monitor enabled
1335 02:49:22.019973 <6>[ 1.095015] usbcore: registered new interface driver usbhid
1336 02:49:22.020464 <6>[ 1.099585] usbhid: USB HID core driver
1337 02:49:22.027494 <6>[ 1.114332] NET: Registered PF_PACKET protocol family
1338 02:49:22.033119 <6>[ 1.114424] 9pnet: Installing 9P2000 support
1339 02:49:22.040690 <5>[ 1.118577] Key type dns_resolver registered
1340 02:49:22.045566 <6>[ 1.130059] registered taskstats version 1
1341 02:49:22.051063 <5>[ 1.130212] Loading compiled-in X.509 certificates
1342 02:49:22.054640 <6>[ 1.138898] Demotion targets for Node 0: null
1343 02:49:22.095376 <6>[ 1.182159] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1344 02:49:22.100823 <6>[ 1.182204] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1345 02:49:22.111932 <4>[ 1.192382] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1346 02:49:22.117929 <4>[ 1.194984] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1347 02:49:22.123145 <6>[ 1.202563] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1348 02:49:22.128573 <6>[ 1.211850] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1349 02:49:22.139669 <6>[ 1.215250] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1350 02:49:22.150719 <6>[ 1.223237] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1351 02:49:22.156298 <6>[ 1.232762] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1352 02:49:22.161892 <6>[ 1.238988] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1353 02:49:22.167431 <6>[ 1.244610] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1354 02:49:22.172992 <6>[ 1.252497] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1355 02:49:22.178496 <6>[ 1.259789] hub 1-0:1.0: USB hub found
1356 02:49:22.184357 <6>[ 1.263271] hub 1-0:1.0: 2 ports detected
1357 02:49:22.189605 <6>[ 1.269427] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1358 02:49:22.195138 <6>[ 1.276218] hub 2-0:1.0: USB hub found
1359 02:49:22.200232 <6>[ 1.279809] hub 2-0:1.0: 1 port detected
1360 02:49:22.227010 <6>[ 1.310860] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1361 02:49:22.237795 <6>[ 1.321270] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1362 02:49:22.273615 <6>[ 1.356734] Trying to probe devices needed for running init ...
1363 02:49:22.431879 <6>[ 1.514292] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1364 02:49:22.580514 <6>[ 1.661613] mmc0: new ultra high speed SDR104 SDXC card at address e624
1365 02:49:22.581233 <6>[ 1.662925] Freeing initrd memory: 22876K
1366 02:49:22.586147 <6>[ 1.663431] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1367 02:49:22.589948 <6>[ 1.673419] mmcblk0: p1
1368 02:49:22.620920 <6>[ 1.707593] hub 1-1:1.0: USB hub found
1369 02:49:22.626652 <6>[ 1.707908] hub 1-1:1.0: 4 ports detected
1370 02:49:22.687949 <6>[ 1.770396] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1371 02:49:22.733713 <6>[ 1.820252] hub 2-1:1.0: USB hub found
1372 02:49:22.739387 <6>[ 1.821072] hub 2-1:1.0: 4 ports detected
1373 02:49:34.560096 <6>[ 13.646396] clk: Disabling unused clocks
1374 02:49:34.565300 <6>[ 13.646638] PM: genpd: Disabling unused power domains
1375 02:49:34.573553 <6>[ 13.650310] ALSA device list:
1376 02:49:34.574106 <6>[ 13.653450] No soundcards found.
1377 02:49:34.580543 <6>[ 13.667210] Freeing unused kernel memory: 10432K
1378 02:49:34.586870 <6>[ 13.667340] Run /init as init process
1379 02:49:34.593782 Loading, please wait...
1380 02:49:34.627320 Starting systemd-udevd version 252.22-1~deb12u1
1381 02:49:35.041885 <6>[ 14.126277] mc: Linux media interface: v0.10
1382 02:49:35.059804 <6>[ 14.140880] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1383 02:49:35.065387 <6>[ 14.142198] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1384 02:49:35.070344 <6>[ 14.148818] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1385 02:49:35.075819 <6>[ 14.149663] videodev: Linux video capture interface: v2.00
1386 02:49:35.081334 <6>[ 14.154839] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1387 02:49:35.090533 <6>[ 14.167295] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1388 02:49:35.096096 <6>[ 14.174105] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1389 02:49:35.101603 <6>[ 14.179875] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1390 02:49:35.110854 <6>[ 14.187226] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1391 02:49:35.116372 <6>[ 14.194913] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1392 02:49:35.121829 <6>[ 14.200369] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1393 02:49:35.133135 <6>[ 14.207646] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1394 02:49:35.138485 <6>[ 14.214452] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1395 02:49:35.144059 <6>[ 14.220493] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1396 02:49:35.149576 <6>[ 14.226564] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1397 02:49:35.155127 <6>[ 14.239002] panfrost ffe40000.gpu: clock rate = 24000000
1398 02:49:35.165687 <3>[ 14.240485] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1399 02:49:35.178437 <6>[ 14.259683] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1400 02:49:35.184101 <6>[ 14.262179] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1401 02:49:35.200645 <6>[ 14.270508] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1402 02:49:35.206240 <6>[ 14.282604] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1403 02:49:35.211779 <6>[ 14.291186] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1404 02:49:35.217328 <3>[ 14.297705] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1405 02:49:35.230296 <6>[ 14.305221] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1406 02:49:35.235867 <4>[ 14.317247] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1407 02:49:35.246983 <4>[ 14.318246] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1408 02:49:35.252538 <6>[ 14.318395] Registered IR keymap rc-empty
1409 02:49:35.258099 <6>[ 14.318499] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1410 02:49:35.269114 <6>[ 14.318612] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1411 02:49:35.269640 <6>[ 14.322775] rc rc0: sw decoder init
1412 02:49:35.274720 <6>[ 14.323273] usbcore: registered new device driver onboard-usb-dev
1413 02:49:35.285794 <6>[ 14.350371] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1414 02:49:35.291346 <6>[ 14.351476] meson-ir ff808000.ir: receiver initialized
1415 02:49:35.296919 <6>[ 14.364627] meson-vrtc ff8000a8.rtc: registered as rtc0
1416 02:49:35.308014 <6>[ 14.364772] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1417 02:49:35.313555 <6>[ 14.365880] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1418 02:49:35.324589 <3>[ 14.366006] meson-drm ff900000.vpu: DSI transceiver device is disabled
1419 02:49:35.330225 <6>[ 14.390462] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1420 02:49:35.335810 <6>[ 14.399272] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1421 02:49:35.343912 <6>[ 14.412784] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1422 02:49:35.524460 <6>[ 14.512058] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1423 02:49:35.535517 <6>[ 14.587041] Console: switching to colour frame buffer device 128x48
1424 02:49:35.541226 <6>[ 14.617479] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1425 02:49:35.773051 <6>[ 14.859540] hub 1-1:1.0: USB hub found
1426 02:49:35.778179 <6>[ 14.859850] hub 1-1:1.0: 4 ports detected
1427 02:49:35.783728 <6>[ 14.864467] onboard-usb-dev 1-1: USB disconnect, device number 2
1428 02:49:35.912051 Begin: Loading essential drivers ... done.
1429 02:49:35.917611 Begin: Running /scripts/init-premount ... done.
1430 02:49:35.923137 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1431 02:49:35.935621 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1432 02:49:35.936178 Device /sys/class/net/end0 found
1433 02:49:35.936664 done.
1434 02:49:35.945547 Begin: Waiting up to 180 secs for any network device to become available ... done.
1435 02:49:35.990403 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1436 02:49:35.996089 <6>[ 15.075868] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1437 02:49:36.081075 <6>[ 15.162367] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=30)
1438 02:49:36.090155 <6>[ 15.163560] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1439 02:49:36.095633 <6>[ 15.179929] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1440 02:49:36.106647 <6>[ 15.182156] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1441 02:49:36.113626 <6>[ 15.189523] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1442 02:49:36.231808 <6>[ 15.314305] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1443 02:49:36.413130 <6>[ 15.499705] hub 1-1:1.0: USB hub found
1444 02:49:36.418757 <6>[ 15.500042] hub 1-1:1.0: 4 ports detected
1445 02:49:37.814369 IP-Config: no response after 2 secs - giving up
1446 02:49:37.891781 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1447 02:49:39.065691 <6>[ 18.146413] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1448 02:49:39.823458 <4>[ 18.910278] rc rc0: two consecutive events of type space
1449 02:49:41.093239 IP-Config: no response after 3 secs - giving up
1450 02:49:41.139785 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1451 02:49:44.113895 IP-Config: end0 guessed broadcast address 192.168.6.255
1452 02:49:44.119246 IP-Config: end0 complete (dhcp from 192.168.6.1):
1453 02:49:44.124727 address: 192.168.6.33 broadcast: 192.168.6.255 netmask: 255.255.255.0
1454 02:49:44.133899 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1455 02:49:44.139334 rootserver: 192.168.6.1 rootpath:
1456 02:49:44.139627 filename :
1457 02:49:44.214833 done.
1458 02:49:44.224740 Begin: Running /scripts/nfs-bottom ... done.
1459 02:49:44.234254 Begin: Running /scripts/init-bottom ... done.
1460 02:49:44.566870 <30>[ 23.649254] systemd[1]: System time before build time, advancing clock.
1461 02:49:44.625716 <6>[ 23.712442] NET: Registered PF_INET6 protocol family
1462 02:49:44.631309 <6>[ 23.714469] Segment Routing with IPv6
1463 02:49:44.636408 <6>[ 23.715970] In-situ OAM (IOAM) with IPv6
1464 02:49:44.732612 <30>[ 23.788215] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1465 02:49:44.736238 <30>[ 23.816411] systemd[1]: Detected architecture arm64.
1466 02:49:44.736524
1467 02:49:44.743416 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1468 02:49:44.743695
1469 02:49:44.753516 <30>[ 23.836531] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1470 02:49:45.459354 <30>[ 24.541027] systemd[1]: Queued start job for default target graphical.target.
1471 02:49:45.479302 <30>[ 24.560620] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1472 02:49:45.486842 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1473 02:49:45.497943 <30>[ 24.579249] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1474 02:49:45.506449 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1475 02:49:45.517982 <30>[ 24.599306] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1476 02:49:45.527072 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1477 02:49:45.538082 <30>[ 24.619026] systemd[1]: Created slice user.slice - User and Session Slice.
1478 02:49:45.544418 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1479 02:49:45.555690 <30>[ 24.634533] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1480 02:49:45.566916 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1481 02:49:45.578034 <30>[ 24.654465] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1482 02:49:45.584585 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1483 02:49:45.606745 <30>[ 24.674435] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1484 02:49:45.612321 <30>[ 24.688496] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1485 02:49:45.620006 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1486 02:49:45.631093 <30>[ 24.710350] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1487 02:49:45.637231 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1488 02:49:45.653066 <30>[ 24.734377] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1489 02:49:45.666727 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1490 02:49:45.672351 <30>[ 24.754381] systemd[1]: Reached target paths.target - Path Units.
1491 02:49:45.680713 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1492 02:49:45.686345 <30>[ 24.770363] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1493 02:49:45.697950 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1494 02:49:45.703526 <30>[ 24.786351] systemd[1]: Reached target slices.target - Slice Units.
1495 02:49:45.711670 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1496 02:49:45.717334 <30>[ 24.802368] systemd[1]: Reached target swap.target - Swaps.
1497 02:49:45.725070 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1498 02:49:45.737076 <30>[ 24.818374] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1499 02:49:45.745871 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1500 02:49:45.761180 <30>[ 24.842540] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1501 02:49:45.770614 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1502 02:49:45.782360 <30>[ 24.863731] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1503 02:49:45.791117 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1504 02:49:45.805864 <30>[ 24.887241] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1505 02:49:45.819020 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1506 02:49:45.824546 <30>[ 24.906692] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1507 02:49:45.831413 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1508 02:49:45.842436 <30>[ 24.923315] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1509 02:49:45.848047 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1510 02:49:45.862779 <30>[ 24.944174] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1511 02:49:45.868331 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1512 02:49:45.881315 <30>[ 24.962604] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1513 02:49:45.889676 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1514 02:49:45.929183 <30>[ 25.010471] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1515 02:49:45.935842 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1516 02:49:45.947616 <30>[ 25.028892] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1517 02:49:45.955062 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1518 02:49:45.967412 <30>[ 25.048496] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1519 02:49:45.974706 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1520 02:49:45.996547 <30>[ 25.070702] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1521 02:49:46.025436 <30>[ 25.106666] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1522 02:49:46.033964 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1523 02:49:46.053336 <30>[ 25.134503] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1524 02:49:46.061234 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1525 02:49:46.109527 <30>[ 25.190619] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1526 02:49:46.116964 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1527 02:49:46.128713 <30>[ 25.210059] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1528 02:49:46.134437 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1529 02:49:46.144693 <6>[ 25.224888] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1530 02:49:46.155922 <30>[ 25.237261] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1531 02:49:46.164236 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1532 02:49:46.175962 <30>[ 25.257257] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1533 02:49:46.183293 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1534 02:49:46.199685 <30>[ 25.281033] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1535 02:49:46.205254 Starting [0;1;39mmodprob<6>[ 25.288774] fuse: init (API version 7.41)
1536 02:49:46.209195 e@loop.ser…e[0m - Load Kernel Module loop...
1537 02:49:46.230580 <30>[ 25.311921] systemd[1]: Starting systemd-journald.service - Journal Service...
1538 02:49:46.236927 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1539 02:49:46.260904 <30>[ 25.342246] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1540 02:49:46.268450 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1541 02:49:46.281382 <30>[ 25.362704] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1542 02:49:46.290686 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1543 02:49:46.303019 <30>[ 25.384439] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1544 02:49:46.311831 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1545 02:49:46.323215 <30>[ 25.404590] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1546 02:49:46.331296 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1547 02:49:46.343538 <30>[ 25.424878] systemd[1]: Started systemd-journald.service - Journal Service.
1548 02:49:46.350349 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1549 02:49:46.362280 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1550 02:49:46.377723 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1551 02:49:46.389599 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1552 02:49:46.401872 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1553 02:49:46.414216 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1554 02:49:46.426214 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1555 02:49:46.437854 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1556 02:49:46.450244 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1557 02:49:46.462009 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1558 02:49:46.478080 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1559 02:49:46.489913 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1560 02:49:46.505987 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1561 02:49:46.522108 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1562 02:49:46.538489 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1563 02:49:46.580556 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1564 02:49:46.587103 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1565 02:49:46.598929 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1566 02:49:46.610580 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1567 02:49:46.629518 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1568 02:49:46.644208 <46>[ 25.725491] systemd-journald[229]: Received client request to flush runtime journal.
1569 02:49:46.655295 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1570 02:49:46.673557 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1571 02:49:46.680023 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1572 02:49:46.701975 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1573 02:49:46.718209 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1574 02:49:46.734026 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1575 02:49:46.790008 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1576 02:49:46.828953 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1577 02:49:46.917624 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1578 02:49:46.937138 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1579 02:49:46.945638 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1580 02:49:46.960690 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1581 02:49:47.004919 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1582 02:49:47.023328 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1583 02:49:47.194721 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1584 02:49:47.249129 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1585 02:49:47.302212 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1586 02:49:47.338878 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1587 02:49:47.396880 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1588 02:49:47.407963 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1589 02:49:47.415232 <5>[ 26.493883] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1590 02:49:47.460638 <5>[ 26.541964] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1591 02:49:47.466143 <5>[ 26.542863] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1592 02:49:47.475066 <4>[ 26.550761] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1593 02:49:47.480608 <6>[ 26.558643] cfg80211: failed to load regulatory.db
1594 02:49:47.488083 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1595 02:49:47.537100 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1596 02:49:47.562754 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1597 02:49:47.569673 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1598 02:49:47.605180 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1599 02:49:47.613174 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1600 02:49:47.625542 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1601 02:49:47.644656 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1602 02:49:47.666909 <46>[ 26.737081] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1603 02:49:47.678103 <46>[ 26.749531] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1604 02:49:47.691682 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1605 02:49:47.699615 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1606 02:49:47.713422 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1607 02:49:47.782040 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1608 02:49:47.809901 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1609 02:49:47.824107 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1610 02:49:47.837613 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1611 02:49:47.856299 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1612 02:49:47.869922 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1613 02:49:47.880208 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1614 02:49:47.912188 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1615 02:49:47.938718 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1616 02:49:47.959767 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1617 02:49:47.970923 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1618 02:49:48.002836 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1619 02:49:48.018502 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1620 02:49:48.030468 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1621 02:49:48.045510 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1622 02:49:48.052044 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1623 02:49:48.064038 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1624 02:49:48.124541 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1625 02:49:48.137072 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1626 02:49:48.144242 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1627 02:49:48.153738 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1628 02:49:48.169773 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1629 02:49:48.181214 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1630 02:49:48.217290 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1631 02:49:48.262331 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1632 02:49:48.338608
1633 02:49:48.339029 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1634 02:49:48.339254
1635 02:49:48.345846 debian-bookworm-arm64 login: root (automatic login)
1636 02:49:48.346183
1637 02:49:48.479305 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Thu Oct 10 01:19:59 UTC 2024 aarch64
1638 02:49:48.479727
1639 02:49:48.484823 The programs included with the Debian GNU/Linux system are free software;
1640 02:49:48.490373 the exact distribution terms for each program are described in the
1641 02:49:48.495881 individual files in /usr/share/doc/*/copyright.
1642 02:49:48.496237
1643 02:49:48.501425 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1644 02:49:48.504700 permitted by applicable law.
1645 02:49:49.245032 Matched prompt #10: / #
1647 02:49:49.245961 Setting prompt string to ['/ #']
1648 02:49:49.246286 end: 2.4.4.1 login-action (duration 00:00:29) [common]
1650 02:49:49.247035 end: 2.4.4 auto-login-action (duration 00:00:29) [common]
1651 02:49:49.247334 start: 2.4.5 expect-shell-connection (timeout 00:03:17) [common]
1652 02:49:49.247579 Setting prompt string to ['/ #']
1653 02:49:49.247798 Forcing a shell prompt, looking for ['/ #']
1655 02:49:49.298402 / #
1656 02:49:49.298882 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1657 02:49:49.299157 Waiting using forced prompt support (timeout 00:02:30)
1658 02:49:49.304772
1659 02:49:49.305345 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1660 02:49:49.305679 start: 2.4.6 export-device-env (timeout 00:03:17) [common]
1661 02:49:49.305945 Sending with 10 millisecond of delay
1663 02:49:54.296092 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3'
1664 02:49:54.307000 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/830727/extract-nfsrootfs-fa4ffkg3'
1665 02:49:54.308178 Sending with 10 millisecond of delay
1667 02:49:56.409501 / # export NFS_SERVER_IP='192.168.6.2'
1668 02:49:56.420471 export NFS_SERVER_IP='192.168.6.2'
1669 02:49:56.421366 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1670 02:49:56.422001 end: 2.4 uboot-commands (duration 00:01:51) [common]
1671 02:49:56.422600 end: 2 uboot-action (duration 00:01:51) [common]
1672 02:49:56.423185 start: 3 lava-test-retry (timeout 00:06:50) [common]
1673 02:49:56.423785 start: 3.1 lava-test-shell (timeout 00:06:50) [common]
1674 02:49:56.424335 Using namespace: common
1676 02:49:56.525585 / # #
1677 02:49:56.526349 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1678 02:49:56.531255 #
1679 02:49:56.532056 Using /lava-830727
1681 02:49:56.633262 / # export SHELL=/bin/bash
1682 02:49:56.639008 export SHELL=/bin/bash
1684 02:49:56.740546 / # . /lava-830727/environment
1685 02:49:56.745592 . /lava-830727/environment
1687 02:49:56.850225 / # /lava-830727/bin/lava-test-runner /lava-830727/0
1688 02:49:56.851058 Test shell timeout: 10s (minimum of the action and connection timeout)
1689 02:49:56.854214 /lava-830727/bin/lava-test-runner /lava-830727/0
1690 02:49:57.047550 + export TESTRUN_ID=0_timesync-off
1691 02:49:57.055462 + TESTRUN_ID=0_timesync-off
1692 02:49:57.056007 + cd /lava-830727/0/tests/0_timesync-off
1693 02:49:57.056486 ++ cat uuid
1694 02:49:57.064451 + UUID=830727_1.6.2.4.1
1695 02:49:57.064947 + set +x
1696 02:49:57.073173 <LAVA_SIGNAL_STARTRUN 0_timesync-off 830727_1.6.2.4.1>
1697 02:49:57.073665 + systemctl stop systemd-timesyncd
1698 02:49:57.074416 Received signal: <STARTRUN> 0_timesync-off 830727_1.6.2.4.1
1699 02:49:57.074895 Starting test lava.0_timesync-off (830727_1.6.2.4.1)
1700 02:49:57.075463 Skipping test definition patterns.
1701 02:49:57.120658 + set +x
1702 02:49:57.121199 <LAVA_SIGNAL_ENDRUN 0_timesync-off 830727_1.6.2.4.1>
1703 02:49:57.121915 Received signal: <ENDRUN> 0_timesync-off 830727_1.6.2.4.1
1704 02:49:57.122445 Ending use of test pattern.
1705 02:49:57.122898 Ending test lava.0_timesync-off (830727_1.6.2.4.1), duration 0.05
1707 02:49:57.199401 + export TESTRUN_ID=1_kselftest-alsa
1708 02:49:57.207881 + TESTRUN_ID=1_kselftest-alsa
1709 02:49:57.208437 + cd /lava-830727/0/tests/1_kselftest-alsa
1710 02:49:57.208896 ++ cat uuid
1711 02:49:57.214345 + UUID=830727_1.6.2.4.5
1712 02:49:57.214821 + set +x
1713 02:49:57.219902 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 830727_1.6.2.4.5>
1714 02:49:57.220474 + cd ./automated/linux/kselftest/
1715 02:49:57.221231 Received signal: <STARTRUN> 1_kselftest-alsa 830727_1.6.2.4.5
1716 02:49:57.221715 Starting test lava.1_kselftest-alsa (830727_1.6.2.4.5)
1717 02:49:57.222256 Skipping test definition patterns.
1718 02:49:57.248756 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1719 02:49:57.295446 INFO: install_deps skipped
1720 02:49:57.419438 --2024-10-10 02:49:57-- http://storage.kernelci.org/mainline/master/v6.12-rc2-74-gd3d1556696c1a/arm64/defconfig/gcc-12/kselftest.tar.xz
1721 02:49:57.443161 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1722 02:49:57.587090 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1723 02:49:57.728604 HTTP request sent, awaiting response... 200 OK
1724 02:49:57.729255 Length: 7108780 (6.8M) [application/octet-stream]
1725 02:49:57.734113 Saving to: 'kselftest_armhf.tar.gz'
1726 02:49:57.734599
1727 02:49:59.195716
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 167KB/s
kselftest_armhf.tar 3%[ ] 218.67K 384KB/s
kselftest_armhf.tar 12%[=> ] 893.67K 1.02MB/s
kselftest_armhf.tar 51%[=========> ] 3.51M 3.09MB/s
kselftest_armhf.tar 93%[=================> ] 6.33M 4.35MB/s
kselftest_armhf.tar 100%[===================>] 6.78M 4.65MB/s in 1.5s
1728 02:49:59.196189
1729 02:49:59.301881 2024-10-10 02:49:59 (4.65 MB/s) - 'kselftest_armhf.tar.gz' saved [7108780/7108780]
1730 02:49:59.302905
1731 02:50:08.347383 skiplist:
1732 02:50:08.348079 ========================================
1733 02:50:08.352740 ========================================
1734 02:50:08.395303 alsa:mixer-test
1735 02:50:08.395925 alsa:pcm-test
1736 02:50:08.396399 alsa:test-pcmtest-driver
1737 02:50:08.399084 alsa:utimer-test
1738 02:50:08.414162 ============== Tests to run ===============
1739 02:50:08.414742 alsa:mixer-test
1740 02:50:08.419497 alsa:pcm-test
1741 02:50:08.420208 alsa:test-pcmtest-driver
1742 02:50:08.420653 alsa:utimer-test
1743 02:50:08.426722 ===========End Tests to run ===============
1744 02:50:08.427223 shardfile-alsa pass
1745 02:50:08.545229 <12>[ 47.629802] kselftest: Running tests in alsa
1746 02:50:08.552431 TAP version 13
1747 02:50:08.562329 1..4
1748 02:50:08.583221 # timeout set to 45
1749 02:50:08.583778 # selftests: alsa: mixer-test
1750 02:50:08.746930 # TAP version 13
1751 02:50:08.747560 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1752 02:50:08.752145 # 1..427
1753 02:50:08.752602 # ok 1 get_value.LCALTA.60
1754 02:50:08.753017 # # LCALTA.60 TDMOUT_A SRC SEL
1755 02:50:08.757697 # ok 2 name.LCALTA.60
1756 02:50:08.758135 # ok 3 write_default.LCALTA.60
1757 02:50:08.763182 # ok 4 write_valid.LCALTA.60
1758 02:50:08.763631 # ok 5 write_invalid.LCALTA.60
1759 02:50:08.768695 # ok 6 event_missing.LCALTA.60
1760 02:50:08.769135 # ok 7 event_spurious.LCALTA.60
1761 02:50:08.774399 # ok 8 get_value.LCALTA.59
1762 02:50:08.774833 # # LCALTA.59 TDMOUT_B SRC SEL
1763 02:50:08.779906 # ok 9 name.LCALTA.59
1764 02:50:08.780374 # ok 10 write_default.LCALTA.59
1765 02:50:08.785441 # ok 11 write_valid.LCALTA.59
1766 02:50:08.785879 # ok 12 write_invalid.LCALTA.59
1767 02:50:08.790895 # ok 13 event_missing.LCALTA.59
1768 02:50:08.791338 # ok 14 event_spurious.LCALTA.59
1769 02:50:08.796436 # ok 15 get_value.LCALTA.58
1770 02:50:08.796933 # # LCALTA.58 TDMOUT_C SRC SEL
1771 02:50:08.802008 # ok 16 name.LCALTA.58
1772 02:50:08.802447 # ok 17 write_default.LCALTA.58
1773 02:50:08.807690 # ok 18 write_valid.LCALTA.58
1774 02:50:08.808146 # ok 19 write_invalid.LCALTA.58
1775 02:50:08.813121 # ok 20 event_missing.LCALTA.58
1776 02:50:08.813556 # ok 21 event_spurious.LCALTA.58
1777 02:50:08.818647 # ok 22 get_value.LCALTA.57
1778 02:50:08.819077 # # LCALTA.57 TDMIN_A SRC SEL
1779 02:50:08.819481 # ok 23 name.LCALTA.57
1780 02:50:08.824154 # ok 24 write_default.LCALTA.57
1781 02:50:08.824584 # ok 25 write_valid.LCALTA.57
1782 02:50:08.829683 # ok 26 write_invalid.LCALTA.57
1783 02:50:08.830106 # ok 27 event_missing.LCALTA.57
1784 02:50:08.835228 # ok 28 event_spurious.LCALTA.57
1785 02:50:08.835659 # ok 29 get_value.LCALTA.56
1786 02:50:08.840782 # # LCALTA.56 TDMIN_B SRC SEL
1787 02:50:08.841214 # ok 30 name.LCALTA.56
1788 02:50:08.846307 # ok 31 write_default.LCALTA.56
1789 02:50:08.857477 # <3>[ 47.930618] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1790 02:50:08.858042 ok 32 write_valid.LCALTA.56
1791 02:50:08.862947 # ok 33 write_invalid.LCALTA.56
1792 02:50:08.863386 # ok 34 event_missing.LCALTA.56
1793 02:50:08.868591 # ok 35 event_spurious.LCALTA.56
1794 02:50:08.869030 # ok 36 get_value.LCALTA.55
1795 02:50:08.874071 # # LCALTA.55 TDMIN_C SRC SEL
1796 02:50:08.874501 # ok 37 name.LCALTA.55
1797 02:50:08.879583 # ok 38 write_default.LCALTA.55
1798 02:50:08.880032 # ok 39 write_valid.LCALTA.55
1799 02:50:08.885122 # ok 40 write_invalid.LCALTA.55
1800 02:50:08.885544 # ok 41 event_missing.LCALTA.55
1801 02:50:08.890688 # ok 42 event_spurious.LCALTA.55
1802 02:50:08.891218 # ok 43 get_value.LCALTA.54
1803 02:50:08.896228 # # LCALTA.54 ACODEC Left DAC Sel
1804 02:50:08.896767 # ok 44 name.LCALTA.54
1805 02:50:08.901749 # ok 45 write_default.LCALTA.54
1806 02:50:08.902468 # ok 46 write_valid.LCALTA.54
1807 02:50:08.907372 # ok 47 write_invalid.LCALTA.54
1808 02:50:08.907914 # ok 48 event_missing.LCALTA.54
1809 02:50:08.912843 # ok 49 event_spurious.LCALTA.54
1810 02:50:08.913351 # ok 50 get_value.LCALTA.53
1811 02:50:08.918397 # # LCALTA.53 ACODEC Right DAC Sel
1812 02:50:08.918921 # ok 51 name.LCALTA.53
1813 02:50:08.923954 # ok 52 write_default.LCALTA.53
1814 02:50:08.924524 # ok 53 write_valid.LCALTA.53
1815 02:50:08.929525 # ok 54 write_invalid.LCALTA.53
1816 02:50:08.929954 # ok 55 event_missing.LCALTA.53
1817 02:50:08.934977 # ok 56 event_spurious.LCALTA.53
1818 02:50:08.935392 # ok 57 get_value.LCALTA.52
1819 02:50:08.940539 # # LCALTA.52 TOACODEC OUT EN Switch
1820 02:50:08.941027 # ok 58 name.LCALTA.52
1821 02:50:08.946085 # ok 59 write_default.LCALTA.52
1822 02:50:08.946563 # ok 60 write_valid.LCALTA.52
1823 02:50:08.951660 # ok 61 write_invalid.LCALTA.52
1824 02:50:08.952138 # ok 62 event_missing.LCALTA.52
1825 02:50:08.957157 # ok 63 event_spurious.LCALTA.52
1826 02:50:08.957576 # ok 64 get_value.LCALTA.51
1827 02:50:08.962720 # # LCALTA.51 TOACODEC SRC
1828 02:50:08.963136 # ok 65 name.LCALTA.51
1829 02:50:08.968305 # ok 66 write_default.LCALTA.51
1830 02:50:08.968717 # ok 67 write_valid.LCALTA.51
1831 02:50:08.973831 # ok 68 write_invalid.LCALTA.51
1832 02:50:08.974319 # ok 69 event_missing.LCALTA.51
1833 02:50:08.979381 # ok 70 event_spurious.LCALTA.51
1834 02:50:08.979827 # ok 71 get_value.LCALTA.50
1835 02:50:08.984906 # # LCALTA.50 TOHDMITX SPDIF SRC
1836 02:50:08.985362 # ok 72 name.LCALTA.50
1837 02:50:08.985757 # ok 73 write_default.LCALTA.50
1838 02:50:08.990536 # ok 74 write_valid.LCALTA.50
1839 02:50:08.990983 # ok 75 write_invalid.LCALTA.50
1840 02:50:08.996016 # ok 76 event_missing.LCALTA.50
1841 02:50:09.001557 # ok 77 event_spurious.LCALTA.50
1842 02:50:09.002004 # ok 78 get_value.LCALTA.49
1843 02:50:09.002412 # # LCALTA.49 TOHDMITX Switch
1844 02:50:09.007156 # ok 79 name.LCALTA.49
1845 02:50:09.007613 # ok 80 write_default.LCALTA.49
1846 02:50:09.012648 # ok 81 write_valid.LCALTA.49
1847 02:50:09.013103 # ok 82 write_invalid.LCALTA.49
1848 02:50:09.018258 # ok 83 event_missing.LCALTA.49
1849 02:50:09.018810 # ok 84 event_spurious.LCALTA.49
1850 02:50:09.023806 # ok 85 get_value.LCALTA.48
1851 02:50:09.024333 # # LCALTA.48 TOHDMITX I2S SRC
1852 02:50:09.029343 # ok 86 name.LCALTA.48
1853 02:50:09.029779 # ok 87 write_default.LCALTA.48
1854 02:50:09.034863 # ok 88 write_valid.LCALTA.48
1855 02:50:09.035285 # ok 89 write_invalid.LCALTA.48
1856 02:50:09.040551 # ok 90 event_missing.LCALTA.48
1857 02:50:09.040969 # ok 91 event_spurious.LCALTA.48
1858 02:50:09.045993 # ok 92 get_value.LCALTA.47
1859 02:50:09.046486 # # LCALTA.47 TODDR_C SRC SEL
1860 02:50:09.051588 # ok 93 name.LCALTA.47
1861 02:50:09.052037 # ok 94 write_default.LCALTA.47
1862 02:50:09.057082 # ok 95 write_valid.LCALTA.47
1863 02:50:09.057500 # ok 96 write_invalid.LCALTA.47
1864 02:50:09.062612 # ok 97 event_missing.LCALTA.47
1865 02:50:09.063025 # ok 98 event_spurious.LCALTA.47
1866 02:50:09.068185 # ok 99 get_value.LCALTA.46
1867 02:50:09.068613 # # LCALTA.46 TODDR_B SRC SEL
1868 02:50:09.069006 # ok 100 name.LCALTA.46
1869 02:50:09.073693 # ok 101 write_default.LCALTA.46
1870 02:50:09.079353 # ok 102 write_valid.LCALTA.46
1871 02:50:09.079793 # ok 103 write_invalid.LCALTA.46
1872 02:50:09.084817 # ok 104 event_missing.LCALTA.46
1873 02:50:09.085244 # ok 105 event_spurious.LCALTA.46
1874 02:50:09.090330 # ok 106 get_value.LCALTA.45
1875 02:50:09.090751 # # LCALTA.45 TODDR_A SRC SEL
1876 02:50:09.091142 # ok 107 name.LCALTA.45
1877 02:50:09.095880 # ok 108 write_default.LCALTA.45
1878 02:50:09.101552 # ok 109 write_valid.LCALTA.45
1879 02:50:09.101974 # ok 110 write_invalid.LCALTA.45
1880 02:50:09.107063 # ok 111 event_missing.LCALTA.45
1881 02:50:09.107481 # ok 112 event_spurious.LCALTA.45
1882 02:50:09.112602 # ok 113 get_value.LCALTA.44
1883 02:50:09.113020 # # LCALTA.44 FRDDR_C SINK 3 SEL
1884 02:50:09.118096 # ok 114 name.LCALTA.44
1885 02:50:09.118519 # ok 115 write_default.LCALTA.44
1886 02:50:09.123631 # ok 116 write_valid.LCALTA.44
1887 02:50:09.124079 # ok 117 write_invalid.LCALTA.44
1888 02:50:09.129178 # ok 118 event_missing.LCALTA.44
1889 02:50:09.129599 # ok 119 event_spurious.LCALTA.44
1890 02:50:09.134717 # ok 120 get_value.LCALTA.43
1891 02:50:09.135134 # # LCALTA.43 FRDDR_C SINK 2 SEL
1892 02:50:09.140353 # ok 121 name.LCALTA.43
1893 02:50:09.140768 # ok 122 write_default.LCALTA.43
1894 02:50:09.145812 # ok 123 write_valid.LCALTA.43
1895 02:50:09.146230 # ok 124 write_invalid.LCALTA.43
1896 02:50:09.151344 # ok 125 event_missing.LCALTA.43
1897 02:50:09.151759 # ok 126 event_spurious.LCALTA.43
1898 02:50:09.156914 # ok 127 get_value.LCALTA.42
1899 02:50:09.157331 # # LCALTA.42 FRDDR_C SINK 1 SEL
1900 02:50:09.162609 # ok 128 name.LCALTA.42
1901 02:50:09.163022 # ok 129 write_default.LCALTA.42
1902 02:50:09.168027 # ok 130 write_valid.LCALTA.42
1903 02:50:09.168444 # ok 131 write_invalid.LCALTA.42
1904 02:50:09.173607 # ok 132 event_missing.LCALTA.42
1905 02:50:09.174020 # ok 133 event_spurious.LCALTA.42
1906 02:50:09.179093 # ok 134 get_value.LCALTA.41
1907 02:50:09.179519 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1908 02:50:09.184647 # ok 135 name.LCALTA.41
1909 02:50:09.185066 # ok 136 write_default.LCALTA.41
1910 02:50:09.190196 # ok 137 write_valid.LCALTA.41
1911 02:50:09.190618 # ok 138 write_invalid.LCALTA.41
1912 02:50:09.195703 # ok 139 event_missing.LCALTA.41
1913 02:50:09.196153 # ok 140 event_spurious.LCALTA.41
1914 02:50:09.201346 # ok 141 get_value.LCALTA.40
1915 02:50:09.201764 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1916 02:50:09.206896 # ok 142 name.LCALTA.40
1917 02:50:09.207320 # ok 143 write_default.LCALTA.40
1918 02:50:09.212390 # ok 144 write_valid.LCALTA.40
1919 02:50:09.212803 # ok 145 write_invalid.LCALTA.40
1920 02:50:09.217917 # ok 146 event_missing.LCALTA.40
1921 02:50:09.218345 # ok 147 event_spurious.LCALTA.40
1922 02:50:09.223636 # ok 148 get_value.LCALTA.39
1923 02:50:09.229232 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1924 02:50:09.229698 # ok 149 name.LCALTA.39
1925 02:50:09.230094 # ok 150 write_default.LCALTA.39
1926 02:50:09.234764 # ok 151 write_valid.LCALTA.39
1927 02:50:09.235214 # ok 152 write_invalid.LCALTA.39
1928 02:50:09.240268 # ok 153 event_missing.LCALTA.39
1929 02:50:09.245891 # ok 154 event_spurious.LCALTA.39
1930 02:50:09.246381 # ok 155 get_value.LCALTA.38
1931 02:50:09.251676 # # LCALTA.38 FRDDR_B SINK 3 SEL
1932 02:50:09.252155 # ok 156 name.LCALTA.38
1933 02:50:09.252553 # ok 157 write_default.LCALTA.38
1934 02:50:09.257410 # ok 158 write_valid.LCALTA.38
1935 02:50:09.257970 # ok 159 write_invalid.LCALTA.38
1936 02:50:09.265565 # ok 160 event_missing.LCALTA.38
1937 02:50:09.269854 # ok 161 event_spurious.LCALTA.38
1938 02:50:09.270695 # ok 162 get_value.LCALTA.37
1939 02:50:09.273695 # # LCALTA.37 FRDDR_B SINK 2 SEL
1940 02:50:09.274248 # ok 163 name.LCALTA.37
1941 02:50:09.274594 # ok 164 write_default.LCALTA.37
1942 02:50:09.279275 # ok 165 write_valid.LCALTA.37
1943 02:50:09.284744 # ok 166 write_invalid.LCALTA.37
1944 02:50:09.285170 # ok 167 event_missing.LCALTA.37
1945 02:50:09.290152 # ok 168 event_spurious.LCALTA.37
1946 02:50:09.290572 # ok 169 get_value.LCALTA.36
1947 02:50:09.295783 # # LCALTA.36 FRDDR_B SINK 1 SEL
1948 02:50:09.296187 # ok 170 name.LCALTA.36
1949 02:50:09.301220 # ok 171 write_default.LCALTA.36
1950 02:50:09.301660 # ok 172 write_valid.LCALTA.36
1951 02:50:09.306751 # ok 173 write_invalid.LCALTA.36
1952 02:50:09.307082 # ok 174 event_missing.LCALTA.36
1953 02:50:09.312303 # ok 175 event_spurious.LCALTA.36
1954 02:50:09.312849 # ok 176 get_value.LCALTA.35
1955 02:50:09.317868 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1956 02:50:09.318394 # ok 177 name.LCALTA.35
1957 02:50:09.323456 # ok 178 write_default.LCALTA.35
1958 02:50:09.324008 # ok 179 write_valid.LCALTA.35
1959 02:50:09.328924 # ok 180 write_invalid.LCALTA.35
1960 02:50:09.329444 # ok 181 event_missing.LCALTA.35
1961 02:50:09.334468 # ok 182 event_spurious.LCALTA.35
1962 02:50:09.335003 # ok 183 get_value.LCALTA.34
1963 02:50:09.340414 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1964 02:50:09.340782 # ok 184 name.LCALTA.34
1965 02:50:09.345705 # ok 185 write_default.LCALTA.34
1966 02:50:09.346049 # ok 186 write_valid.LCALTA.34
1967 02:50:09.351073 # ok 187 write_invalid.LCALTA.34
1968 02:50:09.351525 # ok 188 event_missing.LCALTA.34
1969 02:50:09.356665 # ok 189 event_spurious.LCALTA.34
1970 02:50:09.357014 # ok 190 get_value.LCALTA.33
1971 02:50:09.362132 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1972 02:50:09.362451 # ok 191 name.LCALTA.33
1973 02:50:09.367684 # ok 192 write_default.LCALTA.33
1974 02:50:09.368017 # ok 193 write_valid.LCALTA.33
1975 02:50:09.373265 # ok 194 write_invalid.LCALTA.33
1976 02:50:09.373602 # ok 195 event_missing.LCALTA.33
1977 02:50:09.378861 # ok 196 event_spurious.LCALTA.33
1978 02:50:09.379268 # ok 197 get_value.LCALTA.32
1979 02:50:09.384444 # # LCALTA.32 FRDDR_A SINK 3 SEL
1980 02:50:09.384975 # ok 198 name.LCALTA.32
1981 02:50:09.389879 # ok 199 write_default.LCALTA.32
1982 02:50:09.390194 # ok 200 write_valid.LCALTA.32
1983 02:50:09.395401 # ok 201 write_invalid.LCALTA.32
1984 02:50:09.395699 # ok 202 event_missing.LCALTA.32
1985 02:50:09.400976 # ok 203 event_spurious.LCALTA.32
1986 02:50:09.401287 # ok 204 get_value.LCALTA.31
1987 02:50:09.406755 # # LCALTA.31 FRDDR_A SINK 2 SEL
1988 02:50:09.407255 # ok 205 name.LCALTA.31
1989 02:50:09.412156 # ok 206 write_default.LCALTA.31
1990 02:50:09.412677 # ok 207 write_valid.LCALTA.31
1991 02:50:09.417681 # ok 208 write_invalid.LCALTA.31
1992 02:50:09.418011 # ok 209 event_missing.LCALTA.31
1993 02:50:09.423257 # ok 210 event_spurious.LCALTA.31
1994 02:50:09.423868 # ok 211 get_value.LCALTA.30
1995 02:50:09.428814 # # LCALTA.30 FRDDR_A SINK 1 SEL
1996 02:50:09.429333 # ok 212 name.LCALTA.30
1997 02:50:09.434322 # ok 213 write_default.LCALTA.30
1998 02:50:09.434812 # ok 214 write_valid.LCALTA.30
1999 02:50:09.439848 # ok 215 write_invalid.LCALTA.30
2000 02:50:09.445502 # ok 216 event_missing.LCALTA.30
2001 02:50:09.445994 # ok 217 event_spurious.LCALTA.30
2002 02:50:09.451012 # ok 218 get_value.LCALTA.29
2003 02:50:09.451521 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2004 02:50:09.456508 # ok 219 name.LCALTA.29
2005 02:50:09.456989 # ok 220 write_default.LCALTA.29
2006 02:50:09.462053 # ok 221 write_valid.LCALTA.29
2007 02:50:09.462546 # ok 222 write_invalid.LCALTA.29
2008 02:50:09.467756 # ok 223 event_missing.LCALTA.29
2009 02:50:09.468276 # ok 224 event_spurious.LCALTA.29
2010 02:50:09.473163 # ok 225 get_value.LCALTA.28
2011 02:50:09.473643 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2012 02:50:09.478711 # ok 226 name.LCALTA.28
2013 02:50:09.479187 # ok 227 write_default.LCALTA.28
2014 02:50:09.484286 # ok 228 write_valid.LCALTA.28
2015 02:50:09.484775 # ok 229 write_invalid.LCALTA.28
2016 02:50:09.489806 # ok 230 event_missing.LCALTA.28
2017 02:50:09.490281 # ok 231 event_spurious.LCALTA.28
2018 02:50:09.495352 # ok 232 get_value.LCALTA.27
2019 02:50:09.495831 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2020 02:50:09.500894 # ok 233 name.LCALTA.27
2021 02:50:09.501371 # ok 234 write_default.LCALTA.27
2022 02:50:09.506502 # ok 235 write_valid.LCALTA.27
2023 02:50:09.506989 # ok 236 write_invalid.LCALTA.27
2024 02:50:09.512082 # ok 237 event_missing.LCALTA.27
2025 02:50:09.512607 # ok 238 event_spurious.LCALTA.27
2026 02:50:09.517570 # ok 239 get_value.LCALTA.26
2027 02:50:09.518073 # # LCALTA.26 ELD
2028 02:50:09.523126 # ok 240 name.LCALTA.26
2029 02:50:09.523615 # # ELD is not writeable
2030 02:50:09.528721 # ok 241 # SKIP write_default.LCALTA.26
2031 02:50:09.529217 # # ELD is not writeable
2032 02:50:09.534171 # ok 242 # SKIP write_valid.LCALTA.26
2033 02:50:09.534660 # # ELD is not writeable
2034 02:50:09.539770 # ok 243 # SKIP write_invalid.LCALTA.26
2035 02:50:09.540290 # ok 244 event_missing.LCALTA.26
2036 02:50:09.545439 # ok 245 event_spurious.LCALTA.26
2037 02:50:09.545980 # ok 246 get_value.LCALTA.25
2038 02:50:09.550859 # # LCALTA.25 IEC958 Playback Default
2039 02:50:09.551367 # ok 247 name.LCALTA.25
2040 02:50:09.556429 # ok 248 write_default.LCALTA.25
2041 02:50:09.556930 # ok 249 # SKIP write_valid.LCALTA.25
2042 02:50:09.561918 # ok 250 # SKIP write_invalid.LCALTA.25
2043 02:50:09.567574 # ok 251 event_missing.LCALTA.25
2044 02:50:09.568183 # ok 252 event_spurious.LCALTA.25
2045 02:50:09.572995 # ok 253 get_value.LCALTA.24
2046 02:50:09.573502 # # LCALTA.24 IEC958 Playback Mask
2047 02:50:09.573908 # ok 254 name.LCALTA.24
2048 02:50:09.578590 # # IEC958 Playback Mask is not writeable
2049 02:50:09.584196 # ok 255 # SKIP write_default.LCALTA.24
2050 02:50:09.584714 # # IEC958 Playback Mask is not writeable
2051 02:50:09.589761 # ok 256 # SKIP write_valid.LCALTA.24
2052 02:50:09.595183 # # IEC958 Playback Mask is not writeable
2053 02:50:09.595688 # ok 257 # SKIP write_invalid.LCALTA.24
2054 02:50:09.600765 # ok 258 event_missing.LCALTA.24
2055 02:50:09.601273 # ok 259 event_spurious.LCALTA.24
2056 02:50:09.606379 # ok 260 get_value.LCALTA.23
2057 02:50:09.606832 # # LCALTA.23 Playback Channel Map
2058 02:50:09.611788 # ok 261 name.LCALTA.23
2059 02:50:09.617364 # # Playback Channel Map is not writeable
2060 02:50:09.617828 # ok 262 # SKIP write_default.LCALTA.23
2061 02:50:09.622893 # # Playback Channel Map is not writeable
2062 02:50:09.623342 # ok 263 # SKIP write_valid.LCALTA.23
2063 02:50:09.628461 # # Playback Channel Map is not writeable
2064 02:50:09.633965 # ok 264 # SKIP write_invalid.LCALTA.23
2065 02:50:09.634410 # ok 265 event_missing.LCALTA.23
2066 02:50:09.639523 # ok 266 event_spurious.LCALTA.23
2067 02:50:09.639957 # ok 267 get_value.LCALTA.22
2068 02:50:09.645105 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2069 02:50:09.645559 # ok 268 name.LCALTA.22
2070 02:50:09.650765 # ok 269 write_default.LCALTA.22
2071 02:50:09.651176 # ok 270 write_valid.LCALTA.22
2072 02:50:09.656119 # ok 271 write_invalid.LCALTA.22
2073 02:50:09.656424 # ok 272 event_missing.LCALTA.22
2074 02:50:09.661633 # ok 273 event_spurious.LCALTA.22
2075 02:50:09.667213 # ok 274 get_value.LCALTA.21
2076 02:50:09.667714 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2077 02:50:09.668173 # ok 275 name.LCALTA.21
2078 02:50:09.672787 # ok 276 write_default.LCALTA.21
2079 02:50:09.678378 # ok 277 write_valid.LCALTA.21
2080 02:50:09.678832 # ok 278 write_invalid.LCALTA.21
2081 02:50:09.683893 # ok 279 event_missing.LCALTA.21
2082 02:50:09.684385 # ok 280 event_spurious.LCALTA.21
2083 02:50:09.689508 # ok 281 get_value.LCALTA.20
2084 02:50:09.689969 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2085 02:50:09.694960 # ok 282 name.LCALTA.20
2086 02:50:09.695418 # ok 283 write_default.LCALTA.20
2087 02:50:09.700517 # ok 284 write_valid.LCALTA.20
2088 02:50:09.700970 # ok 285 write_invalid.LCALTA.20
2089 02:50:09.706118 # ok 286 event_missing.LCALTA.20
2090 02:50:09.706570 # ok 287 event_spurious.LCALTA.20
2091 02:50:09.711891 # ok 288 get_value.LCALTA.19
2092 02:50:09.712405 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2093 02:50:09.717235 # ok 289 name.LCALTA.19
2094 02:50:09.717701 # ok 290 write_default.LCALTA.19
2095 02:50:09.723041 # ok 291 write_valid.LCALTA.19
2096 02:50:09.723497 # ok 292 write_invalid.LCALTA.19
2097 02:50:09.728252 # ok 293 event_missing.LCALTA.19
2098 02:50:09.728710 # ok 294 event_spurious.LCALTA.19
2099 02:50:09.733780 # ok 295 get_value.LCALTA.18
2100 02:50:09.734227 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2101 02:50:09.739401 # ok 296 name.LCALTA.18
2102 02:50:09.739950 # ok 297 write_default.LCALTA.18
2103 02:50:09.744939 # ok 298 write_valid.LCALTA.18
2104 02:50:09.745417 # ok 299 write_invalid.LCALTA.18
2105 02:50:09.750428 # ok 300 event_missing.LCALTA.18
2106 02:50:09.750890 # ok 301 event_spurious.LCALTA.18
2107 02:50:09.756036 # ok 302 get_value.LCALTA.17
2108 02:50:09.761493 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2109 02:50:09.761952 # ok 303 name.LCALTA.17
2110 02:50:09.762364 # ok 304 write_default.LCALTA.17
2111 02:50:09.767085 # ok 305 write_valid.LCALTA.17
2112 02:50:09.772681 # ok 306 write_invalid.LCALTA.17
2113 02:50:09.773160 # ok 307 event_missing.LCALTA.17
2114 02:50:09.778338 # ok 308 event_spurious.LCALTA.17
2115 02:50:09.778807 # ok 309 get_value.LCALTA.16
2116 02:50:09.784150 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2117 02:50:09.784704 # ok 310 name.LCALTA.16
2118 02:50:09.789298 # ok 311 write_default.LCALTA.16
2119 02:50:09.789778 # ok 312 write_valid.LCALTA.16
2120 02:50:09.794872 # ok 313 write_invalid.LCALTA.16
2121 02:50:09.795347 # ok 314 event_missing.LCALTA.16
2122 02:50:09.800392 # ok 315 event_spurious.LCALTA.16
2123 02:50:09.800873 # ok 316 get_value.LCALTA.15
2124 02:50:09.806135 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2125 02:50:09.806611 # ok 317 name.LCALTA.15
2126 02:50:09.812014 # ok 318 write_default.LCALTA.15
2127 02:50:09.812653 # ok 319 write_valid.LCALTA.15
2128 02:50:09.817685 # ok 320 write_invalid.LCALTA.15
2129 02:50:09.818087 # ok 321 event_missing.LCALTA.15
2130 02:50:09.823724 # ok 322 event_spurious.LCALTA.15
2131 02:50:09.825355 # ok 323 get_value.LCALTA.14
2132 02:50:09.828126 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2133 02:50:09.828473 # ok 324 name.LCALTA.14
2134 02:50:09.833769 # ok 325 write_default.LCALTA.14
2135 02:50:09.834159 # ok 326 write_valid.LCALTA.14
2136 02:50:09.839332 # ok 327 write_invalid.LCALTA.14
2137 02:50:09.839715 # ok 328 event_missing.LCALTA.14
2138 02:50:09.845139 # ok 329 event_spurious.LCALTA.14
2139 02:50:09.845560 # ok 330 get_value.LCALTA.13
2140 02:50:09.850594 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2141 02:50:09.851086 # ok 331 name.LCALTA.13
2142 02:50:09.856002 # ok 332 write_default.LCALTA.13
2143 02:50:09.856461 # ok 333 write_valid.LCALTA.13
2144 02:50:09.861854 # ok 334 write_invalid.LCALTA.13
2145 02:50:09.862400 # ok 335 event_missing.LCALTA.13
2146 02:50:09.867064 # ok 336 event_spurious.LCALTA.13
2147 02:50:09.867529 # ok 337 get_value.LCALTA.12
2148 02:50:09.872554 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2149 02:50:09.873016 # ok 338 name.LCALTA.12
2150 02:50:09.878114 # ok 339 write_default.LCALTA.12
2151 02:50:09.883496 # ok 340 write_valid.LCALTA.12
2152 02:50:09.883829 # ok 341 write_invalid.LCALTA.12
2153 02:50:09.889093 # ok 342 event_missing.LCALTA.12
2154 02:50:09.889452 # ok 343 event_spurious.LCALTA.12
2155 02:50:09.894716 # ok 344 get_value.LCALTA.11
2156 02:50:09.895076 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2157 02:50:09.900197 # ok 345 name.LCALTA.11
2158 02:50:09.900571 # ok 346 write_default.LCALTA.11
2159 02:50:09.905742 # ok 347 write_valid.LCALTA.11
2160 02:50:09.906088 # ok 348 write_invalid.LCALTA.11
2161 02:50:09.911331 # ok 349 event_missing.LCALTA.11
2162 02:50:09.911940 # ok 350 event_spurious.LCALTA.11
2163 02:50:09.916966 # ok 351 get_value.LCALTA.10
2164 02:50:09.917566 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2165 02:50:09.922330 # ok 352 name.LCALTA.10
2166 02:50:09.922663 # ok 353 write_default.LCALTA.10
2167 02:50:09.927882 # ok 354 write_valid.LCALTA.10
2168 02:50:09.928230 # ok 355 write_invalid.LCALTA.10
2169 02:50:09.933557 # ok 356 event_missing.LCALTA.10
2170 02:50:09.934091 # ok 357 event_spurious.LCALTA.10
2171 02:50:09.939114 # ok 358 get_value.LCALTA.9
2172 02:50:09.939689 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2173 02:50:09.944676 # ok 359 name.LCALTA.9
2174 02:50:09.945304 # ok 360 write_default.LCALTA.9
2175 02:50:09.950215 # ok 361 write_valid.LCALTA.9
2176 02:50:09.950784 # ok 362 write_invalid.LCALTA.9
2177 02:50:09.955895 # ok 363 event_missing.LCALTA.9
2178 02:50:09.956536 # ok 364 event_spurious.LCALTA.9
2179 02:50:09.961342 # ok 365 get_value.LCALTA.8
2180 02:50:09.961730 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2181 02:50:09.966813 # ok 366 name.LCALTA.8
2182 02:50:09.967209 # ok 367 write_default.LCALTA.8
2183 02:50:09.972293 # ok 368 write_valid.LCALTA.8
2184 02:50:09.972684 # ok 369 write_invalid.LCALTA.8
2185 02:50:09.977854 # ok 370 event_missing.LCALTA.8
2186 02:50:09.978251 # ok 371 event_spurious.LCALTA.8
2187 02:50:09.983368 # ok 372 get_value.LCALTA.7
2188 02:50:09.983757 # # LCALTA.7 ACODEC Unmute Ramp Switch
2189 02:50:09.989040 # ok 373 name.LCALTA.7
2190 02:50:09.989428 # ok 374 write_default.LCALTA.7
2191 02:50:09.994536 # ok 375 write_valid.LCALTA.7
2192 02:50:09.994939 # ok 376 write_invalid.LCALTA.7
2193 02:50:10.000061 # ok 377 event_missing.LCALTA.7
2194 02:50:10.000467 # ok 378 event_spurious.LCALTA.7
2195 02:50:10.005586 # ok 379 get_value.LCALTA.6
2196 02:50:10.005989 # # LCALTA.6 ACODEC Mute Ramp Switch
2197 02:50:10.011175 # ok 380 name.LCALTA.6
2198 02:50:10.011567 # ok 381 write_default.LCALTA.6
2199 02:50:10.016883 # ok 382 write_valid.LCALTA.6
2200 02:50:10.017337 # ok 383 write_invalid.LCALTA.6
2201 02:50:10.022377 # ok 384 event_missing.LCALTA.6
2202 02:50:10.023011 # ok 385 event_spurious.LCALTA.6
2203 02:50:10.027968 # ok 386 get_value.LCALTA.5
2204 02:50:10.028625 # # LCALTA.5 ACODEC Volume Ramp Switch
2205 02:50:10.033489 # ok 387 name.LCALTA.5
2206 02:50:10.034106 # ok 388 write_default.LCALTA.5
2207 02:50:10.039042 # ok 389 write_valid.LCALTA.5
2208 02:50:10.039657 # ok 390 write_invalid.LCALTA.5
2209 02:50:10.044636 # ok 391 event_missing.LCALTA.5
2210 02:50:10.045240 # ok 392 event_spurious.LCALTA.5
2211 02:50:10.050921 # ok 393 get_value.LCALTA.4
2212 02:50:10.051595 # # LCALTA.4 ACODEC Ramp Rate
2213 02:50:10.055677 # ok 394 name.LCALTA.4
2214 02:50:10.056316 # ok 395 write_default.LCALTA.4
2215 02:50:10.061219 # ok 396 write_valid.LCALTA.4
2216 02:50:10.061824 # ok 397 write_invalid.LCALTA.4
2217 02:50:10.066763 # ok 398 event_missing.LCALTA.4
2218 02:50:10.067379 # ok 399 event_spurious.LCALTA.4
2219 02:50:10.072384 # ok 400 get_value.LCALTA.3
2220 02:50:10.073022 # # LCALTA.3 ACODEC Playback Volume
2221 02:50:10.077977 # ok 401 name.LCALTA.3
2222 02:50:10.078612 # ok 402 write_default.LCALTA.3
2223 02:50:10.083465 # ok 403 write_valid.LCALTA.3
2224 02:50:10.084121 # ok 404 write_invalid.LCALTA.3
2225 02:50:10.088912 # ok 405 event_missing.LCALTA.3
2226 02:50:10.089488 # ok 406 event_spurious.LCALTA.3
2227 02:50:10.094453 # ok 407 get_value.LCALTA.2
2228 02:50:10.095042 # # LCALTA.2 ACODEC Playback Switch
2229 02:50:10.100027 # ok 408 name.LCALTA.2
2230 02:50:10.100629 # ok 409 write_default.LCALTA.2
2231 02:50:10.105547 # ok 410 write_valid.LCALTA.2
2232 02:50:10.106133 # ok 411 write_invalid.LCALTA.2
2233 02:50:10.111121 # ok 412 event_missing.LCALTA.2
2234 02:50:10.111713 # ok 413 event_spurious.LCALTA.2
2235 02:50:10.116741 # ok 414 get_value.LCALTA.1
2236 02:50:10.117408 # # LCALTA.1 ACODEC Playback Channel Mode
2237 02:50:10.122222 # ok 415 name.LCALTA.1
2238 02:50:10.122833 # ok 416 write_default.LCALTA.1
2239 02:50:10.127735 # ok 417 write_valid.LCALTA.1
2240 02:50:10.128402 # ok 418 write_invalid.LCALTA.1
2241 02:50:10.133371 # ok 419 event_missing.LCALTA.1
2242 02:50:10.134007 # ok 420 event_spurious.LCALTA.1
2243 02:50:10.138937 # ok 421 get_value.LCALTA.0
2244 02:50:10.139506 # # LCALTA.0 TOACODEC Lane Select
2245 02:50:10.144387 # ok 422 name.LCALTA.0
2246 02:50:10.144999 # ok 423 write_default.LCALTA.0
2247 02:50:10.150037 # ok 424 write_valid.LCALTA.0
2248 02:50:10.150702 # ok 425 write_invalid.LCALTA.0
2249 02:50:10.155516 # ok 426 event_missing.LCALTA.0
2250 02:50:10.156152 # ok 427 event_spurious.LCALTA.0
2251 02:50:10.160859 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2252 02:50:10.166722 ok 1 selftests: alsa: mixer-test
2253 02:50:10.167379 # timeout set to 45
2254 02:50:10.167853 # selftests: alsa: pcm-test
2255 02:50:10.172156 # TAP version 13
2256 02:50:10.172731 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2257 02:50:10.177692 # # LCALTA.0 - fe.dai-link-0 (*)
2258 02:50:10.178278 # # LCALTA.0 - fe.dai-link-1 (*)
2259 02:50:10.183198 # # LCALTA.0 - fe.dai-link-2 (*)
2260 02:50:10.183794 # # LCALTA.0 - fe.dai-link-3 (*)
2261 02:50:10.188749 # # LCALTA.0 - fe.dai-link-4 (*)
2262 02:50:10.189343 # # LCALTA.0 - fe.dai-link-5 (*)
2263 02:50:10.194300 # 1..42
2264 02:50:10.200247 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2265 02:50:10.200894 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2266 02:50:10.205418 # # snd_pcm_hw_params: Invalid argument
2267 02:50:10.210938 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2268 02:50:10.216476 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2269 02:50:10.217072 # # snd_pcm_hw_params: Invalid argument
2270 02:50:10.222050 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2271 02:50:10.228189 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2272 02:50:10.233176 # # snd_pcm_hw_params: Invalid argument
2273 02:50:10.238723 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2274 02:50:10.244224 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2275 02:50:10.244815 # # snd_pcm_hw_params: Invalid argument
2276 02:50:10.249872 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2277 02:50:10.255243 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2278 02:50:10.260867 # # snd_pcm_hw_params: Invalid argument
2279 02:50:10.267179 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2280 02:50:10.271903 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2281 02:50:10.272503 # # snd_pcm_hw_params: Invalid argument
2282 02:50:10.277460 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2283 02:50:10.283013 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2284 02:50:10.288662 # # snd_pcm_hw_params: Invalid argument
2285 02:50:10.294140 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2286 02:50:10.294714 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2287 02:50:10.299651 # # snd_pcm_hw_params: Invalid argument
2288 02:50:10.305169 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2289 02:50:10.310882 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2290 02:50:10.311450 # # snd_pcm_hw_params: Invalid argument
2291 02:50:10.321804 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2292 02:50:10.322396 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2293 02:50:10.327393 # # snd_pcm_hw_params: Invalid argument
2294 02:50:10.332902 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2295 02:50:10.338646 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2296 02:50:10.339326 # # snd_pcm_hw_params: Invalid argument
2297 02:50:10.344074 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2298 02:50:10.349695 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2299 02:50:10.355222 # # snd_pcm_hw_params: Invalid argument
2300 02:50:10.360734 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2301 02:50:10.366290 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2302 02:50:10.366897 # # snd_pcm_hw_params: Invalid argument
2303 02:50:10.371931 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2304 02:50:10.377352 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2305 02:50:10.383066 # # snd_pcm_hw_params: Invalid argument
2306 02:50:10.388470 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2307 02:50:10.393937 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2308 02:50:10.394500 # # snd_pcm_hw_params: Invalid argument
2309 02:50:10.399533 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2310 02:50:10.405135 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2311 02:50:10.410696 # # snd_pcm_hw_params: Invalid argument
2312 02:50:10.416361 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2313 02:50:10.417031 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2314 02:50:10.421918 # # snd_pcm_hw_params: Invalid argument
2315 02:50:10.428228 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2316 02:50:10.432958 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2317 02:50:10.438408 # # snd_pcm_hw_params: Invalid argument
2318 02:50:10.444259 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2319 02:50:10.444690 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2320 02:50:10.449438 # # snd_pcm_hw_params: Invalid argument
2321 02:50:10.455486 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2322 02:50:10.460759 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2323 02:50:10.466181 # # snd_pcm_hw_params: Invalid argument
2324 02:50:10.471688 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2325 02:50:10.472137 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2326 02:50:10.477826 # # snd_pcm_hw_params: Invalid argument
2327 02:50:10.482784 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2328 02:50:10.488285 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2329 02:50:10.488810 # # snd_pcm_hw_params: Invalid argument
2330 02:50:10.493890 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2331 02:50:10.499927 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2332 02:50:10.504883 # # snd_pcm_hw_params: Invalid argument
2333 02:50:10.510552 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2334 02:50:10.516012 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2335 02:50:10.516630 # # snd_pcm_hw_params: Invalid argument
2336 02:50:10.521478 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2337 02:50:10.527043 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2338 02:50:10.532695 # # snd_pcm_hw_params: Invalid argument
2339 02:50:10.538059 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2340 02:50:10.543764 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2341 02:50:10.544460 # # snd_pcm_hw_params: Invalid argument
2342 02:50:10.549498 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2343 02:50:10.555022 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2344 02:50:10.560376 # # snd_pcm_hw_params: Invalid argument
2345 02:50:10.565956 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2346 02:50:10.571522 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2347 02:50:10.572132 # # snd_pcm_hw_params: Invalid argument
2348 02:50:10.577063 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2349 02:50:10.583345 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2350 02:50:10.588228 # # snd_pcm_hw_params: Invalid argument
2351 02:50:10.594039 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2352 02:50:10.599132 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2353 02:50:10.599682 # # snd_pcm_hw_params: Invalid argument
2354 02:50:10.604636 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2355 02:50:10.610169 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2356 02:50:10.615807 # # snd_pcm_hw_params: Invalid argument
2357 02:50:10.621277 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2358 02:50:10.627350 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2359 02:50:10.628026 # # snd_pcm_hw_params: Invalid argument
2360 02:50:10.632413 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2361 02:50:10.638138 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2362 02:50:10.643523 # # snd_pcm_hw_params: Invalid argument
2363 02:50:10.649080 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2364 02:50:10.654767 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2365 02:50:10.655386 # # snd_pcm_hw_params: Invalid argument
2366 02:50:10.660306 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2367 02:50:10.665580 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2368 02:50:10.671160 # # snd_pcm_hw_params: Invalid argument
2369 02:50:10.676840 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2370 02:50:10.682460 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2371 02:50:10.682847 # # snd_pcm_hw_params: Invalid argument
2372 02:50:10.688014 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2373 02:50:10.693444 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2374 02:50:10.698930 # # snd_pcm_hw_params: Invalid argument
2375 02:50:10.704506 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2376 02:50:10.710180 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2377 02:50:10.710597 # # snd_pcm_hw_params: Invalid argument
2378 02:50:10.715617 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2379 02:50:10.721359 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2380 02:50:10.726700 # # snd_pcm_hw_params: Invalid argument
2381 02:50:10.732295 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2382 02:50:10.737843 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2383 02:50:10.738370 # # snd_pcm_hw_params: Invalid argument
2384 02:50:10.743315 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2385 02:50:10.748898 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2386 02:50:10.754369 # # snd_pcm_hw_params: Invalid argument
2387 02:50:10.759897 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2388 02:50:10.765682 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2389 02:50:10.766085 # # snd_pcm_hw_params: Invalid argument
2390 02:50:10.771033 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2391 02:50:10.776838 ok 2 selftests: alsa: pcm-test
2392 02:50:10.777523 # timeout set to 45
2393 02:50:10.782312 # selftests: alsa: test-pcmtest-driver
2394 02:50:10.782978 # TAP version 13
2395 02:50:10.783460 # 1..5
2396 02:50:10.787769 # # Starting 5 tests from 1 test cases.
2397 02:50:10.788421 # # RUN pcmtest.playback ...
2398 02:50:10.793398 # # SKIP Can't read patterns. Probably, module isn't loaded
2399 02:50:10.799077 # # OK pcmtest.playback
2400 02:50:10.804919 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2401 02:50:10.809899 # # RUN pcmtest.capture ...
2402 02:50:10.815444 # # SKIP Can't read patterns. Probably, module isn't loaded
2403 02:50:10.820971 # # OK pcmtest.capture
2404 02:50:10.826523 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2405 02:50:10.832084 # # RUN pcmtest.ni_capture ...
2406 02:50:10.837674 # # SKIP Can't read patterns. Probably, module isn't loaded
2407 02:50:10.838258 # # OK pcmtest.ni_capture
2408 02:50:10.848736 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2409 02:50:10.849164 # # RUN pcmtest.ni_playback ...
2410 02:50:10.854362 # # SKIP Can't read patterns. Probably, module isn't loaded
2411 02:50:10.860104 # # OK pcmtest.ni_playback
2412 02:50:10.865487 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2413 02:50:10.871059 # # RUN pcmtest.reset_ioctl ...
2414 02:50:10.876536 # # SKIP Can't read patterns. Probably, module isn't loaded
2415 02:50:10.882120 # # OK pcmtest.reset_ioctl
2416 02:50:10.887580 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2417 02:50:10.893193 # # PASSED: 5 / 5 tests passed.
2418 02:50:10.898687 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2419 02:50:10.899140 ok 3 selftests: alsa: test-pcmtest-driver
2420 02:50:10.904246 # timeout set to 45
2421 02:50:10.904682 # selftests: alsa: utimer-test
2422 02:50:10.904961 # TAP version 13
2423 02:50:10.905336 # 1..2
2424 02:50:10.909759 # # Starting 2 tests from 2 test cases.
2425 02:50:10.915374 # # RUN global.wrong_timers_test ...
2426 02:50:10.921009 # # OK global.wrong_timers_test
2427 02:50:10.921441 # ok 1 global.wrong_timers_test
2428 02:50:10.926366 # # RUN timer_f.utimer ...
2429 02:50:10.931963 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2430 02:50:10.937421 # # utimer: Test terminated by assertion
2431 02:50:10.942943 # # FAIL timer_f.utimer
2432 02:50:10.943259 # not ok 2 timer_f.utimer
2433 02:50:10.948540 # # FAILED: 1 / 2 tests passed.
2434 02:50:10.955888 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2435 02:50:10.956224 not ok 4 selftests: alsa: utimer-test # exit=1
2436 02:50:11.472370 alsa_mixer-test_get_value_LCALTA_60 pass
2437 02:50:11.477890 alsa_mixer-test_name_LCALTA_60 pass
2438 02:50:11.478330 alsa_mixer-test_write_default_LCALTA_60 pass
2439 02:50:11.483262 alsa_mixer-test_write_valid_LCALTA_60 pass
2440 02:50:11.488876 alsa_mixer-test_write_invalid_LCALTA_60 pass
2441 02:50:11.494360 alsa_mixer-test_event_missing_LCALTA_60 pass
2442 02:50:11.494667 alsa_mixer-test_event_spurious_LCALTA_60 pass
2443 02:50:11.499899 alsa_mixer-test_get_value_LCALTA_59 pass
2444 02:50:11.505450 alsa_mixer-test_name_LCALTA_59 pass
2445 02:50:11.505756 alsa_mixer-test_write_default_LCALTA_59 pass
2446 02:50:11.511011 alsa_mixer-test_write_valid_LCALTA_59 pass
2447 02:50:11.516641 alsa_mixer-test_write_invalid_LCALTA_59 pass
2448 02:50:11.517075 alsa_mixer-test_event_missing_LCALTA_59 pass
2449 02:50:11.522113 alsa_mixer-test_event_spurious_LCALTA_59 pass
2450 02:50:11.527662 alsa_mixer-test_get_value_LCALTA_58 pass
2451 02:50:11.527964 alsa_mixer-test_name_LCALTA_58 pass
2452 02:50:11.533176 alsa_mixer-test_write_default_LCALTA_58 pass
2453 02:50:11.538882 alsa_mixer-test_write_valid_LCALTA_58 pass
2454 02:50:11.539317 alsa_mixer-test_write_invalid_LCALTA_58 pass
2455 02:50:11.544268 alsa_mixer-test_event_missing_LCALTA_58 pass
2456 02:50:11.549879 alsa_mixer-test_event_spurious_LCALTA_58 pass
2457 02:50:11.555362 alsa_mixer-test_get_value_LCALTA_57 pass
2458 02:50:11.555664 alsa_mixer-test_name_LCALTA_57 pass
2459 02:50:11.560924 alsa_mixer-test_write_default_LCALTA_57 pass
2460 02:50:11.566475 alsa_mixer-test_write_valid_LCALTA_57 pass
2461 02:50:11.566895 alsa_mixer-test_write_invalid_LCALTA_57 pass
2462 02:50:11.572043 alsa_mixer-test_event_missing_LCALTA_57 pass
2463 02:50:11.577659 alsa_mixer-test_event_spurious_LCALTA_57 pass
2464 02:50:11.577965 alsa_mixer-test_get_value_LCALTA_56 pass
2465 02:50:11.583122 alsa_mixer-test_name_LCALTA_56 pass
2466 02:50:11.588688 alsa_mixer-test_write_default_LCALTA_56 pass
2467 02:50:11.589105 alsa_mixer-test_write_valid_LCALTA_56 pass
2468 02:50:11.594270 alsa_mixer-test_write_invalid_LCALTA_56 pass
2469 02:50:11.599900 alsa_mixer-test_event_missing_LCALTA_56 pass
2470 02:50:11.605302 alsa_mixer-test_event_spurious_LCALTA_56 pass
2471 02:50:11.605605 alsa_mixer-test_get_value_LCALTA_55 pass
2472 02:50:11.610935 alsa_mixer-test_name_LCALTA_55 pass
2473 02:50:11.616418 alsa_mixer-test_write_default_LCALTA_55 pass
2474 02:50:11.616858 alsa_mixer-test_write_valid_LCALTA_55 pass
2475 02:50:11.622004 alsa_mixer-test_write_invalid_LCALTA_55 pass
2476 02:50:11.627645 alsa_mixer-test_event_missing_LCALTA_55 pass
2477 02:50:11.627959 alsa_mixer-test_event_spurious_LCALTA_55 pass
2478 02:50:11.633087 alsa_mixer-test_get_value_LCALTA_54 pass
2479 02:50:11.638808 alsa_mixer-test_name_LCALTA_54 pass
2480 02:50:11.639259 alsa_mixer-test_write_default_LCALTA_54 pass
2481 02:50:11.644210 alsa_mixer-test_write_valid_LCALTA_54 pass
2482 02:50:11.649686 alsa_mixer-test_write_invalid_LCALTA_54 pass
2483 02:50:11.650008 alsa_mixer-test_event_missing_LCALTA_54 pass
2484 02:50:11.655267 alsa_mixer-test_event_spurious_LCALTA_54 pass
2485 02:50:11.660978 alsa_mixer-test_get_value_LCALTA_53 pass
2486 02:50:11.661455 alsa_mixer-test_name_LCALTA_53 pass
2487 02:50:11.666653 alsa_mixer-test_write_default_LCALTA_53 pass
2488 02:50:11.672024 alsa_mixer-test_write_valid_LCALTA_53 pass
2489 02:50:11.677495 alsa_mixer-test_write_invalid_LCALTA_53 pass
2490 02:50:11.677852 alsa_mixer-test_event_missing_LCALTA_53 pass
2491 02:50:11.683055 alsa_mixer-test_event_spurious_LCALTA_53 pass
2492 02:50:11.688565 alsa_mixer-test_get_value_LCALTA_52 pass
2493 02:50:11.689029 alsa_mixer-test_name_LCALTA_52 pass
2494 02:50:11.694102 alsa_mixer-test_write_default_LCALTA_52 pass
2495 02:50:11.699696 alsa_mixer-test_write_valid_LCALTA_52 pass
2496 02:50:11.700040 alsa_mixer-test_write_invalid_LCALTA_52 pass
2497 02:50:11.705178 alsa_mixer-test_event_missing_LCALTA_52 pass
2498 02:50:11.710731 alsa_mixer-test_event_spurious_LCALTA_52 pass
2499 02:50:11.711181 alsa_mixer-test_get_value_LCALTA_51 pass
2500 02:50:11.716287 alsa_mixer-test_name_LCALTA_51 pass
2501 02:50:11.721986 alsa_mixer-test_write_default_LCALTA_51 pass
2502 02:50:11.722317 alsa_mixer-test_write_valid_LCALTA_51 pass
2503 02:50:11.727370 alsa_mixer-test_write_invalid_LCALTA_51 pass
2504 02:50:11.732980 alsa_mixer-test_event_missing_LCALTA_51 pass
2505 02:50:11.738451 alsa_mixer-test_event_spurious_LCALTA_51 pass
2506 02:50:11.738770 alsa_mixer-test_get_value_LCALTA_50 pass
2507 02:50:11.744050 alsa_mixer-test_name_LCALTA_50 pass
2508 02:50:11.749590 alsa_mixer-test_write_default_LCALTA_50 pass
2509 02:50:11.750056 alsa_mixer-test_write_valid_LCALTA_50 pass
2510 02:50:11.755223 alsa_mixer-test_write_invalid_LCALTA_50 pass
2511 02:50:11.760730 alsa_mixer-test_event_missing_LCALTA_50 pass
2512 02:50:11.761067 alsa_mixer-test_event_spurious_LCALTA_50 pass
2513 02:50:11.766205 alsa_mixer-test_get_value_LCALTA_49 pass
2514 02:50:11.771759 alsa_mixer-test_name_LCALTA_49 pass
2515 02:50:11.772293 alsa_mixer-test_write_default_LCALTA_49 pass
2516 02:50:11.777304 alsa_mixer-test_write_valid_LCALTA_49 pass
2517 02:50:11.783005 alsa_mixer-test_write_invalid_LCALTA_49 pass
2518 02:50:11.788402 alsa_mixer-test_event_missing_LCALTA_49 pass
2519 02:50:11.788725 alsa_mixer-test_event_spurious_LCALTA_49 pass
2520 02:50:11.794003 alsa_mixer-test_get_value_LCALTA_48 pass
2521 02:50:11.794458 alsa_mixer-test_name_LCALTA_48 pass
2522 02:50:11.799496 alsa_mixer-test_write_default_LCALTA_48 pass
2523 02:50:11.805032 alsa_mixer-test_write_valid_LCALTA_48 pass
2524 02:50:11.810613 alsa_mixer-test_write_invalid_LCALTA_48 pass
2525 02:50:11.810950 alsa_mixer-test_event_missing_LCALTA_48 pass
2526 02:50:11.816175 alsa_mixer-test_event_spurious_LCALTA_48 pass
2527 02:50:11.821739 alsa_mixer-test_get_value_LCALTA_47 pass
2528 02:50:11.822203 alsa_mixer-test_name_LCALTA_47 pass
2529 02:50:11.827216 alsa_mixer-test_write_default_LCALTA_47 pass
2530 02:50:11.832778 alsa_mixer-test_write_valid_LCALTA_47 pass
2531 02:50:11.833116 alsa_mixer-test_write_invalid_LCALTA_47 pass
2532 02:50:11.838363 alsa_mixer-test_event_missing_LCALTA_47 pass
2533 02:50:11.843965 alsa_mixer-test_event_spurious_LCALTA_47 pass
2534 02:50:11.849383 alsa_mixer-test_get_value_LCALTA_46 pass
2535 02:50:11.849835 alsa_mixer-test_name_LCALTA_46 pass
2536 02:50:11.854978 alsa_mixer-test_write_default_LCALTA_46 pass
2537 02:50:11.860506 alsa_mixer-test_write_valid_LCALTA_46 pass
2538 02:50:11.860823 alsa_mixer-test_write_invalid_LCALTA_46 pass
2539 02:50:11.866031 alsa_mixer-test_event_missing_LCALTA_46 pass
2540 02:50:11.871619 alsa_mixer-test_event_spurious_LCALTA_46 pass
2541 02:50:11.871952 alsa_mixer-test_get_value_LCALTA_45 pass
2542 02:50:11.877132 alsa_mixer-test_name_LCALTA_45 pass
2543 02:50:11.882747 alsa_mixer-test_write_default_LCALTA_45 pass
2544 02:50:11.883079 alsa_mixer-test_write_valid_LCALTA_45 pass
2545 02:50:11.888216 alsa_mixer-test_write_invalid_LCALTA_45 pass
2546 02:50:11.893789 alsa_mixer-test_event_missing_LCALTA_45 pass
2547 02:50:11.894265 alsa_mixer-test_event_spurious_LCALTA_45 pass
2548 02:50:11.899323 alsa_mixer-test_get_value_LCALTA_44 pass
2549 02:50:11.904990 alsa_mixer-test_name_LCALTA_44 pass
2550 02:50:11.905322 alsa_mixer-test_write_default_LCALTA_44 pass
2551 02:50:11.910394 alsa_mixer-test_write_valid_LCALTA_44 pass
2552 02:50:11.915962 alsa_mixer-test_write_invalid_LCALTA_44 pass
2553 02:50:11.921534 alsa_mixer-test_event_missing_LCALTA_44 pass
2554 02:50:11.921851 alsa_mixer-test_event_spurious_LCALTA_44 pass
2555 02:50:11.927033 alsa_mixer-test_get_value_LCALTA_43 pass
2556 02:50:11.932658 alsa_mixer-test_name_LCALTA_43 pass
2557 02:50:11.933105 alsa_mixer-test_write_default_LCALTA_43 pass
2558 02:50:11.938125 alsa_mixer-test_write_valid_LCALTA_43 pass
2559 02:50:11.943745 alsa_mixer-test_write_invalid_LCALTA_43 pass
2560 02:50:11.944108 alsa_mixer-test_event_missing_LCALTA_43 pass
2561 02:50:11.949252 alsa_mixer-test_event_spurious_LCALTA_43 pass
2562 02:50:11.954767 alsa_mixer-test_get_value_LCALTA_42 pass
2563 02:50:11.955220 alsa_mixer-test_name_LCALTA_42 pass
2564 02:50:11.960677 alsa_mixer-test_write_default_LCALTA_42 pass
2565 02:50:11.965972 alsa_mixer-test_write_valid_LCALTA_42 pass
2566 02:50:11.966279 alsa_mixer-test_write_invalid_LCALTA_42 pass
2567 02:50:11.971414 alsa_mixer-test_event_missing_LCALTA_42 pass
2568 02:50:11.976954 alsa_mixer-test_event_spurious_LCALTA_42 pass
2569 02:50:11.982484 alsa_mixer-test_get_value_LCALTA_41 pass
2570 02:50:11.982786 alsa_mixer-test_name_LCALTA_41 pass
2571 02:50:11.988051 alsa_mixer-test_write_default_LCALTA_41 pass
2572 02:50:11.993614 alsa_mixer-test_write_valid_LCALTA_41 pass
2573 02:50:11.994081 alsa_mixer-test_write_invalid_LCALTA_41 pass
2574 02:50:11.999189 alsa_mixer-test_event_missing_LCALTA_41 pass
2575 02:50:12.004759 alsa_mixer-test_event_spurious_LCALTA_41 pass
2576 02:50:12.005100 alsa_mixer-test_get_value_LCALTA_40 pass
2577 02:50:12.010319 alsa_mixer-test_name_LCALTA_40 pass
2578 02:50:12.015862 alsa_mixer-test_write_default_LCALTA_40 pass
2579 02:50:12.016457 alsa_mixer-test_write_valid_LCALTA_40 pass
2580 02:50:12.021427 alsa_mixer-test_write_invalid_LCALTA_40 pass
2581 02:50:12.027066 alsa_mixer-test_event_missing_LCALTA_40 pass
2582 02:50:12.032515 alsa_mixer-test_event_spurious_LCALTA_40 pass
2583 02:50:12.032916 alsa_mixer-test_get_value_LCALTA_39 pass
2584 02:50:12.038066 alsa_mixer-test_name_LCALTA_39 pass
2585 02:50:12.043558 alsa_mixer-test_write_default_LCALTA_39 pass
2586 02:50:12.043927 alsa_mixer-test_write_valid_LCALTA_39 pass
2587 02:50:12.049203 alsa_mixer-test_write_invalid_LCALTA_39 pass
2588 02:50:12.054678 alsa_mixer-test_event_missing_LCALTA_39 pass
2589 02:50:12.055005 alsa_mixer-test_event_spurious_LCALTA_39 pass
2590 02:50:12.060192 alsa_mixer-test_get_value_LCALTA_38 pass
2591 02:50:12.065749 alsa_mixer-test_name_LCALTA_38 pass
2592 02:50:12.066229 alsa_mixer-test_write_default_LCALTA_38 pass
2593 02:50:12.071275 alsa_mixer-test_write_valid_LCALTA_38 pass
2594 02:50:12.076802 alsa_mixer-test_write_invalid_LCALTA_38 pass
2595 02:50:12.077135 alsa_mixer-test_event_missing_LCALTA_38 pass
2596 02:50:12.082395 alsa_mixer-test_event_spurious_LCALTA_38 pass
2597 02:50:12.088034 alsa_mixer-test_get_value_LCALTA_37 pass
2598 02:50:12.088521 alsa_mixer-test_name_LCALTA_37 pass
2599 02:50:12.093478 alsa_mixer-test_write_default_LCALTA_37 pass
2600 02:50:12.098998 alsa_mixer-test_write_valid_LCALTA_37 pass
2601 02:50:12.104572 alsa_mixer-test_write_invalid_LCALTA_37 pass
2602 02:50:12.104917 alsa_mixer-test_event_missing_LCALTA_37 pass
2603 02:50:12.110109 alsa_mixer-test_event_spurious_LCALTA_37 pass
2604 02:50:12.115651 alsa_mixer-test_get_value_LCALTA_36 pass
2605 02:50:12.116165 alsa_mixer-test_name_LCALTA_36 pass
2606 02:50:12.121191 alsa_mixer-test_write_default_LCALTA_36 pass
2607 02:50:12.126740 alsa_mixer-test_write_valid_LCALTA_36 pass
2608 02:50:12.127063 alsa_mixer-test_write_invalid_LCALTA_36 pass
2609 02:50:12.132281 alsa_mixer-test_event_missing_LCALTA_36 pass
2610 02:50:12.137807 alsa_mixer-test_event_spurious_LCALTA_36 pass
2611 02:50:12.138272 alsa_mixer-test_get_value_LCALTA_35 pass
2612 02:50:12.143387 alsa_mixer-test_name_LCALTA_35 pass
2613 02:50:12.148999 alsa_mixer-test_write_default_LCALTA_35 pass
2614 02:50:12.149328 alsa_mixer-test_write_valid_LCALTA_35 pass
2615 02:50:12.154459 alsa_mixer-test_write_invalid_LCALTA_35 pass
2616 02:50:12.160257 alsa_mixer-test_event_missing_LCALTA_35 pass
2617 02:50:12.165680 alsa_mixer-test_event_spurious_LCALTA_35 pass
2618 02:50:12.166024 alsa_mixer-test_get_value_LCALTA_34 pass
2619 02:50:12.171139 alsa_mixer-test_name_LCALTA_34 pass
2620 02:50:12.176665 alsa_mixer-test_write_default_LCALTA_34 pass
2621 02:50:12.177123 alsa_mixer-test_write_valid_LCALTA_34 pass
2622 02:50:12.182211 alsa_mixer-test_write_invalid_LCALTA_34 pass
2623 02:50:12.187751 alsa_mixer-test_event_missing_LCALTA_34 pass
2624 02:50:12.188075 alsa_mixer-test_event_spurious_LCALTA_34 pass
2625 02:50:12.193310 alsa_mixer-test_get_value_LCALTA_33 pass
2626 02:50:12.198892 alsa_mixer-test_name_LCALTA_33 pass
2627 02:50:12.199418 alsa_mixer-test_write_default_LCALTA_33 pass
2628 02:50:12.204397 alsa_mixer-test_write_valid_LCALTA_33 pass
2629 02:50:12.210018 alsa_mixer-test_write_invalid_LCALTA_33 pass
2630 02:50:12.215525 alsa_mixer-test_event_missing_LCALTA_33 pass
2631 02:50:12.215851 alsa_mixer-test_event_spurious_LCALTA_33 pass
2632 02:50:12.221106 alsa_mixer-test_get_value_LCALTA_32 pass
2633 02:50:12.221460 alsa_mixer-test_name_LCALTA_32 pass
2634 02:50:12.226594 alsa_mixer-test_write_default_LCALTA_32 pass
2635 02:50:12.232197 alsa_mixer-test_write_valid_LCALTA_32 pass
2636 02:50:12.237766 alsa_mixer-test_write_invalid_LCALTA_32 pass
2637 02:50:12.238108 alsa_mixer-test_event_missing_LCALTA_32 pass
2638 02:50:12.243215 alsa_mixer-test_event_spurious_LCALTA_32 pass
2639 02:50:12.248761 alsa_mixer-test_get_value_LCALTA_31 pass
2640 02:50:12.249230 alsa_mixer-test_name_LCALTA_31 pass
2641 02:50:12.254344 alsa_mixer-test_write_default_LCALTA_31 pass
2642 02:50:12.259914 alsa_mixer-test_write_valid_LCALTA_31 pass
2643 02:50:12.260318 alsa_mixer-test_write_invalid_LCALTA_31 pass
2644 02:50:12.265441 alsa_mixer-test_event_missing_LCALTA_31 pass
2645 02:50:12.271088 alsa_mixer-test_event_spurious_LCALTA_31 pass
2646 02:50:12.276494 alsa_mixer-test_get_value_LCALTA_30 pass
2647 02:50:12.276865 alsa_mixer-test_name_LCALTA_30 pass
2648 02:50:12.282040 alsa_mixer-test_write_default_LCALTA_30 pass
2649 02:50:12.287609 alsa_mixer-test_write_valid_LCALTA_30 pass
2650 02:50:12.288113 alsa_mixer-test_write_invalid_LCALTA_30 pass
2651 02:50:12.293197 alsa_mixer-test_event_missing_LCALTA_30 pass
2652 02:50:12.298718 alsa_mixer-test_event_spurious_LCALTA_30 pass
2653 02:50:12.299236 alsa_mixer-test_get_value_LCALTA_29 pass
2654 02:50:12.304255 alsa_mixer-test_name_LCALTA_29 pass
2655 02:50:12.309802 alsa_mixer-test_write_default_LCALTA_29 pass
2656 02:50:12.310158 alsa_mixer-test_write_valid_LCALTA_29 pass
2657 02:50:12.315329 alsa_mixer-test_write_invalid_LCALTA_29 pass
2658 02:50:12.320873 alsa_mixer-test_event_missing_LCALTA_29 pass
2659 02:50:12.321356 alsa_mixer-test_event_spurious_LCALTA_29 pass
2660 02:50:12.326413 alsa_mixer-test_get_value_LCALTA_28 pass
2661 02:50:12.332069 alsa_mixer-test_name_LCALTA_28 pass
2662 02:50:12.332405 alsa_mixer-test_write_default_LCALTA_28 pass
2663 02:50:12.337546 alsa_mixer-test_write_valid_LCALTA_28 pass
2664 02:50:12.343094 alsa_mixer-test_write_invalid_LCALTA_28 pass
2665 02:50:12.348622 alsa_mixer-test_event_missing_LCALTA_28 pass
2666 02:50:12.348962 alsa_mixer-test_event_spurious_LCALTA_28 pass
2667 02:50:12.354346 alsa_mixer-test_get_value_LCALTA_27 pass
2668 02:50:12.359690 alsa_mixer-test_name_LCALTA_27 pass
2669 02:50:12.360090 alsa_mixer-test_write_default_LCALTA_27 pass
2670 02:50:12.365236 alsa_mixer-test_write_valid_LCALTA_27 pass
2671 02:50:12.370767 alsa_mixer-test_write_invalid_LCALTA_27 pass
2672 02:50:12.371065 alsa_mixer-test_event_missing_LCALTA_27 pass
2673 02:50:12.376317 alsa_mixer-test_event_spurious_LCALTA_27 pass
2674 02:50:12.381860 alsa_mixer-test_get_value_LCALTA_26 pass
2675 02:50:12.382290 alsa_mixer-test_name_LCALTA_26 pass
2676 02:50:12.387403 alsa_mixer-test_write_default_LCALTA_26 skip
2677 02:50:12.393031 alsa_mixer-test_write_valid_LCALTA_26 skip
2678 02:50:12.393324 alsa_mixer-test_write_invalid_LCALTA_26 skip
2679 02:50:12.398509 alsa_mixer-test_event_missing_LCALTA_26 pass
2680 02:50:12.404048 alsa_mixer-test_event_spurious_LCALTA_26 pass
2681 02:50:12.409588 alsa_mixer-test_get_value_LCALTA_25 pass
2682 02:50:12.409881 alsa_mixer-test_name_LCALTA_25 pass
2683 02:50:12.415157 alsa_mixer-test_write_default_LCALTA_25 pass
2684 02:50:12.420675 alsa_mixer-test_write_valid_LCALTA_25 skip
2685 02:50:12.421175 alsa_mixer-test_write_invalid_LCALTA_25 skip
2686 02:50:12.426224 alsa_mixer-test_event_missing_LCALTA_25 pass
2687 02:50:12.431829 alsa_mixer-test_event_spurious_LCALTA_25 pass
2688 02:50:12.432145 alsa_mixer-test_get_value_LCALTA_24 pass
2689 02:50:12.437332 alsa_mixer-test_name_LCALTA_24 pass
2690 02:50:12.442884 alsa_mixer-test_write_default_LCALTA_24 skip
2691 02:50:12.443340 alsa_mixer-test_write_valid_LCALTA_24 skip
2692 02:50:12.448503 alsa_mixer-test_write_invalid_LCALTA_24 skip
2693 02:50:12.454073 alsa_mixer-test_event_missing_LCALTA_24 pass
2694 02:50:12.459579 alsa_mixer-test_event_spurious_LCALTA_24 pass
2695 02:50:12.459931 alsa_mixer-test_get_value_LCALTA_23 pass
2696 02:50:12.465149 alsa_mixer-test_name_LCALTA_23 pass
2697 02:50:12.470626 alsa_mixer-test_write_default_LCALTA_23 skip
2698 02:50:12.471101 alsa_mixer-test_write_valid_LCALTA_23 skip
2699 02:50:12.476206 alsa_mixer-test_write_invalid_LCALTA_23 skip
2700 02:50:12.481733 alsa_mixer-test_event_missing_LCALTA_23 pass
2701 02:50:12.482077 alsa_mixer-test_event_spurious_LCALTA_23 pass
2702 02:50:12.487302 alsa_mixer-test_get_value_LCALTA_22 pass
2703 02:50:12.492879 alsa_mixer-test_name_LCALTA_22 pass
2704 02:50:12.493362 alsa_mixer-test_write_default_LCALTA_22 pass
2705 02:50:12.498377 alsa_mixer-test_write_valid_LCALTA_22 pass
2706 02:50:12.504125 alsa_mixer-test_write_invalid_LCALTA_22 pass
2707 02:50:12.504488 alsa_mixer-test_event_missing_LCALTA_22 pass
2708 02:50:12.509465 alsa_mixer-test_event_spurious_LCALTA_22 pass
2709 02:50:12.515062 alsa_mixer-test_get_value_LCALTA_21 pass
2710 02:50:12.515506 alsa_mixer-test_name_LCALTA_21 pass
2711 02:50:12.520554 alsa_mixer-test_write_default_LCALTA_21 pass
2712 02:50:12.526053 alsa_mixer-test_write_valid_LCALTA_21 pass
2713 02:50:12.531627 alsa_mixer-test_write_invalid_LCALTA_21 pass
2714 02:50:12.531927 alsa_mixer-test_event_missing_LCALTA_21 pass
2715 02:50:12.537162 alsa_mixer-test_event_spurious_LCALTA_21 pass
2716 02:50:12.542799 alsa_mixer-test_get_value_LCALTA_20 pass
2717 02:50:12.543093 alsa_mixer-test_name_LCALTA_20 pass
2718 02:50:12.548279 alsa_mixer-test_write_default_LCALTA_20 pass
2719 02:50:12.553869 alsa_mixer-test_write_valid_LCALTA_20 pass
2720 02:50:12.554184 alsa_mixer-test_write_invalid_LCALTA_20 pass
2721 02:50:12.559409 alsa_mixer-test_event_missing_LCALTA_20 pass
2722 02:50:12.565125 alsa_mixer-test_event_spurious_LCALTA_20 pass
2723 02:50:12.565643 alsa_mixer-test_get_value_LCALTA_19 pass
2724 02:50:12.570580 alsa_mixer-test_name_LCALTA_19 pass
2725 02:50:12.576220 alsa_mixer-test_write_default_LCALTA_19 pass
2726 02:50:12.576710 alsa_mixer-test_write_valid_LCALTA_19 pass
2727 02:50:12.581678 alsa_mixer-test_write_invalid_LCALTA_19 pass
2728 02:50:12.587213 alsa_mixer-test_event_missing_LCALTA_19 pass
2729 02:50:12.592756 alsa_mixer-test_event_spurious_LCALTA_19 pass
2730 02:50:12.593253 alsa_mixer-test_get_value_LCALTA_18 pass
2731 02:50:12.598300 alsa_mixer-test_name_LCALTA_18 pass
2732 02:50:12.603913 alsa_mixer-test_write_default_LCALTA_18 pass
2733 02:50:12.604424 alsa_mixer-test_write_valid_LCALTA_18 pass
2734 02:50:12.609362 alsa_mixer-test_write_invalid_LCALTA_18 pass
2735 02:50:12.614919 alsa_mixer-test_event_missing_LCALTA_18 pass
2736 02:50:12.615403 alsa_mixer-test_event_spurious_LCALTA_18 pass
2737 02:50:12.620456 alsa_mixer-test_get_value_LCALTA_17 pass
2738 02:50:12.626192 alsa_mixer-test_name_LCALTA_17 pass
2739 02:50:12.626701 alsa_mixer-test_write_default_LCALTA_17 pass
2740 02:50:12.631571 alsa_mixer-test_write_valid_LCALTA_17 pass
2741 02:50:12.637191 alsa_mixer-test_write_invalid_LCALTA_17 pass
2742 02:50:12.642677 alsa_mixer-test_event_missing_LCALTA_17 pass
2743 02:50:12.643195 alsa_mixer-test_event_spurious_LCALTA_17 pass
2744 02:50:12.648238 alsa_mixer-test_get_value_LCALTA_16 pass
2745 02:50:12.648749 alsa_mixer-test_name_LCALTA_16 pass
2746 02:50:12.653770 alsa_mixer-test_write_default_LCALTA_16 pass
2747 02:50:12.659301 alsa_mixer-test_write_valid_LCALTA_16 pass
2748 02:50:12.664947 alsa_mixer-test_write_invalid_LCALTA_16 pass
2749 02:50:12.665475 alsa_mixer-test_event_missing_LCALTA_16 pass
2750 02:50:12.670457 alsa_mixer-test_event_spurious_LCALTA_16 pass
2751 02:50:12.675966 alsa_mixer-test_get_value_LCALTA_15 pass
2752 02:50:12.676504 alsa_mixer-test_name_LCALTA_15 pass
2753 02:50:12.681498 alsa_mixer-test_write_default_LCALTA_15 pass
2754 02:50:12.687205 alsa_mixer-test_write_valid_LCALTA_15 pass
2755 02:50:12.687732 alsa_mixer-test_write_invalid_LCALTA_15 pass
2756 02:50:12.692601 alsa_mixer-test_event_missing_LCALTA_15 pass
2757 02:50:12.698185 alsa_mixer-test_event_spurious_LCALTA_15 pass
2758 02:50:12.703698 alsa_mixer-test_get_value_LCALTA_14 pass
2759 02:50:12.704249 alsa_mixer-test_name_LCALTA_14 pass
2760 02:50:12.709225 alsa_mixer-test_write_default_LCALTA_14 pass
2761 02:50:12.714772 alsa_mixer-test_write_valid_LCALTA_14 pass
2762 02:50:12.715291 alsa_mixer-test_write_invalid_LCALTA_14 pass
2763 02:50:12.720345 alsa_mixer-test_event_missing_LCALTA_14 pass
2764 02:50:12.725987 alsa_mixer-test_event_spurious_LCALTA_14 pass
2765 02:50:12.726520 alsa_mixer-test_get_value_LCALTA_13 pass
2766 02:50:12.731514 alsa_mixer-test_name_LCALTA_13 pass
2767 02:50:12.737025 alsa_mixer-test_write_default_LCALTA_13 pass
2768 02:50:12.737562 alsa_mixer-test_write_valid_LCALTA_13 pass
2769 02:50:12.742546 alsa_mixer-test_write_invalid_LCALTA_13 pass
2770 02:50:12.748266 alsa_mixer-test_event_missing_LCALTA_13 pass
2771 02:50:12.748791 alsa_mixer-test_event_spurious_LCALTA_13 pass
2772 02:50:12.753631 alsa_mixer-test_get_value_LCALTA_12 pass
2773 02:50:12.759203 alsa_mixer-test_name_LCALTA_12 pass
2774 02:50:12.759714 alsa_mixer-test_write_default_LCALTA_12 pass
2775 02:50:12.764726 alsa_mixer-test_write_valid_LCALTA_12 pass
2776 02:50:12.770253 alsa_mixer-test_write_invalid_LCALTA_12 pass
2777 02:50:12.775845 alsa_mixer-test_event_missing_LCALTA_12 pass
2778 02:50:12.776387 alsa_mixer-test_event_spurious_LCALTA_12 pass
2779 02:50:12.781331 alsa_mixer-test_get_value_LCALTA_11 pass
2780 02:50:12.786927 alsa_mixer-test_name_LCALTA_11 pass
2781 02:50:12.787424 alsa_mixer-test_write_default_LCALTA_11 pass
2782 02:50:12.792447 alsa_mixer-test_write_valid_LCALTA_11 pass
2783 02:50:12.797957 alsa_mixer-test_write_invalid_LCALTA_11 pass
2784 02:50:12.798447 alsa_mixer-test_event_missing_LCALTA_11 pass
2785 02:50:12.803495 alsa_mixer-test_event_spurious_LCALTA_11 pass
2786 02:50:12.809181 alsa_mixer-test_get_value_LCALTA_10 pass
2787 02:50:12.809673 alsa_mixer-test_name_LCALTA_10 pass
2788 02:50:12.814592 alsa_mixer-test_write_default_LCALTA_10 pass
2789 02:50:12.820227 alsa_mixer-test_write_valid_LCALTA_10 pass
2790 02:50:12.820729 alsa_mixer-test_write_invalid_LCALTA_10 pass
2791 02:50:12.825688 alsa_mixer-test_event_missing_LCALTA_10 pass
2792 02:50:12.831211 alsa_mixer-test_event_spurious_LCALTA_10 pass
2793 02:50:12.836767 alsa_mixer-test_get_value_LCALTA_9 pass
2794 02:50:12.837258 alsa_mixer-test_name_LCALTA_9 pass
2795 02:50:12.842326 alsa_mixer-test_write_default_LCALTA_9 pass
2796 02:50:12.847912 alsa_mixer-test_write_valid_LCALTA_9 pass
2797 02:50:12.848426 alsa_mixer-test_write_invalid_LCALTA_9 pass
2798 02:50:12.853425 alsa_mixer-test_event_missing_LCALTA_9 pass
2799 02:50:12.858999 alsa_mixer-test_event_spurious_LCALTA_9 pass
2800 02:50:12.859515 alsa_mixer-test_get_value_LCALTA_8 pass
2801 02:50:12.864548 alsa_mixer-test_name_LCALTA_8 pass
2802 02:50:12.870217 alsa_mixer-test_write_default_LCALTA_8 pass
2803 02:50:12.870760 alsa_mixer-test_write_valid_LCALTA_8 pass
2804 02:50:12.875607 alsa_mixer-test_write_invalid_LCALTA_8 pass
2805 02:50:12.881214 alsa_mixer-test_event_missing_LCALTA_8 pass
2806 02:50:12.881719 alsa_mixer-test_event_spurious_LCALTA_8 pass
2807 02:50:12.886678 alsa_mixer-test_get_value_LCALTA_7 pass
2808 02:50:12.892253 alsa_mixer-test_name_LCALTA_7 pass
2809 02:50:12.892745 alsa_mixer-test_write_default_LCALTA_7 pass
2810 02:50:12.897784 alsa_mixer-test_write_valid_LCALTA_7 pass
2811 02:50:12.903320 alsa_mixer-test_write_invalid_LCALTA_7 pass
2812 02:50:12.903819 alsa_mixer-test_event_missing_LCALTA_7 pass
2813 02:50:12.908932 alsa_mixer-test_event_spurious_LCALTA_7 pass
2814 02:50:12.914426 alsa_mixer-test_get_value_LCALTA_6 pass
2815 02:50:12.914912 alsa_mixer-test_name_LCALTA_6 pass
2816 02:50:12.919956 alsa_mixer-test_write_default_LCALTA_6 pass
2817 02:50:12.925546 alsa_mixer-test_write_valid_LCALTA_6 pass
2818 02:50:12.926052 alsa_mixer-test_write_invalid_LCALTA_6 pass
2819 02:50:12.931227 alsa_mixer-test_event_missing_LCALTA_6 pass
2820 02:50:12.936621 alsa_mixer-test_event_spurious_LCALTA_6 pass
2821 02:50:12.937118 alsa_mixer-test_get_value_LCALTA_5 pass
2822 02:50:12.942214 alsa_mixer-test_name_LCALTA_5 pass
2823 02:50:12.947717 alsa_mixer-test_write_default_LCALTA_5 pass
2824 02:50:12.948252 alsa_mixer-test_write_valid_LCALTA_5 pass
2825 02:50:12.953263 alsa_mixer-test_write_invalid_LCALTA_5 pass
2826 02:50:12.958853 alsa_mixer-test_event_missing_LCALTA_5 pass
2827 02:50:12.959347 alsa_mixer-test_event_spurious_LCALTA_5 pass
2828 02:50:12.964374 alsa_mixer-test_get_value_LCALTA_4 pass
2829 02:50:12.969952 alsa_mixer-test_name_LCALTA_4 pass
2830 02:50:12.970440 alsa_mixer-test_write_default_LCALTA_4 pass
2831 02:50:12.975465 alsa_mixer-test_write_valid_LCALTA_4 pass
2832 02:50:12.981019 alsa_mixer-test_write_invalid_LCALTA_4 pass
2833 02:50:12.981522 alsa_mixer-test_event_missing_LCALTA_4 pass
2834 02:50:12.986568 alsa_mixer-test_event_spurious_LCALTA_4 pass
2835 02:50:12.992237 alsa_mixer-test_get_value_LCALTA_3 pass
2836 02:50:12.992734 alsa_mixer-test_name_LCALTA_3 pass
2837 02:50:12.997632 alsa_mixer-test_write_default_LCALTA_3 pass
2838 02:50:13.003180 alsa_mixer-test_write_valid_LCALTA_3 pass
2839 02:50:13.003675 alsa_mixer-test_write_invalid_LCALTA_3 pass
2840 02:50:13.008752 alsa_mixer-test_event_missing_LCALTA_3 pass
2841 02:50:13.014276 alsa_mixer-test_event_spurious_LCALTA_3 pass
2842 02:50:13.014776 alsa_mixer-test_get_value_LCALTA_2 pass
2843 02:50:13.019817 alsa_mixer-test_name_LCALTA_2 pass
2844 02:50:13.025397 alsa_mixer-test_write_default_LCALTA_2 pass
2845 02:50:13.025903 alsa_mixer-test_write_valid_LCALTA_2 pass
2846 02:50:13.030975 alsa_mixer-test_write_invalid_LCALTA_2 pass
2847 02:50:13.036465 alsa_mixer-test_event_missing_LCALTA_2 pass
2848 02:50:13.041988 alsa_mixer-test_event_spurious_LCALTA_2 pass
2849 02:50:13.042478 alsa_mixer-test_get_value_LCALTA_1 pass
2850 02:50:13.047615 alsa_mixer-test_name_LCALTA_1 pass
2851 02:50:13.048157 alsa_mixer-test_write_default_LCALTA_1 pass
2852 02:50:13.053228 alsa_mixer-test_write_valid_LCALTA_1 pass
2853 02:50:13.058640 alsa_mixer-test_write_invalid_LCALTA_1 pass
2854 02:50:13.064266 alsa_mixer-test_event_missing_LCALTA_1 pass
2855 02:50:13.064768 alsa_mixer-test_event_spurious_LCALTA_1 pass
2856 02:50:13.069761 alsa_mixer-test_get_value_LCALTA_0 pass
2857 02:50:13.070259 alsa_mixer-test_name_LCALTA_0 pass
2858 02:50:13.075301 alsa_mixer-test_write_default_LCALTA_0 pass
2859 02:50:13.080847 alsa_mixer-test_write_valid_LCALTA_0 pass
2860 02:50:13.086369 alsa_mixer-test_write_invalid_LCALTA_0 pass
2861 02:50:13.086864 alsa_mixer-test_event_missing_LCALTA_0 pass
2862 02:50:13.092019 alsa_mixer-test_event_spurious_LCALTA_0 pass
2863 02:50:13.092519 alsa_mixer-test pass
2864 02:50:13.097498 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2865 02:50:13.103000 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2866 02:50:13.108577 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2867 02:50:13.114189 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2868 02:50:13.114691 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2869 02:50:13.119652 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2870 02:50:13.125204 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2871 02:50:13.130728 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2872 02:50:13.136286 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2873 02:50:13.141820 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2874 02:50:13.142320 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2875 02:50:13.147409 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2876 02:50:13.152930 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2877 02:50:13.158472 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2878 02:50:13.164040 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2879 02:50:13.169559 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2880 02:50:13.170052 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2881 02:50:13.175185 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2882 02:50:13.180672 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2883 02:50:13.186220 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2884 02:50:13.191738 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2885 02:50:13.197299 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2886 02:50:13.197811 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2887 02:50:13.202854 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2888 02:50:13.208399 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2889 02:50:13.213951 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2890 02:50:13.219499 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2891 02:50:13.225092 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2892 02:50:13.225636 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2893 02:50:13.230582 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2894 02:50:13.236244 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2895 02:50:13.241645 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2896 02:50:13.247179 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2897 02:50:13.252747 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2898 02:50:13.258334 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2899 02:50:13.258866 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2900 02:50:13.263844 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2901 02:50:13.269387 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2902 02:50:13.274975 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2903 02:50:13.280484 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2904 02:50:13.286030 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2905 02:50:13.286530 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2906 02:50:13.291599 alsa_pcm-test pass
2907 02:50:13.297202 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2908 02:50:13.308272 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2909 02:50:13.313817 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2910 02:50:13.325373 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2911 02:50:13.330483 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 02:50:13.336042 alsa_test-pcmtest-driver pass
2913 02:50:13.341545 alsa_utimer-test_global_wrong_timers_test pass
2914 02:50:13.342069 alsa_utimer-test_timer_f_utimer fail
2915 02:50:13.347054 alsa_utimer-test fail
2916 02:50:13.347574 + ../../utils/send-to-lava.sh ./output/result.txt
2917 02:50:13.352628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2918 02:50:13.353611 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2920 02:50:13.363666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2921 02:50:13.364506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2923 02:50:13.369486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2924 02:50:13.370261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2926 02:50:13.403731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2927 02:50:13.404602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2929 02:50:13.460558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2930 02:50:13.461383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2932 02:50:13.525405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2933 02:50:13.526203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2935 02:50:13.575542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2936 02:50:13.576359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2938 02:50:13.634051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2939 02:50:13.634839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2941 02:50:13.685473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2942 02:50:13.686237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2944 02:50:13.740855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2945 02:50:13.741432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2947 02:50:13.798124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2948 02:50:13.798770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2950 02:50:13.848239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2951 02:50:13.848811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2953 02:50:13.898776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2954 02:50:13.899561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2956 02:50:13.945400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2957 02:50:13.946151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2959 02:50:13.995563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2960 02:50:13.996379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2962 02:50:14.047125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2963 02:50:14.047876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2965 02:50:14.094760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2966 02:50:14.095590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2968 02:50:14.146535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2969 02:50:14.147437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2971 02:50:14.199976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2972 02:50:14.200863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2974 02:50:14.245735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2975 02:50:14.246483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2977 02:50:14.296483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2978 02:50:14.297269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2980 02:50:14.352125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2981 02:50:14.352943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2983 02:50:14.401236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2984 02:50:14.402013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2986 02:50:14.447276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2987 02:50:14.448121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2989 02:50:14.496521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2990 02:50:14.497334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2992 02:50:14.548967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2993 02:50:14.549647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2995 02:50:14.606810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2996 02:50:14.607381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2998 02:50:14.652957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2999 02:50:14.653726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3001 02:50:14.702703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3002 02:50:14.703294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3004 02:50:14.749214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3005 02:50:14.750022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3007 02:50:14.802882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3008 02:50:14.803698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3010 02:50:14.850286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3011 02:50:14.851064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3013 02:50:14.910197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3014 02:50:14.910925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3016 02:50:14.963485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3017 02:50:14.964324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3019 02:50:15.008079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3020 02:50:15.008809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3022 02:50:15.060260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3023 02:50:15.060973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3025 02:50:15.106858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3026 02:50:15.107566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3028 02:50:15.164797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3029 02:50:15.165500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3031 02:50:15.213653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3032 02:50:15.214371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3034 02:50:15.258251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3035 02:50:15.258998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3037 02:50:15.303240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3038 02:50:15.303958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3040 02:50:15.357508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3041 02:50:15.358230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3043 02:50:15.402553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3044 02:50:15.403262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3046 02:50:15.459870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3047 02:50:15.460662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3049 02:50:15.511652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3050 02:50:15.512533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3052 02:50:15.562165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3053 02:50:15.563004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3055 02:50:15.607324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3056 02:50:15.608119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3058 02:50:15.652470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3059 02:50:15.654439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3061 02:50:15.697757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3062 02:50:15.698326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3064 02:50:15.742185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3065 02:50:15.743007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3067 02:50:15.784342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3068 02:50:15.785137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3070 02:50:15.838452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3071 02:50:15.839292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3073 02:50:15.884672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3074 02:50:15.885477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3076 02:50:15.932767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3077 02:50:15.933624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3079 02:50:15.981677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3080 02:50:15.982506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3082 02:50:16.028740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3083 02:50:16.029580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3085 02:50:16.080356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3086 02:50:16.081207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3088 02:50:16.131564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3089 02:50:16.132414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3091 02:50:16.184389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3092 02:50:16.185227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3094 02:50:16.230814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3095 02:50:16.231671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3097 02:50:16.287871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3098 02:50:16.288601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3100 02:50:16.334033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3101 02:50:16.334661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3103 02:50:16.389763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3104 02:50:16.390441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3106 02:50:16.442555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3107 02:50:16.443182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3109 02:50:16.499424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3110 02:50:16.500056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3112 02:50:16.546440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3113 02:50:16.547061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3115 02:50:16.601961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3116 02:50:16.602565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3118 02:50:16.655741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3119 02:50:16.656601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3121 02:50:16.712655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3122 02:50:16.713351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3124 02:50:16.771874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3125 02:50:16.772534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3127 02:50:16.824488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3128 02:50:16.825401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3130 02:50:16.874158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3131 02:50:16.875060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3133 02:50:16.924044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3134 02:50:16.924957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3136 02:50:16.974743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3137 02:50:16.975650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3139 02:50:17.032749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3140 02:50:17.033656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3142 02:50:17.084116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3143 02:50:17.085030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3145 02:50:17.134143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3146 02:50:17.135231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3148 02:50:17.184771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3149 02:50:17.185686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3151 02:50:17.233220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3152 02:50:17.233923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3154 02:50:17.291945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3155 02:50:17.292867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3157 02:50:17.350822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3158 02:50:17.351745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3160 02:50:17.405881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3161 02:50:17.406775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3163 02:50:17.456246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3164 02:50:17.457105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3166 02:50:17.504616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3167 02:50:17.505529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3169 02:50:17.560230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3170 02:50:17.561115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3172 02:50:17.605491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3173 02:50:17.606357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3175 02:50:17.658593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3176 02:50:17.659501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3178 02:50:17.711865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3179 02:50:17.712743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3181 02:50:17.764295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3182 02:50:17.765130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3184 02:50:17.813884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3185 02:50:17.814672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3187 02:50:17.862498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3188 02:50:17.863374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3190 02:50:17.909013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3191 02:50:17.909859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3193 02:50:17.960225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3194 02:50:17.961215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3196 02:50:18.019149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3197 02:50:18.020047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3199 02:50:18.067296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3200 02:50:18.068146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3202 02:50:18.114231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3203 02:50:18.115006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3205 02:50:18.171705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3206 02:50:18.172559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3208 02:50:18.220573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3209 02:50:18.221454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3211 02:50:18.266153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3212 02:50:18.266949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3214 02:50:18.319642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3215 02:50:18.320574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3217 02:50:18.370772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3218 02:50:18.371647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3220 02:50:18.424245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3221 02:50:18.425084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3223 02:50:18.473300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3224 02:50:18.474106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3226 02:50:18.526729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3227 02:50:18.527524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3229 02:50:18.579590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3230 02:50:18.580486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3232 02:50:18.632811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3233 02:50:18.633658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3235 02:50:18.685445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3236 02:50:18.686255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3238 02:50:18.732495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3239 02:50:18.733259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3241 02:50:18.782009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3242 02:50:18.782767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3244 02:50:18.840406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3245 02:50:18.841183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3247 02:50:18.893552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3248 02:50:18.894346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3250 02:50:18.946566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3251 02:50:18.947333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3253 02:50:18.998388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3254 02:50:18.999170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3256 02:50:19.048340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3257 02:50:19.049110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3259 02:50:19.103565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3260 02:50:19.104373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3262 02:50:19.164442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3263 02:50:19.165267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3265 02:50:19.215085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3266 02:50:19.215911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3268 02:50:19.274349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3269 02:50:19.275165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3271 02:50:19.324262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3272 02:50:19.325108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3274 02:50:19.384273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3275 02:50:19.385102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3277 02:50:19.430287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3278 02:50:19.431115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3280 02:50:19.482893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3281 02:50:19.483742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3283 02:50:19.535830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3284 02:50:19.536677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3286 02:50:19.596953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3287 02:50:19.597754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3289 02:50:19.644936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3290 02:50:19.645733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3292 02:50:19.692704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3293 02:50:19.693496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3295 02:50:19.737862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3296 02:50:19.738700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3298 02:50:19.790699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3299 02:50:19.791520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3301 02:50:19.851626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3302 02:50:19.852485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3304 02:50:19.900340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3305 02:50:19.901155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3307 02:50:19.953375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3308 02:50:19.954224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3310 02:50:19.999319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3311 02:50:20.000149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3313 02:50:20.056561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3314 02:50:20.057394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3316 02:50:20.107891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3317 02:50:20.108743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3319 02:50:20.160346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3320 02:50:20.161160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3322 02:50:20.211758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3323 02:50:20.212616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3325 02:50:20.260254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3326 02:50:20.261069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3328 02:50:20.314362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3329 02:50:20.315175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3331 02:50:20.361661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3332 02:50:20.362476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3334 02:50:20.414379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3335 02:50:20.415176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3337 02:50:20.467862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3338 02:50:20.468706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3340 02:50:20.525761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3341 02:50:20.526567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3343 02:50:20.592452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3344 02:50:20.593262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3346 02:50:20.645664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3347 02:50:20.646459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3349 02:50:20.692382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3350 02:50:20.693188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3352 02:50:20.749034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3353 02:50:20.749793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3355 02:50:20.801473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3356 02:50:20.802229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3358 02:50:20.854067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3359 02:50:20.854828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3361 02:50:20.901148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3362 02:50:20.901915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3364 02:50:20.950214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3365 02:50:20.950972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3367 02:50:21.002066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3368 02:50:21.002861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3370 02:50:21.059493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3371 02:50:21.060303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3373 02:50:21.108203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3374 02:50:21.108962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3376 02:50:21.154215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3377 02:50:21.154975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3379 02:50:21.207402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3380 02:50:21.208171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3382 02:50:21.255755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3383 02:50:21.256581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3385 02:50:21.305227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3386 02:50:21.306002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3388 02:50:21.363457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3389 02:50:21.364269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3391 02:50:21.409519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3392 02:50:21.410292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3394 02:50:21.469528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3395 02:50:21.470309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3397 02:50:21.517631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3398 02:50:21.518393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3400 02:50:21.569611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3401 02:50:21.570375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3403 02:50:21.620253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3404 02:50:21.621002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3406 02:50:21.672890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3407 02:50:21.673661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3409 02:50:21.726437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3410 02:50:21.727207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3412 02:50:21.783437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3413 02:50:21.784203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3415 02:50:21.837988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3416 02:50:21.838739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3418 02:50:21.885193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3419 02:50:21.885956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3421 02:50:21.930173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3422 02:50:21.930938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3424 02:50:21.983538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3425 02:50:21.984346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3427 02:50:22.031794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3428 02:50:22.032590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3430 02:50:22.084339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3431 02:50:22.085123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3433 02:50:22.137178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3434 02:50:22.137952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3436 02:50:22.192092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3437 02:50:22.192884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3439 02:50:22.244690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3440 02:50:22.245450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3442 02:50:22.295516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3443 02:50:22.296318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3445 02:50:22.344084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3446 02:50:22.344858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3448 02:50:22.388964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3449 02:50:22.389732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3451 02:50:22.442493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3452 02:50:22.443258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3454 02:50:22.496259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3455 02:50:22.497114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3457 02:50:22.551303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3458 02:50:22.552146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3460 02:50:22.611770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3461 02:50:22.612779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3463 02:50:22.665863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3464 02:50:22.666851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3466 02:50:22.718601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3467 02:50:22.719617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3469 02:50:22.764678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3470 02:50:22.765525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3472 02:50:22.811329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3473 02:50:22.812355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3475 02:50:22.864292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3476 02:50:22.865131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3478 02:50:22.926090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3479 02:50:22.926955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3481 02:50:22.974993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3482 02:50:22.975853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3484 02:50:23.025389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3485 02:50:23.026348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3487 02:50:23.075275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3488 02:50:23.076152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3490 02:50:23.135581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3491 02:50:23.136527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3493 02:50:23.189241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3494 02:50:23.190121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3496 02:50:23.246229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3497 02:50:23.247096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3499 02:50:23.305010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3500 02:50:23.305911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3502 02:50:23.361321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3503 02:50:23.362161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3505 02:50:23.416798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3506 02:50:23.417653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3508 02:50:23.467817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3509 02:50:23.468729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3511 02:50:23.531309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3512 02:50:23.532147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3514 02:50:23.577830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3515 02:50:23.578410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3517 02:50:23.626045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3518 02:50:23.626893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3520 02:50:23.675748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3521 02:50:23.676610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3523 02:50:23.725904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3524 02:50:23.726762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3526 02:50:23.777996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3527 02:50:23.778982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3529 02:50:23.826608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3530 02:50:23.827480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3532 02:50:23.874979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3533 02:50:23.875831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3535 02:50:23.928381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3536 02:50:23.929311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3538 02:50:23.985293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3539 02:50:23.986173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3541 02:50:24.038017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3542 02:50:24.038843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3544 02:50:24.089072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3545 02:50:24.089933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3547 02:50:24.143763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3548 02:50:24.144621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3550 02:50:24.195896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3551 02:50:24.196708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3553 02:50:24.253802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3554 02:50:24.254632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3556 02:50:24.314214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3557 02:50:24.315072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3559 02:50:24.362187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3560 02:50:24.363016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3562 02:50:24.407378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3563 02:50:24.408293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3565 02:50:24.463086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3566 02:50:24.463935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3568 02:50:24.522679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3569 02:50:24.523500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3571 02:50:24.565162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3572 02:50:24.565992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3574 02:50:24.620599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3575 02:50:24.621433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3577 02:50:24.675413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3578 02:50:24.676281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3580 02:50:24.733118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3581 02:50:24.733925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3583 02:50:24.785231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3584 02:50:24.786060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3586 02:50:24.850640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3587 02:50:24.851485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3589 02:50:24.906529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3590 02:50:24.907289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3592 02:50:24.956316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3593 02:50:24.957143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3595 02:50:25.015440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3596 02:50:25.016262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3598 02:50:25.059684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3599 02:50:25.060526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3601 02:50:25.105080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3602 02:50:25.105891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3604 02:50:25.152105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3605 02:50:25.152867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3607 02:50:25.206848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3608 02:50:25.207669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3610 02:50:25.262032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3611 02:50:25.262809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3613 02:50:25.311390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3614 02:50:25.312310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3616 02:50:25.366584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3617 02:50:25.367352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3619 02:50:25.418950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3620 02:50:25.419816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3622 02:50:25.469711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3623 02:50:25.470477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3625 02:50:25.531964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3626 02:50:25.532906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3628 02:50:25.587959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3629 02:50:25.588784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3631 02:50:25.635762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3632 02:50:25.636433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3634 02:50:25.688727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3635 02:50:25.689355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3637 02:50:25.744772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3638 02:50:25.745469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3640 02:50:25.797074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3641 02:50:25.797696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3643 02:50:25.844939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3644 02:50:25.845561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3646 02:50:25.899709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3647 02:50:25.900360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3649 02:50:25.944430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3650 02:50:25.945087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3652 02:50:25.993431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3653 02:50:25.994036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3655 02:50:26.042517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3656 02:50:26.043130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3658 02:50:26.088343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3659 02:50:26.089420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3661 02:50:26.142267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3662 02:50:26.143175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3664 02:50:26.192262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3665 02:50:26.193264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3667 02:50:26.527107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3668 02:50:26.527769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3670 02:50:26.576123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3671 02:50:26.576755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3673 02:50:26.630026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3674 02:50:26.630627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3676 02:50:26.687126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3677 02:50:26.687725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3679 02:50:26.736479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3680 02:50:26.737128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3682 02:50:26.795226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3683 02:50:26.795856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3685 02:50:26.843140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3686 02:50:26.843717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3688 02:50:26.900583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3689 02:50:26.901192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3691 02:50:26.946357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3692 02:50:26.946936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3694 02:50:26.993225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3695 02:50:26.993791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3697 02:50:27.051561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3698 02:50:27.052222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3700 02:50:27.096045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3701 02:50:27.096658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3703 02:50:27.141931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3704 02:50:27.142552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3706 02:50:27.191321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3707 02:50:27.191913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3709 02:50:27.246624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3710 02:50:27.247238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3712 02:50:27.294491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3713 02:50:27.295075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3715 02:50:27.347358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3716 02:50:27.348179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3718 02:50:27.403474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3719 02:50:27.404170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3721 02:50:27.447810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3722 02:50:27.448494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3724 02:50:27.503297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3725 02:50:27.503944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3727 02:50:27.552269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3728 02:50:27.553383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3730 02:50:27.597873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3731 02:50:27.598521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3733 02:50:27.648781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3734 02:50:27.649423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3736 02:50:27.705845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3737 02:50:27.706716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3739 02:50:27.758022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3740 02:50:27.758932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3742 02:50:27.813340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3743 02:50:27.814195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3745 02:50:27.870846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3746 02:50:27.871711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3748 02:50:27.921977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3749 02:50:27.922840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3751 02:50:27.977234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3752 02:50:27.978297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3754 02:50:28.025416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3755 02:50:28.026496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3757 02:50:28.075465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3758 02:50:28.076399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3760 02:50:28.121098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3761 02:50:28.121748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3763 02:50:28.172949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3764 02:50:28.173582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3766 02:50:28.224926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3767 02:50:28.225582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3769 02:50:28.279522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3770 02:50:28.280151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3772 02:50:28.325177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3773 02:50:28.325784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3775 02:50:28.372216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3776 02:50:28.372852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3778 02:50:28.423111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3779 02:50:28.423741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3781 02:50:28.475561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3782 02:50:28.476207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3784 02:50:28.526098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3785 02:50:28.526738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3787 02:50:28.584919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3788 02:50:28.585578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3790 02:50:28.639603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3791 02:50:28.640241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3793 02:50:28.691190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3794 02:50:28.691782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3796 02:50:28.736023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3797 02:50:28.736857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3799 02:50:28.792874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3800 02:50:28.793746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3802 02:50:28.838991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3803 02:50:28.839650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3805 02:50:28.891510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3806 02:50:28.892165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3808 02:50:28.937030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3809 02:50:28.937660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3811 02:50:28.990700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3812 02:50:28.991300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3814 02:50:29.049812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3815 02:50:29.050411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3817 02:50:29.101081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3818 02:50:29.101732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3820 02:50:29.152525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3821 02:50:29.153178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3823 02:50:29.202536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3824 02:50:29.203188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3826 02:50:29.254538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3827 02:50:29.255174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3829 02:50:29.304315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3830 02:50:29.304925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3832 02:50:29.354659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3833 02:50:29.355287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3835 02:50:29.403865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3836 02:50:29.404521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3838 02:50:29.460568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3839 02:50:29.461224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3841 02:50:29.512208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3842 02:50:29.512831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3844 02:50:29.563687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3845 02:50:29.564316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3847 02:50:29.614205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3848 02:50:29.614786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3850 02:50:29.662316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3851 02:50:29.662906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3853 02:50:29.709294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3854 02:50:29.709899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3856 02:50:29.765566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3857 02:50:29.766444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3859 02:50:29.815018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3860 02:50:29.815865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3862 02:50:29.865611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3863 02:50:29.866458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3865 02:50:29.909227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3866 02:50:29.910089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3868 02:50:29.961933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3869 02:50:29.962733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3871 02:50:30.016403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3872 02:50:30.017258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3874 02:50:30.070634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3875 02:50:30.071489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3877 02:50:30.114873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3878 02:50:30.115709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3880 02:50:30.176088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3881 02:50:30.176857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3883 02:50:30.225984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3884 02:50:30.226811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3886 02:50:30.280313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3887 02:50:30.281133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3889 02:50:30.332793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3890 02:50:30.333576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3892 02:50:30.379161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3893 02:50:30.380236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3895 02:50:30.433998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3896 02:50:30.434830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3898 02:50:30.487786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3899 02:50:30.488648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3901 02:50:30.536198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3902 02:50:30.537019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3904 02:50:30.588482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3905 02:50:30.589320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3907 02:50:30.640676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3908 02:50:30.641535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3910 02:50:30.685912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3911 02:50:30.686795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3913 02:50:30.739715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3914 02:50:30.740646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3916 02:50:30.792839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3917 02:50:30.793715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3919 02:50:30.846046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3920 02:50:30.847024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3922 02:50:30.898794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3923 02:50:30.899446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3925 02:50:30.947464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3926 02:50:30.948124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3928 02:50:31.001344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3929 02:50:31.001996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3931 02:50:31.057191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3932 02:50:31.058063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3934 02:50:31.104511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3935 02:50:31.105387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3937 02:50:31.155862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3938 02:50:31.156904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3940 02:50:31.206019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3941 02:50:31.206892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3943 02:50:31.258417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3944 02:50:31.259260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3946 02:50:31.307902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3947 02:50:31.308954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3949 02:50:31.350824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3950 02:50:31.351695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3952 02:50:31.401629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3953 02:50:31.402242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3955 02:50:31.455204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3956 02:50:31.455824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3958 02:50:31.507917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3959 02:50:31.508572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3961 02:50:31.553024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3962 02:50:31.553646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3964 02:50:31.604092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3965 02:50:31.604725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3967 02:50:31.650779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3968 02:50:31.651381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3970 02:50:31.700030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3971 02:50:31.700665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3973 02:50:31.760015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3974 02:50:31.760675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3976 02:50:31.813468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3977 02:50:31.814145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3979 02:50:31.863011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3980 02:50:31.863701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3982 02:50:31.920944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3983 02:50:31.921832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3985 02:50:31.968257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3986 02:50:31.969116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3988 02:50:32.286499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3989 02:50:32.287411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3991 02:50:32.288922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3992 02:50:32.289385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3993 02:50:32.289793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3994 02:50:32.290191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3995 02:50:32.290669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
3996 02:50:32.291343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3998 02:50:32.292686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4000 02:50:32.293962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4002 02:50:32.295189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4004 02:50:32.296425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4006 02:50:32.335032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4007 02:50:32.335903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4009 02:50:32.382092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4010 02:50:32.383002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4012 02:50:32.433737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4013 02:50:32.434613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4015 02:50:32.488717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4016 02:50:32.489576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4018 02:50:32.542303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4019 02:50:32.543167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4021 02:50:32.587198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4022 02:50:32.589052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4024 02:50:32.650392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4025 02:50:32.651244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4027 02:50:32.703974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4028 02:50:32.704645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4030 02:50:32.752627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4031 02:50:32.753285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4033 02:50:32.810567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4034 02:50:32.811205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4036 02:50:32.862156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4037 02:50:32.862788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4039 02:50:32.922352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4040 02:50:32.922997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4042 02:50:32.977349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4043 02:50:32.977985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4045 02:50:33.029648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4046 02:50:33.030284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4048 02:50:33.081936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4049 02:50:33.082565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4051 02:50:33.140872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4052 02:50:33.141489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4054 02:50:33.186003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4055 02:50:33.186605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4057 02:50:33.240007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4058 02:50:33.240643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4060 02:50:33.286560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4061 02:50:33.287185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4063 02:50:33.334703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4064 02:50:33.335338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4066 02:50:33.382861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4067 02:50:33.383509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4069 02:50:33.435052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4070 02:50:33.435676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4072 02:50:33.487095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4073 02:50:33.487705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4075 02:50:33.539266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4076 02:50:33.539879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4078 02:50:33.590820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4079 02:50:33.591434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4081 02:50:33.650991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4082 02:50:33.651590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4084 02:50:33.710734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4085 02:50:33.711355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4087 02:50:33.754578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4088 02:50:33.755184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4090 02:50:33.806064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4091 02:50:33.806702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4093 02:50:33.858852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4094 02:50:33.859486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4096 02:50:33.910996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4097 02:50:33.911898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4099 02:50:33.974562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4100 02:50:33.975446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4102 02:50:34.029939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4103 02:50:34.030791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4105 02:50:34.087209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4106 02:50:34.088104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4108 02:50:34.140598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4109 02:50:34.141462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4111 02:50:34.199252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4112 02:50:34.200117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4114 02:50:34.246166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4115 02:50:34.247024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4117 02:50:34.295964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4118 02:50:34.296852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4120 02:50:34.348244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4121 02:50:34.349068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4123 02:50:34.395197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4124 02:50:34.396103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4126 02:50:34.455384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4127 02:50:34.456224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4129 02:50:34.500819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4130 02:50:34.501657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4132 02:50:34.557211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4133 02:50:34.558040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4135 02:50:34.616359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4136 02:50:34.617191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4138 02:50:34.666782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4139 02:50:34.667480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4141 02:50:34.717663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4142 02:50:34.718372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4144 02:50:34.765345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4145 02:50:34.766172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4147 02:50:34.813964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4148 02:50:34.814813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4150 02:50:34.867409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4151 02:50:34.868292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4153 02:50:34.915480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4154 02:50:34.916387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4156 02:50:34.969933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4157 02:50:34.970783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4159 02:50:35.020858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4160 02:50:35.021749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4162 02:50:35.066970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4163 02:50:35.067818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4165 02:50:35.121456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4166 02:50:35.122313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4168 02:50:35.172952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4169 02:50:35.173783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4171 02:50:35.221674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4172 02:50:35.222307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4174 02:50:35.271815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4175 02:50:35.272677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4177 02:50:35.325702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4178 02:50:35.326484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4180 02:50:35.382453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4181 02:50:35.383262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4183 02:50:35.427204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4184 02:50:35.427931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4186 02:50:35.479452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4187 02:50:35.480204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4189 02:50:35.527437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4190 02:50:35.528161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4192 02:50:35.579742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4193 02:50:35.580420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4195 02:50:35.637649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4196 02:50:35.638297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4198 02:50:35.681175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4199 02:50:35.681829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4201 02:50:35.732160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4203 02:50:35.735162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4204 02:50:35.790893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4205 02:50:35.791528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4207 02:50:35.849705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4208 02:50:35.850350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4210 02:50:35.902970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4211 02:50:35.903616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4213 02:50:35.949851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4214 02:50:35.950451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4216 02:50:35.999266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4217 02:50:36.000086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4219 02:50:36.053730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4220 02:50:36.054534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4222 02:50:36.112712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4223 02:50:36.113509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4225 02:50:36.159022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4226 02:50:36.159807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4228 02:50:36.205368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4229 02:50:36.206159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4231 02:50:36.253170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4232 02:50:36.253959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4234 02:50:36.309737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4235 02:50:36.310527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4237 02:50:36.362324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4238 02:50:36.363120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4240 02:50:36.413633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4241 02:50:36.414434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4243 02:50:36.460551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4244 02:50:36.461354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4246 02:50:36.508373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4247 02:50:36.509170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4249 02:50:36.556542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4250 02:50:36.557335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4252 02:50:36.615620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4253 02:50:36.616443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4255 02:50:36.667012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4256 02:50:36.667801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4258 02:50:36.718970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4259 02:50:36.719935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4261 02:50:36.775224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4262 02:50:36.776132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4264 02:50:36.828334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4265 02:50:36.829185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4267 02:50:36.879444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4268 02:50:36.880323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4270 02:50:36.930414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4271 02:50:36.931255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4273 02:50:36.983173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4274 02:50:36.984070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4276 02:50:37.033105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4277 02:50:37.033956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4279 02:50:37.091361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4280 02:50:37.093658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4282 02:50:37.143707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4283 02:50:37.144797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4285 02:50:37.196328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4286 02:50:37.197419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4288 02:50:37.250406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4289 02:50:37.251823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4291 02:50:37.301623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4292 02:50:37.304479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4294 02:50:37.362351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4295 02:50:37.365340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4297 02:50:37.430961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4298 02:50:37.431991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4300 02:50:37.483392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4301 02:50:37.484058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4303 02:50:37.532017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4304 02:50:37.532893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4306 02:50:37.585492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4307 02:50:37.586131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4309 02:50:37.699842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4310 02:50:37.701484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4312 02:50:37.754523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4313 02:50:37.755518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4315 02:50:37.811880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4316 02:50:37.812587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4318 02:50:37.869169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4319 02:50:37.869860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4321 02:50:37.917250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4322 02:50:37.918354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4324 02:50:37.979229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4325 02:50:37.979888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4327 02:50:38.059140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4328 02:50:38.059806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4330 02:50:38.128332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4331 02:50:38.129010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4333 02:50:38.187090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4334 02:50:38.187728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4336 02:50:38.249059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4337 02:50:38.249687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4339 02:50:38.296655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4340 02:50:38.297416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4342 02:50:38.351686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4343 02:50:38.352420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4345 02:50:38.406050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4346 02:50:38.407005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4348 02:50:38.453814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4349 02:50:38.454684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4351 02:50:38.499955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4352 02:50:38.500817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4354 02:50:38.557298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4355 02:50:38.558331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4357 02:50:38.604849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4359 02:50:38.609961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4360 02:50:38.610447 + set +x
4361 02:50:38.615973 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 830727_1.6.2.4.5>
4362 02:50:38.616458 <LAVA_TEST_RUNNER EXIT>
4363 02:50:38.617104 Received signal: <ENDRUN> 1_kselftest-alsa 830727_1.6.2.4.5
4364 02:50:38.617545 Ending use of test pattern.
4365 02:50:38.617946 Ending test lava.1_kselftest-alsa (830727_1.6.2.4.5), duration 41.40
4367 02:50:38.619454 ok: lava_test_shell seems to have completed
4368 02:50:38.641565 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4369 02:50:38.643296 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4370 02:50:38.643868 end: 3 lava-test-retry (duration 00:00:42) [common]
4371 02:50:38.644475 start: 4 finalize (timeout 00:06:07) [common]
4372 02:50:38.645035 start: 4.1 power-off (timeout 00:00:30) [common]
4373 02:50:38.645967 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4374 02:50:38.681588 >> OK - accepted request
4375 02:50:38.683604 Returned 0 in 0 seconds
4376 02:50:38.784659 end: 4.1 power-off (duration 00:00:00) [common]
4378 02:50:38.785669 start: 4.2 read-feedback (timeout 00:06:07) [common]
4379 02:50:38.786313 Listened to connection for namespace 'common' for up to 1s
4380 02:50:39.786518 Finalising connection for namespace 'common'
4381 02:50:39.787023 Disconnecting from shell: Finalise
4382 02:50:39.787313 / #
4383 02:50:39.888045 end: 4.2 read-feedback (duration 00:00:01) [common]
4384 02:50:39.888581 end: 4 finalize (duration 00:00:01) [common]
4385 02:50:39.888940 Cleaning after the job
4386 02:50:39.889292 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/ramdisk
4387 02:50:39.897178 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/kernel
4388 02:50:39.913390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/dtb
4389 02:50:39.914354 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/nfsrootfs
4390 02:50:39.942740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/830727/tftp-deploy-2tyca09k/modules
4391 02:50:39.949934 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/830727
4392 02:50:43.418683 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/830727
4393 02:50:43.419260 Job finished correctly