Boot log: beaglebone-black

    1 08:40:35.822849  lava-dispatcher, installed at version: 2023.08
    2 08:40:35.823172  start: 0 validate
    3 08:40:35.823375  Start time: 2024-10-20 08:40:35.823363+00:00 (UTC)
    4 08:40:35.823624  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 08:40:36.314122  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
    6 08:40:36.435611  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 08:40:36.563264  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 08:40:36.676927  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
    9 08:40:36.795449  validate duration: 0.97
   11 08:40:36.796244  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 08:40:36.796576  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 08:40:36.796919  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 08:40:36.797382  Not decompressing ramdisk as can be used compressed.
   15 08:40:36.797678  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 08:40:36.797921  saving as /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/ramdisk/initrd.cpio.gz
   17 08:40:36.798166  total size: 4775763 (4 MB)
   18 08:40:37.026735  progress   0 % (0 MB)
   19 08:40:37.362486  progress   5 % (0 MB)
   20 08:40:37.472749  progress  10 % (0 MB)
   21 08:40:37.491893  progress  15 % (0 MB)
   22 08:40:37.709917  progress  20 % (0 MB)
   23 08:40:37.739318  progress  25 % (1 MB)
   24 08:40:37.762381  progress  30 % (1 MB)
   25 08:40:37.768140  progress  35 % (1 MB)
   26 08:40:37.844774  progress  40 % (1 MB)
   27 08:40:37.874673  progress  45 % (2 MB)
   28 08:40:37.941815  progress  50 % (2 MB)
   29 08:40:37.983093  progress  55 % (2 MB)
   30 08:40:38.049417  progress  60 % (2 MB)
   31 08:40:38.088201  progress  65 % (2 MB)
   32 08:40:38.154447  progress  70 % (3 MB)
   33 08:40:38.187128  progress  75 % (3 MB)
   34 08:40:38.216169  progress  80 % (3 MB)
   35 08:40:38.287132  progress  85 % (3 MB)
   36 08:40:38.322456  progress  90 % (4 MB)
   37 08:40:38.387640  progress  95 % (4 MB)
   38 08:40:38.424131  progress 100 % (4 MB)
   39 08:40:38.425092  4 MB downloaded in 1.63 s (2.80 MB/s)
   40 08:40:38.425708  end: 1.1.1 http-download (duration 00:00:02) [common]
   42 08:40:38.426803  end: 1.1 download-retry (duration 00:00:02) [common]
   43 08:40:38.427175  start: 1.2 download-retry (timeout 00:09:58) [common]
   44 08:40:38.427547  start: 1.2.1 http-download (timeout 00:09:58) [common]
   45 08:40:38.428068  downloading http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/kernel/zImage
   46 08:40:38.428365  saving as /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/kernel/zImage
   47 08:40:38.428655  total size: 11440640 (10 MB)
   48 08:40:38.428923  No compression specified
   49 08:40:38.547350  progress   0 % (0 MB)
   50 08:40:38.893277  progress   5 % (0 MB)
   51 08:40:39.115719  progress  10 % (1 MB)
   52 08:40:39.311853  progress  15 % (1 MB)
   53 08:40:39.463360  progress  20 % (2 MB)
   54 08:40:39.687453  progress  25 % (2 MB)
   55 08:40:39.907301  progress  30 % (3 MB)
   56 08:40:40.129316  progress  35 % (3 MB)
   57 08:40:40.346634  progress  40 % (4 MB)
   58 08:40:40.566066  progress  45 % (4 MB)
   59 08:40:40.777296  progress  50 % (5 MB)
   60 08:40:40.917626  progress  55 % (6 MB)
   61 08:40:41.133860  progress  60 % (6 MB)
   62 08:40:41.343357  progress  65 % (7 MB)
   63 08:40:41.557661  progress  70 % (7 MB)
   64 08:40:41.697328  progress  75 % (8 MB)
   65 08:40:41.911603  progress  80 % (8 MB)
   66 08:40:42.118690  progress  85 % (9 MB)
   67 08:40:42.259857  progress  90 % (9 MB)
   68 08:40:42.470849  progress  95 % (10 MB)
   69 08:40:42.677787  progress 100 % (10 MB)
   70 08:40:42.678226  10 MB downloaded in 4.25 s (2.57 MB/s)
   71 08:40:42.678671  end: 1.2.1 http-download (duration 00:00:04) [common]
   73 08:40:42.679495  end: 1.2 download-retry (duration 00:00:04) [common]
   74 08:40:42.679792  start: 1.3 download-retry (timeout 00:09:54) [common]
   75 08:40:42.680077  start: 1.3.1 http-download (timeout 00:09:54) [common]
   76 08:40:42.680476  downloading http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
   77 08:40:42.680706  saving as /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/dtb/am335x-boneblack.dtb
   78 08:40:42.680898  total size: 70568 (0 MB)
   79 08:40:42.681032  No compression specified
   80 08:40:42.799208  progress  46 % (0 MB)
   81 08:40:42.802037  progress  92 % (0 MB)
   82 08:40:42.803001  progress 100 % (0 MB)
   83 08:40:42.803390  0 MB downloaded in 0.12 s (0.55 MB/s)
   84 08:40:42.803795  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 08:40:42.804592  end: 1.3 download-retry (duration 00:00:00) [common]
   87 08:40:42.804900  start: 1.4 download-retry (timeout 00:09:54) [common]
   88 08:40:42.805186  start: 1.4.1 http-download (timeout 00:09:54) [common]
   89 08:40:42.805546  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 08:40:42.805772  saving as /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/nfsrootfs/full.rootfs.tar
   91 08:40:42.805985  total size: 117747780 (112 MB)
   92 08:40:42.806208  Using unxz to decompress xz
   93 08:40:42.921604  progress   0 % (0 MB)
   94 08:40:45.396834  progress   5 % (5 MB)
   95 08:40:47.404773  progress  10 % (11 MB)
   96 08:40:49.841866  progress  15 % (16 MB)
   97 08:40:55.196808  progress  20 % (22 MB)
   98 08:41:02.031096  progress  25 % (28 MB)
   99 08:41:08.669755  progress  30 % (33 MB)
  100 08:41:11.238231  progress  35 % (39 MB)
  101 08:41:12.678688  progress  40 % (44 MB)
  102 08:41:13.695800  progress  45 % (50 MB)
  103 08:41:14.507075  progress  50 % (56 MB)
  104 08:41:15.193079  progress  55 % (61 MB)
  105 08:41:15.781960  progress  60 % (67 MB)
  106 08:41:16.447574  progress  65 % (73 MB)
  107 08:41:17.813129  progress  70 % (78 MB)
  108 08:41:19.944425  progress  75 % (84 MB)
  109 08:41:22.149769  progress  80 % (89 MB)
  110 08:41:24.212768  progress  85 % (95 MB)
  111 08:41:26.291434  progress  90 % (101 MB)
  112 08:41:28.200440  progress  95 % (106 MB)
  113 08:41:30.108380  progress 100 % (112 MB)
  114 08:41:30.111936  112 MB downloaded in 47.31 s (2.37 MB/s)
  115 08:41:30.112332  end: 1.4.1 http-download (duration 00:00:47) [common]
  117 08:41:30.113076  end: 1.4 download-retry (duration 00:00:47) [common]
  118 08:41:30.113304  start: 1.5 download-retry (timeout 00:09:07) [common]
  119 08:41:30.113528  start: 1.5.1 http-download (timeout 00:09:07) [common]
  120 08:41:30.113859  downloading http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
  121 08:41:30.114036  saving as /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/modules/modules.tar
  122 08:41:30.114203  total size: 6603568 (6 MB)
  123 08:41:30.114373  Using unxz to decompress xz
  124 08:41:30.232959  progress   0 % (0 MB)
  125 08:41:30.346320  progress   5 % (0 MB)
  126 08:41:30.457972  progress  10 % (0 MB)
  127 08:41:30.568692  progress  15 % (0 MB)
  128 08:41:30.679171  progress  20 % (1 MB)
  129 08:41:30.788683  progress  25 % (1 MB)
  130 08:41:30.863941  progress  30 % (1 MB)
  131 08:41:30.931894  progress  35 % (2 MB)
  132 08:41:31.041594  progress  40 % (2 MB)
  133 08:41:31.150006  progress  45 % (2 MB)
  134 08:41:31.258821  progress  50 % (3 MB)
  135 08:41:31.366665  progress  55 % (3 MB)
  136 08:41:31.474148  progress  60 % (3 MB)
  137 08:41:31.582236  progress  65 % (4 MB)
  138 08:41:31.692537  progress  70 % (4 MB)
  139 08:41:31.799317  progress  75 % (4 MB)
  140 08:41:31.903066  progress  80 % (5 MB)
  141 08:41:31.935810  progress  85 % (5 MB)
  142 08:41:32.048620  progress  90 % (5 MB)
  143 08:41:32.153968  progress  95 % (6 MB)
  144 08:41:32.256696  progress 100 % (6 MB)
  145 08:41:32.259836  6 MB downloaded in 2.15 s (2.94 MB/s)
  146 08:41:32.260255  end: 1.5.1 http-download (duration 00:00:02) [common]
  148 08:41:32.261021  end: 1.5 download-retry (duration 00:00:02) [common]
  149 08:41:32.261259  start: 1.6 prepare-tftp-overlay (timeout 00:09:05) [common]
  150 08:41:32.261496  start: 1.6.1 extract-nfsrootfs (timeout 00:09:05) [common]
  151 08:41:37.803790  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n
  152 08:41:37.804079  end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
  153 08:41:37.804207  start: 1.6.2 lava-overlay (timeout 00:08:59) [common]
  154 08:41:37.804475  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt
  155 08:41:37.804642  makedir: /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin
  156 08:41:37.804804  makedir: /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/tests
  157 08:41:37.804932  makedir: /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/results
  158 08:41:37.805072  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-add-keys
  159 08:41:37.805272  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-add-sources
  160 08:41:37.805442  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-background-process-start
  161 08:41:37.805610  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-background-process-stop
  162 08:41:37.805790  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-common-functions
  163 08:41:37.805956  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-echo-ipv4
  164 08:41:37.806121  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-install-packages
  165 08:41:37.806283  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-installed-packages
  166 08:41:37.806443  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-os-build
  167 08:41:37.806605  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-probe-channel
  168 08:41:37.806769  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-probe-ip
  169 08:41:37.806935  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-target-ip
  170 08:41:37.807099  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-target-mac
  171 08:41:37.807260  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-target-storage
  172 08:41:37.807427  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-case
  173 08:41:37.807593  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-event
  174 08:41:37.807753  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-feedback
  175 08:41:37.807919  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-raise
  176 08:41:37.808080  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-reference
  177 08:41:37.808241  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-runner
  178 08:41:37.808401  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-set
  179 08:41:37.808561  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-test-shell
  180 08:41:37.808863  Updating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-add-keys (debian)
  181 08:41:37.809078  Updating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-add-sources (debian)
  182 08:41:37.809260  Updating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-install-packages (debian)
  183 08:41:37.809442  Updating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-installed-packages (debian)
  184 08:41:37.809623  Updating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/bin/lava-os-build (debian)
  185 08:41:37.809783  Creating /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/environment
  186 08:41:37.809906  LAVA metadata
  187 08:41:37.810001  - LAVA_JOB_ID=1209565
  188 08:41:37.810091  - LAVA_DISPATCHER_IP=192.168.11.5
  189 08:41:37.810227  start: 1.6.2.1 ssh-authorize (timeout 00:08:59) [common]
  190 08:41:37.810542  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 08:41:37.810700  start: 1.6.2.2 lava-vland-overlay (timeout 00:08:59) [common]
  192 08:41:37.810790  skipped lava-vland-overlay
  193 08:41:37.810896  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 08:41:37.811008  start: 1.6.2.3 lava-multinode-overlay (timeout 00:08:59) [common]
  195 08:41:37.811099  skipped lava-multinode-overlay
  196 08:41:37.811205  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 08:41:37.811321  start: 1.6.2.4 test-definition (timeout 00:08:59) [common]
  198 08:41:37.811418  Loading test definitions
  199 08:41:37.811533  start: 1.6.2.4.1 inline-repo-action (timeout 00:08:59) [common]
  200 08:41:37.811627  Using /lava-1209565 at stage 0
  201 08:41:37.812027  uuid=1209565_1.6.2.4.1 testdef=None
  202 08:41:37.812144  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 08:41:37.812258  start: 1.6.2.4.2 test-overlay (timeout 00:08:59) [common]
  204 08:41:37.812868  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 08:41:37.813187  start: 1.6.2.4.3 test-install-overlay (timeout 00:08:59) [common]
  207 08:41:37.813954  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 08:41:37.814282  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:08:59) [common]
  210 08:41:37.815019  runner path: /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/0/tests/0_timesync-off test_uuid 1209565_1.6.2.4.1
  211 08:41:37.815208  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 08:41:37.815532  start: 1.6.2.4.5 git-repo-action (timeout 00:08:59) [common]
  214 08:41:37.815629  Using /lava-1209565 at stage 0
  215 08:41:37.815761  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 08:41:37.815858  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/0/tests/1_kselftest-dt'
  217 08:41:43.318576  Running '/usr/bin/git checkout kernelci.org
  218 08:41:43.538509  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 08:41:43.539539  uuid=1209565_1.6.2.4.5 testdef=None
  220 08:41:43.539809  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 08:41:43.540418  start: 1.6.2.4.6 test-overlay (timeout 00:08:53) [common]
  223 08:41:43.542433  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 08:41:43.543068  start: 1.6.2.4.7 test-install-overlay (timeout 00:08:53) [common]
  226 08:41:43.545871  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 08:41:43.546540  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:53) [common]
  229 08:41:43.549071  runner path: /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/0/tests/1_kselftest-dt test_uuid 1209565_1.6.2.4.5
  230 08:41:43.549191  BOARD='beaglebone-black'
  231 08:41:43.549286  BRANCH='mainline'
  232 08:41:43.549377  SKIPFILE='/dev/null'
  233 08:41:43.549467  SKIP_INSTALL='True'
  234 08:41:43.549556  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
  235 08:41:43.549646  TST_CASENAME=''
  236 08:41:43.549735  TST_CMDFILES='dt'
  237 08:41:43.549931  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 08:41:43.550248  Creating lava-test-runner.conf files
  240 08:41:43.550340  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1209565/lava-overlay-0bn4pvnt/lava-1209565/0 for stage 0
  241 08:41:43.550466  - 0_timesync-off
  242 08:41:43.550562  - 1_kselftest-dt
  243 08:41:43.550715  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 08:41:43.550836  start: 1.6.2.5 compress-overlay (timeout 00:08:53) [common]
  245 08:41:52.036299  end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
  246 08:41:52.036491  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:45) [common]
  247 08:41:52.036615  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 08:41:52.036761  end: 1.6.2 lava-overlay (duration 00:00:14) [common]
  249 08:41:52.036884  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:45) [common]
  250 08:41:52.160507  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 08:41:52.160816  start: 1.6.4 extract-modules (timeout 00:08:45) [common]
  252 08:41:52.160982  extracting modules file /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n
  253 08:41:52.462409  extracting modules file /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1209565/extract-overlay-ramdisk-c9wgcnym/ramdisk
  254 08:41:52.768067  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 08:41:52.768271  start: 1.6.5 apply-overlay-tftp (timeout 00:08:44) [common]
  256 08:41:52.768385  [common] Applying overlay to NFS
  257 08:41:52.768476  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1209565/compress-overlay-s3j2kl3p/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n
  258 08:41:53.955804  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  259 08:41:53.956002  start: 1.6.6 prepare-kernel (timeout 00:08:43) [common]
  260 08:41:53.956125  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:43) [common]
  261 08:41:53.956250  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 08:41:53.956365  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 08:41:53.956482  start: 1.6.7 configure-preseed-file (timeout 00:08:43) [common]
  264 08:41:53.956593  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 08:41:53.956721  start: 1.6.8 compress-ramdisk (timeout 00:08:43) [common]
  266 08:41:53.956830  Building ramdisk /var/lib/lava/dispatcher/tmp/1209565/extract-overlay-ramdisk-c9wgcnym/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1209565/extract-overlay-ramdisk-c9wgcnym/ramdisk
  267 08:41:54.265828  >> 74892 blocks

  268 08:41:56.199119  Adding RAMdisk u-boot header.
  269 08:41:56.199398  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1209565/extract-overlay-ramdisk-c9wgcnym/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1209565/extract-overlay-ramdisk-c9wgcnym/ramdisk.cpio.gz.uboot
  270 08:41:56.352084  output: Image Name:   
  271 08:41:56.352426  output: Created:      Sun Oct 20 08:41:56 2024
  272 08:41:56.352638  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 08:41:56.352882  output: Data Size:    14791163 Bytes = 14444.50 KiB = 14.11 MiB
  274 08:41:56.353084  output: Load Address: 00000000
  275 08:41:56.353278  output: Entry Point:  00000000
  276 08:41:56.353471  output: 
  277 08:41:56.353781  rename /var/lib/lava/dispatcher/tmp/1209565/extract-overlay-ramdisk-c9wgcnym/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot
  278 08:41:56.354108  end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
  279 08:41:56.354378  end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
  280 08:41:56.354640  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
  281 08:41:56.354848  No LXC device requested
  282 08:41:56.355093  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 08:41:56.355346  start: 1.8 deploy-device-env (timeout 00:08:40) [common]
  284 08:41:56.355593  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 08:41:56.355791  Checking files for TFTP limit of 4294967296 bytes.
  286 08:41:56.357050  end: 1 tftp-deploy (duration 00:01:20) [common]
  287 08:41:56.357319  start: 2 uboot-action (timeout 00:05:00) [common]
  288 08:41:56.357578  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 08:41:56.357823  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 08:41:56.358072  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 08:41:56.358443  substitutions:
  292 08:41:56.358645  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 08:41:56.358841  - {DTB_ADDR}: 0x88000000
  294 08:41:56.359032  - {DTB}: 1209565/tftp-deploy-cjedyn5k/dtb/am335x-boneblack.dtb
  295 08:41:56.359222  - {INITRD}: 1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot
  296 08:41:56.359410  - {KERNEL_ADDR}: 0x82000000
  297 08:41:56.359598  - {KERNEL}: 1209565/tftp-deploy-cjedyn5k/kernel/zImage
  298 08:41:56.359784  - {LAVA_MAC}: None
  299 08:41:56.359982  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n
  300 08:41:56.360171  - {NFS_SERVER_IP}: 192.168.11.5
  301 08:41:56.360354  - {PRESEED_CONFIG}: None
  302 08:41:56.360536  - {PRESEED_LOCAL}: None
  303 08:41:56.360739  - {RAMDISK_ADDR}: 0x83000000
  304 08:41:56.360868  - {RAMDISK}: 1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot
  305 08:41:56.360961  - {ROOT_PART}: None
  306 08:41:56.361051  - {ROOT}: None
  307 08:41:56.361142  - {SERVER_IP}: 192.168.11.5
  308 08:41:56.361232  - {TEE_ADDR}: 0x83000000
  309 08:41:56.361323  - {TEE}: None
  310 08:41:56.361414  Parsed boot commands:
  311 08:41:56.361503  - setenv autoload no
  312 08:41:56.361592  - setenv initrd_high 0xffffffff
  313 08:41:56.361683  - setenv fdt_high 0xffffffff
  314 08:41:56.361772  - dhcp
  315 08:41:56.361861  - setenv serverip 192.168.11.5
  316 08:41:56.361952  - tftp 0x82000000 1209565/tftp-deploy-cjedyn5k/kernel/zImage
  317 08:41:56.362043  - tftp 0x83000000 1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot
  318 08:41:56.362134  - setenv initrd_size ${filesize}
  319 08:41:56.362223  - tftp 0x88000000 1209565/tftp-deploy-cjedyn5k/dtb/am335x-boneblack.dtb
  320 08:41:56.362313  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 08:41:56.362408  - bootz 0x82000000 0x83000000 0x88000000
  322 08:41:56.362526  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 08:41:56.362868  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 08:41:56.362966  [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
  326 08:41:56.721839  Setting prompt string to ['lava-test: # ']
  327 08:41:56.722265  end: 2.3 connect-device (duration 00:00:00) [common]
  328 08:41:56.722413  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 08:41:56.722592  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 08:41:56.722721  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 08:41:56.723057  Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
  332 08:41:57.086396  Returned 0 in 0 seconds
  333 08:41:57.187397  end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
  335 08:41:57.188251  end: 2.4.1 reset-device (duration 00:00:00) [common]
  336 08:41:57.188560  start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
  337 08:41:57.188857  Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
  338 08:41:57.189101  bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
  339 08:41:57.189830  Trying 127.0.0.1...
  340 08:41:57.190056  Connected to 127.0.0.1.
  341 08:41:57.190258  Escape character is '^]'.
  342 08:42:02.090160  
  343 08:42:02.093806  U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
  344 08:42:02.150284  Trying to boot from MMC2
  345 08:42:02.198774  Loading Environment from EXT4... Card did not respond to voltage select!
  346 08:42:02.265863  
  347 08:42:02.266132  
  348 08:42:02.271479  U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
  349 08:42:02.271755  
  350 08:42:02.276429  CPU  : AM335X-GP rev 2.1
  351 08:42:02.330284  I2C:   ready
  352 08:42:02.330560  DRAM:  512 MiB
  353 08:42:02.384606  No match for driver 'omap_hsmmc'
  354 08:42:02.390100  No match for driver 'omap_hsmmc'
  355 08:42:02.390379  Some drivers were not found
  356 08:42:02.396476  Reset Source: Power-on reset has occurred.
  357 08:42:02.396805  RTC 32KCLK Source: External.
  358 08:42:02.404045  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  359 08:42:02.417268  Loading Environment from EXT4... Card did not respond to voltage select!
  360 08:42:02.481686  Board: BeagleBone Black
  361 08:42:02.485714  <ethaddr> not set. Validating first E-fuse MAC
  362 08:42:02.542201  BeagleBone Black:
  363 08:42:02.542488  BeagleBone: cape eeprom: i2c_probe: 0x54:
  364 08:42:02.547791  BeagleBone: cape eeprom: i2c_probe: 0x55:
  365 08:42:02.553789  BeagleBone: cape eeprom: i2c_probe: 0x56:
  366 08:42:02.554057  BeagleBone: cape eeprom: i2c_probe: 0x57:
  367 08:42:02.558716  Net:   eth0: MII MODE
  368 08:42:02.568191  cpsw, usb_ether
  369 08:42:02.568457  Press SPACE to abort autoboot in 2 seconds
  370 08:42:02.619237  end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
  371 08:42:02.619602  start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
  372 08:42:02.619862  Setting prompt string to ['=> ']
  373 08:42:02.620122  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
  374 08:42:02.623483  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  375 08:42:02.623785  Sending with 10 millisecond of delay
  377 08:42:03.758396   => setenv autoload no
  378 08:42:03.768866  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
  379 08:42:03.771191  setenv autoload no
  380 08:42:03.771646  Sending with 10 millisecond of delay
  382 08:42:05.568533  => setenv initrd_high 0xffffffff
  383 08:42:05.579038  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
  384 08:42:05.579511  setenv initrd_high 0xffffffff
  385 08:42:05.579953  Sending with 10 millisecond of delay
  387 08:42:07.196148  => setenv fdt_high 0xffffffff
  388 08:42:07.206618  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
  389 08:42:07.207077  setenv fdt_high 0xffffffff
  390 08:42:07.207519  Sending with 10 millisecond of delay
  392 08:42:07.498924  => dhcp
  393 08:42:07.509310  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
  394 08:42:07.509747  dhcp
  395 08:42:07.510247  link up on port 0, speed 100, full duplex
  396 08:42:07.510509  BOOTP broadcast 1
  397 08:42:07.517609  DHCP client bound to address 192.168.11.6 (4 ms)
  398 08:42:07.518042  Sending with 10 millisecond of delay
  400 08:42:09.254798  => setenv serverip 192.168.11.5
  401 08:42:09.265280  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
  402 08:42:09.265743  setenv serverip 192.168.11.5
  403 08:42:09.266186  Sending with 10 millisecond of delay
  405 08:42:12.809078  => tftp 0x82000000 1209565/tftp-deploy-cjedyn5k/kernel/zImage
  406 08:42:12.819572  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
  407 08:42:12.820035  tftp 0x82000000 1209565/tftp-deploy-cjedyn5k/kernel/zImage
  408 08:42:12.820261  link up on port 0, speed 100, full duplex
  409 08:42:12.820471  Using cpsw device
  410 08:42:12.823945  TFTP from server 192.168.11.5; our IP address is 192.168.11.6
  411 08:42:12.829545  Filename '1209565/tftp-deploy-cjedyn5k/kernel/zImage'.
  412 08:42:12.836498  Load address: 0x82000000
  413 08:42:13.031740  Loading: *#################################################################
  414 08:42:13.192870  	 #################################################################
  415 08:42:13.368096  	 #################################################################
  416 08:42:13.563450  	 #################################################################
  417 08:42:13.737685  	 #################################################################
  418 08:42:13.912195  	 #################################################################
  419 08:42:14.084054  	 #################################################################
  420 08:42:14.258243  	 #################################################################
  421 08:42:14.432989  	 #################################################################
  422 08:42:14.606841  	 #################################################################
  423 08:42:14.804439  	 #################################################################
  424 08:42:14.958262  	 #################################################################
  425 08:42:14.958512  	 5.1 MiB/s
  426 08:42:14.958718  done
  427 08:42:14.965173  Bytes transferred = 11440640 (ae9200 hex)
  428 08:42:14.965690  Sending with 10 millisecond of delay
  430 08:42:19.472415  => tftp 0x83000000 1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot
  431 08:42:19.482933  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
  432 08:42:19.483441  tftp 0x83000000 1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot
  433 08:42:19.483692  link up on port 0, speed 100, full duplex
  434 08:42:19.483926  Using cpsw device
  435 08:42:19.487135  TFTP from server 192.168.11.5; our IP address is 192.168.11.6
  436 08:42:19.501085  Filename '1209565/tftp-deploy-cjedyn5k/ramdisk/ramdisk.cpio.gz.uboot'.
  437 08:42:19.501352  Load address: 0x83000000
  438 08:42:19.696238  Loading: *#################################################################
  439 08:42:19.870974  	 #################################################################
  440 08:42:20.043479  	 #################################################################
  441 08:42:20.216851  	 #################################################################
  442 08:42:20.391581  	 #################################################################
  443 08:42:20.566329  	 #################################################################
  444 08:42:20.740687  	 #################################################################
  445 08:42:20.936937  	 #################################################################
  446 08:42:21.108799  	 #################################################################
  447 08:42:21.283566  	 #################################################################
  448 08:42:21.458027  	 #################################################################
  449 08:42:21.631837  	 #################################################################
  450 08:42:21.806625  	 #################################################################
  451 08:42:21.981592  	 #################################################################
  452 08:42:22.175469  	 #################################################################
  453 08:42:22.251991  	 #################################
  454 08:42:22.252280  	 5.1 MiB/s
  455 08:42:22.252504  done
  456 08:42:22.255518  Bytes transferred = 14791227 (e1b23b hex)
  457 08:42:22.256005  Sending with 10 millisecond of delay
  459 08:42:24.113025  => setenv initrd_size ${filesize}
  460 08:42:24.123522  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  461 08:42:24.123986  setenv initrd_size ${filesize}
  462 08:42:24.124426  Sending with 10 millisecond of delay
  464 08:42:28.330218  => tftp 0x88000000 1209565/tftp-deploy-cjedyn5k/dtb/am335x-boneblack.dtb
  465 08:42:28.340672  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
  466 08:42:28.341137  tftp 0x88000000 1209565/tftp-deploy-cjedyn5k/dtb/am335x-boneblack.dtb
  467 08:42:28.341372  link up on port 0, speed 100, full duplex
  468 08:42:28.341594  Using cpsw device
  469 08:42:28.344910  TFTP from server 192.168.11.5; our IP address is 192.168.11.6
  470 08:42:28.358414  Filename '1209565/tftp-deploy-cjedyn5k/dtb/am335x-boneblack.dtb'.
  471 08:42:28.358690  Load address: 0x88000000
  472 08:42:28.373979  Loading: *#####
  473 08:42:28.374245  	 4.5 MiB/s
  474 08:42:28.374463  done
  475 08:42:28.374668  Bytes transferred = 70568 (113a8 hex)
  476 08:42:28.377488  Sending with 10 millisecond of delay
  478 08:42:41.675212  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  479 08:42:41.685693  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
  480 08:42:41.686150  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  481 08:42:41.686604  Sending with 10 millisecond of delay
  483 08:42:44.025091  => bootz 0x82000000 0x83000000 0x88000000
  484 08:42:44.035569  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  485 08:42:44.035931  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
  486 08:42:44.036525  bootz 0x82000000 0x83000000 0x88000000
  487 08:42:44.036801  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  488 08:42:44.037300     Image Name:   
  489 08:42:44.037550     Created:      2024-10-20   8:41:56 UTC
  490 08:42:44.042664     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  491 08:42:44.048284     Data Size:    14791163 Bytes = 14.1 MiB
  492 08:42:44.048522     Load Address: 00000000
  493 08:42:44.055552     Entry Point:  00000000
  494 08:42:44.192843     Verifying Checksum ... OK
  495 08:42:44.193163  ## Flattened Device Tree blob at 88000000
  496 08:42:44.199282     Booting using the fdt blob at 0x88000000
  497 08:42:44.204202     Using Device Tree in place at 88000000, end 880143a7
  498 08:42:44.211846  
  499 08:42:44.212071  Starting kernel ...
  500 08:42:44.212278  
  501 08:42:44.212820  end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
  502 08:42:44.213111  start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
  503 08:42:44.213350  Setting prompt string to ['Linux version [0-9]']
  504 08:42:44.213587  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  505 08:42:44.213834  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  506 08:42:45.054425  [    0.000000] Booting Linux on physical CPU 0x0
  507 08:42:45.060332  start: 2.4.4.1 login-action (timeout 00:04:11) [common]
  508 08:42:45.060640  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  509 08:42:45.060929  Setting prompt string to []
  510 08:42:45.061226  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  511 08:42:45.061506  Using line separator: #'\n'#
  512 08:42:45.061752  No login prompt set.
  513 08:42:45.062006  Parsing kernel messages
  514 08:42:45.062242  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  515 08:42:45.062666  [login-action] Waiting for messages, (timeout 00:04:11)
  516 08:42:45.077249  [    0.000000] Linux version 6.12.0-rc3 (KernelCI@build-j348365-arm-gcc-12-multi-v7-defconfig-95tzl) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sun Oct 20 02:10:34 UTC 2024
  517 08:42:45.082876  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  518 08:42:45.088613  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  519 08:42:45.100007  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  520 08:42:45.105858  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  521 08:42:45.111606  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  522 08:42:45.111864  [    0.000000] Memory policy: Data cache writeback
  523 08:42:45.118244  [    0.000000] efi: UEFI not found.
  524 08:42:45.123645  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  525 08:42:45.129367  [    0.000000] Zone ranges:
  526 08:42:45.135072  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  527 08:42:45.140858  [    0.000000]   Normal   empty
  528 08:42:45.141116  [    0.000000]   HighMem  empty
  529 08:42:45.146631  [    0.000000] Movable zone start for each node
  530 08:42:45.146889  [    0.000000] Early memory node ranges
  531 08:42:45.158021  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  532 08:42:45.163303  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  533 08:42:45.188660  [    0.000000] CPU: All CPU(s) started in SVC mode.
  534 08:42:45.194313  [    0.000000] AM335X ES2.1 (sgx neon)
  535 08:42:45.205970  [    0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
  536 08:42:45.223623  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  537 08:42:45.235262  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  538 08:42:45.241019  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  539 08:42:45.246746  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  540 08:42:45.256861  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  541 08:42:45.285998  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  542 08:42:45.291865  <6>[    0.000000] trace event string verifier disabled
  543 08:42:45.292123  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  544 08:42:45.297587  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  545 08:42:45.309145  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  546 08:42:45.314833  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  547 08:42:45.322045  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  548 08:42:45.337130  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  549 08:42:45.354263  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  550 08:42:45.361054  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  551 08:42:45.452916  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  552 08:42:45.464378  <6>[    0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  553 08:42:45.471111  <6>[    0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  554 08:42:45.484103  <6>[    0.019144] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  555 08:42:45.491473  <6>[    0.033957] Console: colour dummy device 80x30
  556 08:42:45.497392  Matched prompt #6: WARNING:
  557 08:42:45.497656  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  558 08:42:45.502950  <3>[    0.038852] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  559 08:42:45.508749  <3>[    0.045922] This ensures that you still see kernel messages. Please
  560 08:42:45.511911  <3>[    0.052651] update your kernel commandline.
  561 08:42:45.552610  <6>[    0.057264] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  562 08:42:45.558355  <6>[    0.096150] CPU: Testing write buffer coherency: ok
  563 08:42:45.564330  <6>[    0.101515] CPU0: Spectre v2: using BPIALL workaround
  564 08:42:45.564589  <6>[    0.106980] pid_max: default: 32768 minimum: 301
  565 08:42:45.575907  <6>[    0.112175] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  566 08:42:45.582660  <6>[    0.119998] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  567 08:42:45.589587  <6>[    0.129346] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  568 08:42:45.655367  <6>[    0.189531] Setting up static identity map for 0x80300000 - 0x803000ac
  569 08:42:45.661114  <6>[    0.199110] rcu: Hierarchical SRCU implementation.
  570 08:42:45.665005  <6>[    0.204402] rcu: 	Max phase no-delay instances is 1000.
  571 08:42:45.673288  <6>[    0.215418] EFI services will not be available.
  572 08:42:45.679120  <6>[    0.220765] smp: Bringing up secondary CPUs ...
  573 08:42:45.684833  <6>[    0.225735] smp: Brought up 1 node, 1 CPU
  574 08:42:45.690566  <6>[    0.230220] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  575 08:42:45.696587  <6>[    0.236942] CPU: All CPU(s) started in SVC mode.
  576 08:42:45.716869  <6>[    0.242145] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
  577 08:42:45.717152  <6>[    0.258429] devtmpfs: initialized
  578 08:42:45.739249  <6>[    0.275591] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  579 08:42:45.750795  <6>[    0.284199] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  580 08:42:45.756807  <6>[    0.294643] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  581 08:42:45.767337  <6>[    0.306898] pinctrl core: initialized pinctrl subsystem
  582 08:42:45.776615  <6>[    0.317535] DMI not present or invalid.
  583 08:42:45.784976  <6>[    0.323386] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  584 08:42:45.794462  <6>[    0.332328] DMA: preallocated 256 KiB pool for atomic coherent allocations
  585 08:42:45.809566  <6>[    0.343783] thermal_sys: Registered thermal governor 'step_wise'
  586 08:42:45.809835  <6>[    0.343957] cpuidle: using governor menu
  587 08:42:45.837314  <6>[    0.379801] No ATAGs?
  588 08:42:45.843421  <6>[    0.382443] hw-breakpoint: debug architecture 0x4 unsupported.
  589 08:42:45.853546  <6>[    0.394337] Serial: AMBA PL011 UART driver
  590 08:42:45.883132  <6>[    0.425464] iommu: Default domain type: Translated
  591 08:42:45.892188  <6>[    0.430816] iommu: DMA domain TLB invalidation policy: strict mode
  592 08:42:45.919688  <5>[    0.460821] SCSI subsystem initialized
  593 08:42:45.933514  <6>[    0.470229] usbcore: registered new interface driver usbfs
  594 08:42:45.940370  <6>[    0.476184] usbcore: registered new interface driver hub
  595 08:42:45.940646  <6>[    0.482016] usbcore: registered new device driver usb
  596 08:42:45.946112  <6>[    0.488504] pps_core: LinuxPPS API ver. 1 registered
  597 08:42:45.957615  <6>[    0.493941] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  598 08:42:45.966301  <6>[    0.503657] PTP clock support registered
  599 08:42:45.966570  <6>[    0.508100] EDAC MC: Ver: 3.0.0
  600 08:42:46.013559  <6>[    0.553463] scmi_core: SCMI protocol bus registered
  601 08:42:46.038125  <6>[    0.579967] vgaarb: loaded
  602 08:42:46.044323  <6>[    0.583739] clocksource: Switched to clocksource dmtimer
  603 08:42:46.068499  <6>[    0.610585] NET: Registered PF_INET protocol family
  604 08:42:46.081132  <6>[    0.616285] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  605 08:42:46.088482  <6>[    0.625127] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  606 08:42:46.094235  <6>[    0.634050] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  607 08:42:46.105731  <6>[    0.642290] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  608 08:42:46.111482  <6>[    0.650577] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  609 08:42:46.117386  <6>[    0.658297] TCP: Hash tables configured (established 4096 bind 4096)
  610 08:42:46.128869  <6>[    0.665225] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  611 08:42:46.134875  <6>[    0.672237] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  612 08:42:46.140756  <6>[    0.679844] NET: Registered PF_UNIX/PF_LOCAL protocol family
  613 08:42:46.226873  <6>[    0.763577] RPC: Registered named UNIX socket transport module.
  614 08:42:46.227144  <6>[    0.770009] RPC: Registered udp transport module.
  615 08:42:46.232611  <6>[    0.775138] RPC: Registered tcp transport module.
  616 08:42:46.241235  <6>[    0.780244] RPC: Registered tcp-with-tls transport module.
  617 08:42:46.247001  <6>[    0.786163] RPC: Registered tcp NFSv4.1 backchannel transport module.
  618 08:42:46.254246  <6>[    0.793070] PCI: CLS 0 bytes, default 64
  619 08:42:46.256416  <5>[    0.798868] Initialise system trusted keyrings
  620 08:42:46.279556  <6>[    0.818967] Trying to unpack rootfs image as initramfs...
  621 08:42:46.358116  <6>[    0.894334] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  622 08:42:46.362922  <6>[    0.901816] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  623 08:42:46.401883  <5>[    0.944306] NFS: Registering the id_resolver key type
  624 08:42:46.407858  <5>[    0.949909] Key type id_resolver registered
  625 08:42:46.413528  <5>[    0.954603] Key type id_legacy registered
  626 08:42:46.422102  <6>[    0.959042] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  627 08:42:46.428921  <6>[    0.966257] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  628 08:42:46.498480  <5>[    1.040862] Key type asymmetric registered
  629 08:42:46.504344  <5>[    1.045477] Asymmetric key parser 'x509' registered
  630 08:42:46.515844  <6>[    1.050903] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  631 08:42:46.516111  <6>[    1.058830] io scheduler mq-deadline registered
  632 08:42:46.521610  <6>[    1.063786] io scheduler kyber registered
  633 08:42:46.527168  <6>[    1.068240] io scheduler bfq registered
  634 08:42:46.657987  <6>[    1.196707] ledtrig-cpu: registered to indicate activity on CPUs
  635 08:42:46.956888  <6>[    1.495434] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  636 08:42:46.996331  <6>[    1.538576] msm_serial: driver initialized
  637 08:42:47.002462  <6>[    1.543364] SuperH (H)SCI(F) driver initialized
  638 08:42:47.008307  <6>[    1.548692] STMicroelectronics ASC driver initialized
  639 08:42:47.013487  <6>[    1.554365] STM32 USART driver initialized
  640 08:42:47.162872  <6>[    1.704618] brd: module loaded
  641 08:42:47.207121  <6>[    1.748935] loop: module loaded
  642 08:42:47.249359  <6>[    1.790958] CAN device driver interface
  643 08:42:47.255927  <6>[    1.796176] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  644 08:42:47.261809  <6>[    1.803136] e1000e: Intel(R) PRO/1000 Network Driver
  645 08:42:47.267569  <6>[    1.808586] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  646 08:42:47.273312  <6>[    1.815025] igb: Intel(R) Gigabit Ethernet Network Driver
  647 08:42:47.281497  <6>[    1.820845] igb: Copyright (c) 2007-2014 Intel Corporation.
  648 08:42:47.293568  <6>[    1.830248] pegasus: Pegasus/Pegasus II USB Ethernet driver
  649 08:42:47.299318  <6>[    1.836424] usbcore: registered new interface driver pegasus
  650 08:42:47.305102  <6>[    1.842552] usbcore: registered new interface driver asix
  651 08:42:47.310944  <6>[    1.848438] usbcore: registered new interface driver ax88179_178a
  652 08:42:47.316691  <6>[    1.855030] usbcore: registered new interface driver cdc_ether
  653 08:42:47.322440  <6>[    1.861327] usbcore: registered new interface driver smsc75xx
  654 08:42:47.328189  <6>[    1.867558] usbcore: registered new interface driver smsc95xx
  655 08:42:47.333958  <6>[    1.873796] usbcore: registered new interface driver net1080
  656 08:42:47.339817  <6>[    1.879916] usbcore: registered new interface driver cdc_subset
  657 08:42:47.345565  <6>[    1.886344] usbcore: registered new interface driver zaurus
  658 08:42:47.353173  <6>[    1.892391] usbcore: registered new interface driver cdc_ncm
  659 08:42:47.363156  <6>[    1.901973] usbcore: registered new interface driver usb-storage
  660 08:42:47.656042  <6>[    2.196670] i2c_dev: i2c /dev entries driver
  661 08:42:47.705930  <5>[    2.240320] cpuidle: enable-method property 'ti,am3352' found operations
  662 08:42:47.711811  <6>[    2.249975] sdhci: Secure Digital Host Controller Interface driver
  663 08:42:47.719310  <6>[    2.256757] sdhci: Copyright(c) Pierre Ossman
  664 08:42:47.726800  <6>[    2.263292] Synopsys Designware Multimedia Card Interface Driver
  665 08:42:47.732235  <6>[    2.271397] sdhci-pltfm: SDHCI platform and OF driver helper
  666 08:42:47.859706  <6>[    2.394795] usbcore: registered new interface driver usbhid
  667 08:42:47.859978  <6>[    2.400835] usbhid: USB HID core driver
  668 08:42:47.910977  <6>[    2.450848] NET: Registered PF_INET6 protocol family
  669 08:42:47.952038  <6>[    2.494577] Segment Routing with IPv6
  670 08:42:47.957900  <6>[    2.498730] In-situ OAM (IOAM) with IPv6
  671 08:42:47.964649  <6>[    2.503124] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  672 08:42:47.970395  <6>[    2.510478] NET: Registered PF_PACKET protocol family
  673 08:42:47.976293  <6>[    2.516049] can: controller area network core
  674 08:42:47.982028  <6>[    2.520876] NET: Registered PF_CAN protocol family
  675 08:42:47.982297  <6>[    2.526138] can: raw protocol
  676 08:42:47.987789  <6>[    2.529469] can: broadcast manager protocol
  677 08:42:47.994290  <6>[    2.534072] can: netlink gateway - max_hops=1
  678 08:42:48.000415  <5>[    2.539540] Key type dns_resolver registered
  679 08:42:48.006793  <6>[    2.544606] ThumbEE CPU extension supported.
  680 08:42:48.007061  <5>[    2.549293] Registering SWP/SWPB emulation handler
  681 08:42:48.016490  <3>[    2.554987] omap_voltage_late_init: Voltage driver support not added
  682 08:42:48.204472  <5>[    2.744525] Loading compiled-in X.509 certificates
  683 08:42:48.342781  <6>[    2.872366] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  684 08:42:48.349955  <6>[    2.889023] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  685 08:42:48.376225  <3>[    2.912618] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  686 08:42:48.556960  <3>[    3.093452] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  687 08:42:48.764353  <6>[    3.305163] OMAP GPIO hardware version 0.1
  688 08:42:48.785097  <6>[    3.323883] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  689 08:42:48.867099  <4>[    3.405585] at24 2-0054: supply vcc not found, using dummy regulator
  690 08:42:48.901811  <4>[    3.440376] at24 2-0055: supply vcc not found, using dummy regulator
  691 08:42:48.940232  <4>[    3.478777] at24 2-0056: supply vcc not found, using dummy regulator
  692 08:42:48.979018  <4>[    3.517427] at24 2-0057: supply vcc not found, using dummy regulator
  693 08:42:49.021261  <6>[    3.560551] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  694 08:42:49.071682  <3>[    3.606969] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  695 08:42:49.096196  <6>[    3.627813] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  696 08:42:49.118256  <4>[    3.654605] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  697 08:42:49.125927  <4>[    3.663206] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  698 08:42:49.215316  <6>[    3.754082] omap_rng 48310000.rng: Random Number Generator ver. 20
  699 08:42:49.238936  <5>[    3.780451] random: crng init done
  700 08:42:49.292505  <6>[    3.834896] Freeing initrd memory: 14448K
  701 08:42:49.302388  <6>[    3.839525] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  702 08:42:49.359866  <6>[    3.896171] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  703 08:42:49.365760  <6>[    3.906493] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  704 08:42:49.377396  <6>[    3.913830] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  705 08:42:49.383247  <6>[    3.921275] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  706 08:42:49.394745  <6>[    3.929416] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  707 08:42:49.402119  <6>[    3.941048] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
  708 08:42:49.415293  <5>[    3.950076] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  709 08:42:49.442989  <3>[    3.979750] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  710 08:42:49.448804  <6>[    3.988339] edma 49000000.dma: TI EDMA DMA engine driver
  711 08:42:49.519543  <3>[    4.055724] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  712 08:42:49.534316  <6>[    4.070041] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  713 08:42:49.547168  <3>[    4.087129] l3-aon-clkctrl:0000:0: failed to disable
  714 08:42:49.595378  <6>[    4.132131] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  715 08:42:49.601125  <6>[    4.141642] printk: legacy console [ttyS0] enabled
  716 08:42:49.606752  <6>[    4.141642] printk: legacy console [ttyS0] enabled
  717 08:42:49.612504  <6>[    4.151986] printk: legacy bootconsole [omap8250] disabled
  718 08:42:49.618327  <6>[    4.151986] printk: legacy bootconsole [omap8250] disabled
  719 08:42:49.658736  <4>[    4.194502] tps65217-pmic: Failed to locate of_node [id: -1]
  720 08:42:49.662354  <4>[    4.201889] tps65217-bl: Failed to locate of_node [id: -1]
  721 08:42:49.678745  <6>[    4.221460] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  722 08:42:49.697140  <6>[    4.228405] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  723 08:42:49.708906  <6>[    4.242088] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  724 08:42:49.714425  <6>[    4.253993] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  725 08:42:49.736358  <6>[    4.273470] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  726 08:42:49.742231  <6>[    4.282661] sdhci-omap 48060000.mmc: Got CD GPIO
  727 08:42:49.750279  <4>[    4.287831] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  728 08:42:49.764866  <4>[    4.301290] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  729 08:42:49.771226  <4>[    4.309919] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  730 08:42:49.781039  <4>[    4.318584] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  731 08:42:49.854411  <6>[    4.392620] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  732 08:42:49.891405  <6>[    4.428702] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  733 08:42:49.914406  <6>[    4.450842] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  734 08:42:49.921092  <6>[    4.459784] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  735 08:42:49.991909  <6>[    4.524194] mmc1: new high speed MMC card at address 0001
  736 08:42:49.992177  <6>[    4.532513] mmcblk1: mmc1:0001 M62704 3.56 GiB
  737 08:42:50.002487  <6>[    4.543186]  mmcblk1: p1
  738 08:42:50.007873  <6>[    4.548069] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  739 08:42:50.018387  <6>[    4.558622] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  740 08:42:50.033961  <6>[    4.568970] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  741 08:42:50.041136  <6>[    4.577624] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  742 08:42:53.177850  <6>[    7.714761] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  743 08:42:53.251099  <5>[    7.753832] Sending DHCP requests ., OK
  744 08:42:53.262534  <6>[    7.798178] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.6
  745 08:42:53.262806  <6>[    7.806418] IP-Config: Complete:
  746 08:42:53.273813  <6>[    7.809955]      device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.6, mask=255.255.255.0, gw=192.168.11.1
  747 08:42:53.279563  <6>[    7.820549]      host=192.168.11.6, domain=usen.ad.jp, nis-domain=(none)
  748 08:42:53.291810  <6>[    7.827629]      bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
  749 08:42:53.292066  <6>[    7.827664]      nameserver0=192.168.11.1
  750 08:42:53.297948  <6>[    7.839934] clk: Disabling unused clocks
  751 08:42:53.304536  <6>[    7.844683] PM: genpd: Disabling unused power domains
  752 08:42:53.323777  <6>[    7.863070] Freeing unused kernel image (initmem) memory: 2048K
  753 08:42:53.331271  <6>[    7.872816] Run /init as init process
  754 08:42:53.356435  Loading, please wait...
  755 08:42:53.431702  Starting systemd-udevd version 252.22-1~deb12u1
  756 08:42:56.478222  <4>[   11.013899] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  757 08:42:56.625390  <4>[   11.160995] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  758 08:42:56.751067  <6>[   11.294089] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  759 08:42:56.761747  <6>[   11.299762] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  760 08:42:56.982969  <6>[   11.524541] hub 1-0:1.0: USB hub found
  761 08:42:57.026473  <6>[   11.567049] tda998x 0-0070: found TDA19988
  762 08:42:57.032459  <6>[   11.573978] hub 1-0:1.0: 1 port detected
  763 08:42:59.945441  Begin: Loading essential drivers ... done.
  764 08:42:59.950976  Begin: Running /scripts/init-premount ... done.
  765 08:42:59.956639  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  766 08:42:59.966927  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  767 08:42:59.976036  Device /sys/class/net/eth0 found
  768 08:42:59.976155  done.
  769 08:43:00.035027  Begin: Waiting up to 180 secs for any network device to become available ... done.
  770 08:43:00.106499  IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
  771 08:43:00.106628  IP-Config: eth0 guessed broadcast address 192.168.11.255
  772 08:43:00.111996  IP-Config: eth0 complete (dhcp from 192.168.11.1):
  773 08:43:00.123238   address: 192.168.11.6     broadcast: 192.168.11.255   netmask: 255.255.255.0   
  774 08:43:00.128868   gateway: 192.168.11.1     dns0     : 192.168.11.1     dns1   : 0.0.0.0         
  775 08:43:00.134458   domain : usen.ad.jp                                                      
  776 08:43:00.139265   rootserver: 192.168.11.1 rootpath: 
  777 08:43:00.139366   filename  : 
  778 08:43:00.211523  done.
  779 08:43:00.217635  Begin: Running /scripts/nfs-bottom ... done.
  780 08:43:00.282543  Begin: Running /scripts/init-bottom ... done.
  781 08:43:01.674271  <30>[   16.213104] systemd[1]: System time before build time, advancing clock.
  782 08:43:01.857197  <30>[   16.369905] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  783 08:43:01.865863  <30>[   16.406557] systemd[1]: Detected architecture arm.
  784 08:43:01.878468  
  785 08:43:01.878736  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  786 08:43:01.878956  
  787 08:43:01.904654  <30>[   16.444250] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  788 08:43:04.108397  <30>[   18.646831] systemd[1]: Queued start job for default target graphical.target.
  789 08:43:04.125053  <30>[   18.661311] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  790 08:43:04.132510  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  791 08:43:04.163816  <30>[   18.699647] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  792 08:43:04.171268  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  793 08:43:04.201091  <30>[   18.736476] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  794 08:43:04.208371  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  795 08:43:04.241551  <30>[   18.777458] systemd[1]: Created slice user.slice - User and Session Slice.
  796 08:43:04.248262  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  797 08:43:04.273818  <30>[   18.805023] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  798 08:43:04.279860  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  799 08:43:04.297935  <30>[   18.834830] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  800 08:43:04.306872  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  801 08:43:04.338931  <30>[   18.864847] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  802 08:43:04.345326  <30>[   18.885317] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  803 08:43:04.353731           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  804 08:43:04.377202  <30>[   18.914247] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  805 08:43:04.385378  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  806 08:43:04.407802  <30>[   18.944607] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  807 08:43:04.416254  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  808 08:43:04.437801  <30>[   18.974799] systemd[1]: Reached target paths.target - Path Units.
  809 08:43:04.442898  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  810 08:43:04.467449  <30>[   19.004431] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  811 08:43:04.474730  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  812 08:43:04.497305  <30>[   19.034333] systemd[1]: Reached target slices.target - Slice Units.
  813 08:43:04.502616  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  814 08:43:04.527555  <30>[   19.064609] systemd[1]: Reached target swap.target - Swaps.
  815 08:43:04.531696  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  816 08:43:04.557695  <30>[   19.094522] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  817 08:43:04.566675  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  818 08:43:04.588555  <30>[   19.125327] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  819 08:43:04.596911  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  820 08:43:04.677106  <30>[   19.209077] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  821 08:43:04.689796  <30>[   19.226719] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  822 08:43:04.698292  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  823 08:43:04.720434  <30>[   19.256465] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  824 08:43:04.727725  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  825 08:43:04.750191  <30>[   19.286886] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  826 08:43:04.758224  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  827 08:43:04.783563  <30>[   19.319201] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  828 08:43:04.789216  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  829 08:43:04.819813  <30>[   19.355433] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  830 08:43:04.827371  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  831 08:43:04.854631  <30>[   19.385542] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  832 08:43:04.873335  <30>[   19.404179] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  833 08:43:04.917592  <30>[   19.455327] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  834 08:43:04.941162           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  835 08:43:04.997088  <30>[   19.534670] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  836 08:43:05.028802           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  837 08:43:05.088539  <30>[   19.625121] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  838 08:43:05.099003           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  839 08:43:05.139213  <30>[   19.676495] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  840 08:43:05.165386           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  841 08:43:05.207342  <30>[   19.744916] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  842 08:43:05.224120           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  843 08:43:05.254448  <30>[   19.792443] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  844 08:43:05.276594           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  845 08:43:05.318237  <30>[   19.855079] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  846 08:43:05.333345           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  847 08:43:05.377088  <30>[   19.915016] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  848 08:43:05.394588           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  849 08:43:05.436967  <30>[   19.975013] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  850 08:43:05.451401           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  851 08:43:05.487842  <28>[   20.019888] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  852 08:43:05.496392  <28>[   20.033575] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  853 08:43:05.536795  <30>[   20.075224] systemd[1]: Starting systemd-journald.service - Journal Service...
  854 08:43:05.555767           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  855 08:43:05.637405  <30>[   20.175162] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  856 08:43:05.650437           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  857 08:43:05.698589  <30>[   20.236580] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  858 08:43:05.736353           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  859 08:43:05.801531  <30>[   20.337998] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  860 08:43:05.845545           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  861 08:43:05.932404  <30>[   20.469705] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  862 08:43:06.001283           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  863 08:43:06.035389  <30>[   20.573578] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  864 08:43:06.114150  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  865 08:43:06.131251  <30>[   20.669306] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  866 08:43:06.170379  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  867 08:43:06.200371  <30>[   20.737297] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  868 08:43:06.221165  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  869 08:43:06.390567  <30>[   20.929206] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  870 08:43:06.427000  <30>[   20.964171] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  871 08:43:06.435791  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  872 08:43:06.447751  <30>[   20.986516] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  873 08:43:06.487734  <30>[   21.025576] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  874 08:43:06.507255  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  875 08:43:06.528491  <30>[   21.065556] systemd[1]: Started systemd-journald.service - Journal Service.
  876 08:43:06.535252  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  877 08:43:06.569105  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  878 08:43:06.592873  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  879 08:43:06.631797  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  880 08:43:06.668325  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  881 08:43:06.697426  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  882 08:43:06.727154  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  883 08:43:06.749527  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  884 08:43:06.780654  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  885 08:43:06.846723           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  886 08:43:06.918613           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  887 08:43:06.987943           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  888 08:43:07.089566           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  889 08:43:07.158187           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  890 08:43:07.188278  <46>[   21.726249] systemd-journald[162]: Received client request to flush runtime journal.
  891 08:43:07.293664  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  892 08:43:07.437097  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  893 08:43:08.189734  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  894 08:43:08.568878  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  895 08:43:08.629425           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  896 08:43:08.981522  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  897 08:43:09.192638  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  898 08:43:09.227027  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  899 08:43:09.247001  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  900 08:43:09.321649           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  901 08:43:09.367288           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  902 08:43:10.320086  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  903 08:43:10.387984           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  904 08:43:10.470721  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  905 08:43:10.587218           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  906 08:43:10.632383           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  907 08:43:12.457151  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  908 08:43:13.229628  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  909 08:43:13.388363  <5>[   27.926696] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  910 08:43:14.186855  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  911 08:43:14.715868  <5>[   29.256308] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  912 08:43:14.805602  <5>[   29.344566] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  913 08:43:14.828808  <4>[   29.366947] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  914 08:43:14.834559  <6>[   29.376066] cfg80211: failed to load regulatory.db
  915 08:43:15.188869  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  916 08:43:15.664403  <46>[   30.192828] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
  917 08:43:15.842773  <46>[   30.374165] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
  918 08:43:15.894797  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  919 08:43:24.521835  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  920 08:43:24.549323  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  921 08:43:24.583934  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  922 08:43:24.609059  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  923 08:43:24.667056           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  924 08:43:24.717709           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  925 08:43:24.760662           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  926 08:43:24.820629           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  927 08:43:24.878951  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  928 08:43:24.905060  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  929 08:43:24.937554  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  930 08:43:24.962180  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  931 08:43:24.991567  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  932 08:43:25.044563  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  933 08:43:25.078785  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  934 08:43:25.110022  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  935 08:43:25.149060  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  936 08:43:25.177796  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  937 08:43:25.203816  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  938 08:43:25.227090  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  939 08:43:25.257064  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  940 08:43:25.277174  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  941 08:43:25.303551  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  942 08:43:25.377519           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  943 08:43:25.430534           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  944 08:43:25.535308           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  945 08:43:25.636544           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  946 08:43:25.695977           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  947 08:43:25.714248  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  948 08:43:25.749475  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  949 08:43:25.953464  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  950 08:43:26.034101  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  951 08:43:26.099150  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  952 08:43:26.116928  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  953 08:43:26.147052  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  954 08:43:26.316907  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  955 08:43:26.630560  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  956 08:43:26.680753  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  957 08:43:26.711679  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  958 08:43:26.805068           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  959 08:43:26.976893  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  960 08:43:27.096907  
  961 08:43:27.097176  Debian GNU/Linux 1worm-armhf login: root (automatic login)
  962 08:43:27.100368  
  963 08:43:27.384354  Linux debian-bookworm-armhf 6.12.0-rc3 #1 SMP Sun Oct 20 02:10:34 UTC 2024 armv7l
  964 08:43:27.384625  
  965 08:43:27.389837  The programs included with the Debian GNU/Linux system are free software;
  966 08:43:27.395450  the exact distribution terms for each program are described in the
  967 08:43:27.401135  individual files in /usr/share/doc/*/copyright.
  968 08:43:27.401376  
  969 08:43:27.409060  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  970 08:43:27.409330  permitted by applicable law.
  971 08:43:31.984097  Unable to match end of the kernel message
  973 08:43:31.984928  Setting prompt string to ['/ #']
  974 08:43:31.985231  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  976 08:43:31.985912  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  977 08:43:31.986204  start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
  978 08:43:31.986442  Setting prompt string to ['/ #']
  979 08:43:31.986650  Forcing a shell prompt, looking for ['/ #']
  981 08:43:32.037162  / # 
  982 08:43:32.037542  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  983 08:43:32.037793  Waiting using forced prompt support (timeout 00:02:30)
  984 08:43:32.042069  
  985 08:43:32.049972  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  986 08:43:32.050306  start: 2.4.6 export-device-env (timeout 00:03:24) [common]
  987 08:43:32.050561  Sending with 10 millisecond of delay
  989 08:43:37.099149  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n'
  990 08:43:37.109745  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1209565/extract-nfsrootfs-xd_xcf2n'
  991 08:43:37.110254  Sending with 10 millisecond of delay
  993 08:43:39.268460  / # export NFS_SERVER_IP='192.168.11.5'
  994 08:43:39.279051  export NFS_SERVER_IP='192.168.11.5'
  995 08:43:39.280090  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  996 08:43:39.280423  end: 2.4 uboot-commands (duration 00:01:43) [common]
  997 08:43:39.280746  end: 2 uboot-action (duration 00:01:43) [common]
  998 08:43:39.281053  start: 3 lava-test-retry (timeout 00:06:58) [common]
  999 08:43:39.281356  start: 3.1 lava-test-shell (timeout 00:06:58) [common]
 1000 08:43:39.281613  Using namespace: common
 1002 08:43:39.382349  / # #
 1003 08:43:39.382720  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
 1004 08:43:39.387091  #
 1005 08:43:39.393043  Using /lava-1209565
 1007 08:43:39.493749  / # export SHELL=/bin/bash
 1008 08:43:39.498587  export SHELL=/bin/bash
 1010 08:43:39.604854  / # . /lava-1209565/environment
 1011 08:43:39.609602  . /lava-1209565/environment
 1013 08:43:39.723477  / # /lava-1209565/bin/lava-test-runner /lava-1209565/0
 1014 08:43:39.723858  Test shell timeout: 10s (minimum of the action and connection timeout)
 1015 08:43:39.728292  /lava-1209565/bin/lava-test-runner /lava-1209565/0
 1016 08:43:40.137428  + export TESTRUN_ID=0_timesync-off
 1017 08:43:40.145457  + TESTRUN_ID=0_timesync-off
 1018 08:43:40.145700  + cd /lava-1209565/0/tests/0_timesync-off
 1019 08:43:40.145921  ++ cat uuid
 1020 08:43:40.161300  + UUID=1209565_1.6.2.4.1
 1021 08:43:40.161610  + set +x
 1022 08:43:40.166904  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1209565_1.6.2.4.1>
 1023 08:43:40.167365  Received signal: <STARTRUN> 0_timesync-off 1209565_1.6.2.4.1
 1024 08:43:40.167598  Starting test lava.0_timesync-off (1209565_1.6.2.4.1)
 1025 08:43:40.167863  Skipping test definition patterns.
 1026 08:43:40.170156  + systemctl stop systemd-timesyncd
 1027 08:43:40.468037  + set +x
 1028 08:43:40.468519  Received signal: <ENDRUN> 0_timesync-off 1209565_1.6.2.4.1
 1029 08:43:40.468837  Ending use of test pattern.
 1030 08:43:40.469059  Ending test lava.0_timesync-off (1209565_1.6.2.4.1), duration 0.30
 1032 08:43:40.471227  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1209565_1.6.2.4.1>
 1033 08:43:40.710166  + export TESTRUN_ID=1_kselftest-dt
 1034 08:43:40.718245  + TESTRUN_ID=1_kselftest-dt
 1035 08:43:40.718521  + cd /lava-1209565/0/tests/1_kselftest-dt
 1036 08:43:40.718754  ++ cat uuid
 1037 08:43:40.735039  + UUID=1209565_1.6.2.4.5
 1038 08:43:40.735320  + set +x
 1039 08:43:40.740499  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1209565_1.6.2.4.5>
 1040 08:43:40.740743  + cd ./automated/linux/kselftest/
 1041 08:43:40.741184  Received signal: <STARTRUN> 1_kselftest-dt 1209565_1.6.2.4.5
 1042 08:43:40.741406  Starting test lava.1_kselftest-dt (1209565_1.6.2.4.5)
 1043 08:43:40.741671  Skipping test definition patterns.
 1044 08:43:40.768936  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1045 08:43:40.874590  INFO: install_deps skipped
 1046 08:43:41.420486  --2024-10-20 08:43:41--  http://storage.kernelci.org/mainline/master/v6.12-rc3-420-g715ca9dd687f8/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
 1047 08:43:41.432867  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1048 08:43:41.547427  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1049 08:43:41.662502  HTTP request sent, awaiting response... 200 OK
 1050 08:43:41.662777  Length: 4113516 (3.9M) [application/octet-stream]
 1051 08:43:41.668104  Saving to: 'kselftest_armhf.tar.gz'
 1052 08:43:41.668374  
 1053 08:43:43.324331  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  49.92K   223KB/s               kselftest_armhf.tar   4%[                    ] 194.76K   428KB/s               kselftest_armhf.tar  18%[==>                 ] 730.98K   936KB/s               kselftest_armhf.tar  28%[====>               ]   1.13M  1.12MB/s               kselftest_armhf.tar  55%[==========>         ]   2.18M  1.76MB/s               kselftest_armhf.tar  82%[===============>    ]   3.23M  2.25MB/s               kselftest_armhf.tar  98%[==================> ]   3.86M  2.36MB/s               kselftest_armhf.tar 100%[===================>]   3.92M  2.37MB/s    in 1.7s    
 1054 08:43:43.324661  
 1055 08:43:43.904263  2024-10-20 08:43:43 (2.37 MB/s) - 'kselftest_armhf.tar.gz' saved [4113516/4113516]
 1056 08:43:43.904623  
 1057 08:44:06.076697  skiplist:
 1058 08:44:06.077101  ========================================
 1059 08:44:06.082282  ========================================
 1060 08:44:06.185454  dt:test_unprobed_devices.sh
 1061 08:44:06.216698  ============== Tests to run ===============
 1062 08:44:06.225778  dt:test_unprobed_devices.sh
 1063 08:44:06.229700  ===========End Tests to run ===============
 1064 08:44:06.239079  shardfile-dt pass
 1065 08:44:06.468175  <12>[   81.012240] kselftest: Running tests in dt
 1066 08:44:06.496152  TAP version 13
 1067 08:44:06.520154  1..1
 1068 08:44:06.574601  # timeout set to 45
 1069 08:44:06.574868  # selftests: dt: test_unprobed_devices.sh
 1070 08:44:07.424690  # TAP version 13
 1071 08:44:32.635750  # 1..257
 1072 08:44:32.812344  # ok 1 / # SKIP
 1073 08:44:32.834375  # ok 2 /clk_mcasp0
 1074 08:44:32.912429  # ok 3 /clk_mcasp0_fixed # SKIP
 1075 08:44:32.983483  # ok 4 /cpus/cpu@0 # SKIP
 1076 08:44:33.055787  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 1077 08:44:33.075977  # ok 6 /fixedregulator0
 1078 08:44:33.095504  # ok 7 /leds
 1079 08:44:33.115090  # ok 8 /ocp
 1080 08:44:33.143085  # ok 9 /ocp/interconnect@44c00000
 1081 08:44:33.160590  # ok 10 /ocp/interconnect@44c00000/segment@0
 1082 08:44:33.188779  # ok 11 /ocp/interconnect@44c00000/segment@100000
 1083 08:44:33.213452  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 1084 08:44:33.287091  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 1085 08:44:33.307311  # ok 14 /ocp/interconnect@44c00000/segment@200000
 1086 08:44:33.330120  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 1087 08:44:33.433637  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 1088 08:44:33.506127  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 1089 08:44:33.578828  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 1090 08:44:33.651200  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 1091 08:44:33.728348  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 1092 08:44:33.795956  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 1093 08:44:33.868877  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 1094 08:44:33.940966  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 1095 08:44:34.017957  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 1096 08:44:34.085189  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 1097 08:44:34.156462  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 1098 08:44:34.229428  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 1099 08:44:34.302157  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 1100 08:44:34.374413  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 1101 08:44:34.446187  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 1102 08:44:34.519092  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 1103 08:44:34.590596  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 1104 08:44:34.663772  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 1105 08:44:34.735745  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 1106 08:44:34.809171  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 1107 08:44:34.881402  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 1108 08:44:34.955082  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 1109 08:44:35.027517  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 1110 08:44:35.099429  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 1111 08:44:35.171759  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 1112 08:44:35.249162  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 1113 08:44:35.317284  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 1114 08:44:35.390018  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 1115 08:44:35.462540  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 1116 08:44:35.540057  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 1117 08:44:35.613079  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 1118 08:44:35.683865  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 1119 08:44:35.753313  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 1120 08:44:35.825191  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 1121 08:44:35.898186  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 1122 08:44:35.970950  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 1123 08:44:36.043687  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 1124 08:44:36.115491  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 1125 08:44:36.189067  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 1126 08:44:36.261337  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 1127 08:44:36.342211  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 1128 08:44:36.412624  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 1129 08:44:36.483140  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 1130 08:44:36.557868  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 1131 08:44:36.630959  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 1132 08:44:36.703210  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 1133 08:44:36.776201  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 1134 08:44:36.849465  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 1135 08:44:36.922272  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 1136 08:44:36.992681  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 1137 08:44:37.070661  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 1138 08:44:37.143266  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 1139 08:44:37.217423  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 1140 08:44:37.284366  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 1141 08:44:37.358541  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 1142 08:44:37.431311  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 1143 08:44:37.512536  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 1144 08:44:37.579345  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 1145 08:44:37.652089  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 1146 08:44:37.729705  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 1147 08:44:37.803402  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 1148 08:44:37.872328  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 1149 08:44:37.949430  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 1150 08:44:38.023521  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 1151 08:44:38.095549  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 1152 08:44:38.167277  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 1153 08:44:38.239060  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 1154 08:44:38.310258  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 1155 08:44:38.387903  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 1156 08:44:38.456184  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 1157 08:44:38.528642  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 1158 08:44:38.601062  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 1159 08:44:38.677930  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 1160 08:44:38.748280  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 1161 08:44:38.821124  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 1162 08:44:38.890878  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 1163 08:44:38.965544  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 1164 08:44:39.038363  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 1165 08:44:39.111979  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 1166 08:44:39.132989  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 1167 08:44:39.156989  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 1168 08:44:39.182529  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 1169 08:44:39.204649  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 1170 08:44:39.229260  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 1171 08:44:39.253620  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 1172 08:44:39.277061  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 1173 08:44:39.299838  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 1174 08:44:39.411333  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 1175 08:44:39.436004  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 1176 08:44:39.460240  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 1177 08:44:39.481870  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 1178 08:44:39.587446  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 1179 08:44:39.664468  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 1180 08:44:39.736230  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 1181 08:44:39.810207  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 1182 08:44:39.883717  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 1183 08:44:39.957202  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 1184 08:44:40.030572  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 1185 08:44:40.111828  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 1186 08:44:40.179226  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 1187 08:44:40.253204  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 1188 08:44:40.331199  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 1189 08:44:40.404849  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 1190 08:44:40.479342  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 1191 08:44:40.554835  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 1192 08:44:40.624392  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 1193 08:44:40.702459  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 1194 08:44:40.722824  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 1195 08:44:40.791091  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 1196 08:44:40.861476  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 1197 08:44:40.935630  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 1198 08:44:40.957710  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 1199 08:44:41.035177  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 1200 08:44:41.052949  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 1201 08:44:41.125466  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 1202 08:44:41.148900  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 1203 08:44:41.174028  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 1204 08:44:41.196902  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 1205 08:44:41.221651  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 1206 08:44:41.249177  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 1207 08:44:41.270527  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 1208 08:44:41.296083  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 1209 08:44:41.370905  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 1210 08:44:41.397422  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 1211 08:44:41.422187  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 1212 08:44:41.492287  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 1213 08:44:41.564540  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 1214 08:44:41.585763  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 1215 08:44:41.692168  # not ok 144 /ocp/interconnect@47c00000
 1216 08:44:41.765041  # not ok 145 /ocp/interconnect@47c00000/segment@0
 1217 08:44:41.786041  # ok 146 /ocp/interconnect@48000000
 1218 08:44:41.804457  # ok 147 /ocp/interconnect@48000000/segment@0
 1219 08:44:41.833608  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 1220 08:44:41.854819  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 1221 08:44:41.879757  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 1222 08:44:41.902142  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 1223 08:44:41.925380  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 1224 08:44:41.949752  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 1225 08:44:41.976990  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 1226 08:44:42.050026  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 1227 08:44:42.119498  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 1228 08:44:42.142257  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 1229 08:44:42.166004  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 1230 08:44:42.194881  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 1231 08:44:42.214877  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 1232 08:44:42.237421  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 1233 08:44:42.266623  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 1234 08:44:42.289281  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 1235 08:44:42.310241  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 1236 08:44:42.336876  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 1237 08:44:42.360465  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 1238 08:44:42.383913  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 1239 08:44:42.409256  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 1240 08:44:42.429610  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 1241 08:44:42.452235  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 1242 08:44:42.479341  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 1243 08:44:42.500484  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 1244 08:44:42.526994  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 1245 08:44:42.550793  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 1246 08:44:42.573394  # ok 175 /ocp/interconnect@48000000/segment@100000
 1247 08:44:42.594249  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 1248 08:44:42.618874  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 1249 08:44:42.695760  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 1250 08:44:42.767839  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 1251 08:44:42.838885  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 1252 08:44:42.915131  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 1253 08:44:42.984237  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 1254 08:44:43.063829  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 1255 08:44:43.137097  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 1256 08:44:43.208720  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 1257 08:44:43.228549  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 1258 08:44:43.252854  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 1259 08:44:43.276214  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 1260 08:44:43.303378  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 1261 08:44:43.323986  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 1262 08:44:43.348769  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 1263 08:44:43.376273  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 1264 08:44:43.400722  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 1265 08:44:43.424355  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 1266 08:44:43.448598  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 1267 08:44:43.470330  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 1268 08:44:43.492748  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 1269 08:44:43.513240  # ok 198 /ocp/interconnect@48000000/segment@200000
 1270 08:44:43.537966  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 1271 08:44:43.617143  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 1272 08:44:43.637380  # ok 201 /ocp/interconnect@48000000/segment@300000
 1273 08:44:43.659798  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 1274 08:44:43.686417  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 1275 08:44:43.710625  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 1276 08:44:43.737268  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 1277 08:44:43.754284  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 1278 08:44:43.777590  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 1279 08:44:43.851839  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 1280 08:44:43.869996  # ok 209 /ocp/interconnect@4a000000
 1281 08:44:43.897873  # ok 210 /ocp/interconnect@4a000000/segment@0
 1282 08:44:43.919284  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 1283 08:44:43.943970  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 1284 08:44:43.971314  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 1285 08:44:43.991658  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 1286 08:44:44.063809  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 1287 08:44:44.170436  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 1288 08:44:44.244370  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 1289 08:44:44.349429  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 1290 08:44:44.427440  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 1291 08:44:44.495424  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 1292 08:44:44.595188  # not ok 221 /ocp/interconnect@4b140000
 1293 08:44:44.672468  # not ok 222 /ocp/interconnect@4b140000/segment@0
 1294 08:44:44.739019  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 1295 08:44:44.764741  # ok 224 /ocp/target-module@40300000
 1296 08:44:44.787681  # ok 225 /ocp/target-module@40300000/sram@0
 1297 08:44:44.858233  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 1298 08:44:44.930922  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 1299 08:44:44.951210  # ok 228 /ocp/target-module@47400000
 1300 08:44:44.978852  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 1301 08:44:44.998793  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 1302 08:44:45.021751  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 1303 08:44:45.043974  # ok 232 /ocp/target-module@47400000/usb@1400
 1304 08:44:45.067796  # ok 233 /ocp/target-module@47400000/usb@1800
 1305 08:44:45.088911  # ok 234 /ocp/target-module@47810000
 1306 08:44:45.115454  # ok 235 /ocp/target-module@49000000
 1307 08:44:45.137686  # ok 236 /ocp/target-module@49000000/dma@0
 1308 08:44:45.156808  # ok 237 /ocp/target-module@49800000
 1309 08:44:45.184060  # ok 238 /ocp/target-module@49800000/dma@0
 1310 08:44:45.205889  # ok 239 /ocp/target-module@49900000
 1311 08:44:45.224575  # ok 240 /ocp/target-module@49900000/dma@0
 1312 08:44:45.247164  # ok 241 /ocp/target-module@49a00000
 1313 08:44:45.274413  # ok 242 /ocp/target-module@49a00000/dma@0
 1314 08:44:45.292092  # ok 243 /ocp/target-module@4c000000
 1315 08:44:45.368089  # not ok 244 /ocp/target-module@4c000000/emif@0
 1316 08:44:45.386695  # ok 245 /ocp/target-module@50000000
 1317 08:44:45.413282  # ok 246 /ocp/target-module@53100000
 1318 08:44:45.485331  # not ok 247 /ocp/target-module@53100000/sham@0
 1319 08:44:45.502404  # ok 248 /ocp/target-module@53500000
 1320 08:44:45.578026  # not ok 249 /ocp/target-module@53500000/aes@0
 1321 08:44:45.595937  # ok 250 /ocp/target-module@56000000
 1322 08:44:45.701898  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 1323 08:44:45.771414  # ok 252 /opp-table # SKIP
 1324 08:44:45.845662  # ok 253 /soc # SKIP
 1325 08:44:45.864260  # ok 254 /sound
 1326 08:44:45.888855  # ok 255 /target-module@4b000000
 1327 08:44:45.917888  # ok 256 /target-module@4b000000/target-module@140000
 1328 08:44:45.934370  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 1329 08:44:45.942989  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 1330 08:44:45.950638  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 1331 08:44:48.164259  dt_test_unprobed_devices_sh_ skip
 1332 08:44:48.169807  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 1333 08:44:48.175443  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 1334 08:44:48.175699  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 1335 08:44:48.181084  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 1336 08:44:48.186583  dt_test_unprobed_devices_sh_fixedregulator0 pass
 1337 08:44:48.192203  dt_test_unprobed_devices_sh_leds pass
 1338 08:44:48.192452  dt_test_unprobed_devices_sh_ocp pass
 1339 08:44:48.197831  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 1340 08:44:48.203456  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 1341 08:44:48.209082  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 1342 08:44:48.220328  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 1343 08:44:48.225955  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 1344 08:44:48.231579  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 1345 08:44:48.242703  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 1346 08:44:48.248454  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 1347 08:44:48.259589  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 1348 08:44:48.270841  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 1349 08:44:48.281963  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 1350 08:44:48.287590  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 1351 08:44:48.298842  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 1352 08:44:48.310090  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 1353 08:44:48.321339  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 1354 08:44:48.332461  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 1355 08:44:48.338093  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 1356 08:44:48.349246  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 1357 08:44:48.360462  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 1358 08:44:48.371589  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 1359 08:44:48.382840  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 1360 08:44:48.388462  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 1361 08:44:48.399590  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 1362 08:44:48.410839  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 1363 08:44:48.421960  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 1364 08:44:48.427583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 1365 08:44:48.438836  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 1366 08:44:48.449998  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 1367 08:44:48.461141  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 1368 08:44:48.472473  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 1369 08:44:48.477889  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 1370 08:44:48.489130  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 1371 08:44:48.500368  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 1372 08:44:48.511642  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 1373 08:44:48.522736  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 1374 08:44:48.533985  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 1375 08:44:48.545125  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 1376 08:44:48.556357  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 1377 08:44:48.567478  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 1378 08:44:48.578734  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 1379 08:44:48.589859  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 1380 08:44:48.601115  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 1381 08:44:48.612163  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 1382 08:44:48.623439  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 1383 08:44:48.634524  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 1384 08:44:48.645794  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 1385 08:44:48.657059  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 1386 08:44:48.668147  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 1387 08:44:48.679485  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 1388 08:44:48.690552  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 1389 08:44:48.701771  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 1390 08:44:48.712913  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 1391 08:44:48.724145  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 1392 08:44:48.735397  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 1393 08:44:48.746520  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 1394 08:44:48.757711  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 1395 08:44:48.763400  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 1396 08:44:48.774583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 1397 08:44:48.785708  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 1398 08:44:48.796971  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 1399 08:44:48.808082  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 1400 08:44:48.819334  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 1401 08:44:48.830581  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 1402 08:44:48.841706  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 1403 08:44:48.852969  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 1404 08:44:48.864078  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 1405 08:44:48.875199  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 1406 08:44:48.886464  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 1407 08:44:48.897712  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 1408 08:44:48.908827  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 1409 08:44:48.920077  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 1410 08:44:48.931200  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 1411 08:44:48.942453  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 1412 08:44:48.953545  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 1413 08:44:48.959201  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 1414 08:44:48.970451  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 1415 08:44:48.981592  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 1416 08:44:48.992824  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 1417 08:44:49.003949  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 1418 08:44:49.009587  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 1419 08:44:49.026446  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 1420 08:44:49.037574  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 1421 08:44:49.043196  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 1422 08:44:49.059946  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 1423 08:44:49.071072  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 1424 08:44:49.082331  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 1425 08:44:49.087946  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 1426 08:44:49.099069  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 1427 08:44:49.110320  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 1428 08:44:49.115818  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 1429 08:44:49.127071  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 1430 08:44:49.138191  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 1431 08:44:49.143818  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 1432 08:44:49.155082  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 1433 08:44:49.160693  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 1434 08:44:49.171846  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 1435 08:44:49.183072  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 1436 08:44:49.194195  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 1437 08:44:49.205444  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 1438 08:44:49.216568  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 1439 08:44:49.227817  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 1440 08:44:49.238943  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 1441 08:44:49.250191  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 1442 08:44:49.261442  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 1443 08:44:49.272564  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 1444 08:44:49.283689  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 1445 08:44:49.294944  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 1446 08:44:49.311813  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 1447 08:44:49.322940  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 1448 08:44:49.334185  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 1449 08:44:49.345438  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 1450 08:44:49.356687  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 1451 08:44:49.373561  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 1452 08:44:49.384685  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 1453 08:44:49.395935  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 1454 08:44:49.407184  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 1455 08:44:49.412686  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 1456 08:44:49.423934  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 1457 08:44:49.435061  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 1458 08:44:49.440684  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 1459 08:44:49.451917  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 1460 08:44:49.457612  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 1461 08:44:49.468748  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 1462 08:44:49.474495  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 1463 08:44:49.485615  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 1464 08:44:49.491106  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 1465 08:44:49.502360  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 1466 08:44:49.507983  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 1467 08:44:49.519108  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 1468 08:44:49.530362  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 1469 08:44:49.541488  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 1470 08:44:49.552748  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 1471 08:44:49.563856  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 1472 08:44:49.569486  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 1473 08:44:49.580745  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 1474 08:44:49.586238  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 1475 08:44:49.591859  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 1476 08:44:49.597486  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 1477 08:44:49.603106  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 1478 08:44:49.608745  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 1479 08:44:49.619852  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 1480 08:44:49.625480  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 1481 08:44:49.631111  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 1482 08:44:49.642234  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 1483 08:44:49.647858  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 1484 08:44:49.658980  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 1485 08:44:49.664605  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 1486 08:44:49.675855  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 1487 08:44:49.681483  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 1488 08:44:49.692601  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 1489 08:44:49.698226  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 1490 08:44:49.709478  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 1491 08:44:49.714979  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 1492 08:44:49.726228  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 1493 08:44:49.731727  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 1494 08:44:49.742976  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 1495 08:44:49.748602  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 1496 08:44:49.754108  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 1497 08:44:49.765355  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 1498 08:44:49.770976  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 1499 08:44:49.782103  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 1500 08:44:49.787729  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 1501 08:44:49.798849  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 1502 08:44:49.804474  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 1503 08:44:49.815725  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 1504 08:44:49.821349  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 1505 08:44:49.826849  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 1506 08:44:49.838102  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 1507 08:44:49.843726  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 1508 08:44:49.854847  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 1509 08:44:49.866095  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 1510 08:44:49.877227  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 1511 08:44:49.888466  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 1512 08:44:49.899721  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 1513 08:44:49.910847  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 1514 08:44:49.922097  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 1515 08:44:49.933228  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 1516 08:44:49.938845  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 1517 08:44:49.949970  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 1518 08:44:49.955593  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 1519 08:44:49.966842  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 1520 08:44:49.972470  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 1521 08:44:49.983550  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 1522 08:44:49.989171  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 1523 08:44:50.000411  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 1524 08:44:50.005915  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 1525 08:44:50.017162  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 1526 08:45:08.751304  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 1527 08:45:08.751616  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 1528 08:45:08.751835  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 1529 08:45:08.752044  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 1530 08:45:08.752248  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 1531 08:45:08.752451  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 1532 08:45:08.752648  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 1533 08:45:08.752864  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 1534 08:45:08.753061  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 1535 08:45:08.753256  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 1536 08:45:08.753450  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 1537 08:45:08.753643  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 1538 08:45:08.753836  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 1539 08:45:08.754029  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 1540 08:45:08.754219  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 1541 08:45:08.754410  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 1542 08:45:08.754601  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 1543 08:45:08.754793  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 1544 08:45:08.754983  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 1545 08:45:08.755174  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 1546 08:45:08.755365  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 1547 08:45:08.755555  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 1548 08:45:08.755747  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 1549 08:45:08.755939  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 1550 08:45:08.756130  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 1551 08:45:08.756320  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 1552 08:45:08.756508  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 1553 08:45:08.756698  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 1554 08:45:08.756966  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 1555 08:45:08.757158  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 1556 08:45:08.757348  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 1557 08:45:08.757537  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 1558 08:45:08.757725  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 1559 08:45:08.757913  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 1560 08:45:08.758102  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 1561 08:45:08.758291  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 1562 08:45:08.758485  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 1563 08:45:08.758671  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 1564 08:45:08.758857  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 1565 08:45:08.759046  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 1566 08:45:08.759232  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 1567 08:45:08.759419  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 1568 08:45:08.759606  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 1569 08:45:08.759793  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 1570 08:45:08.759982  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 1571 08:45:08.760169  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 1572 08:45:08.760356  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 1573 08:45:08.760543  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 1574 08:45:08.760741  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 1575 08:45:08.760884  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 1576 08:45:08.761269  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 1577 08:45:08.761363  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 1578 08:45:08.761451  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 1579 08:45:08.761537  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 1580 08:45:08.761621  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 1581 08:45:08.761707  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 1582 08:45:08.761793  dt_test_unprobed_devices_sh_opp-table skip
 1583 08:45:08.761879  dt_test_unprobed_devices_sh_soc skip
 1584 08:45:08.761964  dt_test_unprobed_devices_sh_sound pass
 1585 08:45:08.762049  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 1586 08:45:08.762134  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 1587 08:45:08.762220  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 1588 08:45:08.762306  dt_test_unprobed_devices_sh fail
 1589 08:45:08.762407  + ../../utils/send-to-lava.sh ./output/result.txt
 1590 08:45:08.762495  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 1591 08:45:08.762584  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 1592 08:45:08.762671  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 1593 08:45:08.762758  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 1594 08:45:08.762844  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 1595 08:45:08.762930  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 1596 08:45:08.763017  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 1597 08:45:08.763103  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 1598 08:45:08.763190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 1599 08:45:08.763276  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 1600 08:45:08.763363  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 1601 08:45:08.763450  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 1602 08:45:08.763537  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 1603 08:45:08.763625  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 1604 08:45:08.763713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 1605 08:45:08.763799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 1606 08:45:08.763887  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 1607 08:45:08.763977  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 1608 08:45:08.764068  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 1609 08:45:08.764158  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 1610 08:45:08.764248  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 1611 08:45:08.764338  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 1612 08:45:08.764427  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 1613 08:45:08.764517  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 1614 08:45:08.764606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 1615 08:45:08.764697  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 1616 08:45:08.765072  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 1618 08:45:08.765391  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 1620 08:45:08.765673  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 1622 08:45:08.765958  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 1624 08:45:08.766256  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 1626 08:45:08.766570  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 1628 08:45:08.766849  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 1630 08:45:08.767125  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 1632 08:45:08.767406  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 1634 08:45:08.767679  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 1636 08:45:08.767954  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 1638 08:45:08.768229  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 1640 08:45:08.768504  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 1642 08:45:08.768786  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 1644 08:45:08.769062  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 1646 08:45:08.769335  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 1648 08:45:08.769610  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 1650 08:45:08.769885  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 1652 08:45:08.770159  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 1654 08:45:08.770433  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 1656 08:45:08.770706  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 1658 08:45:08.770980  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 1660 08:45:08.771254  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 1662 08:45:08.771526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 1664 08:45:08.771796  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 1666 08:45:08.772083  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 1668 08:45:08.772427  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 1669 08:45:08.772525  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 1670 08:45:08.772618  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 1671 08:45:08.772719  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 1672 08:45:08.772822  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 1673 08:45:08.772911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 1674 08:45:08.773000  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 1675 08:45:08.773089  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 1676 08:45:08.773179  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 1677 08:45:08.773267  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 1678 08:45:08.773354  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 1679 08:45:08.773442  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 1680 08:45:08.773529  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 1681 08:45:08.773617  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 1682 08:45:08.773705  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 1683 08:45:08.773792  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 1684 08:45:08.773880  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 1685 08:45:08.773968  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 1686 08:45:08.774056  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 1687 08:45:08.774144  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 1688 08:45:08.774232  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 1689 08:45:08.774319  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 1690 08:45:08.774407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 1691 08:45:08.774494  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 1692 08:45:08.774582  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 1693 08:45:08.774669  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 1694 08:45:08.774973  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 1696 08:45:08.775274  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 1698 08:45:08.775549  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 1700 08:45:08.775820  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 1702 08:45:08.776108  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 1704 08:45:08.776380  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 1706 08:45:08.776650  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 1708 08:45:08.776932  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 1710 08:45:08.777201  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 1712 08:45:08.777469  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 1714 08:45:08.777737  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 1716 08:45:08.778014  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 1718 08:45:08.778314  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 1720 08:45:08.778588  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 1722 08:45:08.778858  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 1724 08:45:08.779126  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 1726 08:45:08.779394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 1728 08:45:08.779673  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 1730 08:45:08.779943  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 1732 08:45:08.780223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 1734 08:45:08.780493  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 1736 08:45:08.780765  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 1738 08:45:08.781030  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 1740 08:45:08.781297  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 1742 08:45:08.781568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 1744 08:45:08.781832  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 1746 08:45:08.782151  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 1747 08:45:08.782242  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 1748 08:45:08.782339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 1749 08:45:08.782445  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 1750 08:45:08.782532  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 1751 08:45:08.782618  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 1752 08:45:08.782704  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 1753 08:45:08.782790  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 1754 08:45:08.782876  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 1755 08:45:08.782961  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 1756 08:45:08.783047  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 1757 08:45:08.783133  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 1758 08:45:08.783228  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 1759 08:45:08.783325  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 1760 08:45:08.783427  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 1761 08:45:08.783513  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 1762 08:45:08.783599  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 1763 08:45:08.783685  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 1764 08:45:08.783770  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 1765 08:45:08.783855  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 1766 08:45:08.783940  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 1767 08:45:08.784025  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 1768 08:45:08.784109  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 1769 08:45:08.784194  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 1770 08:45:08.784504  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 1772 08:45:08.784840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 1774 08:45:08.785115  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 1776 08:45:08.785386  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 1778 08:45:08.785657  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 1780 08:45:08.785927  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 1782 08:45:08.786198  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 1784 08:45:08.786468  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 1786 08:45:08.786737  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 1788 08:45:08.787007  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 1790 08:45:08.787275  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 1792 08:45:08.787544  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 1794 08:45:08.787812  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 1796 08:45:08.788080  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 1798 08:45:08.788348  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 1800 08:45:08.788616  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 1802 08:45:08.788896  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 1804 08:45:08.789163  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 1806 08:45:08.789427  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 1808 08:45:08.789693  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 1810 08:45:08.789959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 1812 08:45:08.790226  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 1814 08:45:08.790490  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 1816 08:45:08.790753  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 1818 08:45:08.791055  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 1819 08:45:08.791150  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 1820 08:45:08.791241  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 1821 08:45:08.791330  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 1822 08:45:08.791419  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 1823 08:45:08.791508  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 1824 08:45:08.791596  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 1825 08:45:08.791684  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 1826 08:45:08.791771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 1827 08:45:08.791859  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 1828 08:45:08.791954  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 1829 08:45:08.792040  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 1830 08:45:08.792124  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 1831 08:45:08.792209  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 1832 08:45:08.792294  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 1833 08:45:08.792379  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 1834 08:45:08.792464  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 1835 08:45:08.792549  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 1836 08:45:08.792634  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 1837 08:45:08.792754  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 1838 08:45:08.792841  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 1839 08:45:08.792926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 1840 08:45:08.793022  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 1841 08:45:08.793117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 1842 08:45:08.793219  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 1843 08:45:08.793521  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 1845 08:45:08.793820  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 1847 08:45:08.794127  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 1849 08:45:08.794410  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 1851 08:45:08.794690  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 1853 08:45:08.794960  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 1855 08:45:08.795230  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 1857 08:45:08.795498  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 1859 08:45:08.795766  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 1861 08:45:08.796032  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 1863 08:45:08.796300  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 1865 08:45:08.796567  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 1867 08:45:08.796865  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 1869 08:45:08.797131  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 1871 08:45:08.797401  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 1873 08:45:08.797670  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 1875 08:45:08.797936  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 1877 08:45:08.798201  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 1879 08:45:08.798466  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 1881 08:45:08.798734  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 1883 08:45:08.798997  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 1885 08:45:08.799260  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 1887 08:45:08.799523  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 1889 08:45:08.799785  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 1891 08:45:08.800047  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 1893 08:45:08.800336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 1894 08:45:08.800429  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 1895 08:45:08.800519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 1896 08:45:08.800607  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 1897 08:45:08.800695  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 1898 08:45:08.800813  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 1899 08:45:08.800901  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 1900 08:45:08.800989  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 1901 08:45:08.801076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 1902 08:45:08.801164  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 1903 08:45:08.801251  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 1904 08:45:08.801338  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 1905 08:45:08.801425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 1906 08:45:08.801513  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 1907 08:45:08.801601  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 1908 08:45:08.801688  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 1909 08:45:08.801775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 1910 08:45:08.801863  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 1911 08:45:08.801950  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 1912 08:45:08.802037  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 1913 08:45:08.802124  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 1914 08:45:08.802213  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 1915 08:45:08.802300  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 1916 08:45:08.802387  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 1917 08:45:08.802690  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 1919 08:45:08.802989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 1921 08:45:08.803257  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 1923 08:45:08.803526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 1925 08:45:08.803794  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 1927 08:45:08.804063  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 1929 08:45:08.804333  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 1931 08:45:08.804601  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 1933 08:45:08.804895  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 1935 08:45:08.805166  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 1937 08:45:08.805434  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 1939 08:45:08.805702  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 1941 08:45:08.805968  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 1943 08:45:08.806255  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 1945 08:45:08.806524  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 1947 08:45:08.806791  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 1949 08:45:08.807057  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 1951 08:45:08.807326  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 1953 08:45:08.807594  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 1955 08:45:08.807860  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 1957 08:45:08.808128  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 1959 08:45:08.808393  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 1961 08:45:08.808657  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 1963 08:45:08.808953  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 1965 08:45:08.809243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 1966 08:45:08.809336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 1967 08:45:08.809425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 1968 08:45:08.809513  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 1969 08:45:08.809602  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 1970 08:45:08.809689  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 1971 08:45:08.809777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 1972 08:45:08.809864  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 1973 08:45:08.809959  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 1974 08:45:08.810044  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 1975 08:45:08.810129  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 1976 08:45:08.810215  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 1977 08:45:08.810299  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 1978 08:45:08.810384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 1979 08:45:08.810469  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 1980 08:45:08.810553  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 1981 08:45:08.810638  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 1982 08:45:08.810722  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 1983 08:45:08.810806  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 1984 08:45:08.810891  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 1985 08:45:08.810975  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 1986 08:45:08.811059  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 1987 08:45:08.811143  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 1988 08:45:08.811236  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 1989 08:45:08.811328  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 1990 08:45:08.811430  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 1991 08:45:08.811514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 1992 08:45:08.811598  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 1993 08:45:08.811682  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 1994 08:45:08.811982  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 1996 08:45:08.812292  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 1998 08:45:08.812591  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 2000 08:45:08.812887  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 2002 08:45:08.813156  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 2004 08:45:08.813422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 2006 08:45:08.813690  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 2008 08:45:08.813957  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 2010 08:45:08.814227  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 2012 08:45:08.814496  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 2014 08:45:08.814763  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 2016 08:45:08.815030  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 2018 08:45:08.815297  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 2020 08:45:08.815564  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 2022 08:45:08.815831  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 2024 08:45:08.816098  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 2026 08:45:08.816365  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 2028 08:45:08.816632  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 2030 08:45:08.816913  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 2032 08:45:08.817177  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 2034 08:45:08.817441  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 2036 08:45:08.817706  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 2038 08:45:08.817968  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 2040 08:45:08.818230  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 2042 08:45:08.818493  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 2044 08:45:08.818758  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 2046 08:45:08.819023  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 2048 08:45:08.819285  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 2050 08:45:08.819547  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 2052 08:45:08.819837  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 2053 08:45:08.819930  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 2054 08:45:08.820020  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 2055 08:45:08.820108  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 2056 08:45:08.820196  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 2057 08:45:08.820283  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 2058 08:45:08.820372  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 2059 08:45:08.820459  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 2060 08:45:08.820547  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 2061 08:45:08.820635  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 2062 08:45:08.820750  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 2063 08:45:08.820839  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 2064 08:45:08.820927  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 2065 08:45:08.821014  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 2066 08:45:08.821101  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 2067 08:45:08.821188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 2068 08:45:08.821274  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 2069 08:45:08.821360  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 2070 08:45:08.821447  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 2071 08:45:08.821533  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 2072 08:45:08.821619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 2073 08:45:08.821706  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 2074 08:45:08.821792  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 2075 08:45:08.821879  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 2076 08:45:08.821965  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 2077 08:45:08.822058  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 2078 08:45:08.822143  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 2079 08:45:08.822228  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 2080 08:45:08.822312  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 2081 08:45:08.822614  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 2083 08:45:08.822916  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 2085 08:45:08.823186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 2087 08:45:08.823453  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 2089 08:45:08.823719  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 2091 08:45:08.823984  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 2093 08:45:08.824250  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 2095 08:45:08.824517  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 2097 08:45:08.824810  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 2099 08:45:08.825077  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 2101 08:45:08.825342  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 2103 08:45:08.825608  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 2105 08:45:08.825872  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 2107 08:45:08.826136  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 2109 08:45:08.826400  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 2111 08:45:08.826665  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 2113 08:45:08.826928  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 2115 08:45:08.827193  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 2117 08:45:08.827457  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 2119 08:45:08.827721  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 2121 08:45:08.827984  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 2123 08:45:08.828246  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 2125 08:45:08.828508  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 2127 08:45:08.828821  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 2129 08:45:08.829085  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 2131 08:45:08.829349  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 2133 08:45:08.829608  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 2135 08:45:08.829868  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 2137 08:45:08.830127  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 2139 08:45:08.830401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 2140 08:45:08.830493  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 2141 08:45:08.830580  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 2142 08:45:08.830667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 2143 08:45:08.830943  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 2145 08:45:08.831223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 2147 08:45:08.831483  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 2149 08:45:08.831742  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 2151 08:45:08.860585  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 2152 08:45:08.861124  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 2154 08:45:08.956723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 2155 08:45:08.957035  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 2157 08:45:09.057687  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 2158 08:45:09.058174  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 2160 08:45:09.156219  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 2161 08:45:09.156699  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 2163 08:45:09.255751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 2164 08:45:09.256229  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 2166 08:45:09.352329  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 2167 08:45:09.352818  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 2169 08:45:09.450370  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 2170 08:45:09.450849  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 2172 08:45:09.550175  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 2173 08:45:09.550653  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 2175 08:45:09.649544  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 2176 08:45:09.650026  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 2178 08:45:09.749415  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 2179 08:45:09.749896  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 2181 08:45:09.847479  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 2182 08:45:09.847977  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 2184 08:45:09.947289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 2185 08:45:09.947778  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 2187 08:45:10.049155  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 2188 08:45:10.049635  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 2190 08:45:10.149649  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 2191 08:45:10.150135  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 2193 08:45:10.247027  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 2194 08:45:10.247510  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 2196 08:45:10.349522  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 2197 08:45:10.350000  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 2199 08:45:10.445982  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 2200 08:45:10.446533  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 2202 08:45:10.546927  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 2203 08:45:10.547399  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 2205 08:45:10.646456  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 2206 08:45:10.647011  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 2208 08:45:10.746578  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 2209 08:45:10.747048  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 2211 08:45:10.844301  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 2212 08:45:10.844762  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 2214 08:45:10.943913  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 2215 08:45:10.944416  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 2217 08:45:11.037971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 2218 08:45:11.038442  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 2220 08:45:11.133865  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 2221 08:45:11.134351  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 2223 08:45:11.238982  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 2224 08:45:11.239455  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 2226 08:45:11.337675  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 2227 08:45:11.338144  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 2229 08:45:11.437292  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 2230 08:45:11.437762  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 2232 08:45:11.533292  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 2233 08:45:11.533761  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 2235 08:45:11.633682  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 2236 08:45:11.634152  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 2238 08:45:11.734943  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 2239 08:45:11.735415  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 2241 08:45:11.838352  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 2242 08:45:11.838840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 2244 08:45:11.936105  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 2245 08:45:11.936589  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 2247 08:45:12.037810  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 2248 08:45:12.038279  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 2250 08:45:12.138558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 2251 08:45:12.139029  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 2253 08:45:12.234076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 2254 08:45:12.234555  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 2256 08:45:12.334430  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 2257 08:45:12.334899  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 2259 08:45:12.433673  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 2260 08:45:12.434143  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 2262 08:45:12.533795  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 2263 08:45:12.534266  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 2265 08:45:12.632291  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 2266 08:45:12.632779  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 2268 08:45:12.732191  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 2269 08:45:12.732670  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 2271 08:45:12.823301  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 2273 08:45:12.826285  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 2274 08:45:12.918162  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 2275 08:45:12.918646  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 2277 08:45:13.011784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 2278 08:45:13.012261  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 2280 08:45:13.107030  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 2281 08:45:13.107502  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 2283 08:45:13.200900  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 2284 08:45:13.201374  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 2286 08:45:13.294396  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 2287 08:45:13.294864  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 2289 08:45:13.388438  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 2290 08:45:13.388925  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 2292 08:45:13.479392  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 2293 08:45:13.479860  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 2295 08:45:13.575515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 2296 08:45:13.575982  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 2298 08:45:13.667633  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 2299 08:45:13.668104  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 2301 08:45:13.762627  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 2302 08:45:13.763097  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 2304 08:45:13.858626  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 2305 08:45:13.859103  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 2307 08:45:13.953414  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 2308 08:45:13.953899  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 2310 08:45:14.048017  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 2311 08:45:14.048487  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 2313 08:45:14.142615  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 2314 08:45:14.143082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 2316 08:45:14.237383  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 2317 08:45:14.237853  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 2319 08:45:14.329610  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 2320 08:45:14.330080  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 2322 08:45:14.424392  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 2323 08:45:14.424864  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 2325 08:45:14.519096  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 2326 08:45:14.519564  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 2328 08:45:14.613972  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 2329 08:45:14.614456  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 2331 08:45:14.707653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 2332 08:45:14.708146  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 2334 08:45:14.801303  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 2335 08:45:14.801789  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 2337 08:45:14.900289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 2338 08:45:14.900773  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 2340 08:45:14.999299  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 2341 08:45:14.999772  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 2343 08:45:15.099830  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 2344 08:45:15.100306  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 2346 08:45:15.195629  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 2347 08:45:15.196114  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 2349 08:45:15.290849  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 2350 08:45:15.291325  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 2352 08:45:15.389263  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 2353 08:45:15.389746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 2355 08:45:15.492158  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 2356 08:45:15.492632  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 2358 08:45:15.591969  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 2359 08:45:15.592445  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 2361 08:45:15.693392  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 2362 08:45:15.693879  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 2364 08:45:15.789266  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 2365 08:45:15.789616  + set +x
 2366 08:45:15.790126  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 2368 08:45:15.793652  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1209565_1.6.2.4.5>
 2369 08:45:15.794133  Received signal: <ENDRUN> 1_kselftest-dt 1209565_1.6.2.4.5
 2370 08:45:15.794380  Ending use of test pattern.
 2371 08:45:15.794597  Ending test lava.1_kselftest-dt (1209565_1.6.2.4.5), duration 95.05
 2373 08:45:15.801716  <LAVA_TEST_RUNNER EXIT>
 2374 08:45:15.802193  ok: lava_test_shell seems to have completed
 2375 08:45:15.808153  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 2376 08:45:15.809107  end: 3.1 lava-test-shell (duration 00:01:37) [common]
 2377 08:45:15.809305  end: 3 lava-test-retry (duration 00:01:37) [common]
 2378 08:45:15.809505  start: 4 finalize (timeout 00:05:21) [common]
 2379 08:45:15.809701  start: 4.1 power-off (timeout 00:00:30) [common]
 2380 08:45:15.809963  Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
 2381 08:45:16.178206  Returned 0 in 0 seconds
 2382 08:45:16.279114  end: 4.1 power-off (duration 00:00:00) [common]
 2384 08:45:16.280025  start: 4.2 read-feedback (timeout 00:05:21) [common]
 2385 08:45:16.280644  Listened to connection for namespace 'common' for up to 1s
 2386 08:45:16.281206  Listened to connection for namespace 'common' for up to 1s
 2387 08:45:17.281539  Finalising connection for namespace 'common'
 2388 08:45:17.281963  Disconnecting from shell: Finalise
 2389 08:45:17.282234  / # 
 2390 08:45:17.382795  end: 4.2 read-feedback (duration 00:00:01) [common]
 2391 08:45:17.383157  end: 4 finalize (duration 00:00:02) [common]
 2392 08:45:17.383512  Cleaning after the job
 2393 08:45:17.383824  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/ramdisk
 2394 08:45:17.387391  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/kernel
 2395 08:45:17.390220  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/dtb
 2396 08:45:17.390692  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/nfsrootfs
 2397 08:45:17.439196  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1209565/tftp-deploy-cjedyn5k/modules
 2398 08:45:17.442447  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1209565
 2399 08:45:18.095176  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1209565
 2400 08:45:18.095452  Job finished correctly