Boot log: beaglebone-black

    1 18:47:02.756573  lava-dispatcher, installed at version: 2023.08
    2 18:47:02.756958  start: 0 validate
    3 18:47:02.757195  Start time: 2024-10-14 18:47:02.757180+00:00 (UTC)
    4 18:47:02.757470  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 18:47:03.095362  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
    6 18:47:03.253209  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 18:47:03.411477  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 18:47:03.570324  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
    9 18:47:03.737451  validate duration: 0.98
   11 18:47:03.738597  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 18:47:03.739067  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 18:47:03.739509  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 18:47:03.740246  Not decompressing ramdisk as can be used compressed.
   15 18:47:03.740696  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 18:47:03.741038  saving as /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/ramdisk/initrd.cpio.gz
   17 18:47:03.741385  total size: 4775763 (4 MB)
   18 18:47:04.057880  progress   0 % (0 MB)
   19 18:47:04.527724  progress   5 % (0 MB)
   20 18:47:04.683924  progress  10 % (0 MB)
   21 18:47:04.870772  progress  15 % (0 MB)
   22 18:47:05.037388  progress  20 % (0 MB)
   23 18:47:05.043753  progress  25 % (1 MB)
   24 18:47:05.049743  progress  30 % (1 MB)
   25 18:47:05.056539  progress  35 % (1 MB)
   26 18:47:05.160646  progress  40 % (1 MB)
   27 18:47:05.188445  progress  45 % (2 MB)
   28 18:47:05.336880  progress  50 % (2 MB)
   29 18:47:05.482980  progress  55 % (2 MB)
   30 18:47:05.510509  progress  60 % (2 MB)
   31 18:47:05.656642  progress  65 % (2 MB)
   32 18:47:05.807039  progress  70 % (3 MB)
   33 18:47:05.937515  progress  75 % (3 MB)
   34 18:47:05.974817  progress  80 % (3 MB)
   35 18:47:06.118425  progress  85 % (3 MB)
   36 18:47:06.252673  progress  90 % (4 MB)
   37 18:47:06.289876  progress  95 % (4 MB)
   38 18:47:06.430665  progress 100 % (4 MB)
   39 18:47:06.431719  4 MB downloaded in 2.69 s (1.69 MB/s)
   40 18:47:06.432426  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 18:47:06.433588  end: 1.1 download-retry (duration 00:00:03) [common]
   43 18:47:06.434035  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 18:47:06.434440  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 18:47:06.435043  downloading http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/kernel/zImage
   46 18:47:06.435368  saving as /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/kernel/zImage
   47 18:47:06.435676  total size: 11444736 (10 MB)
   48 18:47:06.435985  No compression specified
   49 18:47:06.598036  progress   0 % (0 MB)
   50 18:47:06.787555  progress   5 % (0 MB)
   51 18:47:07.093495  progress  10 % (1 MB)
   52 18:47:07.539235  progress  15 % (1 MB)
   53 18:47:07.851836  progress  20 % (2 MB)
   54 18:47:08.167628  progress  25 % (2 MB)
   55 18:47:08.476945  progress  30 % (3 MB)
   56 18:47:08.787656  progress  35 % (3 MB)
   57 18:47:08.984594  progress  40 % (4 MB)
   58 18:47:09.295506  progress  45 % (4 MB)
   59 18:47:09.604236  progress  50 % (5 MB)
   60 18:47:09.914516  progress  55 % (6 MB)
   61 18:47:10.217794  progress  60 % (6 MB)
   62 18:47:10.526823  progress  65 % (7 MB)
   63 18:47:10.830395  progress  70 % (7 MB)
   64 18:47:11.022142  progress  75 % (8 MB)
   65 18:47:11.332049  progress  80 % (8 MB)
   66 18:47:11.640004  progress  85 % (9 MB)
   67 18:47:11.949796  progress  90 % (9 MB)
   68 18:47:12.248889  progress  95 % (10 MB)
   69 18:47:12.551144  progress 100 % (10 MB)
   70 18:47:12.551953  10 MB downloaded in 6.12 s (1.78 MB/s)
   71 18:47:12.552809  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 18:47:12.554063  end: 1.2 download-retry (duration 00:00:06) [common]
   74 18:47:12.554493  start: 1.3 download-retry (timeout 00:09:51) [common]
   75 18:47:12.554940  start: 1.3.1 http-download (timeout 00:09:51) [common]
   76 18:47:12.555569  downloading http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
   77 18:47:12.555926  saving as /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/dtb/am335x-boneblack.dtb
   78 18:47:12.556261  total size: 70568 (0 MB)
   79 18:47:12.556563  No compression specified
   80 18:47:12.719182  progress  46 % (0 MB)
   81 18:47:12.722082  progress  92 % (0 MB)
   82 18:47:12.723369  progress 100 % (0 MB)
   83 18:47:12.723923  0 MB downloaded in 0.17 s (0.40 MB/s)
   84 18:47:12.724491  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 18:47:12.725574  end: 1.3 download-retry (duration 00:00:00) [common]
   87 18:47:12.725997  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 18:47:12.726399  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 18:47:12.726944  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 18:47:12.727258  saving as /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/nfsrootfs/full.rootfs.tar
   91 18:47:12.727551  total size: 117747780 (112 MB)
   92 18:47:12.727861  Using unxz to decompress xz
   93 18:47:12.889585  progress   0 % (0 MB)
   94 18:47:16.218000  progress   5 % (5 MB)
   95 18:47:19.194518  progress  10 % (11 MB)
   96 18:47:22.139514  progress  15 % (16 MB)
   97 18:47:24.543187  progress  20 % (22 MB)
   98 18:47:26.413397  progress  25 % (28 MB)
   99 18:47:27.812225  progress  30 % (33 MB)
  100 18:47:28.901778  progress  35 % (39 MB)
  101 18:47:29.810311  progress  40 % (44 MB)
  102 18:47:30.746909  progress  45 % (50 MB)
  103 18:47:31.729294  progress  50 % (56 MB)
  104 18:47:32.631637  progress  55 % (61 MB)
  105 18:47:33.489540  progress  60 % (67 MB)
  106 18:47:34.305880  progress  65 % (73 MB)
  107 18:47:35.107616  progress  70 % (78 MB)
  108 18:47:35.897478  progress  75 % (84 MB)
  109 18:47:36.679210  progress  80 % (89 MB)
  110 18:47:37.460830  progress  85 % (95 MB)
  111 18:47:38.238444  progress  90 % (101 MB)
  112 18:47:39.013728  progress  95 % (106 MB)
  113 18:47:39.788623  progress 100 % (112 MB)
  114 18:47:39.791378  112 MB downloaded in 27.06 s (4.15 MB/s)
  115 18:47:39.791924  end: 1.4.1 http-download (duration 00:00:27) [common]
  117 18:47:39.793041  end: 1.4 download-retry (duration 00:00:27) [common]
  118 18:47:39.793440  start: 1.5 download-retry (timeout 00:09:24) [common]
  119 18:47:39.793869  start: 1.5.1 http-download (timeout 00:09:24) [common]
  120 18:47:39.794160  downloading http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
  121 18:47:39.794432  saving as /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/modules/modules.tar
  122 18:47:39.794726  total size: 6603628 (6 MB)
  123 18:47:39.795027  Using unxz to decompress xz
  124 18:47:39.956634  progress   0 % (0 MB)
  125 18:47:40.139942  progress   5 % (0 MB)
  126 18:47:40.187460  progress  10 % (0 MB)
  127 18:47:40.230097  progress  15 % (0 MB)
  128 18:47:40.261936  progress  20 % (1 MB)
  129 18:47:40.290061  progress  25 % (1 MB)
  130 18:47:40.319333  progress  30 % (1 MB)
  131 18:47:40.348949  progress  35 % (2 MB)
  132 18:47:40.377438  progress  40 % (2 MB)
  133 18:47:40.447257  progress  45 % (2 MB)
  134 18:47:40.483423  progress  50 % (3 MB)
  135 18:47:40.584558  progress  55 % (3 MB)
  136 18:47:40.616926  progress  60 % (3 MB)
  137 18:47:40.654594  progress  65 % (4 MB)
  138 18:47:40.755065  progress  70 % (4 MB)
  139 18:47:40.787496  progress  75 % (4 MB)
  140 18:47:40.825910  progress  80 % (5 MB)
  141 18:47:40.920356  progress  85 % (5 MB)
  142 18:47:40.954376  progress  90 % (5 MB)
  143 18:47:41.035023  progress  95 % (6 MB)
  144 18:47:41.083199  progress 100 % (6 MB)
  145 18:47:41.093226  6 MB downloaded in 1.30 s (4.85 MB/s)
  146 18:47:41.093856  end: 1.5.1 http-download (duration 00:00:01) [common]
  148 18:47:41.094801  end: 1.5 download-retry (duration 00:00:01) [common]
  149 18:47:41.095202  start: 1.6 prepare-tftp-overlay (timeout 00:09:23) [common]
  150 18:47:41.095599  start: 1.6.1 extract-nfsrootfs (timeout 00:09:23) [common]
  151 18:47:50.202025  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo
  152 18:47:50.202402  end: 1.6.1 extract-nfsrootfs (duration 00:00:09) [common]
  153 18:47:50.202581  start: 1.6.2 lava-overlay (timeout 00:09:14) [common]
  154 18:47:50.202957  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p
  155 18:47:50.203217  makedir: /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin
  156 18:47:50.203417  makedir: /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/tests
  157 18:47:50.203610  makedir: /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/results
  158 18:47:50.203806  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-add-keys
  159 18:47:50.204102  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-add-sources
  160 18:47:50.204364  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-background-process-start
  161 18:47:50.204626  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-background-process-stop
  162 18:47:50.204906  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-common-functions
  163 18:47:50.205164  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-echo-ipv4
  164 18:47:50.205419  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-install-packages
  165 18:47:50.205677  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-installed-packages
  166 18:47:50.206036  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-os-build
  167 18:47:50.206289  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-probe-channel
  168 18:47:50.206549  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-probe-ip
  169 18:47:50.206805  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-target-ip
  170 18:47:50.207073  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-target-mac
  171 18:47:50.207332  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-target-storage
  172 18:47:50.207591  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-case
  173 18:47:50.207848  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-event
  174 18:47:50.208098  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-feedback
  175 18:47:50.208422  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-raise
  176 18:47:50.208677  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-reference
  177 18:47:50.208934  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-runner
  178 18:47:50.209188  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-set
  179 18:47:50.209442  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-test-shell
  180 18:47:50.209703  Updating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-add-keys (debian)
  181 18:47:50.210028  Updating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-add-sources (debian)
  182 18:47:50.210304  Updating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-install-packages (debian)
  183 18:47:50.210581  Updating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-installed-packages (debian)
  184 18:47:50.210858  Updating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/bin/lava-os-build (debian)
  185 18:47:50.211095  Creating /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/environment
  186 18:47:50.211279  LAVA metadata
  187 18:47:50.211412  - LAVA_JOB_ID=1206272
  188 18:47:50.211537  - LAVA_DISPATCHER_IP=172.16.3.3
  189 18:47:50.211731  start: 1.6.2.1 ssh-authorize (timeout 00:09:14) [common]
  190 18:47:50.212220  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 18:47:50.212384  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:14) [common]
  192 18:47:50.212505  skipped lava-vland-overlay
  193 18:47:50.212651  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 18:47:50.212805  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:14) [common]
  195 18:47:50.212930  skipped lava-multinode-overlay
  196 18:47:50.213075  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 18:47:50.213225  start: 1.6.2.4 test-definition (timeout 00:09:14) [common]
  198 18:47:50.213359  Loading test definitions
  199 18:47:50.213520  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:14) [common]
  200 18:47:50.213650  Using /lava-1206272 at stage 0
  201 18:47:50.214340  uuid=1206272_1.6.2.4.1 testdef=None
  202 18:47:50.214507  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 18:47:50.214665  start: 1.6.2.4.2 test-overlay (timeout 00:09:14) [common]
  204 18:47:50.215546  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 18:47:50.215986  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:14) [common]
  207 18:47:50.217040  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 18:47:50.217478  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:14) [common]
  210 18:47:50.241456  runner path: /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/0/tests/0_timesync-off test_uuid 1206272_1.6.2.4.1
  211 18:47:50.241753  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 18:47:50.242211  start: 1.6.2.4.5 git-repo-action (timeout 00:09:13) [common]
  214 18:47:50.242347  Using /lava-1206272 at stage 0
  215 18:47:50.242539  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 18:47:50.242679  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/0/tests/1_kselftest-dt'
  217 18:47:56.272303  Running '/usr/bin/git checkout kernelci.org
  218 18:47:56.522066  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 18:47:56.523321  uuid=1206272_1.6.2.4.5 testdef=None
  220 18:47:56.523712  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 18:47:56.524199  start: 1.6.2.4.6 test-overlay (timeout 00:09:07) [common]
  223 18:47:56.526707  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 18:47:56.527328  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:07) [common]
  226 18:47:56.530910  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 18:47:56.531550  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:07) [common]
  229 18:47:56.554438  runner path: /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/0/tests/1_kselftest-dt test_uuid 1206272_1.6.2.4.5
  230 18:47:56.554789  BOARD='beaglebone-black'
  231 18:47:56.554918  BRANCH='mainline'
  232 18:47:56.555039  SKIPFILE='/dev/null'
  233 18:47:56.555164  SKIP_INSTALL='True'
  234 18:47:56.555282  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
  235 18:47:56.555401  TST_CASENAME=''
  236 18:47:56.555518  TST_CMDFILES='dt'
  237 18:47:56.555803  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 18:47:56.556215  Creating lava-test-runner.conf files
  240 18:47:56.556338  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1206272/lava-overlay-wnt92t5p/lava-1206272/0 for stage 0
  241 18:47:56.556593  - 0_timesync-off
  242 18:47:56.556863  - 1_kselftest-dt
  243 18:47:56.557114  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 18:47:56.557431  start: 1.6.2.5 compress-overlay (timeout 00:09:07) [common]
  245 18:48:07.673547  end: 1.6.2.5 compress-overlay (duration 00:00:11) [common]
  246 18:48:07.673783  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
  247 18:48:07.673976  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 18:48:07.674144  end: 1.6.2 lava-overlay (duration 00:00:17) [common]
  249 18:48:07.674310  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
  250 18:48:07.840793  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 18:48:07.841059  start: 1.6.4 extract-modules (timeout 00:08:56) [common]
  252 18:48:07.841215  extracting modules file /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo
  253 18:48:08.322746  extracting modules file /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1206272/extract-overlay-ramdisk-_3twhmbi/ramdisk
  254 18:48:08.794964  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 18:48:08.795261  start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
  256 18:48:08.795416  [common] Applying overlay to NFS
  257 18:48:08.795546  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1206272/compress-overlay-ynmcebhk/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo
  258 18:48:10.431913  end: 1.6.5 apply-overlay-tftp (duration 00:00:02) [common]
  259 18:48:10.432159  start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
  260 18:48:10.432333  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
  261 18:48:10.432508  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 18:48:10.432666  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 18:48:10.432827  start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
  264 18:48:10.432982  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 18:48:10.433138  start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
  266 18:48:10.433271  Building ramdisk /var/lib/lava/dispatcher/tmp/1206272/extract-overlay-ramdisk-_3twhmbi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1206272/extract-overlay-ramdisk-_3twhmbi/ramdisk
  267 18:48:10.720601  >> 74887 blocks

  268 18:48:13.193792  Adding RAMdisk u-boot header.
  269 18:48:13.194148  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1206272/extract-overlay-ramdisk-_3twhmbi/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1206272/extract-overlay-ramdisk-_3twhmbi/ramdisk.cpio.gz.uboot
  270 18:48:13.459821  output: Image Name:   
  271 18:48:13.460209  output: Created:      Mon Oct 14 18:48:13 2024
  272 18:48:13.460532  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 18:48:13.460840  output: Data Size:    14794001 Bytes = 14447.27 KiB = 14.11 MiB
  274 18:48:13.461138  output: Load Address: 00000000
  275 18:48:13.461431  output: Entry Point:  00000000
  276 18:48:13.461721  output: 
  277 18:48:13.462113  rename /var/lib/lava/dispatcher/tmp/1206272/extract-overlay-ramdisk-_3twhmbi/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot
  278 18:48:13.462622  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 18:48:13.463037  end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
  280 18:48:13.463439  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
  281 18:48:13.463756  No LXC device requested
  282 18:48:13.464131  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 18:48:13.464525  start: 1.8 deploy-device-env (timeout 00:08:50) [common]
  284 18:48:13.464905  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 18:48:13.465210  Checking files for TFTP limit of 4294967296 bytes.
  286 18:48:13.466950  end: 1 tftp-deploy (duration 00:01:10) [common]
  287 18:48:13.467371  start: 2 uboot-action (timeout 00:05:00) [common]
  288 18:48:13.467775  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 18:48:13.468158  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 18:48:13.468549  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 18:48:13.469110  substitutions:
  292 18:48:13.469421  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 18:48:13.469722  - {DTB_ADDR}: 0x88000000
  294 18:48:13.469951  - {DTB}: 1206272/tftp-deploy-q3rg7qgn/dtb/am335x-boneblack.dtb
  295 18:48:13.470102  - {INITRD}: 1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot
  296 18:48:13.470397  - {KERNEL_ADDR}: 0x82000000
  297 18:48:13.470688  - {KERNEL}: 1206272/tftp-deploy-q3rg7qgn/kernel/zImage
  298 18:48:13.470974  - {LAVA_MAC}: None
  299 18:48:13.471277  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo
  300 18:48:13.471564  - {NFS_SERVER_IP}: 172.16.3.3
  301 18:48:13.471846  - {PRESEED_CONFIG}: None
  302 18:48:13.472125  - {PRESEED_LOCAL}: None
  303 18:48:13.472407  - {RAMDISK_ADDR}: 0x83000000
  304 18:48:13.472688  - {RAMDISK}: 1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot
  305 18:48:13.472969  - {ROOT_PART}: None
  306 18:48:13.473246  - {ROOT}: None
  307 18:48:13.473521  - {SERVER_IP}: 172.16.3.3
  308 18:48:13.473795  - {TEE_ADDR}: 0x83000000
  309 18:48:13.473954  - {TEE}: None
  310 18:48:13.474073  Parsed boot commands:
  311 18:48:13.474359  - setenv autoload no
  312 18:48:13.474633  - setenv initrd_high 0xffffffff
  313 18:48:13.474908  - setenv fdt_high 0xffffffff
  314 18:48:13.475180  - dhcp
  315 18:48:13.475452  - setenv serverip 172.16.3.3
  316 18:48:13.475724  - tftp 0x82000000 1206272/tftp-deploy-q3rg7qgn/kernel/zImage
  317 18:48:13.476001  - tftp 0x83000000 1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot
  318 18:48:13.476280  - setenv initrd_size ${filesize}
  319 18:48:13.476554  - tftp 0x88000000 1206272/tftp-deploy-q3rg7qgn/dtb/am335x-boneblack.dtb
  320 18:48:13.476829  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 18:48:13.477114  - bootz 0x82000000 0x83000000 0x88000000
  322 18:48:13.477473  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 18:48:13.478275  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 18:48:13.478574  [common] connect-device Connecting to device using 'telnet ts5 2000'
  326 18:48:13.485791  Setting prompt string to ['lava-test: # ']
  327 18:48:13.486294  end: 2.3 connect-device (duration 00:00:00) [common]
  328 18:48:13.486495  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 18:48:13.486682  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 18:48:13.486867  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 18:48:13.487166  Calling: 'drpm' 'lf-bbb' 'powercycle'
  332 18:48:13.824000  >> OFF

  333 18:48:29.114646  >> ON

  334 18:48:29.115433  Returned 0 in 15 seconds
  335 18:48:29.216352  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 18:48:29.217480  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 18:48:29.217921  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 18:48:29.218186  Setting prompt string to ['Hit any key to stop autoboot']
  340 18:48:29.218537  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 18:48:29.219490  Trying 192.168.1.205...
  342 18:48:29.219802  Connected to ts5.
  343 18:48:29.220099  Escape character is '^]'.
  344 18:48:29.220386  
  345 18:48:29.220672  ser2net port telnet,2000 device serialdev,/dev/ttyUSB-lf-bbb-01,115200n81,local [] (Debian GNU/Linux)
  346 18:48:29.220965  
  347 18:48:29.793646  
  348 18:48:29.801876  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 18:48:29.802276  Trying to boot from MMC2
  350 18:48:30.314665  
  351 18:48:30.315066  
  352 18:48:30.319679  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 18:48:30.320075  
  354 18:48:30.320400  CPU  : AM335X-GP rev 2.1
  355 18:48:30.326364  Model: TI AM335x BeagleBone Black
  356 18:48:30.326762  DRAM:  512 MiB
  357 18:48:30.407452  WDT:   Started with servicing (60s timeout)
  358 18:48:30.812229  NAND:  0 MiB
  359 18:48:30.822967  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 18:48:30.856748  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 18:48:30.885904  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 18:48:30.943562  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 18:48:30.944077  start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
  364 18:48:30.944445  Setting prompt string to ['=> ']
  365 18:48:30.944814  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:43)
  366 18:48:30.954548  Hit any key to stop autoboot:  2   0 
  367 18:48:30.955326  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 18:48:30.955705  Sending with 10 millisecond of delay
  370 18:48:32.092025  => setenv autoload no
  371 18:48:32.102639  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 18:48:32.105734  setenv autoload no
  373 18:48:32.106369  Sending with 10 millisecond of delay
  375 18:48:33.905747  => setenv initrd_high 0xffffffff
  376 18:48:33.916387  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:40)
  377 18:48:33.917023  setenv initrd_high 0xffffffff
  378 18:48:33.917590  Sending with 10 millisecond of delay
  380 18:48:35.536056  => setenv fdt_high 0xffffffff
  381 18:48:35.546607  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 18:48:35.547224  setenv fdt_high 0xffffffff
  383 18:48:35.547788  Sending with 10 millisecond of delay
  385 18:48:35.839690  => dhcp
  386 18:48:35.850251  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 18:48:35.851533  dhcp
  388 18:48:35.851927  link up on port 0, speed 100, full duplex
  389 18:48:35.852238  BOOTP broadcast 1
  390 18:48:35.896743  DHCP client bound to address 172.16.3.203 (40 ms)
  391 18:48:35.897361  Sending with 10 millisecond of delay
  393 18:48:37.515718  => setenv serverip 172.16.3.3
  394 18:48:37.526321  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 18:48:37.526955  setenv serverip 172.16.3.3
  396 18:48:37.527523  Sending with 10 millisecond of delay
  398 18:48:41.075573  => tftp 0x82000000 1206272/tftp-deploy-q3rg7qgn/kernel/zImage
  399 18:48:41.086164  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 18:48:41.086812  tftp 0x82000000 1206272/tftp-deploy-q3rg7qgn/kernel/zImage
  401 18:48:41.087140  link up on port 0, speed 100, full duplex
  402 18:48:41.091597  Using ethernet@4a100000 device
  403 18:48:41.097800  TFTP from server 172.16.3.3; our IP address is 172.16.3.203
  404 18:48:41.104524  Filename '1206272/tftp-deploy-q3rg7qgn/kernel/zImage'.
  405 18:48:41.104803  Load address: 0x82000000
  406 18:48:43.498482  Loading: *##################################################  10.9 MiB
  407 18:48:43.499013  	 4.6 MiB/s
  408 18:48:43.499323  done
  409 18:48:43.503956  Bytes transferred = 11444736 (aea200 hex)
  410 18:48:43.504609  Sending with 10 millisecond of delay
  412 18:48:48.016940  => tftp 0x83000000 1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot
  413 18:48:48.027581  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 18:48:48.028059  tftp 0x83000000 1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot
  415 18:48:48.028388  link up on port 0, speed 100, full duplex
  416 18:48:48.033567  Using ethernet@4a100000 device
  417 18:48:48.039556  TFTP from server 172.16.3.3; our IP address is 172.16.3.203
  418 18:48:48.047507  Filename '1206272/tftp-deploy-q3rg7qgn/ramdisk/ramdisk.cpio.gz.uboot'.
  419 18:48:48.047708  Load address: 0x83000000
  420 18:48:51.122871  Loading: *##################################################  14.1 MiB
  421 18:48:51.123395  	 4.6 MiB/s
  422 18:48:51.123705  done
  423 18:48:51.127129  Bytes transferred = 14794065 (e1bd51 hex)
  424 18:48:51.127781  Sending with 10 millisecond of delay
  426 18:48:52.985966  => setenv initrd_size ${filesize}
  427 18:48:52.996606  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:20)
  428 18:48:52.997243  setenv initrd_size ${filesize}
  429 18:48:52.997829  Sending with 10 millisecond of delay
  431 18:48:57.206499  => tftp 0x88000000 1206272/tftp-deploy-q3rg7qgn/dtb/am335x-boneblack.dtb
  432 18:48:57.217147  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:16)
  433 18:48:57.218117  tftp 0x88000000 1206272/tftp-deploy-q3rg7qgn/dtb/am335x-boneblack.dtb
  434 18:48:57.218495  link up on port 0, speed 100, full duplex
  435 18:48:57.223133  Using ethernet@4a100000 device
  436 18:48:57.228304  TFTP from server 172.16.3.3; our IP address is 172.16.3.203
  437 18:48:57.230497  Filename '1206272/tftp-deploy-q3rg7qgn/dtb/am335x-boneblack.dtb'.
  438 18:48:57.244074  Load address: 0x88000000
  439 18:48:57.257530  Loading: *##################################################  68.9 KiB
  440 18:48:57.257914  	 3.7 MiB/s
  441 18:48:57.258249  done
  442 18:48:57.261900  Bytes transferred = 70568 (113a8 hex)
  443 18:48:57.262536  Sending with 10 millisecond of delay
  445 18:49:10.624995  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 18:49:10.635656  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:03)
  447 18:49:10.636323  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 18:49:10.636910  Sending with 10 millisecond of delay
  450 18:49:12.974787  => bootz 0x82000000 0x83000000 0x88000000
  451 18:49:12.985214  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 18:49:12.985404  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:00)
  453 18:49:12.985757  bootz 0x82000000 0x83000000 0x88000000
  454 18:49:12.985899  Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
  455 18:49:12.988556  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 18:49:12.994708     Image Name:   
  457 18:49:12.994864     Created:      2024-10-14  18:48:13 UTC
  458 18:49:12.998534     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 18:49:13.003538     Data Size:    14794001 Bytes = 14.1 MiB
  460 18:49:13.011669     Load Address: 00000000
  461 18:49:13.011824     Entry Point:  00000000
  462 18:49:13.179681     Verifying Checksum ... OK
  463 18:49:13.179850  ## Flattened Device Tree blob at 88000000
  464 18:49:13.187039     Booting using the fdt blob at 0x88000000
  465 18:49:13.191340     Using Device Tree in place at 88000000, end 880143a7
  466 18:49:13.204535  
  467 18:49:13.204690  Starting kernel ...
  468 18:49:13.204815  
  469 18:49:13.205205  end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
  470 18:49:13.205381  start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
  471 18:49:13.205525  Setting prompt string to ['Linux version [0-9]']
  472 18:49:13.205664  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 18:49:13.205802  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 18:49:14.046037  [    0.000000] Booting Linux on physical CPU 0x0
  475 18:49:14.052346  start: 2.4.4.1 login-action (timeout 00:03:59) [common]
  476 18:49:14.052529  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 18:49:14.052685  Setting prompt string to []
  478 18:49:14.052834  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 18:49:14.052979  Using line separator: #'\n'#
  480 18:49:14.053101  No login prompt set.
  481 18:49:14.053227  Parsing kernel messages
  482 18:49:14.053341  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 18:49:14.053555  [login-action] Waiting for messages, (timeout 00:03:59)
  484 18:49:14.066679  [    0.000000] Linux version 6.12.0-rc3 (KernelCI@build-j342167-arm-gcc-12-multi-v7-defconfig-c64d6) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Oct 14 17:55:33 UTC 2024
  485 18:49:14.079154  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 18:49:14.082661  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 18:49:14.087776  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 18:49:14.093882  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 18:49:14.100027  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 18:49:14.110149  [    0.000000] Memory policy: Data cache writeback
  491 18:49:14.110302  [    0.000000] efi: UEFI not found.
  492 18:49:14.118417  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 18:49:14.124458  [    0.000000] Zone ranges:
  494 18:49:14.129447  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 18:49:14.129612  [    0.000000]   Normal   empty
  496 18:49:14.135792  [    0.000000]   HighMem  empty
  497 18:49:14.135952  [    0.000000] Movable zone start for each node
  498 18:49:14.141950  [    0.000000] Early memory node ranges
  499 18:49:14.150584  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 18:49:14.156116  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 18:49:14.181867  [    0.000000] CPU: All CPU(s) started in SVC mode.
  502 18:49:14.190039  [    0.000000] AM335X ES2.1 (sgx neon)
  503 18:49:14.198818  [    0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
  504 18:49:14.219967  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  505 18:49:14.226000  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  506 18:49:14.235694  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  507 18:49:14.240727  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  508 18:49:14.247280  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  509 18:49:14.278841  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  510 18:49:14.285077  <6>[    0.000000] trace event string verifier disabled
  511 18:49:14.285374  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  512 18:49:14.292510  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  513 18:49:14.298566  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  514 18:49:14.308179  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  515 18:49:14.315028  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  516 18:49:14.330033  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  517 18:49:14.346808  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  518 18:49:14.353577  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  519 18:49:14.445370  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  520 18:49:14.453834  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  521 18:49:14.466008  <6>[    0.008341] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  522 18:49:14.474306  <6>[    0.019150] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  523 18:49:14.483851  <6>[    0.033941] Console: colour dummy device 80x30
  524 18:49:14.490248  Matched prompt #6: WARNING:
  525 18:49:14.490461  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  526 18:49:14.496145  <3>[    0.038837] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  527 18:49:14.498289  <3>[    0.045910] This ensures that you still see kernel messages. Please
  528 18:49:14.504140  <3>[    0.052640] update your kernel commandline.
  529 18:49:14.545198  <6>[    0.057249] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  530 18:49:14.550131  <6>[    0.096154] CPU: Testing write buffer coherency: ok
  531 18:49:14.553850  <6>[    0.101519] CPU0: Spectre v2: using BPIALL workaround
  532 18:49:14.558717  <6>[    0.106984] pid_max: default: 32768 minimum: 301
  533 18:49:14.565122  <6>[    0.112178] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  534 18:49:14.574868  <6>[    0.120003] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  535 18:49:14.581390  <6>[    0.129361] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  536 18:49:14.595876  <6>[    0.136347] Setting up static identity map for 0x80300000 - 0x803000ac
  537 18:49:14.596066  <6>[    0.146008] rcu: Hierarchical SRCU implementation.
  538 18:49:14.603983  <6>[    0.151291] rcu: 	Max phase no-delay instances is 1000.
  539 18:49:14.612895  <6>[    0.162388] EFI services will not be available.
  540 18:49:14.618842  <6>[    0.167662] smp: Bringing up secondary CPUs ...
  541 18:49:14.626014  <6>[    0.172706] smp: Brought up 1 node, 1 CPU
  542 18:49:14.632295  <6>[    0.177105] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  543 18:49:14.637361  <6>[    0.183871] CPU: All CPU(s) started in SVC mode.
  544 18:49:14.649645  <6>[    0.189048] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
  545 18:49:14.656445  <6>[    0.205323] devtmpfs: initialized
  546 18:49:14.678356  <6>[    0.222856] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  547 18:49:14.686991  <6>[    0.231432] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  548 18:49:14.696351  <6>[    0.241882] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  549 18:49:14.706863  <6>[    0.254143] pinctrl core: initialized pinctrl subsystem
  550 18:49:14.715449  <6>[    0.264793] DMI not present or invalid.
  551 18:49:14.725139  <6>[    0.270644] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  552 18:49:14.734170  <6>[    0.279599] DMA: preallocated 256 KiB pool for atomic coherent allocations
  553 18:49:14.748679  <6>[    0.291042] thermal_sys: Registered thermal governor 'step_wise'
  554 18:49:14.749064  <6>[    0.291206] cpuidle: using governor menu
  555 18:49:14.777427  <6>[    0.326611] No ATAGs?
  556 18:49:14.782870  <6>[    0.329254] hw-breakpoint: debug architecture 0x4 unsupported.
  557 18:49:14.793288  <6>[    0.341252] Serial: AMBA PL011 UART driver
  558 18:49:14.826080  <6>[    0.375393] iommu: Default domain type: Translated
  559 18:49:14.835132  <6>[    0.380743] iommu: DMA domain TLB invalidation policy: strict mode
  560 18:49:14.861898  <5>[    0.410737] SCSI subsystem initialized
  561 18:49:14.866983  <6>[    0.415623] usbcore: registered new interface driver usbfs
  562 18:49:14.873088  <6>[    0.421678] usbcore: registered new interface driver hub
  563 18:49:14.881716  <6>[    0.427463] usbcore: registered new device driver usb
  564 18:49:14.887966  <6>[    0.433965] pps_core: LinuxPPS API ver. 1 registered
  565 18:49:14.894076  <6>[    0.439355] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  566 18:49:14.903265  <6>[    0.449089] PTP clock support registered
  567 18:49:14.903466  <6>[    0.453554] EDAC MC: Ver: 3.0.0
  568 18:49:14.952938  <6>[    0.500457] scmi_core: SCMI protocol bus registered
  569 18:49:14.968280  <6>[    0.517783] vgaarb: loaded
  570 18:49:14.980088  <6>[    0.530775] clocksource: Switched to clocksource dmtimer
  571 18:49:15.016265  <6>[    0.566890] NET: Registered PF_INET protocol family
  572 18:49:15.029799  <6>[    0.572579] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  573 18:49:15.036020  <6>[    0.581371] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  574 18:49:15.047283  <6>[    0.590302] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  575 18:49:15.052214  <6>[    0.598562] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  576 18:49:15.063399  <6>[    0.606848] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  577 18:49:15.069515  <6>[    0.614575] TCP: Hash tables configured (established 4096 bind 4096)
  578 18:49:15.077993  <6>[    0.621481] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  579 18:49:15.084279  <6>[    0.628519] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  580 18:49:15.088531  <6>[    0.636123] NET: Registered PF_UNIX/PF_LOCAL protocol family
  581 18:49:15.165456  <6>[    0.710575] RPC: Registered named UNIX socket transport module.
  582 18:49:15.165889  <6>[    0.717011] RPC: Registered udp transport module.
  583 18:49:15.171531  <6>[    0.722141] RPC: Registered tcp transport module.
  584 18:49:15.180288  <6>[    0.727245] RPC: Registered tcp-with-tls transport module.
  585 18:49:15.186517  <6>[    0.733168] RPC: Registered tcp NFSv4.1 backchannel transport module.
  586 18:49:15.193869  <6>[    0.740073] PCI: CLS 0 bytes, default 64
  587 18:49:15.196172  <5>[    0.745876] Initialise system trusted keyrings
  588 18:49:15.219181  <6>[    0.765946] Trying to unpack rootfs image as initramfs...
  589 18:49:15.297954  <6>[    0.841939] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  590 18:49:15.302162  <6>[    0.849435] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  591 18:49:15.342361  <5>[    0.892431] NFS: Registering the id_resolver key type
  592 18:49:15.347117  <5>[    0.898032] Key type id_resolver registered
  593 18:49:15.353345  <5>[    0.902722] Key type id_legacy registered
  594 18:49:15.359459  <6>[    0.907164] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  595 18:49:15.368720  <6>[    0.914366] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  596 18:49:15.438368  <5>[    0.988753] Key type asymmetric registered
  597 18:49:15.444341  <5>[    0.993327] Asymmetric key parser 'x509' registered
  598 18:49:15.452850  <6>[    0.998754] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  599 18:49:15.457971  <6>[    1.006672] io scheduler mq-deadline registered
  600 18:49:15.464303  <6>[    1.011638] io scheduler kyber registered
  601 18:49:15.467536  <6>[    1.016091] io scheduler bfq registered
  602 18:49:15.571673  <6>[    1.117964] ledtrig-cpu: registered to indicate activity on CPUs
  603 18:49:15.851430  <6>[    1.398437] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  604 18:49:15.897028  <6>[    1.446480] msm_serial: driver initialized
  605 18:49:15.903142  <6>[    1.451263] SuperH (H)SCI(F) driver initialized
  606 18:49:15.908147  <6>[    1.456578] STMicroelectronics ASC driver initialized
  607 18:49:15.913660  <6>[    1.462247] STM32 USART driver initialized
  608 18:49:16.015531  <6>[    1.565542] brd: module loaded
  609 18:49:16.058642  <6>[    1.607749] loop: module loaded
  610 18:49:16.102998  <6>[    1.653336] CAN device driver interface
  611 18:49:16.110520  <6>[    1.658365] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  612 18:49:16.116646  <6>[    1.665482] e1000e: Intel(R) PRO/1000 Network Driver
  613 18:49:16.121647  <6>[    1.670870] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  614 18:49:16.127642  <6>[    1.677352] igb: Intel(R) Gigabit Ethernet Network Driver
  615 18:49:16.135614  <6>[    1.683205] igb: Copyright (c) 2007-2014 Intel Corporation.
  616 18:49:16.148178  <6>[    1.692860] pegasus: Pegasus/Pegasus II USB Ethernet driver
  617 18:49:16.153051  <6>[    1.698936] usbcore: registered new interface driver pegasus
  618 18:49:16.159428  <6>[    1.705119] usbcore: registered new interface driver asix
  619 18:49:16.165555  <6>[    1.710973] usbcore: registered new interface driver ax88179_178a
  620 18:49:16.171805  <6>[    1.717577] usbcore: registered new interface driver cdc_ether
  621 18:49:16.175292  <6>[    1.723900] usbcore: registered new interface driver smsc75xx
  622 18:49:16.180561  <6>[    1.730114] usbcore: registered new interface driver smsc95xx
  623 18:49:16.186772  <6>[    1.736351] usbcore: registered new interface driver net1080
  624 18:49:16.196390  <6>[    1.742494] usbcore: registered new interface driver cdc_subset
  625 18:49:16.201409  <6>[    1.748890] usbcore: registered new interface driver zaurus
  626 18:49:16.206985  <6>[    1.754956] usbcore: registered new interface driver cdc_ncm
  627 18:49:16.217662  <6>[    1.764781] usbcore: registered new interface driver usb-storage
  628 18:49:16.519247  <6>[    2.067317] i2c_dev: i2c /dev entries driver
  629 18:49:16.586715  <5>[    2.128576] cpuidle: enable-method property 'ti,am3352' found operations
  630 18:49:16.592773  <6>[    2.138275] sdhci: Secure Digital Host Controller Interface driver
  631 18:49:16.600271  <6>[    2.145056] sdhci: Copyright(c) Pierre Ossman
  632 18:49:16.606210  <6>[    2.151729] Synopsys Designware Multimedia Card Interface Driver
  633 18:49:16.612888  <6>[    2.159786] sdhci-pltfm: SDHCI platform and OF driver helper
  634 18:49:16.730814  <6>[    2.273383] usbcore: registered new interface driver usbhid
  635 18:49:16.731276  <6>[    2.279423] usbhid: USB HID core driver
  636 18:49:16.780413  <6>[    2.328399] NET: Registered PF_INET6 protocol family
  637 18:49:16.828166  <6>[    2.377742] Segment Routing with IPv6
  638 18:49:16.834198  <6>[    2.381972] In-situ OAM (IOAM) with IPv6
  639 18:49:16.839410  <6>[    2.386376] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  640 18:49:16.846699  <6>[    2.393646] NET: Registered PF_PACKET protocol family
  641 18:49:16.852796  <6>[    2.399134] can: controller area network core
  642 18:49:16.859007  <6>[    2.404015] NET: Registered PF_CAN protocol family
  643 18:49:16.859528  <6>[    2.409219] can: raw protocol
  644 18:49:16.862288  <6>[    2.412568] can: broadcast manager protocol
  645 18:49:16.868651  <6>[    2.417148] can: netlink gateway - max_hops=1
  646 18:49:16.874630  <5>[    2.422645] Key type dns_resolver registered
  647 18:49:16.880919  <6>[    2.427638] ThumbEE CPU extension supported.
  648 18:49:16.883162  <5>[    2.432405] Registering SWP/SWPB emulation handler
  649 18:49:16.891385  <3>[    2.438053] omap_voltage_late_init: Voltage driver support not added
  650 18:49:17.084525  <5>[    2.632673] Loading compiled-in X.509 certificates
  651 18:49:17.194198  <6>[    2.730858] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  652 18:49:17.201004  <6>[    2.747524] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  653 18:49:17.226618  <3>[    2.771084] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  654 18:49:17.449527  <3>[    2.994416] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  655 18:49:17.643696  <6>[    3.192306] OMAP GPIO hardware version 0.1
  656 18:49:17.664622  <6>[    3.210800] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  657 18:49:17.747211  <4>[    3.293253] at24 2-0054: supply vcc not found, using dummy regulator
  658 18:49:17.781333  <4>[    3.327757] at24 2-0055: supply vcc not found, using dummy regulator
  659 18:49:17.830996  <4>[    3.376981] at24 2-0056: supply vcc not found, using dummy regulator
  660 18:49:17.869142  <4>[    3.415242] at24 2-0057: supply vcc not found, using dummy regulator
  661 18:49:17.907434  <6>[    3.454808] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  662 18:49:17.985046  <3>[    3.527502] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  663 18:49:18.009361  <6>[    3.548608] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  664 18:49:18.030331  <4>[    3.574724] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  665 18:49:18.038154  <4>[    3.583879] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  666 18:49:18.175766  <6>[    3.722074] omap_rng 48310000.rng: Random Number Generator ver. 20
  667 18:49:18.198807  <5>[    3.748444] random: crng init done
  668 18:49:18.240134  <6>[    3.789442] Freeing initrd memory: 14448K
  669 18:49:18.249375  <6>[    3.794222] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  670 18:49:18.299999  <6>[    3.844093] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  671 18:49:18.306050  <6>[    3.854387] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  672 18:49:18.313381  <6>[    3.861737] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  673 18:49:18.325591  <6>[    3.869179] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  674 18:49:18.334114  <6>[    3.877326] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  675 18:49:18.346395  <6>[    3.888961] cpsw-switch 4a100000.switch: Detected MACID = 34:03:de:5e:2c:05
  676 18:49:18.355635  <5>[    3.897991] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  677 18:49:18.382978  <3>[    3.927602] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  678 18:49:18.388436  <6>[    3.936203] edma 49000000.dma: TI EDMA DMA engine driver
  679 18:49:18.459629  <3>[    4.003205] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  680 18:49:18.474019  <6>[    4.017488] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  681 18:49:18.486315  <3>[    4.034583] l3-aon-clkctrl:0000:0: failed to disable
  682 18:49:18.534819  <6>[    4.079315] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  683 18:49:18.540899  <6>[    4.088820] printk: legacy console [ttyS0] enabled
  684 18:49:18.543179  <6>[    4.088820] printk: legacy console [ttyS0] enabled
  685 18:49:18.554278  <6>[    4.099175] printk: legacy bootconsole [omap8250] disabled
  686 18:49:18.557553  <6>[    4.099175] printk: legacy bootconsole [omap8250] disabled
  687 18:49:18.598329  <4>[    4.142340] tps65217-pmic: Failed to locate of_node [id: -1]
  688 18:49:18.602674  <4>[    4.149751] tps65217-bl: Failed to locate of_node [id: -1]
  689 18:49:18.618472  <6>[    4.169317] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  690 18:49:18.634279  <6>[    4.176220] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  691 18:49:18.646524  <6>[    4.189906] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  692 18:49:18.654575  <6>[    4.201820] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  693 18:49:18.676437  <6>[    4.221300] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  694 18:49:18.682494  <6>[    4.230480] sdhci-omap 48060000.mmc: Got CD GPIO
  695 18:49:18.690515  <4>[    4.235630] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  696 18:49:18.705170  <4>[    4.249030] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  697 18:49:18.711273  <4>[    4.257701] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  698 18:49:18.720502  <4>[    4.266404] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  699 18:49:18.845406  <6>[    4.390528] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  700 18:49:18.890542  <6>[    4.434596] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  701 18:49:18.897862  <6>[    4.443925] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  702 18:49:18.907282  <6>[    4.452861] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  703 18:49:18.971368  <6>[    4.512396] mmc1: new high speed MMC card at address 0001
  704 18:49:18.971766  <6>[    4.520395] mmcblk1: mmc1:0001 M62704 3.56 GiB
  705 18:49:18.980463  <6>[    4.530678]  mmcblk1: p1
  706 18:49:18.989202  <6>[    4.537711] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  707 18:49:19.001372  <6>[    4.544952] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  708 18:49:19.011561  <6>[    4.559973] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  709 18:49:19.026368  <6>[    4.573509] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  710 18:49:21.137348  <6>[    6.682667] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  711 18:49:21.241071  <5>[    6.711638] Sending DHCP requests ., OK
  712 18:49:21.251978  <6>[    6.796070] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.203
  713 18:49:21.252268  <6>[    6.804162] IP-Config: Complete:
  714 18:49:21.266630  <6>[    6.807702]      device=eth0, hwaddr=34:03:de:5e:2c:05, ipaddr=172.16.3.203, mask=255.255.255.0, gw=172.16.3.3
  715 18:49:21.271557  <6>[    6.818123]      host=172.16.3.203, domain=denx.de, nis-domain=(none)
  716 18:49:21.277617  <6>[    6.824939]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  717 18:49:21.283656  <6>[    6.824973]      nameserver0=172.16.3.3
  718 18:49:21.290953  <6>[    6.836279]      ntpserver0=172.16.3.3
  719 18:49:21.291162  <6>[    6.841821] clk: Disabling unused clocks
  720 18:49:21.298917  <6>[    6.846423] PM: genpd: Disabling unused power domains
  721 18:49:21.317929  <6>[    6.865043] Freeing unused kernel image (initmem) memory: 2048K
  722 18:49:21.326042  <6>[    6.874753] Run /init as init process
  723 18:49:21.347630  Loading, please wait...
  724 18:49:21.422319  Starting systemd-udevd version 252.22-1~deb12u1
  725 18:49:24.411122  <4>[    9.953571] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  726 18:49:24.644290  <4>[   10.185498] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  727 18:49:24.787440  <6>[   10.338759] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  728 18:49:24.799086  <6>[   10.344576] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  729 18:49:25.024773  <6>[   10.574381] hub 1-0:1.0: USB hub found
  730 18:49:25.083991  <6>[   10.633367] hub 1-0:1.0: 1 port detected
  731 18:49:25.089471  <6>[   10.639026] tda998x 0-0070: found TDA19988
  732 18:49:28.255642  Begin: Loading essential drivers ... done.
  733 18:49:28.269361  Begin: Running /scripts/init-premount ... done.
  734 18:49:28.281660  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  735 18:49:28.293172  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  736 18:49:28.293561  Device /sys/class/net/eth0 found
  737 18:49:28.293898  done.
  738 18:49:28.351596  Begin: Waiting up to 180 secs for any network device to become available ... done.
  739 18:49:28.415000  IP-Config: eth0 hardware address 34:03:de:5e:2c:05 mtu 1500 DHCP
  740 18:49:28.451110  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  741 18:49:28.462119   address: 172.16.3.203     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  742 18:49:28.464430   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  743 18:49:28.475611   domain : denx.de                                                         
  744 18:49:28.475996   rootserver: 172.16.3.33 rootpath: 
  745 18:49:28.481230   filename  : this-host-is-not-configured.kpxe
  746 18:49:28.540582  done.
  747 18:49:28.549310  Begin: Running /scripts/nfs-bottom ... done.
  748 18:49:28.614068  Begin: Running /scripts/init-bottom ... done.
  749 18:49:29.982939  <30>[   15.529284] systemd[1]: System time before build time, advancing clock.
  750 18:49:30.165090  <30>[   15.686321] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  751 18:49:30.174343  <30>[   15.723546] systemd[1]: Detected architecture arm.
  752 18:49:30.188960  
  753 18:49:30.189353  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  754 18:49:30.189669  
  755 18:49:30.214272  <30>[   15.761539] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  756 18:49:32.605237  <30>[   18.151501] systemd[1]: Queued start job for default target graphical.target.
  757 18:49:32.624083  <30>[   18.168568] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  758 18:49:32.632139  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  759 18:49:32.660620  <30>[   18.204620] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  760 18:49:32.668590  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  761 18:49:32.690604  <30>[   18.235004] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  762 18:49:32.698064  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  763 18:49:32.718813  <30>[   18.263578] systemd[1]: Created slice user.slice - User and Session Slice.
  764 18:49:32.725568  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  765 18:49:32.755172  <30>[   18.292998] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  766 18:49:32.760639  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  767 18:49:32.789089  <30>[   18.332711] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  768 18:49:32.800724  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  769 18:49:32.833135  <30>[   18.362790] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  770 18:49:32.839421  <30>[   18.385099] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  771 18:49:32.846195           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  772 18:49:32.867179  <30>[   18.412177] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  773 18:49:32.875281  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  774 18:49:32.897299  <30>[   18.442527] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  775 18:49:32.905646  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  776 18:49:32.927507  <30>[   18.472608] systemd[1]: Reached target paths.target - Path Units.
  777 18:49:32.933167  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  778 18:49:32.957291  <30>[   18.502280] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  779 18:49:32.965304  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  780 18:49:32.987345  <30>[   18.532199] systemd[1]: Reached target slices.target - Slice Units.
  781 18:49:32.992913  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  782 18:49:33.018283  <30>[   18.562352] systemd[1]: Reached target swap.target - Swaps.
  783 18:49:33.021530  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  784 18:49:33.047667  <30>[   18.592349] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  785 18:49:33.056125  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  786 18:49:33.078165  <30>[   18.623162] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  787 18:49:33.086520  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  788 18:49:33.171969  <30>[   18.711375] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  789 18:49:33.184513  <30>[   18.729098] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  790 18:49:33.192903  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  791 18:49:33.219300  <30>[   18.765992] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  792 18:49:33.232244  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  793 18:49:33.261052  <30>[   18.804538] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  794 18:49:33.268387  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  795 18:49:33.293548  <30>[   18.837053] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  796 18:49:33.299555  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  797 18:49:33.331164  <30>[   18.875109] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  798 18:49:33.338375  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  799 18:49:33.364273  <30>[   18.903226] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  800 18:49:33.382078  <30>[   18.919704] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  801 18:49:33.427421  <30>[   18.972150] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  802 18:49:33.434272           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  803 18:49:33.475002  <30>[   19.019675] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  804 18:49:33.495187           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  805 18:49:33.552660  <30>[   19.096853] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  806 18:49:33.572877           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  807 18:49:33.628197  <30>[   19.172863] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  808 18:49:33.649396           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  809 18:49:33.711210  <30>[   19.255618] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  810 18:49:33.724195           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  811 18:49:33.760322  <30>[   19.306632] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  812 18:49:33.786094           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  813 18:49:33.838188  <30>[   19.382761] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  814 18:49:33.860451           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  815 18:49:33.927217  <30>[   19.472950] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  816 18:49:33.943162           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  817 18:49:34.009858  <30>[   19.555434] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  818 18:49:34.023689           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  819 18:49:34.045859  <28>[   19.585856] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  820 18:49:34.061999  <28>[   19.607012] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  821 18:49:34.107616  <30>[   19.653593] systemd[1]: Starting systemd-journald.service - Journal Service...
  822 18:49:34.125696           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  823 18:49:34.197922  <30>[   19.743138] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  824 18:49:34.221144           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  825 18:49:34.268483  <30>[   19.814647] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  826 18:49:34.325420           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  827 18:49:34.398654  <30>[   19.943110] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  828 18:49:34.447326           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  829 18:49:34.495155  <30>[   20.039206] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  830 18:49:34.548216           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  831 18:49:34.585537  <30>[   20.131257] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  832 18:49:34.646038  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  833 18:49:34.670122  <30>[   20.213959] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  834 18:49:34.708048  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  835 18:49:34.730530  <30>[   20.274831] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  836 18:49:34.751025  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  837 18:49:34.883188  <30>[   20.428953] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  838 18:49:34.918364  <30>[   20.463391] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  839 18:49:34.947122  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  840 18:49:34.967379  <30>[   20.514479] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  841 18:49:35.006993  <30>[   20.552140] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  842 18:49:35.015380  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  843 18:49:35.038239  <30>[   20.583334] systemd[1]: Started systemd-journald.service - Journal Service.
  844 18:49:35.046220  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  845 18:49:35.078362  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  846 18:49:35.109220  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  847 18:49:35.132715  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  848 18:49:35.168870  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  849 18:49:35.197584  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  850 18:49:35.220044  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  851 18:49:35.240455  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  852 18:49:35.277834  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  853 18:49:35.340155           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  854 18:49:35.400354           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  855 18:49:35.458386           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  856 18:49:35.536783           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  857 18:49:35.599146           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  858 18:49:35.739930  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  859 18:49:35.808936  <46>[   21.353873] systemd-journald[162]: Received client request to flush runtime journal.
  860 18:49:35.969524  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  861 18:49:36.023704  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  862 18:49:36.058146  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  863 18:49:36.110081           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  864 18:49:37.089619  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  865 18:49:37.098765  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  866 18:49:37.112690  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  867 18:49:37.377889           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  868 18:49:37.890918  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  869 18:49:37.939908           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  870 18:49:38.413923  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  871 18:49:38.488120           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  872 18:49:39.578528  <5>[   25.124478] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  873 18:49:40.383235  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  874 18:49:41.195910  <5>[   26.744225] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  875 18:49:41.254866  <5>[   26.800047] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  876 18:49:41.260905  <4>[   26.809431] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  877 18:49:41.270115  <6>[   26.818566] cfg80211: failed to load regulatory.db
  878 18:49:41.404393  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  879 18:49:42.412502  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  880 18:49:42.553325  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  881 18:49:50.796487  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  882 18:49:50.817864  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  883 18:49:50.839513  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  884 18:49:50.896858           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  885 18:49:50.943352           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  886 18:49:50.998289           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  887 18:49:51.054284           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  888 18:49:51.281653           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  889 18:49:51.355746           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  890 18:49:51.411080  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  891 18:49:51.450555  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  892 18:49:51.469973  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  893 18:49:51.506108  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  894 18:49:51.656428  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  895 18:49:52.114526  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  896 18:49:52.137884  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  897 18:49:52.159294  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  898 18:49:52.177276  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  899 18:49:52.296910  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  900 18:49:52.429167  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  901 18:49:52.449845  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  902 18:49:52.536862  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  903 18:49:52.623816  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  904 18:49:52.647025  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  905 18:49:52.673791  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  906 18:49:52.689903  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  907 18:49:52.700609  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  908 18:49:52.769248           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  909 18:49:52.810327           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  910 18:49:53.004813           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  911 18:49:53.197151           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  912 18:49:53.231170           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  913 18:49:53.258724  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  914 18:49:53.336000  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  915 18:49:53.359701  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  916 18:49:53.379983  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  917 18:49:53.446593  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  918 18:49:53.486068  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  919 18:49:53.506189  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  920 18:49:53.698291           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  921 18:49:53.948845  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  922 18:49:54.366076  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  923 18:49:54.453069  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  924 18:49:54.519779  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  925 18:49:54.548412  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  926 18:49:54.631977           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  927 18:49:54.836363  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  928 18:49:55.033639  
  929 18:49:55.037889  Debian GNU/Linux 12 debiadebian-bookworm-armhf login: root (automatic login)
  930 18:49:55.038286  
  931 18:49:55.399189  Linux debian-bookworm-armhf 6.12.0-rc3 #1 SMP Mon Oct 14 17:55:33 UTC 2024 armv7l
  932 18:49:55.399460  
  933 18:49:55.405401  The programs included with the Debian GNU/Linux system are free software;
  934 18:49:55.408862  the exact distribution terms for each program are described in the
  935 18:49:55.413872  individual files in /usr/share/doc/*/copyright.
  936 18:49:55.414025  
  937 18:49:55.420150  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  938 18:49:55.424512  permitted by applicable law.
  939 18:50:00.146871  Unable to match end of the kernel message
  941 18:50:00.147346  Setting prompt string to ['/ #']
  942 18:50:00.147528  end: 2.4.4.1 login-action (duration 00:00:46) [common]
  944 18:50:00.147910  end: 2.4.4 auto-login-action (duration 00:00:47) [common]
  945 18:50:00.148085  start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
  946 18:50:00.148231  Setting prompt string to ['/ #']
  947 18:50:00.148350  Forcing a shell prompt, looking for ['/ #']
  949 18:50:00.198670  / # 
  950 18:50:00.198926  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  951 18:50:00.199083  Waiting using forced prompt support (timeout 00:02:30)
  952 18:50:00.207824  
  953 18:50:00.214732  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  954 18:50:00.214929  start: 2.4.6 export-device-env (timeout 00:03:13) [common]
  955 18:50:00.215082  Sending with 10 millisecond of delay
  957 18:50:05.258158  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo'
  958 18:50:05.268550  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1206272/extract-nfsrootfs-miinjixo'
  959 18:50:05.272366  Sending with 10 millisecond of delay
  961 18:50:07.307759  / # export NFS_SERVER_IP='172.16.3.3'
  962 18:50:07.318141  export NFS_SERVER_IP='172.16.3.3'
  963 18:50:07.321360  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  964 18:50:07.321560  end: 2.4 uboot-commands (duration 00:01:54) [common]
  965 18:50:07.321747  end: 2 uboot-action (duration 00:01:54) [common]
  966 18:50:07.321936  start: 3 lava-test-retry (timeout 00:06:56) [common]
  967 18:50:07.322113  start: 3.1 lava-test-shell (timeout 00:06:56) [common]
  968 18:50:07.322255  Using namespace: common
  970 18:50:07.422856  / # #
  971 18:50:07.423377  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  972 18:50:07.430417  #
  973 18:50:07.436274  Using /lava-1206272
  975 18:50:07.537139  / # export SHELL=/bin/bash
  976 18:50:07.544410  export SHELL=/bin/bash
  978 18:50:07.650599  / # . /lava-1206272/environment
  979 18:50:07.657417  . /lava-1206272/environment
  981 18:50:07.771509  / # /lava-1206272/bin/lava-test-runner /lava-1206272/0
  982 18:50:07.772039  Test shell timeout: 10s (minimum of the action and connection timeout)
  983 18:50:07.779266  /lava-1206272/bin/lava-test-runner /lava-1206272/0
  984 18:50:08.359708  + export TESTRUN_ID=0_timesync-off
  985 18:50:08.367628  + TESTRUN_ID=0_timesync-off
  986 18:50:08.368016  + cd /lava-1206272/0/tests/0_timesync-off
  987 18:50:08.368357  ++ cat uuid
  988 18:50:08.384603  + UUID=1206272_1.6.2.4.1
  989 18:50:08.385017  + set +x
  990 18:50:08.390733  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1206272_1.6.2.4.1>
  991 18:50:08.391388  Received signal: <STARTRUN> 0_timesync-off 1206272_1.6.2.4.1
  992 18:50:08.391736  Starting test lava.0_timesync-off (1206272_1.6.2.4.1)
  993 18:50:08.392155  Skipping test definition patterns.
  994 18:50:08.393936  + systemctl stop systemd-timesyncd
  995 18:50:08.681720  + set +x
  996 18:50:08.682372  Received signal: <ENDRUN> 0_timesync-off 1206272_1.6.2.4.1
  997 18:50:08.682755  Ending use of test pattern.
  998 18:50:08.683064  Ending test lava.0_timesync-off (1206272_1.6.2.4.1), duration 0.29
 1000 18:50:08.684868  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1206272_1.6.2.4.1>
 1001 18:50:09.002528  + export TESTRUN_ID=1_kselftest-dt
 1002 18:50:09.010498  + TESTRUN_ID=1_kselftest-dt
 1003 18:50:09.010812  + cd /lava-1206272/0/tests/1_kselftest-dt
 1004 18:50:09.010943  ++ cat uuid
 1005 18:50:09.032617  + UUID=1206272_1.6.2.4.5
 1006 18:50:09.033007  + set +x
 1007 18:50:09.038562  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1206272_1.6.2.4.5>
 1008 18:50:09.038950  + cd ./automated/linux/kselftest/
 1009 18:50:09.039509  Received signal: <STARTRUN> 1_kselftest-dt 1206272_1.6.2.4.5
 1010 18:50:09.039828  Starting test lava.1_kselftest-dt (1206272_1.6.2.4.5)
 1011 18:50:09.040194  Skipping test definition patterns.
 1012 18:50:09.067541  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1013 18:50:09.214751  INFO: install_deps skipped
 1014 18:50:09.917154  --2024-01-26 21:49:15--  http://storage.kernelci.org/mainline/master/v6.12-rc3-7-g6485cf5ea253d/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
 1015 18:50:09.960632  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1016 18:50:10.121072  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1017 18:50:10.278403  HTTP request sent, awaiting response... 200 OK
 1018 18:50:10.278798  Length: 4112600 (3.9M) [application/octet-stream]
 1019 18:50:10.284570  Saving to: 'kselftest_armhf.tar.gz'
 1020 18:50:10.284948  
 1021 18:50:12.701541  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  47.54K   154KB/s               kselftest_armhf.tar   5%[>                   ] 216.29K   348KB/s               kselftest_armhf.tar  15%[==>                 ] 633.51K   665KB/s               kselftest_armhf.tar  33%[=====>              ]   1.31M  1.11MB/s               kselftest_armhf.tar  43%[=======>            ]   1.70M  1.21MB/s               kselftest_armhf.tar  55%[==========>         ]   2.16M  1.35MB/s               kselftest_armhf.tar  67%[============>       ]   2.63M  1.46MB/s               kselftest_armhf.tar  76%[==============>     ]   3.00M  1.48MB/s               kselftest_armhf.tar  89%[================>   ]   3.50M  1.57MB/s               kselftest_armhf.tar 100%[===================>]   3.92M  1.62MB/s    in 2.4s    
 1022 18:50:12.702059  
 1023 18:50:13.465840  2024-01-26 21:49:18 (1.62 MB/s) - 'kselftest_armhf.tar.gz' saved [4112600/4112600]
 1024 18:50:13.466302  
 1025 18:50:13.749405  tar: ./proc/fd-003-kthread: time stamp 2024-10-14 18:07:00 is 22623460.233912787 s in the future
 1026 18:50:13.873692  tar: ./proc/config: time stamp 2024-10-02 20:28:12 is 21595132.108600245 s in the future
 1027 18:50:13.998682  tar: ./proc/proc-tid0: time stamp 2024-10-14 18:07:01 is 22623460.983385245 s in the future
 1028 18:50:14.107806  tar: ./proc/proc-loadavg-001: time stamp 2024-10-14 18:07:00 is 22623459.875069954 s in the future
 1029 18:50:14.232687  tar: ./proc/proc-self-syscall: time stamp 2024-10-14 18:07:01 is 22623460.750195829 s in the future
 1030 18:50:14.340686  tar: ./proc/setns-dcache: time stamp 2024-10-14 18:07:02 is 22623461.640965079 s in the future
 1031 18:50:14.581584  tar: ./proc/setns-sysvipc: time stamp 2024-10-14 18:07:02 is 22623461.399920454 s in the future
 1032 18:50:14.784690  tar: ./proc/proc-uptime-001: time stamp 2024-10-14 18:07:01 is 22623460.198856578 s in the future
 1033 18:50:14.973925  tar: ./proc/fd-001-lookup: time stamp 2024-10-14 18:07:00 is 22623459.008010912 s in the future
 1034 18:50:15.108602  tar: ./proc/proc-uptime-002: time stamp 2024-10-14 18:07:01 is 22623459.87443437 s in the future
 1035 18:50:15.226499  tar: ./proc/fd-002-posix-eq: time stamp 2024-10-14 18:07:00 is 22623458.75666112 s in the future
 1036 18:50:15.339744  tar: ./proc/thread-self: time stamp 2024-10-14 18:07:02 is 22623460.642264828 s in the future
 1037 18:50:15.482336  tar: ./proc/read: time stamp 2024-10-14 18:07:01 is 22623459.499232578 s in the future
 1038 18:50:15.617706  tar: ./proc/self: time stamp 2024-10-14 18:07:01 is 22623459.364689245 s in the future
 1039 18:50:15.742680  tar: ./proc/proc-pid-vm: time stamp 2024-10-14 18:07:00 is 22623458.239426953 s in the future
 1040 18:50:15.884616  tar: ./proc/proc-multiple-procfs: time stamp 2024-10-14 18:07:02 is 22623460.098744953 s in the future
 1041 18:50:16.010674  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-10-14 18:07:01 is 22623458.972461662 s in the future
 1042 18:50:16.641985  tar: ./proc/proc-subset-pid: time stamp 2024-10-14 18:07:01 is 22623458.340893828 s in the future
 1043 18:50:16.759695  tar: ./proc/proc-self-map-files-001: time stamp 2024-10-14 18:07:00 is 22623457.22234537 s in the future
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 1345 18:51:02.115104  tar: ./net/tcp_ao/self-connect_ipv4: time stamp 2024-10-14 18:06:51 is 22623402.865917281 s in the future
 1346 18:51:02.327589  tar: ./net/tcp_ao/connect_ipv6: time stamp 2024-10-14 18:06:53 is 22623404.653186948 s in the future
 1347 18:51:02.541311  tar: ./net/tcp_ao/key-management_ipv6: time stamp 2024-10-14 18:06:55 is 22623406.440313364 s in the future
 1348 18:51:02.823688  tar: ./net/tcp_ao/restore_ipv4: time stamp 2024-10-14 18:06:50 is 22623401.157233656 s in the future
 1349 18:51:03.017338  tar: ./net/tcp_ao/unsigned-md5_ipv6: time stamp 2024-10-14 18:06:58 is 22623408.963872156 s in the future
 1350 18:51:03.216287  tar: ./net/tcp_ao/restore_ipv6: time stamp 2024-10-14 18:06:55 is 22623405.763877281 s in the future
 1351 18:51:03.433251  tar: ./net/tcp_ao/icmps-accept_ipv6: time stamp 2024-10-14 18:06:54 is 22623404.548501698 s in the future
 1352 18:51:03.625013  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-10-14 18:06:51 is 22623401.354994864 s in the future
 1353 18:51:03.748644  tar: ./net/tcp_ao/config: time stamp 2024-10-02 20:28:12 is 21595082.231143823 s in the future
 1354 18:51:03.949485  tar: ./net/tcp_ao/setsockopt-closed_ipv6: time stamp 2024-10-14 18:06:57 is 22623407.031428448 s in the future
 1355 18:51:04.159143  tar: ./net/tcp_ao/unsigned-md5_ipv4: time stamp 2024-10-14 18:06:52 is 22623401.821606239 s in the future
 1356 18:51:04.350771  tar: ./net/tcp_ao/icmps-discard_ipv4: time stamp 2024-10-14 18:06:49 is 22623398.629812073 s in the future
 1357 18:51:04.549704  tar: ./net/tcp_ao/connect-deny_ipv4: time stamp 2024-10-14 18:06:48 is 22623397.430728531 s in the future
 1358 18:51:04.760328  tar: ./net/tcp_ao/setsockopt-closed_ipv4: time stamp 2024-10-14 18:06:52 is 22623401.220771989 s in the future
 1359 18:51:04.950546  tar: ./net/tcp_ao/rst_ipv6: time stamp 2024-10-14 18:06:56 is 22623405.029067531 s in the future
 1360 18:51:05.159019  tar: ./net/tcp_ao/seq-ext_ipv6: time stamp 2024-10-14 18:06:56 is 22623404.821615197 s in the future
 1361 18:51:05.284826  tar: ./net/tcp_ao/settings: time stamp 2024-10-02 20:28:12 is 21595080.695197406 s in the future
 1362 18:51:05.510269  tar: ./net/tcp_ao/icmps-discard_ipv6: time stamp 2024-10-14 18:06:54 is 22623402.471249947 s in the future
 1363 18:51:05.701918  tar: ./net/tcp_ao/connect-deny_ipv6: time stamp 2024-10-14 18:06:53 is 22623401.279742656 s in the future
 1364 18:51:06.902715  tar: ./net/tcp_ao/key-management_ipv4: time stamp 2024-10-14 18:06:49 is 22623396.078777989 s in the future
 1365 18:51:07.086787  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-10-14 18:06:48 is 22623394.893969322 s in the future
 1366 18:51:07.265651  tar: ./net/tcp_ao/bench-lookups_ipv6: time stamp 2024-10-14 18:06:52 is 22623398.715642322 s in the future
 1367 18:51:07.484761  tar: ./net/tcp_ao/self-connect_ipv6: time stamp 2024-10-14 18:06:56 is 22623402.496180322 s in the future
 1368 18:51:07.678417  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-10-14 18:06:50 is 22623396.301734947 s in the future
 1369 18:51:07.733634  tar: ./net/tcp_ao: time stamp 2024-10-14 18:07:45 is 22623451.245977197 s in the future
 1370 18:51:07.911703  tar: ./net/forwarding/q_in_vni.sh: time stamp 2024-10-02 20:28:12 is 21595078.06934678 s in the future
 1371 18:51:08.046325  tar: ./net/forwarding/router_mpath_nh_res.sh: time stamp 2024-10-02 20:28:12 is 21595077.935870572 s in the future
 1372 18:51:08.171604  tar: ./net/forwarding/vxlan_bridge_1q.sh: time stamp 2024-10-02 20:28:12 is 21595077.809648239 s in the future
 1373 18:51:08.309214  tar: ./net/forwarding/sch_tbf_etsprio.sh: time stamp 2024-10-02 20:28:12 is 21595077.671535489 s in the future
 1374 18:51:08.433202  tar: ./net/forwarding/router_bridge.sh: time stamp 2024-10-02 20:28:12 is 21595077.547881572 s in the future
 1375 18:51:08.572066  tar: ./net/forwarding/vxlan_symmetric.sh: time stamp 2024-10-02 20:28:12 is 21595077.409244989 s in the future
 1376 18:51:08.702393  tar: ./net/forwarding/ip6gre_hier.sh: time stamp 2024-10-02 20:28:12 is 21595077.279333155 s in the future
 1377 18:51:08.825304  tar: ./net/forwarding/sch_tbf_prio.sh: time stamp 2024-10-02 20:28:12 is 21595077.155863197 s in the future
 1378 18:51:08.958723  tar: ./net/forwarding/tc_actions.sh: time stamp 2024-10-02 20:28:12 is 21595077.022356739 s in the future
 1379 18:51:09.080780  tar: ./net/forwarding/tc_flower_port_range.sh: time stamp 2024-10-02 20:28:12 is 21595076.901210989 s in the future
 1380 18:51:09.211450  tar: ./net/forwarding/vxlan_bridge_1d_port_8472_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595076.770522364 s in the future
 1381 18:51:09.332430  tar: ./net/forwarding/gre_multipath_nh_res.sh: time stamp 2024-10-02 20:28:12 is 21595076.649778614 s in the future
 1382 18:51:09.469302  tar: ./net/forwarding/devlink_lib.sh: time stamp 2024-10-02 20:28:12 is 21595076.512005364 s in the future
 1383 18:51:09.606238  tar: ./net/forwarding/ipip_hier_gre_key.sh: time stamp 2024-10-02 20:28:12 is 21595076.375664905 s in the future
 1384 18:51:09.740016  tar: ./net/forwarding/tc_flower_router.sh: time stamp 2024-10-02 20:28:12 is 21595076.241947947 s in the future
 1385 18:51:09.901002  tar: ./net/forwarding/lib.sh: time stamp 2024-10-02 20:28:12 is 21595076.079599697 s in the future
 1386 18:51:10.046433  tar: ./net/forwarding/mirror_gre_bridge_1q_lag.sh: time stamp 2024-10-02 20:28:12 is 21595075.93651978 s in the future
 1387 18:51:10.172442  tar: ./net/forwarding/router_bridge_lag.sh: time stamp 2024-10-02 20:28:12 is 21595075.808422614 s in the future
 1388 18:51:10.298493  tar: ./net/forwarding/ipip_flat_gre.sh: time stamp 2024-10-02 20:28:12 is 21595075.682241405 s in the future
 1389 18:51:10.439388  tar: ./net/forwarding/sch_tbf_root.sh: time stamp 2024-10-02 20:28:12 is 21595075.541246447 s in the future
 1390 18:51:10.568843  tar: ./net/forwarding/skbedit_priority.sh: time stamp 2024-10-02 20:28:12 is 21595075.41222128 s in the future
 1391 18:51:10.697006  tar: ./net/forwarding/bridge_mdb_max.sh: time stamp 2024-10-02 20:28:12 is 21595075.28418503 s in the future
 1392 18:51:10.825520  tar: ./net/forwarding/ip6gre_custom_multipath_hash.sh: time stamp 2024-10-02 20:28:12 is 21595075.157182238 s in the future
 1393 18:51:10.974836  tar: ./net/forwarding/router_multicast.sh: time stamp 2024-10-02 20:28:12 is 21595075.00638003 s in the future
 1394 18:51:11.102985  tar: ./net/forwarding/mirror_gre_flower.sh: time stamp 2024-10-02 20:28:12 is 21595074.878271738 s in the future
 1395 18:51:11.226223  tar: ./net/forwarding/router_multipath.sh: time stamp 2024-10-02 20:28:12 is 21595074.756023655 s in the future
 1396 18:51:11.354758  tar: ./net/forwarding/vxlan_bridge_1d_port_8472.sh: time stamp 2024-10-02 20:28:12 is 21595074.626943947 s in the future
 1397 18:51:11.508234  tar: ./net/forwarding/tc_shblocks.sh: time stamp 2024-10-02 20:28:12 is 21595074.472437405 s in the future
 1398 18:51:11.937231  tar: ./net/forwarding/config: time stamp 2024-10-02 20:28:12 is 21595074.04352753 s in the future
 1399 18:51:12.066690  tar: ./net/forwarding/dual_vxlan_bridge.sh: time stamp 2024-10-02 20:28:12 is 21595073.915018738 s in the future
 1400 18:51:12.321865  tar: ./net/forwarding/mirror_gre_vlan_bridge_1q.sh: time stamp 2024-10-02 20:28:12 is 21595073.65987153 s in the future
 1401 18:51:12.462833  tar: ./net/forwarding/sch_ets_tests.sh: time stamp 2024-10-02 20:28:12 is 21595073.518368905 s in the future
 1402 18:51:12.585110  tar: ./net/forwarding/ip6gre_inner_v4_multipath.sh: time stamp 2024-10-02 20:28:12 is 21595073.396368072 s in the future
 1403 18:51:12.737738  tar: ./net/forwarding/mirror_vlan.sh: time stamp 2024-10-02 20:28:12 is 21595073.24294103 s in the future
 1404 18:51:12.872636  tar: ./net/forwarding/fib_offload_lib.sh: time stamp 2024-10-02 20:28:12 is 21595073.10960603 s in the future
 1405 18:51:13.001725  tar: ./net/forwarding/bridge_mdb.sh: time stamp 2024-10-02 20:28:12 is 21595072.979009697 s in the future
 1406 18:51:13.131135  tar: ./net/forwarding/bridge_vlan_aware.sh: time stamp 2024-10-02 20:28:12 is 21595072.850964697 s in the future
 1407 18:51:13.252061  tar: ./net/forwarding/router_bridge_1d.sh: time stamp 2024-10-02 20:28:12 is 21595072.72971103 s in the future
 1408 18:51:13.385548  tar: ./net/forwarding/bridge_vlan_mcast.sh: time stamp 2024-10-02 20:28:12 is 21595072.595238447 s in the future
 1409 18:51:13.513912  tar: ./net/forwarding/router.sh: time stamp 2024-10-02 20:28:12 is 21595072.467101196 s in the future
 1410 18:51:13.641136  tar: ./net/forwarding/ipip_flat_gre_key.sh: time stamp 2024-10-02 20:28:12 is 21595072.339329696 s in the future
 1411 18:51:13.777950  tar: ./net/forwarding/vxlan_asymmetric_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595072.204217613 s in the future
 1412 18:51:13.911428  tar: ./net/forwarding/router_broadcast.sh: time stamp 2024-10-02 20:28:12 is 21595072.069753613 s in the future
 1413 18:51:14.044024  tar: ./net/forwarding/ip6gre_hier_key.sh: time stamp 2024-10-02 20:28:12 is 21595071.937108113 s in the future
 1414 18:51:14.178683  tar: ./net/forwarding/bridge_fdb_learning_limit.sh: time stamp 2024-10-02 20:28:12 is 21595071.803672821 s in the future
 1415 18:51:14.303897  tar: ./net/forwarding/ip6gre_flat_key.sh: time stamp 2024-10-02 20:28:12 is 21595071.677730071 s in the future
 1416 18:51:14.431125  tar: ./net/forwarding/tc_flower_l2_miss.sh: time stamp 2024-10-02 20:28:12 is 21595071.549894946 s in the future
 1417 18:51:14.552060  tar: ./net/forwarding/ip6gre_inner_v6_multipath.sh: time stamp 2024-10-02 20:28:12 is 21595071.429997696 s in the future
 1418 18:51:14.670068  tar: ./net/forwarding/tc_tunnel_key.sh: time stamp 2024-10-02 20:28:12 is 21595071.311589446 s in the future
 1419 18:51:14.786556  tar: ./net/forwarding/no_forwarding.sh: time stamp 2024-10-14 14:49:46 is 22611565.193821071 s in the future
 1420 18:51:14.920010  tar: ./net/forwarding/router_mpath_seed.sh: time stamp 2024-10-02 20:28:12 is 21595071.061135946 s in the future
 1421 18:51:15.139061  tar: ./net/forwarding/vxlan_bridge_1q_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595070.842014363 s in the future
 1422 18:51:15.282144  tar: ./net/forwarding/vxlan_asymmetric.sh: time stamp 2024-10-02 20:28:12 is 21595070.699220696 s in the future
 1423 18:51:15.407202  tar: ./net/forwarding/sch_tbf_core.sh: time stamp 2024-10-02 20:28:12 is 21595070.573654905 s in the future
 1424 18:51:15.596782  tar: ./net/forwarding/gre_multipath.sh: time stamp 2024-10-02 20:28:12 is 21595070.384611988 s in the future
 1425 18:51:15.768156  tar: ./net/forwarding/sch_ets_core.sh: time stamp 2024-10-02 20:28:12 is 21595070.212636196 s in the future
 1426 18:51:15.929451  tar: ./net/forwarding/gre_inner_v6_multipath.sh: time stamp 2024-10-02 20:28:12 is 21595070.052135488 s in the future
 1427 18:51:16.068096  tar: ./net/forwarding/mirror_gre_lib.sh: time stamp 2024-10-02 20:28:12 is 21595069.912731446 s in the future
 1428 18:51:16.261686  tar: ./net/forwarding/sch_red.sh: time stamp 2024-10-02 20:28:12 is 21595069.718846196 s in the future
 1429 18:51:16.558057  tar: ./net/forwarding/ip6gre_flat_keys.sh: time stamp 2024-10-02 20:28:12 is 21595069.423476988 s in the future
 1430 18:51:16.724222  tar: ./net/forwarding/router_mpath_nh.sh: time stamp 2024-10-02 20:28:12 is 21595069.256607863 s in the future
 1431 18:51:16.873498  tar: ./net/forwarding/ipip_flat_gre_keys.sh: time stamp 2024-10-02 20:28:12 is 21595069.107181613 s in the future
 1432 18:51:18.802474  tar: ./net/forwarding/ip6gre_lib.sh: time stamp 2024-10-02 20:28:12 is 21595067.178288696 s in the future
 1433 18:51:19.285761  tar: ./net/forwarding/bridge_sticky_fdb.sh: time stamp 2024-10-02 20:28:12 is 21595066.695649279 s in the future
 1434 18:51:19.415428  tar: ./net/forwarding/vxlan_bridge_1q_port_8472_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595066.566112946 s in the future
 1435 18:51:19.584268  tar: ./net/forwarding/mirror_gre_bridge_1d_vlan.sh: time stamp 2024-10-02 20:28:12 is 21595066.397214404 s in the future
 1436 18:51:19.714583  tar: ./net/forwarding/tc_police.sh: time stamp 2024-10-02 20:28:12 is 21595066.265659737 s in the future
 1437 18:51:19.835458  tar: ./net/forwarding/gre_multipath_nh.sh: time stamp 2024-10-02 20:28:12 is 21595066.144962821 s in the future
 1438 18:51:19.962775  tar: ./net/forwarding/vxlan_bridge_1d_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595066.018463154 s in the future
 1439 18:51:20.103867  tar: ./net/forwarding/q_in_vni_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595065.878118821 s in the future
 1440 18:51:20.235322  tar: ./net/forwarding/vxlan_bridge_1q_port_8472.sh: time stamp 2024-10-02 20:28:12 is 21595065.746530029 s in the future
 1441 18:51:20.362382  tar: ./net/forwarding/mirror_lib.sh: time stamp 2024-10-02 20:28:12 is 21595065.618176779 s in the future
 1442 18:51:20.503160  tar: ./net/forwarding/vxlan_symmetric_ipv6.sh: time stamp 2024-10-02 20:28:12 is 21595065.477622821 s in the future
 1443 18:51:20.617618  tar: ./net/forwarding/pedit_dsfield.sh: time stamp 2024-10-02 20:28:12 is 21595065.362589029 s in the future
 1444 18:51:20.740560  tar: ./net/forwarding/settings: time stamp 2024-10-02 20:28:12 is 21595065.239156362 s in the future
 1445 18:51:20.895242  tar: ./net/forwarding/mirror_gre_nh.sh: time stamp 2024-10-02 20:28:12 is 21595065.085148612 s in the future
 1446 18:51:21.018112  tar: ./net/forwarding/ip6gre_flat.sh: time stamp 2024-10-02 20:28:12 is 21595064.962194779 s in the future
 1447 18:51:21.154786  tar: ./net/forwarding/tc_chains.sh: time stamp 2024-10-02 20:28:12 is 21595064.825773029 s in the future
 1448 18:51:21.269378  tar: ./net/forwarding/bridge_mdb_port_down.sh: time stamp 2024-10-02 20:28:12 is 21595064.711902779 s in the future
 1449 18:51:21.398076  tar: ./net/forwarding/gre_custom_multipath_hash.sh: time stamp 2024-10-02 20:28:12 is 21595064.584477446 s in the future
 1450 18:51:21.584535  tar: ./net/forwarding/mirror_gre_bound.sh: time stamp 2024-10-02 20:28:12 is 21595064.396439029 s in the future
 1451 18:51:21.803834  tar: ./net/forwarding/ip6_forward_instats_vrf.sh: time stamp 2024-10-02 20:28:12 is 21595064.177767029 s in the future
 1452 18:51:22.034395  tar: ./net/forwarding/tc_vlan_modify.sh: time stamp 2024-10-02 20:28:12 is 21595063.946210362 s in the future
 1453 18:51:22.239782  tar: ./net/forwarding/bridge_vlan_unaware.sh: time stamp 2024-10-02 20:28:12 is 21595063.74167782 s in the future
 1454 18:51:22.380617  tar: ./net/forwarding/bridge_mld.sh: time stamp 2024-10-02 20:28:12 is 21595063.599441487 s in the future
 1455 18:51:22.523693  tar: ./net/forwarding/gre_inner_v4_multipath.sh: time stamp 2024-10-02 20:28:12 is 21595063.457315404 s in the future
 1456 18:51:22.668765  tar: ./net/forwarding/router_nh.sh: time stamp 2024-10-02 20:28:12 is 21595063.311311612 s in the future
 1457 18:51:22.794988  tar: ./net/forwarding/mirror_topo_lib.sh: time stamp 2024-10-02 20:28:12 is 21595063.184787112 s in the future
 1458 18:51:22.923315  tar: ./net/forwarding/bridge_port_isolation.sh: time stamp 2024-10-02 20:28:12 is 21595063.057277695 s in the future
 1459 18:51:23.056995  tar: ./net/forwarding/sch_tbf_ets.sh: time stamp 2024-10-02 20:28:12 is 21595062.92394157 s in the future
 1460 18:51:23.174955  tar: ./net/forwarding/router_bridge_vlan_upper.sh: time stamp 2024-10-02 20:28:12 is 21595062.806939987 s in the future
 1461 18:51:23.441518  tar: ./net/forwarding/router_bridge_1d_lag.sh: time stamp 2024-10-02 20:28:12 is 21595062.53989557 s in the future
 1462 18:51:23.679596  tar: ./net/forwarding/custom_multipath_hash.sh: time stamp 2024-10-02 20:28:12 is 21595062.30157332 s in the future
 1463 18:51:23.821675  tar: ./net/forwarding/mirror_gre_lag_lacp.sh: time stamp 2024-10-02 20:28:12 is 21595062.159779654 s in the future
 1464 18:51:24.650979  tar: ./net/forwarding/min_max_mtu.sh: time stamp 2024-10-02 20:28:12 is 21595061.331014862 s in the future
 1465 18:51:24.880502  tar: ./net/forwarding/sch_ets.sh: time stamp 2024-10-02 20:28:12 is 21595061.09946132 s in the future
 1466 18:51:25.054017  tar: ./net/forwarding/tc_flower_cfm.sh: time stamp 2024-10-02 20:28:12 is 21595060.925725653 s in the future
 1467 18:51:25.181165  tar: ./net/forwarding/router_bridge_vlan.sh: time stamp 2024-10-02 20:28:12 is 21595060.799062528 s in the future
 1468 18:51:25.567059  tar: ./net/forwarding/local_termination.sh: time stamp 2024-10-02 20:28:12 is 21595060.413527528 s in the future
 1469 18:51:25.732142  tar: ./net/forwarding/mirror_gre_vlan.sh: time stamp 2024-10-02 20:28:12 is 21595060.247944528 s in the future
 1470 18:51:25.886764  tar: ./net/forwarding/router_bridge_vlan_upper_pvid.sh: time stamp 2024-10-02 20:28:12 is 21595060.09554757 s in the future
 1471 18:51:26.062844  tar: ./net/forwarding/mirror_gre_changes.sh: time stamp 2024-10-02 20:28:12 is 21595059.918529862 s in the future
 1472 18:51:26.299813  tar: ./net/forwarding/tc_common.sh: time stamp 2024-10-02 20:28:12 is 21595059.680459778 s in the future
 1473 18:51:26.576708  tar: ./net/forwarding/router_vid_1.sh: time stamp 2024-10-02 20:28:12 is 21595059.403246653 s in the future
 1474 18:51:26.826119  tar: ./net/forwarding/bridge_mdb_host.sh: time stamp 2024-10-02 20:28:12 is 21595059.154004237 s in the future
 1475 18:51:27.088566  tar: ./net/forwarding/ipip_hier_gre_keys.sh: time stamp 2024-10-02 20:28:12 is 21595058.891948737 s in the future
 1476 18:51:27.312872  tar: ./net/forwarding/mirror_gre_topo_lib.sh: time stamp 2024-10-02 20:28:12 is 21595058.668312112 s in the future
 1477 18:51:27.503510  tar: ./net/forwarding/forwarding.config.sample: time stamp 2024-10-02 20:28:12 is 21595058.477973278 s in the future
 1478 18:51:27.705873  tar: ./net/forwarding/pedit_l4port.sh: time stamp 2024-10-02 20:28:12 is 21595058.27448582 s in the future
 1479 18:51:27.945895  tar: ./net/forwarding/lib_sh_test.sh: time stamp 2024-10-02 20:28:12 is 21595058.034177486 s in the future
 1480 18:51:28.153187  tar: ./net/forwarding/ip6gre_hier_keys.sh: time stamp 2024-10-02 20:28:12 is 21595057.827181736 s in the future
 1481 18:51:28.357760  tar: ./net/forwarding/router_mpath_nh_lib.sh: time stamp 2024-10-02 20:28:12 is 21595057.623374028 s in the future
 1482 18:51:28.589505  tar: ./net/forwarding/mirror_gre_bridge_1q.sh: time stamp 2024-10-02 20:28:12 is 21595057.39172807 s in the future
 1483 18:51:28.798155  tar: ./net/forwarding/ipip_hier_gre.sh: time stamp 2024-10-02 20:28:12 is 21595057.182876653 s in the future
 1484 18:51:29.007727  tar: ./net/forwarding/bridge_igmp.sh: time stamp 2024-10-02 20:28:12 is 21595056.97236407 s in the future
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 1525 18:51:36.666309  tar: ./net/packetdrill/tcp_zerocopy_small.pkt: time stamp 2024-10-02 20:28:12 is 21595049.31409561 s in the future
 1526 18:51:36.802395  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-win-update.pkt: time stamp 2024-10-02 20:28:12 is 21595049.17978536 s in the future
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 1529 18:51:37.264113  tar: ./net/packetdrill/tcp_zerocopy_closed.pkt: time stamp 2024-10-02 20:28:12 is 21595048.715928235 s in the future
 1530 18:51:37.402467  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-6pkt.pkt: time stamp 2024-10-02 20:28:12 is 21595048.58070361 s in the future
 1531 18:51:37.534508  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited-9-packets-out.pkt: time stamp 2024-10-02 20:28:12 is 21595048.449091152 s in the future
 1532 18:51:37.674731  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-10-02 20:28:12 is 21595048.306879319 s in the future
 1533 18:51:37.825419  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited.pkt: time stamp 2024-10-02 20:28:12 is 21595048.157058152 s in the future
 1534 18:51:37.976117  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt.pkt: time stamp 2024-10-02 20:28:12 is 21595048.005757777 s in the future
 1535 18:51:38.128882  tar: ./net/packetdrill/ksft_runner.sh: time stamp 2024-10-02 20:28:12 is 21595047.851682735 s in the future
 1536 18:51:38.299739  tar: ./net/packetdrill/tcp_md5_md5-only-on-client-ack.pkt: time stamp 2024-10-02 20:28:12 is 21595047.682356819 s in the future
 1537 18:51:38.435343  tar: ./net/packetdrill/tcp_zerocopy_batch.pkt: time stamp 2024-10-02 20:28:12 is 21595047.544931652 s in the future
 1538 18:51:38.565917  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-1pkt.pkt: time stamp 2024-10-02 20:28:12 is 21595047.416502777 s in the future
 1539 18:51:38.889687  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-10-02 20:28:12 is 21595047.091140485 s in the future
 1540 18:51:39.021417  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-5pkt.pkt: time stamp 2024-10-02 20:28:12 is 21595046.961174735 s in the future
 1541 18:51:39.138514  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-02 20:28:12 is 21595046.844273735 s in the future
 1542 18:51:39.275647  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-4pkt.pkt: time stamp 2024-10-02 20:28:12 is 21595046.707283527 s in the future
 1543 18:51:39.412728  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-idle.pkt: time stamp 2024-10-02 20:28:12 is 21595046.569088568 s in the future
 1544 18:51:39.544122  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-10-02 20:28:12 is 21595046.436245443 s in the future
 1545 18:51:39.671457  tar: ./net/packetdrill/tcp_inq_server.pkt: time stamp 2024-10-02 20:28:12 is 21595046.308897527 s in the future
 1546 18:51:39.806027  tar: ./net/packetdrill/tcp_inq_client.pkt: time stamp 2024-10-02 20:28:12 is 21595046.173428318 s in the future
 1547 18:51:39.951246  tar: ./net/packetdrill/tcp_zerocopy_fastopen-client.pkt: time stamp 2024-10-02 20:28:12 is 21595046.02969661 s in the future
 1548 18:51:40.073278  tar: ./net/packetdrill/tcp_zerocopy_epoll_edge.pkt: time stamp 2024-10-02 20:28:12 is 21595045.908512902 s in the future
 1549 18:51:40.130790  tar: ./net/packetdrill: time stamp 2024-10-02 20:28:12 is 21595045.848195318 s in the future
 1550 18:51:40.197566  tar: ./net: time stamp 2024-10-14 18:07:45 is 22623418.779629277 s in the future
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 1557 18:51:41.373334  tar: ./drivers/net/virtio_net/basic_features.sh: time stamp 2024-10-02 20:28:12 is 21595044.607309652 s in the future
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 1575 18:51:43.650878  tar: ./drivers/net/bonding/mode-1-recovery-updelay.sh: time stamp 2024-10-02 20:28:12 is 21595042.330243443 s in the future
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 1578 18:51:44.070955  tar: ./drivers/net/bonding/bond-arp-interval-causes-panic.sh: time stamp 2024-10-02 20:28:12 is 21595041.910720568 s in the future
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 1580 18:51:44.339056  tar: ./drivers/net/bonding/mode-2-recovery-updelay.sh: time stamp 2024-10-02 20:28:12 is 21595041.641347443 s in the future
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 1582 18:51:44.586094  tar: ./drivers/net/bonding/settings: time stamp 2024-10-02 20:28:12 is 21595041.393380818 s in the future
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 1593 18:51:46.670100  tar: ./drivers/platform/x86/intel/ifs/test_ifs.sh: time stamp 2024-10-02 20:28:12 is 21595039.310756568 s in the future
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 2074 18:52:53.820820  tar: ./tc-testing/tc-tests/qdiscs/skbprio.json: time stamp 2024-10-02 20:28:12 is 21594972.156433143 s in the future
 2075 18:52:53.946007  tar: ./tc-testing/tc-tests/qdiscs/hhf.json: time stamp 2024-10-02 20:28:12 is 21594972.031218476 s in the future
 2076 18:52:54.110365  tar: ./tc-testing/tc-tests/qdiscs/codel.json: time stamp 2024-10-02 20:28:12 is 21594971.866469143 s in the future
 2077 18:52:54.263148  tar: ./tc-testing/tc-tests/qdiscs/ets.json: time stamp 2024-10-02 20:28:12 is 21594971.712819893 s in the future
 2078 18:52:54.432581  tar: ./tc-testing/tc-tests/qdiscs/pfifo_fast.json: time stamp 2024-10-02 20:28:12 is 21594971.545003643 s in the future
 2079 18:52:54.600065  tar: ./tc-testing/tc-tests/qdiscs/qfq.json: time stamp 2024-10-02 20:28:12 is 21594971.376968018 s in the future
 2080 18:52:54.767566  tar: ./tc-testing/tc-tests/qdiscs/etf.json: time stamp 2024-10-02 20:28:12 is 21594971.209433268 s in the future
 2081 18:52:54.924337  tar: ./tc-testing/tc-tests/qdiscs/cake.json: time stamp 2024-10-02 20:28:12 is 21594971.051730393 s in the future
 2082 18:52:55.051582  tar: ./tc-testing/tc-tests/qdiscs/taprio.json: time stamp 2024-10-02 20:28:12 is 21594970.925115851 s in the future
 2083 18:52:55.202001  tar: ./tc-testing/tc-tests/qdiscs/drr.json: time stamp 2024-10-02 20:28:12 is 21594970.774309434 s in the future
 2084 18:52:55.386444  tar: ./tc-testing/tc-tests/qdiscs/prio.json: time stamp 2024-10-02 20:28:12 is 21594970.590410101 s in the future
 2085 18:52:55.524244  tar: ./tc-testing/tc-tests/qdiscs/fq_pie.json: time stamp 2024-10-02 20:28:12 is 21594970.452110768 s in the future
 2086 18:52:55.670294  tar: ./tc-testing/tc-tests/qdiscs/mq.json: time stamp 2024-10-02 20:28:12 is 21594970.305823018 s in the future
 2087 18:52:55.838746  tar: ./tc-testing/tc-tests/qdiscs/plug.json: time stamp 2024-10-02 20:28:12 is 21594970.138301934 s in the future
 2088 18:52:56.005994  tar: ./tc-testing/tc-tests/qdiscs/mqprio.json: time stamp 2024-10-02 20:28:12 is 21594969.970522809 s in the future
 2089 18:52:56.071894  tar: ./tc-testing/tc-tests/qdiscs: time stamp 2024-10-02 20:28:12 is 21594969.902671434 s in the future
 2090 18:52:56.266787  tar: ./tc-testing/tc-tests/actions/sample.json: time stamp 2024-10-02 20:28:12 is 21594969.709973351 s in the future
 2091 18:52:56.434110  tar: ./tc-testing/tc-tests/actions/connmark.json: time stamp 2024-10-02 20:28:12 is 21594969.542711268 s in the future
 2092 18:52:56.591988  tar: ./tc-testing/tc-tests/actions/tunnel_key.json: time stamp 2024-10-02 20:28:12 is 21594969.385446434 s in the future
 2093 18:52:56.754981  tar: ./tc-testing/tc-tests/actions/mpls.json: time stamp 2024-10-02 20:28:12 is 21594969.221212601 s in the future
 2094 18:52:56.893895  tar: ./tc-testing/tc-tests/actions/skbedit.json: time stamp 2024-10-02 20:28:12 is 21594969.082949059 s in the future
 2095 18:52:57.061075  tar: ./tc-testing/tc-tests/actions/skbmod.json: time stamp 2024-10-02 20:28:12 is 21594968.914634434 s in the future
 2096 18:52:57.213675  tar: ./tc-testing/tc-tests/actions/ife.json: time stamp 2024-10-02 20:28:12 is 21594968.763409184 s in the future
 2097 18:52:57.376832  tar: ./tc-testing/tc-tests/actions/gact.json: time stamp 2024-10-02 20:28:12 is 21594968.599955267 s in the future
 2098 18:52:57.553696  tar: ./tc-testing/tc-tests/actions/gate.json: time stamp 2024-10-02 20:28:12 is 21594968.422768976 s in the future
 2099 18:52:57.733919  tar: ./tc-testing/tc-tests/actions/pedit.json: time stamp 2024-10-02 20:28:12 is 21594968.242741184 s in the future
 2100 18:52:58.477802  tar: ./tc-testing/tc-tests/actions/bpf.json: time stamp 2024-10-02 20:28:12 is 21594967.499256559 s in the future
 2101 18:53:01.532425  tar: ./tc-testing/tc-tests/actions/simple.json: time stamp 2024-10-02 20:28:12 is 21594964.4446636 s in the future
 2102 18:53:05.452960  tar: ./tc-testing/tc-tests/actions/police.json: time stamp 2024-10-02 20:28:12 is 21594960.524873891 s in the future
 2103 18:53:09.274117  tar: ./tc-testing/tc-tests/actions/nat.json: time stamp 2024-10-02 20:28:12 is 21594956.702519058 s in the future
 2104 18:53:09.438437  tar: ./tc-testing/tc-tests/actions/csum.json: time stamp 2024-10-02 20:28:12 is 21594956.538029474 s in the future
 2105 18:53:09.623753  tar: ./tc-testing/tc-tests/actions/ctinfo.json: time stamp 2024-10-02 20:28:12 is 21594956.351539266 s in the future
 2106 18:53:09.776286  tar: ./tc-testing/tc-tests/actions/vlan.json: time stamp 2024-10-02 20:28:12 is 21594956.199752141 s in the future
 2107 18:53:09.924570  tar: ./tc-testing/tc-tests/actions/mirred.json: time stamp 2024-10-02 20:28:12 is 21594956.051706933 s in the future
 2108 18:53:10.142740  tar: ./tc-testing/tc-tests/actions/ct.json: time stamp 2024-10-02 20:28:12 is 21594955.833308058 s in the future
 2109 18:53:10.195902  tar: ./tc-testing/tc-tests/actions: time stamp 2024-10-02 20:28:12 is 21594955.779254183 s in the future
 2110 18:53:10.257564  tar: ./tc-testing/tc-tests: time stamp 2024-10-02 20:28:12 is 21594955.716598516 s in the future
 2111 18:53:10.475514  tar: ./tc-testing/config: time stamp 2024-10-02 20:28:12 is 21594955.498899724 s in the future
 2112 18:53:10.609988  tar: ./tc-testing/TdcPlugin.py: time stamp 2024-10-02 20:28:12 is 21594955.365295808 s in the future
 2113 18:53:10.718143  tar: ./tc-testing/tdc_helper.py: time stamp 2024-10-02 20:28:12 is 21594955.257691558 s in the future
 2114 18:53:10.884360  tar: ./tc-testing/tdc.sh: time stamp 2024-10-02 20:28:12 is 21594955.090026432 s in the future
 2115 18:53:11.010426  tar: ./tc-testing/tdc_config.py: time stamp 2024-10-02 20:28:12 is 21594954.964781599 s in the future
 2116 18:53:11.125961  tar: ./tc-testing/settings: time stamp 2024-10-02 20:28:12 is 21594954.848895724 s in the future
 2117 18:53:11.261594  tar: ./tc-testing/plugin-lib/scapyPlugin.py: time stamp 2024-10-02 20:28:12 is 21594954.714505682 s in the future
 2118 18:53:11.386715  tar: ./tc-testing/plugin-lib/README-PLUGINS: time stamp 2024-10-02 20:28:12 is 21594954.589315349 s in the future
 2119 18:53:11.499264  tar: ./tc-testing/plugin-lib/rootPlugin.py: time stamp 2024-10-02 20:28:12 is 21594954.477877141 s in the future
 2120 18:53:11.628368  tar: ./tc-testing/plugin-lib/nsPlugin.py: time stamp 2024-10-02 20:28:12 is 21594954.347127057 s in the future
 2121 18:53:11.791401  tar: ./tc-testing/plugin-lib/valgrindPlugin.py: time stamp 2024-10-02 20:28:12 is 21594954.184131766 s in the future
 2122 18:53:11.891088  tar: ./tc-testing/plugin-lib: time stamp 2024-10-02 20:28:12 is 21594954.083863141 s in the future
 2123 18:53:12.050823  tar: ./tc-testing/action-ebpf: time stamp 2024-10-02 20:28:12 is 21594953.924392016 s in the future
 2124 18:53:12.209755  tar: ./tc-testing/scripts/taprio_wait_for_admin.sh: time stamp 2024-10-02 20:28:12 is 21594953.766972349 s in the future
 2125 18:53:12.261906  tar: ./tc-testing/scripts: time stamp 2024-10-02 20:28:12 is 21594953.713300099 s in the future
 2126 18:53:12.379602  tar: ./tc-testing/tdc_config_local_template.py: time stamp 2024-10-02 20:28:12 is 21594953.596871557 s in the future
 2127 18:53:12.503764  tar: ./tc-testing/tdc_batch.py: time stamp 2024-10-02 20:28:12 is 21594953.471273016 s in the future
 2128 18:53:12.695080  tar: ./tc-testing/tdc_multibatch.py: time stamp 2024-10-02 20:28:12 is 21594953.280058724 s in the future
 2129 18:53:12.819190  tar: ./tc-testing/plugins/__init__.py: time stamp 2024-10-02 20:28:12 is 21594953.156862141 s in the future
 2130 18:53:12.869263  tar: ./tc-testing/plugins: time stamp 2024-10-02 20:28:12 is 21594953.104871516 s in the future
 2131 18:53:12.919208  tar: ./tc-testing: time stamp 2024-10-14 18:07:48 is 22623329.054314266 s in the future
 2132 18:53:13.076906  tar: ./kselftest/runner.sh: time stamp 2024-10-14 18:07:36 is 22623316.898405432 s in the future
 2133 18:53:13.202904  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-02 20:28:12 is 21594952.771032974 s in the future
 2134 18:53:13.334000  tar: ./kselftest/module.sh: time stamp 2024-10-14 18:07:36 is 22623316.639553182 s in the future
 2135 18:53:13.461993  tar: ./kselftest/ksft.py: time stamp 2024-10-14 18:07:36 is 22623316.512062307 s in the future
 2136 18:53:13.595343  tar: ./kselftest/prefix.pl: time stamp 2024-10-14 18:07:36 is 22623316.378541891 s in the future
 2137 18:53:13.669490  tar: ./kselftest: time stamp 2024-10-02 20:28:12 is 21594952.303959016 s in the future
 2138 18:53:14.212436  tar: ./fchmodat2/fchmodat2_test: time stamp 2024-10-14 18:05:50 is 22623209.762000557 s in the future
 2139 18:53:14.284499  tar: ./fchmodat2: time stamp 2024-10-14 18:07:39 is 22623318.688720474 s in the future
 2140 18:53:14.437008  tar: ./tty/tty_tstamp_update: time stamp 2024-10-14 18:07:21 is 22623300.536699724 s in the future
 2141 18:53:14.498266  tar: ./tty: time stamp 2024-10-14 18:07:49 is 22623328.473918765 s in the future
 2142 18:53:14.567014  tar: .: time stamp 2024-10-14 18:07:51 is 22623330.405360224 s in the future
 2143 18:53:14.833000  skiplist:
 2144 18:53:14.833393  ========================================
 2145 18:53:14.839744  ========================================
 2146 18:53:15.148594  dt:test_unprobed_devices.sh
 2147 18:53:15.288719  ============== Tests to run ===============
 2148 18:53:15.306583  dt:test_unprobed_devices.sh
 2149 18:53:15.309881  ===========End Tests to run ===============
 2150 18:53:15.344074  shardfile-dt pass
 2151 18:53:15.686868  <12>[  241.245935] kselftest: Running tests in dt
 2152 18:53:15.716860  TAP version 13
 2153 18:53:15.743500  1..1
 2154 18:53:15.801699  # timeout set to 45
 2155 18:53:15.802110  # selftests: dt: test_unprobed_devices.sh
 2156 18:53:16.586107  # TAP version 13
 2157 18:53:41.848777  # 1..257
 2158 18:53:42.016837  # ok 1 / # SKIP
 2159 18:53:42.040466  # ok 2 /clk_mcasp0
 2160 18:53:42.112864  # ok 3 /clk_mcasp0_fixed # SKIP
 2161 18:53:42.194113  # ok 4 /cpus/cpu@0 # SKIP
 2162 18:53:42.264382  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2163 18:53:42.289741  # ok 6 /fixedregulator0
 2164 18:53:42.307099  # ok 7 /leds
 2165 18:53:42.328982  # ok 8 /ocp
 2166 18:53:42.353766  # ok 9 /ocp/interconnect@44c00000
 2167 18:53:42.381434  # ok 10 /ocp/interconnect@44c00000/segment@0
 2168 18:53:42.403731  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2169 18:53:42.431852  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2170 18:53:42.503868  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2171 18:53:42.521797  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2172 18:53:42.547444  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2173 18:53:42.657372  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2174 18:53:42.733916  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2175 18:53:42.805938  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2176 18:53:42.881876  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2177 18:53:42.985763  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2178 18:53:43.034933  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2179 18:53:43.110240  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2180 18:53:43.181935  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2181 18:53:43.256469  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2182 18:53:43.331038  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2183 18:53:43.406574  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2184 18:53:43.478795  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2185 18:53:43.554231  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2186 18:53:43.628855  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2187 18:53:43.702090  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2188 18:53:43.777636  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2189 18:53:43.851245  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2190 18:53:43.925904  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2191 18:53:43.999573  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2192 18:53:44.073421  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2193 18:53:44.148697  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2194 18:53:44.222361  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2195 18:53:44.301094  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2196 18:53:44.376175  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2197 18:53:44.451609  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2198 18:53:44.521865  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2199 18:53:44.598952  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2200 18:53:44.670203  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2201 18:53:44.744869  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2202 18:53:44.820762  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2203 18:53:44.893435  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2204 18:53:44.966985  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2205 18:53:45.042706  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2206 18:53:45.116861  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2207 18:53:45.194511  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2208 18:53:45.265056  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2209 18:53:45.339911  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2210 18:53:45.415222  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2211 18:53:45.488628  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2212 18:53:45.563023  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2213 18:53:45.637020  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2214 18:53:45.711913  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2215 18:53:45.786319  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2216 18:53:45.859201  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2217 18:53:45.934862  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2218 18:53:46.007280  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2219 18:53:46.082764  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2220 18:53:46.161721  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2221 18:53:46.235358  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2222 18:53:46.310763  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2223 18:53:46.386558  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2224 18:53:46.461668  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2225 18:53:46.535219  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2226 18:53:46.606534  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2227 18:53:46.679321  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2228 18:53:46.754772  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2229 18:53:46.827571  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2230 18:53:46.899792  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2231 18:53:46.974440  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2232 18:53:47.051443  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2233 18:53:47.119787  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2234 18:53:47.193371  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2235 18:53:47.266651  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2236 18:53:47.342743  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2237 18:53:47.418862  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2238 18:53:47.490934  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2239 18:53:47.565742  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2240 18:53:47.638081  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2241 18:53:47.712750  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2242 18:53:47.786302  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2243 18:53:47.860976  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2244 18:53:47.976779  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2245 18:53:48.015598  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2246 18:53:48.091805  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2247 18:53:48.163575  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2248 18:53:48.235920  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2249 18:53:48.311722  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2250 18:53:48.385376  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2251 18:53:48.461216  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2252 18:53:48.482854  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2253 18:53:48.506157  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2254 18:53:48.530874  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2255 18:53:48.554788  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2256 18:53:48.579510  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2257 18:53:48.609796  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2258 18:53:48.627997  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2259 18:53:48.653716  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2260 18:53:48.763910  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2261 18:53:48.787464  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2262 18:53:48.811065  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2263 18:53:48.835744  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2264 18:53:48.946388  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2265 18:53:49.020896  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2266 18:53:49.095780  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2267 18:53:49.170571  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2268 18:53:49.249798  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2269 18:53:49.320169  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2270 18:53:49.394978  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2271 18:53:49.469471  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2272 18:53:49.544326  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2273 18:53:49.623345  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2274 18:53:49.697351  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2275 18:53:49.767786  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2276 18:53:49.842666  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2277 18:53:49.917697  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2278 18:53:49.992753  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2279 18:53:50.066907  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2280 18:53:50.089796  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2281 18:53:50.161391  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2282 18:53:50.231503  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2283 18:53:50.305570  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2284 18:53:50.328239  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2285 18:53:50.402330  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2286 18:53:50.425585  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2287 18:53:50.499492  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2288 18:53:50.524455  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2289 18:53:50.546775  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2290 18:53:50.571527  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2291 18:53:50.596105  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2292 18:53:50.619619  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2293 18:53:50.644247  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2294 18:53:50.670182  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 2295 18:53:50.752897  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 2296 18:53:50.770322  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2297 18:53:50.797632  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2298 18:53:50.868781  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2299 18:53:50.943409  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2300 18:53:50.964588  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2301 18:53:51.068878  # not ok 144 /ocp/interconnect@47c00000
 2302 18:53:51.147040  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2303 18:53:51.164637  # ok 146 /ocp/interconnect@48000000
 2304 18:53:51.189488  # ok 147 /ocp/interconnect@48000000/segment@0
 2305 18:53:51.214710  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2306 18:53:51.242429  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2307 18:53:51.262827  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2308 18:53:51.290673  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2309 18:53:51.312081  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2310 18:53:51.334466  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2311 18:53:51.357109  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2312 18:53:51.432324  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2313 18:53:51.509804  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2314 18:53:51.527062  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2315 18:53:51.551544  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2316 18:53:51.574892  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2317 18:53:51.598298  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2318 18:53:51.621798  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2319 18:53:51.644973  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2320 18:53:51.668704  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2321 18:53:51.698833  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2322 18:53:51.715952  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2323 18:53:51.741562  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2324 18:53:51.763833  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2325 18:53:51.788191  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2326 18:53:51.810824  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2327 18:53:51.840728  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2328 18:53:51.862208  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2329 18:53:51.891462  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2330 18:53:51.906187  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2331 18:53:51.932814  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2332 18:53:51.952832  # ok 175 /ocp/interconnect@48000000/segment@100000
 2333 18:53:51.978547  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2334 18:53:52.002239  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2335 18:53:52.081224  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 2336 18:53:52.151739  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 2337 18:53:52.220913  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 2338 18:53:52.298203  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 2339 18:53:52.369626  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 2340 18:53:52.445510  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 2341 18:53:52.515996  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 2342 18:53:52.596155  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 2343 18:53:52.612323  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2344 18:53:52.636030  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2345 18:53:52.662665  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2346 18:53:52.683020  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2347 18:53:52.707357  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2348 18:53:52.732311  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2349 18:53:52.755823  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2350 18:53:52.780766  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2351 18:53:52.803439  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2352 18:53:52.826807  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2353 18:53:52.850408  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2354 18:53:52.875723  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2355 18:53:52.900187  # ok 198 /ocp/interconnect@48000000/segment@200000
 2356 18:53:52.922868  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2357 18:53:56.399529  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2358 18:53:56.404424  # ok 201 /ocp/interconnect@48000000/segment@300000
 2359 18:53:56.407968  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2360 18:53:56.413146  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2361 18:53:56.419474  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2362 18:53:56.424390  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2363 18:53:56.434505  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2364 18:53:56.440394  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2365 18:53:56.445360  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2366 18:53:56.450066  # ok 209 /ocp/interconnect@4a000000
 2367 18:53:56.455093  # ok 210 /ocp/interconnect@4a000000/segment@0
 2368 18:53:56.461255  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2369 18:53:56.466204  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2370 18:53:56.476196  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2371 18:53:56.482387  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2372 18:53:56.487246  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2373 18:53:56.497175  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2374 18:53:56.503581  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2375 18:53:56.513290  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2376 18:53:56.518316  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2377 18:53:56.529570  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2378 18:53:56.534171  # not ok 221 /ocp/interconnect@4b140000
 2379 18:53:56.539223  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2380 18:53:56.539610  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2381 18:53:56.545453  # ok 224 /ocp/target-module@40300000
 2382 18:53:56.550206  # ok 225 /ocp/target-module@40300000/sram@0
 2383 18:53:56.554948  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2384 18:53:56.560082  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2385 18:53:56.566138  # ok 228 /ocp/target-module@47400000
 2386 18:53:56.570998  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2387 18:53:56.571386  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2388 18:53:56.575804  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2389 18:53:56.580767  # ok 232 /ocp/target-module@47400000/usb@1400
 2390 18:53:56.586922  # ok 233 /ocp/target-module@47400000/usb@1800
 2391 18:53:56.587306  # ok 234 /ocp/target-module@47810000
 2392 18:53:56.591803  # ok 235 /ocp/target-module@49000000
 2393 18:53:56.596581  # ok 236 /ocp/target-module@49000000/dma@0
 2394 18:53:56.601667  # ok 237 /ocp/target-module@49800000
 2395 18:53:56.602074  # ok 238 /ocp/target-module@49800000/dma@0
 2396 18:53:56.607708  # ok 239 /ocp/target-module@49900000
 2397 18:53:56.612672  # ok 240 /ocp/target-module@49900000/dma@0
 2398 18:53:56.613053  # ok 241 /ocp/target-module@49a00000
 2399 18:53:56.617321  # ok 242 /ocp/target-module@49a00000/dma@0
 2400 18:53:56.622517  # ok 243 /ocp/target-module@4c000000
 2401 18:53:56.628560  # not ok 244 /ocp/target-module@4c000000/emif@0
 2402 18:53:56.628943  # ok 245 /ocp/target-module@50000000
 2403 18:53:56.633572  # ok 246 /ocp/target-module@53100000
 2404 18:53:56.638297  # not ok 247 /ocp/target-module@53100000/sham@0
 2405 18:53:56.638680  # ok 248 /ocp/target-module@53500000
 2406 18:53:56.643370  # not ok 249 /ocp/target-module@53500000/aes@0
 2407 18:53:56.649609  # ok 250 /ocp/target-module@56000000
 2408 18:53:56.654510  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2409 18:53:56.654892  # ok 252 /opp-table # SKIP
 2410 18:53:56.655201  # ok 253 /soc # SKIP
 2411 18:53:56.659224  # ok 254 /sound
 2412 18:53:56.659606  # ok 255 /target-module@4b000000
 2413 18:53:56.664308  # ok 256 /target-module@4b000000/target-module@140000
 2414 18:53:56.670617  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2415 18:53:56.674522  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2416 18:53:56.680505  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2417 18:53:58.794237  dt_test_unprobed_devices_sh_ skip
 2418 18:53:58.799439  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2419 18:53:58.805560  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2420 18:53:58.805963  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2421 18:53:58.814398  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2422 18:53:58.814776  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2423 18:53:58.820518  dt_test_unprobed_devices_sh_leds pass
 2424 18:53:58.825396  dt_test_unprobed_devices_sh_ocp pass
 2425 18:53:58.825776  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2426 18:53:58.835142  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2427 18:53:58.841388  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2428 18:53:58.846165  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2429 18:53:58.856393  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2430 18:53:58.861389  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2431 18:53:58.871391  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2432 18:53:58.877587  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2433 18:53:58.888845  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2434 18:53:58.898910  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2435 18:53:58.910005  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2436 18:53:58.922434  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2437 18:53:58.927459  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2438 18:53:58.938581  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2439 18:53:58.949745  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2440 18:53:58.961084  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2441 18:53:58.972451  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2442 18:53:58.978530  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2443 18:53:58.989578  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2444 18:53:59.000588  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2445 18:53:59.011382  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2446 18:53:59.022371  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2447 18:53:59.032199  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2448 18:53:59.038250  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2449 18:53:59.048201  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2450 18:53:59.059333  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2451 18:53:59.069086  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2452 18:53:59.079451  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2453 18:53:59.090575  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2454 18:53:59.096708  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2455 18:53:59.107700  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2456 18:53:59.118733  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2457 18:53:59.130080  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2458 18:53:59.141113  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2459 18:53:59.153881  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2460 18:53:59.163313  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2461 18:53:59.173385  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2462 18:53:59.189293  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2463 18:53:59.200204  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2464 18:53:59.211351  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2465 18:53:59.223575  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2466 18:53:59.234626  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2467 18:53:59.245614  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2468 18:53:59.255620  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2469 18:53:59.266613  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2470 18:53:59.278866  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2471 18:53:59.289889  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2472 18:53:59.300858  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2473 18:53:59.311851  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2474 18:53:59.322864  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2475 18:53:59.329108  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2476 18:53:59.340065  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2477 18:53:59.351040  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2478 18:53:59.363499  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2479 18:53:59.374387  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2480 18:53:59.385398  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2481 18:53:59.396523  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2482 18:53:59.407531  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2483 18:53:59.418510  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2484 18:53:59.429619  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2485 18:53:59.440735  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2486 18:53:59.450409  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2487 18:53:59.461280  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2488 18:53:59.472454  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2489 18:53:59.482055  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2490 18:53:59.493140  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2491 18:53:59.502868  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2492 18:53:59.514116  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2493 18:53:59.528736  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2494 18:53:59.539773  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2495 18:53:59.549658  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2496 18:53:59.559448  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2497 18:53:59.570389  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2498 18:53:59.581461  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2499 18:53:59.591297  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2500 18:53:59.602243  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2501 18:53:59.612092  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2502 18:53:59.623145  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2503 18:53:59.633053  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2504 18:53:59.643968  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2505 18:53:59.653863  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2506 18:53:59.664907  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2507 18:53:59.675882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2508 18:53:59.688293  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2509 18:53:59.699412  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2510 18:53:59.710467  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2511 18:53:59.721518  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2512 18:53:59.727568  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2513 18:53:59.738531  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2514 18:53:59.749614  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2515 18:53:59.755655  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2516 18:53:59.766603  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2517 18:53:59.777621  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2518 18:53:59.782586  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2519 18:53:59.793664  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2520 18:53:59.804658  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2521 18:53:59.810748  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2522 18:53:59.821836  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2523 18:53:59.832791  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2524 18:53:59.842583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2525 18:53:59.858347  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2526 18:53:59.869579  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2527 18:53:59.879188  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2528 18:53:59.890287  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2529 18:53:59.905049  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2530 18:53:59.915993  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2531 18:53:59.925722  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2532 18:53:59.936783  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2533 18:53:59.953909  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2534 18:53:59.964882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2535 18:53:59.975851  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2536 18:53:59.987983  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2537 18:54:00.004019  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2538 18:54:00.016499  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2539 18:54:00.027395  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2540 18:54:00.038462  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2541 18:54:00.044537  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2542 18:54:00.055583  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2543 18:54:00.060543  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2544 18:54:00.072664  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2545 18:54:00.076534  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2546 18:54:00.088670  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2547 18:54:00.093660  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2548 18:54:00.104579  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2549 18:54:00.110625  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2550 18:54:00.121683  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2551 18:54:00.132861  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2552 18:54:00.138817  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2553 18:54:00.148692  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 2554 18:54:00.158501  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 2555 18:54:00.169685  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2556 18:54:00.180779  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2557 18:54:00.190486  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2558 18:54:00.201675  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2559 18:54:00.210171  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2560 18:54:00.216330  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2561 18:54:00.221270  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2562 18:54:00.227191  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2563 18:54:00.232252  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2564 18:54:00.238604  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2565 18:54:00.248334  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2566 18:54:00.253393  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2567 18:54:00.264356  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2568 18:54:00.269105  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2569 18:54:00.280405  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2570 18:54:00.285221  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2571 18:54:00.294954  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2572 18:54:00.305939  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2573 18:54:00.310781  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2574 18:54:00.321880  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2575 18:54:00.326699  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2576 18:54:00.336544  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2577 18:54:00.347626  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2578 18:54:00.352354  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2579 18:54:00.363499  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2580 18:54:00.368405  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2581 18:54:00.378088  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2582 18:54:00.384169  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2583 18:54:00.393837  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2584 18:54:00.405075  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2585 18:54:00.410030  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2586 18:54:00.419757  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2587 18:54:00.425854  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2588 18:54:00.435538  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2589 18:54:00.446655  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2590 18:54:00.451649  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2591 18:54:00.461330  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2592 18:54:00.467523  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2593 18:54:00.476994  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2594 18:54:00.488139  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 2595 18:54:00.497964  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 2596 18:54:00.509121  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 2597 18:54:00.518742  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 2598 18:54:00.529877  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 2599 18:54:00.539519  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 2600 18:54:00.550628  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 2601 18:54:00.565370  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 2602 18:54:00.571447  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2603 18:54:00.576400  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2604 18:54:00.586113  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2605 18:54:00.597084  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2606 18:54:00.601884  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2607 18:54:00.613027  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2608 18:54:00.622683  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2609 18:54:00.627652  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2610 18:54:00.638608  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2611 18:54:00.648578  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2612 18:54:00.654659  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2613 18:54:00.664097  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2614 18:54:00.669354  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2615 18:54:00.680409  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2616 18:54:00.685103  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2617 18:54:00.696210  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2618 18:54:00.701105  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2619 18:54:00.710790  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2620 18:54:00.717148  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2621 18:54:00.726722  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2622 18:54:00.731861  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2623 18:54:00.742866  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2624 18:54:00.752426  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2625 18:54:00.758538  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2626 18:54:00.763404  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2627 18:54:00.773463  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2628 18:54:00.779500  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2629 18:54:00.789148  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2630 18:54:00.800284  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2631 18:54:00.805140  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2632 18:54:00.814713  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2633 18:54:00.825954  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2634 18:54:00.835739  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2635 18:54:00.846610  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2636 18:54:00.856664  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2637 18:54:00.862589  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2638 18:54:00.866414  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2639 18:54:00.872448  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2640 18:54:00.877517  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2641 18:54:00.883648  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2642 18:54:00.893195  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2643 18:54:00.898247  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2644 18:54:00.904344  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2645 18:54:00.909179  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2646 18:54:00.918915  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2647 18:54:00.925157  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2648 18:54:00.930039  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2649 18:54:00.934724  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2650 18:54:00.939705  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2651 18:54:00.945845  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2652 18:54:00.950735  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2653 18:54:00.960635  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2654 18:54:00.966632  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2655 18:54:00.970393  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2656 18:54:00.976359  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2657 18:54:00.981402  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2658 18:54:00.987589  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2659 18:54:00.992530  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2660 18:54:00.997124  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2661 18:54:01.002214  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2662 18:54:01.008324  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2663 18:54:01.013094  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2664 18:54:01.017957  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2665 18:54:01.029159  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2666 18:54:01.029544  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2667 18:54:01.038658  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2668 18:54:01.039042  dt_test_unprobed_devices_sh_opp-table skip
 2669 18:54:01.043694  dt_test_unprobed_devices_sh_soc skip
 2670 18:54:01.049926  dt_test_unprobed_devices_sh_sound pass
 2671 18:54:01.054747  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2672 18:54:01.059532  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2673 18:54:01.069573  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2674 18:54:01.069983  dt_test_unprobed_devices_sh fail
 2675 18:54:01.075069  + ../../utils/send-to-lava.sh ./output/result.txt
 2676 18:54:01.139440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2677 18:54:01.140470  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2679 18:54:01.347423  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2680 18:54:01.348051  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2682 18:54:01.599984  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2683 18:54:01.600605  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2685 18:54:01.777607  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2686 18:54:01.778263  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2688 18:54:01.964768  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2689 18:54:01.965390  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2691 18:54:02.145890  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2692 18:54:02.146511  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2694 18:54:02.361758  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2695 18:54:02.362407  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2697 18:54:02.551777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2698 18:54:02.552396  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2700 18:54:02.759775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2701 18:54:02.760394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2703 18:54:02.976689  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2704 18:54:02.977314  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2706 18:54:03.170267  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2707 18:54:03.170904  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2709 18:54:03.431483  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2710 18:54:03.432121  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2712 18:54:03.642388  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2713 18:54:03.642923  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2715 18:54:03.824742  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2716 18:54:03.825365  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2718 18:54:03.990126  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2719 18:54:03.990745  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2721 18:54:04.171617  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2722 18:54:04.172234  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2724 18:54:04.360251  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2725 18:54:04.360873  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2727 18:54:04.543804  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2728 18:54:04.544429  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2730 18:54:04.726465  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2731 18:54:04.727089  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2733 18:54:04.902891  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2734 18:54:04.903513  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2736 18:54:05.075907  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2737 18:54:05.076530  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2739 18:54:05.253353  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2740 18:54:05.253973  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2742 18:54:05.437911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2743 18:54:05.438530  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2745 18:54:05.614363  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2746 18:54:05.614987  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2748 18:54:05.797106  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2749 18:54:05.797729  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2751 18:54:05.975540  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2752 18:54:05.976163  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2754 18:54:06.203229  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2755 18:54:06.203851  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2757 18:54:06.394303  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2758 18:54:06.394926  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2760 18:54:06.579051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2761 18:54:06.579676  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2763 18:54:06.763786  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2764 18:54:06.764416  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2766 18:54:06.954920  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2767 18:54:06.955548  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2769 18:54:07.173438  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2770 18:54:07.174088  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2772 18:54:07.362241  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2773 18:54:07.362871  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2775 18:54:07.538655  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2776 18:54:07.539278  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2778 18:54:07.714823  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2779 18:54:07.715449  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2781 18:54:07.930315  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2782 18:54:07.930938  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2784 18:54:08.105537  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2785 18:54:08.106187  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2787 18:54:08.289143  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2788 18:54:08.289769  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2790 18:54:08.471751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2791 18:54:08.472378  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2793 18:54:08.650369  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2794 18:54:08.650991  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2796 18:54:08.823654  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2797 18:54:08.824280  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2799 18:54:09.007367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2800 18:54:09.007993  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2802 18:54:09.181703  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2803 18:54:09.182353  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2805 18:54:09.383606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2806 18:54:09.384228  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2808 18:54:09.555674  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2809 18:54:09.556296  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2811 18:54:09.749006  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2812 18:54:09.749629  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2814 18:54:09.925609  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2815 18:54:09.926262  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2817 18:54:10.107177  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2818 18:54:10.107799  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2820 18:54:10.281568  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2821 18:54:10.282212  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2823 18:54:10.489671  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2824 18:54:10.490317  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2826 18:54:10.673588  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2827 18:54:10.674240  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2829 18:54:10.874317  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2830 18:54:10.874940  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2832 18:54:11.058336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2833 18:54:11.058956  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2835 18:54:11.250665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2836 18:54:11.251286  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2838 18:54:11.961141  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2839 18:54:11.961887  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2841 18:54:12.133497  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2842 18:54:12.134157  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2844 18:54:12.322587  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2845 18:54:12.323210  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2847 18:54:12.516986  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2848 18:54:12.517613  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2850 18:54:12.724967  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2851 18:54:12.725595  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2853 18:54:12.924619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2854 18:54:12.925247  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2856 18:54:13.104127  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2857 18:54:13.104751  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2859 18:54:13.281626  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2860 18:54:13.282285  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2862 18:54:13.465328  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2863 18:54:13.465953  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2865 18:54:13.689049  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2866 18:54:13.689673  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2868 18:54:13.867520  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2869 18:54:13.868148  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2871 18:54:14.053327  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2872 18:54:14.053890  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2874 18:54:14.224363  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2875 18:54:14.224990  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2877 18:54:14.402855  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2878 18:54:14.403494  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2880 18:54:14.573981  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2881 18:54:14.574625  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2883 18:54:14.785015  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2884 18:54:14.785645  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2886 18:54:14.973136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2887 18:54:14.973768  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2889 18:54:15.138130  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2890 18:54:15.138773  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2892 18:54:15.320036  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2893 18:54:15.320672  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2895 18:54:15.521794  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2896 18:54:15.522456  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2898 18:54:15.702333  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2899 18:54:15.702964  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2901 18:54:15.892579  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2902 18:54:15.893217  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2904 18:54:16.084667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2905 18:54:16.085306  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2907 18:54:16.268673  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2908 18:54:16.269304  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2910 18:54:16.431457  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2911 18:54:16.432091  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2913 18:54:16.609190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2914 18:54:16.609840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2916 18:54:16.794053  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2917 18:54:16.794673  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2919 18:54:16.993604  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2920 18:54:16.994281  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2922 18:54:17.193299  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2923 18:54:17.193898  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2925 18:54:17.425324  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2926 18:54:17.425949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2928 18:54:17.602670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2929 18:54:17.603291  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2931 18:54:17.785417  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2932 18:54:17.786074  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2934 18:54:17.958474  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2935 18:54:17.959098  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2937 18:54:18.125288  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2938 18:54:18.125911  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2940 18:54:18.307137  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2941 18:54:18.307762  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2943 18:54:18.504723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2944 18:54:18.505347  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2946 18:54:18.681519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2947 18:54:18.682172  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2949 18:54:18.862025  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2950 18:54:18.862647  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2952 18:54:19.040594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2953 18:54:19.041221  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2955 18:54:19.224476  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2956 18:54:19.225099  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2958 18:54:19.419159  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2959 18:54:19.419783  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2961 18:54:19.600733  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2962 18:54:19.601353  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2964 18:54:19.788486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2965 18:54:19.789109  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2967 18:54:20.008977  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2968 18:54:20.009601  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2970 18:54:20.228412  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2971 18:54:20.229038  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2973 18:54:20.406605  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2974 18:54:20.407227  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2976 18:54:20.583801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2977 18:54:20.584422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2979 18:54:20.757832  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2980 18:54:20.758467  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2982 18:54:20.939073  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2983 18:54:20.939703  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2985 18:54:21.116394  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2986 18:54:21.117016  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2988 18:54:21.285312  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2989 18:54:21.285899  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 2991 18:54:21.458441  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 2992 18:54:21.459061  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 2994 18:54:21.693682  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 2995 18:54:21.694332  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 2997 18:54:21.872207  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 2998 18:54:21.872838  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 3000 18:54:22.057109  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 3001 18:54:22.057732  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 3003 18:54:22.284310  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 3004 18:54:22.284935  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 3006 18:54:22.480845  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 3007 18:54:22.481467  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 3009 18:54:22.675015  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 3010 18:54:22.675417  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 3012 18:54:22.884348  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 3013 18:54:22.885066  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 3015 18:54:23.097958  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 3016 18:54:23.098593  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 3018 18:54:23.281914  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3019 18:54:23.282541  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3021 18:54:23.470946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3022 18:54:23.471571  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3024 18:54:23.679485  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3025 18:54:23.680112  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3027 18:54:23.851648  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3028 18:54:23.852271  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3030 18:54:24.031328  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3031 18:54:24.031967  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3033 18:54:24.216209  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3034 18:54:24.216719  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3036 18:54:24.405847  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3038 18:54:24.408888  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3039 18:54:24.590226  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3041 18:54:24.593265  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3042 18:54:24.776586  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3044 18:54:24.779604  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3045 18:54:24.955852  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3046 18:54:24.956474  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3048 18:54:25.161733  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3049 18:54:25.162384  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3051 18:54:25.332638  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3052 18:54:25.333260  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3054 18:54:25.522308  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3055 18:54:25.522931  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3057 18:54:25.699648  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3058 18:54:25.700270  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3060 18:54:25.873651  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3061 18:54:25.874305  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3063 18:54:26.060244  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3064 18:54:26.060871  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3066 18:54:26.229185  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3067 18:54:26.229831  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3069 18:54:26.390505  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3070 18:54:26.391127  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3072 18:54:26.561514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3073 18:54:26.562161  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3075 18:54:26.885440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3076 18:54:26.886103  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3078 18:54:27.081490  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3079 18:54:27.082145  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3081 18:54:27.253329  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3082 18:54:27.253952  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3084 18:54:27.435592  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3085 18:54:27.436214  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3087 18:54:27.612992  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 3088 18:54:27.613623  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 3090 18:54:27.808432  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 3091 18:54:27.809060  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 3093 18:54:28.012268  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3094 18:54:28.012898  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3096 18:54:28.188383  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3097 18:54:28.189004  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3099 18:54:28.366912  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3100 18:54:28.367538  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3102 18:54:28.534832  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3103 18:54:28.535460  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3105 18:54:28.706621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3106 18:54:28.707242  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3108 18:54:28.877134  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3109 18:54:28.877761  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3111 18:54:29.104382  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3112 18:54:29.105006  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3114 18:54:29.296836  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3115 18:54:29.297454  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3117 18:54:29.499078  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3118 18:54:29.499698  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3120 18:54:29.703515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3121 18:54:29.704136  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3123 18:54:29.878472  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3124 18:54:29.879091  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3126 18:54:30.052501  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3127 18:54:30.053127  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3129 18:54:30.219103  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3130 18:54:30.219726  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3132 18:54:30.396076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3133 18:54:30.396699  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3135 18:54:30.590073  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3136 18:54:30.590693  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3138 18:54:30.777946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3139 18:54:30.778566  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3141 18:54:30.954220  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3142 18:54:30.954840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3144 18:54:31.133188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3145 18:54:31.133829  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3147 18:54:31.314607  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3148 18:54:31.315222  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3150 18:54:31.490332  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3151 18:54:31.490951  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3153 18:54:31.700083  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3154 18:54:31.700706  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3156 18:54:31.980603  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3157 18:54:31.981314  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3159 18:54:32.171549  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3160 18:54:32.172167  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3162 18:54:32.362205  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3163 18:54:32.362823  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3165 18:54:32.561659  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3166 18:54:32.562325  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3168 18:54:32.739728  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3169 18:54:32.740362  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3171 18:54:32.929474  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3172 18:54:32.930118  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3174 18:54:33.115038  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3175 18:54:33.115683  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3177 18:54:33.299565  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3178 18:54:33.300179  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3180 18:54:33.469117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3181 18:54:33.469732  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3183 18:54:33.645285  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3184 18:54:33.645902  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3186 18:54:33.823527  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3187 18:54:33.824185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3189 18:54:33.998529  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3190 18:54:33.999186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3192 18:54:34.187216  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3193 18:54:34.187836  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3195 18:54:34.360028  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3196 18:54:34.360658  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3198 18:54:34.545729  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3199 18:54:34.546377  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3201 18:54:34.718389  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3202 18:54:34.719004  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3204 18:54:34.889378  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3205 18:54:34.889994  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3207 18:54:35.082394  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3208 18:54:35.083019  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3210 18:54:35.291364  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 3211 18:54:35.291985  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 3213 18:54:35.465655  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 3214 18:54:35.466302  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 3216 18:54:35.647282  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 3217 18:54:35.647899  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 3219 18:54:35.840777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 3220 18:54:35.841396  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 3222 18:54:36.054219  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 3223 18:54:36.054840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 3225 18:54:36.248555  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 3226 18:54:36.249174  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 3228 18:54:36.451071  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 3229 18:54:36.451688  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 3231 18:54:36.623313  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 3232 18:54:36.623935  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 3234 18:54:36.808945  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3235 18:54:36.809561  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3237 18:54:37.020997  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3238 18:54:37.021613  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3240 18:54:37.201384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3241 18:54:37.202000  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3243 18:54:37.394150  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3244 18:54:37.394764  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3246 18:54:37.569187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3247 18:54:37.569827  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3249 18:54:37.743172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3250 18:54:37.743794  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3252 18:54:37.938235  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3253 18:54:37.938849  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3255 18:54:38.150368  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3256 18:54:38.150985  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3258 18:54:38.345436  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3259 18:54:38.346077  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3261 18:54:38.525495  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3262 18:54:38.526137  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3264 18:54:38.725894  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3265 18:54:38.726517  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3267 18:54:38.938851  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3268 18:54:38.939473  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3270 18:54:39.118859  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3271 18:54:39.119487  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3273 18:54:39.327912  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3274 18:54:39.328536  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3276 18:54:39.502622  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3277 18:54:39.503239  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3279 18:54:39.691298  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3280 18:54:39.691915  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3282 18:54:39.879020  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3283 18:54:39.879634  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3285 18:54:40.051809  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3286 18:54:40.052431  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3288 18:54:40.239571  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3289 18:54:40.240185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3291 18:54:40.426202  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3292 18:54:40.426819  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3294 18:54:40.626649  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3295 18:54:40.627263  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3297 18:54:40.826922  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3298 18:54:40.827540  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3300 18:54:41.023119  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3301 18:54:41.023738  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3303 18:54:41.201936  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3304 18:54:41.202554  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3306 18:54:41.412741  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3307 18:54:41.413359  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3309 18:54:41.593802  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3310 18:54:41.594447  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3312 18:54:41.779469  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3313 18:54:41.780093  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3315 18:54:41.956714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3316 18:54:41.957350  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3318 18:54:42.349065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3319 18:54:42.349768  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3321 18:54:42.528217  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3322 18:54:42.528838  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3324 18:54:42.717260  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3325 18:54:42.717897  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3327 18:54:42.887267  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3328 18:54:42.887890  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3330 18:54:43.099417  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3331 18:54:43.100035  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3333 18:54:43.298463  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3334 18:54:43.299081  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3336 18:54:43.494323  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3337 18:54:43.494961  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3339 18:54:43.713972  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3340 18:54:43.714412  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3342 18:54:43.872112  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3343 18:54:43.872825  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3345 18:54:44.039979  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3346 18:54:44.040367  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3348 18:54:44.196656  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3349 18:54:44.197063  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3351 18:54:44.377775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3352 18:54:44.378229  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3354 18:54:44.566551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3355 18:54:44.566968  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3357 18:54:44.759746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3359 18:54:44.763816  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3360 18:54:44.944835  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3361 18:54:44.945509  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3363 18:54:45.162713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3364 18:54:45.163224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3366 18:54:45.339397  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3367 18:54:45.339788  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3369 18:54:45.530190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3370 18:54:45.530884  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3372 18:54:45.709165  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3373 18:54:45.709854  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3375 18:54:45.927025  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3376 18:54:45.927461  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3378 18:54:46.130028  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3379 18:54:46.130430  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3381 18:54:46.316454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3382 18:54:46.317145  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3384 18:54:46.496387  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3385 18:54:46.497056  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3387 18:54:46.706631  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3388 18:54:46.707093  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3390 18:54:46.881551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3391 18:54:46.882236  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3393 18:54:47.064399  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3394 18:54:47.064846  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3396 18:54:47.285611  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3397 18:54:47.286380  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3399 18:54:47.447295  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3400 18:54:47.447674  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3402 18:54:47.623072  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3403 18:54:47.623507  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3405 18:54:47.817841  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3406 18:54:47.818400  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3408 18:54:47.990283  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3409 18:54:47.990744  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3411 18:54:48.178743  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3412 18:54:48.179149  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3414 18:54:48.379825  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3415 18:54:48.380534  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3417 18:54:48.560733  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3418 18:54:48.561168  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3420 18:54:48.725998  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3421 18:54:48.726419  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3423 18:54:48.892281  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3424 18:54:48.892723  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3426 18:54:49.058737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3427 18:54:49.059432  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3429 18:54:49.226869  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3430 18:54:49.227297  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3432 18:54:49.408627  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3433 18:54:49.409040  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3435 18:54:49.575401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3436 18:54:49.575811  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3438 18:54:49.755395  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3439 18:54:49.756081  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3441 18:54:49.943568  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3442 18:54:49.944262  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3444 18:54:50.109996  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3445 18:54:50.110684  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3447 18:54:50.307021  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3448 18:54:50.307533  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3450 18:54:50.500154  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3451 18:54:50.500431  + set +x
 3452 18:54:50.500862  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3454 18:54:50.504467  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1206272_1.6.2.4.5>
 3455 18:54:50.504946  Received signal: <ENDRUN> 1_kselftest-dt 1206272_1.6.2.4.5
 3456 18:54:50.505193  Ending use of test pattern.
 3457 18:54:50.505407  Ending test lava.1_kselftest-dt (1206272_1.6.2.4.5), duration 281.47
 3459 18:54:50.563112  <LAVA_TEST_RUNNER EXIT>
 3460 18:54:50.563731  ok: lava_test_shell seems to have completed
 3461 18:54:50.571399  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3462 18:54:50.572852  end: 3.1 lava-test-shell (duration 00:04:43) [common]
 3463 18:54:50.573270  end: 3 lava-test-retry (duration 00:04:43) [common]
 3464 18:54:50.573697  start: 4 finalize (timeout 00:02:13) [common]
 3465 18:54:50.574157  start: 4.1 power-off (timeout 00:00:30) [common]
 3466 18:54:50.574567  Calling: 'drpm' 'lf-bbb' 'off'
 3467 18:54:50.867295  >> OFF

 3468 18:54:50.868387  Returned 0 in 0 seconds
 3469 18:54:50.969197  end: 4.1 power-off (duration 00:00:00) [common]
 3471 18:54:50.969962  start: 4.2 read-feedback (timeout 00:02:13) [common]
 3472 18:54:50.970510  Listened to connection for namespace 'common' for up to 1s
 3473 18:54:50.970978  Listened to connection for namespace 'common' for up to 1s
 3474 18:54:51.970779  Finalising connection for namespace 'common'
 3475 18:54:51.971376  Disconnecting from shell: Finalise
 3476 18:54:51.971761  / # 
 3477 18:54:52.072432  end: 4.2 read-feedback (duration 00:00:01) [common]
 3478 18:54:52.072759  end: 4 finalize (duration 00:00:01) [common]
 3479 18:54:52.073081  Cleaning after the job
 3480 18:54:52.073381  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/ramdisk
 3481 18:54:52.077015  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/kernel
 3482 18:54:52.080031  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/dtb
 3483 18:54:52.080495  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/nfsrootfs
 3484 18:54:52.175859  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1206272/tftp-deploy-q3rg7qgn/modules
 3485 18:54:52.180465  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1206272
 3486 18:54:53.305714  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1206272
 3487 18:54:53.306289  Job finished correctly