Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 23:56:55.954802 lava-dispatcher, installed at version: 2024.01
2 23:56:55.956440 start: 0 validate
3 23:56:55.956994 Start time: 2024-10-25 23:56:55.956963+00:00 (UTC)
4 23:56:55.957586 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:56:55.958205 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 23:56:56.006527 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:56:56.007272 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc4-256-gc71f8fb4dc91%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 23:56:56.036691 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:56:56.037620 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc4-256-gc71f8fb4dc91%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 23:56:56.070217 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:56:56.070897 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 23:56:56.100769 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:56:56.101297 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc4-256-gc71f8fb4dc91%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 23:56:56.141216 validate duration: 0.18
16 23:56:56.142135 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:56:56.142460 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:56:56.142751 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:56:56.143359 Not decompressing ramdisk as can be used compressed.
20 23:56:56.143807 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 23:56:56.144095 saving as /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/ramdisk/initrd.cpio.gz
22 23:56:56.144398 total size: 4775763 (4 MB)
23 23:56:56.186624 progress 0 % (0 MB)
24 23:56:56.190475 progress 5 % (0 MB)
25 23:56:56.194153 progress 10 % (0 MB)
26 23:56:56.197739 progress 15 % (0 MB)
27 23:56:56.201997 progress 20 % (0 MB)
28 23:56:56.205610 progress 25 % (1 MB)
29 23:56:56.209123 progress 30 % (1 MB)
30 23:56:56.213141 progress 35 % (1 MB)
31 23:56:56.216652 progress 40 % (1 MB)
32 23:56:56.220131 progress 45 % (2 MB)
33 23:56:56.223502 progress 50 % (2 MB)
34 23:56:56.227438 progress 55 % (2 MB)
35 23:56:56.230868 progress 60 % (2 MB)
36 23:56:56.234302 progress 65 % (2 MB)
37 23:56:56.238093 progress 70 % (3 MB)
38 23:56:56.241416 progress 75 % (3 MB)
39 23:56:56.244959 progress 80 % (3 MB)
40 23:56:56.248467 progress 85 % (3 MB)
41 23:56:56.252379 progress 90 % (4 MB)
42 23:56:56.255418 progress 95 % (4 MB)
43 23:56:56.258415 progress 100 % (4 MB)
44 23:56:56.259139 4 MB downloaded in 0.11 s (39.70 MB/s)
45 23:56:56.259720 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:56:56.260690 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:56:56.261004 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:56:56.261290 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:56:56.261797 downloading http://storage.kernelci.org/mainline/master/v6.12-rc4-256-gc71f8fb4dc91/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 23:56:56.262070 saving as /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/kernel/zImage
52 23:56:56.262290 total size: 12046848 (11 MB)
53 23:56:56.262516 No compression specified
54 23:56:56.300762 progress 0 % (0 MB)
55 23:56:56.308758 progress 5 % (0 MB)
56 23:56:56.316901 progress 10 % (1 MB)
57 23:56:56.325201 progress 15 % (1 MB)
58 23:56:56.333322 progress 20 % (2 MB)
59 23:56:56.341147 progress 25 % (2 MB)
60 23:56:56.349494 progress 30 % (3 MB)
61 23:56:56.357577 progress 35 % (4 MB)
62 23:56:56.365777 progress 40 % (4 MB)
63 23:56:56.373731 progress 45 % (5 MB)
64 23:56:56.381656 progress 50 % (5 MB)
65 23:56:56.390008 progress 55 % (6 MB)
66 23:56:56.397978 progress 60 % (6 MB)
67 23:56:56.406235 progress 65 % (7 MB)
68 23:56:56.415019 progress 70 % (8 MB)
69 23:56:56.423121 progress 75 % (8 MB)
70 23:56:56.431398 progress 80 % (9 MB)
71 23:56:56.439549 progress 85 % (9 MB)
72 23:56:56.447369 progress 90 % (10 MB)
73 23:56:56.455544 progress 95 % (10 MB)
74 23:56:56.462782 progress 100 % (11 MB)
75 23:56:56.463441 11 MB downloaded in 0.20 s (57.12 MB/s)
76 23:56:56.463939 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:56:56.464835 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:56:56.465138 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:56:56.465420 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:56:56.466286 downloading http://storage.kernelci.org/mainline/master/v6.12-rc4-256-gc71f8fb4dc91/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 23:56:56.466589 saving as /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/dtb/am335x-boneblack.dtb
83 23:56:56.466811 total size: 70568 (0 MB)
84 23:56:56.467032 No compression specified
85 23:56:56.500976 progress 46 % (0 MB)
86 23:56:56.501843 progress 92 % (0 MB)
87 23:56:56.502526 progress 100 % (0 MB)
88 23:56:56.502930 0 MB downloaded in 0.04 s (1.86 MB/s)
89 23:56:56.503402 end: 1.3.1 http-download (duration 00:00:00) [common]
91 23:56:56.504275 end: 1.3 download-retry (duration 00:00:00) [common]
92 23:56:56.504563 start: 1.4 download-retry (timeout 00:10:00) [common]
93 23:56:56.504842 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 23:56:56.505351 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 23:56:56.505618 saving as /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/nfsrootfs/full.rootfs.tar
96 23:56:56.505833 total size: 117747780 (112 MB)
97 23:56:56.506052 Using unxz to decompress xz
98 23:56:56.542786 progress 0 % (0 MB)
99 23:56:57.268497 progress 5 % (5 MB)
100 23:56:58.027833 progress 10 % (11 MB)
101 23:56:58.801340 progress 15 % (16 MB)
102 23:56:59.520002 progress 20 % (22 MB)
103 23:57:00.096527 progress 25 % (28 MB)
104 23:57:00.899152 progress 30 % (33 MB)
105 23:57:01.698082 progress 35 % (39 MB)
106 23:57:02.054071 progress 40 % (44 MB)
107 23:57:02.424935 progress 45 % (50 MB)
108 23:57:03.079777 progress 50 % (56 MB)
109 23:57:03.891283 progress 55 % (61 MB)
110 23:57:04.620116 progress 60 % (67 MB)
111 23:57:05.333871 progress 65 % (73 MB)
112 23:57:06.085334 progress 70 % (78 MB)
113 23:57:06.837795 progress 75 % (84 MB)
114 23:57:07.632931 progress 80 % (89 MB)
115 23:57:08.354650 progress 85 % (95 MB)
116 23:57:09.147919 progress 90 % (101 MB)
117 23:57:09.949198 progress 95 % (106 MB)
118 23:57:10.779313 progress 100 % (112 MB)
119 23:57:10.792404 112 MB downloaded in 14.29 s (7.86 MB/s)
120 23:57:10.793480 end: 1.4.1 http-download (duration 00:00:14) [common]
122 23:57:10.795224 end: 1.4 download-retry (duration 00:00:14) [common]
123 23:57:10.795832 start: 1.5 download-retry (timeout 00:09:45) [common]
124 23:57:10.796494 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 23:57:10.797353 downloading http://storage.kernelci.org/mainline/master/v6.12-rc4-256-gc71f8fb4dc91/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 23:57:10.797838 saving as /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/modules/modules.tar
127 23:57:10.798248 total size: 6905980 (6 MB)
128 23:57:10.798668 Using unxz to decompress xz
129 23:57:10.842837 progress 0 % (0 MB)
130 23:57:10.878527 progress 5 % (0 MB)
131 23:57:10.927404 progress 10 % (0 MB)
132 23:57:10.974444 progress 15 % (1 MB)
133 23:57:11.026901 progress 20 % (1 MB)
134 23:57:11.072881 progress 25 % (1 MB)
135 23:57:11.126606 progress 30 % (2 MB)
136 23:57:11.173143 progress 35 % (2 MB)
137 23:57:11.224537 progress 40 % (2 MB)
138 23:57:11.280107 progress 45 % (2 MB)
139 23:57:11.338430 progress 50 % (3 MB)
140 23:57:11.390248 progress 55 % (3 MB)
141 23:57:11.447849 progress 60 % (3 MB)
142 23:57:11.492778 progress 65 % (4 MB)
143 23:57:11.539342 progress 70 % (4 MB)
144 23:57:11.598325 progress 75 % (4 MB)
145 23:57:11.655521 progress 80 % (5 MB)
146 23:57:11.710403 progress 85 % (5 MB)
147 23:57:11.759782 progress 90 % (5 MB)
148 23:57:11.815759 progress 95 % (6 MB)
149 23:57:11.860197 progress 100 % (6 MB)
150 23:57:11.874620 6 MB downloaded in 1.08 s (6.12 MB/s)
151 23:57:11.875467 end: 1.5.1 http-download (duration 00:00:01) [common]
153 23:57:11.877097 end: 1.5 download-retry (duration 00:00:01) [common]
154 23:57:11.877614 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 23:57:11.878127 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 23:57:28.489510 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5
157 23:57:28.490116 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 23:57:28.490435 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 23:57:28.491096 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4
160 23:57:28.491623 makedir: /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin
161 23:57:28.492070 makedir: /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/tests
162 23:57:28.492476 makedir: /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/results
163 23:57:28.492927 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-add-keys
164 23:57:28.493562 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-add-sources
165 23:57:28.494348 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-background-process-start
166 23:57:28.494903 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-background-process-stop
167 23:57:28.495449 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-common-functions
168 23:57:28.496002 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-echo-ipv4
169 23:57:28.496627 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-install-packages
170 23:57:28.497300 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-installed-packages
171 23:57:28.497856 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-os-build
172 23:57:28.498351 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-probe-channel
173 23:57:28.498853 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-probe-ip
174 23:57:28.499361 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-target-ip
175 23:57:28.500100 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-target-mac
176 23:57:28.500621 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-target-storage
177 23:57:28.501185 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-case
178 23:57:28.501770 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-event
179 23:57:28.502286 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-feedback
180 23:57:28.502805 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-raise
181 23:57:28.503331 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-reference
182 23:57:28.503859 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-runner
183 23:57:28.504476 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-set
184 23:57:28.505015 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-test-shell
185 23:57:28.505551 Updating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-add-keys (debian)
186 23:57:28.506177 Updating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-add-sources (debian)
187 23:57:28.506721 Updating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-install-packages (debian)
188 23:57:28.507322 Updating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-installed-packages (debian)
189 23:57:28.507890 Updating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/bin/lava-os-build (debian)
190 23:57:28.508401 Creating /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/environment
191 23:57:28.508803 LAVA metadata
192 23:57:28.509080 - LAVA_JOB_ID=892286
193 23:57:28.509298 - LAVA_DISPATCHER_IP=192.168.6.2
194 23:57:28.509682 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 23:57:28.510704 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 23:57:28.511044 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 23:57:28.511254 skipped lava-vland-overlay
198 23:57:28.511496 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 23:57:28.511752 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 23:57:28.511971 skipped lava-multinode-overlay
201 23:57:28.512250 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 23:57:28.512509 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 23:57:28.512767 Loading test definitions
204 23:57:28.513047 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 23:57:28.513267 Using /lava-892286 at stage 0
206 23:57:28.514625 uuid=892286_1.6.2.4.1 testdef=None
207 23:57:28.514959 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 23:57:28.515226 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 23:57:28.516891 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 23:57:28.517695 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 23:57:28.519748 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 23:57:28.520628 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 23:57:28.522683 runner path: /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/0/tests/0_timesync-off test_uuid 892286_1.6.2.4.1
216 23:57:28.523300 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 23:57:28.524171 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 23:57:28.524405 Using /lava-892286 at stage 0
220 23:57:28.524777 Fetching tests from https://github.com/kernelci/test-definitions.git
221 23:57:28.525076 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/0/tests/1_kselftest-dt'
222 23:57:31.989252 Running '/usr/bin/git checkout kernelci.org
223 23:57:32.439430 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 23:57:32.440925 uuid=892286_1.6.2.4.5 testdef=None
225 23:57:32.441279 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 23:57:32.442047 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 23:57:32.444931 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 23:57:32.445763 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 23:57:32.449538 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 23:57:32.450411 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 23:57:32.454106 runner path: /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/0/tests/1_kselftest-dt test_uuid 892286_1.6.2.4.5
235 23:57:32.454403 BOARD='beaglebone-black'
236 23:57:32.454617 BRANCH='mainline'
237 23:57:32.454819 SKIPFILE='/dev/null'
238 23:57:32.455019 SKIP_INSTALL='True'
239 23:57:32.455214 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc4-256-gc71f8fb4dc91/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 23:57:32.455415 TST_CASENAME=''
241 23:57:32.455613 TST_CMDFILES='dt'
242 23:57:32.456213 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 23:57:32.457024 Creating lava-test-runner.conf files
245 23:57:32.457236 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/892286/lava-overlay-f_480ix4/lava-892286/0 for stage 0
246 23:57:32.457682 - 0_timesync-off
247 23:57:32.457946 - 1_kselftest-dt
248 23:57:32.458298 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 23:57:32.458590 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 23:57:55.930585 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 23:57:55.931039 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 23:57:55.931332 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 23:57:55.931641 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 23:57:55.931936 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 23:57:56.309951 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 23:57:56.310419 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 23:57:56.310693 extracting modules file /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5
258 23:57:57.211286 extracting modules file /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/892286/extract-overlay-ramdisk-t6gns1u_/ramdisk
259 23:57:58.157008 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 23:57:58.157489 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 23:57:58.157785 [common] Applying overlay to NFS
262 23:57:58.158014 [common] Applying overlay /var/lib/lava/dispatcher/tmp/892286/compress-overlay-14c0_hko/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5
263 23:58:00.909716 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 23:58:00.910202 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 23:58:00.910502 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 23:58:00.910794 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 23:58:00.911060 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 23:58:00.911332 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 23:58:00.911597 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 23:58:00.911866 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 23:58:00.912176 Building ramdisk /var/lib/lava/dispatcher/tmp/892286/extract-overlay-ramdisk-t6gns1u_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/892286/extract-overlay-ramdisk-t6gns1u_/ramdisk
272 23:58:01.972610 >> 79007 blocks
273 23:58:07.204306 Adding RAMdisk u-boot header.
274 23:58:07.204800 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/892286/extract-overlay-ramdisk-t6gns1u_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/892286/extract-overlay-ramdisk-t6gns1u_/ramdisk.cpio.gz.uboot
275 23:58:07.375314 output: Image Name:
276 23:58:07.375749 output: Created: Fri Oct 25 23:58:07 2024
277 23:58:07.376275 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 23:58:07.376747 output: Data Size: 15351701 Bytes = 14991.90 KiB = 14.64 MiB
279 23:58:07.377274 output: Load Address: 00000000
280 23:58:07.377750 output: Entry Point: 00000000
281 23:58:07.378200 output:
282 23:58:07.379381 rename /var/lib/lava/dispatcher/tmp/892286/extract-overlay-ramdisk-t6gns1u_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot
283 23:58:07.380240 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 23:58:07.380872 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 23:58:07.381473 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 23:58:07.381985 No LXC device requested
287 23:58:07.382551 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 23:58:07.383134 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 23:58:07.383693 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 23:58:07.384202 Checking files for TFTP limit of 4294967296 bytes.
291 23:58:07.387391 end: 1 tftp-deploy (duration 00:01:11) [common]
292 23:58:07.388137 start: 2 uboot-action (timeout 00:05:00) [common]
293 23:58:07.388762 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 23:58:07.389336 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 23:58:07.389914 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 23:58:07.390765 substitutions:
297 23:58:07.391253 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 23:58:07.391718 - {DTB_ADDR}: 0x88000000
299 23:58:07.392216 - {DTB}: 892286/tftp-deploy-52zbqtjl/dtb/am335x-boneblack.dtb
300 23:58:07.392672 - {INITRD}: 892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot
301 23:58:07.393121 - {KERNEL_ADDR}: 0x82000000
302 23:58:07.393562 - {KERNEL}: 892286/tftp-deploy-52zbqtjl/kernel/zImage
303 23:58:07.394005 - {LAVA_MAC}: None
304 23:58:07.394522 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5
305 23:58:07.394985 - {NFS_SERVER_IP}: 192.168.6.2
306 23:58:07.395431 - {PRESEED_CONFIG}: None
307 23:58:07.395872 - {PRESEED_LOCAL}: None
308 23:58:07.396354 - {RAMDISK_ADDR}: 0x83000000
309 23:58:07.396801 - {RAMDISK}: 892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot
310 23:58:07.397247 - {ROOT_PART}: None
311 23:58:07.397686 - {ROOT}: None
312 23:58:07.398123 - {SERVER_IP}: 192.168.6.2
313 23:58:07.398555 - {TEE_ADDR}: 0x83000000
314 23:58:07.398988 - {TEE}: None
315 23:58:07.399420 Parsed boot commands:
316 23:58:07.399846 - setenv autoload no
317 23:58:07.400334 - setenv initrd_high 0xffffffff
318 23:58:07.400777 - setenv fdt_high 0xffffffff
319 23:58:07.401209 - dhcp
320 23:58:07.401640 - setenv serverip 192.168.6.2
321 23:58:07.402071 - tftp 0x82000000 892286/tftp-deploy-52zbqtjl/kernel/zImage
322 23:58:07.402507 - tftp 0x83000000 892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot
323 23:58:07.402940 - setenv initrd_size ${filesize}
324 23:58:07.403371 - tftp 0x88000000 892286/tftp-deploy-52zbqtjl/dtb/am335x-boneblack.dtb
325 23:58:07.403803 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 23:58:07.404286 - bootz 0x82000000 0x83000000 0x88000000
327 23:58:07.404879 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 23:58:07.406575 start: 2.3 connect-device (timeout 00:05:00) [common]
330 23:58:07.407068 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 23:58:07.424852 Setting prompt string to ['lava-test: # ']
332 23:58:07.426579 end: 2.3 connect-device (duration 00:00:00) [common]
333 23:58:07.427287 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 23:58:07.427919 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 23:58:07.428599 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 23:58:07.430168 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 23:58:07.471431 >> OK - accepted request
338 23:58:07.473760 Returned 0 in 0 seconds
339 23:58:07.574788 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 23:58:07.576698 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 23:58:07.577360 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 23:58:07.577945 Setting prompt string to ['Hit any key to stop autoboot']
344 23:58:07.578462 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 23:58:07.580220 Trying 192.168.56.21...
346 23:58:07.580764 Connected to conserv1.
347 23:58:07.581237 Escape character is '^]'.
348 23:58:07.581693
349 23:58:07.582164 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 23:58:07.582635
351 23:58:15.242145
352 23:58:15.242571 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 23:58:15.247350 Trying to boot from MMC1
354 23:58:15.823192
355 23:58:15.823778
356 23:58:15.824062 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 23:58:15.824287
358 23:58:15.828536 CPU : AM335X-GP rev 2.1
359 23:58:15.828993 Model: TI AM335x BeagleBone Black
360 23:58:15.832768 DRAM: 512 MiB
361 23:58:15.916081 Core: 160 devices, 18 uclasses, devicetree: separate
362 23:58:15.925637 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 23:58:19.295870 7[r[999;999H[6n8NAND:
364 23:58:19.296377 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 23:58:19.303296 Trying to boot from MMC1
366 23:58:19.873147
367 23:58:19.873606
368 23:58:19.873842 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 23:58:19.874059
370 23:58:19.878682 CPU : AM335X-GP rev 2.1
371 23:58:19.879066 Model: TI AM335x BeagleBone Black
372 23:58:19.882870 DRAM: 512 MiB
373 23:58:19.965461 Core: 160 devices, 18 uclasses, devicetree: separate
374 23:58:19.975182 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 23:58:21.992477 7[r[999;999H[6n8NAND:
376 23:58:21.992905 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 23:58:21.997881 Trying to boot from MMC1
378 23:58:22.569455
379 23:58:22.570113
380 23:58:22.570576 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 23:58:22.571025
382 23:58:22.575031 CPU : AM335X-GP rev 2.1
383 23:58:22.575521 Model: TI AM335x BeagleBone Black
384 23:58:22.579044 DRAM: 512 MiB
385 23:58:22.661894 Core: 160 devices, 18 uclasses, devicetree: separate
386 23:58:22.671461 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 23:58:23.176614 7[r[999;999H[6n8NAND: 0 MiB
388 23:58:23.186901 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 23:58:23.259679 Loading Environment from FAT... Unable to use mmc 0:1...
390 23:58:23.281053 <ethaddr> not set. Validating first E-fuse MAC
391 23:58:23.311444 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 23:58:23.370294 Hit any key to stop autoboot: 2
394 23:58:23.371254 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 23:58:23.371946 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 23:58:23.372555 Setting prompt string to ['=>']
397 23:58:23.373131 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 23:58:23.379864 0
399 23:58:23.380884 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 23:58:23.381434 Sending with 10 millisecond of delay
402 23:58:24.517149 => setenv autoload no
403 23:58:24.527750 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 23:58:24.530409 setenv autoload no
405 23:58:24.530904 Sending with 10 millisecond of delay
407 23:58:26.327967 => setenv initrd_high 0xffffffff
408 23:58:26.338738 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 23:58:26.339289 setenv initrd_high 0xffffffff
410 23:58:26.339773 Sending with 10 millisecond of delay
412 23:58:27.957461 => setenv fdt_high 0xffffffff
413 23:58:27.968277 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 23:58:27.969157 setenv fdt_high 0xffffffff
415 23:58:27.969867 Sending with 10 millisecond of delay
417 23:58:28.261809 => dhcp
418 23:58:28.272593 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 23:58:28.273435 dhcp
420 23:58:28.274166 link up on port 0, speed 100, full duplex
421 23:58:28.274596 BOOTP broadcast 1
422 23:58:28.306824 DHCP client bound to address 192.168.6.12 (29 ms)
423 23:58:28.307633 Sending with 10 millisecond of delay
425 23:58:29.984435 => setenv serverip 192.168.6.2
426 23:58:29.994991 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 23:58:29.995520 setenv serverip 192.168.6.2
428 23:58:29.996010 Sending with 10 millisecond of delay
430 23:58:33.476893 => tftp 0x82000000 892286/tftp-deploy-52zbqtjl/kernel/zImage
431 23:58:33.487447 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 23:58:33.488019 tftp 0x82000000 892286/tftp-deploy-52zbqtjl/kernel/zImage
433 23:58:33.488280 link up on port 0, speed 100, full duplex
434 23:58:33.492167 Using ethernet@4a100000 device
435 23:58:33.497756 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 23:58:33.504347 Filename '892286/tftp-deploy-52zbqtjl/kernel/zImage'.
437 23:58:33.504660 Load address: 0x82000000
438 23:58:35.975313 Loading: *################################################## 11.5 MiB
439 23:58:35.976033 4.7 MiB/s
440 23:58:35.976571 done
441 23:58:35.978649 Bytes transferred = 12046848 (b7d200 hex)
442 23:58:35.979481 Sending with 10 millisecond of delay
444 23:58:40.425661 => tftp 0x83000000 892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot
445 23:58:40.436245 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 23:58:40.437158 tftp 0x83000000 892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot
447 23:58:40.437649 link up on port 0, speed 100, full duplex
448 23:58:40.441281 Using ethernet@4a100000 device
449 23:58:40.446879 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 23:58:40.455036 Filename '892286/tftp-deploy-52zbqtjl/ramdisk/ramdisk.cpio.gz.uboot'.
451 23:58:40.455530 Load address: 0x83000000
452 23:58:43.675351 Loading: *################################################## 14.6 MiB
453 23:58:43.675773 4.5 MiB/s
454 23:58:43.676058 done
455 23:58:43.679339 Bytes transferred = 15351765 (ea3fd5 hex)
456 23:58:43.679907 Sending with 10 millisecond of delay
458 23:58:45.537230 => setenv initrd_size ${filesize}
459 23:58:45.547768 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 23:58:45.548324 setenv initrd_size ${filesize}
461 23:58:45.548871 Sending with 10 millisecond of delay
463 23:58:49.694421 => tftp 0x88000000 892286/tftp-deploy-52zbqtjl/dtb/am335x-boneblack.dtb
464 23:58:49.705072 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 23:58:49.705791 tftp 0x88000000 892286/tftp-deploy-52zbqtjl/dtb/am335x-boneblack.dtb
466 23:58:49.706106 link up on port 0, speed 100, full duplex
467 23:58:49.709760 Using ethernet@4a100000 device
468 23:58:49.715258 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 23:58:49.723507 Filename '892286/tftp-deploy-52zbqtjl/dtb/am335x-boneblack.dtb'.
470 23:58:49.723963 Load address: 0x88000000
471 23:58:49.740523 Loading: *################################################## 68.9 KiB
472 23:58:49.750196 3.4 MiB/s
473 23:58:49.750640 done
474 23:58:49.750894 Bytes transferred = 70568 (113a8 hex)
475 23:58:49.751548 Sending with 10 millisecond of delay
477 23:59:02.931327 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 23:59:02.942090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 23:59:02.942936 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 23:59:02.943640 Sending with 10 millisecond of delay
482 23:59:05.282888 => bootz 0x82000000 0x83000000 0x88000000
483 23:59:05.293646 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 23:59:05.294178 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 23:59:05.295168 bootz 0x82000000 0x83000000 0x88000000
486 23:59:05.295619 Kernel image @ 0x82000000 [ 0x000000 - 0xb7d200 ]
487 23:59:05.296160 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 23:59:05.301043 Image Name:
489 23:59:05.301484 Created: 2024-10-25 23:58:07 UTC
490 23:59:05.304442 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 23:59:05.310046 Data Size: 15351701 Bytes = 14.6 MiB
492 23:59:05.318368 Load Address: 00000000
493 23:59:05.318829 Entry Point: 00000000
494 23:59:05.493139 Verifying Checksum ... OK
495 23:59:05.493750 ## Flattened Device Tree blob at 88000000
496 23:59:05.499569 Booting using the fdt blob at 0x88000000
497 23:59:05.504432 Using Device Tree in place at 88000000, end 880143a7
498 23:59:05.518045
499 23:59:05.518560 Starting kernel ...
500 23:59:05.518988
501 23:59:05.519872 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 23:59:05.520497 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 23:59:05.520977 Setting prompt string to ['Linux version [0-9]']
504 23:59:05.521439 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 23:59:05.521898 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 23:59:06.408899 [ 0.000000] Booting Linux on physical CPU 0x0
507 23:59:06.414811 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 23:59:06.415363 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 23:59:06.415859 Setting prompt string to []
510 23:59:06.416425 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 23:59:06.416895 Using line separator: #'\n'#
512 23:59:06.417303 No login prompt set.
513 23:59:06.417729 Parsing kernel messages
514 23:59:06.418121 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 23:59:06.418881 [login-action] Waiting for messages, (timeout 00:04:01)
516 23:59:06.419326 Waiting using forced prompt support (timeout 00:02:00)
517 23:59:06.425777 [ 0.000000] Linux version 6.12.0-rc4 (KernelCI@build-j352659-arm-clang-15-multi-v7-defconfig-tvx7w) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Fri Oct 25 23:08:25 UTC 2024
518 23:59:06.431522 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 23:59:06.442955 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 23:59:06.448721 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 23:59:06.454494 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 23:59:06.460118 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 23:59:06.466929 [ 0.000000] Memory policy: Data cache writeback
524 23:59:06.467359 [ 0.000000] efi: UEFI not found.
525 23:59:06.473665 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 23:59:06.480228 [ 0.000000] Zone ranges:
527 23:59:06.485982 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 23:59:06.491796 [ 0.000000] Normal empty
529 23:59:06.492259 [ 0.000000] HighMem empty
530 23:59:06.494540 [ 0.000000] Movable zone start for each node
531 23:59:06.500446 [ 0.000000] Early memory node ranges
532 23:59:06.506346 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 23:59:06.513513 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 23:59:06.532328 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 23:59:06.537445 [ 0.000000] AM335X ES2.1 (sgx neon)
536 23:59:06.549736 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
537 23:59:06.567365 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 23:59:06.579036 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 23:59:06.584750 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 23:59:06.590520 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 23:59:06.599631 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 23:59:06.629721 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 23:59:06.635732 <6>[ 0.000000] trace event string verifier disabled
544 23:59:06.636210 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 23:59:06.643762 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 23:59:06.649448 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 23:59:06.660992 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 23:59:06.665056 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 23:59:06.680018 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 23:59:06.698575 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 23:59:06.704416 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 23:59:06.805238 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 23:59:06.813923 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 23:59:06.826226 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 23:59:06.834010 <6>[ 0.019189] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 23:59:06.844157 <6>[ 0.034217] Console: colour dummy device 80x30
557 23:59:06.850149 Matched prompt #6: WARNING:
558 23:59:06.850651 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 23:59:06.855652 <3>[ 0.039117] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 23:59:06.858382 <3>[ 0.046190] This ensures that you still see kernel messages. Please
561 23:59:06.863581 <3>[ 0.052918] update your kernel commandline.
562 23:59:06.905094 <6>[ 0.057531] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 23:59:06.910901 <6>[ 0.096200] CPU: Testing write buffer coherency: ok
564 23:59:06.916765 <6>[ 0.101566] CPU0: Spectre v2: using BPIALL workaround
565 23:59:06.917237 <6>[ 0.107031] pid_max: default: 32768 minimum: 301
566 23:59:06.928204 <6>[ 0.112222] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 23:59:06.935138 <6>[ 0.120043] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 23:59:06.942307 <6>[ 0.129437] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 23:59:06.949561 <6>[ 0.136472] Setting up static identity map for 0x80300000 - 0x803000ac
570 23:59:06.956060 <6>[ 0.146176] rcu: Hierarchical SRCU implementation.
571 23:59:06.963367 <6>[ 0.151467] rcu: Max phase no-delay instances is 1000.
572 23:59:06.972981 <6>[ 0.162813] EFI services will not be available.
573 23:59:06.978946 <6>[ 0.168093] smp: Bringing up secondary CPUs ...
574 23:59:06.984508 <6>[ 0.173146] smp: Brought up 1 node, 1 CPU
575 23:59:06.990288 <6>[ 0.177545] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 23:59:06.996415 <6>[ 0.184318] CPU: All CPU(s) started in SVC mode.
577 23:59:07.015690 <6>[ 0.189535] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
578 23:59:07.016206 <6>[ 0.205841] devtmpfs: initialized
579 23:59:07.039964 <6>[ 0.223973] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 23:59:07.051469 <6>[ 0.232581] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 23:59:07.056434 <6>[ 0.243048] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 23:59:07.067194 <6>[ 0.255400] pinctrl core: initialized pinctrl subsystem
583 23:59:07.077686 <6>[ 0.266263] DMI not present or invalid.
584 23:59:07.084632 <6>[ 0.272159] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 23:59:07.094673 <6>[ 0.281164] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 23:59:07.109882 <6>[ 0.292764] thermal_sys: Registered thermal governor 'step_wise'
587 23:59:07.110204 <6>[ 0.292943] cpuidle: using governor menu
588 23:59:07.138316 <6>[ 0.328417] No ATAGs?
589 23:59:07.143575 <6>[ 0.331157] hw-breakpoint: debug architecture 0x4 unsupported.
590 23:59:07.154126 <6>[ 0.343280] Serial: AMBA PL011 UART driver
591 23:59:07.185971 <6>[ 0.375970] iommu: Default domain type: Translated
592 23:59:07.195061 <6>[ 0.381322] iommu: DMA domain TLB invalidation policy: strict mode
593 23:59:07.221664 <5>[ 0.410470] SCSI subsystem initialized
594 23:59:07.235526 <6>[ 0.420048] usbcore: registered new interface driver usbfs
595 23:59:07.242500 <6>[ 0.426007] usbcore: registered new interface driver hub
596 23:59:07.242815 <6>[ 0.431846] usbcore: registered new device driver usb
597 23:59:07.249953 <6>[ 0.438388] pps_core: LinuxPPS API ver. 1 registered
598 23:59:07.261368 <6>[ 0.443823] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 23:59:07.264280 <6>[ 0.453530] PTP clock support registered
600 23:59:07.268454 <6>[ 0.457984] EDAC MC: Ver: 3.0.0
601 23:59:07.321230 <6>[ 0.509690] scmi_core: SCMI protocol bus registered
602 23:59:07.327249 <6>[ 0.517865] vgaarb: loaded
603 23:59:07.341308 <6>[ 0.530641] clocksource: Switched to clocksource dmtimer
604 23:59:07.382917 <6>[ 0.569340] NET: Registered PF_INET protocol family
605 23:59:07.392386 <6>[ 0.575060] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 23:59:07.398148 <6>[ 0.584082] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 23:59:07.409588 <6>[ 0.593013] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 23:59:07.415366 <6>[ 0.601275] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 23:59:07.427054 <6>[ 0.609546] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 23:59:07.432773 <6>[ 0.617273] TCP: Hash tables configured (established 4096 bind 4096)
611 23:59:07.438580 <6>[ 0.624189] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 23:59:07.444505 <6>[ 0.631229] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 23:59:07.451106 <6>[ 0.638819] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 23:59:07.533810 <6>[ 0.718166] RPC: Registered named UNIX socket transport module.
615 23:59:07.534399 <6>[ 0.724619] RPC: Registered udp transport module.
616 23:59:07.539511 <6>[ 0.729725] RPC: Registered tcp transport module.
617 23:59:07.548105 <6>[ 0.734849] RPC: Registered tcp-with-tls transport module.
618 23:59:07.554164 <6>[ 0.740773] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 23:59:07.561139 <6>[ 0.747683] PCI: CLS 0 bytes, default 64
620 23:59:07.562376 <5>[ 0.753576] Initialise system trusted keyrings
621 23:59:07.587545 <6>[ 0.774634] Trying to unpack rootfs image as initramfs...
622 23:59:07.656878 <6>[ 0.840768] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 23:59:07.660796 <6>[ 0.848286] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 23:59:07.701994 <5>[ 0.891916] NFS: Registering the id_resolver key type
625 23:59:07.707742 <5>[ 0.897505] Key type id_resolver registered
626 23:59:07.713539 <5>[ 0.902201] Key type id_legacy registered
627 23:59:07.721884 <6>[ 0.906644] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 23:59:07.728801 <6>[ 0.913857] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 23:59:07.811125 <5>[ 1.001137] Key type asymmetric registered
630 23:59:07.816932 <5>[ 1.005666] Asymmetric key parser 'x509' registered
631 23:59:07.828411 <6>[ 1.011220] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 23:59:07.828874 <6>[ 1.019110] io scheduler mq-deadline registered
633 23:59:07.834300 <6>[ 1.024088] io scheduler kyber registered
634 23:59:07.839339 <6>[ 1.028540] io scheduler bfq registered
635 23:59:07.933597 <6>[ 1.120862] ledtrig-cpu: registered to indicate activity on CPUs
636 23:59:08.237434 <6>[ 1.423587] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 23:59:08.270093 <6>[ 1.459646] msm_serial: driver initialized
638 23:59:08.275971 <6>[ 1.464691] SuperH (H)SCI(F) driver initialized
639 23:59:08.281894 <6>[ 1.469809] STMicroelectronics ASC driver initialized
640 23:59:08.287063 <6>[ 1.475477] STM32 USART driver initialized
641 23:59:08.397208 <6>[ 1.586533] brd: module loaded
642 23:59:08.436845 <6>[ 1.627115] loop: module loaded
643 23:59:08.479751 <6>[ 1.668774] CAN device driver interface
644 23:59:08.486486 <6>[ 1.674125] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 23:59:08.492288 <6>[ 1.681244] e1000e: Intel(R) PRO/1000 Network Driver
646 23:59:08.498034 <6>[ 1.686631] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 23:59:08.503716 <6>[ 1.693101] igb: Intel(R) Gigabit Ethernet Network Driver
648 23:59:08.511089 <6>[ 1.698922] igb: Copyright (c) 2007-2014 Intel Corporation.
649 23:59:08.524002 <6>[ 1.708138] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 23:59:08.529629 <6>[ 1.714305] usbcore: registered new interface driver pegasus
651 23:59:08.535432 <6>[ 1.720435] usbcore: registered new interface driver asix
652 23:59:08.541237 <6>[ 1.726336] usbcore: registered new interface driver ax88179_178a
653 23:59:08.546954 <6>[ 1.732931] usbcore: registered new interface driver cdc_ether
654 23:59:08.552723 <6>[ 1.739230] usbcore: registered new interface driver smsc75xx
655 23:59:08.558659 <6>[ 1.745461] usbcore: registered new interface driver smsc95xx
656 23:59:08.564375 <6>[ 1.751706] usbcore: registered new interface driver net1080
657 23:59:08.570167 <6>[ 1.757828] usbcore: registered new interface driver cdc_subset
658 23:59:08.575910 <6>[ 1.764241] usbcore: registered new interface driver zaurus
659 23:59:08.582534 <6>[ 1.770286] usbcore: registered new interface driver cdc_ncm
660 23:59:08.592413 <6>[ 1.779764] usbcore: registered new interface driver usb-storage
661 23:59:08.904056 <6>[ 2.093097] i2c_dev: i2c /dev entries driver
662 23:59:08.970363 <5>[ 2.157110] cpuidle: enable-method property 'ti,am3352' found operations
663 23:59:08.983964 <6>[ 2.166776] sdhci: Secure Digital Host Controller Interface driver
664 23:59:08.984568 <6>[ 2.173552] sdhci: Copyright(c) Pierre Ossman
665 23:59:08.990772 <6>[ 2.179960] Synopsys Designware Multimedia Card Interface Driver
666 23:59:09.000769 <6>[ 2.187917] sdhci-pltfm: SDHCI platform and OF driver helper
667 23:59:09.109285 <6>[ 2.292035] usbcore: registered new interface driver usbhid
668 23:59:09.109911 <6>[ 2.298075] usbhid: USB HID core driver
669 23:59:09.158681 <6>[ 2.347192] NET: Registered PF_INET6 protocol family
670 23:59:09.192488 <6>[ 2.382702] Segment Routing with IPv6
671 23:59:09.198448 <6>[ 2.386851] In-situ OAM (IOAM) with IPv6
672 23:59:09.205227 <6>[ 2.391402] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 23:59:09.212004 <6>[ 2.398707] NET: Registered PF_PACKET protocol family
674 23:59:09.216838 <6>[ 2.404303] can: controller area network core
675 23:59:09.222590 <6>[ 2.409128] NET: Registered PF_CAN protocol family
676 23:59:09.223090 <6>[ 2.414366] can: raw protocol
677 23:59:09.228369 <6>[ 2.417692] can: broadcast manager protocol
678 23:59:09.234882 <6>[ 2.422293] can: netlink gateway - max_hops=1
679 23:59:09.241024 <5>[ 2.427793] Key type dns_resolver registered
680 23:59:09.247360 <6>[ 2.432864] ThumbEE CPU extension supported.
681 23:59:09.247850 <5>[ 2.437557] Registering SWP/SWPB emulation handler
682 23:59:09.257015 <3>[ 2.443263] omap_voltage_late_init: Voltage driver support not added
683 23:59:09.493734 <5>[ 2.681496] Loading compiled-in X.509 certificates
684 23:59:09.613010 <6>[ 2.790199] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 23:59:09.620169 <6>[ 2.806927] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 23:59:09.647006 <3>[ 2.831223] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 23:59:09.841444 <3>[ 3.025622] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 23:59:10.042664 <6>[ 3.231130] OMAP GPIO hardware version 0.1
689 23:59:10.062710 <6>[ 3.250094] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 23:59:10.125950 <4>[ 3.312415] at24 2-0054: supply vcc not found, using dummy regulator
691 23:59:10.159762 <4>[ 3.346086] at24 2-0055: supply vcc not found, using dummy regulator
692 23:59:10.198101 <4>[ 3.384288] at24 2-0056: supply vcc not found, using dummy regulator
693 23:59:10.247222 <4>[ 3.434196] at24 2-0057: supply vcc not found, using dummy regulator
694 23:59:10.286920 <6>[ 3.473968] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 23:59:10.330725 <3>[ 3.513752] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 23:59:10.355693 <6>[ 3.535023] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 23:59:10.377698 <4>[ 3.561661] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 23:59:10.385459 <4>[ 3.570387] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 23:59:10.474743 <6>[ 3.661210] omap_rng 48310000.rng: Random Number Generator ver. 20
700 23:59:10.499046 <5>[ 3.688109] random: crng init done
701 23:59:10.521244 <6>[ 3.709834] Freeing initrd memory: 14992K
702 23:59:10.545137 <6>[ 3.730655] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 23:59:10.599290 <6>[ 3.783104] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 23:59:10.605096 <6>[ 3.793459] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 23:59:10.613147 <6>[ 3.800803] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 23:59:10.624715 <6>[ 3.808264] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 23:59:10.636230 <6>[ 3.816399] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 23:59:10.643778 <6>[ 3.828042] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 23:59:10.653844 <5>[ 3.837150] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 23:59:10.683193 <3>[ 3.867681] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 23:59:10.689056 <6>[ 3.876280] edma 49000000.dma: TI EDMA DMA engine driver
712 23:59:10.760812 <3>[ 3.945238] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 23:59:10.775752 <6>[ 3.959761] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 23:59:10.788759 <3>[ 3.977058] l3-aon-clkctrl:0000:0: failed to disable
715 23:59:10.845107 <6>[ 4.029441] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 23:59:10.850842 <6>[ 4.038963] printk: legacy console [ttyS0] enabled
717 23:59:10.856485 <6>[ 4.038963] printk: legacy console [ttyS0] enabled
718 23:59:10.862121 <6>[ 4.049302] printk: legacy bootconsole [omap8250] disabled
719 23:59:10.868191 <6>[ 4.049302] printk: legacy bootconsole [omap8250] disabled
720 23:59:10.898049 <4>[ 4.081475] tps65217-pmic: Failed to locate of_node [id: -1]
721 23:59:10.901642 <4>[ 4.088876] tps65217-bl: Failed to locate of_node [id: -1]
722 23:59:10.918587 <6>[ 4.108982] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 23:59:10.937034 <6>[ 4.116045] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 23:59:10.948706 <6>[ 4.129742] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 23:59:10.954389 <6>[ 4.141631] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 23:59:10.977089 <6>[ 4.161752] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 23:59:10.982774 <6>[ 4.170915] sdhci-omap 48060000.mmc: Got CD GPIO
728 23:59:10.990827 <4>[ 4.176055] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 23:59:11.005625 <4>[ 4.189769] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 23:59:11.012148 <4>[ 4.198477] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 23:59:11.022068 <4>[ 4.207200] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 23:59:11.121114 <6>[ 4.307002] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 23:59:11.160679 <6>[ 4.346482] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 23:59:11.182006 <6>[ 4.365987] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 23:59:11.188767 <6>[ 4.374916] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 23:59:11.230190 <6>[ 4.410484] mmc0: new high speed SDHC card at address 1234
737 23:59:11.230678 <6>[ 4.418468] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 23:59:11.237461 <6>[ 4.427663] mmcblk0: p1
739 23:59:11.269793 <6>[ 4.451927] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 23:59:11.293508 <6>[ 4.474577] mmc1: new high speed MMC card at address 0001
741 23:59:11.294011 <6>[ 4.481774] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 23:59:11.302015 <6>[ 4.489765] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 23:59:11.310223 <6>[ 4.497684] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 23:59:11.315762 <6>[ 4.505447] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 23:59:13.407213 <6>[ 6.591709] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 23:59:13.470851 <5>[ 6.620660] Sending DHCP requests ., OK
747 23:59:13.482247 <6>[ 6.665439] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 23:59:13.482712 <6>[ 6.673637] IP-Config: Complete:
749 23:59:13.495959 <6>[ 6.677176] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 23:59:13.501534 <6>[ 6.687702] host=192.168.6.12, domain=, nis-domain=(none)
751 23:59:13.507226 <6>[ 6.693917] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 23:59:13.513968 <6>[ 6.693952] nameserver0=10.255.253.1
753 23:59:13.520128 <6>[ 6.706593] clk: Disabling unused clocks
754 23:59:13.523482 <6>[ 6.711350] PM: genpd: Disabling unused power domains
755 23:59:13.541067 <6>[ 6.728043] Freeing unused kernel image (initmem) memory: 2048K
756 23:59:13.548054 <6>[ 6.737911] Run /init as init process
757 23:59:13.576318 Loading, please wait...
758 23:59:13.654451 Starting systemd-udevd version 252.22-1~deb12u1
759 23:59:16.736771 <4>[ 9.920034] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 23:59:16.859100 <4>[ 10.042397] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 23:59:17.001031 <6>[ 10.191790] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 23:59:17.011744 <6>[ 10.197469] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 23:59:17.313675 <6>[ 10.503716] hub 1-0:1.0: USB hub found
764 23:59:17.355099 <6>[ 10.544078] hub 1-0:1.0: 1 port detected
765 23:59:17.524415 <6>[ 10.714103] tda998x 0-0070: found TDA19988
766 23:59:20.803301 Begin: Loading essential drivers ... done.
767 23:59:20.808812 Begin: Running /scripts/init-premount ... done.
768 23:59:20.814413 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 23:59:20.824301 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 23:59:20.836405 Device /sys/class/net/eth0 found
771 23:59:20.836844 done.
772 23:59:20.915224 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 23:59:21.012901 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 23:59:21.035570 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 23:59:21.040996 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 23:59:21.046607 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 23:59:21.057865 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 23:59:21.058580 rootserver: 192.168.6.1 rootpath:
779 23:59:21.060384 filename :
780 23:59:21.179952 done.
781 23:59:21.187448 Begin: Running /scripts/nfs-bottom ... done.
782 23:59:21.249641 Begin: Running /scripts/init-bottom ... done.
783 23:59:22.696780 <30>[ 15.883500] systemd[1]: System time before build time, advancing clock.
784 23:59:22.861449 <30>[ 16.022068] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 23:59:22.870416 <30>[ 16.059020] systemd[1]: Detected architecture arm.
786 23:59:22.883158
787 23:59:22.883642 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 23:59:22.884103
789 23:59:22.913419 <30>[ 16.101731] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 23:59:25.129982 <30>[ 18.316949] systemd[1]: Queued start job for default target graphical.target.
791 23:59:25.148181 <30>[ 18.332221] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 23:59:25.154694 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 23:59:25.179298 <30>[ 18.363694] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 23:59:25.187710 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 23:59:25.210529 <30>[ 18.393673] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 23:59:25.217785 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 23:59:25.247206 <30>[ 18.434740] systemd[1]: Created slice user.slice - User and Session Slice.
798 23:59:25.259638 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 23:59:25.293214 <30>[ 18.472018] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 23:59:25.298294 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 23:59:25.317132 <30>[ 18.501835] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 23:59:25.328221 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 23:59:25.357918 <30>[ 18.531662] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 23:59:25.364380 <30>[ 18.552151] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 23:59:25.372929 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 23:59:25.396156 <30>[ 18.581160] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 23:59:25.403597 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 23:59:25.426971 <30>[ 18.611594] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 23:59:25.435405 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 23:59:25.457019 <30>[ 18.641845] systemd[1]: Reached target paths.target - Path Units.
811 23:59:25.461092 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 23:59:25.489751 <30>[ 18.672602] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 23:59:25.496204 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 23:59:25.516231 <30>[ 18.701171] systemd[1]: Reached target slices.target - Slice Units.
815 23:59:25.521235 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 23:59:25.546661 <30>[ 18.731496] systemd[1]: Reached target swap.target - Swaps.
817 23:59:25.549735 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 23:59:25.576794 <30>[ 18.761473] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 23:59:25.584675 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 23:59:25.607681 <30>[ 18.792259] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 23:59:25.615624 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 23:59:25.697602 <30>[ 18.877525] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 23:59:25.710491 <30>[ 18.895073] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 23:59:25.718828 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 23:59:25.748751 <30>[ 18.935016] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 23:59:25.761447 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 23:59:25.787804 <30>[ 18.973581] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 23:59:25.798715 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 23:59:25.833314 <30>[ 19.018669] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 23:59:25.845876 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 23:59:25.868296 <30>[ 19.052680] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 23:59:25.875949 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 23:59:25.903842 <30>[ 19.082438] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 23:59:25.920502 <30>[ 19.099157] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 23:59:25.970977 <30>[ 19.156571] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 23:59:25.996875 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 23:59:26.047831 <30>[ 19.234260] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 23:59:26.069624 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 23:59:26.156480 <30>[ 19.341935] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 23:59:26.185296 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 23:59:26.247142 <30>[ 19.432280] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 23:59:26.266949 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 23:59:26.330368 <30>[ 19.515900] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 23:59:26.364767 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 23:59:26.417647 <30>[ 19.603492] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 23:59:26.443360 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 23:59:26.499504 <30>[ 19.684235] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 23:59:26.533428 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 23:59:26.587792 <30>[ 19.773489] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 23:59:26.614083 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 23:59:26.668381 <30>[ 19.854201] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 23:59:26.694351 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 23:59:26.723110 <28>[ 19.902955] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 23:59:26.731658 <28>[ 19.916566] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 23:59:26.775804 <30>[ 19.962004] systemd[1]: Starting systemd-journald.service - Journal Service...
856 23:59:26.794004 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 23:59:26.879614 <30>[ 20.065149] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 23:59:26.905837 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 23:59:26.959377 <30>[ 20.145130] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 23:59:27.007540 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 23:59:27.079444 <30>[ 20.264692] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 23:59:27.126381 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 23:59:27.189383 <30>[ 20.374418] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 23:59:27.245758 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 23:59:27.308064 <30>[ 20.493936] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 23:59:27.366231 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 23:59:27.386953 <30>[ 20.572737] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 23:59:27.427722 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 23:59:27.450685 <30>[ 20.636401] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 23:59:27.479630 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 23:59:27.605780 <30>[ 20.793135] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 23:59:27.637284 <30>[ 20.822594] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 23:59:27.665152 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 23:59:27.677314 <30>[ 20.862435] systemd[1]: Started systemd-journald.service - Journal Service.
875 23:59:27.684242 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
876 23:59:27.712934 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 23:59:27.737435 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 23:59:27.768366 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
879 23:59:27.798604 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
880 23:59:27.826650 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
881 23:59:27.856435 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
882 23:59:27.877812 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
883 23:59:27.906562 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
884 23:59:27.936214 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
885 23:59:27.998796 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
886 23:59:28.046112 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
887 23:59:28.114312 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
888 23:59:28.189213 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
889 23:59:28.282457 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
890 23:59:28.441181 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
891 23:59:28.452739 <46>[ 21.638626] systemd-journald[163]: Received client request to flush runtime journal.
892 23:59:28.540729 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
893 23:59:29.408248 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
894 23:59:29.806022 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
895 23:59:29.868572 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
896 23:59:30.208095 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
897 23:59:30.439569 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
898 23:59:30.457290 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
899 23:59:30.486351 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
900 23:59:30.576056 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 23:59:30.614923 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 23:59:31.597971 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 23:59:31.666428 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 23:59:31.796047 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
905 23:59:31.916232 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 23:59:31.955155 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 23:59:33.117625 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
908 23:59:34.420025 <5>[ 27.606187] cfg80211: Loading compiled-in X.509 certificates for regulatory database
909 23:59:34.639349 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
910 23:59:35.716779 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
911 23:59:36.000590 <5>[ 29.189469] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
912 23:59:36.118623 <5>[ 29.303035] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
913 23:59:36.124384 <4>[ 29.312353] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
914 23:59:36.131429 <6>[ 29.321481] cfg80211: failed to load regulatory.db
915 23:59:36.617398 <46>[ 29.794355] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
916 23:59:36.640473 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
917 23:59:36.758921 <46>[ 29.938286] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
918 23:59:37.186141 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
919 23:59:46.124588 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
920 23:59:46.145847 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
921 23:59:46.169446 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
922 23:59:46.202215 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
923 23:59:46.266326 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
924 23:59:46.316854 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
925 23:59:46.389083 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
926 23:59:46.437719 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
927 23:59:46.490903 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
928 23:59:46.520982 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
929 23:59:46.551490 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
930 23:59:46.593468 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
931 23:59:46.621177 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
932 23:59:46.666495 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
933 23:59:46.695748 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
934 23:59:46.716453 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
935 23:59:46.742235 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
936 23:59:46.771347 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
937 23:59:46.800695 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
938 23:59:46.825092 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
939 23:59:46.855301 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
940 23:59:46.875288 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
941 23:59:46.904642 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
942 23:59:46.975822 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
943 23:59:47.017980 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
944 23:59:47.108574 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
945 23:59:47.200697 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
946 23:59:47.257977 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
947 23:59:47.298479 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
948 23:59:47.335739 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
949 23:59:47.541265 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
950 23:59:47.615393 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
951 23:59:47.688326 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
952 23:59:47.716075 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
953 23:59:47.745091 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
954 23:59:47.956246 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
955 23:59:48.401092 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
956 23:59:48.446506 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
957 23:59:48.470437 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
958 23:59:48.549992 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
959 23:59:48.726712 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
960 23:59:48.877741
961 23:59:48.880327 Debian GNU/Linux 12 debworm-armhf login: root (automatic login)
962 23:59:48.880809
963 23:59:49.216213 Linux debian-bookworm-armhf 6.12.0-rc4 #1 SMP Fri Oct 25 23:08:25 UTC 2024 armv7l
964 23:59:49.216812
965 23:59:49.221864 The programs included with the Debian GNU/Linux system are free software;
966 23:59:49.225177 the exact distribution terms for each program are described in the
967 23:59:49.230682 individual files in /usr/share/doc/*/copyright.
968 23:59:49.231167
969 23:59:49.236330 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
970 23:59:49.240093 permitted by applicable law.
971 23:59:53.915915 Unable to match end of the kernel message
973 23:59:53.917227 Setting prompt string to ['/ #']
974 23:59:53.917678 end: 2.4.4.1 login-action (duration 00:00:48) [common]
976 23:59:53.918743 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
977 23:59:53.919200 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
978 23:59:53.919579 Setting prompt string to ['/ #']
979 23:59:53.919922 Forcing a shell prompt, looking for ['/ #']
981 23:59:53.970772 / #
982 23:59:53.971401 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
983 23:59:53.971767 Waiting using forced prompt support (timeout 00:02:30)
984 23:59:53.975751
985 23:59:53.982244 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
986 23:59:53.982687 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
987 23:59:53.983041 Sending with 10 millisecond of delay
989 23:59:58.974102 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5'
990 23:59:58.984888 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/892286/extract-nfsrootfs-safa9gj5'
991 23:59:58.985742 Sending with 10 millisecond of delay
993 00:00:01.084807 / # export NFS_SERVER_IP='192.168.6.2'
994 00:00:01.095733 export NFS_SERVER_IP='192.168.6.2'
995 00:00:01.096728 end: 2.4.6 export-device-env (duration 00:00:07) [common]
996 00:00:01.097333 end: 2.4 uboot-commands (duration 00:01:54) [common]
997 00:00:01.097972 end: 2 uboot-action (duration 00:01:54) [common]
998 00:00:01.098545 start: 3 lava-test-retry (timeout 00:06:55) [common]
999 00:00:01.099120 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
1000 00:00:01.099776 Using namespace: common
1002 00:00:01.201087 / # #
1003 00:00:01.201837 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1004 00:00:01.205784 #
1005 00:00:01.211946 Using /lava-892286
1007 00:00:01.313227 / # export SHELL=/bin/bash
1008 00:00:01.317664 export SHELL=/bin/bash
1010 00:00:01.424707 / # . /lava-892286/environment
1011 00:00:01.429055 . /lava-892286/environment
1013 00:00:01.542572 / # /lava-892286/bin/lava-test-runner /lava-892286/0
1014 00:00:01.543481 Test shell timeout: 10s (minimum of the action and connection timeout)
1015 00:00:01.547247 /lava-892286/bin/lava-test-runner /lava-892286/0
1016 00:00:02.011051 + export TESTRUN_ID=0_timesync-off
1017 00:00:02.017962 + TESTRUN_ID=0_timesync-off
1018 00:00:02.018491 + cd /lava-892286/0/tests/0_timesync-off
1019 00:00:02.018930 ++ cat uuid
1020 00:00:02.036274 + UUID=892286_1.6.2.4.1
1021 00:00:02.036812 + set +x
1022 00:00:02.043855 <LAVA_SIGNAL_STARTRUN 0_timesync-off 892286_1.6.2.4.1>
1023 00:00:02.044390 + systemctl stop systemd-timesyncd
1024 00:00:02.045111 Received signal: <STARTRUN> 0_timesync-off 892286_1.6.2.4.1
1025 00:00:02.045552 Starting test lava.0_timesync-off (892286_1.6.2.4.1)
1026 00:00:02.046111 Skipping test definition patterns.
1027 00:00:02.534765 + set +x
1028 00:00:02.535353 <LAVA_SIGNAL_ENDRUN 0_timesync-off 892286_1.6.2.4.1>
1029 00:00:02.536078 Received signal: <ENDRUN> 0_timesync-off 892286_1.6.2.4.1
1030 00:00:02.536591 Ending use of test pattern.
1031 00:00:02.537010 Ending test lava.0_timesync-off (892286_1.6.2.4.1), duration 0.49
1033 00:00:02.820744 + export TESTRUN_ID=1_kselftest-dt
1034 00:00:02.827627 + TESTRUN_ID=1_kselftest-dt
1035 00:00:02.828187 + cd /lava-892286/0/tests/1_kselftest-dt
1036 00:00:02.828640 ++ cat uuid
1037 00:00:02.874340 + UUID=892286_1.6.2.4.5
1038 00:00:02.874899 + set +x
1039 00:00:02.879923 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 892286_1.6.2.4.5>
1040 00:00:02.880430 + cd ./automated/linux/kselftest/
1041 00:00:02.881127 Received signal: <STARTRUN> 1_kselftest-dt 892286_1.6.2.4.5
1042 00:00:02.881558 Starting test lava.1_kselftest-dt (892286_1.6.2.4.5)
1043 00:00:02.882046 Skipping test definition patterns.
1044 00:00:02.907190 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc4-256-gc71f8fb4dc91/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1045 00:00:03.165049 INFO: install_deps skipped
1046 00:00:03.780776 --2024-10-26 00:00:03-- http://storage.kernelci.org/mainline/master/v6.12-rc4-256-gc71f8fb4dc91/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1047 00:00:03.808962 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1048 00:00:03.950176 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1049 00:00:04.092391 HTTP request sent, awaiting response... 200 OK
1050 00:00:04.092987 Length: 2714232 (2.6M) [application/octet-stream]
1051 00:00:04.097908 Saving to: 'kselftest_armhf.tar.gz'
1052 00:00:04.098414
1053 00:00:05.714369
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
kselftest_armhf.tar 8%[> ] 218.67K 393KB/s
kselftest_armhf.tar 33%[=====> ] 888.48K 1.04MB/s
kselftest_armhf.tar 83%[===============> ] 2.16M 2.05MB/s
kselftest_armhf.tar 93%[=================> ] 2.42M 1.81MB/s
kselftest_armhf.tar 99%[==================> ] 2.57M 1.60MB/s
kselftest_armhf.tar 100%[===================>] 2.59M 1.61MB/s in 1.6s
1054 00:00:05.714993
1055 00:00:06.068904 2024-10-26 00:00:05 (1.61 MB/s) - 'kselftest_armhf.tar.gz' saved [2714232/2714232]
1056 00:00:06.069494
1057 00:00:17.034266 skiplist:
1058 00:00:17.034864 ========================================
1059 00:00:17.038954 ========================================
1060 00:00:17.126994 dt:test_unprobed_devices.sh
1061 00:00:17.159546 ============== Tests to run ===============
1062 00:00:17.172212 dt:test_unprobed_devices.sh
1063 00:00:17.175115 ===========End Tests to run ===============
1064 00:00:17.183283 shardfile-dt pass
1065 00:00:17.435079 <12>[ 70.628061] kselftest: Running tests in dt
1066 00:00:17.463366 TAP version 13
1067 00:00:17.488524 1..1
1068 00:00:17.545555 # timeout set to 45
1069 00:00:17.546309 # selftests: dt: test_unprobed_devices.sh
1070 00:00:18.386776 # TAP version 13
1071 00:00:44.143595 # 1..257
1072 00:00:44.320542 # ok 1 / # SKIP
1073 00:00:44.341862 # ok 2 /clk_mcasp0
1074 00:00:44.420835 # ok 3 /clk_mcasp0_fixed # SKIP
1075 00:00:44.490682 # ok 4 /cpus/cpu@0 # SKIP
1076 00:00:44.563761 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1077 00:00:44.584878 # ok 6 /fixedregulator0
1078 00:00:44.601844 # ok 7 /leds
1079 00:00:44.628371 # ok 8 /ocp
1080 00:00:44.648137 # ok 9 /ocp/interconnect@44c00000
1081 00:00:44.675846 # ok 10 /ocp/interconnect@44c00000/segment@0
1082 00:00:44.704500 # ok 11 /ocp/interconnect@44c00000/segment@100000
1083 00:00:44.721588 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1084 00:00:44.795719 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1085 00:00:44.816792 # ok 14 /ocp/interconnect@44c00000/segment@200000
1086 00:00:44.846623 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1087 00:00:44.953588 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1088 00:00:45.027864 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1089 00:00:45.101174 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1090 00:00:45.176549 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1091 00:00:45.250516 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1092 00:00:45.326608 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1093 00:00:45.394670 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1094 00:00:45.468789 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1095 00:00:45.542604 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1096 00:00:45.615885 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1097 00:00:45.688737 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1098 00:00:45.763867 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1099 00:00:45.837596 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1100 00:00:45.912673 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1101 00:00:45.984855 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1102 00:00:46.059156 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1103 00:00:46.133268 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1104 00:00:46.206679 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1105 00:00:46.279668 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1106 00:00:46.358301 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1107 00:00:46.430573 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1108 00:00:46.503563 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1109 00:00:46.576267 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1110 00:00:46.649133 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1111 00:00:46.722061 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1112 00:00:46.795550 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1113 00:00:46.870312 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1114 00:00:46.944989 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1115 00:00:47.017867 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1116 00:00:47.091928 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1117 00:00:47.171347 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1118 00:00:47.241642 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1119 00:00:47.319631 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1120 00:00:47.392565 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1121 00:00:47.463504 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1122 00:00:47.539228 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1123 00:00:47.882412 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1124 00:00:47.883219 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1125 00:00:47.883563 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1126 00:00:47.886986 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1127 00:00:47.911541 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1128 00:00:47.986102 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1129 00:00:48.059666 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1130 00:00:48.137760 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1131 00:00:48.212584 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1132 00:00:48.285882 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1133 00:00:48.360229 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1134 00:00:48.435463 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1135 00:00:48.512432 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1136 00:00:48.582479 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1137 00:00:48.658758 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1138 00:00:48.733272 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1139 00:00:48.807622 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1140 00:00:48.882468 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1141 00:00:48.956195 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1142 00:00:49.031475 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1143 00:00:49.105738 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1144 00:00:49.183281 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1145 00:00:49.258330 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1146 00:00:49.339638 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1147 00:00:49.408928 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1148 00:00:49.484128 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1149 00:00:49.559063 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1150 00:00:49.635479 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1151 00:00:49.709524 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1152 00:00:49.785939 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1153 00:00:49.860690 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1154 00:00:49.934136 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1155 00:00:50.020131 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1156 00:00:50.091807 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1157 00:00:50.171242 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1158 00:00:50.244339 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1159 00:00:50.320027 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1160 00:00:50.400262 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1161 00:00:50.477464 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1162 00:00:50.546738 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1163 00:00:50.630513 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1164 00:00:50.699330 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1165 00:00:50.774324 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1166 00:00:50.795039 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1167 00:00:50.823907 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1168 00:00:50.848656 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1169 00:00:50.874051 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1170 00:00:50.893490 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1171 00:00:50.917607 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1172 00:00:50.942704 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1173 00:00:50.968069 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1174 00:00:51.075690 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1175 00:00:51.105686 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1176 00:00:51.126341 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1177 00:00:51.155852 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1178 00:00:51.258628 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1179 00:00:51.337822 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1180 00:00:51.418710 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1181 00:00:51.495763 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1182 00:00:51.571444 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1183 00:00:51.647021 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1184 00:00:51.721621 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1185 00:00:51.797261 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1186 00:00:51.870939 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1187 00:00:51.948328 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1188 00:00:52.023091 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1189 00:00:52.097259 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1190 00:00:52.171442 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1191 00:00:52.248271 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1192 00:00:52.331537 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1193 00:00:52.401132 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1194 00:00:52.427643 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1195 00:00:52.499602 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1196 00:00:52.569208 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1197 00:00:52.642209 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1198 00:00:52.667790 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1199 00:00:52.738823 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1200 00:00:52.761330 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1201 00:00:52.835409 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1202 00:00:52.859448 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1203 00:00:52.883531 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1204 00:00:52.907820 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1205 00:00:52.937938 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1206 00:00:52.958199 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1207 00:00:52.980765 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1208 00:00:53.007885 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1209 00:00:53.084921 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1210 00:00:53.106146 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1211 00:00:53.135884 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1212 00:00:53.210355 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1213 00:00:53.281041 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1214 00:00:53.306892 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1215 00:00:53.410992 # not ok 144 /ocp/interconnect@47c00000
1216 00:00:53.479579 # not ok 145 /ocp/interconnect@47c00000/segment@0
1217 00:00:53.505678 # ok 146 /ocp/interconnect@48000000
1218 00:00:53.530901 # ok 147 /ocp/interconnect@48000000/segment@0
1219 00:00:53.557527 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1220 00:00:53.578301 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1221 00:00:53.605446 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1222 00:00:53.628371 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1223 00:00:53.653460 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1224 00:00:53.678086 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1225 00:00:53.702651 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1226 00:00:53.770784 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1227 00:00:53.846298 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1228 00:00:53.873493 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1229 00:00:53.893461 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1230 00:00:53.918158 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1231 00:00:53.941404 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1232 00:00:53.965179 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1233 00:00:53.996200 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1234 00:00:54.017555 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1235 00:00:54.039703 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1236 00:00:54.062759 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1237 00:00:54.087377 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1238 00:00:54.110831 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1239 00:00:54.135482 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1240 00:00:54.158863 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1241 00:00:54.183565 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1242 00:00:54.206907 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1243 00:00:54.236665 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1244 00:00:54.258188 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1245 00:00:54.281009 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1246 00:00:54.302603 # ok 175 /ocp/interconnect@48000000/segment@100000
1247 00:00:54.328627 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1248 00:00:54.357660 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1249 00:00:54.686950 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1250 00:00:54.687909 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1251 00:00:54.688257 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1252 00:00:54.690654 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1253 00:00:54.724507 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1254 00:00:54.800182 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1255 00:00:54.872028 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1256 00:00:54.948496 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1257 00:00:54.973686 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1258 00:00:54.993407 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1259 00:00:55.018547 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1260 00:00:55.041132 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1261 00:00:55.065160 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1262 00:00:55.090163 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1263 00:00:55.113831 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1264 00:00:55.138485 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1265 00:00:55.167256 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1266 00:00:55.188481 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1267 00:00:55.210969 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1268 00:00:55.235579 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1269 00:00:55.261654 # ok 198 /ocp/interconnect@48000000/segment@200000
1270 00:00:55.286824 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1271 00:00:55.359465 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1272 00:00:55.379458 # ok 201 /ocp/interconnect@48000000/segment@300000
1273 00:00:55.408327 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1274 00:00:55.431031 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1275 00:00:55.452700 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1276 00:00:55.477315 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1277 00:00:55.502141 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1278 00:00:55.525853 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1279 00:00:55.605916 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1280 00:00:55.625592 # ok 209 /ocp/interconnect@4a000000
1281 00:00:55.644677 # ok 210 /ocp/interconnect@4a000000/segment@0
1282 00:00:55.674801 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1283 00:00:55.698963 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1284 00:00:55.721033 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1285 00:00:55.744161 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1286 00:00:55.818390 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1287 00:00:55.928053 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1288 00:00:56.005989 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1289 00:00:56.110841 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1290 00:00:56.182905 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1291 00:00:56.256414 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1292 00:00:56.358216 # not ok 221 /ocp/interconnect@4b140000
1293 00:00:56.431662 # not ok 222 /ocp/interconnect@4b140000/segment@0
1294 00:00:56.506868 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1295 00:00:56.530922 # ok 224 /ocp/target-module@40300000
1296 00:00:56.555420 # ok 225 /ocp/target-module@40300000/sram@0
1297 00:00:56.626466 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1298 00:00:56.705152 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1299 00:00:56.725074 # ok 228 /ocp/target-module@47400000
1300 00:00:56.747241 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1301 00:00:56.773502 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1302 00:00:56.796917 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1303 00:00:56.814944 # ok 232 /ocp/target-module@47400000/usb@1400
1304 00:00:56.842684 # ok 233 /ocp/target-module@47400000/usb@1800
1305 00:00:56.864109 # ok 234 /ocp/target-module@47810000
1306 00:00:56.882534 # ok 235 /ocp/target-module@49000000
1307 00:00:56.910737 # ok 236 /ocp/target-module@49000000/dma@0
1308 00:00:56.933191 # ok 237 /ocp/target-module@49800000
1309 00:00:56.952251 # ok 238 /ocp/target-module@49800000/dma@0
1310 00:00:56.975839 # ok 239 /ocp/target-module@49900000
1311 00:00:57.003187 # ok 240 /ocp/target-module@49900000/dma@0
1312 00:00:57.025822 # ok 241 /ocp/target-module@49a00000
1313 00:00:57.051325 # ok 242 /ocp/target-module@49a00000/dma@0
1314 00:00:57.069431 # ok 243 /ocp/target-module@4c000000
1315 00:00:57.146654 # not ok 244 /ocp/target-module@4c000000/emif@0
1316 00:00:57.170876 # ok 245 /ocp/target-module@50000000
1317 00:00:57.190172 # ok 246 /ocp/target-module@53100000
1318 00:00:57.266624 # not ok 247 /ocp/target-module@53100000/sham@0
1319 00:00:57.290799 # ok 248 /ocp/target-module@53500000
1320 00:00:57.365919 # not ok 249 /ocp/target-module@53500000/aes@0
1321 00:00:57.383530 # ok 250 /ocp/target-module@56000000
1322 00:00:57.496854 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1323 00:00:57.563010 # ok 252 /opp-table # SKIP
1324 00:00:57.640447 # ok 253 /soc # SKIP
1325 00:00:57.662577 # ok 254 /sound
1326 00:00:57.681507 # ok 255 /target-module@4b000000
1327 00:00:57.708559 # ok 256 /target-module@4b000000/target-module@140000
1328 00:00:57.729847 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1329 00:00:57.738463 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1330 00:00:57.746326 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1331 00:01:00.004836 dt_test_unprobed_devices_sh_ skip
1332 00:01:00.010491 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1333 00:01:00.016044 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1334 00:01:00.016617 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1335 00:01:00.024918 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1336 00:01:00.025454 dt_test_unprobed_devices_sh_fixedregulator0 pass
1337 00:01:00.030616 dt_test_unprobed_devices_sh_leds pass
1338 00:01:00.036208 dt_test_unprobed_devices_sh_ocp pass
1339 00:01:00.041723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1340 00:01:00.047266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1341 00:01:00.052991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1342 00:01:00.058531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1343 00:01:00.069771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1344 00:01:00.075401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1345 00:01:00.080989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1346 00:01:00.092281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1347 00:01:00.097869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1348 00:01:00.109281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1349 00:01:00.120314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1350 00:01:00.131544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1351 00:01:00.142664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1352 00:01:00.148359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1353 00:01:00.159504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1354 00:01:00.170711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1355 00:01:00.181866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1356 00:01:00.193151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1357 00:01:00.198749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1358 00:01:00.209860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1359 00:01:00.221058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1360 00:01:00.232339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1361 00:01:00.243450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1362 00:01:00.249075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1363 00:01:00.260300 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1364 00:01:00.271458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1365 00:01:00.282624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1366 00:01:00.288305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1367 00:01:00.299466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1368 00:01:00.310647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1369 00:01:00.321807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1370 00:01:00.332988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1371 00:01:00.344380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1372 00:01:00.355495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1373 00:01:00.366726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1374 00:01:00.377865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1375 00:01:00.389015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1376 00:01:00.400265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1377 00:01:00.411386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1378 00:01:00.422608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1379 00:01:00.433810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1380 00:01:00.444973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1381 00:01:00.456216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1382 00:01:00.467398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1383 00:01:00.478614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1384 00:01:00.489754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1385 00:01:00.500930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1386 00:01:00.512247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1387 00:01:00.523507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1388 00:01:00.534580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1389 00:01:00.540258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1390 00:01:00.551309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1391 00:01:00.562534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1392 00:01:00.573710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1393 00:01:00.585027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1394 00:01:00.596116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1395 00:01:00.607358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1396 00:01:00.618495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1397 00:01:00.629725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1398 00:01:00.640883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1399 00:01:00.646508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1400 00:01:00.657735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1401 00:01:00.668792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1402 00:01:00.680067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1403 00:01:00.691215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1404 00:01:00.702402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1405 00:01:00.713651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1406 00:01:00.724825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1407 00:01:00.735975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1408 00:01:00.747167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1409 00:01:00.758369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1410 00:01:00.769522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1411 00:01:00.780777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1412 00:01:00.791975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1413 00:01:00.803157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1414 00:01:00.814348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1415 00:01:00.819932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1416 00:01:00.831125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1417 00:01:00.842304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1418 00:01:00.853505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1419 00:01:00.864749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1420 00:01:00.875998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1421 00:01:00.887130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1422 00:01:00.898347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1423 00:01:00.909519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1424 00:01:00.920735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1425 00:01:00.931951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1426 00:01:00.943084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1427 00:01:00.948662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1428 00:01:00.959869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1429 00:01:00.971025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1430 00:01:00.976627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1431 00:01:00.987900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1432 00:01:00.993426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1433 00:01:01.004637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1434 00:01:01.015795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1435 00:01:01.021484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1436 00:01:01.032604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1437 00:01:01.043805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1438 00:01:01.054958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1439 00:01:01.066208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1440 00:01:01.077458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1441 00:01:01.088598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1442 00:01:01.105394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1443 00:01:01.116543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1444 00:01:01.127751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1445 00:01:01.138891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1446 00:01:01.150132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1447 00:01:01.161354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1448 00:01:01.172513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1449 00:01:01.183769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1450 00:01:01.200540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1451 00:01:01.211740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1452 00:01:01.228608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1453 00:01:01.239774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1454 00:01:01.245360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1455 00:01:01.256560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1456 00:01:01.262180 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1457 00:01:01.273378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1458 00:01:01.284501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1459 00:01:01.290115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1460 00:01:01.301297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1461 00:01:01.306912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1462 00:01:01.318099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1463 00:01:01.323743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1464 00:01:01.334909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1465 00:01:01.340502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1466 00:01:01.351707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1467 00:01:01.363816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1468 00:01:01.374112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1469 00:01:01.379756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1470 00:01:01.390950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1471 00:01:01.402153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1472 00:01:01.413302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1473 00:01:01.418937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1474 00:01:01.424536 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1475 00:01:01.430099 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1476 00:01:01.435669 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1477 00:01:01.441287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1478 00:01:01.452539 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1479 00:01:01.458085 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1480 00:01:01.463674 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1481 00:01:01.474851 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1482 00:01:01.480538 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1483 00:01:01.491651 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1484 00:01:01.497264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1485 00:01:01.508443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1486 00:01:01.514065 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1487 00:01:01.525216 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1488 00:01:01.530818 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1489 00:01:01.542044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1490 00:01:01.547599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1491 00:01:01.553222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1492 00:01:01.564398 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1493 00:01:01.569997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1494 00:01:01.581201 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1495 00:01:01.586804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1496 00:01:01.598005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1497 00:01:01.603633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1498 00:01:01.614857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1499 00:01:01.620476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1500 00:01:01.631616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1501 00:01:01.637270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1502 00:01:01.648415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1503 00:01:01.654063 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1504 00:01:01.665194 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1505 00:01:01.670828 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1506 00:01:01.676467 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1507 00:01:01.687646 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1508 00:01:01.698770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1509 00:01:01.710004 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1510 00:01:01.721156 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1511 00:01:01.732389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1512 00:01:01.738005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1513 00:01:01.749132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1514 00:01:01.760300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1515 00:01:01.771505 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1516 00:01:01.782722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1517 00:01:01.788357 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1518 00:01:01.799509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1519 00:01:01.805135 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1520 00:01:01.816308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1521 00:01:01.821941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1522 00:01:01.833103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1523 00:01:01.838751 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1524 00:01:01.849897 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1525 00:01:01.855488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1526 00:01:01.866843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1527 00:01:01.872196 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1528 00:01:01.883346 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1529 00:01:01.888944 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1530 00:01:01.900158 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1531 00:01:01.905735 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1532 00:01:01.911336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1533 00:01:01.922512 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1534 00:01:01.928174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1535 00:01:01.939329 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1536 00:01:01.944975 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1537 00:01:01.956140 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1538 00:01:01.961741 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1539 00:01:01.967360 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1540 00:01:01.972932 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1541 00:01:01.984136 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1542 00:01:01.989640 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1543 00:01:02.000930 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1544 00:01:02.006546 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1545 00:01:02.017740 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1546 00:01:02.028905 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1547 00:01:02.040097 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1548 00:01:02.045689 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1549 00:01:02.056993 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1550 00:01:02.068248 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1551 00:01:02.073772 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1552 00:01:02.079385 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1553 00:01:02.085053 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1554 00:01:02.090631 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1555 00:01:02.096223 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1556 00:01:02.101711 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1557 00:01:02.107382 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1558 00:01:02.112981 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1559 00:01:02.124276 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1560 00:01:02.129754 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1561 00:01:02.135498 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1562 00:01:02.141047 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1563 00:01:02.146620 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1564 00:01:02.152228 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1565 00:01:02.157880 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1566 00:01:02.163314 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1567 00:01:02.168944 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1568 00:01:02.174784 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1569 00:01:02.180244 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1570 00:01:02.185796 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1571 00:01:02.191418 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1572 00:01:02.197006 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1573 00:01:02.202585 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1574 00:01:02.208444 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1575 00:01:02.213783 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1576 00:01:02.219356 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1577 00:01:02.225042 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1578 00:01:02.230567 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1579 00:01:02.236197 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1580 00:01:02.241835 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1581 00:01:02.247398 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1582 00:01:02.253029 dt_test_unprobed_devices_sh_opp-table skip
1583 00:01:02.253337 dt_test_unprobed_devices_sh_soc skip
1584 00:01:02.258621 dt_test_unprobed_devices_sh_sound pass
1585 00:01:02.264237 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1586 00:01:02.269809 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1587 00:01:02.275408 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1588 00:01:02.281040 dt_test_unprobed_devices_sh fail
1589 00:01:02.286675 + ../../utils/send-to-lava.sh ./output/result.txt
1590 00:01:02.292821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1591 00:01:02.293463 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1593 00:01:02.298398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1594 00:01:02.298915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1596 00:01:02.396014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1597 00:01:02.396590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1599 00:01:02.486419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1600 00:01:02.486992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1602 00:01:02.575752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1603 00:01:02.576364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1605 00:01:02.676518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1606 00:01:02.677096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1608 00:01:02.773566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1609 00:01:02.774146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1611 00:01:02.870708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1612 00:01:02.871292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1614 00:01:02.969150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1615 00:01:02.969729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1617 00:01:03.067441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1618 00:01:03.068025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1620 00:01:03.162915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1621 00:01:03.163483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1623 00:01:03.254735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1624 00:01:03.255313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1626 00:01:03.351343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1627 00:01:03.351959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1629 00:01:03.446516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1630 00:01:03.447137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1632 00:01:03.544582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1633 00:01:03.545227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1635 00:01:03.634299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1636 00:01:03.634941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1638 00:01:03.729473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1639 00:01:03.730094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1641 00:01:03.819925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1642 00:01:03.820578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1644 00:01:03.916792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1645 00:01:03.917398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1647 00:01:04.010811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1648 00:01:04.011427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1650 00:01:04.104020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1651 00:01:04.104640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1653 00:01:04.198330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1654 00:01:04.198954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1656 00:01:04.290991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1657 00:01:04.291610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1659 00:01:04.380490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1660 00:01:04.381082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1662 00:01:04.472308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1663 00:01:04.472931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1665 00:01:04.569544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1666 00:01:04.570148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1668 00:01:04.664260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1669 00:01:04.664889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1671 00:01:04.760505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1672 00:01:04.761422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1674 00:01:04.856739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1675 00:01:04.857565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1677 00:01:04.957803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1678 00:01:04.958593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1680 00:01:05.052934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1681 00:01:05.053432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1683 00:01:05.150527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1684 00:01:05.151119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1686 00:01:05.247325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1687 00:01:05.247928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1689 00:01:05.342873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1690 00:01:05.343505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1692 00:01:05.438102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1693 00:01:05.438710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1695 00:01:05.528551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1696 00:01:05.529196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1698 00:01:05.621959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1699 00:01:05.622541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1701 00:01:05.712957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1702 00:01:05.713576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1704 00:01:05.803539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1705 00:01:05.804175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1707 00:01:05.897973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1708 00:01:05.898568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1710 00:01:05.993500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1711 00:01:05.994092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1713 00:01:06.083121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1714 00:01:06.083725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1716 00:01:06.172996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1717 00:01:06.173603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1719 00:01:06.267529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1720 00:01:06.268136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1722 00:01:06.357052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1723 00:01:06.357699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1725 00:01:06.451548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1726 00:01:06.452177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1728 00:01:06.548921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1729 00:01:06.549567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1731 00:01:06.642916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1732 00:01:06.643566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1734 00:01:06.731339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1735 00:01:06.731945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1737 00:01:06.825388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1738 00:01:06.826000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1740 00:01:06.914009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1741 00:01:06.914630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1743 00:01:07.003284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1744 00:01:07.003891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1746 00:01:07.099528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1747 00:01:07.100123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1749 00:01:07.194058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1750 00:01:07.194706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1752 00:01:07.291279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1753 00:01:07.291896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1755 00:01:07.387169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1756 00:01:07.387762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1758 00:01:07.477686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1759 00:01:07.478325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1761 00:01:07.572798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1762 00:01:07.573436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1764 00:01:07.661214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1765 00:01:07.661880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1767 00:01:07.752030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1768 00:01:07.752651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1770 00:01:07.850144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1771 00:01:07.850769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1773 00:01:07.944783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1774 00:01:07.945400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1776 00:01:08.034904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1777 00:01:08.035512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1779 00:01:08.124486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1780 00:01:08.125057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1782 00:01:08.222422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1783 00:01:08.222981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1785 00:01:08.318163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1786 00:01:08.318773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1788 00:01:08.414108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1789 00:01:08.414718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1791 00:01:08.504839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1792 00:01:08.505436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1794 00:01:08.593205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1795 00:01:08.593811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1797 00:01:08.689367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1798 00:01:08.689967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1800 00:01:08.780926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1801 00:01:08.781556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1803 00:01:08.876628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1804 00:01:08.877266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1806 00:01:08.973675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1807 00:01:08.974298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1809 00:01:09.068914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1810 00:01:09.069527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1812 00:01:09.163915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1813 00:01:09.164535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1815 00:01:09.254148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1816 00:01:09.254767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1818 00:01:09.343391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1819 00:01:09.344035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1821 00:01:09.438001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1822 00:01:09.438580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1824 00:01:09.527325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1825 00:01:09.527924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1827 00:01:09.622696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1828 00:01:09.623280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1830 00:01:09.710557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1831 00:01:09.711121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1833 00:01:09.808838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1834 00:01:09.809437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1836 00:01:09.902307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1837 00:01:09.902941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1839 00:01:09.997027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1840 00:01:09.997635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1842 00:01:10.085993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1843 00:01:10.087360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1845 00:01:10.175076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1846 00:01:10.175965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1848 00:01:10.264426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1849 00:01:10.265308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1851 00:01:10.359807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1852 00:01:10.360888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1854 00:01:10.454460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1855 00:01:10.455413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1857 00:01:10.545156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1858 00:01:10.546158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1860 00:01:10.633683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1861 00:01:10.634690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1863 00:01:10.726799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1864 00:01:10.727706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1866 00:01:10.825026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1867 00:01:10.826002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1869 00:01:10.920288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1870 00:01:10.921413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1872 00:01:11.018920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1873 00:01:11.019928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1875 00:01:11.111134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1876 00:01:11.112189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1878 00:01:11.200518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1879 00:01:11.201496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1881 00:01:11.290327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1882 00:01:11.291293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1884 00:01:11.386222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1885 00:01:11.387219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1887 00:01:11.483385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1888 00:01:11.484504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1890 00:01:11.579328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1891 00:01:11.580248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1893 00:01:11.674902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1894 00:01:11.675827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1896 00:01:11.763027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1897 00:01:11.764030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1899 00:01:11.858076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1900 00:01:11.859078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1902 00:01:11.950512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1903 00:01:11.951461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1905 00:01:12.043651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1906 00:01:12.044690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1908 00:01:12.133174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1909 00:01:12.134117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1911 00:01:12.223225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1912 00:01:12.224098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1914 00:01:12.321338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1915 00:01:12.322286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1917 00:01:12.410762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1918 00:01:12.411703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1920 00:01:12.504881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1921 00:01:12.505814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1923 00:01:12.595367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1924 00:01:12.596434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1926 00:01:12.685278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1927 00:01:12.686207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1929 00:01:12.780704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1930 00:01:12.781668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1932 00:01:12.874722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1933 00:01:12.875645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1935 00:01:12.965318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1936 00:01:12.966224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1938 00:01:13.055610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1939 00:01:13.056557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1941 00:01:13.150440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1942 00:01:13.151443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1944 00:01:13.240788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1945 00:01:13.241784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1947 00:01:13.335121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1948 00:01:13.336011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1950 00:01:13.424807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1952 00:01:13.427862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1953 00:01:13.519787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1955 00:01:13.522117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1956 00:01:13.609362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1958 00:01:13.611656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1959 00:01:13.704884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1960 00:01:13.705849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1962 00:01:13.800957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1963 00:01:13.801912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1965 00:01:13.893829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1966 00:01:13.894782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1968 00:01:13.988969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1969 00:01:13.989935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1971 00:01:14.077097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1972 00:01:14.077947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1974 00:01:14.172328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1975 00:01:14.173283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1977 00:01:14.261895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1978 00:01:14.262876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1980 00:01:14.352031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1981 00:01:14.352996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1983 00:01:14.813487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1984 00:01:14.814410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1986 00:01:14.917809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1987 00:01:14.918750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1989 00:01:15.020131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1990 00:01:15.021093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1992 00:01:15.121247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1993 00:01:15.122178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1995 00:01:15.217027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1996 00:01:15.217988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1998 00:01:15.308043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1999 00:01:15.308991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2001 00:01:15.408882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2002 00:01:15.409787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2004 00:01:15.505196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2005 00:01:15.506151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2007 00:01:15.600224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2008 00:01:15.601190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2010 00:01:15.694801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2011 00:01:15.695780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2013 00:01:15.785916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2014 00:01:15.786915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2016 00:01:15.881636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2017 00:01:15.882515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2019 00:01:15.970440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2020 00:01:15.971320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2022 00:01:16.064819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2023 00:01:16.065727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2025 00:01:16.163168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2026 00:01:16.164059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2028 00:01:16.256426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2029 00:01:16.257404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2031 00:01:16.352858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2032 00:01:16.353825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2034 00:01:16.450453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2035 00:01:16.451352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2037 00:01:16.548254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2038 00:01:16.549170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2040 00:01:16.644510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2041 00:01:16.645442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2043 00:01:16.738950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2044 00:01:16.739865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2046 00:01:16.835888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2047 00:01:16.836841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2049 00:01:16.930204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2050 00:01:16.931102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2052 00:01:17.020316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2053 00:01:17.022061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2055 00:01:17.110561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2056 00:01:17.111467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2058 00:01:17.201176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2059 00:01:17.202090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2061 00:01:17.299116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2062 00:01:17.299977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2064 00:01:17.398181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2065 00:01:17.399101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2067 00:01:17.486257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2068 00:01:17.487126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2070 00:01:17.579288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2071 00:01:17.580135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2073 00:01:17.669379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2074 00:01:17.670218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2076 00:01:17.766442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2077 00:01:17.767320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2079 00:01:17.856060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2080 00:01:17.856918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2082 00:01:17.951662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2083 00:01:17.952585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2085 00:01:18.041868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2086 00:01:18.042744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2088 00:01:18.131242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2089 00:01:18.132079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2091 00:01:18.227712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2092 00:01:18.228665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2094 00:01:18.321877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2095 00:01:18.322761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2097 00:01:18.411840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2098 00:01:18.412767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2100 00:01:18.501826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2101 00:01:18.502490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2103 00:01:18.598019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2104 00:01:18.598641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2106 00:01:18.694343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2107 00:01:18.695239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2109 00:01:18.790723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2110 00:01:18.791559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2112 00:01:18.886459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2113 00:01:18.887291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2115 00:01:18.974401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2116 00:01:18.975235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2118 00:01:19.071087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2119 00:01:19.071939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2121 00:01:19.162022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2122 00:01:19.162870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2124 00:01:19.259538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2125 00:01:19.260419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2127 00:01:19.351625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2128 00:01:19.352515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2130 00:01:19.445898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2131 00:01:19.446767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2133 00:01:19.543194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2134 00:01:19.544121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2136 00:01:19.632604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2137 00:01:19.633508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2139 00:01:19.723367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2140 00:01:19.724204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2142 00:01:19.817460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2143 00:01:19.818376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2145 00:01:19.912955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2146 00:01:19.913720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2148 00:01:20.004334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2149 00:01:20.005083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2151 00:01:20.093872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2152 00:01:20.094715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2154 00:01:20.188357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2155 00:01:20.189217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2157 00:01:20.277812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2158 00:01:20.278648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2160 00:01:20.373761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2161 00:01:20.374708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2163 00:01:20.467416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2164 00:01:20.468365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2166 00:01:20.563189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2167 00:01:20.564098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2169 00:01:20.680230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2170 00:01:20.681102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2172 00:01:20.784475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2173 00:01:20.785188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2175 00:01:20.882003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2176 00:01:20.882936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2178 00:01:20.977374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2179 00:01:20.978313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2181 00:01:21.070998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2182 00:01:21.071961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2184 00:01:21.163910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2185 00:01:21.164809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2187 00:01:21.260781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2188 00:01:21.261726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2190 00:01:21.363627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2191 00:01:21.364575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2193 00:01:21.462352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2194 00:01:21.463057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2196 00:01:21.560312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2197 00:01:21.561164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2199 00:01:21.649852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2200 00:01:21.650691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2202 00:01:21.739570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2203 00:01:21.740491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2205 00:01:21.831749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2206 00:01:21.832640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2208 00:01:21.920591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2209 00:01:21.921366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2211 00:01:22.009749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2212 00:01:22.010656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2214 00:01:22.106100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2215 00:01:22.106889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2217 00:01:22.190711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2218 00:01:22.191535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2220 00:01:22.285356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2221 00:01:22.286122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2223 00:01:22.374907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2224 00:01:22.375779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2226 00:01:22.466038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2227 00:01:22.467025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2229 00:01:22.562013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2230 00:01:22.562864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2232 00:01:22.681006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2233 00:01:22.681792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2235 00:01:22.778151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2236 00:01:22.778966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2238 00:01:22.873493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2239 00:01:22.874271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2241 00:01:22.965036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2242 00:01:22.965899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2244 00:01:23.058434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2245 00:01:23.059277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2247 00:01:23.146803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2248 00:01:23.147579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2250 00:01:23.235508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2251 00:01:23.236367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2253 00:01:23.325136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2254 00:01:23.325787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2256 00:01:23.414811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2257 00:01:23.415475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2259 00:01:23.503125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2260 00:01:23.504106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2262 00:01:23.598956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2263 00:01:23.599891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2265 00:01:23.694426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2266 00:01:23.695281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2268 00:01:23.790368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2269 00:01:23.791220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2271 00:01:23.881567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2273 00:01:23.884641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2274 00:01:23.972851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2275 00:01:23.973719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2277 00:01:24.067404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2278 00:01:24.068354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2280 00:01:24.160642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2281 00:01:24.161541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2283 00:01:24.255096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2284 00:01:24.256022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2286 00:01:24.348025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2287 00:01:24.349006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2289 00:01:24.437440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2290 00:01:24.438358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2292 00:01:24.532111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2293 00:01:24.533029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2295 00:01:24.627096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2296 00:01:24.628024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2298 00:01:24.721583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2299 00:01:24.722482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2301 00:01:24.810471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2302 00:01:24.811360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2304 00:01:24.904629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2305 00:01:24.905537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2307 00:01:24.993227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2308 00:01:24.993945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2310 00:01:25.086311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2311 00:01:25.086934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2313 00:01:25.180893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2314 00:01:25.181534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2316 00:01:25.276203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2317 00:01:25.277366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2319 00:01:25.366259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2320 00:01:25.367151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2322 00:01:25.455940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2323 00:01:25.456849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2325 00:01:25.548570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2326 00:01:25.549575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2328 00:01:25.638899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2329 00:01:25.639845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2331 00:01:25.729053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2332 00:01:25.729966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2334 00:01:25.822331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2335 00:01:25.823212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2337 00:01:25.910681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2338 00:01:25.911579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2340 00:01:25.998501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2342 00:01:26.001631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 00:01:26.097798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2344 00:01:26.098768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2346 00:01:26.191935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2347 00:01:26.193005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2349 00:01:26.278945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2350 00:01:26.279562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2352 00:01:26.368729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2353 00:01:26.369373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2355 00:01:26.463719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2356 00:01:26.464345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2358 00:01:26.554608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2359 00:01:26.555226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2361 00:01:26.649308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2362 00:01:26.649939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2364 00:01:26.740193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2365 00:01:26.740593 + set +x
2366 00:01:26.741094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2368 00:01:26.743497 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 892286_1.6.2.4.5>
2369 00:01:26.744136 Received signal: <ENDRUN> 1_kselftest-dt 892286_1.6.2.4.5
2370 00:01:26.744429 Ending use of test pattern.
2371 00:01:26.744646 Ending test lava.1_kselftest-dt (892286_1.6.2.4.5), duration 83.86
2373 00:01:26.748822 <LAVA_TEST_RUNNER EXIT>
2374 00:01:26.749339 ok: lava_test_shell seems to have completed
2375 00:01:26.756227 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2376 00:01:26.757288 end: 3.1 lava-test-shell (duration 00:01:26) [common]
2377 00:01:26.757616 end: 3 lava-test-retry (duration 00:01:26) [common]
2378 00:01:26.757929 start: 4 finalize (timeout 00:05:29) [common]
2379 00:01:26.758237 start: 4.1 power-off (timeout 00:00:30) [common]
2380 00:01:26.758770 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2381 00:01:26.791928 >> OK - accepted request
2382 00:01:26.793993 Returned 0 in 0 seconds
2383 00:01:26.894966 end: 4.1 power-off (duration 00:00:00) [common]
2385 00:01:26.896235 start: 4.2 read-feedback (timeout 00:05:29) [common]
2386 00:01:26.896923 Listened to connection for namespace 'common' for up to 1s
2387 00:01:26.897513 Listened to connection for namespace 'common' for up to 1s
2388 00:01:27.897556 Finalising connection for namespace 'common'
2389 00:01:27.898058 Disconnecting from shell: Finalise
2390 00:01:27.898343 / #
2391 00:01:27.999024 end: 4.2 read-feedback (duration 00:00:01) [common]
2392 00:01:27.999542 end: 4 finalize (duration 00:00:01) [common]
2393 00:01:27.999918 Cleaning after the job
2394 00:01:28.000420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/ramdisk
2395 00:01:28.002075 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/kernel
2396 00:01:28.003247 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/dtb
2397 00:01:28.004029 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/nfsrootfs
2398 00:01:28.024130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/892286/tftp-deploy-52zbqtjl/modules
2399 00:01:28.028242 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/892286
2400 00:01:31.317110 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/892286
2401 00:01:31.317670 Job finished correctly