Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:17:43.156933 lava-dispatcher, installed at version: 2024.01
2 03:17:43.158076 start: 0 validate
3 03:17:43.158603 Start time: 2024-10-22 03:17:43.158572+00:00 (UTC)
4 03:17:43.159154 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:17:43.159735 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:17:43.197075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:17:43.197682 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc4-47-gc2ee9f594da8%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 03:17:43.227059 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:17:43.227719 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc4-47-gc2ee9f594da8%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:17:43.260679 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:17:43.261206 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:17:43.295704 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:17:43.296238 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc4-47-gc2ee9f594da8%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 03:17:43.330161 validate duration: 0.17
16 03:17:43.331081 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:17:43.331452 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:17:43.331804 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:17:43.332426 Not decompressing ramdisk as can be used compressed.
20 03:17:43.332907 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 03:17:43.333219 saving as /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/ramdisk/initrd.cpio.gz
22 03:17:43.333514 total size: 5628182 (5 MB)
23 03:17:43.369243 progress 0 % (0 MB)
24 03:17:43.373875 progress 5 % (0 MB)
25 03:17:43.377995 progress 10 % (0 MB)
26 03:17:43.381689 progress 15 % (0 MB)
27 03:17:43.385752 progress 20 % (1 MB)
28 03:17:43.389405 progress 25 % (1 MB)
29 03:17:43.393447 progress 30 % (1 MB)
30 03:17:43.397563 progress 35 % (1 MB)
31 03:17:43.401194 progress 40 % (2 MB)
32 03:17:43.405155 progress 45 % (2 MB)
33 03:17:43.408795 progress 50 % (2 MB)
34 03:17:43.412804 progress 55 % (2 MB)
35 03:17:43.416786 progress 60 % (3 MB)
36 03:17:43.420431 progress 65 % (3 MB)
37 03:17:43.424392 progress 70 % (3 MB)
38 03:17:43.427824 progress 75 % (4 MB)
39 03:17:43.431550 progress 80 % (4 MB)
40 03:17:43.434842 progress 85 % (4 MB)
41 03:17:43.438543 progress 90 % (4 MB)
42 03:17:43.442124 progress 95 % (5 MB)
43 03:17:43.445377 progress 100 % (5 MB)
44 03:17:43.446013 5 MB downloaded in 0.11 s (47.72 MB/s)
45 03:17:43.446557 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:17:43.447426 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:17:43.447719 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:17:43.448008 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:17:43.448482 downloading http://storage.kernelci.org/mainline/master/v6.12-rc4-47-gc2ee9f594da8/arm64/defconfig/clang-16/kernel/Image
51 03:17:43.448725 saving as /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/kernel/Image
52 03:17:43.448931 total size: 37814784 (36 MB)
53 03:17:43.449140 No compression specified
54 03:17:43.485405 progress 0 % (0 MB)
55 03:17:43.508150 progress 5 % (1 MB)
56 03:17:43.530947 progress 10 % (3 MB)
57 03:17:43.553368 progress 15 % (5 MB)
58 03:17:43.575594 progress 20 % (7 MB)
59 03:17:43.598828 progress 25 % (9 MB)
60 03:17:43.621698 progress 30 % (10 MB)
61 03:17:43.643880 progress 35 % (12 MB)
62 03:17:43.666415 progress 40 % (14 MB)
63 03:17:43.689131 progress 45 % (16 MB)
64 03:17:43.712100 progress 50 % (18 MB)
65 03:17:43.735141 progress 55 % (19 MB)
66 03:17:43.759495 progress 60 % (21 MB)
67 03:17:43.783520 progress 65 % (23 MB)
68 03:17:43.806818 progress 70 % (25 MB)
69 03:17:43.830482 progress 75 % (27 MB)
70 03:17:43.852803 progress 80 % (28 MB)
71 03:17:43.874681 progress 85 % (30 MB)
72 03:17:43.897229 progress 90 % (32 MB)
73 03:17:43.919691 progress 95 % (34 MB)
74 03:17:43.940983 progress 100 % (36 MB)
75 03:17:43.941494 36 MB downloaded in 0.49 s (73.22 MB/s)
76 03:17:43.941966 end: 1.2.1 http-download (duration 00:00:00) [common]
78 03:17:43.942778 end: 1.2 download-retry (duration 00:00:00) [common]
79 03:17:43.943052 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:17:43.943316 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:17:43.943786 downloading http://storage.kernelci.org/mainline/master/v6.12-rc4-47-gc2ee9f594da8/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 03:17:43.944080 saving as /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/dtb/meson-g12b-a311d-libretech-cc.dtb
83 03:17:43.944292 total size: 54703 (0 MB)
84 03:17:43.944529 No compression specified
85 03:17:43.979886 progress 59 % (0 MB)
86 03:17:43.980823 progress 100 % (0 MB)
87 03:17:43.981432 0 MB downloaded in 0.04 s (1.41 MB/s)
88 03:17:43.981979 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:17:43.982894 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:17:43.983210 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:17:43.983522 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:17:43.984041 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 03:17:43.984331 saving as /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/nfsrootfs/full.rootfs.tar
95 03:17:43.984567 total size: 107552908 (102 MB)
96 03:17:43.984806 Using unxz to decompress xz
97 03:17:44.020392 progress 0 % (0 MB)
98 03:17:44.702072 progress 5 % (5 MB)
99 03:17:45.431705 progress 10 % (10 MB)
100 03:17:46.162037 progress 15 % (15 MB)
101 03:17:46.928299 progress 20 % (20 MB)
102 03:17:47.502791 progress 25 % (25 MB)
103 03:17:48.126673 progress 30 % (30 MB)
104 03:17:48.873823 progress 35 % (35 MB)
105 03:17:49.217838 progress 40 % (41 MB)
106 03:17:49.641377 progress 45 % (46 MB)
107 03:17:50.339079 progress 50 % (51 MB)
108 03:17:51.028453 progress 55 % (56 MB)
109 03:17:51.790479 progress 60 % (61 MB)
110 03:17:52.555129 progress 65 % (66 MB)
111 03:17:53.293393 progress 70 % (71 MB)
112 03:17:54.067430 progress 75 % (76 MB)
113 03:17:54.756031 progress 80 % (82 MB)
114 03:17:55.474906 progress 85 % (87 MB)
115 03:17:56.209075 progress 90 % (92 MB)
116 03:17:56.927618 progress 95 % (97 MB)
117 03:17:57.665900 progress 100 % (102 MB)
118 03:17:57.678233 102 MB downloaded in 13.69 s (7.49 MB/s)
119 03:17:57.678829 end: 1.4.1 http-download (duration 00:00:14) [common]
121 03:17:57.679694 end: 1.4 download-retry (duration 00:00:14) [common]
122 03:17:57.679977 start: 1.5 download-retry (timeout 00:09:46) [common]
123 03:17:57.680317 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 03:17:57.680899 downloading http://storage.kernelci.org/mainline/master/v6.12-rc4-47-gc2ee9f594da8/arm64/defconfig/clang-16/modules.tar.xz
125 03:17:57.681301 saving as /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/modules/modules.tar
126 03:17:57.681550 total size: 11768964 (11 MB)
127 03:17:57.681774 Using unxz to decompress xz
128 03:17:57.723574 progress 0 % (0 MB)
129 03:17:57.794705 progress 5 % (0 MB)
130 03:17:57.874845 progress 10 % (1 MB)
131 03:17:57.966530 progress 15 % (1 MB)
132 03:17:58.063372 progress 20 % (2 MB)
133 03:17:58.146534 progress 25 % (2 MB)
134 03:17:58.226853 progress 30 % (3 MB)
135 03:17:58.312453 progress 35 % (3 MB)
136 03:17:58.395177 progress 40 % (4 MB)
137 03:17:58.474880 progress 45 % (5 MB)
138 03:17:58.561065 progress 50 % (5 MB)
139 03:17:58.646613 progress 55 % (6 MB)
140 03:17:58.736395 progress 60 % (6 MB)
141 03:17:58.813808 progress 65 % (7 MB)
142 03:17:58.896470 progress 70 % (7 MB)
143 03:17:58.976275 progress 75 % (8 MB)
144 03:17:59.054298 progress 80 % (9 MB)
145 03:17:59.140687 progress 85 % (9 MB)
146 03:17:59.225049 progress 90 % (10 MB)
147 03:17:59.306276 progress 95 % (10 MB)
148 03:17:59.388960 progress 100 % (11 MB)
149 03:17:59.400368 11 MB downloaded in 1.72 s (6.53 MB/s)
150 03:17:59.401329 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:17:59.402439 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:17:59.402844 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 03:17:59.403184 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 03:18:09.974901 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/878987/extract-nfsrootfs-512ghbov
156 03:18:09.975520 end: 1.6.1 extract-nfsrootfs (duration 00:00:11) [common]
157 03:18:09.975859 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 03:18:09.976723 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq
159 03:18:09.977229 makedir: /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin
160 03:18:09.977574 makedir: /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/tests
161 03:18:09.977892 makedir: /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/results
162 03:18:09.978270 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-add-keys
163 03:18:09.978981 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-add-sources
164 03:18:09.979523 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-background-process-start
165 03:18:09.980045 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-background-process-stop
166 03:18:09.980607 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-common-functions
167 03:18:09.981109 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-echo-ipv4
168 03:18:09.981620 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-install-packages
169 03:18:09.982120 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-installed-packages
170 03:18:09.982603 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-os-build
171 03:18:09.983080 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-probe-channel
172 03:18:09.983558 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-probe-ip
173 03:18:09.984053 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-target-ip
174 03:18:09.984574 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-target-mac
175 03:18:09.985079 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-target-storage
176 03:18:09.985573 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-case
177 03:18:09.986057 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-event
178 03:18:09.986526 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-feedback
179 03:18:09.986999 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-raise
180 03:18:09.987469 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-reference
181 03:18:09.988007 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-runner
182 03:18:09.988557 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-set
183 03:18:09.989049 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-test-shell
184 03:18:09.989541 Updating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-install-packages (oe)
185 03:18:09.990187 Updating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/bin/lava-installed-packages (oe)
186 03:18:09.990691 Creating /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/environment
187 03:18:09.991081 LAVA metadata
188 03:18:09.991347 - LAVA_JOB_ID=878987
189 03:18:09.991560 - LAVA_DISPATCHER_IP=192.168.6.2
190 03:18:09.991939 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 03:18:09.993000 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 03:18:09.993327 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 03:18:09.993535 skipped lava-vland-overlay
194 03:18:09.993777 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 03:18:09.994033 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 03:18:09.994250 skipped lava-multinode-overlay
197 03:18:09.994489 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 03:18:09.994738 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 03:18:09.994990 Loading test definitions
200 03:18:09.995267 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 03:18:09.995488 Using /lava-878987 at stage 0
202 03:18:09.996812 uuid=878987_1.6.2.4.1 testdef=None
203 03:18:09.997140 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 03:18:09.997405 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 03:18:09.999215 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 03:18:10.000019 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 03:18:10.002320 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 03:18:10.003150 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 03:18:10.005399 runner path: /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/0/tests/0_dmesg test_uuid 878987_1.6.2.4.1
212 03:18:10.005985 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 03:18:10.006738 Creating lava-test-runner.conf files
215 03:18:10.006937 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/878987/lava-overlay-0mg7vpjq/lava-878987/0 for stage 0
216 03:18:10.007271 - 0_dmesg
217 03:18:10.007618 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 03:18:10.007892 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 03:18:10.029809 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 03:18:10.030234 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 03:18:10.030495 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 03:18:10.030760 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 03:18:10.031022 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 03:18:10.689977 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 03:18:10.690440 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 03:18:10.690687 extracting modules file /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/878987/extract-nfsrootfs-512ghbov
227 03:18:12.088532 extracting modules file /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/878987/extract-overlay-ramdisk-ik9hthsr/ramdisk
228 03:18:13.527819 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 03:18:13.528300 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 03:18:13.528576 [common] Applying overlay to NFS
231 03:18:13.528788 [common] Applying overlay /var/lib/lava/dispatcher/tmp/878987/compress-overlay-punk_zzv/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/878987/extract-nfsrootfs-512ghbov
232 03:18:13.558020 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 03:18:13.558446 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 03:18:13.558720 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 03:18:13.558951 Converting downloaded kernel to a uImage
236 03:18:13.559256 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/kernel/Image /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/kernel/uImage
237 03:18:13.944053 output: Image Name:
238 03:18:13.944482 output: Created: Tue Oct 22 03:18:13 2024
239 03:18:13.944690 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 03:18:13.944892 output: Data Size: 37814784 Bytes = 36928.50 KiB = 36.06 MiB
241 03:18:13.945092 output: Load Address: 01080000
242 03:18:13.945289 output: Entry Point: 01080000
243 03:18:13.945485 output:
244 03:18:13.945821 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 03:18:13.946084 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 03:18:13.946355 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 03:18:13.946607 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 03:18:13.946865 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 03:18:13.947130 Building ramdisk /var/lib/lava/dispatcher/tmp/878987/extract-overlay-ramdisk-ik9hthsr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/878987/extract-overlay-ramdisk-ik9hthsr/ramdisk
250 03:18:16.467154 >> 173394 blocks
251 03:18:24.197008 Adding RAMdisk u-boot header.
252 03:18:24.197711 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/878987/extract-overlay-ramdisk-ik9hthsr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/878987/extract-overlay-ramdisk-ik9hthsr/ramdisk.cpio.gz.uboot
253 03:18:24.454830 output: Image Name:
254 03:18:24.455242 output: Created: Tue Oct 22 03:18:24 2024
255 03:18:24.455455 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 03:18:24.455661 output: Data Size: 24133197 Bytes = 23567.58 KiB = 23.02 MiB
257 03:18:24.455860 output: Load Address: 00000000
258 03:18:24.456404 output: Entry Point: 00000000
259 03:18:24.456882 output:
260 03:18:24.457985 rename /var/lib/lava/dispatcher/tmp/878987/extract-overlay-ramdisk-ik9hthsr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot
261 03:18:24.458766 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 03:18:24.459356 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 03:18:24.459886 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 03:18:24.460397 No LXC device requested
265 03:18:24.460899 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 03:18:24.461411 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 03:18:24.461907 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 03:18:24.462317 Checking files for TFTP limit of 4294967296 bytes.
269 03:18:24.464988 end: 1 tftp-deploy (duration 00:00:41) [common]
270 03:18:24.465585 start: 2 uboot-action (timeout 00:05:00) [common]
271 03:18:24.466109 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 03:18:24.466603 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 03:18:24.467104 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 03:18:24.467626 Using kernel file from prepare-kernel: 878987/tftp-deploy-2rtsprmb/kernel/uImage
275 03:18:24.468282 substitutions:
276 03:18:24.468694 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 03:18:24.469096 - {DTB_ADDR}: 0x01070000
278 03:18:24.469490 - {DTB}: 878987/tftp-deploy-2rtsprmb/dtb/meson-g12b-a311d-libretech-cc.dtb
279 03:18:24.469885 - {INITRD}: 878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot
280 03:18:24.470278 - {KERNEL_ADDR}: 0x01080000
281 03:18:24.470665 - {KERNEL}: 878987/tftp-deploy-2rtsprmb/kernel/uImage
282 03:18:24.471055 - {LAVA_MAC}: None
283 03:18:24.471482 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/878987/extract-nfsrootfs-512ghbov
284 03:18:24.471876 - {NFS_SERVER_IP}: 192.168.6.2
285 03:18:24.472292 - {PRESEED_CONFIG}: None
286 03:18:24.472678 - {PRESEED_LOCAL}: None
287 03:18:24.473061 - {RAMDISK_ADDR}: 0x08000000
288 03:18:24.473444 - {RAMDISK}: 878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot
289 03:18:24.473828 - {ROOT_PART}: None
290 03:18:24.474211 - {ROOT}: None
291 03:18:24.474596 - {SERVER_IP}: 192.168.6.2
292 03:18:24.474977 - {TEE_ADDR}: 0x83000000
293 03:18:24.475358 - {TEE}: None
294 03:18:24.475741 Parsed boot commands:
295 03:18:24.476140 - setenv autoload no
296 03:18:24.476525 - setenv initrd_high 0xffffffff
297 03:18:24.476912 - setenv fdt_high 0xffffffff
298 03:18:24.477297 - dhcp
299 03:18:24.477676 - setenv serverip 192.168.6.2
300 03:18:24.478069 - tftpboot 0x01080000 878987/tftp-deploy-2rtsprmb/kernel/uImage
301 03:18:24.478486 - tftpboot 0x08000000 878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot
302 03:18:24.478906 - tftpboot 0x01070000 878987/tftp-deploy-2rtsprmb/dtb/meson-g12b-a311d-libretech-cc.dtb
303 03:18:24.479330 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/878987/extract-nfsrootfs-512ghbov,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 03:18:24.479769 - bootm 0x01080000 0x08000000 0x01070000
305 03:18:24.480325 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 03:18:24.481805 start: 2.3 connect-device (timeout 00:05:00) [common]
308 03:18:24.482221 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 03:18:24.497429 Setting prompt string to ['lava-test: # ']
310 03:18:24.498906 end: 2.3 connect-device (duration 00:00:00) [common]
311 03:18:24.499490 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 03:18:24.500085 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 03:18:24.500670 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 03:18:24.501889 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 03:18:24.539956 >> OK - accepted request
316 03:18:24.542230 Returned 0 in 0 seconds
317 03:18:24.643398 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 03:18:24.645107 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 03:18:24.645682 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 03:18:24.646187 Setting prompt string to ['Hit any key to stop autoboot']
322 03:18:24.646649 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 03:18:24.648348 Trying 192.168.56.21...
324 03:18:24.648878 Connected to conserv1.
325 03:18:24.649289 Escape character is '^]'.
326 03:18:24.649702
327 03:18:24.650119 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 03:18:24.650539
329 03:18:35.713040 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 03:18:35.713698 bl2_stage_init 0x01
331 03:18:35.714133 bl2_stage_init 0x81
332 03:18:35.718680 hw id: 0x0000 - pwm id 0x01
333 03:18:35.719059 bl2_stage_init 0xc1
334 03:18:35.719280 bl2_stage_init 0x02
335 03:18:35.719509
336 03:18:35.724271 L0:00000000
337 03:18:35.724816 L1:20000703
338 03:18:35.725220 L2:00008067
339 03:18:35.725619 L3:14000000
340 03:18:35.729770 B2:00402000
341 03:18:35.730267 B1:e0f83180
342 03:18:35.730666
343 03:18:35.731059 TE: 58124
344 03:18:35.731450
345 03:18:35.735415 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 03:18:35.735928
347 03:18:35.736368 Board ID = 1
348 03:18:35.740983 Set A53 clk to 24M
349 03:18:35.741463 Set A73 clk to 24M
350 03:18:35.741856 Set clk81 to 24M
351 03:18:35.746538 A53 clk: 1200 MHz
352 03:18:35.747088 A73 clk: 1200 MHz
353 03:18:35.747477 CLK81: 166.6M
354 03:18:35.747859 smccc: 00012a92
355 03:18:35.752293 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 03:18:35.757746 board id: 1
357 03:18:35.763582 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 03:18:35.774278 fw parse done
359 03:18:35.780320 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 03:18:35.822715 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 03:18:35.833620 PIEI prepare done
362 03:18:35.834093 fastboot data load
363 03:18:35.834491 fastboot data verify
364 03:18:35.839298 verify result: 266
365 03:18:35.844932 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 03:18:35.845468 LPDDR4 probe
367 03:18:35.845887 ddr clk to 1584MHz
368 03:18:35.851962 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 03:18:35.890426
370 03:18:35.890999 dmc_version 0001
371 03:18:35.896815 Check phy result
372 03:18:35.902648 INFO : End of CA training
373 03:18:35.903127 INFO : End of initialization
374 03:18:35.908285 INFO : Training has run successfully!
375 03:18:35.908769 Check phy result
376 03:18:35.913900 INFO : End of initialization
377 03:18:35.914380 INFO : End of read enable training
378 03:18:35.917165 INFO : End of fine write leveling
379 03:18:35.922685 INFO : End of Write leveling coarse delay
380 03:18:35.928284 INFO : Training has run successfully!
381 03:18:35.928758 Check phy result
382 03:18:35.929169 INFO : End of initialization
383 03:18:35.933902 INFO : End of read dq deskew training
384 03:18:35.939482 INFO : End of MPR read delay center optimization
385 03:18:35.939965 INFO : End of write delay center optimization
386 03:18:35.945168 INFO : End of read delay center optimization
387 03:18:35.950700 INFO : End of max read latency training
388 03:18:35.951183 INFO : Training has run successfully!
389 03:18:35.956315 1D training succeed
390 03:18:35.962286 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 03:18:36.009855 Check phy result
392 03:18:36.010365 INFO : End of initialization
393 03:18:36.031440 INFO : End of 2D read delay Voltage center optimization
394 03:18:36.051581 INFO : End of 2D read delay Voltage center optimization
395 03:18:36.103583 INFO : End of 2D write delay Voltage center optimization
396 03:18:36.152693 INFO : End of 2D write delay Voltage center optimization
397 03:18:36.158271 INFO : Training has run successfully!
398 03:18:36.158750
399 03:18:36.159171 channel==0
400 03:18:36.163845 RxClkDly_Margin_A0==88 ps 9
401 03:18:36.164378 TxDqDly_Margin_A0==98 ps 10
402 03:18:36.169452 RxClkDly_Margin_A1==88 ps 9
403 03:18:36.169927 TxDqDly_Margin_A1==98 ps 10
404 03:18:36.170347 TrainedVREFDQ_A0==74
405 03:18:36.175186 TrainedVREFDQ_A1==74
406 03:18:36.175657 VrefDac_Margin_A0==25
407 03:18:36.176100 DeviceVref_Margin_A0==40
408 03:18:36.180698 VrefDac_Margin_A1==25
409 03:18:36.181172 DeviceVref_Margin_A1==40
410 03:18:36.181576
411 03:18:36.181977
412 03:18:36.186283 channel==1
413 03:18:36.186758 RxClkDly_Margin_A0==98 ps 10
414 03:18:36.187170 TxDqDly_Margin_A0==88 ps 9
415 03:18:36.191949 RxClkDly_Margin_A1==98 ps 10
416 03:18:36.192458 TxDqDly_Margin_A1==88 ps 9
417 03:18:36.197479 TrainedVREFDQ_A0==76
418 03:18:36.197955 TrainedVREFDQ_A1==77
419 03:18:36.198368 VrefDac_Margin_A0==22
420 03:18:36.203208 DeviceVref_Margin_A0==38
421 03:18:36.203673 VrefDac_Margin_A1==24
422 03:18:36.208642 DeviceVref_Margin_A1==37
423 03:18:36.209112
424 03:18:36.209520 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 03:18:36.209923
426 03:18:36.242235 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 03:18:36.242823 2D training succeed
428 03:18:36.247843 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 03:18:36.253475 auto size-- 65535DDR cs0 size: 2048MB
430 03:18:36.253954 DDR cs1 size: 2048MB
431 03:18:36.259062 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 03:18:36.259565 cs0 DataBus test pass
433 03:18:36.264673 cs1 DataBus test pass
434 03:18:36.265261 cs0 AddrBus test pass
435 03:18:36.265735 cs1 AddrBus test pass
436 03:18:36.266188
437 03:18:36.270217 100bdlr_step_size ps== 420
438 03:18:36.270724 result report
439 03:18:36.275830 boot times 0Enable ddr reg access
440 03:18:36.281244 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 03:18:36.294444 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 03:18:36.866707 0.0;M3 CHK:0;cm4_sp_mode 0
443 03:18:36.867338 MVN_1=0x00000000
444 03:18:36.872202 MVN_2=0x00000000
445 03:18:36.877943 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 03:18:36.878452 OPS=0x10
447 03:18:36.878913 ring efuse init
448 03:18:36.879373 chipver efuse init
449 03:18:36.883502 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 03:18:36.889210 [0.018961 Inits done]
451 03:18:36.889715 secure task start!
452 03:18:36.890175 high task start!
453 03:18:36.893656 low task start!
454 03:18:36.894139 run into bl31
455 03:18:36.900275 NOTICE: BL31: v1.3(release):4fc40b1
456 03:18:36.908080 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 03:18:36.908582 NOTICE: BL31: G12A normal boot!
458 03:18:36.933524 NOTICE: BL31: BL33 decompress pass
459 03:18:36.939273 ERROR: Error initializing runtime service opteed_fast
460 03:18:38.172143
461 03:18:38.172824
462 03:18:38.180459 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 03:18:38.180955
464 03:18:38.181417 Model: Libre Computer AML-A311D-CC Alta
465 03:18:38.388961 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 03:18:38.412283 DRAM: 2 GiB (effective 3.8 GiB)
467 03:18:38.555360 Core: 408 devices, 31 uclasses, devicetree: separate
468 03:18:38.561132 WDT: Not starting watchdog@f0d0
469 03:18:38.593475 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 03:18:38.605850 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 03:18:38.609952 ** Bad device specification mmc 0 **
472 03:18:38.621161 Card did not respond to voltage select! : -110
473 03:18:38.628807 ** Bad device specification mmc 0 **
474 03:18:38.629297 Couldn't find partition mmc 0
475 03:18:38.637174 Card did not respond to voltage select! : -110
476 03:18:38.642683 ** Bad device specification mmc 0 **
477 03:18:38.643163 Couldn't find partition mmc 0
478 03:18:38.647717 Error: could not access storage.
479 03:18:39.913406 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 03:18:39.914058 bl2_stage_init 0x01
481 03:18:39.914524 bl2_stage_init 0x81
482 03:18:39.918921 hw id: 0x0000 - pwm id 0x01
483 03:18:39.919433 bl2_stage_init 0xc1
484 03:18:39.919884 bl2_stage_init 0x02
485 03:18:39.920376
486 03:18:39.924621 L0:00000000
487 03:18:39.925129 L1:20000703
488 03:18:39.925582 L2:00008067
489 03:18:39.926024 L3:14000000
490 03:18:39.927452 B2:00402000
491 03:18:39.927921 B1:e0f83180
492 03:18:39.928425
493 03:18:39.928888 TE: 58159
494 03:18:39.929328
495 03:18:39.938703 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 03:18:39.939266
497 03:18:39.939726 Board ID = 1
498 03:18:39.940215 Set A53 clk to 24M
499 03:18:39.940660 Set A73 clk to 24M
500 03:18:39.944298 Set clk81 to 24M
501 03:18:39.944797 A53 clk: 1200 MHz
502 03:18:39.945247 A73 clk: 1200 MHz
503 03:18:39.949822 CLK81: 166.6M
504 03:18:39.950295 smccc: 00012ab5
505 03:18:39.955417 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 03:18:39.955899 board id: 1
507 03:18:39.964044 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 03:18:39.974667 fw parse done
509 03:18:39.980455 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 03:18:40.023307 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 03:18:40.034211 PIEI prepare done
512 03:18:40.034709 fastboot data load
513 03:18:40.035162 fastboot data verify
514 03:18:40.039751 verify result: 266
515 03:18:40.045456 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 03:18:40.045965 LPDDR4 probe
517 03:18:40.046416 ddr clk to 1584MHz
518 03:18:40.052981 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 03:18:40.090598
520 03:18:40.091122 dmc_version 0001
521 03:18:40.097385 Check phy result
522 03:18:40.103208 INFO : End of CA training
523 03:18:40.103740 INFO : End of initialization
524 03:18:40.108944 INFO : Training has run successfully!
525 03:18:40.109429 Check phy result
526 03:18:40.114471 INFO : End of initialization
527 03:18:40.114999 INFO : End of read enable training
528 03:18:40.120061 INFO : End of fine write leveling
529 03:18:40.125677 INFO : End of Write leveling coarse delay
530 03:18:40.126165 INFO : Training has run successfully!
531 03:18:40.126615 Check phy result
532 03:18:40.131326 INFO : End of initialization
533 03:18:40.131825 INFO : End of read dq deskew training
534 03:18:40.136847 INFO : End of MPR read delay center optimization
535 03:18:40.142361 INFO : End of write delay center optimization
536 03:18:40.148022 INFO : End of read delay center optimization
537 03:18:40.148517 INFO : End of max read latency training
538 03:18:40.153618 INFO : Training has run successfully!
539 03:18:40.154145 1D training succeed
540 03:18:40.162794 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 03:18:40.210535 Check phy result
542 03:18:40.211137 INFO : End of initialization
543 03:18:40.232832 INFO : End of 2D read delay Voltage center optimization
544 03:18:40.252950 INFO : End of 2D read delay Voltage center optimization
545 03:18:40.304995 INFO : End of 2D write delay Voltage center optimization
546 03:18:40.354076 INFO : End of 2D write delay Voltage center optimization
547 03:18:40.359868 INFO : Training has run successfully!
548 03:18:40.360404
549 03:18:40.360856 channel==0
550 03:18:40.365252 RxClkDly_Margin_A0==88 ps 9
551 03:18:40.365775 TxDqDly_Margin_A0==98 ps 10
552 03:18:40.370809 RxClkDly_Margin_A1==88 ps 9
553 03:18:40.371288 TxDqDly_Margin_A1==98 ps 10
554 03:18:40.371739 TrainedVREFDQ_A0==74
555 03:18:40.376462 TrainedVREFDQ_A1==74
556 03:18:40.376959 VrefDac_Margin_A0==24
557 03:18:40.377408 DeviceVref_Margin_A0==40
558 03:18:40.382004 VrefDac_Margin_A1==24
559 03:18:40.382490 DeviceVref_Margin_A1==40
560 03:18:40.382936
561 03:18:40.383374
562 03:18:40.387740 channel==1
563 03:18:40.388238 RxClkDly_Margin_A0==98 ps 10
564 03:18:40.388682 TxDqDly_Margin_A0==98 ps 10
565 03:18:40.393193 RxClkDly_Margin_A1==98 ps 10
566 03:18:40.393666 TxDqDly_Margin_A1==98 ps 10
567 03:18:40.398850 TrainedVREFDQ_A0==77
568 03:18:40.399389 TrainedVREFDQ_A1==78
569 03:18:40.399857 VrefDac_Margin_A0==22
570 03:18:40.404485 DeviceVref_Margin_A0==37
571 03:18:40.404979 VrefDac_Margin_A1==22
572 03:18:40.409951 DeviceVref_Margin_A1==36
573 03:18:40.410422
574 03:18:40.410875 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 03:18:40.415693
576 03:18:40.443727 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 03:18:40.444331 2D training succeed
578 03:18:40.449234 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 03:18:40.454734 auto size-- 65535DDR cs0 size: 2048MB
580 03:18:40.455216 DDR cs1 size: 2048MB
581 03:18:40.460430 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 03:18:40.460905 cs0 DataBus test pass
583 03:18:40.465987 cs1 DataBus test pass
584 03:18:40.466458 cs0 AddrBus test pass
585 03:18:40.466906 cs1 AddrBus test pass
586 03:18:40.467346
587 03:18:40.471714 100bdlr_step_size ps== 420
588 03:18:40.472312 result report
589 03:18:40.477190 boot times 0Enable ddr reg access
590 03:18:40.482842 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 03:18:40.496254 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 03:18:41.068527 0.0;M3 CHK:0;cm4_sp_mode 0
593 03:18:41.069196 MVN_1=0x00000000
594 03:18:41.074077 MVN_2=0x00000000
595 03:18:41.079803 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 03:18:41.080392 OPS=0x10
597 03:18:41.080878 ring efuse init
598 03:18:41.081364 chipver efuse init
599 03:18:41.088063 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 03:18:41.088604 [0.018960 Inits done]
601 03:18:41.089038 secure task start!
602 03:18:41.095475 high task start!
603 03:18:41.095952 low task start!
604 03:18:41.096424 run into bl31
605 03:18:41.102196 NOTICE: BL31: v1.3(release):4fc40b1
606 03:18:41.109990 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 03:18:41.110476 NOTICE: BL31: G12A normal boot!
608 03:18:41.135480 NOTICE: BL31: BL33 decompress pass
609 03:18:41.141175 ERROR: Error initializing runtime service opteed_fast
610 03:18:42.374092
611 03:18:42.374706
612 03:18:42.382451 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 03:18:42.382955
614 03:18:42.383392 Model: Libre Computer AML-A311D-CC Alta
615 03:18:42.591043 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 03:18:42.614287 DRAM: 2 GiB (effective 3.8 GiB)
617 03:18:42.757054 Core: 408 devices, 31 uclasses, devicetree: separate
618 03:18:42.763128 WDT: Not starting watchdog@f0d0
619 03:18:42.795305 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 03:18:42.807714 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 03:18:42.812547 ** Bad device specification mmc 0 **
622 03:18:42.822909 Card did not respond to voltage select! : -110
623 03:18:42.829840 ** Bad device specification mmc 0 **
624 03:18:42.830361 Couldn't find partition mmc 0
625 03:18:42.838906 Card did not respond to voltage select! : -110
626 03:18:42.844425 ** Bad device specification mmc 0 **
627 03:18:42.844861 Couldn't find partition mmc 0
628 03:18:42.849507 Error: could not access storage.
629 03:18:43.193285 Net: eth0: ethernet@ff3f0000
630 03:18:43.193890 starting USB...
631 03:18:43.444943 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 03:18:43.445565 Starting the controller
633 03:18:43.451961 USB XHCI 1.10
634 03:18:45.165341 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 03:18:45.165756 bl2_stage_init 0x01
636 03:18:45.166168 bl2_stage_init 0x81
637 03:18:45.170782 hw id: 0x0000 - pwm id 0x01
638 03:18:45.171244 bl2_stage_init 0xc1
639 03:18:45.171657 bl2_stage_init 0x02
640 03:18:45.172114
641 03:18:45.176501 L0:00000000
642 03:18:45.176951 L1:20000703
643 03:18:45.177358 L2:00008067
644 03:18:45.177760 L3:14000000
645 03:18:45.181957 B2:00402000
646 03:18:45.182397 B1:e0f83180
647 03:18:45.182795
648 03:18:45.183191 TE: 58167
649 03:18:45.183588
650 03:18:45.187537 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 03:18:45.188016
652 03:18:45.188428 Board ID = 1
653 03:18:45.193190 Set A53 clk to 24M
654 03:18:45.193629 Set A73 clk to 24M
655 03:18:45.194029 Set clk81 to 24M
656 03:18:45.199055 A53 clk: 1200 MHz
657 03:18:45.199493 A73 clk: 1200 MHz
658 03:18:45.199897 CLK81: 166.6M
659 03:18:45.200331 smccc: 00012abe
660 03:18:45.204460 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 03:18:45.210023 board id: 1
662 03:18:45.215846 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 03:18:45.226391 fw parse done
664 03:18:45.232498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 03:18:45.275006 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 03:18:45.285943 PIEI prepare done
667 03:18:45.286401 fastboot data load
668 03:18:45.286813 fastboot data verify
669 03:18:45.291650 verify result: 266
670 03:18:45.297382 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 03:18:45.297834 LPDDR4 probe
672 03:18:45.298243 ddr clk to 1584MHz
673 03:18:45.305156 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 03:18:45.342453
675 03:18:45.342937 dmc_version 0001
676 03:18:45.349174 Check phy result
677 03:18:45.355011 INFO : End of CA training
678 03:18:45.355447 INFO : End of initialization
679 03:18:45.360647 INFO : Training has run successfully!
680 03:18:45.361149 Check phy result
681 03:18:45.366192 INFO : End of initialization
682 03:18:45.366627 INFO : End of read enable training
683 03:18:45.369569 INFO : End of fine write leveling
684 03:18:45.374998 INFO : End of Write leveling coarse delay
685 03:18:45.380686 INFO : Training has run successfully!
686 03:18:45.381125 Check phy result
687 03:18:45.381527 INFO : End of initialization
688 03:18:45.386228 INFO : End of read dq deskew training
689 03:18:45.392070 INFO : End of MPR read delay center optimization
690 03:18:45.392506 INFO : End of write delay center optimization
691 03:18:45.397512 INFO : End of read delay center optimization
692 03:18:45.403148 INFO : End of max read latency training
693 03:18:45.403580 INFO : Training has run successfully!
694 03:18:45.408692 1D training succeed
695 03:18:45.414631 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 03:18:45.462189 Check phy result
697 03:18:45.462700 INFO : End of initialization
698 03:18:45.483918 INFO : End of 2D read delay Voltage center optimization
699 03:18:45.504119 INFO : End of 2D read delay Voltage center optimization
700 03:18:45.556471 INFO : End of 2D write delay Voltage center optimization
701 03:18:45.605670 INFO : End of 2D write delay Voltage center optimization
702 03:18:45.611110 INFO : Training has run successfully!
703 03:18:45.611566
704 03:18:45.612013 channel==0
705 03:18:45.616798 RxClkDly_Margin_A0==88 ps 9
706 03:18:45.617252 TxDqDly_Margin_A0==98 ps 10
707 03:18:45.620071 RxClkDly_Margin_A1==88 ps 9
708 03:18:45.620500 TxDqDly_Margin_A1==98 ps 10
709 03:18:45.625648 TrainedVREFDQ_A0==74
710 03:18:45.626091 TrainedVREFDQ_A1==75
711 03:18:45.626495 VrefDac_Margin_A0==25
712 03:18:45.631289 DeviceVref_Margin_A0==40
713 03:18:45.631754 VrefDac_Margin_A1==25
714 03:18:45.636850 DeviceVref_Margin_A1==39
715 03:18:45.637286
716 03:18:45.637688
717 03:18:45.638084 channel==1
718 03:18:45.638474 RxClkDly_Margin_A0==98 ps 10
719 03:18:45.642460 TxDqDly_Margin_A0==88 ps 9
720 03:18:45.642904 RxClkDly_Margin_A1==98 ps 10
721 03:18:45.647966 TxDqDly_Margin_A1==88 ps 9
722 03:18:45.648448 TrainedVREFDQ_A0==77
723 03:18:45.648854 TrainedVREFDQ_A1==77
724 03:18:45.653583 VrefDac_Margin_A0==22
725 03:18:45.654017 DeviceVref_Margin_A0==37
726 03:18:45.659376 VrefDac_Margin_A1==22
727 03:18:45.659858 DeviceVref_Margin_A1==37
728 03:18:45.660328
729 03:18:45.664842 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 03:18:45.665287
731 03:18:45.692764 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 03:18:45.698447 2D training succeed
733 03:18:45.704090 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 03:18:45.704571 auto size-- 65535DDR cs0 size: 2048MB
735 03:18:45.710341 DDR cs1 size: 2048MB
736 03:18:45.710789 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 03:18:45.715165 cs0 DataBus test pass
738 03:18:45.715598 cs1 DataBus test pass
739 03:18:45.716032 cs0 AddrBus test pass
740 03:18:45.720866 cs1 AddrBus test pass
741 03:18:45.721408
742 03:18:45.721820 100bdlr_step_size ps== 420
743 03:18:45.722225 result report
744 03:18:45.726481 boot times 0Enable ddr reg access
745 03:18:45.734561 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 03:18:45.747669 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 03:18:46.321150 0.0;M3 CHK:0;cm4_sp_mode 0
748 03:18:46.321905 MVN_1=0x00000000
749 03:18:46.326715 MVN_2=0x00000000
750 03:18:46.332610 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 03:18:46.333122 OPS=0x10
752 03:18:46.333623 ring efuse init
753 03:18:46.334042 chipver efuse init
754 03:18:46.338087 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 03:18:46.343785 [0.018961 Inits done]
756 03:18:46.344370 secure task start!
757 03:18:46.344803 high task start!
758 03:18:46.348175 low task start!
759 03:18:46.348638 run into bl31
760 03:18:46.354833 NOTICE: BL31: v1.3(release):4fc40b1
761 03:18:46.362658 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 03:18:46.363160 NOTICE: BL31: G12A normal boot!
763 03:18:46.388012 NOTICE: BL31: BL33 decompress pass
764 03:18:46.393663 ERROR: Error initializing runtime service opteed_fast
765 03:18:47.627231
766 03:18:47.627858
767 03:18:47.635096 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 03:18:47.635604
769 03:18:47.636047 Model: Libre Computer AML-A311D-CC Alta
770 03:18:47.843468 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 03:18:47.866915 DRAM: 2 GiB (effective 3.8 GiB)
772 03:18:48.009907 Core: 408 devices, 31 uclasses, devicetree: separate
773 03:18:48.015743 WDT: Not starting watchdog@f0d0
774 03:18:48.048025 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 03:18:48.060599 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 03:18:48.065536 ** Bad device specification mmc 0 **
777 03:18:48.076875 Card did not respond to voltage select! : -110
778 03:18:48.083512 ** Bad device specification mmc 0 **
779 03:18:48.084109 Couldn't find partition mmc 0
780 03:18:48.091905 Card did not respond to voltage select! : -110
781 03:18:48.097300 ** Bad device specification mmc 0 **
782 03:18:48.097845 Couldn't find partition mmc 0
783 03:18:48.102432 Error: could not access storage.
784 03:18:48.444822 Net: eth0: ethernet@ff3f0000
785 03:18:48.445432 starting USB...
786 03:18:48.696635 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 03:18:48.697248 Starting the controller
788 03:18:48.703829 USB XHCI 1.10
789 03:18:50.845492 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 03:18:50.846090 bl2_stage_init 0x01
791 03:18:50.846524 bl2_stage_init 0x81
792 03:18:50.850851 hw id: 0x0000 - pwm id 0x01
793 03:18:50.851329 bl2_stage_init 0xc1
794 03:18:50.852860 bl2_stage_init 0x02
795 03:18:50.853297
796 03:18:50.856464 L0:00000000
797 03:18:50.856934 L1:20000703
798 03:18:50.857345 L2:00008067
799 03:18:50.857746 L3:14000000
800 03:18:50.859628 B2:00402000
801 03:18:50.860105 B1:e0f83180
802 03:18:50.860533
803 03:18:50.860954 TE: 58124
804 03:18:50.862528
805 03:18:50.870146 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 03:18:50.870631
807 03:18:50.871046 Board ID = 1
808 03:18:50.871449 Set A53 clk to 24M
809 03:18:50.875836 Set A73 clk to 24M
810 03:18:50.876357 Set clk81 to 24M
811 03:18:50.876774 A53 clk: 1200 MHz
812 03:18:50.877176 A73 clk: 1200 MHz
813 03:18:50.881012 CLK81: 166.6M
814 03:18:50.881585 smccc: 00012a92
815 03:18:50.886675 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 03:18:50.887149 board id: 1
817 03:18:50.895106 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 03:18:50.906180 fw parse done
819 03:18:50.912175 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 03:18:50.953799 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 03:18:50.965865 PIEI prepare done
822 03:18:50.966571 fastboot data load
823 03:18:50.967359 fastboot data verify
824 03:18:50.971510 verify result: 266
825 03:18:50.977096 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 03:18:50.977769 LPDDR4 probe
827 03:18:50.978326 ddr clk to 1584MHz
828 03:18:50.985001 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 03:18:51.021353
830 03:18:51.022052 dmc_version 0001
831 03:18:51.028070 Check phy result
832 03:18:51.035036 INFO : End of CA training
833 03:18:51.035741 INFO : End of initialization
834 03:18:51.040549 INFO : Training has run successfully!
835 03:18:51.041228 Check phy result
836 03:18:51.046160 INFO : End of initialization
837 03:18:51.046834 INFO : End of read enable training
838 03:18:51.049481 INFO : End of fine write leveling
839 03:18:51.055130 INFO : End of Write leveling coarse delay
840 03:18:51.061197 INFO : Training has run successfully!
841 03:18:51.061881 Check phy result
842 03:18:51.062436 INFO : End of initialization
843 03:18:51.066189 INFO : End of read dq deskew training
844 03:18:51.069631 INFO : End of MPR read delay center optimization
845 03:18:51.075132 INFO : End of write delay center optimization
846 03:18:51.080878 INFO : End of read delay center optimization
847 03:18:51.081587 INFO : End of max read latency training
848 03:18:51.086359 INFO : Training has run successfully!
849 03:18:51.087022 1D training succeed
850 03:18:51.094448 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 03:18:51.141063 Check phy result
852 03:18:51.141788 INFO : End of initialization
853 03:18:51.162861 INFO : End of 2D read delay Voltage center optimization
854 03:18:51.183793 INFO : End of 2D read delay Voltage center optimization
855 03:18:51.235647 INFO : End of 2D write delay Voltage center optimization
856 03:18:51.284912 INFO : End of 2D write delay Voltage center optimization
857 03:18:51.290462 INFO : Training has run successfully!
858 03:18:51.291138
859 03:18:51.291711 channel==0
860 03:18:51.296454 RxClkDly_Margin_A0==88 ps 9
861 03:18:51.297144 TxDqDly_Margin_A0==98 ps 10
862 03:18:51.299380 RxClkDly_Margin_A1==88 ps 9
863 03:18:51.300083 TxDqDly_Margin_A1==98 ps 10
864 03:18:51.305037 TrainedVREFDQ_A0==74
865 03:18:51.305730 TrainedVREFDQ_A1==74
866 03:18:51.306286 VrefDac_Margin_A0==25
867 03:18:51.310605 DeviceVref_Margin_A0==40
868 03:18:51.311276 VrefDac_Margin_A1==25
869 03:18:51.316234 DeviceVref_Margin_A1==40
870 03:18:51.316778
871 03:18:51.317206
872 03:18:51.317617 channel==1
873 03:18:51.318016 RxClkDly_Margin_A0==98 ps 10
874 03:18:51.319527 TxDqDly_Margin_A0==88 ps 9
875 03:18:51.325127 RxClkDly_Margin_A1==98 ps 10
876 03:18:51.325660 TxDqDly_Margin_A1==98 ps 10
877 03:18:51.326101 TrainedVREFDQ_A0==77
878 03:18:51.330643 TrainedVREFDQ_A1==78
879 03:18:51.331178 VrefDac_Margin_A0==22
880 03:18:51.336363 DeviceVref_Margin_A0==37
881 03:18:51.336892 VrefDac_Margin_A1==22
882 03:18:51.337302 DeviceVref_Margin_A1==36
883 03:18:51.337698
884 03:18:51.341911 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 03:18:51.342463
886 03:18:51.375386 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 03:18:51.375955 2D training succeed
888 03:18:51.381351 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 03:18:51.386614 auto size-- 65535DDR cs0 size: 2048MB
890 03:18:51.387116 DDR cs1 size: 2048MB
891 03:18:51.392311 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 03:18:51.392819 cs0 DataBus test pass
893 03:18:51.393268 cs1 DataBus test pass
894 03:18:51.397816 cs0 AddrBus test pass
895 03:18:51.398330 cs1 AddrBus test pass
896 03:18:51.398719
897 03:18:51.403429 100bdlr_step_size ps== 420
898 03:18:51.403930 result report
899 03:18:51.404372 boot times 0Enable ddr reg access
900 03:18:51.413372 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 03:18:51.426792 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 03:18:51.998796 0.0;M3 CHK:0;cm4_sp_mode 0
903 03:18:51.999381 MVN_1=0x00000000
904 03:18:52.005055 MVN_2=0x00000000
905 03:18:52.010089 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 03:18:52.010551 OPS=0x10
907 03:18:52.010951 ring efuse init
908 03:18:52.011342 chipver efuse init
909 03:18:52.018305 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 03:18:52.018793 [0.018961 Inits done]
911 03:18:52.025765 secure task start!
912 03:18:52.026227 high task start!
913 03:18:52.026620 low task start!
914 03:18:52.027006 run into bl31
915 03:18:52.032484 NOTICE: BL31: v1.3(release):4fc40b1
916 03:18:52.040398 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 03:18:52.040876 NOTICE: BL31: G12A normal boot!
918 03:18:52.065642 NOTICE: BL31: BL33 decompress pass
919 03:18:52.070771 ERROR: Error initializing runtime service opteed_fast
920 03:18:53.304297
921 03:18:53.305052
922 03:18:53.312636 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 03:18:53.313121
924 03:18:53.313545 Model: Libre Computer AML-A311D-CC Alta
925 03:18:53.521031 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 03:18:53.544499 DRAM: 2 GiB (effective 3.8 GiB)
927 03:18:53.687367 Core: 408 devices, 31 uclasses, devicetree: separate
928 03:18:53.692292 WDT: Not starting watchdog@f0d0
929 03:18:53.725540 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 03:18:53.737930 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 03:18:53.742942 ** Bad device specification mmc 0 **
932 03:18:53.753265 Card did not respond to voltage select! : -110
933 03:18:53.760937 ** Bad device specification mmc 0 **
934 03:18:53.761396 Couldn't find partition mmc 0
935 03:18:53.769278 Card did not respond to voltage select! : -110
936 03:18:53.774796 ** Bad device specification mmc 0 **
937 03:18:53.775255 Couldn't find partition mmc 0
938 03:18:53.779847 Error: could not access storage.
939 03:18:54.122390 Net: eth0: ethernet@ff3f0000
940 03:18:54.122969 starting USB...
941 03:18:54.374104 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 03:18:54.374649 Starting the controller
943 03:18:54.381113 USB XHCI 1.10
944 03:18:56.244888 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 03:18:56.245507 bl2_stage_init 0x01
946 03:18:56.245935 bl2_stage_init 0x81
947 03:18:56.250435 hw id: 0x0000 - pwm id 0x01
948 03:18:56.250901 bl2_stage_init 0xc1
949 03:18:56.251314 bl2_stage_init 0x02
950 03:18:56.251719
951 03:18:56.256000 L0:00000000
952 03:18:56.256459 L1:20000703
953 03:18:56.256867 L2:00008067
954 03:18:56.257265 L3:14000000
955 03:18:56.261583 B2:00402000
956 03:18:56.262034 B1:e0f83180
957 03:18:56.262440
958 03:18:56.262840 TE: 58167
959 03:18:56.263237
960 03:18:56.267180 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 03:18:56.267638
962 03:18:56.268083 Board ID = 1
963 03:18:56.272796 Set A53 clk to 24M
964 03:18:56.273244 Set A73 clk to 24M
965 03:18:56.273644 Set clk81 to 24M
966 03:18:56.278371 A53 clk: 1200 MHz
967 03:18:56.278817 A73 clk: 1200 MHz
968 03:18:56.279218 CLK81: 166.6M
969 03:18:56.279609 smccc: 00012abe
970 03:18:56.283941 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 03:18:56.289609 board id: 1
972 03:18:56.295454 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 03:18:56.306100 fw parse done
974 03:18:56.312126 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 03:18:56.354738 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 03:18:56.365679 PIEI prepare done
977 03:18:56.366183 fastboot data load
978 03:18:56.366585 fastboot data verify
979 03:18:56.371285 verify result: 266
980 03:18:56.376792 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 03:18:56.377229 LPDDR4 probe
982 03:18:56.377612 ddr clk to 1584MHz
983 03:18:56.384833 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 03:18:56.422153
985 03:18:56.422623 dmc_version 0001
986 03:18:56.428753 Check phy result
987 03:18:56.434630 INFO : End of CA training
988 03:18:56.435058 INFO : End of initialization
989 03:18:56.440181 INFO : Training has run successfully!
990 03:18:56.440603 Check phy result
991 03:18:56.445854 INFO : End of initialization
992 03:18:56.446275 INFO : End of read enable training
993 03:18:56.451551 INFO : End of fine write leveling
994 03:18:56.457014 INFO : End of Write leveling coarse delay
995 03:18:56.457443 INFO : Training has run successfully!
996 03:18:56.457831 Check phy result
997 03:18:56.462664 INFO : End of initialization
998 03:18:56.463099 INFO : End of read dq deskew training
999 03:18:56.468334 INFO : End of MPR read delay center optimization
1000 03:18:56.473885 INFO : End of write delay center optimization
1001 03:18:56.479533 INFO : End of read delay center optimization
1002 03:18:56.479972 INFO : End of max read latency training
1003 03:18:56.485088 INFO : Training has run successfully!
1004 03:18:56.485532 1D training succeed
1005 03:18:56.494331 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 03:18:56.541982 Check phy result
1007 03:18:56.542515 INFO : End of initialization
1008 03:18:56.563578 INFO : End of 2D read delay Voltage center optimization
1009 03:18:56.583798 INFO : End of 2D read delay Voltage center optimization
1010 03:18:56.635869 INFO : End of 2D write delay Voltage center optimization
1011 03:18:56.685345 INFO : End of 2D write delay Voltage center optimization
1012 03:18:56.690732 INFO : Training has run successfully!
1013 03:18:56.691184
1014 03:18:56.691596 channel==0
1015 03:18:56.696535 RxClkDly_Margin_A0==88 ps 9
1016 03:18:56.696988 TxDqDly_Margin_A0==98 ps 10
1017 03:18:56.701978 RxClkDly_Margin_A1==88 ps 9
1018 03:18:56.702422 TxDqDly_Margin_A1==88 ps 9
1019 03:18:56.702828 TrainedVREFDQ_A0==74
1020 03:18:56.707615 TrainedVREFDQ_A1==74
1021 03:18:56.708108 VrefDac_Margin_A0==25
1022 03:18:56.708522 DeviceVref_Margin_A0==40
1023 03:18:56.713095 VrefDac_Margin_A1==25
1024 03:18:56.713554 DeviceVref_Margin_A1==40
1025 03:18:56.713960
1026 03:18:56.714357
1027 03:18:56.714755 channel==1
1028 03:18:56.718744 RxClkDly_Margin_A0==98 ps 10
1029 03:18:56.719193 TxDqDly_Margin_A0==88 ps 9
1030 03:18:56.724375 RxClkDly_Margin_A1==98 ps 10
1031 03:18:56.724829 TxDqDly_Margin_A1==88 ps 9
1032 03:18:56.730112 TrainedVREFDQ_A0==77
1033 03:18:56.730563 TrainedVREFDQ_A1==77
1034 03:18:56.730966 VrefDac_Margin_A0==22
1035 03:18:56.735554 DeviceVref_Margin_A0==37
1036 03:18:56.736052 VrefDac_Margin_A1==22
1037 03:18:56.741200 DeviceVref_Margin_A1==37
1038 03:18:56.741661
1039 03:18:56.742065 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 03:18:56.742467
1041 03:18:56.774703 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1042 03:18:56.775241 2D training succeed
1043 03:18:56.780318 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 03:18:56.785897 auto size-- 65535DDR cs0 size: 2048MB
1045 03:18:56.786385 DDR cs1 size: 2048MB
1046 03:18:56.791461 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 03:18:56.791904 cs0 DataBus test pass
1048 03:18:56.797062 cs1 DataBus test pass
1049 03:18:56.797500 cs0 AddrBus test pass
1050 03:18:56.797903 cs1 AddrBus test pass
1051 03:18:56.798297
1052 03:18:56.802653 100bdlr_step_size ps== 420
1053 03:18:56.803092 result report
1054 03:18:56.808263 boot times 0Enable ddr reg access
1055 03:18:56.813526 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 03:18:56.827044 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 03:18:57.400754 0.0;M3 CHK:0;cm4_sp_mode 0
1058 03:18:57.401360 MVN_1=0x00000000
1059 03:18:57.406280 MVN_2=0x00000000
1060 03:18:57.412114 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 03:18:57.412580 OPS=0x10
1062 03:18:57.412993 ring efuse init
1063 03:18:57.413399 chipver efuse init
1064 03:18:57.417623 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 03:18:57.423208 [0.018961 Inits done]
1066 03:18:57.423654 secure task start!
1067 03:18:57.424096 high task start!
1068 03:18:57.427797 low task start!
1069 03:18:57.428261 run into bl31
1070 03:18:57.434404 NOTICE: BL31: v1.3(release):4fc40b1
1071 03:18:57.442247 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 03:18:57.442707 NOTICE: BL31: G12A normal boot!
1073 03:18:57.467629 NOTICE: BL31: BL33 decompress pass
1074 03:18:57.472848 ERROR: Error initializing runtime service opteed_fast
1075 03:18:58.706226
1076 03:18:58.706841
1077 03:18:58.714587 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 03:18:58.715059
1079 03:18:58.715469 Model: Libre Computer AML-A311D-CC Alta
1080 03:18:58.922128 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 03:18:58.946440 DRAM: 2 GiB (effective 3.8 GiB)
1082 03:18:59.089427 Core: 408 devices, 31 uclasses, devicetree: separate
1083 03:18:59.095293 WDT: Not starting watchdog@f0d0
1084 03:18:59.127499 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 03:18:59.140005 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 03:18:59.145027 ** Bad device specification mmc 0 **
1087 03:18:59.155401 Card did not respond to voltage select! : -110
1088 03:18:59.161990 ** Bad device specification mmc 0 **
1089 03:18:59.162468 Couldn't find partition mmc 0
1090 03:18:59.171431 Card did not respond to voltage select! : -110
1091 03:18:59.176807 ** Bad device specification mmc 0 **
1092 03:18:59.177268 Couldn't find partition mmc 0
1093 03:18:59.181853 Error: could not access storage.
1094 03:18:59.523438 Net: eth0: ethernet@ff3f0000
1095 03:18:59.524034 starting USB...
1096 03:18:59.776213 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 03:18:59.776817 Starting the controller
1098 03:18:59.783131 USB XHCI 1.10
1099 03:19:01.340102 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 03:19:01.348468 scanning usb for storage devices... 0 Storage Device(s) found
1102 03:19:01.399651 Hit any key to stop autoboot: 1
1103 03:19:01.401329 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 03:19:01.401803 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 03:19:01.402153 Setting prompt string to ['=>']
1106 03:19:01.402500 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 03:19:01.416005 0
1108 03:19:01.416872 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 03:19:01.417300 Sending with 10 millisecond of delay
1111 03:19:02.553288 => setenv autoload no
1112 03:19:02.564255 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 03:19:02.566921 setenv autoload no
1114 03:19:02.567604 Sending with 10 millisecond of delay
1116 03:19:04.366199 => setenv initrd_high 0xffffffff
1117 03:19:04.376905 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 03:19:04.377639 setenv initrd_high 0xffffffff
1119 03:19:04.378264 Sending with 10 millisecond of delay
1121 03:19:05.995010 => setenv fdt_high 0xffffffff
1122 03:19:06.005834 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 03:19:06.006826 setenv fdt_high 0xffffffff
1124 03:19:06.007534 Sending with 10 millisecond of delay
1126 03:19:06.299492 => dhcp
1127 03:19:06.310332 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 03:19:06.311176 dhcp
1129 03:19:06.311614 Speed: 1000, full duplex
1130 03:19:06.312053 BOOTP broadcast 1
1131 03:19:06.320425 DHCP client bound to address 192.168.6.27 (10 ms)
1132 03:19:06.321115 Sending with 10 millisecond of delay
1134 03:19:07.997251 => setenv serverip 192.168.6.2
1135 03:19:08.008034 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 03:19:08.008818 setenv serverip 192.168.6.2
1137 03:19:08.009497 Sending with 10 millisecond of delay
1139 03:19:11.733575 => tftpboot 0x01080000 878987/tftp-deploy-2rtsprmb/kernel/uImage
1140 03:19:11.744358 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 03:19:11.745152 tftpboot 0x01080000 878987/tftp-deploy-2rtsprmb/kernel/uImage
1142 03:19:11.745613 Speed: 1000, full duplex
1143 03:19:11.746038 Using ethernet@ff3f0000 device
1144 03:19:11.746793 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 03:19:11.752386 Filename '878987/tftp-deploy-2rtsprmb/kernel/uImage'.
1146 03:19:11.756249 Load address: 0x1080000
1147 03:19:14.104823 Loading: *################################################## 36.1 MiB
1148 03:19:14.105407 15.3 MiB/s
1149 03:19:14.105807 done
1150 03:19:14.108351 Bytes transferred = 37814848 (2410240 hex)
1151 03:19:14.109096 Sending with 10 millisecond of delay
1153 03:19:18.799288 => tftpboot 0x08000000 878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot
1154 03:19:18.810148 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:06)
1155 03:19:18.811042 tftpboot 0x08000000 878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot
1156 03:19:18.811532 Speed: 1000, full duplex
1157 03:19:18.812016 Using ethernet@ff3f0000 device
1158 03:19:18.812799 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 03:19:18.824423 Filename '878987/tftp-deploy-2rtsprmb/ramdisk/ramdisk.cpio.gz.uboot'.
1160 03:19:18.824988 Load address: 0x8000000
1161 03:19:26.027734 Loading: *###T ############################################## UDP wrong checksum 00000005 000005a3
1162 03:19:30.868235 UDP wrong checksum 000000ff 00006066
1163 03:19:30.878967 UDP wrong checksum 000000ff 0000ee58
1164 03:19:31.029923 T UDP wrong checksum 00000005 000005a3
1165 03:19:36.193112 T UDP wrong checksum 000000ff 00004032
1166 03:19:36.243124 UDP wrong checksum 000000ff 0000d124
1167 03:19:41.032331 T UDP wrong checksum 00000005 000005a3
1168 03:19:44.360560 UDP wrong checksum 000000ff 0000a905
1169 03:19:44.382809 UDP wrong checksum 000000ff 00003ff8
1170 03:20:01.035934 T T T T UDP wrong checksum 00000005 000005a3
1171 03:20:07.994404 T UDP wrong checksum 000000ff 00001ef0
1172 03:20:08.055734 UDP wrong checksum 000000ff 0000b1e2
1173 03:20:16.040331 T
1174 03:20:16.040766 Retry count exceeded; starting again
1176 03:20:16.041666 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1179 03:20:16.042611 end: 2.4 uboot-commands (duration 00:01:52) [common]
1181 03:20:16.043340 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1183 03:20:16.043898 end: 2 uboot-action (duration 00:01:52) [common]
1185 03:20:16.044938 Cleaning after the job
1186 03:20:16.045301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/ramdisk
1187 03:20:16.046144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/kernel
1188 03:20:16.057743 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/dtb
1189 03:20:16.058498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/nfsrootfs
1190 03:20:16.086492 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/878987/tftp-deploy-2rtsprmb/modules
1191 03:20:16.093475 start: 4.1 power-off (timeout 00:00:30) [common]
1192 03:20:16.094093 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1193 03:20:16.128684 >> OK - accepted request
1194 03:20:16.130968 Returned 0 in 0 seconds
1195 03:20:16.231851 end: 4.1 power-off (duration 00:00:00) [common]
1197 03:20:16.232912 start: 4.2 read-feedback (timeout 00:10:00) [common]
1198 03:20:16.233561 Listened to connection for namespace 'common' for up to 1s
1199 03:20:17.234493 Finalising connection for namespace 'common'
1200 03:20:17.235042 Disconnecting from shell: Finalise
1201 03:20:17.235336 =>
1202 03:20:17.336047 end: 4.2 read-feedback (duration 00:00:01) [common]
1203 03:20:17.336533 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/878987
1204 03:20:19.063455 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/878987
1205 03:20:19.064501 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.