Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 59
1 03:11:06.328058 lava-dispatcher, installed at version: 2024.01
2 03:11:06.328827 start: 0 validate
3 03:11:06.329290 Start time: 2024-11-01 03:11:06.329260+00:00 (UTC)
4 03:11:06.329868 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:11:06.330439 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 03:11:06.373626 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:11:06.374182 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 03:11:06.408868 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:11:06.409526 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 03:11:06.440295 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:11:06.440803 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 03:11:06.476640 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:11:06.477164 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 03:11:06.525298 validate duration: 0.20
16 03:11:06.526984 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:11:06.527668 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:11:06.528338 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:11:06.529371 Not decompressing ramdisk as can be used compressed.
20 03:11:06.530148 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 03:11:06.530674 saving as /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/ramdisk/initrd.cpio.gz
22 03:11:06.531235 total size: 4775763 (4 MB)
23 03:11:06.578315 progress 0 % (0 MB)
24 03:11:06.586048 progress 5 % (0 MB)
25 03:11:06.593443 progress 10 % (0 MB)
26 03:11:06.600734 progress 15 % (0 MB)
27 03:11:06.608967 progress 20 % (0 MB)
28 03:11:06.615936 progress 25 % (1 MB)
29 03:11:06.621399 progress 30 % (1 MB)
30 03:11:06.625345 progress 35 % (1 MB)
31 03:11:06.628805 progress 40 % (1 MB)
32 03:11:06.632223 progress 45 % (2 MB)
33 03:11:06.635639 progress 50 % (2 MB)
34 03:11:06.639418 progress 55 % (2 MB)
35 03:11:06.642928 progress 60 % (2 MB)
36 03:11:06.646273 progress 65 % (2 MB)
37 03:11:06.649976 progress 70 % (3 MB)
38 03:11:06.653231 progress 75 % (3 MB)
39 03:11:06.656523 progress 80 % (3 MB)
40 03:11:06.659836 progress 85 % (3 MB)
41 03:11:06.663570 progress 90 % (4 MB)
42 03:11:06.666673 progress 95 % (4 MB)
43 03:11:06.669626 progress 100 % (4 MB)
44 03:11:06.670316 4 MB downloaded in 0.14 s (32.75 MB/s)
45 03:11:06.670876 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:11:06.671792 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:11:06.672129 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:11:06.672421 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:11:06.672899 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 03:11:06.673154 saving as /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/kernel/zImage
52 03:11:06.673373 total size: 12050944 (11 MB)
53 03:11:06.673595 No compression specified
54 03:11:06.712730 progress 0 % (0 MB)
55 03:11:06.720693 progress 5 % (0 MB)
56 03:11:06.728612 progress 10 % (1 MB)
57 03:11:06.737033 progress 15 % (1 MB)
58 03:11:06.745182 progress 20 % (2 MB)
59 03:11:06.752859 progress 25 % (2 MB)
60 03:11:06.760848 progress 30 % (3 MB)
61 03:11:06.768640 progress 35 % (4 MB)
62 03:11:06.776839 progress 40 % (4 MB)
63 03:11:06.784670 progress 45 % (5 MB)
64 03:11:06.792437 progress 50 % (5 MB)
65 03:11:06.800694 progress 55 % (6 MB)
66 03:11:06.808803 progress 60 % (6 MB)
67 03:11:06.816930 progress 65 % (7 MB)
68 03:11:06.824593 progress 70 % (8 MB)
69 03:11:06.832370 progress 75 % (8 MB)
70 03:11:06.840492 progress 80 % (9 MB)
71 03:11:06.848380 progress 85 % (9 MB)
72 03:11:06.856009 progress 90 % (10 MB)
73 03:11:06.864146 progress 95 % (10 MB)
74 03:11:06.871521 progress 100 % (11 MB)
75 03:11:06.872192 11 MB downloaded in 0.20 s (57.81 MB/s)
76 03:11:06.872673 end: 1.2.1 http-download (duration 00:00:00) [common]
78 03:11:06.873505 end: 1.2 download-retry (duration 00:00:00) [common]
79 03:11:06.873778 start: 1.3 download-retry (timeout 00:10:00) [common]
80 03:11:06.874043 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 03:11:06.874517 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 03:11:06.874784 saving as /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/dtb/am335x-boneblack.dtb
83 03:11:06.874995 total size: 70568 (0 MB)
84 03:11:06.875203 No compression specified
85 03:11:06.906899 progress 46 % (0 MB)
86 03:11:06.907751 progress 92 % (0 MB)
87 03:11:06.908498 progress 100 % (0 MB)
88 03:11:06.908898 0 MB downloaded in 0.03 s (1.99 MB/s)
89 03:11:06.909366 end: 1.3.1 http-download (duration 00:00:00) [common]
91 03:11:06.910182 end: 1.3 download-retry (duration 00:00:00) [common]
92 03:11:06.910449 start: 1.4 download-retry (timeout 00:10:00) [common]
93 03:11:06.910737 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 03:11:06.911214 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 03:11:06.911458 saving as /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/nfsrootfs/full.rootfs.tar
96 03:11:06.911665 total size: 117747780 (112 MB)
97 03:11:06.911875 Using unxz to decompress xz
98 03:11:06.951207 progress 0 % (0 MB)
99 03:11:07.691074 progress 5 % (5 MB)
100 03:11:08.437079 progress 10 % (11 MB)
101 03:11:09.203176 progress 15 % (16 MB)
102 03:11:09.943184 progress 20 % (22 MB)
103 03:11:10.526235 progress 25 % (28 MB)
104 03:11:11.330645 progress 30 % (33 MB)
105 03:11:12.131713 progress 35 % (39 MB)
106 03:11:12.477335 progress 40 % (44 MB)
107 03:11:12.823327 progress 45 % (50 MB)
108 03:11:13.492916 progress 50 % (56 MB)
109 03:11:14.306684 progress 55 % (61 MB)
110 03:11:15.039576 progress 60 % (67 MB)
111 03:11:15.756804 progress 65 % (73 MB)
112 03:11:16.517645 progress 70 % (78 MB)
113 03:11:17.268517 progress 75 % (84 MB)
114 03:11:18.002075 progress 80 % (89 MB)
115 03:11:18.707350 progress 85 % (95 MB)
116 03:11:19.494470 progress 90 % (101 MB)
117 03:11:20.258843 progress 95 % (106 MB)
118 03:11:21.071408 progress 100 % (112 MB)
119 03:11:21.084690 112 MB downloaded in 14.17 s (7.92 MB/s)
120 03:11:21.085563 end: 1.4.1 http-download (duration 00:00:14) [common]
122 03:11:21.087173 end: 1.4 download-retry (duration 00:00:14) [common]
123 03:11:21.087689 start: 1.5 download-retry (timeout 00:09:45) [common]
124 03:11:21.088248 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 03:11:21.089805 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 03:11:21.090340 saving as /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/modules/modules.tar
127 03:11:21.090780 total size: 6909472 (6 MB)
128 03:11:21.091211 Using unxz to decompress xz
129 03:11:21.136322 progress 0 % (0 MB)
130 03:11:21.172136 progress 5 % (0 MB)
131 03:11:21.219914 progress 10 % (0 MB)
132 03:11:21.265805 progress 15 % (1 MB)
133 03:11:21.316079 progress 20 % (1 MB)
134 03:11:21.361301 progress 25 % (1 MB)
135 03:11:21.410981 progress 30 % (2 MB)
136 03:11:21.454727 progress 35 % (2 MB)
137 03:11:21.503333 progress 40 % (2 MB)
138 03:11:21.548046 progress 45 % (2 MB)
139 03:11:21.598452 progress 50 % (3 MB)
140 03:11:21.642005 progress 55 % (3 MB)
141 03:11:21.691079 progress 60 % (3 MB)
142 03:11:21.740336 progress 65 % (4 MB)
143 03:11:21.782079 progress 70 % (4 MB)
144 03:11:21.833530 progress 75 % (4 MB)
145 03:11:21.880066 progress 80 % (5 MB)
146 03:11:21.932776 progress 85 % (5 MB)
147 03:11:21.976798 progress 90 % (5 MB)
148 03:11:22.028609 progress 95 % (6 MB)
149 03:11:22.072136 progress 100 % (6 MB)
150 03:11:22.086911 6 MB downloaded in 1.00 s (6.62 MB/s)
151 03:11:22.087516 end: 1.5.1 http-download (duration 00:00:01) [common]
153 03:11:22.089099 end: 1.5 download-retry (duration 00:00:01) [common]
154 03:11:22.089727 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 03:11:22.090310 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 03:11:38.671707 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha
157 03:11:38.672332 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 03:11:38.672627 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 03:11:38.673418 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3
160 03:11:38.673896 makedir: /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin
161 03:11:38.674238 makedir: /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/tests
162 03:11:38.674563 makedir: /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/results
163 03:11:38.674894 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-add-keys
164 03:11:38.675421 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-add-sources
165 03:11:38.676725 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-background-process-start
166 03:11:38.677350 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-background-process-stop
167 03:11:38.678412 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-common-functions
168 03:11:38.679350 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-echo-ipv4
169 03:11:38.680377 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-install-packages
170 03:11:38.681222 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-installed-packages
171 03:11:38.681872 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-os-build
172 03:11:38.683004 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-probe-channel
173 03:11:38.684015 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-probe-ip
174 03:11:38.684670 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-target-ip
175 03:11:38.685613 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-target-mac
176 03:11:38.686369 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-target-storage
177 03:11:38.686887 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-case
178 03:11:38.687387 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-event
179 03:11:38.687930 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-feedback
180 03:11:38.688506 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-raise
181 03:11:38.689176 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-reference
182 03:11:38.689737 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-runner
183 03:11:38.690245 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-set
184 03:11:38.690740 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-test-shell
185 03:11:38.691255 Updating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-add-keys (debian)
186 03:11:38.692482 Updating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-add-sources (debian)
187 03:11:38.693188 Updating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-install-packages (debian)
188 03:11:38.694576 Updating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-installed-packages (debian)
189 03:11:38.695595 Updating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/bin/lava-os-build (debian)
190 03:11:38.697022 Creating /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/environment
191 03:11:38.698997 LAVA metadata
192 03:11:38.699450 - LAVA_JOB_ID=919674
193 03:11:38.699841 - LAVA_DISPATCHER_IP=192.168.6.2
194 03:11:38.700266 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 03:11:38.701453 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 03:11:38.701786 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 03:11:38.701994 skipped lava-vland-overlay
198 03:11:38.702237 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 03:11:38.702513 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 03:11:38.702728 skipped lava-multinode-overlay
201 03:11:38.702968 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 03:11:38.703220 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 03:11:38.703470 Loading test definitions
204 03:11:38.703748 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 03:11:38.703967 Using /lava-919674 at stage 0
206 03:11:38.705113 uuid=919674_1.6.2.4.1 testdef=None
207 03:11:38.705429 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 03:11:38.705693 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 03:11:38.708095 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 03:11:38.708922 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 03:11:38.711826 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 03:11:38.712727 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 03:11:38.717437 runner path: /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/0/tests/0_timesync-off test_uuid 919674_1.6.2.4.1
216 03:11:38.718086 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 03:11:38.718940 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 03:11:38.719178 Using /lava-919674 at stage 0
220 03:11:38.719550 Fetching tests from https://github.com/kernelci/test-definitions.git
221 03:11:38.719857 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/0/tests/1_kselftest-dt'
222 03:11:42.120023 Running '/usr/bin/git checkout kernelci.org
223 03:11:42.286849 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 03:11:42.288412 uuid=919674_1.6.2.4.5 testdef=None
225 03:11:42.288786 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 03:11:42.289563 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 03:11:42.292513 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 03:11:42.293370 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 03:11:42.297355 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 03:11:42.298255 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 03:11:42.302031 runner path: /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/0/tests/1_kselftest-dt test_uuid 919674_1.6.2.4.5
235 03:11:42.302344 BOARD='beaglebone-black'
236 03:11:42.302562 BRANCH='mainline'
237 03:11:42.302766 SKIPFILE='/dev/null'
238 03:11:42.302968 SKIP_INSTALL='True'
239 03:11:42.303167 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 03:11:42.303372 TST_CASENAME=''
241 03:11:42.303575 TST_CMDFILES='dt'
242 03:11:42.304229 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 03:11:42.305072 Creating lava-test-runner.conf files
245 03:11:42.305287 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919674/lava-overlay-neahx0e3/lava-919674/0 for stage 0
246 03:11:42.305770 - 0_timesync-off
247 03:11:42.306060 - 1_kselftest-dt
248 03:11:42.306429 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 03:11:42.306731 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 03:12:05.500540 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 03:12:05.501025 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 03:12:05.501325 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 03:12:05.501636 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 03:12:05.501929 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 03:12:05.873912 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 03:12:05.874387 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 03:12:05.874658 extracting modules file /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha
258 03:12:06.796825 extracting modules file /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919674/extract-overlay-ramdisk-m3ik6cs0/ramdisk
259 03:12:07.758023 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 03:12:07.758484 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 03:12:07.758783 [common] Applying overlay to NFS
262 03:12:07.759012 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919674/compress-overlay-wdja8i9o/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha
263 03:12:10.584430 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 03:12:10.584914 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 03:12:10.585193 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 03:12:10.585470 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 03:12:10.585722 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 03:12:10.585982 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 03:12:10.586231 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 03:12:10.586484 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 03:12:10.586735 Building ramdisk /var/lib/lava/dispatcher/tmp/919674/extract-overlay-ramdisk-m3ik6cs0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919674/extract-overlay-ramdisk-m3ik6cs0/ramdisk
272 03:12:11.791168 >> 79010 blocks
273 03:12:16.858513 Adding RAMdisk u-boot header.
274 03:12:16.858994 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919674/extract-overlay-ramdisk-m3ik6cs0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919674/extract-overlay-ramdisk-m3ik6cs0/ramdisk.cpio.gz.uboot
275 03:12:17.027740 output: Image Name:
276 03:12:17.028239 output: Created: Fri Nov 1 03:12:16 2024
277 03:12:17.028669 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 03:12:17.029078 output: Data Size: 15354574 Bytes = 14994.70 KiB = 14.64 MiB
279 03:12:17.029484 output: Load Address: 00000000
280 03:12:17.029882 output: Entry Point: 00000000
281 03:12:17.030282 output:
282 03:12:17.031280 rename /var/lib/lava/dispatcher/tmp/919674/extract-overlay-ramdisk-m3ik6cs0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot
283 03:12:17.032046 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 03:12:17.032617 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 03:12:17.033145 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 03:12:17.033610 No LXC device requested
287 03:12:17.034108 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 03:12:17.034616 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 03:12:17.035109 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 03:12:17.035520 Checking files for TFTP limit of 4294967296 bytes.
291 03:12:17.038192 end: 1 tftp-deploy (duration 00:01:11) [common]
292 03:12:17.038778 start: 2 uboot-action (timeout 00:05:00) [common]
293 03:12:17.039301 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 03:12:17.039795 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 03:12:17.040333 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 03:12:17.041091 substitutions:
297 03:12:17.041515 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 03:12:17.041922 - {DTB_ADDR}: 0x88000000
299 03:12:17.042321 - {DTB}: 919674/tftp-deploy-yi3hy7u_/dtb/am335x-boneblack.dtb
300 03:12:17.042717 - {INITRD}: 919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot
301 03:12:17.043112 - {KERNEL_ADDR}: 0x82000000
302 03:12:17.043504 - {KERNEL}: 919674/tftp-deploy-yi3hy7u_/kernel/zImage
303 03:12:17.043903 - {LAVA_MAC}: None
304 03:12:17.044380 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha
305 03:12:17.044787 - {NFS_SERVER_IP}: 192.168.6.2
306 03:12:17.045182 - {PRESEED_CONFIG}: None
307 03:12:17.045574 - {PRESEED_LOCAL}: None
308 03:12:17.045965 - {RAMDISK_ADDR}: 0x83000000
309 03:12:17.046354 - {RAMDISK}: 919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot
310 03:12:17.046744 - {ROOT_PART}: None
311 03:12:17.047131 - {ROOT}: None
312 03:12:17.047516 - {SERVER_IP}: 192.168.6.2
313 03:12:17.047901 - {TEE_ADDR}: 0x83000000
314 03:12:17.048320 - {TEE}: None
315 03:12:17.048710 Parsed boot commands:
316 03:12:17.049090 - setenv autoload no
317 03:12:17.049478 - setenv initrd_high 0xffffffff
318 03:12:17.049865 - setenv fdt_high 0xffffffff
319 03:12:17.050247 - dhcp
320 03:12:17.050629 - setenv serverip 192.168.6.2
321 03:12:17.051010 - tftp 0x82000000 919674/tftp-deploy-yi3hy7u_/kernel/zImage
322 03:12:17.051401 - tftp 0x83000000 919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot
323 03:12:17.051787 - setenv initrd_size ${filesize}
324 03:12:17.052203 - tftp 0x88000000 919674/tftp-deploy-yi3hy7u_/dtb/am335x-boneblack.dtb
325 03:12:17.052596 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 03:12:17.052997 - bootz 0x82000000 0x83000000 0x88000000
327 03:12:17.053500 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 03:12:17.054988 start: 2.3 connect-device (timeout 00:05:00) [common]
330 03:12:17.055409 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 03:12:17.070977 Setting prompt string to ['lava-test: # ']
332 03:12:17.072519 end: 2.3 connect-device (duration 00:00:00) [common]
333 03:12:17.073125 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 03:12:17.073676 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 03:12:17.074413 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 03:12:17.075644 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 03:12:17.110288 >> OK - accepted request
338 03:12:17.112779 Returned 0 in 0 seconds
339 03:12:17.213760 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 03:12:17.215476 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 03:12:17.216105 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 03:12:17.216644 Setting prompt string to ['Hit any key to stop autoboot']
344 03:12:17.217099 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 03:12:17.218712 Trying 192.168.56.22...
346 03:12:17.219211 Connected to conserv3.
347 03:12:17.219617 Escape character is '^]'.
348 03:12:17.220057
349 03:12:17.220481 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 03:12:17.220889
351 03:12:55.381408
352 03:12:55.388086 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 03:12:55.388552 Trying to boot from MMC1
354 03:12:55.963946
355 03:12:55.964581
356 03:12:55.969409 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 03:12:55.969861
358 03:12:55.970266 CPU : AM335X-GP rev 2.0
359 03:12:55.974513 Model: TI AM335x BeagleBone Black
360 03:12:55.974956 DRAM: 512 MiB
361 03:12:56.059129 Core: 160 devices, 18 uclasses, devicetree: separate
362 03:12:56.072882 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 03:12:56.473755 NAND: 0 MiB
364 03:12:56.483683 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 03:12:56.558463 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 03:12:56.579801 <ethaddr> not set. Validating first E-fuse MAC
367 03:12:56.609444 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 03:12:56.667931 Hit any key to stop autoboot: 2
370 03:12:56.668782 end: 2.4.2 bootloader-interrupt (duration 00:00:39) [common]
371 03:12:56.669369 start: 2.4.3 bootloader-commands (timeout 00:04:20) [common]
372 03:12:56.669835 Setting prompt string to ['=>']
373 03:12:56.670303 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:20)
374 03:12:56.677813 0
375 03:12:56.678660 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 03:12:56.679160 Sending with 10 millisecond of delay
378 03:12:57.813918 => setenv autoload no
379 03:12:57.824699 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
380 03:12:57.829523 setenv autoload no
381 03:12:57.830251 Sending with 10 millisecond of delay
383 03:12:59.627041 => setenv initrd_high 0xffffffff
384 03:12:59.637783 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
385 03:12:59.638575 setenv initrd_high 0xffffffff
386 03:12:59.639275 Sending with 10 millisecond of delay
388 03:13:01.255654 => setenv fdt_high 0xffffffff
389 03:13:01.266485 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
390 03:13:01.267351 setenv fdt_high 0xffffffff
391 03:13:01.268066 Sending with 10 millisecond of delay
393 03:13:01.559916 => dhcp
394 03:13:01.570709 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
395 03:13:01.571503 dhcp
396 03:13:01.571935 link up on port 0, speed 100, full duplex
397 03:13:01.572377 BOOTP broadcast 1
398 03:13:01.828267 DHCP client bound to address 192.168.6.16 (252 ms)
399 03:13:01.829069 Sending with 10 millisecond of delay
401 03:13:03.505916 => setenv serverip 192.168.6.2
402 03:13:03.516763 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
403 03:13:03.517668 setenv serverip 192.168.6.2
404 03:13:03.518434 Sending with 10 millisecond of delay
406 03:13:07.002036 => tftp 0x82000000 919674/tftp-deploy-yi3hy7u_/kernel/zImage
407 03:13:07.012908 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
408 03:13:07.013876 tftp 0x82000000 919674/tftp-deploy-yi3hy7u_/kernel/zImage
409 03:13:07.014349 link up on port 0, speed 100, full duplex
410 03:13:07.018059 Using ethernet@4a100000 device
411 03:13:07.023591 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 03:13:07.024158 Filename '919674/tftp-deploy-yi3hy7u_/kernel/zImage'.
413 03:13:07.027061 Load address: 0x82000000
414 03:13:09.224527 Loading: *################################################## 11.5 MiB
415 03:13:09.225204 5.2 MiB/s
416 03:13:09.225685 done
417 03:13:09.228061 Bytes transferred = 12050944 (b7e200 hex)
418 03:13:09.228854 Sending with 10 millisecond of delay
420 03:13:13.674122 => tftp 0x83000000 919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot
421 03:13:13.686217 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
422 03:13:13.687237 tftp 0x83000000 919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot
423 03:13:13.687680 link up on port 0, speed 100, full duplex
424 03:13:13.689701 Using ethernet@4a100000 device
425 03:13:13.695268 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 03:13:13.704461 Filename '919674/tftp-deploy-yi3hy7u_/ramdisk/ramdisk.cpio.gz.uboot'.
427 03:13:13.705020 Load address: 0x83000000
428 03:13:16.605653 Loading: *################################################## 14.6 MiB
429 03:13:16.606085 5 MiB/s
430 03:13:16.606335 done
431 03:13:16.609673 Bytes transferred = 15354638 (ea4b0e hex)
432 03:13:16.610221 Sending with 10 millisecond of delay
434 03:13:18.467359 => setenv initrd_size ${filesize}
435 03:13:18.478211 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
436 03:13:18.479341 setenv initrd_size ${filesize}
437 03:13:18.480208 Sending with 10 millisecond of delay
439 03:13:22.624452 => tftp 0x88000000 919674/tftp-deploy-yi3hy7u_/dtb/am335x-boneblack.dtb
440 03:13:22.635261 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:54)
441 03:13:22.636212 tftp 0x88000000 919674/tftp-deploy-yi3hy7u_/dtb/am335x-boneblack.dtb
442 03:13:22.636654 link up on port 0, speed 100, full duplex
443 03:13:22.639761 Using ethernet@4a100000 device
444 03:13:22.645295 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 03:13:22.653511 Filename '919674/tftp-deploy-yi3hy7u_/dtb/am335x-boneblack.dtb'.
446 03:13:22.653949 Load address: 0x88000000
447 03:13:22.674832 Loading: *################################################## 68.9 KiB
448 03:13:22.681312 2.8 MiB/s
449 03:13:22.681763 done
450 03:13:22.682156 Bytes transferred = 70568 (113a8 hex)
451 03:13:22.684834 Sending with 10 millisecond of delay
453 03:13:35.858871 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 03:13:35.869880 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
455 03:13:35.870988 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 03:13:35.871851 Sending with 10 millisecond of delay
458 03:13:38.210754 => bootz 0x82000000 0x83000000 0x88000000
459 03:13:38.221724 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 03:13:38.222397 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
461 03:13:38.223684 bootz 0x82000000 0x83000000 0x88000000
462 03:13:38.224318 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
463 03:13:38.224957 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 03:13:38.229472 Image Name:
465 03:13:38.230025 Created: 2024-11-01 3:12:16 UTC
466 03:13:38.238131 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 03:13:38.238698 Data Size: 15354574 Bytes = 14.6 MiB
468 03:13:38.246686 Load Address: 00000000
469 03:13:38.247244 Entry Point: 00000000
470 03:13:38.421090 Verifying Checksum ... OK
471 03:13:38.421669 ## Flattened Device Tree blob at 88000000
472 03:13:38.427722 Booting using the fdt blob at 0x88000000
473 03:13:38.428316 Working FDT set to 88000000
474 03:13:38.433223 Using Device Tree in place at 88000000, end 880143a7
475 03:13:38.437758 Working FDT set to 88000000
476 03:13:38.450949
477 03:13:38.451507 Starting kernel ...
478 03:13:38.452059
479 03:13:38.453100 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 03:13:38.453830 start: 2.4.4 auto-login-action (timeout 00:03:39) [common]
481 03:13:38.454415 Setting prompt string to ['Linux version [0-9]']
482 03:13:38.454985 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 03:13:38.455595 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 03:13:39.341490 [ 0.000000] Booting Linux on physical CPU 0x0
485 03:13:39.347493 start: 2.4.4.1 login-action (timeout 00:03:38) [common]
486 03:13:39.348252 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 03:13:39.348881 Setting prompt string to []
488 03:13:39.349539 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 03:13:39.350137 Using line separator: #'\n'#
490 03:13:39.350672 No login prompt set.
491 03:13:39.351229 Parsing kernel messages
492 03:13:39.351739 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 03:13:39.352750 [login-action] Waiting for messages, (timeout 00:03:38)
494 03:13:39.353340 Waiting using forced prompt support (timeout 00:01:49)
495 03:13:39.358442 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j358334-arm-clang-15-multi-v7-defconfig-bm9v7) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Fri Nov 1 00:34:39 UTC 2024
496 03:13:39.364196 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 03:13:39.375603 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 03:13:39.381345 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 03:13:39.387042 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 03:13:39.392823 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 03:13:39.399948 [ 0.000000] Memory policy: Data cache writeback
502 03:13:39.400527 [ 0.000000] efi: UEFI not found.
503 03:13:39.408613 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 03:13:39.413888 [ 0.000000] Zone ranges:
505 03:13:39.419725 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 03:13:39.420384 [ 0.000000] Normal empty
507 03:13:39.425476 [ 0.000000] HighMem empty
508 03:13:39.431082 [ 0.000000] Movable zone start for each node
509 03:13:39.431652 [ 0.000000] Early memory node ranges
510 03:13:39.436929 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 03:13:39.446821 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 03:13:39.464925 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 03:13:39.470639 [ 0.000000] AM335X ES2.0 (sgx neon)
514 03:13:39.482311 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
515 03:13:39.499997 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 03:13:39.511594 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 03:13:39.517262 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 03:13:39.523001 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 03:13:39.532993 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 03:13:39.562324 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 03:13:39.568417 <6>[ 0.000000] trace event string verifier disabled
522 03:13:39.568977 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 03:13:39.574031 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 03:13:39.585583 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 03:13:39.591152 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 03:13:39.598454 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 03:13:39.613635 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 03:13:39.631188 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 03:13:39.637950 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 03:13:39.737626 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 03:13:39.748985 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 03:13:39.755731 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 03:13:39.768909 <6>[ 0.019185] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 03:13:39.777123 <6>[ 0.034205] Console: colour dummy device 80x30
535 03:13:39.782690 Matched prompt #6: WARNING:
536 03:13:39.784063 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 03:13:39.787962 <3>[ 0.039106] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 03:13:39.794697 <3>[ 0.046182] This ensures that you still see kernel messages. Please
539 03:13:39.797149 <3>[ 0.052911] update your kernel commandline.
540 03:13:39.837411 <6>[ 0.057528] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 03:13:39.843139 <6>[ 0.096189] CPU: Testing write buffer coherency: ok
542 03:13:39.849063 <6>[ 0.101560] CPU0: Spectre v2: using BPIALL workaround
543 03:13:39.849609 <6>[ 0.107028] pid_max: default: 32768 minimum: 301
544 03:13:39.860673 <6>[ 0.112227] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 03:13:39.867652 <6>[ 0.120053] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 03:13:39.874681 <6>[ 0.129508] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 03:13:39.883177 <6>[ 0.136475] Setting up static identity map for 0x80300000 - 0x803000ac
548 03:13:39.888905 <6>[ 0.146173] rcu: Hierarchical SRCU implementation.
549 03:13:39.896453 <6>[ 0.151462] rcu: Max phase no-delay instances is 1000.
550 03:13:39.905215 <6>[ 0.162794] EFI services will not be available.
551 03:13:39.911134 <6>[ 0.168083] smp: Bringing up secondary CPUs ...
552 03:13:39.916745 <6>[ 0.173140] smp: Brought up 1 node, 1 CPU
553 03:13:39.924919 <6>[ 0.177541] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 03:13:39.930930 <6>[ 0.184316] CPU: All CPU(s) started in SVC mode.
555 03:13:39.943038 <6>[ 0.189535] Memory: 404428K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50620K reserved, 65536K cma-reserved, 0K highmem)
556 03:13:39.948927 <6>[ 0.205819] devtmpfs: initialized
557 03:13:39.972025 <6>[ 0.223710] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 03:13:39.980284 <6>[ 0.232331] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 03:13:39.989492 <6>[ 0.242794] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 03:13:40.000238 <6>[ 0.255086] pinctrl core: initialized pinctrl subsystem
561 03:13:40.009800 <6>[ 0.265936] DMI not present or invalid.
562 03:13:40.018158 <6>[ 0.271827] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 03:13:40.027703 <6>[ 0.280832] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 03:13:40.042897 <6>[ 0.292482] thermal_sys: Registered thermal governor 'step_wise'
565 03:13:40.043490 <6>[ 0.292654] cpuidle: using governor menu
566 03:13:40.070383 <6>[ 0.328089] No ATAGs?
567 03:13:40.076570 <6>[ 0.330830] hw-breakpoint: debug architecture 0x4 unsupported.
568 03:13:40.087009 <6>[ 0.343022] Serial: AMBA PL011 UART driver
569 03:13:40.118004 <6>[ 0.375688] iommu: Default domain type: Translated
570 03:13:40.127180 <6>[ 0.381051] iommu: DMA domain TLB invalidation policy: strict mode
571 03:13:40.153466 <5>[ 0.410492] SCSI subsystem initialized
572 03:13:40.159339 <6>[ 0.415420] usbcore: registered new interface driver usbfs
573 03:13:40.165098 <6>[ 0.421496] usbcore: registered new interface driver hub
574 03:13:40.172009 <6>[ 0.427286] usbcore: registered new device driver usb
575 03:13:40.177825 <6>[ 0.433858] pps_core: LinuxPPS API ver. 1 registered
576 03:13:40.189291 <6>[ 0.439248] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 03:13:40.196446 <6>[ 0.448976] PTP clock support registered
578 03:13:40.197021 <6>[ 0.453444] EDAC MC: Ver: 3.0.0
579 03:13:40.254442 <6>[ 0.509376] scmi_core: SCMI protocol bus registered
580 03:13:40.260147 <6>[ 0.517593] vgaarb: loaded
581 03:13:40.272476 <6>[ 0.530360] clocksource: Switched to clocksource dmtimer
582 03:13:40.311785 <6>[ 0.569069] NET: Registered PF_INET protocol family
583 03:13:40.324420 <6>[ 0.574787] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 03:13:40.330183 <6>[ 0.583793] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 03:13:40.341724 <6>[ 0.592720] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 03:13:40.347391 <6>[ 0.600985] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 03:13:40.359033 <6>[ 0.609255] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 03:13:40.364886 <6>[ 0.616983] TCP: Hash tables configured (established 4096 bind 4096)
589 03:13:40.370784 <6>[ 0.623902] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 03:13:40.376510 <6>[ 0.630939] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 03:13:40.384208 <6>[ 0.638524] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 03:13:40.465779 <6>[ 0.717875] RPC: Registered named UNIX socket transport module.
593 03:13:40.466360 <6>[ 0.724336] RPC: Registered udp transport module.
594 03:13:40.471578 <6>[ 0.729444] RPC: Registered tcp transport module.
595 03:13:40.477368 <6>[ 0.734566] RPC: Registered tcp-with-tls transport module.
596 03:13:40.490411 <6>[ 0.740493] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 03:13:40.490983 <6>[ 0.747403] PCI: CLS 0 bytes, default 64
598 03:13:40.497621 <5>[ 0.753291] Initialise system trusted keyrings
599 03:13:40.519697 <6>[ 0.774396] Trying to unpack rootfs image as initramfs...
600 03:13:40.590216 <6>[ 0.841782] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 03:13:40.595015 <6>[ 0.849300] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 03:13:40.633881 <5>[ 0.891624] NFS: Registering the id_resolver key type
603 03:13:40.639765 <5>[ 0.897223] Key type id_resolver registered
604 03:13:40.645536 <5>[ 0.901916] Key type id_legacy registered
605 03:13:40.651301 <6>[ 0.906362] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 03:13:40.660830 <6>[ 0.913574] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 03:13:40.743061 <5>[ 1.000879] Key type asymmetric registered
608 03:13:40.749594 <5>[ 1.005405] Asymmetric key parser 'x509' registered
609 03:13:40.760621 <6>[ 1.010957] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 03:13:40.761205 <6>[ 1.018848] io scheduler mq-deadline registered
611 03:13:40.766305 <6>[ 1.023825] io scheduler kyber registered
612 03:13:40.771928 <6>[ 1.028278] io scheduler bfq registered
613 03:13:40.866606 <6>[ 1.120703] ledtrig-cpu: registered to indicate activity on CPUs
614 03:13:41.143560 <6>[ 1.397589] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 03:13:41.191345 <6>[ 1.448833] msm_serial: driver initialized
616 03:13:41.197267 <6>[ 1.453861] SuperH (H)SCI(F) driver initialized
617 03:13:41.203278 <6>[ 1.458983] STMicroelectronics ASC driver initialized
618 03:13:41.208503 <6>[ 1.464690] STM32 USART driver initialized
619 03:13:41.324472 <6>[ 1.581681] brd: module loaded
620 03:13:41.356227 <6>[ 1.613399] loop: module loaded
621 03:13:41.399269 <6>[ 1.656295] CAN device driver interface
622 03:13:41.405757 <6>[ 1.661497] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 03:13:41.411749 <6>[ 1.668442] e1000e: Intel(R) PRO/1000 Network Driver
624 03:13:41.417475 <6>[ 1.673914] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 03:13:41.423168 <6>[ 1.680389] igb: Intel(R) Gigabit Ethernet Network Driver
626 03:13:41.431446 <6>[ 1.686218] igb: Copyright (c) 2007-2014 Intel Corporation.
627 03:13:41.443219 <6>[ 1.695452] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 03:13:41.449115 <6>[ 1.701616] usbcore: registered new interface driver pegasus
629 03:13:41.451774 <6>[ 1.707745] usbcore: registered new interface driver asix
630 03:13:41.457550 <6>[ 1.713635] usbcore: registered new interface driver ax88179_178a
631 03:13:41.463297 <6>[ 1.720204] usbcore: registered new interface driver cdc_ether
632 03:13:41.469163 <6>[ 1.726538] usbcore: registered new interface driver smsc75xx
633 03:13:41.477822 <6>[ 1.732769] usbcore: registered new interface driver smsc95xx
634 03:13:41.483512 <6>[ 1.738994] usbcore: registered new interface driver net1080
635 03:13:41.489353 <6>[ 1.745139] usbcore: registered new interface driver cdc_subset
636 03:13:41.497922 <6>[ 1.751548] usbcore: registered new interface driver zaurus
637 03:13:41.502994 <6>[ 1.757588] usbcore: registered new interface driver cdc_ncm
638 03:13:41.512911 <6>[ 1.767020] usbcore: registered new interface driver usb-storage
639 03:13:41.818339 <6>[ 2.074278] i2c_dev: i2c /dev entries driver
640 03:13:41.887512 <5>[ 2.137343] cpuidle: enable-method property 'ti,am3352' found operations
641 03:13:41.893448 <6>[ 2.147012] sdhci: Secure Digital Host Controller Interface driver
642 03:13:41.900833 <6>[ 2.153788] sdhci: Copyright(c) Pierre Ossman
643 03:13:41.907999 <6>[ 2.160170] Synopsys Designware Multimedia Card Interface Driver
644 03:13:41.913455 <6>[ 2.168084] sdhci-pltfm: SDHCI platform and OF driver helper
645 03:13:42.040956 <6>[ 2.291506] usbcore: registered new interface driver usbhid
646 03:13:42.041464 <6>[ 2.297544] usbhid: USB HID core driver
647 03:13:42.071352 <6>[ 2.326721] NET: Registered PF_INET6 protocol family
648 03:13:42.104440 <6>[ 2.362409] Segment Routing with IPv6
649 03:13:42.110436 <6>[ 2.366554] In-situ OAM (IOAM) with IPv6
650 03:13:42.117036 <6>[ 2.371107] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 03:13:42.122876 <6>[ 2.378406] NET: Registered PF_PACKET protocol family
652 03:13:42.128827 <6>[ 2.383980] can: controller area network core
653 03:13:42.134507 <6>[ 2.388810] NET: Registered PF_CAN protocol family
654 03:13:42.134963 <6>[ 2.394045] can: raw protocol
655 03:13:42.140371 <6>[ 2.397372] can: broadcast manager protocol
656 03:13:42.146873 <6>[ 2.401975] can: netlink gateway - max_hops=1
657 03:13:42.152990 <5>[ 2.407497] Key type dns_resolver registered
658 03:13:42.159322 <6>[ 2.412598] ThumbEE CPU extension supported.
659 03:13:42.159777 <5>[ 2.417289] Registering SWP/SWPB emulation handler
660 03:13:42.169073 <3>[ 2.422994] omap_voltage_late_init: Voltage driver support not added
661 03:13:42.385860 <5>[ 2.641331] Loading compiled-in X.509 certificates
662 03:13:42.542155 <6>[ 2.787019] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 03:13:42.549204 <6>[ 2.803736] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 03:13:42.576030 <3>[ 2.827923] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 03:13:42.779064 <3>[ 3.031003] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 03:13:42.964511 <6>[ 3.220821] OMAP GPIO hardware version 0.1
667 03:13:42.985597 <6>[ 3.239854] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 03:13:43.078051 <4>[ 3.332063] at24 2-0054: supply vcc not found, using dummy regulator
669 03:13:43.110140 <4>[ 3.364069] at24 2-0055: supply vcc not found, using dummy regulator
670 03:13:43.151476 <4>[ 3.405415] at24 2-0056: supply vcc not found, using dummy regulator
671 03:13:43.189833 <4>[ 3.443801] at24 2-0057: supply vcc not found, using dummy regulator
672 03:13:43.228703 <6>[ 3.483367] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 03:13:43.286296 <3>[ 3.537001] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 03:13:43.311162 <6>[ 3.558212] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 03:13:43.332524 <4>[ 3.585217] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 03:13:43.348856 <4>[ 3.601524] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 03:13:43.419478 <6>[ 3.676160] Freeing initrd memory: 14996K
678 03:13:43.428206 <6>[ 3.681763] omap_rng 48310000.rng: Random Number Generator ver. 20
679 03:13:43.451632 <5>[ 3.708478] random: crng init done
680 03:13:43.497713 <6>[ 3.750375] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 03:13:43.551090 <6>[ 3.802824] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 03:13:43.556849 <6>[ 3.813140] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 03:13:43.568665 <6>[ 3.820477] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 03:13:43.574436 <6>[ 3.827951] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 03:13:43.586046 <6>[ 3.836090] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 03:13:43.593463 <6>[ 3.847733] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 03:13:43.606615 <5>[ 3.856851] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 03:13:43.635093 <3>[ 3.887308] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 03:13:43.640850 <6>[ 3.895910] edma 49000000.dma: TI EDMA DMA engine driver
690 03:13:43.713677 <3>[ 3.965216] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 03:13:43.728526 <6>[ 3.979729] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 03:13:43.741645 <3>[ 3.997017] l3-aon-clkctrl:0000:0: failed to disable
693 03:13:43.797081 <6>[ 4.049197] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 03:13:43.802749 <6>[ 4.058716] printk: legacy console [ttyS0] enabled
695 03:13:43.808380 <6>[ 4.058716] printk: legacy console [ttyS0] enabled
696 03:13:43.814071 <6>[ 4.069051] printk: legacy bootconsole [omap8250] disabled
697 03:13:43.819932 <6>[ 4.069051] printk: legacy bootconsole [omap8250] disabled
698 03:13:43.850108 <4>[ 4.101184] tps65217-pmic: Failed to locate of_node [id: -1]
699 03:13:43.853537 <4>[ 4.108585] tps65217-bl: Failed to locate of_node [id: -1]
700 03:13:43.870573 <6>[ 4.128811] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 03:13:43.891102 <6>[ 4.135818] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 03:13:43.902709 <6>[ 4.149518] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 03:13:43.905423 <6>[ 4.161404] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 03:13:43.929079 <6>[ 4.181540] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 03:13:43.934859 <6>[ 4.190721] sdhci-omap 48060000.mmc: Got CD GPIO
706 03:13:43.942923 <4>[ 4.195874] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 03:13:43.958094 <4>[ 4.209707] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 03:13:43.964365 <4>[ 4.218511] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 03:13:43.974241 <4>[ 4.227164] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 03:13:44.073501 <6>[ 4.327221] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 03:13:44.113444 <6>[ 4.366153] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
712 03:13:44.133778 <6>[ 4.385507] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
713 03:13:44.140480 <6>[ 4.394439] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 03:13:44.181721 <6>[ 4.429844] mmc0: new high speed SDHC card at address 0001
715 03:13:44.182188 <6>[ 4.437865] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 03:13:44.188849 <6>[ 4.446764] mmcblk0: p1
717 03:13:44.221754 <6>[ 4.471654] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
718 03:13:44.237669 <4>[ 4.488463] mmc1: unexpected status 0x2000980 after switch
719 03:13:44.243795 <4>[ 4.496067] mmc1: unexpected status 0x2000900 after switch
720 03:13:44.250169 <4>[ 4.502395] mmc1: unexpected status 0x2000900 after switch
721 03:13:44.255810 <4>[ 4.508936] mmc1: unexpected status 0x2000900 after switch
722 03:13:44.266577 <6>[ 4.514827] mmc1: new high speed MMC card at address 0001
723 03:13:44.267073 <6>[ 4.522587] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 03:13:45.962221 <4>[ 6.212801] mmc1: unexpected status 0x2000980 after switch
725 03:13:45.968599 <4>[ 6.220473] mmc1: unexpected status 0x2000900 after switch
726 03:13:45.975158 <4>[ 6.226756] mmc1: unexpected status 0x2000900 after switch
727 03:13:45.978875 <4>[ 6.233646] mmc1: unexpected status 0x2000900 after switch
728 03:13:46.339546 <6>[ 6.591452] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 03:13:46.482878 <5>[ 6.620383] Sending DHCP requests ., OK
730 03:13:46.493988 <6>[ 6.744810] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 03:13:46.494481 <6>[ 6.752977] IP-Config: Complete:
732 03:13:46.508047 <6>[ 6.756517] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 03:13:46.513773 <6>[ 6.767040] host=192.168.6.16, domain=, nis-domain=(none)
734 03:13:46.517296 <6>[ 6.773258] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 03:13:46.524049 <6>[ 6.773294] nameserver0=10.255.253.1
736 03:13:46.530225 <6>[ 6.785906] clk: Disabling unused clocks
737 03:13:46.535268 <6>[ 6.790682] PM: genpd: Disabling unused power domains
738 03:13:46.553036 <6>[ 6.807576] Freeing unused kernel image (initmem) memory: 2048K
739 03:13:46.560674 <6>[ 6.817460] Run /init as init process
740 03:13:46.587008 Loading, please wait...
741 03:13:46.664626 Starting systemd-udevd version 252.22-1~deb12u1
742 03:13:46.721656 <3>[ 6.973734] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
743 03:13:47.458626 <3>[ 7.710777] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 03:13:48.198511 <3>[ 8.450677] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 03:13:48.941632 <3>[ 9.193797] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 03:13:49.689284 <3>[ 9.942551] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 03:13:49.873841 <4>[ 10.124729] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 03:13:50.040511 <4>[ 10.291491] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 03:13:50.193599 <6>[ 10.452082] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 03:13:50.204374 <6>[ 10.457771] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 03:13:50.427180 <6>[ 10.683612] tda998x 0-0070: found TDA19988
752 03:13:50.448347 <3>[ 10.700650] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
753 03:13:50.714160 <6>[ 10.970920] hub 1-0:1.0: USB hub found
754 03:13:50.733770 <6>[ 10.990599] hub 1-0:1.0: 1 port detected
755 03:13:51.238432 <3>[ 11.490696] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 03:13:51.566464 <6>[ 11.820672] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 03:13:51.746040 <3>[ 12.000867] usb 1-1: device descriptor read/64, error -71
758 03:13:51.972036 <3>[ 12.224023] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
759 03:13:51.979647 <3>[ 12.232933] Buffer I/O error on dev mmcblk1, logical block 0, async page read
760 03:13:51.999162 <3>[ 12.254111] usb 1-1: device descriptor read/64, error -71
761 03:13:52.236674 <6>[ 12.490683] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 03:13:52.405679 <3>[ 12.660715] usb 1-1: device descriptor read/64, error -71
763 03:13:52.655874 <3>[ 12.910736] usb 1-1: device descriptor read/64, error -71
764 03:13:52.783682 <6>[ 13.039604] usb usb1-port1: attempt power cycle
765 03:13:52.976716 <6>[ 13.230664] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 03:13:53.566847 <6>[ 13.820809] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 03:13:54.034766 Begin: Loading essential drivers ... done.
768 03:13:54.040240 Begin: Running /scripts/init-premount ... done.
769 03:13:54.045849 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 03:13:54.059721 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 03:13:54.060329 Device /sys/class/net/eth0 found
772 03:13:54.060812 done.
773 03:13:54.137439 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 03:13:54.235374 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
775 03:13:54.421986 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 03:13:54.427438 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 03:13:54.433106 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 03:13:54.444370 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 03:13:54.444915 rootserver: 192.168.6.1 rootpath:
780 03:13:54.447779 filename :
781 03:13:54.565410 done.
782 03:13:54.578975 Begin: Running /scripts/nfs-bottom ... done.
783 03:13:54.647787 Begin: Running /scripts/init-bottom ... done.
784 03:13:55.111259 <3>[ 15.363365] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
785 03:13:57.704590 <3>[ 17.956866] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
786 03:13:57.902750 <30>[ 18.156826] systemd[1]: System time before build time, advancing clock.
787 03:13:58.087015 <30>[ 18.314804] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
788 03:13:58.096369 <30>[ 18.352035] systemd[1]: Detected architecture arm.
789 03:13:58.111855
790 03:13:58.112400 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
791 03:13:58.112862
792 03:13:58.135469 <30>[ 18.390111] systemd[1]: Hostname set to <debian-bookworm-armhf>.
793 03:13:58.442823 <3>[ 18.694985] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
794 03:13:59.195588 <3>[ 19.447904] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 03:13:59.929993 <3>[ 20.182404] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 03:14:00.469322 <30>[ 20.723040] systemd[1]: Queued start job for default target graphical.target.
797 03:14:00.485928 <30>[ 20.737642] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
798 03:14:00.493683 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
799 03:14:00.522583 <30>[ 20.773255] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
800 03:14:00.530074 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
801 03:14:00.554582 <30>[ 20.806657] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
802 03:14:00.568269 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
803 03:14:00.589797 <30>[ 20.842256] systemd[1]: Created slice user.slice - User and Session Slice.
804 03:14:00.596542 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
805 03:14:00.625406 <30>[ 20.871828] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
806 03:14:00.631502 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
807 03:14:00.665431 <3>[ 20.917141] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
808 03:14:00.680608 <30>[ 20.927395] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
809 03:14:00.687512 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
810 03:14:00.720380 <30>[ 20.961661] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
811 03:14:00.726783 <30>[ 20.982192] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
812 03:14:00.735350 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
813 03:14:00.758403 <30>[ 21.010920] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
814 03:14:00.766663 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
815 03:14:00.789081 <30>[ 21.041260] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
816 03:14:00.797505 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
817 03:14:00.819296 <30>[ 21.071676] systemd[1]: Reached target paths.target - Path Units.
818 03:14:00.824385 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
819 03:14:00.848667 <30>[ 21.101058] systemd[1]: Reached target remote-fs.target - Remote File Systems.
820 03:14:00.856075 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
821 03:14:00.878491 <30>[ 21.130948] systemd[1]: Reached target slices.target - Slice Units.
822 03:14:00.883969 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
823 03:14:00.910454 <30>[ 21.162294] systemd[1]: Reached target swap.target - Swaps.
824 03:14:00.914529 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
825 03:14:00.938850 <30>[ 21.191166] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
826 03:14:00.947777 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
827 03:14:00.970786 <30>[ 21.222039] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
828 03:14:00.978134 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
829 03:14:01.069753 <30>[ 21.317144] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
830 03:14:01.082886 <30>[ 21.335014] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
831 03:14:01.091356 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
832 03:14:01.121256 <30>[ 21.374897] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
833 03:14:01.133779 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
834 03:14:01.162392 <30>[ 21.413759] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
835 03:14:01.169602 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
836 03:14:01.204112 <30>[ 21.454960] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
837 03:14:01.209712 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
838 03:14:01.242702 <30>[ 21.493779] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
839 03:14:01.250245 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
840 03:14:01.275683 <30>[ 21.522044] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
841 03:14:01.292444 <30>[ 21.538549] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
842 03:14:01.342866 <30>[ 21.596008] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
843 03:14:01.391167 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
844 03:14:01.399126 <3>[ 21.650414] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
845 03:14:01.413222 <30>[ 21.666276] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
846 03:14:01.433469 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
847 03:14:01.501897 <30>[ 21.753909] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
848 03:14:01.530921 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
849 03:14:01.588914 <30>[ 21.841522] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
850 03:14:01.617648 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
851 03:14:01.670822 <30>[ 21.923811] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
852 03:14:01.697876 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
853 03:14:01.748853 <30>[ 22.002279] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
854 03:14:01.766701 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
855 03:14:01.792352 <30>[ 22.044634] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
856 03:14:01.818560 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
857 03:14:01.870693 <30>[ 22.124057] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
858 03:14:01.897373 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
859 03:14:01.926245 <30>[ 22.179516] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
860 03:14:01.957485 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
861 03:14:01.985514 <28>[ 22.232677] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
862 03:14:01.993975 <28>[ 22.246406] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
863 03:14:02.037994 <30>[ 22.291757] systemd[1]: Starting systemd-journald.service - Journal Service...
864 03:14:02.049546 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
865 03:14:02.132237 <3>[ 22.385265] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
866 03:14:02.138067 <3>[ 22.394278] Buffer I/O error on dev mmcblk1, logical block 0, async page read
867 03:14:02.147140 <6>[ 22.401908] mmcblk1: unable to read partition table
868 03:14:02.154760 <6>[ 22.407786] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
869 03:14:02.163376 <30>[ 22.414966] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
870 03:14:02.177677 Starting [0;1;39msystemd-modules-l…rvice[0m - Load <6>[ 22.427774] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
871 03:14:02.178169 Kernel Modules...
872 03:14:02.198510 <30>[ 22.451847] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
873 03:14:02.225410 <6>[ 22.480261] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
874 03:14:02.270906 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 03:14:02.330102 <30>[ 22.581794] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 03:14:02.354681 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 03:14:02.421099 <30>[ 22.673602] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 03:14:02.470335 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 03:14:02.550321 <30>[ 22.803716] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 03:14:02.611632 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 03:14:02.618823 <30>[ 22.873113] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 03:14:02.663819 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 03:14:02.681050 <30>[ 22.933279] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 03:14:02.731729 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 03:14:02.879177 <30>[ 23.132994] systemd[1]: modprobe@configfs.service: Deactivated successfully.
886 03:14:02.909841 <30>[ 23.162474] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
887 03:14:02.938483 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 03:14:02.969247 <30>[ 23.223177] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
889 03:14:02.998949 <30>[ 23.252086] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
890 03:14:03.028483 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
891 03:14:03.048936 <30>[ 23.303364] systemd[1]: modprobe@drm.service: Deactivated successfully.
892 03:14:03.068384 <30>[ 23.322111] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
893 03:14:03.097382 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
894 03:14:03.109744 <30>[ 23.363434] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
895 03:14:03.139754 <30>[ 23.392266] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
896 03:14:03.168340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
897 03:14:03.178907 <30>[ 23.433265] systemd[1]: modprobe@fuse.service: Deactivated successfully.
898 03:14:03.218730 <30>[ 23.472236] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
899 03:14:03.237577 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
900 03:14:03.259351 <30>[ 23.511976] systemd[1]: Started systemd-journald.service - Journal Service.
901 03:14:03.266159 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
902 03:14:03.309714 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
903 03:14:03.341943 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
904 03:14:03.371751 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
905 03:14:03.401049 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
906 03:14:03.428505 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
907 03:14:03.507549 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
908 03:14:03.584723 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
909 03:14:03.640136 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
910 03:14:03.722529 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
911 03:14:03.820655 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
912 03:14:03.965157 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
913 03:14:04.004788 <46>[ 24.257886] systemd-journald[164]: Received client request to flush runtime journal.
914 03:14:04.082182 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
915 03:14:04.776762 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
916 03:14:05.193721 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
917 03:14:05.260857 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
918 03:14:05.772652 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
919 03:14:06.045425 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
920 03:14:06.078454 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
921 03:14:06.098376 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
922 03:14:06.183409 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
923 03:14:06.226088 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
924 03:14:07.190242 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
925 03:14:07.299581 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
926 03:14:07.331273 <4>[ 27.586753] mmc1: unexpected status 0x2000980 after switch
927 03:14:07.361616 <4>[ 27.617064] mmc1: unexpected status 0x2000900 after switch
928 03:14:07.419247 <4>[ 27.674744] mmc1: unexpected status 0x2000900 after switch
929 03:14:07.488059 <4>[ 27.743695] mmc1: unexpected status 0x2000900 after switch
930 03:14:07.768618 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
931 03:14:07.906090 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
932 03:14:08.002952 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
933 03:14:09.663595 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
934 03:14:10.154037 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
935 03:14:10.349347 <5>[ 30.602896] cfg80211: Loading compiled-in X.509 certificates for regulatory database
936 03:14:10.655962 <3>[ 30.907906] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
937 03:14:11.422088 <3>[ 31.673993] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
938 03:14:11.498557 <5>[ 31.752853] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
939 03:14:11.558645 <5>[ 31.812685] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
940 03:14:11.577412 <4>[ 31.830881] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
941 03:14:11.583372 <6>[ 31.839858] cfg80211: failed to load regulatory.db
942 03:14:12.173022 <3>[ 32.424800] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
943 03:14:12.319711 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
944 03:14:12.539259 <46>[ 32.783621] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
945 03:14:12.604897 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
946 03:14:12.745852 <46>[ 32.992311] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
947 03:14:12.919339 <3>[ 33.171145] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
948 03:14:13.671682 <3>[ 33.923619] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
949 03:14:14.428734 <3>[ 34.680646] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
950 03:14:14.755904 [[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
951 03:14:15.168713 <3>[ 35.420517] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
952 03:14:15.226661 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
953 03:14:15.609640 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
954 03:14:15.902561 <3>[ 36.154823] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
955 03:14:16.044832 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
956 03:14:16.544615 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
957 03:14:16.985924 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
958 03:14:17.504704 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
959 03:14:17.874769 M
[K[ [0;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
960 03:14:18.266453 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
961 03:14:18.614509 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
962 03:14:18.977746 <3>[ 39.230464] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
963 03:14:18.992098 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
964 03:14:19.474563 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
965 03:14:19.528021 M
[K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
966 03:14:19.547383 [K[[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
967 03:14:19.572679 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
968 03:14:19.649446 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
969 03:14:19.724186 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Mod<3>[ 39.969781] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
970 03:14:19.724812 ule efi_pstore...
971 03:14:19.769048 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
972 03:14:19.823612 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
973 03:14:19.897350 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
974 03:14:19.926244 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
975 03:14:19.953975 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
976 03:14:19.984033 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
977 03:14:20.019934 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
978 03:14:20.047647 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
979 03:14:20.073650 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
980 03:14:20.106515 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
981 03:14:20.157721 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
982 03:14:20.184595 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
983 03:14:20.209418 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
984 03:14:20.231091 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
985 03:14:20.268898 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
986 03:14:20.288507 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
987 03:14:20.311507 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
988 03:14:20.378273 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
989 03:14:20.421715 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
990 03:14:20.474130 <3>[ 40.726709] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
991 03:14:20.555758 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
992 03:14:20.641561 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
993 03:14:20.731936 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
994 03:14:20.788064 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
995 03:14:20.817038 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
996 03:14:20.982532 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
997 03:14:21.059354 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
998 03:14:21.086933 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
999 03:14:21.208591 <3>[ 41.461144] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1000 03:14:21.515571 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1001 03:14:21.780537 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1002 03:14:21.977747 <3>[ 42.230176] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1003 03:14:22.746794 <3>[ 42.999225] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1004 03:14:23.515786 <3>[ 43.768311] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1005 03:14:24.045838 [[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (23s / 1min 30s)
1006 03:14:24.283855 <3>[ 44.537442] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1007 03:14:24.292879 <3>[ 44.546935] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1008 03:14:25.088038 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (24s / 1min 30s)
1009 03:14:26.317275 M
[K[[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1010 03:14:27.534456 [K[[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1011 03:14:27.691375 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1012 03:14:27.713531 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1013 03:14:27.748058 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1014 03:14:27.774757 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1015 03:14:27.839544 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1016 03:14:28.121976
1017 03:14:28.126260 Debian GNU/Linux 12 debian-boworm-armhf login: root (automatic login)
1018 03:14:28.126775
1019 03:14:28.404957 <3>[ 48.657377] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1020 03:14:28.541805 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Fri Nov 1 00:34:39 UTC 2024 armv7l
1021 03:14:28.542371
1022 03:14:28.547381 The programs included with the Debian GNU/Linux system are free software;
1023 03:14:28.552946 the exact distribution terms for each program are described in the
1024 03:14:28.558591 individual files in /usr/share/doc/*/copyright.
1025 03:14:28.559088
1026 03:14:28.565837 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1027 03:14:28.566337 permitted by applicable law.
1028 03:14:29.139292 <3>[ 49.391742] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1029 03:14:29.873379 <3>[ 50.125776] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1030 03:14:30.607384 <3>[ 50.859818] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1031 03:14:31.341379 <3>[ 51.593863] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1032 03:14:32.075430 <3>[ 52.327941] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1033 03:14:32.811147 <3>[ 53.063613] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1034 03:14:33.477485 Unable to match end of the kernel message
1036 03:14:33.479160 Setting prompt string to ['/ #']
1037 03:14:33.479797 end: 2.4.4.1 login-action (duration 00:00:54) [common]
1039 03:14:33.481485 end: 2.4.4 auto-login-action (duration 00:00:55) [common]
1040 03:14:33.482102 start: 2.4.5 expect-shell-connection (timeout 00:02:44) [common]
1041 03:14:33.482596 Setting prompt string to ['/ #']
1042 03:14:33.483068 Forcing a shell prompt, looking for ['/ #']
1044 03:14:33.534148 / #
1045 03:14:33.534889 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1046 03:14:33.535459 Waiting using forced prompt support (timeout 00:02:30)
1047 03:14:33.547223 <3>[ 53.799323] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1048 03:14:33.547837
1049 03:14:33.552768 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1050 03:14:33.553483 start: 2.4.6 export-device-env (timeout 00:02:43) [common]
1051 03:14:33.553993 Sending with 10 millisecond of delay
1053 03:14:38.545328 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/919674/extract-nfsrootfs-vo2hwwha'
1054 03:14:38.556261 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/919<3>[ 56.987394] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1055 03:14:38.556755 674/extract-n<3>[ 57.722756] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1056 03:14:38.557174 fsrootfs-vo2<3>[ 58.491738] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1057 03:14:38.557578 hwwha'
1058 03:14:38.562853 Sending with 10 millisecond of delay
1060 03:14:40.662396 / # export NFS_SERVER_IP='192.168.6.2'
1061 03:14:40.673351 export<3>[ 59.260863] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1062 03:14:40.673850 NFS_SERVER_I<3>[ 60.029876] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1063 03:14:40.674263 P='192.168.6<3>[ 60.799021] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1064 03:14:40.674670 .2'
1065 03:14:40.675508 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1066 03:14:40.676110 end: 2.4 uboot-commands (duration 00:02:24) [common]
1067 03:14:40.676692 end: 2 uboot-action (duration 00:02:24) [common]
1068 03:14:40.677244 start: 3 lava-test-retry (timeout 00:06:26) [common]
1069 03:14:40.677800 start: 3.1 lava-test-shell (timeout 00:06:26) [common]
1070 03:14:40.678250 Using namespace: common
1072 03:14:40.779395 / # #
1073 03:14:40.780059 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1074 03:14:40.785196 #
1075 03:14:40.792073 Using /lava-919674
1077 03:14:40.893193 / # export SHELL=/bin/bash
1078 03:14:40.898699 export SHELL=/bin/bash
1080 03:14:41.005706 / # . /lava-919674/environment
1081 03:14:41.011149 . /lava-919674/environment
1083 03:14:41.125194 / # /lava-919674/bin/lava-test-runner /lava-919674/0
1084 03:14:41.125808 Test shell timeout: 10s (minimum of the action and connection timeout)
1085 03:14:41.130639 /lava-919674/bin/lava-test-runner /lava-919674/0
1086 03:14:41.279692 <3>[ 61.533015] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1087 03:14:41.569316 + export TESTRUN_ID=0_timesync-off
1088 03:14:41.576862 + TESTRUN_ID=0_timesync-off
1089 03:14:41.577308 + cd /lava-919674/0/tests/0_timesync-off
1090 03:14:41.577717 ++ cat uuid
1091 03:14:41.594134 + UUID=919674_1.6.2.4.1
1092 03:14:41.594570 + set +x
1093 03:14:41.603431 <LAVA_SIGNAL_STARTRUN 0_timesync-off 919674_1.6.2.4.1>
1094 03:14:41.603888 + systemctl stop systemd-timesyncd
1095 03:14:41.604623 Received signal: <STARTRUN> 0_timesync-off 919674_1.6.2.4.1
1096 03:14:41.605067 Starting test lava.0_timesync-off (919674_1.6.2.4.1)
1097 03:14:41.605583 Skipping test definition patterns.
1098 03:14:41.922251 + set +x
1099 03:14:41.922772 <LAVA_SIGNAL_ENDRUN 0_timesync-off 919674_1.6.2.4.1>
1100 03:14:41.923430 Received signal: <ENDRUN> 0_timesync-off 919674_1.6.2.4.1
1101 03:14:41.923910 Ending use of test pattern.
1102 03:14:41.924347 Ending test lava.0_timesync-off (919674_1.6.2.4.1), duration 0.32
1104 03:14:42.012516 <3>[ 62.266937] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1105 03:14:42.021497 <3>[ 62.276337] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1106 03:14:42.195444 + export TESTRUN_ID=1_kselftest-dt
1107 03:14:42.203494 + TESTRUN_ID=1_kselftest-dt
1108 03:14:42.203927 + cd /lava-919674/0/tests/1_kselftest-dt
1109 03:14:42.204366 ++ cat uuid
1110 03:14:42.220184 + UUID=919674_1.6.2.4.5
1111 03:14:42.220616 + set +x
1112 03:14:42.225676 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 919674_1.6.2.4.5>
1113 03:14:42.226103 + cd ./automated/linux/kselftest/
1114 03:14:42.226771 Received signal: <STARTRUN> 1_kselftest-dt 919674_1.6.2.4.5
1115 03:14:42.227190 Starting test lava.1_kselftest-dt (919674_1.6.2.4.5)
1116 03:14:42.227668 Skipping test definition patterns.
1117 03:14:42.253923 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1118 03:14:42.357253 INFO: install_deps skipped
1119 03:14:42.977570 --2024-11-01 03:14:42-- http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1120 03:14:43.011333 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1121 03:14:43.149184 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1122 03:14:43.285430 HTTP request sent, awaiting response... 200 OK
1123 03:14:43.285953 Length: 2714836 (2.6M) [application/octet-stream]
1124 03:14:43.290856 Saving to: 'kselftest_armhf.tar.gz'
1125 03:14:43.291296
1126 03:14:44.906774
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 186KB/s
kselftest_armhf.tar 8%[> ] 218.67K 408KB/s
kselftest_armhf.tar 22%[===> ] 601.60K 720KB/s
kselftest_armhf.tar 44%[=======> ] 1.16M 1.04MB/s
kselftest_armhf.tar 77%[==============> ] 2.00M 1.36MB/s
kselftest_armhf.tar 100%[===================>] 2.59M 1.60MB/s in 1.6s
1127 03:14:44.907379
1128 03:14:45.458558 2024-11-01 03:14:44 (1.60 MB/s) - 'kselftest_armhf.tar.gz' saved [2714836/2714836]
1129 03:14:45.459152
1130 03:14:56.493147 skiplist:
1131 03:14:56.493746 ========================================
1132 03:14:56.498837 ========================================
1133 03:14:56.602883 dt:test_unprobed_devices.sh
1134 03:14:56.633993 ============== Tests to run ===============
1135 03:14:56.642302 dt:test_unprobed_devices.sh
1136 03:14:56.646292 ===========End Tests to run ===============
1137 03:14:56.657299 shardfile-dt pass
1138 03:14:56.888060 <12>[ 77.146691] kselftest: Running tests in dt
1139 03:14:56.917255 TAP version 13
1140 03:14:56.941968 1..1
1141 03:14:56.997365 # timeout set to 45
1142 03:14:56.997816 # selftests: dt: test_unprobed_devices.sh
1143 03:14:57.824595 # TAP version 13
1144 03:15:23.368335 # 1..257
1145 03:15:23.535450 # ok 1 / # SKIP
1146 03:15:23.557648 # ok 2 /clk_mcasp0
1147 03:15:23.637330 # ok 3 /clk_mcasp0_fixed # SKIP
1148 03:15:23.708866 # ok 4 /cpus/cpu@0 # SKIP
1149 03:15:23.779105 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1150 03:15:23.800073 # ok 6 /fixedregulator0
1151 03:15:23.820619 # ok 7 /leds
1152 03:15:23.846473 # ok 8 /ocp
1153 03:15:23.865957 # ok 9 /ocp/interconnect@44c00000
1154 03:15:23.891096 # ok 10 /ocp/interconnect@44c00000/segment@0
1155 03:15:23.913635 # ok 11 /ocp/interconnect@44c00000/segment@100000
1156 03:15:23.942482 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1157 03:15:24.014052 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1158 03:15:24.034463 # ok 14 /ocp/interconnect@44c00000/segment@200000
1159 03:15:24.059345 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1160 03:15:24.171029 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1161 03:15:24.244235 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1162 03:15:24.321155 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1163 03:15:24.395137 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1164 03:15:24.463558 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1165 03:15:24.537633 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1166 03:15:24.612207 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1167 03:15:24.689119 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1168 03:15:24.759536 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1169 03:15:24.838662 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1170 03:15:24.913199 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1171 03:15:24.985126 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1172 03:15:25.061602 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1173 03:15:25.135171 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1174 03:15:25.205249 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1175 03:15:25.278274 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1176 03:15:25.353393 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1177 03:15:25.430022 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1178 03:15:25.500586 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1179 03:15:25.579850 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1180 03:15:25.650364 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1181 03:15:25.725220 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1182 03:15:25.798977 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1183 03:15:25.873529 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1184 03:15:25.948062 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1185 03:15:26.021397 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1186 03:15:26.097094 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1187 03:15:26.169783 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1188 03:15:26.244814 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1189 03:15:26.319584 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1190 03:15:26.393098 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1191 03:15:26.468309 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1192 03:15:26.541666 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1193 03:15:26.616115 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1194 03:15:26.689398 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1195 03:15:26.764575 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1196 03:15:26.842713 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1197 03:15:26.912823 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1198 03:15:26.992229 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1199 03:15:27.061581 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1200 03:15:27.138935 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1201 03:15:27.210912 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1202 03:15:27.286738 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1203 03:15:27.360239 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1204 03:15:27.434359 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1205 03:15:27.508954 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1206 03:15:27.584249 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1207 03:15:27.660175 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1208 03:15:27.734040 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1209 03:15:27.807912 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1210 03:15:27.885796 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1211 03:15:27.961885 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1212 03:15:28.035408 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1213 03:15:28.105111 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1214 03:15:28.179630 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1215 03:15:28.253501 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1216 03:15:28.328311 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1217 03:15:28.404964 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1218 03:15:28.477697 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1219 03:15:28.555879 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1220 03:15:28.627232 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1221 03:15:28.701816 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1222 03:15:28.775932 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1223 03:15:28.849369 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1224 03:15:28.923889 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1225 03:15:29.002329 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1226 03:15:29.072118 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1227 03:15:29.150005 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1228 03:15:29.219854 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1229 03:15:29.293450 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1230 03:15:29.368363 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1231 03:15:29.445174 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1232 03:15:29.516546 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1233 03:15:29.596574 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1234 03:15:29.673740 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1235 03:15:29.740438 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1236 03:15:29.816114 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1237 03:15:29.892620 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1238 03:15:29.969835 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1239 03:15:29.987483 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1240 03:15:30.012358 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1241 03:15:30.037153 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1242 03:15:30.061436 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1243 03:15:30.086015 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1244 03:15:30.110019 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1245 03:15:30.133703 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1246 03:15:30.161889 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1247 03:15:30.264380 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1248 03:15:30.294113 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1249 03:15:30.318814 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1250 03:15:30.344145 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1251 03:15:30.450923 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1252 03:15:30.523930 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1253 03:15:30.597939 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1254 03:15:30.672432 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1255 03:15:30.746861 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1256 03:15:30.820355 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1257 03:15:30.894913 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1258 03:15:30.969229 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1259 03:15:31.045531 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1260 03:15:31.123889 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1261 03:15:31.197055 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1262 03:15:31.272901 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1263 03:15:31.341078 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1264 03:15:31.420784 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1265 03:15:31.493348 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1266 03:15:31.573272 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1267 03:15:31.595148 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1268 03:15:31.664799 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1269 03:15:31.736665 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1270 03:15:31.811326 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1271 03:15:31.838576 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1272 03:15:31.912128 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1273 03:15:31.932539 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1274 03:15:32.004424 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1275 03:15:32.027242 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1276 03:15:32.052927 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1277 03:15:32.075647 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1278 03:15:32.100597 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1279 03:15:32.128341 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1280 03:15:32.152906 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1281 03:15:32.180501 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1282 03:15:32.256255 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1283 03:15:32.275813 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1284 03:15:32.299876 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1285 03:15:32.372713 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1286 03:15:32.447162 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1287 03:15:32.468310 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1288 03:15:32.572103 # not ok 144 /ocp/interconnect@47c00000
1289 03:15:32.649546 # not ok 145 /ocp/interconnect@47c00000/segment@0
1290 03:15:32.669154 # ok 146 /ocp/interconnect@48000000
1291 03:15:32.691931 # ok 147 /ocp/interconnect@48000000/segment@0
1292 03:15:32.716375 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1293 03:15:32.742228 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1294 03:15:32.768289 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1295 03:15:32.791926 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1296 03:15:32.811410 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1297 03:15:32.836392 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1298 03:15:32.859443 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1299 03:15:32.937561 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1300 03:15:33.008348 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1301 03:15:33.030533 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1302 03:15:33.055322 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1303 03:15:33.077817 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1304 03:15:33.106477 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1305 03:15:33.126349 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1306 03:15:33.150870 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1307 03:15:33.174019 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1308 03:15:33.198386 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1309 03:15:33.221380 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1310 03:15:33.246477 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1311 03:15:33.271352 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1312 03:15:33.294539 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1313 03:15:33.317560 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1314 03:15:33.341744 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1315 03:15:33.365417 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1316 03:15:33.392076 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1317 03:15:33.413845 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1318 03:15:33.438909 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1319 03:15:33.460300 # ok 175 /ocp/interconnect@48000000/segment@100000
1320 03:15:33.490218 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1321 03:15:33.512130 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1322 03:15:33.585785 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1323 03:15:33.661947 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1324 03:15:33.733296 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1325 03:15:33.809601 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1326 03:15:33.880475 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1327 03:15:33.957447 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1328 03:15:34.027263 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1329 03:15:34.103533 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1330 03:15:34.124310 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1331 03:15:34.148022 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1332 03:15:34.172476 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1333 03:15:34.195091 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1334 03:15:34.222446 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1335 03:15:34.251104 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1336 03:15:34.270232 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1337 03:15:34.295179 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1338 03:15:34.318337 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1339 03:15:34.346666 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1340 03:15:34.365705 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1341 03:15:34.391081 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1342 03:15:34.412428 # ok 198 /ocp/interconnect@48000000/segment@200000
1343 03:15:34.441556 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1344 03:15:34.517494 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1345 03:15:34.533384 # ok 201 /ocp/interconnect@48000000/segment@300000
1346 03:15:34.559083 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1347 03:15:34.583386 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1348 03:15:34.612435 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1349 03:15:34.631568 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1350 03:15:34.659090 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1351 03:15:34.682509 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1352 03:15:34.755510 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1353 03:15:34.774192 # ok 209 /ocp/interconnect@4a000000
1354 03:15:34.800280 # ok 210 /ocp/interconnect@4a000000/segment@0
1355 03:15:34.828332 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1356 03:15:34.852814 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1357 03:15:34.875694 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1358 03:15:34.897368 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1359 03:15:34.972708 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1360 03:15:35.084299 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1361 03:15:35.156269 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1362 03:15:35.262658 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1363 03:15:35.336288 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1364 03:15:35.409607 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1365 03:15:35.511238 # not ok 221 /ocp/interconnect@4b140000
1366 03:15:35.585353 # not ok 222 /ocp/interconnect@4b140000/segment@0
1367 03:15:35.660774 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1368 03:15:35.684488 # ok 224 /ocp/target-module@40300000
1369 03:15:35.704953 # ok 225 /ocp/target-module@40300000/sram@0
1370 03:15:35.782206 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1371 03:15:35.853020 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1372 03:15:35.873113 # ok 228 /ocp/target-module@47400000
1373 03:15:35.897451 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1374 03:15:35.925299 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1375 03:15:35.948383 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1376 03:15:35.966522 # ok 232 /ocp/target-module@47400000/usb@1400
1377 03:15:35.990185 # ok 233 /ocp/target-module@47400000/usb@1800
1378 03:15:36.015793 # ok 234 /ocp/target-module@47810000
1379 03:15:36.038138 # ok 235 /ocp/target-module@49000000
1380 03:15:36.057217 # ok 236 /ocp/target-module@49000000/dma@0
1381 03:15:36.083850 # ok 237 /ocp/target-module@49800000
1382 03:15:36.107299 # ok 238 /ocp/target-module@49800000/dma@0
1383 03:15:36.124622 # ok 239 /ocp/target-module@49900000
1384 03:15:36.150056 # ok 240 /ocp/target-module@49900000/dma@0
1385 03:15:36.171557 # ok 241 /ocp/target-module@49a00000
1386 03:15:36.198854 # ok 242 /ocp/target-module@49a00000/dma@0
1387 03:15:36.220936 # ok 243 /ocp/target-module@4c000000
1388 03:15:36.289888 # not ok 244 /ocp/target-module@4c000000/emif@0
1389 03:15:36.312898 # ok 245 /ocp/target-module@50000000
1390 03:15:36.335311 # ok 246 /ocp/target-module@53100000
1391 03:15:36.409519 # not ok 247 /ocp/target-module@53100000/sham@0
1392 03:15:36.431546 # ok 248 /ocp/target-module@53500000
1393 03:15:36.508579 # not ok 249 /ocp/target-module@53500000/aes@0
1394 03:15:36.530713 # ok 250 /ocp/target-module@56000000
1395 03:15:36.633473 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1396 03:15:36.707777 # ok 252 /opp-table # SKIP
1397 03:15:36.778030 # ok 253 /soc # SKIP
1398 03:15:36.804217 # ok 254 /sound
1399 03:15:36.828291 # ok 255 /target-module@4b000000
1400 03:15:36.848366 # ok 256 /target-module@4b000000/target-module@140000
1401 03:15:36.869420 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1402 03:15:36.877820 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1403 03:15:36.887222 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1404 03:15:39.152443 dt_test_unprobed_devices_sh_ skip
1405 03:15:39.158228 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1406 03:15:39.163510 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1407 03:15:39.164118 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1408 03:15:39.172543 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1409 03:15:39.173066 dt_test_unprobed_devices_sh_fixedregulator0 pass
1410 03:15:39.178066 dt_test_unprobed_devices_sh_leds pass
1411 03:15:39.183739 dt_test_unprobed_devices_sh_ocp pass
1412 03:15:39.189348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1413 03:15:39.195022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1414 03:15:39.200620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1415 03:15:39.206249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1416 03:15:39.217396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1417 03:15:39.223111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1418 03:15:39.228649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1419 03:15:39.239905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1420 03:15:39.245634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1421 03:15:39.256767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1422 03:15:39.267760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1423 03:15:39.279019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1424 03:15:39.290229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1425 03:15:39.296049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1426 03:15:39.307196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1427 03:15:39.318394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1428 03:15:39.329582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1429 03:15:39.340827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1430 03:15:39.346429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1431 03:15:39.357560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1432 03:15:39.368719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1433 03:15:39.380033 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1434 03:15:39.391145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1435 03:15:39.396796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1436 03:15:39.408019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1437 03:15:39.419131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1438 03:15:39.430303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1439 03:15:39.436099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1440 03:15:39.447192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1441 03:15:39.458379 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1442 03:15:39.469588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1443 03:15:39.480699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1444 03:15:39.492112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1445 03:15:39.503148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1446 03:15:39.514347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1447 03:15:39.525522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1448 03:15:39.536738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1449 03:15:39.547891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1450 03:15:39.559093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1451 03:15:39.570244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1452 03:15:39.581439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1453 03:15:39.592657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1454 03:15:39.603888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1455 03:15:39.615056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1456 03:15:39.626285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1457 03:15:39.637510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1458 03:15:39.648733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1459 03:15:39.660060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1460 03:15:39.671201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1461 03:15:39.682402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1462 03:15:39.688125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1463 03:15:39.699204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1464 03:15:39.710409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1465 03:15:39.721591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1466 03:15:39.732817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1467 03:15:39.744068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1468 03:15:39.755205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1469 03:15:39.766400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1470 03:15:39.777554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1471 03:15:39.788753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1472 03:15:39.794406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1473 03:15:39.805575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1474 03:15:39.816731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1475 03:15:39.827916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1476 03:15:39.839118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1477 03:15:39.850362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1478 03:15:39.861505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1479 03:15:39.872747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1480 03:15:39.883924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1481 03:15:39.895118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1482 03:15:39.906321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1483 03:15:39.917515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1484 03:15:39.928683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1485 03:15:39.939936 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1486 03:15:39.951100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1487 03:15:39.962298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1488 03:15:39.968006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1489 03:15:39.979076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1490 03:15:39.990265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1491 03:15:40.001475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1492 03:15:40.012654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1493 03:15:40.023863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1494 03:15:40.035084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1495 03:15:40.046247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1496 03:15:40.057407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1497 03:15:40.068631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1498 03:15:40.079814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1499 03:15:40.091078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1500 03:15:40.096654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1501 03:15:40.107780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1502 03:15:40.119061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1503 03:15:40.124617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1504 03:15:40.135796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1505 03:15:40.141466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1506 03:15:40.152607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1507 03:15:40.163784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1508 03:15:40.169416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1509 03:15:40.180568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1510 03:15:40.191746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1511 03:15:40.202964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1512 03:15:40.214143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1513 03:15:40.225360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1514 03:15:40.236507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1515 03:15:40.253302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1516 03:15:40.264521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1517 03:15:40.275693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1518 03:15:40.286906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1519 03:15:40.298116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1520 03:15:40.309299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1521 03:15:40.320498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1522 03:15:40.331668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1523 03:15:40.348488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1524 03:15:40.359770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1525 03:15:40.376426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1526 03:15:40.387657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1527 03:15:40.393357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1528 03:15:40.404517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1529 03:15:40.410135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1530 03:15:40.421263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1531 03:15:40.432512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1532 03:15:40.438140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1533 03:15:40.449215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1534 03:15:40.454826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1535 03:15:40.466068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1536 03:15:40.471617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1537 03:15:40.482795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1538 03:15:40.488484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1539 03:15:40.499608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1540 03:15:40.510780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1541 03:15:40.522056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1542 03:15:40.527673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1543 03:15:40.538814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1544 03:15:40.550051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1545 03:15:40.561200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1546 03:15:40.566813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1547 03:15:40.572414 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1548 03:15:40.578030 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1549 03:15:40.583647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1550 03:15:40.589262 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1551 03:15:40.600387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1552 03:15:40.606095 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1553 03:15:40.611643 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1554 03:15:40.622787 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1555 03:15:40.628445 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1556 03:15:40.639593 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1557 03:15:40.645273 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1558 03:15:40.656391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1559 03:15:40.662077 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1560 03:15:40.673174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1561 03:15:40.678843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1562 03:15:40.690040 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1563 03:15:40.695613 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1564 03:15:40.701215 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1565 03:15:40.712344 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1566 03:15:40.717986 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1567 03:15:40.729189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1568 03:15:40.734786 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1569 03:15:40.745914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1570 03:15:40.751625 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1571 03:15:40.762757 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1572 03:15:40.768385 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1573 03:15:40.779497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1574 03:15:40.785249 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1575 03:15:40.796306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1576 03:15:40.801943 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1577 03:15:40.813191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1578 03:15:40.818725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1579 03:15:40.824332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1580 03:15:40.835485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1581 03:15:40.846698 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1582 03:15:40.857855 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1583 03:15:40.869062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1584 03:15:40.880260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1585 03:15:40.885899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1586 03:15:40.897074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1587 03:15:40.908276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1588 03:15:40.919450 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1589 03:15:40.930630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1590 03:15:40.936338 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1591 03:15:40.947454 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1592 03:15:40.953132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1593 03:15:40.964223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1594 03:15:40.969877 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1595 03:15:40.980989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1596 03:15:40.986654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1597 03:15:40.997815 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1598 03:15:41.003481 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1599 03:15:41.014619 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1600 03:15:41.020335 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1601 03:15:41.031462 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1602 03:15:41.037133 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1603 03:15:41.048302 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1604 03:15:41.053919 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1605 03:15:41.059501 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1606 03:15:41.070632 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1607 03:15:41.076324 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1608 03:15:41.087401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1609 03:15:41.093186 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1610 03:15:41.104311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1611 03:15:41.109906 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1612 03:15:41.115533 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1613 03:15:41.121160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1614 03:15:41.132340 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1615 03:15:41.137960 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1616 03:15:41.149263 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1617 03:15:41.154854 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1618 03:15:41.166015 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1619 03:15:41.177257 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1620 03:15:41.188475 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1621 03:15:41.194163 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1622 03:15:41.205331 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1623 03:15:41.216526 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1624 03:15:41.222198 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1625 03:15:41.227776 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1626 03:15:41.233435 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1627 03:15:41.239028 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1628 03:15:41.244606 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1629 03:15:41.250322 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1630 03:15:41.255901 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1631 03:15:41.261493 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1632 03:15:41.272628 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1633 03:15:41.278312 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1634 03:15:41.283909 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1635 03:15:41.289516 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1636 03:15:41.295206 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1637 03:15:41.300721 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1638 03:15:41.306319 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1639 03:15:41.311911 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1640 03:15:41.317500 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1641 03:15:41.323119 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1642 03:15:41.328718 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1643 03:15:41.334342 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1644 03:15:41.339866 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1645 03:15:41.345492 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1646 03:15:41.351113 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1647 03:15:41.356719 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1648 03:15:41.362320 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1649 03:15:41.367910 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1650 03:15:41.373500 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1651 03:15:41.379185 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1652 03:15:41.384767 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1653 03:15:41.390362 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1654 03:15:41.395938 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1655 03:15:41.401591 dt_test_unprobed_devices_sh_opp-table skip
1656 03:15:41.402086 dt_test_unprobed_devices_sh_soc skip
1657 03:15:41.407190 dt_test_unprobed_devices_sh_sound pass
1658 03:15:41.412764 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1659 03:15:41.418386 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1660 03:15:41.424023 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1661 03:15:41.429587 dt_test_unprobed_devices_sh fail
1662 03:15:41.435195 + ../../utils/send-to-lava.sh ./output/result.txt
1663 03:15:41.441189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1664 03:15:41.442156 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1666 03:15:41.447053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1667 03:15:41.447815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1669 03:15:41.536695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1670 03:15:41.537470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1672 03:15:41.631809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1673 03:15:41.632613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1675 03:15:41.721447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1676 03:15:41.722215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1678 03:15:41.812673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1679 03:15:41.813449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1681 03:15:41.907891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1682 03:15:41.908692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1684 03:15:42.000949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1685 03:15:42.001707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1687 03:15:42.090686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1688 03:15:42.091446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1690 03:15:42.181843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1691 03:15:42.182612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1693 03:15:42.280681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1694 03:15:42.281456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1696 03:15:42.370229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1697 03:15:42.371002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1699 03:15:42.469629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1700 03:15:42.470403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1702 03:15:42.564826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1703 03:15:42.565605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1705 03:15:42.652523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1706 03:15:42.653293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1708 03:15:42.742524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1709 03:15:42.743299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1711 03:15:42.839193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1712 03:15:42.839971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1714 03:15:42.928553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1715 03:15:42.929349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1717 03:15:43.017856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1718 03:15:43.018632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1720 03:15:43.113879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1721 03:15:43.114660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1723 03:15:43.202723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1724 03:15:43.203514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1726 03:15:43.297951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1727 03:15:43.298769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1729 03:15:43.392699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1730 03:15:43.393501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1732 03:15:43.487675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1733 03:15:43.488520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1735 03:15:43.577254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1736 03:15:43.578064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1738 03:15:43.672928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1739 03:15:43.673737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1741 03:15:43.761176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1742 03:15:43.761978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1744 03:15:43.852767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1745 03:15:43.853581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1747 03:15:43.946149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1748 03:15:43.946959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1750 03:15:44.035775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1751 03:15:44.036628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1753 03:15:44.128585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1754 03:15:44.129408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1756 03:15:44.217952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1757 03:15:44.218789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1759 03:15:44.306094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1760 03:15:44.306945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1762 03:15:44.402582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1763 03:15:44.403390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1765 03:15:44.490405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1766 03:15:44.491244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1768 03:15:44.584439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1769 03:15:44.585253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1771 03:15:44.673625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1772 03:15:44.674451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1774 03:15:44.770270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1775 03:15:44.771097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1777 03:15:44.859236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1778 03:15:44.860092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1780 03:15:44.947154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1781 03:15:44.947976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1783 03:15:45.042984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1784 03:15:45.043811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1786 03:15:45.131374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1787 03:15:45.132202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1789 03:15:45.226919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1790 03:15:45.227727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1792 03:15:45.323668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1793 03:15:45.324491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1795 03:15:45.419201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1796 03:15:45.419961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1798 03:15:45.510146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1799 03:15:45.510928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1801 03:15:45.607613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1802 03:15:45.608472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1804 03:15:45.704654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1805 03:15:45.705479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1807 03:15:45.811378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1808 03:15:45.812217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1810 03:15:45.908293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1811 03:15:45.909102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1813 03:15:46.004599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1814 03:15:46.005334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1816 03:15:46.098500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1817 03:15:46.099247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1819 03:15:46.187598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1820 03:15:46.188361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1822 03:15:46.276363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1823 03:15:46.277084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1825 03:15:46.373091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1826 03:15:46.373806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1828 03:15:46.467188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1829 03:15:46.467967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1831 03:15:46.561873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1832 03:15:46.562637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1834 03:15:46.658167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1835 03:15:46.658896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1837 03:15:46.752030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1838 03:15:46.752756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1840 03:15:46.840914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1841 03:15:46.841637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1843 03:15:46.935268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1844 03:15:46.936023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1846 03:15:47.026089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1847 03:15:47.026810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1849 03:15:47.120285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1850 03:15:47.121014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1852 03:15:47.216180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1853 03:15:47.216891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1855 03:15:47.313955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1856 03:15:47.314693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1858 03:15:47.409970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1859 03:15:47.410696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1861 03:15:47.508455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1862 03:15:47.509219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1864 03:15:47.603251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1865 03:15:47.604065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1867 03:15:47.692955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1868 03:15:47.693663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1870 03:15:47.787909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1871 03:15:47.788662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1873 03:15:47.878312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1874 03:15:47.879021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1876 03:15:47.968215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1877 03:15:47.968939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1879 03:15:48.063500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1880 03:15:48.064221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1882 03:15:48.152241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1883 03:15:48.152953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1885 03:15:48.248493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1886 03:15:48.249200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1888 03:15:48.338102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1889 03:15:48.338811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1891 03:15:48.428331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1892 03:15:48.429043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1894 03:15:48.524065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1895 03:15:48.524824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1897 03:15:48.612885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1898 03:15:48.613634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1900 03:15:48.708279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1901 03:15:48.708988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1903 03:15:48.797734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1904 03:15:48.798455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1906 03:15:48.887613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1907 03:15:48.888370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1909 03:15:48.983261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1910 03:15:48.984041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1912 03:15:49.071529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1913 03:15:49.072306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1915 03:15:49.165382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1916 03:15:49.166106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1918 03:15:49.255499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1919 03:15:49.256218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1921 03:15:49.349027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1922 03:15:49.349665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1924 03:15:49.438012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1925 03:15:49.438587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1927 03:15:49.526853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1928 03:15:49.527458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1930 03:15:49.625373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1931 03:15:49.625987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1933 03:15:49.719691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1934 03:15:49.720310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1936 03:15:49.812483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1937 03:15:49.813134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1939 03:15:49.909365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1940 03:15:49.910012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1942 03:15:50.063631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1943 03:15:50.064305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1945 03:15:50.164635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1946 03:15:50.165176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1948 03:15:50.256923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1949 03:15:50.257653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1951 03:15:50.351355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1952 03:15:50.352066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1954 03:15:50.446987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1955 03:15:50.447696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1957 03:15:50.543020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1958 03:15:50.543785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1960 03:15:50.632368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1961 03:15:50.633105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1963 03:15:50.721635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1964 03:15:50.722343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1966 03:15:50.810475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1967 03:15:50.811192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1969 03:15:50.900516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1970 03:15:50.901215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1972 03:15:50.994284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1973 03:15:50.995019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1975 03:15:51.092030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1976 03:15:51.092751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1978 03:15:51.185727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1979 03:15:51.186442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1981 03:15:51.280580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1982 03:15:51.281290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1984 03:15:51.369291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1985 03:15:51.370015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1987 03:15:51.460368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1988 03:15:51.461070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1990 03:15:51.555141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1991 03:15:51.555914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1993 03:15:51.644106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1994 03:15:51.644812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1996 03:15:51.733423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1997 03:15:51.734214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1999 03:15:51.827864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2000 03:15:51.828630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2002 03:15:51.916855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2003 03:15:51.917557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2005 03:15:52.011456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2006 03:15:52.012169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2008 03:15:52.100475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2009 03:15:52.101194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2011 03:15:52.190077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2012 03:15:52.190774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2014 03:15:52.286136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2015 03:15:52.286854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2017 03:15:52.374544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2018 03:15:52.375265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2020 03:15:52.468441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2021 03:15:52.469151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2023 03:15:52.557106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2025 03:15:52.559322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2026 03:15:52.647121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2028 03:15:52.650311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2029 03:15:52.742102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2031 03:15:52.745200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2032 03:15:52.832212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2033 03:15:52.832912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2035 03:15:52.922735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2036 03:15:52.923440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2038 03:15:53.013413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2039 03:15:53.014177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2041 03:15:53.110158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2042 03:15:53.110919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2044 03:15:53.202229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2045 03:15:53.202956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2047 03:15:53.297173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2048 03:15:53.297886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2050 03:15:53.386911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2051 03:15:53.387625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2053 03:15:53.476685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2054 03:15:53.477438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2056 03:15:53.572207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2057 03:15:53.572952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2059 03:15:53.667312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2060 03:15:53.668060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2062 03:15:53.756165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2063 03:15:53.756873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2065 03:15:53.846137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2066 03:15:53.846843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2068 03:15:53.940998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2069 03:15:53.941707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2071 03:15:54.029657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2072 03:15:54.030361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2074 03:15:54.127512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2075 03:15:54.128257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2077 03:15:54.218305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2078 03:15:54.219009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2080 03:15:54.306184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2081 03:15:54.306894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2083 03:15:54.401424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2084 03:15:54.402196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2086 03:15:54.497097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2087 03:15:54.497834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2089 03:15:54.586521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2090 03:15:54.587284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2092 03:15:54.674162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2093 03:15:54.674876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2095 03:15:54.765816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2096 03:15:54.766517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2098 03:15:54.862665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2099 03:15:54.863363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2101 03:15:54.956611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2102 03:15:54.957315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2104 03:15:55.046337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2105 03:15:55.047061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2107 03:15:55.150845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2108 03:15:55.151554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2110 03:15:55.231598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2111 03:15:55.232338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2113 03:15:55.327900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2114 03:15:55.328673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2116 03:15:55.416746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2117 03:15:55.417452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2119 03:15:55.511766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2120 03:15:55.512552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2122 03:15:55.600683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2123 03:15:55.601428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2125 03:15:55.695674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2126 03:15:55.696427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2128 03:15:55.791886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2129 03:15:55.792673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2131 03:15:55.886309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2132 03:15:55.887018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2134 03:15:55.974758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2135 03:15:55.975454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2137 03:15:56.063868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2138 03:15:56.064621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2140 03:15:56.161677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2141 03:15:56.162383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2143 03:15:56.256521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2144 03:15:56.257220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2146 03:15:56.350718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2147 03:15:56.351419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2149 03:15:56.439583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2150 03:15:56.440331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2152 03:15:56.528211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2153 03:15:56.528950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2155 03:15:56.626448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2156 03:15:56.627188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2158 03:15:56.720832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2159 03:15:56.721540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2161 03:15:56.815966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2162 03:15:56.816706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2164 03:15:56.903893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2165 03:15:56.904624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2167 03:15:56.995070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2168 03:15:56.995767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2170 03:15:57.089635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2171 03:15:57.090336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2173 03:15:57.178796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2174 03:15:57.179500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2176 03:15:57.273128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2177 03:15:57.273825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2179 03:15:57.363496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2180 03:15:57.364203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2182 03:15:57.459056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2183 03:15:57.459756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2185 03:15:57.553330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2186 03:15:57.554087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2188 03:15:57.645137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2189 03:15:57.645865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2191 03:15:57.736144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2192 03:15:57.736845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2194 03:15:57.825552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2195 03:15:57.826247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2197 03:15:57.924626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2198 03:15:57.925337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2200 03:15:58.019611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2201 03:15:58.020359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2203 03:15:58.107525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2204 03:15:58.108260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2206 03:15:58.199187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2207 03:15:58.199891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2209 03:15:58.292579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2210 03:15:58.293285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2212 03:15:58.389839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2213 03:15:58.390549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2215 03:15:58.477644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2216 03:15:58.478340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2218 03:15:58.568575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2219 03:15:58.569330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2221 03:15:58.660346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2222 03:15:58.661163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2224 03:15:58.755300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2225 03:15:58.756066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2227 03:15:58.844985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2228 03:15:58.845695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2230 03:15:58.934290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2231 03:15:58.934993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2233 03:15:59.028766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2234 03:15:59.029478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2236 03:15:59.118454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2237 03:15:59.119167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2239 03:15:59.206745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2240 03:15:59.207446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2242 03:15:59.302512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2243 03:15:59.303217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2245 03:15:59.395701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2246 03:15:59.396449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2248 03:15:59.492354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2249 03:15:59.493123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2251 03:15:59.586538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2252 03:15:59.587263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2254 03:15:59.676244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2255 03:15:59.676992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2257 03:15:59.763297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2258 03:15:59.764034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2260 03:15:59.858867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2261 03:15:59.859575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2263 03:15:59.948892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2264 03:15:59.949597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2266 03:16:00.035180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2267 03:16:00.035889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2269 03:16:00.132072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2270 03:16:00.132775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2272 03:16:00.228675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2273 03:16:00.229376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2275 03:16:00.323813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2276 03:16:00.324567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2278 03:16:00.417865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2279 03:16:00.418569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2281 03:16:00.506639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2282 03:16:00.507386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2284 03:16:00.595793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2285 03:16:00.596564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2287 03:16:00.691590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2288 03:16:00.692343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2290 03:16:00.776337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2291 03:16:00.777126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2293 03:16:00.866319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2294 03:16:00.867058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2296 03:16:00.962032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2297 03:16:00.962738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2299 03:16:01.060768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2300 03:16:01.061475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2302 03:16:01.157921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2303 03:16:01.158798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2305 03:16:01.259576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2306 03:16:01.260365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2308 03:16:01.357229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2309 03:16:01.357946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2311 03:16:01.453005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2312 03:16:01.453714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2314 03:16:01.544330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2315 03:16:01.545064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2317 03:16:01.637806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2318 03:16:01.638569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2320 03:16:01.733067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2321 03:16:01.733765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2323 03:16:01.828248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2324 03:16:01.828946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2326 03:16:01.912730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2327 03:16:01.913421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2329 03:16:02.003067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2330 03:16:02.003764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2332 03:16:02.098918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2333 03:16:02.099606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2335 03:16:02.197802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2336 03:16:02.198493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2338 03:16:02.291555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2339 03:16:02.292290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2341 03:16:02.387664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2342 03:16:02.388383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2344 03:16:02.473899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2346 03:16:02.477015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2347 03:16:02.563320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2348 03:16:02.564089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2350 03:16:02.659958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2351 03:16:02.660687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2353 03:16:02.754466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2354 03:16:02.755152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2356 03:16:02.843610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2357 03:16:02.844431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2359 03:16:02.933593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2360 03:16:02.934350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2362 03:16:03.028868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2363 03:16:03.029645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2365 03:16:03.125595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2366 03:16:03.126401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2368 03:16:03.221233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2369 03:16:03.222040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2371 03:16:03.316440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2372 03:16:03.317222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2374 03:16:03.404793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2375 03:16:03.405543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2377 03:16:03.501340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2378 03:16:03.502129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2380 03:16:03.590063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2381 03:16:03.590834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2383 03:16:03.685167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2384 03:16:03.685923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2386 03:16:03.773613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2387 03:16:03.774348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2389 03:16:03.863550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2390 03:16:03.864340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2392 03:16:03.956777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2393 03:16:03.957510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2395 03:16:04.046247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2396 03:16:04.046965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2398 03:16:04.140079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2399 03:16:04.140816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2401 03:16:04.228535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2402 03:16:04.229263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2404 03:16:04.319683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2405 03:16:04.320424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2407 03:16:04.412483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2408 03:16:04.413197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2410 03:16:04.502848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2411 03:16:04.503597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2413 03:16:04.590316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2414 03:16:04.591044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2416 03:16:04.687612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2417 03:16:04.688411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2419 03:16:04.777165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2420 03:16:04.777888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2422 03:16:04.871862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2423 03:16:04.872627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2425 03:16:04.961252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2426 03:16:04.961990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2428 03:16:05.052524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2429 03:16:05.053257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2431 03:16:05.148815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2432 03:16:05.149572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2434 03:16:05.242615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2435 03:16:05.243329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2437 03:16:05.329304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2438 03:16:05.329776 + set +x
2439 03:16:05.330430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2441 03:16:05.338575 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 919674_1.6.2.4.5>
2442 03:16:05.339024 <LAVA_TEST_RUNNER EXIT>
2443 03:16:05.339671 Received signal: <ENDRUN> 1_kselftest-dt 919674_1.6.2.4.5
2444 03:16:05.340140 Ending use of test pattern.
2445 03:16:05.340555 Ending test lava.1_kselftest-dt (919674_1.6.2.4.5), duration 83.11
2447 03:16:05.342058 ok: lava_test_shell seems to have completed
2448 03:16:05.354626 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2449 03:16:05.356532 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2450 03:16:05.357108 end: 3 lava-test-retry (duration 00:01:25) [common]
2451 03:16:05.357664 start: 4 finalize (timeout 00:05:01) [common]
2452 03:16:05.358216 start: 4.1 power-off (timeout 00:00:30) [common]
2453 03:16:05.359202 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2454 03:16:05.395291 >> OK - accepted request
2455 03:16:05.397362 Returned 0 in 0 seconds
2456 03:16:05.498496 end: 4.1 power-off (duration 00:00:00) [common]
2458 03:16:05.500224 start: 4.2 read-feedback (timeout 00:05:01) [common]
2459 03:16:05.501335 Listened to connection for namespace 'common' for up to 1s
2460 03:16:05.502205 Listened to connection for namespace 'common' for up to 1s
2461 03:16:06.352347 Listened to connection for namespace 'common' for up to 1s
2462 03:16:06.501279 Finalising connection for namespace 'common'
2463 03:16:06.502032 Disconnecting from shell: Finalise
2464 03:16:06.504875 / # <3>[ 14
2465 03:16:06.606968 end: 4.2 read-feedback (duration 00:00:01) [common]
2466 03:16:06.607784 end: 4 finalize (duration 00:00:01) [common]
2467 03:16:06.608612 Cleaning after the job
2468 03:16:06.609304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/ramdisk
2469 03:16:06.612151 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/kernel
2470 03:16:06.620258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/dtb
2471 03:16:06.621807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/nfsrootfs
2472 03:16:06.661454 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919674/tftp-deploy-yi3hy7u_/modules
2473 03:16:06.666013 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919674
2474 03:16:09.686665 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919674
2475 03:16:09.687224 Job finished correctly