Boot log: beaglebone-black

    1 02:00:07.765749  lava-dispatcher, installed at version: 2023.08
    2 02:00:07.766131  start: 0 validate
    3 02:00:07.766367  Start time: 2024-11-01 02:00:07.766350+00:00 (UTC)
    4 02:00:07.766636  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 02:00:08.077144  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
    6 02:00:08.230693  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 02:00:08.383832  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 02:00:08.538119  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
    9 02:00:08.699310  validate duration: 0.93
   11 02:00:08.700382  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 02:00:08.700867  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 02:00:08.701311  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 02:00:08.702025  Not decompressing ramdisk as can be used compressed.
   15 02:00:08.702456  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 02:00:08.702790  saving as /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/ramdisk/initrd.cpio.gz
   17 02:00:08.703132  total size: 4775763 (4 MB)
   18 02:00:09.009952  progress   0 % (0 MB)
   19 02:00:09.464904  progress   5 % (0 MB)
   20 02:00:09.615745  progress  10 % (0 MB)
   21 02:00:09.800102  progress  15 % (0 MB)
   22 02:00:09.807933  progress  20 % (0 MB)
   23 02:00:09.939334  progress  25 % (1 MB)
   24 02:00:09.960104  progress  30 % (1 MB)
   25 02:00:09.962921  progress  35 % (1 MB)
   26 02:00:10.068428  progress  40 % (1 MB)
   27 02:00:10.096644  progress  45 % (2 MB)
   28 02:00:10.229086  progress  50 % (2 MB)
   29 02:00:10.367398  progress  55 % (2 MB)
   30 02:00:10.406479  progress  60 % (2 MB)
   31 02:00:10.539373  progress  65 % (2 MB)
   32 02:00:10.676671  progress  70 % (3 MB)
   33 02:00:10.713398  progress  75 % (3 MB)
   34 02:00:10.845531  progress  80 % (3 MB)
   35 02:00:10.975507  progress  85 % (3 MB)
   36 02:00:11.016747  progress  90 % (4 MB)
   37 02:00:11.149905  progress  95 % (4 MB)
   38 02:00:11.277142  progress 100 % (4 MB)
   39 02:00:11.277601  4 MB downloaded in 2.57 s (1.77 MB/s)
   40 02:00:11.277913  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 02:00:11.278382  end: 1.1 download-retry (duration 00:00:03) [common]
   43 02:00:11.278551  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 02:00:11.278715  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 02:00:11.278994  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kernel/zImage
   46 02:00:11.279123  saving as /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/kernel/zImage
   47 02:00:11.279245  total size: 12050944 (11 MB)
   48 02:00:11.279369  No compression specified
   49 02:00:11.434880  progress   0 % (0 MB)
   50 02:00:11.615257  progress   5 % (0 MB)
   51 02:00:12.037933  progress  10 % (1 MB)
   52 02:00:12.350397  progress  15 % (1 MB)
   53 02:00:12.654647  progress  20 % (2 MB)
   54 02:00:12.958127  progress  25 % (2 MB)
   55 02:00:13.264598  progress  30 % (3 MB)
   56 02:00:13.567350  progress  35 % (4 MB)
   57 02:00:13.872349  progress  40 % (4 MB)
   58 02:00:14.172228  progress  45 % (5 MB)
   59 02:00:14.471782  progress  50 % (5 MB)
   60 02:00:14.774639  progress  55 % (6 MB)
   61 02:00:15.075027  progress  60 % (6 MB)
   62 02:00:15.376709  progress  65 % (7 MB)
   63 02:00:15.673234  progress  70 % (8 MB)
   64 02:00:15.964295  progress  75 % (8 MB)
   65 02:00:16.265686  progress  80 % (9 MB)
   66 02:00:16.459474  progress  85 % (9 MB)
   67 02:00:16.756737  progress  90 % (10 MB)
   68 02:00:17.058818  progress  95 % (10 MB)
   69 02:00:17.355430  progress 100 % (11 MB)
   70 02:00:17.356047  11 MB downloaded in 6.08 s (1.89 MB/s)
   71 02:00:17.356377  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 02:00:17.356858  end: 1.2 download-retry (duration 00:00:06) [common]
   74 02:00:17.357033  start: 1.3 download-retry (timeout 00:09:51) [common]
   75 02:00:17.357199  start: 1.3.1 http-download (timeout 00:09:51) [common]
   76 02:00:17.357502  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
   77 02:00:17.357637  saving as /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/dtb/am335x-boneblack.dtb
   78 02:00:17.357759  total size: 70568 (0 MB)
   79 02:00:17.357881  No compression specified
   80 02:00:17.512826  progress  46 % (0 MB)
   81 02:00:17.515657  progress  92 % (0 MB)
   82 02:00:17.516178  progress 100 % (0 MB)
   83 02:00:17.516414  0 MB downloaded in 0.16 s (0.42 MB/s)
   84 02:00:17.516721  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 02:00:17.517191  end: 1.3 download-retry (duration 00:00:00) [common]
   87 02:00:17.517356  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 02:00:17.517518  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 02:00:17.517775  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 02:00:17.517902  saving as /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/nfsrootfs/full.rootfs.tar
   91 02:00:17.518023  total size: 117747780 (112 MB)
   92 02:00:17.518148  Using unxz to decompress xz
   93 02:00:17.674131  progress   0 % (0 MB)
   94 02:00:21.965794  progress   5 % (5 MB)
   95 02:00:26.693085  progress  10 % (11 MB)
   96 02:00:30.869936  progress  15 % (16 MB)
   97 02:00:33.824481  progress  20 % (22 MB)
   98 02:00:35.668455  progress  25 % (28 MB)
   99 02:00:36.969061  progress  30 % (33 MB)
  100 02:00:37.973300  progress  35 % (39 MB)
  101 02:00:38.827725  progress  40 % (44 MB)
  102 02:00:39.703264  progress  45 % (50 MB)
  103 02:00:40.471784  progress  50 % (56 MB)
  104 02:00:41.287549  progress  55 % (61 MB)
  105 02:00:42.062780  progress  60 % (67 MB)
  106 02:00:42.809981  progress  65 % (73 MB)
  107 02:00:43.773404  progress  70 % (78 MB)
  108 02:00:44.726605  progress  75 % (84 MB)
  109 02:00:45.628832  progress  80 % (89 MB)
  110 02:00:46.510752  progress  85 % (95 MB)
  111 02:00:47.495644  progress  90 % (101 MB)
  112 02:00:48.550897  progress  95 % (106 MB)
  113 02:00:49.656939  progress 100 % (112 MB)
  114 02:00:49.662983  112 MB downloaded in 32.14 s (3.49 MB/s)
  115 02:00:49.664980  end: 1.4.1 http-download (duration 00:00:32) [common]
  117 02:00:49.666464  end: 1.4 download-retry (duration 00:00:32) [common]
  118 02:00:49.666898  start: 1.5 download-retry (timeout 00:09:19) [common]
  119 02:00:49.667347  start: 1.5.1 http-download (timeout 00:09:19) [common]
  120 02:00:49.668289  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/modules.tar.xz
  121 02:00:49.668608  saving as /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/modules/modules.tar
  122 02:00:49.668909  total size: 6909472 (6 MB)
  123 02:00:49.669091  Using unxz to decompress xz
  124 02:00:49.830466  progress   0 % (0 MB)
  125 02:00:50.008690  progress   5 % (0 MB)
  126 02:00:50.051781  progress  10 % (0 MB)
  127 02:00:50.143674  progress  15 % (1 MB)
  128 02:00:50.176008  progress  20 % (1 MB)
  129 02:00:50.204680  progress  25 % (1 MB)
  130 02:00:50.298905  progress  30 % (2 MB)
  131 02:00:50.335286  progress  35 % (2 MB)
  132 02:00:50.458155  progress  40 % (2 MB)
  133 02:00:50.498492  progress  45 % (2 MB)
  134 02:00:50.618635  progress  50 % (3 MB)
  135 02:00:50.738582  progress  55 % (3 MB)
  136 02:00:50.779931  progress  60 % (3 MB)
  137 02:00:50.903691  progress  65 % (4 MB)
  138 02:00:50.940181  progress  70 % (4 MB)
  139 02:00:51.060410  progress  75 % (4 MB)
  140 02:00:51.099504  progress  80 % (5 MB)
  141 02:00:51.216821  progress  85 % (5 MB)
  142 02:00:51.256774  progress  90 % (5 MB)
  143 02:00:51.374929  progress  95 % (6 MB)
  144 02:00:51.413132  progress 100 % (6 MB)
  145 02:00:51.420145  6 MB downloaded in 1.75 s (3.76 MB/s)
  146 02:00:51.420677  end: 1.5.1 http-download (duration 00:00:02) [common]
  148 02:00:51.421593  end: 1.5 download-retry (duration 00:00:02) [common]
  149 02:00:51.422101  start: 1.6 prepare-tftp-overlay (timeout 00:09:17) [common]
  150 02:00:51.422637  start: 1.6.1 extract-nfsrootfs (timeout 00:09:17) [common]
  151 02:00:58.901861  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz
  152 02:00:58.902158  end: 1.6.1 extract-nfsrootfs (duration 00:00:07) [common]
  153 02:00:58.902310  start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
  154 02:00:58.902625  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_
  155 02:00:58.902867  makedir: /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin
  156 02:00:58.903039  makedir: /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/tests
  157 02:00:58.903209  makedir: /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/results
  158 02:00:58.903372  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-add-keys
  159 02:00:58.903620  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-add-sources
  160 02:00:58.903841  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-background-process-start
  161 02:00:58.904064  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-background-process-stop
  162 02:00:58.904302  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-common-functions
  163 02:00:58.904524  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-echo-ipv4
  164 02:00:58.904743  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-install-packages
  165 02:00:58.905090  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-installed-packages
  166 02:00:58.905301  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-os-build
  167 02:00:58.905520  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-probe-channel
  168 02:00:58.905738  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-probe-ip
  169 02:00:58.905968  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-target-ip
  170 02:00:58.906181  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-target-mac
  171 02:00:58.906394  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-target-storage
  172 02:00:58.906608  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-case
  173 02:00:58.906825  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-event
  174 02:00:58.907033  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-feedback
  175 02:00:58.907241  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-raise
  176 02:00:58.907456  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-reference
  177 02:00:58.907667  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-runner
  178 02:00:58.907875  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-set
  179 02:00:58.908086  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-test-shell
  180 02:00:58.908303  Updating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-add-keys (debian)
  181 02:00:58.908587  Updating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-add-sources (debian)
  182 02:00:58.908881  Updating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-install-packages (debian)
  183 02:00:58.909141  Updating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-installed-packages (debian)
  184 02:00:58.909379  Updating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/bin/lava-os-build (debian)
  185 02:00:58.909586  Creating /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/environment
  186 02:00:58.909747  LAVA metadata
  187 02:00:58.909860  - LAVA_JOB_ID=1214616
  188 02:00:58.909971  - LAVA_DISPATCHER_IP=172.16.3.3
  189 02:00:58.910134  start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
  190 02:00:58.910574  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 02:00:58.910726  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
  192 02:00:58.910831  skipped lava-vland-overlay
  193 02:00:58.910955  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 02:00:58.911088  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
  195 02:00:58.911201  skipped lava-multinode-overlay
  196 02:00:58.911325  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 02:00:58.911452  start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
  198 02:00:58.911565  Loading test definitions
  199 02:00:58.911702  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
  200 02:00:58.911812  Using /lava-1214616 at stage 0
  201 02:00:58.912374  uuid=1214616_1.6.2.4.1 testdef=None
  202 02:00:58.912520  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 02:00:58.912654  start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
  204 02:00:58.913477  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 02:00:58.913858  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
  207 02:00:58.914770  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 02:00:58.915148  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
  210 02:00:58.931563  runner path: /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/0/tests/0_timesync-off test_uuid 1214616_1.6.2.4.1
  211 02:00:58.931834  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 02:00:58.932284  start: 1.6.2.4.5 git-repo-action (timeout 00:09:10) [common]
  214 02:00:58.932407  Using /lava-1214616 at stage 0
  215 02:00:58.932604  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 02:00:58.932724  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/0/tests/1_kselftest-dt'
  217 02:01:04.729024  Running '/usr/bin/git checkout kernelci.org
  218 02:01:05.058366  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 02:01:05.059401  uuid=1214616_1.6.2.4.5 testdef=None
  220 02:01:05.059728  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 02:01:05.060198  start: 1.6.2.4.6 test-overlay (timeout 00:09:04) [common]
  223 02:01:05.062598  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 02:01:05.063165  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:04) [common]
  226 02:01:05.066091  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 02:01:05.066658  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:04) [common]
  229 02:01:05.072010  runner path: /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/0/tests/1_kselftest-dt test_uuid 1214616_1.6.2.4.5
  230 02:01:05.072269  BOARD='beaglebone-black'
  231 02:01:05.072452  BRANCH='mainline'
  232 02:01:05.072664  SKIPFILE='/dev/null'
  233 02:01:05.072822  SKIP_INSTALL='True'
  234 02:01:05.072943  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
  235 02:01:05.073065  TST_CASENAME=''
  236 02:01:05.073182  TST_CMDFILES='dt'
  237 02:01:05.073471  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 02:01:05.073870  Creating lava-test-runner.conf files
  240 02:01:05.073991  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1214616/lava-overlay-kd6k5qj_/lava-1214616/0 for stage 0
  241 02:01:05.074171  - 0_timesync-off
  242 02:01:05.074301  - 1_kselftest-dt
  243 02:01:05.074528  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 02:01:05.074798  start: 1.6.2.5 compress-overlay (timeout 00:09:04) [common]
  245 02:01:14.826228  end: 1.6.2.5 compress-overlay (duration 00:00:10) [common]
  246 02:01:14.826473  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:54) [common]
  247 02:01:14.826618  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 02:01:14.826766  end: 1.6.2 lava-overlay (duration 00:00:16) [common]
  249 02:01:14.826913  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:54) [common]
  250 02:01:14.965809  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 02:01:14.966075  start: 1.6.4 extract-modules (timeout 00:08:54) [common]
  252 02:01:14.966204  extracting modules file /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz
  253 02:01:15.358370  extracting modules file /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214616/extract-overlay-ramdisk-blt10cpw/ramdisk
  254 02:01:15.750413  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 02:01:15.750682  start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
  256 02:01:15.750811  [common] Applying overlay to NFS
  257 02:01:15.750919  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1214616/compress-overlay-3vxmh2lc/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz
  258 02:01:17.140991  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  259 02:01:17.141280  start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
  260 02:01:17.141450  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
  261 02:01:17.141619  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 02:01:17.141760  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 02:01:17.141925  start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
  264 02:01:17.142066  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 02:01:17.142225  start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
  266 02:01:17.142375  Building ramdisk /var/lib/lava/dispatcher/tmp/1214616/extract-overlay-ramdisk-blt10cpw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1214616/extract-overlay-ramdisk-blt10cpw/ramdisk
  267 02:01:17.448238  >> 79010 blocks

  268 02:01:19.863065  Adding RAMdisk u-boot header.
  269 02:01:19.863522  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1214616/extract-overlay-ramdisk-blt10cpw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1214616/extract-overlay-ramdisk-blt10cpw/ramdisk.cpio.gz.uboot
  270 02:01:20.167975  output: Image Name:   
  271 02:01:20.168453  output: Created:      Fri Nov  1 02:01:19 2024
  272 02:01:20.168771  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 02:01:20.168962  output: Data Size:    15357776 Bytes = 14997.83 KiB = 14.65 MiB
  274 02:01:20.169168  output: Load Address: 00000000
  275 02:01:20.169453  output: Entry Point:  00000000
  276 02:01:20.169740  output: 
  277 02:01:20.170245  rename /var/lib/lava/dispatcher/tmp/1214616/extract-overlay-ramdisk-blt10cpw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot
  278 02:01:20.170755  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 02:01:20.171172  end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
  280 02:01:20.171585  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
  281 02:01:20.171904  No LXC device requested
  282 02:01:20.172282  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 02:01:20.172678  start: 1.8 deploy-device-env (timeout 00:08:49) [common]
  284 02:01:20.172950  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 02:01:20.173165  Checking files for TFTP limit of 4294967296 bytes.
  286 02:01:20.175103  end: 1 tftp-deploy (duration 00:01:11) [common]
  287 02:01:20.175529  start: 2 uboot-action (timeout 00:05:00) [common]
  288 02:01:20.175933  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 02:01:20.176309  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 02:01:20.176690  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 02:01:20.177109  substitutions:
  292 02:01:20.177418  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 02:01:20.177715  - {DTB_ADDR}: 0x88000000
  294 02:01:20.178003  - {DTB}: 1214616/tftp-deploy-0fzdm02b/dtb/am335x-boneblack.dtb
  295 02:01:20.178291  - {INITRD}: 1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot
  296 02:01:20.178577  - {KERNEL_ADDR}: 0x82000000
  297 02:01:20.178862  - {KERNEL}: 1214616/tftp-deploy-0fzdm02b/kernel/zImage
  298 02:01:20.179142  - {LAVA_MAC}: None
  299 02:01:20.179440  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz
  300 02:01:20.179727  - {NFS_SERVER_IP}: 172.16.3.3
  301 02:01:20.180006  - {PRESEED_CONFIG}: None
  302 02:01:20.180283  - {PRESEED_LOCAL}: None
  303 02:01:20.180559  - {RAMDISK_ADDR}: 0x83000000
  304 02:01:20.180846  - {RAMDISK}: 1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot
  305 02:01:20.180971  - {ROOT_PART}: None
  306 02:01:20.181192  - {ROOT}: None
  307 02:01:20.181464  - {SERVER_IP}: 172.16.3.3
  308 02:01:20.181734  - {TEE_ADDR}: 0x83000000
  309 02:01:20.182006  - {TEE}: None
  310 02:01:20.182278  Parsed boot commands:
  311 02:01:20.182544  - setenv autoload no
  312 02:01:20.182814  - setenv initrd_high 0xffffffff
  313 02:01:20.183083  - setenv fdt_high 0xffffffff
  314 02:01:20.183351  - dhcp
  315 02:01:20.183617  - setenv serverip 172.16.3.3
  316 02:01:20.183886  - tftp 0x82000000 1214616/tftp-deploy-0fzdm02b/kernel/zImage
  317 02:01:20.184159  - tftp 0x83000000 1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot
  318 02:01:20.184432  - setenv initrd_size ${filesize}
  319 02:01:20.184701  - tftp 0x88000000 1214616/tftp-deploy-0fzdm02b/dtb/am335x-boneblack.dtb
  320 02:01:20.184909  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 02:01:20.185058  - bootz 0x82000000 0x83000000 0x88000000
  322 02:01:20.185417  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 02:01:20.186423  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 02:01:20.186719  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 02:01:20.195337  Setting prompt string to ['lava-test: # ']
  327 02:01:20.195902  end: 2.3 connect-device (duration 00:00:00) [common]
  328 02:01:20.196147  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 02:01:20.196371  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 02:01:20.196597  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 02:01:20.196958  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 02:01:20.493291  >> OFF

  333 02:01:35.856866  >> ON

  334 02:01:35.857762  Returned 0 in 15 seconds
  335 02:01:35.958712  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 02:01:35.959868  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 02:01:35.960296  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 02:01:35.960692  Setting prompt string to ['Hit any key to stop autoboot']
  340 02:01:35.960986  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 02:01:35.961796  Trying 192.168.1.205...
  342 02:01:35.962113  Connected to ts5.
  343 02:01:35.962399  Escape character is '^]'.
  344 02:01:35.962683  
  345 02:01:35.962977  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [,115200N81,CLOCAL] (Debian GNU/Linux)
  346 02:01:35.963275  
  347 02:01:37.184987  
  348 02:01:37.192880  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 02:01:37.193266  Trying to boot from MMC2
  350 02:01:37.705988  
  351 02:01:37.706381  
  352 02:01:37.710786  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 02:01:37.711190  
  354 02:01:37.711522  CPU  : AM335X-GP rev 2.1
  355 02:01:37.717510  Model: TI AM335x BeagleBone Black
  356 02:01:37.717918  DRAM:  512 MiB
  357 02:01:37.798506  WDT:   Started with servicing (60s timeout)
  358 02:01:38.204575  NAND:  0 MiB
  359 02:01:38.214511  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 02:01:38.248025  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 02:01:38.277323  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 02:01:38.336013  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 02:01:38.336514  start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
  364 02:01:38.336919  Setting prompt string to ['=> ']
  365 02:01:38.337291  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:42)
  366 02:01:38.345595  Hit any key to stop autoboot:  2   0 
  367 02:01:38.346367  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 02:01:38.346757  Sending with 10 millisecond of delay
  370 02:01:39.482765  => setenv autoload no
  371 02:01:39.493315  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 02:01:39.496373  setenv autoload no
  373 02:01:39.496977  Sending with 10 millisecond of delay
  375 02:01:41.296824  => setenv initrd_high 0xffffffff
  376 02:01:41.307418  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:39)
  377 02:01:41.308032  setenv initrd_high 0xffffffff
  378 02:01:41.308594  Sending with 10 millisecond of delay
  380 02:01:42.927315  => setenv fdt_high 0xffffffff
  381 02:01:42.937924  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
  382 02:01:42.938547  setenv fdt_high 0xffffffff
  383 02:01:42.939112  Sending with 10 millisecond of delay
  385 02:01:43.231020  => dhcp
  386 02:01:43.241557  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
  387 02:01:43.242461  dhcp
  388 02:01:43.242788  link up on port 0, speed 100, full duplex
  389 02:01:43.243088  BOOTP broadcast 1
  390 02:01:43.294987  DHCP client bound to address 172.16.3.190 (46 ms)
  391 02:01:43.295607  Sending with 10 millisecond of delay
  393 02:01:44.914549  => setenv serverip 172.16.3.3
  394 02:01:44.925177  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:35)
  395 02:01:44.925813  setenv serverip 172.16.3.3
  396 02:01:44.926392  Sending with 10 millisecond of delay
  398 02:01:48.474116  => tftp 0x82000000 1214616/tftp-deploy-0fzdm02b/kernel/zImage
  399 02:01:48.484854  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 02:01:48.485553  tftp 0x82000000 1214616/tftp-deploy-0fzdm02b/kernel/zImage
  401 02:01:48.485876  link up on port 0, speed 100, full duplex
  402 02:01:48.490412  Using ethernet@4a100000 device
  403 02:01:48.496407  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  404 02:01:48.504177  Filename '1214616/tftp-deploy-0fzdm02b/kernel/zImage'.
  405 02:01:48.504462  Load address: 0x82000000
  406 02:01:51.542244  Loading: *##################################################  11.5 MiB
  407 02:01:51.542670  	 3.8 MiB/s
  408 02:01:51.542977  done
  409 02:01:51.546535  Bytes transferred = 12050944 (b7e200 hex)
  410 02:01:51.547174  Sending with 10 millisecond of delay
  412 02:01:56.061556  => tftp 0x83000000 1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot
  413 02:01:56.072123  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:24)
  414 02:01:56.072774  tftp 0x83000000 1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot
  415 02:01:56.073129  link up on port 0, speed 100, full duplex
  416 02:01:56.078409  Using ethernet@4a100000 device
  417 02:01:56.083192  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  418 02:01:56.092144  Filename '1214616/tftp-deploy-0fzdm02b/ramdisk/ramdisk.cpio.gz.uboot'.
  419 02:01:56.092481  Load address: 0x83000000
  420 02:02:00.067465  Loading: *##################################################  14.6 MiB
  421 02:02:00.067918  	 3.7 MiB/s
  422 02:02:00.068231  done
  423 02:02:00.071763  Bytes transferred = 15357840 (ea5790 hex)
  424 02:02:00.072418  Sending with 10 millisecond of delay
  426 02:02:01.932079  => setenv initrd_size ${filesize}
  427 02:02:01.942653  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:18)
  428 02:02:01.943280  setenv initrd_size ${filesize}
  429 02:02:01.943843  Sending with 10 millisecond of delay
  431 02:02:06.154019  => tftp 0x88000000 1214616/tftp-deploy-0fzdm02b/dtb/am335x-boneblack.dtb
  432 02:02:06.164693  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:14)
  433 02:02:06.165511  tftp 0x88000000 1214616/tftp-deploy-0fzdm02b/dtb/am335x-boneblack.dtb
  434 02:02:06.165847  link up on port 0, speed 100, full duplex
  435 02:02:06.170538  Using ethernet@4a100000 device
  436 02:02:06.176761  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  437 02:02:06.188779  Filename '1214616/tftp-deploy-0fzdm02b/dtb/am335x-boneblack.dtb'.
  438 02:02:06.188995  Load address: 0x88000000
  439 02:02:06.203740  Loading: *##################################################  68.9 KiB
  440 02:02:06.204122  	 3.2 MiB/s
  441 02:02:06.212885  done
  442 02:02:06.213256  Bytes transferred = 70568 (113a8 hex)
  443 02:02:06.213830  Sending with 10 millisecond of delay
  445 02:02:19.592842  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 02:02:19.603508  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:01)
  447 02:02:19.604145  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 02:02:19.604723  Sending with 10 millisecond of delay
  450 02:02:21.946865  => bootz 0x82000000 0x83000000 0x88000000
  451 02:02:21.957495  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 02:02:21.957956  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:03:58)
  453 02:02:21.958689  bootz 0x82000000 0x83000000 0x88000000
  454 02:02:21.959016  Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
  455 02:02:21.962125  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 02:02:21.967152     Image Name:   
  457 02:02:21.967532     Created:      2024-11-01   2:01:19 UTC
  458 02:02:21.975696     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 02:02:21.976083     Data Size:    15357776 Bytes = 14.6 MiB
  460 02:02:21.983723     Load Address: 00000000
  461 02:02:21.984118     Entry Point:  00000000
  462 02:02:22.158027     Verifying Checksum ... OK
  463 02:02:22.158406  ## Flattened Device Tree blob at 88000000
  464 02:02:22.165440     Booting using the fdt blob at 0x88000000
  465 02:02:22.169912     Using Device Tree in place at 88000000, end 880143a7
  466 02:02:22.184245  
  467 02:02:22.184630  Starting kernel ...
  468 02:02:22.184965  
  469 02:02:22.185656  end: 2.4.3 bootloader-commands (duration 00:00:44) [common]
  470 02:02:22.186077  start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
  471 02:02:22.186437  Setting prompt string to ['Linux version [0-9]']
  472 02:02:22.186793  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 02:02:22.187142  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 02:02:23.072984  [    0.000000] Booting Linux on physical CPU 0x0
  475 02:02:23.079508  start: 2.4.4.1 login-action (timeout 00:03:57) [common]
  476 02:02:23.079930  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 02:02:23.080273  Setting prompt string to []
  478 02:02:23.080623  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 02:02:23.080991  Using line separator: #'\n'#
  480 02:02:23.081289  No login prompt set.
  481 02:02:23.081597  Parsing kernel messages
  482 02:02:23.081875  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 02:02:23.082397  [login-action] Waiting for messages, (timeout 00:03:57)
  484 02:02:23.092579  [    0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j358334-arm-clang-15-multi-v7-defconfig-bm9v7) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Fri Nov  1 00:34:39 UTC 2024
  485 02:02:23.098712  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 02:02:23.104851  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 02:02:23.113459  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 02:02:23.119579  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 02:02:23.125566  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 02:02:23.129042  [    0.000000] Memory policy: Data cache writeback
  491 02:02:23.135440  [    0.000000] efi: UEFI not found.
  492 02:02:23.138608  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 02:02:23.143868  [    0.000000] Zone ranges:
  494 02:02:23.150157  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 02:02:23.156371  [    0.000000]   Normal   empty
  496 02:02:23.156751  [    0.000000]   HighMem  empty
  497 02:02:23.159961  [    0.000000] Movable zone start for each node
  498 02:02:23.163985  [    0.000000] Early memory node ranges
  499 02:02:23.170219  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 02:02:23.178188  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 02:02:23.196582  [    0.000000] CPU: All CPU(s) started in SVC mode.
  502 02:02:23.202204  [    0.000000] AM335X ES2.1 (sgx neon)
  503 02:02:23.214763  [    0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
  504 02:02:23.234729  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  505 02:02:23.240742  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  506 02:02:23.249313  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  507 02:02:23.255624  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  508 02:02:23.264977  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  509 02:02:23.294359  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  510 02:02:23.300464  <6>[    0.000000] trace event string verifier disabled
  511 02:02:23.300879  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  512 02:02:23.307858  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  513 02:02:23.313981  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  514 02:02:23.323604  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  515 02:02:23.330451  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  516 02:02:23.346728  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  517 02:02:23.362984  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  518 02:02:23.370974  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  519 02:02:23.468956  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  520 02:02:23.478688  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  521 02:02:23.491112  <6>[    0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  522 02:02:23.499846  <6>[    0.019184] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  523 02:02:23.508107  <6>[    0.034218] Console: colour dummy device 80x30
  524 02:02:23.514715  Matched prompt #6: WARNING:
  525 02:02:23.515112  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  526 02:02:23.520434  <3>[    0.039120] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  527 02:02:23.522681  <3>[    0.046201] This ensures that you still see kernel messages. Please
  528 02:02:23.529656  <3>[    0.052932] update your kernel commandline.
  529 02:02:23.569644  <6>[    0.057544] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  530 02:02:23.575860  <6>[    0.096189] CPU: Testing write buffer coherency: ok
  531 02:02:23.578178  <6>[    0.101556] CPU0: Spectre v2: using BPIALL workaround
  532 02:02:23.583379  <6>[    0.107023] pid_max: default: 32768 minimum: 301
  533 02:02:23.589415  <6>[    0.112220] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  534 02:02:23.599406  <6>[    0.120045] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  535 02:02:23.607000  <6>[    0.129499] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  536 02:02:23.620501  <6>[    0.136448] Setting up static identity map for 0x80300000 - 0x803000ac
  537 02:02:23.620910  <6>[    0.146156] rcu: Hierarchical SRCU implementation.
  538 02:02:23.628693  <6>[    0.151441] rcu: 	Max phase no-delay instances is 1000.
  539 02:02:23.637306  <6>[    0.162775] EFI services will not be available.
  540 02:02:23.643562  <6>[    0.168066] smp: Bringing up secondary CPUs ...
  541 02:02:23.649858  <6>[    0.173123] smp: Brought up 1 node, 1 CPU
  542 02:02:23.657172  <6>[    0.177523] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  543 02:02:23.663268  <6>[    0.184296] CPU: All CPU(s) started in SVC mode.
  544 02:02:23.681405  <6>[    0.189511] Memory: 404424K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50624K reserved, 65536K cma-reserved, 0K highmem)
  545 02:02:23.681805  <6>[    0.205802] devtmpfs: initialized
  546 02:02:23.704503  <6>[    0.223681] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  547 02:02:23.713018  <6>[    0.232303] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  548 02:02:23.721295  <6>[    0.242772] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  549 02:02:23.732719  <6>[    0.255088] pinctrl core: initialized pinctrl subsystem
  550 02:02:23.742671  <6>[    0.265950] DMI not present or invalid.
  551 02:02:23.751082  <6>[    0.271849] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  552 02:02:23.760349  <6>[    0.280851] DMA: preallocated 256 KiB pool for atomic coherent allocations
  553 02:02:23.775617  <6>[    0.292516] thermal_sys: Registered thermal governor 'step_wise'
  554 02:02:23.776007  <6>[    0.292686] cpuidle: using governor menu
  555 02:02:23.802736  <6>[    0.328145] No ATAGs?
  556 02:02:23.807464  <6>[    0.330886] hw-breakpoint: debug architecture 0x4 unsupported.
  557 02:02:23.818711  <6>[    0.343060] Serial: AMBA PL011 UART driver
  558 02:02:23.850347  <6>[    0.375735] iommu: Default domain type: Translated
  559 02:02:23.859427  <6>[    0.381090] iommu: DMA domain TLB invalidation policy: strict mode
  560 02:02:23.885043  <5>[    0.410524] SCSI subsystem initialized
  561 02:02:23.891213  <6>[    0.415459] usbcore: registered new interface driver usbfs
  562 02:02:23.897505  <6>[    0.421521] usbcore: registered new interface driver hub
  563 02:02:23.903886  <6>[    0.427318] usbcore: registered new device driver usb
  564 02:02:23.910057  <6>[    0.433887] pps_core: LinuxPPS API ver. 1 registered
  565 02:02:23.920811  <6>[    0.439277] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  566 02:02:23.927926  <6>[    0.449005] PTP clock support registered
  567 02:02:23.928307  <6>[    0.453474] EDAC MC: Ver: 3.0.0
  568 02:02:23.987533  <6>[    0.509398] scmi_core: SCMI protocol bus registered
  569 02:02:23.992044  <6>[    0.517634] vgaarb: loaded
  570 02:02:24.004727  <6>[    0.530410] clocksource: Switched to clocksource dmtimer
  571 02:02:24.043650  <6>[    0.569143] NET: Registered PF_INET protocol family
  572 02:02:24.056393  <6>[    0.574860] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  573 02:02:24.063763  <6>[    0.583857] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  574 02:02:24.076099  <6>[    0.592787] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  575 02:02:24.079680  <6>[    0.601054] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  576 02:02:24.089940  <6>[    0.609322] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  577 02:02:24.096093  <6>[    0.617047] TCP: Hash tables configured (established 4096 bind 4096)
  578 02:02:24.100928  <6>[    0.623963] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  579 02:02:24.112096  <6>[    0.631004] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  580 02:02:24.116387  <6>[    0.638587] NET: Registered PF_UNIX/PF_LOCAL protocol family
  581 02:02:24.198705  <6>[    0.717935] RPC: Registered named UNIX socket transport module.
  582 02:02:24.199092  <6>[    0.724387] RPC: Registered udp transport module.
  583 02:02:24.203554  <6>[    0.729497] RPC: Registered tcp transport module.
  584 02:02:24.212123  <6>[    0.734619] RPC: Registered tcp-with-tls transport module.
  585 02:02:24.218363  <6>[    0.740544] RPC: Registered tcp NFSv4.1 backchannel transport module.
  586 02:02:24.225597  <6>[    0.747455] PCI: CLS 0 bytes, default 64
  587 02:02:24.227953  <5>[    0.753347] Initialise system trusted keyrings
  588 02:02:24.251218  <6>[    0.774431] Trying to unpack rootfs image as initramfs...
  589 02:02:24.321771  <6>[    0.840831] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  590 02:02:24.326094  <6>[    0.848349] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  591 02:02:24.366080  <5>[    0.891739] NFS: Registering the id_resolver key type
  592 02:02:24.372377  <5>[    0.897329] Key type id_resolver registered
  593 02:02:24.377268  <5>[    0.902018] Key type id_legacy registered
  594 02:02:24.385877  <6>[    0.906461] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  595 02:02:24.393875  <6>[    0.913671] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  596 02:02:24.475157  <5>[    1.001553] Key type asymmetric registered
  597 02:02:24.481275  <5>[    1.006082] Asymmetric key parser 'x509' registered
  598 02:02:24.490933  <6>[    1.011589] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  599 02:02:24.496035  <6>[    1.019479] io scheduler mq-deadline registered
  600 02:02:24.502012  <6>[    1.024467] io scheduler kyber registered
  601 02:02:24.505258  <6>[    1.028920] io scheduler bfq registered
  602 02:02:24.610919  <6>[    1.132875] ledtrig-cpu: registered to indicate activity on CPUs
  603 02:02:24.907391  <6>[    1.428717] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  604 02:02:24.940259  <6>[    1.465494] msm_serial: driver initialized
  605 02:02:24.946403  <6>[    1.470283] SuperH (H)SCI(F) driver initialized
  606 02:02:24.952669  <6>[    1.475642] STMicroelectronics ASC driver initialized
  607 02:02:24.958331  <6>[    1.481331] STM32 USART driver initialized
  608 02:02:25.117169  <6>[    1.641837] brd: module loaded
  609 02:02:25.140137  <6>[    1.664290] loop: module loaded
  610 02:02:25.195237  <6>[    1.719927] CAN device driver interface
  611 02:02:25.201649  <6>[    1.725148] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  612 02:02:25.207781  <6>[    1.732193] e1000e: Intel(R) PRO/1000 Network Driver
  613 02:02:25.213869  <6>[    1.737576] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  614 02:02:25.218911  <6>[    1.744051] igb: Intel(R) Gigabit Ethernet Network Driver
  615 02:02:25.228450  <6>[    1.749876] igb: Copyright (c) 2007-2014 Intel Corporation.
  616 02:02:25.234771  <6>[    1.759118] pegasus: Pegasus/Pegasus II USB Ethernet driver
  617 02:02:25.245840  <6>[    1.765299] usbcore: registered new interface driver pegasus
  618 02:02:25.251976  <6>[    1.771460] usbcore: registered new interface driver asix
  619 02:02:25.258228  <6>[    1.777318] usbcore: registered new interface driver ax88179_178a
  620 02:02:25.262936  <6>[    1.783908] usbcore: registered new interface driver cdc_ether
  621 02:02:25.269115  <6>[    1.790208] usbcore: registered new interface driver smsc75xx
  622 02:02:25.274128  <6>[    1.796472] usbcore: registered new interface driver smsc95xx
  623 02:02:25.280339  <6>[    1.802713] usbcore: registered new interface driver net1080
  624 02:02:25.286691  <6>[    1.808834] usbcore: registered new interface driver cdc_subset
  625 02:02:25.291586  <6>[    1.815248] usbcore: registered new interface driver zaurus
  626 02:02:25.298408  <6>[    1.821312] usbcore: registered new interface driver cdc_ncm
  627 02:02:25.309192  <6>[    1.830993] usbcore: registered new interface driver usb-storage
  628 02:02:25.588564  <6>[    2.111945] i2c_dev: i2c /dev entries driver
  629 02:02:25.639406  <5>[    2.157085] cpuidle: enable-method property 'ti,am3352' found operations
  630 02:02:25.645483  <6>[    2.166810] sdhci: Secure Digital Host Controller Interface driver
  631 02:02:25.651892  <6>[    2.173587] sdhci: Copyright(c) Pierre Ossman
  632 02:02:25.659252  <6>[    2.180085] Synopsys Designware Multimedia Card Interface Driver
  633 02:02:25.666011  <6>[    2.188160] sdhci-pltfm: SDHCI platform and OF driver helper
  634 02:02:25.795653  <6>[    2.313330] usbcore: registered new interface driver usbhid
  635 02:02:25.796058  <6>[    2.319373] usbhid: USB HID core driver
  636 02:02:25.854796  <6>[    2.377685] NET: Registered PF_INET6 protocol family
  637 02:02:25.895821  <6>[    2.421681] Segment Routing with IPv6
  638 02:02:25.900753  <6>[    2.425832] In-situ OAM (IOAM) with IPv6
  639 02:02:25.908542  <6>[    2.430235] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  640 02:02:25.916022  <6>[    2.437626] NET: Registered PF_PACKET protocol family
  641 02:02:25.922093  <6>[    2.443246] can: controller area network core
  642 02:02:25.927066  <6>[    2.448080] NET: Registered PF_CAN protocol family
  643 02:02:25.927452  <6>[    2.453322] can: raw protocol
  644 02:02:25.931815  <6>[    2.456651] can: broadcast manager protocol
  645 02:02:25.938043  <6>[    2.461255] can: netlink gateway - max_hops=1
  646 02:02:25.943111  <5>[    2.466790] Key type dns_resolver registered
  647 02:02:25.949285  <6>[    2.471873] ThumbEE CPU extension supported.
  648 02:02:25.952931  <5>[    2.476561] Registering SWP/SWPB emulation handler
  649 02:02:25.960008  <3>[    2.482258] omap_voltage_late_init: Voltage driver support not added
  650 02:02:26.144610  <5>[    2.667937] Loading compiled-in X.509 certificates
  651 02:02:26.287201  <6>[    2.799926] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  652 02:02:26.295133  <6>[    2.816656] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  653 02:02:26.322114  <3>[    2.841118] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  654 02:02:26.512912  <3>[    3.032480] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  655 02:02:26.716461  <6>[    3.240811] OMAP GPIO hardware version 0.1
  656 02:02:26.737820  <6>[    3.259834] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  657 02:02:26.821370  <4>[    3.342726] at24 2-0054: supply vcc not found, using dummy regulator
  658 02:02:26.853180  <4>[    3.374144] at24 2-0055: supply vcc not found, using dummy regulator
  659 02:02:26.892436  <4>[    3.414013] at24 2-0056: supply vcc not found, using dummy regulator
  660 02:02:26.934781  <4>[    3.455816] at24 2-0057: supply vcc not found, using dummy regulator
  661 02:02:26.972945  <6>[    3.494973] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  662 02:02:27.028343  <3>[    3.547155] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  663 02:02:27.053818  <6>[    3.568451] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  664 02:02:27.075394  <4>[    3.595463] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  665 02:02:27.090526  <4>[    3.611102] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  666 02:02:27.156065  <6>[    3.681395] Freeing initrd memory: 15000K
  667 02:02:27.165288  <6>[    3.686996] omap_rng 48310000.rng: Random Number Generator ver. 20
  668 02:02:27.189324  <5>[    3.713934] random: crng init done
  669 02:02:27.240144  <6>[    3.760412] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  670 02:02:27.294186  <6>[    3.812875] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  671 02:02:27.299181  <6>[    3.823192] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  672 02:02:27.307816  <6>[    3.830532] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  673 02:02:27.318748  <6>[    3.837999] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  674 02:02:27.327323  <6>[    3.846136] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  675 02:02:27.341085  <6>[    3.857780] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  676 02:02:27.349131  <5>[    3.866904] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  677 02:02:27.377534  <3>[    3.897381] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  678 02:02:27.383210  <6>[    3.905983] edma 49000000.dma: TI EDMA DMA engine driver
  679 02:02:27.456678  <3>[    3.975352] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  680 02:02:27.470195  <6>[    3.989853] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  681 02:02:27.484836  <3>[    4.007147] l3-aon-clkctrl:0000:0: failed to disable
  682 02:02:27.539811  <6>[    4.059287] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  683 02:02:27.545936  <6>[    4.068809] printk: legacy console [ttyS0] enabled
  684 02:02:27.548239  <6>[    4.068809] printk: legacy console [ttyS0] enabled
  685 02:02:27.553321  <6>[    4.079145] printk: legacy bootconsole [omap8250] disabled
  686 02:02:27.559314  <6>[    4.079145] printk: legacy bootconsole [omap8250] disabled
  687 02:02:27.592118  <4>[    4.111345] tps65217-pmic: Failed to locate of_node [id: -1]
  688 02:02:27.596484  <4>[    4.118756] tps65217-bl: Failed to locate of_node [id: -1]
  689 02:02:27.612324  <6>[    4.138814] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  690 02:02:27.628437  <6>[    4.145832] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  691 02:02:27.646087  <6>[    4.159535] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  692 02:02:27.649296  <6>[    4.171431] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  693 02:02:27.671037  <6>[    4.191982] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  694 02:02:27.677179  <6>[    4.201175] sdhci-omap 48060000.mmc: Got CD GPIO
  695 02:02:27.685198  <4>[    4.206319] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  696 02:02:27.700046  <4>[    4.219876] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  697 02:02:27.706218  <4>[    4.228675] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  698 02:02:27.717047  <4>[    4.237354] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  699 02:02:27.792157  <6>[    4.312464] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  700 02:02:27.823104  <6>[    4.344050] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  701 02:02:27.871825  <6>[    4.390611] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  702 02:02:27.877279  <6>[    4.399442] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  703 02:02:27.945903  <6>[    4.460925] mmc1: new high speed MMC card at address 0001
  704 02:02:27.946286  <6>[    4.469023] mmcblk1: mmc1:0001 M62704 3.56 GiB
  705 02:02:27.956669  <6>[    4.481071]  mmcblk1: p1
  706 02:02:27.969793  <6>[    4.485450] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  707 02:02:27.974270  <6>[    4.498183] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  708 02:02:27.986917  <6>[    4.509628] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  709 02:02:28.000846  <6>[    4.522838] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  710 02:02:30.071745  <6>[    6.591479] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  711 02:02:30.194238  <5>[    6.620439] Sending DHCP requests ., OK
  712 02:02:30.206702  <6>[    6.724881] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.190
  713 02:02:30.207083  <6>[    6.732961] IP-Config: Complete:
  714 02:02:30.220214  <6>[    6.736499]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.190, mask=255.255.255.0, gw=172.16.3.3
  715 02:02:30.226292  <6>[    6.746943]      host=172.16.3.190, domain=denx.de, nis-domain=(none)
  716 02:02:30.234984  <6>[    6.753769]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  717 02:02:30.235361  <6>[    6.753805]      nameserver0=172.16.3.3
  718 02:02:30.241139  <6>[    6.765111]      ntpserver0=172.16.3.3
  719 02:02:30.247214  <6>[    6.770620] clk: Disabling unused clocks
  720 02:02:30.250593  <6>[    6.775239] PM: genpd: Disabling unused power domains
  721 02:02:30.269653  <6>[    6.791649] Freeing unused kernel image (initmem) memory: 2048K
  722 02:02:30.276745  <6>[    6.801591] Run /init as init process
  723 02:02:30.301716  Loading, please wait...
  724 02:02:30.379680  Starting systemd-udevd version 252.22-1~deb12u1
  725 02:02:33.386461  <4>[    9.905625] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  726 02:02:33.576067  <4>[   10.095322] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  727 02:02:33.715560  <6>[   10.241886] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  728 02:02:33.726117  <6>[   10.247560] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  729 02:02:34.018251  <6>[   10.543138] hub 1-0:1.0: USB hub found
  730 02:02:34.049709  <6>[   10.573717] hub 1-0:1.0: 1 port detected
  731 02:02:34.219537  <6>[   10.744409] tda998x 0-0070: found TDA19988
  732 02:02:36.899171  Begin: Loading essential drivers ... done.
  733 02:02:36.905393  Begin: Running /scripts/init-premount ... done.
  734 02:02:36.911405  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  735 02:02:36.918658  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  736 02:02:36.924334  Device /sys/class/net/eth0 found
  737 02:02:36.924717  done.
  738 02:02:37.021150  Begin: Waiting up to 180 secs for any network device to become available ... done.
  739 02:02:37.107639  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  740 02:02:37.145630  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  741 02:02:37.156679   address: 172.16.3.190     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  742 02:02:37.159147   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  743 02:02:37.170478   domain : denx.de                                                         
  744 02:02:37.170882   rootserver: 172.16.3.33 rootpath: 
  745 02:02:37.174855   filename  : this-host-is-not-configured.kpxe
  746 02:02:37.218606  done.
  747 02:02:37.231472  Begin: Running /scripts/nfs-bottom ... done.
  748 02:02:37.309070  Begin: Running /scripts/init-bottom ... done.
  749 02:02:38.820861  <30>[   15.343563] systemd[1]: System time before build time, advancing clock.
  750 02:02:39.013814  <30>[   15.506235] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  751 02:02:39.019347  <30>[   15.543113] systemd[1]: Detected architecture arm.
  752 02:02:39.033052  
  753 02:02:39.033437  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  754 02:02:39.033746  
  755 02:02:39.058442  <30>[   15.580888] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  756 02:02:41.387937  <30>[   17.909807] systemd[1]: Queued start job for default target graphical.target.
  757 02:02:41.404898  <30>[   17.925070] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  758 02:02:41.413075  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  759 02:02:41.433020  <30>[   17.953337] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  760 02:02:41.441021  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  761 02:02:41.464261  <30>[   17.983853] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  762 02:02:41.471490  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  763 02:02:41.492372  <30>[   18.012430] systemd[1]: Created slice user.slice - User and Session Slice.
  764 02:02:41.498960  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  765 02:02:41.527305  <30>[   18.041898] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  766 02:02:41.533964  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  767 02:02:41.551977  <30>[   18.071635] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  768 02:02:41.562484  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  769 02:02:41.594940  <30>[   18.101572] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  770 02:02:41.602242  <30>[   18.122427] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  771 02:02:41.609018           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  772 02:02:41.631298  <30>[   18.150897] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  773 02:02:41.638183  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  774 02:02:41.661130  <30>[   18.181281] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  775 02:02:41.669414  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  776 02:02:41.691692  <30>[   18.211441] systemd[1]: Reached target paths.target - Path Units.
  777 02:02:41.696004  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  778 02:02:41.721109  <30>[   18.241183] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  779 02:02:41.728000  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  780 02:02:41.750293  <30>[   18.270940] systemd[1]: Reached target slices.target - Slice Units.
  781 02:02:41.756944  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  782 02:02:41.781093  <30>[   18.301196] systemd[1]: Reached target swap.target - Swaps.
  783 02:02:41.785356  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  784 02:02:41.811918  <30>[   18.331295] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  785 02:02:41.820912  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  786 02:02:41.841959  <30>[   18.362125] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  787 02:02:41.850213  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  788 02:02:41.936416  <30>[   18.448389] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  789 02:02:41.948955  <30>[   18.465863] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  790 02:02:41.955669  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  791 02:02:41.982042  <30>[   18.502166] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  792 02:02:41.990127  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  793 02:02:42.014297  <30>[   18.534120] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  794 02:02:42.021832  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  795 02:02:42.052220  <30>[   18.571684] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  796 02:02:42.058670  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  797 02:02:42.081872  <30>[   18.602126] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  798 02:02:42.090146  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  799 02:02:42.118334  <30>[   18.632266] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  800 02:02:42.135164  <30>[   18.648973] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  801 02:02:42.187024  <30>[   18.707314] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  802 02:02:42.215758           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  803 02:02:42.262467  <30>[   18.783523] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  804 02:02:42.286888           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  805 02:02:42.372951  <30>[   18.892304] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  806 02:02:42.389192           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  807 02:02:42.452006  <30>[   18.971967] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  808 02:02:42.473422           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  809 02:02:42.540439  <30>[   19.061574] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  810 02:02:42.560043           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  811 02:02:42.623664  <30>[   19.145205] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  812 02:02:42.643071           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  813 02:02:42.710945  <30>[   19.231835] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  814 02:02:42.732251           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  815 02:02:42.760111  <30>[   19.281934] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  816 02:02:42.782396           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  817 02:02:42.832417  <30>[   19.353854] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  818 02:02:42.859009           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  819 02:02:42.889348  <28>[   19.402690] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  820 02:02:42.897282  <28>[   19.418000] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  821 02:02:42.940892  <30>[   19.461855] systemd[1]: Starting systemd-journald.service - Journal Service...
  822 02:02:42.951506           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  823 02:02:43.020908  <30>[   19.541898] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  824 02:02:43.040022           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  825 02:02:43.069323  <30>[   19.590276] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  826 02:02:43.121219           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  827 02:02:43.183963  <30>[   19.703581] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  828 02:02:43.231748           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  829 02:02:43.295189  <30>[   19.816255] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  830 02:02:43.353582           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  831 02:02:43.412932  <30>[   19.935003] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  832 02:02:43.475748  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  833 02:02:43.491919  <30>[   20.012847] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  834 02:02:43.532448  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  835 02:02:43.553869  <30>[   20.075015] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  836 02:02:43.603910  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  837 02:02:43.763651  <30>[   20.285170] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  838 02:02:43.800929  <30>[   20.322305] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  839 02:02:43.830822  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  840 02:02:43.851127  <30>[   20.373227] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  841 02:02:43.890228  <30>[   20.410930] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  842 02:02:43.898260  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  843 02:02:43.921349  <30>[   20.442243] systemd[1]: Started systemd-journald.service - Journal Service.
  844 02:02:43.928305  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  845 02:02:43.961346  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  846 02:02:43.985270  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  847 02:02:44.016027  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  848 02:02:44.052164  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  849 02:02:44.080016  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  850 02:02:44.103027  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  851 02:02:44.132878  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  852 02:02:44.155450  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  853 02:02:44.220317           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  854 02:02:44.295481           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  855 02:02:44.374966           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  856 02:02:44.443947           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  857 02:02:44.502949           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  858 02:02:44.640654  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  859 02:02:44.657110  <46>[   21.177773] systemd-journald[162]: Received client request to flush runtime journal.
  860 02:02:44.883177  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  861 02:02:44.923526  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  862 02:02:44.955530  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  863 02:02:45.020126           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  864 02:02:46.560440  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  865 02:02:46.581890  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  866 02:02:46.600226  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  867 02:02:46.672997           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  868 02:02:46.751969  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  869 02:02:46.823876           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  870 02:02:47.700565  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  871 02:02:47.769234           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  872 02:02:49.011904  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  873 02:02:50.210230  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  874 02:02:50.690517  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  875 02:02:50.836507  <5>[   27.357710] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  876 02:02:52.255561  <5>[   28.779215] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  877 02:02:52.363387  <5>[   28.882478] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  878 02:02:52.369556  <4>[   28.892213] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  879 02:02:52.376473  <6>[   28.901294] cfg80211: failed to load regulatory.db
  880 02:02:52.757822  [[0m[0;31m*     [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
  881 02:02:53.234104  M[K[[0;1;31m*[0m[0;31m*    [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
  882 02:02:53.292829  M[K[[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  883 02:03:00.370960  [K[[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  884 02:03:00.401899  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  885 02:03:00.422397  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  886 02:03:00.494330           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  887 02:03:00.528244           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  888 02:03:00.570739           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  889 02:03:00.623707           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  890 02:03:00.909019           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  891 02:03:00.937817           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  892 02:03:00.971914  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  893 02:03:01.010285  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  894 02:03:01.049655  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  895 02:03:01.073148  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  896 02:03:01.247772  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  897 02:03:01.913390  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  898 02:03:01.970563  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  899 02:03:01.989911  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  900 02:03:02.009282  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  901 02:03:02.194484  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  902 02:03:02.323614  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  903 02:03:02.350295  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  904 02:03:02.530203  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  905 02:03:02.679524  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  906 02:03:02.702034  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  907 02:03:02.762501  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  908 02:03:02.778577  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  909 02:03:02.799982  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  910 02:03:02.860492           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  911 02:03:02.909202           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  912 02:03:03.150120           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  913 02:03:03.490115           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  914 02:03:03.519026           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  915 02:03:03.546785  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  916 02:03:03.649753  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  917 02:03:03.668885  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  918 02:03:03.913965           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  919 02:03:03.955379  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  920 02:03:04.032613  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  921 02:03:04.092025  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  922 02:03:04.119767  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  923 02:03:04.248719  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  924 02:03:04.577145  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  925 02:03:04.626119  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  926 02:03:04.672502  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  927 02:03:04.701750  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  928 02:03:04.799002           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  929 02:03:05.039065  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  930 02:03:05.256633  
  931 02:03:05.262169  Debian GNU/Linux 12 debian-boodebian-bookworm-armhf login: root (automatic login)
  932 02:03:05.262550  
  933 02:03:05.664448  Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Fri Nov  1 00:34:39 UTC 2024 armv7l
  934 02:03:05.664857  
  935 02:03:05.669370  The programs included with the Debian GNU/Linux system are free software;
  936 02:03:05.674296  the exact distribution terms for each program are described in the
  937 02:03:05.678081  individual files in /usr/share/doc/*/copyright.
  938 02:03:05.678463  
  939 02:03:05.684125  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  940 02:03:05.688517  permitted by applicable law.
  941 02:03:10.496068  Unable to match end of the kernel message
  943 02:03:10.497135  Setting prompt string to ['/ #']
  944 02:03:10.497559  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  946 02:03:10.498484  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  947 02:03:10.498895  start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
  948 02:03:10.499239  Setting prompt string to ['/ #']
  949 02:03:10.499535  Forcing a shell prompt, looking for ['/ #']
  951 02:03:10.550302  / # 
  952 02:03:10.550820  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  953 02:03:10.551188  Waiting using forced prompt support (timeout 00:02:30)
  954 02:03:10.557857  
  955 02:03:10.564862  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  956 02:03:10.565347  start: 2.4.6 export-device-env (timeout 00:03:10) [common]
  957 02:03:10.565754  Sending with 10 millisecond of delay
  959 02:03:15.620004  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz'
  960 02:03:15.630807  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214616/extract-nfsrootfs-vo1wn9rz'
  961 02:03:15.634389  Sending with 10 millisecond of delay
  963 02:03:17.673405  / # export NFS_SERVER_IP='172.16.3.3'
  964 02:03:17.684145  export NFS_SERVER_IP='172.16.3.3'
  965 02:03:17.687400  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  966 02:03:17.687889  end: 2.4 uboot-commands (duration 00:01:57) [common]
  967 02:03:17.688337  end: 2 uboot-action (duration 00:01:58) [common]
  968 02:03:17.688800  start: 3 lava-test-retry (timeout 00:06:51) [common]
  969 02:03:17.689249  start: 3.1 lava-test-shell (timeout 00:06:51) [common]
  970 02:03:17.689598  Using namespace: common
  972 02:03:17.790591  / # #
  973 02:03:17.791115  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  974 02:03:17.798381  #
  975 02:03:17.804261  Using /lava-1214616
  977 02:03:17.905254  / # export SHELL=/bin/bash
  978 02:03:17.911513  export SHELL=/bin/bash
  980 02:03:18.020208  / # . /lava-1214616/environment
  981 02:03:18.027647  . /lava-1214616/environment
  983 02:03:18.141708  / # /lava-1214616/bin/lava-test-runner /lava-1214616/0
  984 02:03:18.142231  Test shell timeout: 10s (minimum of the action and connection timeout)
  985 02:03:18.149673  /lava-1214616/bin/lava-test-runner /lava-1214616/0
  986 02:03:18.757784  + export TESTRUN_ID=0_timesync-off
  987 02:03:18.765142  + TESTRUN_ID=0_timesync-off
  988 02:03:18.765534  + cd /lava-1214616/0/tests/0_timesync-off
  989 02:03:18.765851  ++ cat uuid
  990 02:03:18.790036  + UUID=1214616_1.6.2.4.1
  991 02:03:18.790423  + set +x
  992 02:03:18.796225  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1214616_1.6.2.4.1>
  993 02:03:18.796886  Received signal: <STARTRUN> 0_timesync-off 1214616_1.6.2.4.1
  994 02:03:18.797222  Starting test lava.0_timesync-off (1214616_1.6.2.4.1)
  995 02:03:18.797598  Skipping test definition patterns.
  996 02:03:18.799450  + systemctl stop systemd-timesyncd
  997 02:03:19.118226  + set +x
  998 02:03:19.118852  Received signal: <ENDRUN> 0_timesync-off 1214616_1.6.2.4.1
  999 02:03:19.119376  Ending use of test pattern.
 1000 02:03:19.119739  Ending test lava.0_timesync-off (1214616_1.6.2.4.1), duration 0.32
 1002 02:03:19.121337  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1214616_1.6.2.4.1>
 1003 02:03:19.484480  + export TESTRUN_ID=1_kselftest-dt
 1004 02:03:19.492545  + TESTRUN_ID=1_kselftest-dt
 1005 02:03:19.492956  + cd /lava-1214616/0/tests/1_kselftest-dt
 1006 02:03:19.493364  ++ cat uuid
 1007 02:03:19.514556  + UUID=1214616_1.6.2.4.5
 1008 02:03:19.514940  + set +x
 1009 02:03:19.520536  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1214616_1.6.2.4.5>
 1010 02:03:19.520946  + cd ./automated/linux/kselftest/
 1011 02:03:19.521503  Received signal: <STARTRUN> 1_kselftest-dt 1214616_1.6.2.4.5
 1012 02:03:19.521816  Starting test lava.1_kselftest-dt (1214616_1.6.2.4.5)
 1013 02:03:19.522176  Skipping test definition patterns.
 1014 02:03:19.549563  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1015 02:03:19.725118  INFO: install_deps skipped
 1016 02:03:20.402381  --2024-01-26 21:49:17--  http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
 1017 02:03:20.439453  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1018 02:03:20.594504  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1019 02:03:20.747522  HTTP request sent, awaiting response... 200 OK
 1020 02:03:20.747905  Length: 2714836 (2.6M) [application/octet-stream]
 1021 02:03:20.752332  Saving to: 'kselftest_armhf.tar.gz'
 1022 02:03:20.752713  
 1023 02:03:22.321026  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  49.92K   164KB/s               kselftest_armhf.tar   8%[>                   ] 217.70K   358KB/s               kselftest_armhf.tar  28%[====>               ] 758.67K   649KB/s               kselftest_armhf.tar  74%[=============>      ]   1.93M  1.41MB/s               kselftest_armhf.tar 100%[===================>]   2.59M  1.65MB/s    in 1.6s    
 1024 02:03:22.321444  
 1025 02:03:22.676918  2024-01-26 21:49:19 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [2714836/2714836]
 1026 02:03:22.677343  
 1027 02:03:23.002273  tar: ./proc/fd-003-kthread: time stamp 2024-11-01 00:53:36 is 24116655.820957454 s in the future
 1028 02:03:23.252657  tar: ./proc/config: time stamp 2024-10-27 19:28:30 is 23751549.567190995 s in the future
 1029 02:03:23.503130  tar: ./proc/proc-tid0: time stamp 2024-11-01 00:53:37 is 24116656.317159079 s in the future
 1030 02:03:23.837305  tar: ./proc/proc-loadavg-001: time stamp 2024-11-01 00:53:36 is 24116654.98358337 s in the future
 1031 02:03:24.088102  tar: ./proc/proc-self-syscall: time stamp 2024-11-01 00:53:37 is 24116655.733328245 s in the future
 1032 02:03:24.346458  tar: ./proc/setns-dcache: time stamp 2024-11-01 00:53:38 is 24116656.474884245 s in the future
 1033 02:03:24.621355  tar: ./proc/setns-sysvipc: time stamp 2024-11-01 00:53:38 is 24116656.199722912 s in the future
 1034 02:03:24.879191  tar: ./proc/proc-uptime-001: time stamp 2024-11-01 00:53:37 is 24116654.94124412 s in the future
 1035 02:03:25.138206  tar: ./proc/fd-001-lookup: time stamp 2024-11-01 00:53:35 is 24116652.682475578 s in the future
 1036 02:03:25.387811  tar: ./proc/proc-uptime-002: time stamp 2024-11-01 00:53:37 is 24116654.432525787 s in the future
 1037 02:03:25.646804  tar: ./proc/fd-002-posix-eq: time stamp 2024-11-01 00:53:36 is 24116653.17373487 s in the future
 1038 02:03:25.880472  tar: ./proc/thread-self: time stamp 2024-11-01 00:53:38 is 24116654.940507537 s in the future
 1039 02:03:26.138342  tar: ./proc/read: time stamp 2024-11-01 00:53:38 is 24116654.681607287 s in the future
 1040 02:03:26.387675  tar: ./proc/self: time stamp 2024-11-01 00:53:38 is 24116654.431727661 s in the future
 1041 02:03:26.655797  tar: ./proc/proc-pid-vm: time stamp 2024-11-01 00:53:36 is 24116652.164400036 s in the future
 1042 02:03:26.889479  tar: ./proc/proc-multiple-procfs: time stamp 2024-11-01 00:53:38 is 24116653.93151737 s in the future
 1043 02:03:27.124461  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-11-01 00:53:37 is 24116652.697443745 s in the future
 1044 02:03:27.356152  tar: ./proc/proc-subset-pid: time stamp 2024-11-01 00:53:37 is 24116652.464474286 s in the future
 1045 02:03:27.607780  tar: ./proc/proc-self-map-files-001: time stamp 2024-11-01 00:53:37 is 24116652.213448078 s in the future
 1046 02:03:27.832010  tar: ./proc/proc-self-wchan: time stamp 2024-11-01 00:53:37 is 24116651.989055036 s in the future
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 1350 02:04:42.045899  tar: ./net/tcp_ao/restore_ipv4: time stamp 2024-11-01 00:53:28 is 24116568.771177944 s in the future
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 1353 02:04:42.922098  tar: ./net/tcp_ao/icmps-accept_ipv6: time stamp 2024-11-01 00:53:30 is 24116569.895313861 s in the future
 1354 02:04:43.216483  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-11-01 00:53:28 is 24116567.600616027 s in the future
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 1357 02:04:44.065800  tar: ./net/tcp_ao/unsigned-md5_ipv4: time stamp 2024-11-01 00:53:29 is 24116567.751952986 s in the future
 1358 02:04:44.380972  tar: ./net/tcp_ao/icmps-discard_ipv4: time stamp 2024-11-01 00:53:27 is 24116565.435880486 s in the future
 1359 02:04:44.694858  tar: ./net/tcp_ao/connect-deny_ipv4: time stamp 2024-11-01 00:53:26 is 24116564.121526527 s in the future
 1360 02:04:44.988847  tar: ./net/tcp_ao/setsockopt-closed_ipv4: time stamp 2024-11-01 00:53:29 is 24116566.828256027 s in the future
 1361 02:04:45.300442  tar: ./net/tcp_ao/rst_ipv6: time stamp 2024-11-01 00:53:31 is 24116568.51555011 s in the future
 1362 02:04:45.592312  tar: ./net/tcp_ao/seq-ext_ipv6: time stamp 2024-11-01 00:53:32 is 24116569.224636527 s in the future
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 1364 02:04:46.154855  tar: ./net/tcp_ao/icmps-discard_ipv6: time stamp 2024-11-01 00:53:31 is 24116567.662182527 s in the future
 1365 02:04:46.535309  tar: ./net/tcp_ao/connect-deny_ipv6: time stamp 2024-11-01 00:53:30 is 24116566.281442319 s in the future
 1366 02:04:46.866592  tar: ./net/tcp_ao/key-management_ipv4: time stamp 2024-11-01 00:53:27 is 24116562.950626944 s in the future
 1367 02:04:47.182839  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-11-01 00:53:27 is 24116562.634742902 s in the future
 1368 02:04:47.500972  tar: ./net/tcp_ao/bench-lookups_ipv6: time stamp 2024-11-01 00:53:30 is 24116565.316232027 s in the future
 1369 02:04:47.779097  tar: ./net/tcp_ao/self-connect_ipv6: time stamp 2024-11-01 00:53:32 is 24116567.037712735 s in the future
 1370 02:04:48.074941  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-11-01 00:53:28 is 24116562.740607693 s in the future
 1371 02:04:48.222830  tar: ./net/tcp_ao: time stamp 2024-11-01 00:54:18 is 24116612.591792318 s in the future
 1372 02:04:48.495522  tar: ./net/forwarding/q_in_vni.sh: time stamp 2024-10-27 19:28:30 is 23751464.32131686 s in the future
 1373 02:04:48.754529  tar: ./net/forwarding/router_mpath_nh_res.sh: time stamp 2024-10-27 19:28:30 is 23751464.062596735 s in the future
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 1375 02:04:49.268547  tar: ./net/forwarding/sch_tbf_etsprio.sh: time stamp 2024-10-27 19:28:30 is 23751463.548187527 s in the future
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 1377 02:04:49.763435  tar: ./net/forwarding/vxlan_symmetric.sh: time stamp 2024-10-27 19:28:30 is 23751463.05350011 s in the future
 1378 02:04:49.998225  tar: ./net/forwarding/ip6gre_hier.sh: time stamp 2024-11-01 00:06:48 is 24113760.820368402 s in the future
 1379 02:04:50.239440  tar: ./net/forwarding/sch_tbf_prio.sh: time stamp 2024-10-27 19:28:30 is 23751462.577739485 s in the future
 1380 02:04:50.472035  tar: ./net/forwarding/tc_actions.sh: time stamp 2024-10-27 19:28:30 is 23751462.34503386 s in the future
 1381 02:04:50.774484  tar: ./net/forwarding/tc_flower_port_range.sh: time stamp 2024-10-27 19:28:30 is 23751462.043802526 s in the future
 1382 02:04:51.031814  tar: ./net/forwarding/vxlan_bridge_1d_port_8472_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751461.786370901 s in the future
 1383 02:04:51.283492  tar: ./net/forwarding/gre_multipath_nh_res.sh: time stamp 2024-10-27 19:28:30 is 23751461.534838901 s in the future
 1384 02:04:51.522448  tar: ./net/forwarding/devlink_lib.sh: time stamp 2024-10-27 19:28:30 is 23751461.294363026 s in the future
 1385 02:04:51.833668  tar: ./net/forwarding/ipip_hier_gre_key.sh: time stamp 2024-10-27 19:28:30 is 23751460.984318193 s in the future
 1386 02:04:52.089770  tar: ./net/forwarding/tc_flower_router.sh: time stamp 2024-10-27 19:28:30 is 23751460.727317651 s in the future
 1387 02:04:52.338347  tar: ./net/forwarding/lib.sh: time stamp 2024-10-27 19:28:30 is 23751460.47821786 s in the future
 1388 02:04:52.582735  tar: ./net/forwarding/mirror_gre_bridge_1q_lag.sh: time stamp 2024-10-27 19:28:30 is 23751460.23530886 s in the future
 1389 02:04:52.826008  tar: ./net/forwarding/router_bridge_lag.sh: time stamp 2024-10-27 19:28:30 is 23751459.99116036 s in the future
 1390 02:04:53.057609  tar: ./net/forwarding/ipip_flat_gre.sh: time stamp 2024-10-27 19:28:30 is 23751459.759985776 s in the future
 1391 02:04:53.290642  tar: ./net/forwarding/sch_tbf_root.sh: time stamp 2024-10-27 19:28:30 is 23751459.526976109 s in the future
 1392 02:04:53.549881  tar: ./net/forwarding/skbedit_priority.sh: time stamp 2024-10-27 19:28:30 is 23751459.267953359 s in the future
 1393 02:04:53.782798  tar: ./net/forwarding/bridge_mdb_max.sh: time stamp 2024-10-27 19:28:30 is 23751459.034951859 s in the future
 1394 02:04:54.033636  tar: ./net/forwarding/ip6gre_custom_multipath_hash.sh: time stamp 2024-10-27 19:28:30 is 23751458.784212109 s in the future
 1395 02:04:54.273995  tar: ./net/forwarding/router_multicast.sh: time stamp 2024-10-27 19:28:30 is 23751458.542899651 s in the future
 1396 02:04:54.533197  tar: ./net/forwarding/mirror_gre_flower.sh: time stamp 2024-10-27 19:28:30 is 23751458.283838276 s in the future
 1397 02:04:54.761617  tar: ./net/forwarding/router_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751458.055381026 s in the future
 1398 02:04:55.017869  tar: ./net/forwarding/vxlan_bridge_1d_port_8472.sh: time stamp 2024-10-27 19:28:30 is 23751457.800216276 s in the future
 1399 02:04:55.250749  tar: ./net/forwarding/tc_shblocks.sh: time stamp 2024-10-27 19:28:30 is 23751457.566888068 s in the future
 1400 02:04:55.515845  tar: ./net/forwarding/config: time stamp 2024-10-27 19:28:30 is 23751457.299869568 s in the future
 1401 02:04:55.759517  tar: ./net/forwarding/dual_vxlan_bridge.sh: time stamp 2024-10-27 19:28:30 is 23751457.058075484 s in the future
 1402 02:04:56.012261  tar: ./net/forwarding/mirror_gre_vlan_bridge_1q.sh: time stamp 2024-10-27 19:28:30 is 23751456.805619859 s in the future
 1403 02:04:56.258747  tar: ./net/forwarding/sch_ets_tests.sh: time stamp 2024-10-27 19:28:30 is 23751456.557566817 s in the future
 1404 02:04:56.507633  tar: ./net/forwarding/ip6gre_inner_v4_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751456.309731984 s in the future
 1405 02:04:56.775942  tar: ./net/forwarding/mirror_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751456.040449984 s in the future
 1406 02:04:57.028682  tar: ./net/forwarding/fib_offload_lib.sh: time stamp 2024-10-27 19:28:30 is 23751455.788097651 s in the future
 1407 02:04:57.310153  tar: ./net/forwarding/bridge_mdb.sh: time stamp 2024-10-27 19:28:30 is 23751455.506603151 s in the future
 1408 02:04:57.587282  tar: ./net/forwarding/bridge_vlan_aware.sh: time stamp 2024-10-27 19:28:30 is 23751455.229469734 s in the future
 1409 02:04:57.835004  tar: ./net/forwarding/router_bridge_1d.sh: time stamp 2024-10-27 19:28:30 is 23751454.981915692 s in the future
 1410 02:04:58.078262  tar: ./net/forwarding/bridge_vlan_mcast.sh: time stamp 2024-10-27 19:28:30 is 23751454.739268609 s in the future
 1411 02:04:58.309973  tar: ./net/forwarding/router.sh: time stamp 2024-10-27 19:28:30 is 23751454.505784317 s in the future
 1412 02:04:58.752743  tar: ./net/forwarding/ipip_flat_gre_key.sh: time stamp 2024-10-27 19:28:30 is 23751454.063937192 s in the future
 1413 02:04:58.994980  tar: ./net/forwarding/vxlan_asymmetric_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751453.821878109 s in the future
 1414 02:04:59.278356  tar: ./net/forwarding/router_broadcast.sh: time stamp 2024-10-27 19:28:30 is 23751453.538410109 s in the future
 1415 02:04:59.512160  tar: ./net/forwarding/ip6gre_hier_key.sh: time stamp 2024-11-01 00:06:48 is 24113751.304400942 s in the future
 1416 02:04:59.771474  tar: ./net/forwarding/bridge_fdb_learning_limit.sh: time stamp 2024-10-27 19:28:30 is 23751453.046293775 s in the future
 1417 02:05:00.021074  tar: ./net/forwarding/ip6gre_flat_key.sh: time stamp 2024-11-01 00:06:48 is 24113750.7956574 s in the future
 1418 02:05:00.270709  tar: ./net/forwarding/tc_flower_l2_miss.sh: time stamp 2024-10-27 19:28:30 is 23751452.545914984 s in the future
 1419 02:05:00.505798  tar: ./net/forwarding/ip6gre_inner_v6_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751452.311852275 s in the future
 1420 02:05:00.739586  tar: ./net/forwarding/tc_tunnel_key.sh: time stamp 2024-10-27 19:28:30 is 23751452.077076317 s in the future
 1421 02:05:00.961939  tar: ./net/forwarding/no_forwarding.sh: time stamp 2024-10-27 19:28:30 is 23751451.854190775 s in the future
 1422 02:05:01.207471  tar: ./net/forwarding/router_mpath_seed.sh: time stamp 2024-10-27 19:28:30 is 23751451.609888734 s in the future
 1423 02:05:01.441249  tar: ./net/forwarding/vxlan_bridge_1q_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751451.376445025 s in the future
 1424 02:05:01.674473  tar: ./net/forwarding/vxlan_asymmetric.sh: time stamp 2024-10-27 19:28:30 is 23751451.142877275 s in the future
 1425 02:05:01.906932  tar: ./net/forwarding/sch_tbf_core.sh: time stamp 2024-10-27 19:28:30 is 23751450.909330858 s in the future
 1426 02:05:02.154679  tar: ./net/forwarding/gre_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751450.661178317 s in the future
 1427 02:05:02.373693  tar: ./net/forwarding/sch_ets_core.sh: time stamp 2024-10-27 19:28:30 is 23751450.442244442 s in the future
 1428 02:05:02.632686  tar: ./net/forwarding/gre_inner_v6_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751450.183790025 s in the future
 1429 02:05:02.866181  tar: ./net/forwarding/mirror_gre_lib.sh: time stamp 2024-10-27 19:28:30 is 23751449.950265442 s in the future
 1430 02:05:03.124319  tar: ./net/forwarding/sch_red.sh: time stamp 2024-10-27 19:28:30 is 23751449.69171165 s in the future
 1431 02:05:03.424918  tar: ./net/forwarding/ip6gre_flat_keys.sh: time stamp 2024-11-01 00:06:48 is 24113747.39159965 s in the future
 1432 02:05:03.708167  tar: ./net/forwarding/router_mpath_nh.sh: time stamp 2024-10-27 19:28:30 is 23751449.108222067 s in the future
 1433 02:05:04.059078  tar: ./net/forwarding/ipip_flat_gre_keys.sh: time stamp 2024-10-27 19:28:30 is 23751448.757842858 s in the future
 1434 02:05:04.317085  tar: ./net/forwarding/ip6gre_lib.sh: time stamp 2024-11-01 00:06:48 is 24113746.4993129 s in the future
 1435 02:05:04.542618  tar: ./net/forwarding/bridge_sticky_fdb.sh: time stamp 2024-10-27 19:28:30 is 23751448.274029191 s in the future
 1436 02:05:04.802034  tar: ./net/forwarding/vxlan_bridge_1q_port_8472_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751448.015598941 s in the future
 1437 02:05:05.035047  tar: ./net/forwarding/mirror_gre_bridge_1d_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751447.78206715 s in the future
 1438 02:05:05.301657  tar: ./net/forwarding/tc_police.sh: time stamp 2024-10-27 19:28:30 is 23751447.515233358 s in the future
 1439 02:05:05.584422  tar: ./net/forwarding/gre_multipath_nh.sh: time stamp 2024-10-27 19:28:30 is 23751447.232542816 s in the future
 1440 02:05:05.836238  tar: ./net/forwarding/vxlan_bridge_1d_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751446.981003233 s in the future
 1441 02:05:06.077616  tar: ./net/forwarding/q_in_vni_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751446.739068858 s in the future
 1442 02:05:06.327776  tar: ./net/forwarding/vxlan_bridge_1q_port_8472.sh: time stamp 2024-10-27 19:28:30 is 23751446.488999108 s in the future
 1443 02:05:06.551925  tar: ./net/forwarding/mirror_lib.sh: time stamp 2024-10-27 19:28:30 is 23751446.263763275 s in the future
 1444 02:05:06.795493  tar: ./net/forwarding/vxlan_symmetric_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751446.021961316 s in the future
 1445 02:05:07.034519  tar: ./net/forwarding/pedit_dsfield.sh: time stamp 2024-10-27 19:28:30 is 23751445.781165399 s in the future
 1446 02:05:07.286229  tar: ./net/forwarding/settings: time stamp 2024-10-27 19:28:30 is 23751445.529874108 s in the future
 1447 02:05:07.510553  tar: ./net/forwarding/mirror_gre_nh.sh: time stamp 2024-10-27 19:28:30 is 23751445.305636733 s in the future
 1448 02:05:07.787691  tar: ./net/forwarding/ip6gre_flat.sh: time stamp 2024-11-01 00:06:48 is 24113743.029447858 s in the future
 1449 02:05:08.011144  tar: ./net/forwarding/tc_chains.sh: time stamp 2024-10-27 19:28:30 is 23751444.805232608 s in the future
 1450 02:05:08.271435  tar: ./net/forwarding/bridge_mdb_port_down.sh: time stamp 2024-10-27 19:28:30 is 23751444.545705024 s in the future
 1451 02:05:08.487548  tar: ./net/forwarding/gre_custom_multipath_hash.sh: time stamp 2024-10-27 19:28:30 is 23751444.329715274 s in the future
 1452 02:05:08.738602  tar: ./net/forwarding/mirror_gre_bound.sh: time stamp 2024-10-27 19:28:30 is 23751444.078634899 s in the future
 1453 02:05:08.954507  tar: ./net/forwarding/ip6_forward_instats_vrf.sh: time stamp 2024-10-27 19:28:30 is 23751443.862502858 s in the future
 1454 02:05:09.427901  tar: ./net/forwarding/tc_vlan_modify.sh: time stamp 2024-10-27 19:28:30 is 23751443.387662774 s in the future
 1455 02:05:09.779105  tar: ./net/forwarding/bridge_vlan_unaware.sh: time stamp 2024-10-27 19:28:30 is 23751443.037172649 s in the future
 1456 02:05:10.046617  tar: ./net/forwarding/bridge_mld.sh: time stamp 2024-10-27 19:28:30 is 23751442.769493482 s in the future
 1457 02:05:10.280472  tar: ./net/forwarding/gre_inner_v4_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751442.536686732 s in the future
 1458 02:05:10.514009  tar: ./net/forwarding/router_nh.sh: time stamp 2024-10-27 19:28:30 is 23751442.301871441 s in the future
 1459 02:05:10.755483  tar: ./net/forwarding/mirror_topo_lib.sh: time stamp 2024-10-27 19:28:30 is 23751442.061130024 s in the future
 1460 02:05:10.989595  tar: ./net/forwarding/bridge_port_isolation.sh: time stamp 2024-10-27 19:28:30 is 23751441.827171149 s in the future
 1461 02:05:11.213761  tar: ./net/forwarding/sch_tbf_ets.sh: time stamp 2024-10-27 19:28:30 is 23751441.602262857 s in the future
 1462 02:05:11.447650  tar: ./net/forwarding/router_bridge_vlan_upper.sh: time stamp 2024-10-27 19:28:30 is 23751441.368457066 s in the future
 1463 02:05:11.681621  tar: ./net/forwarding/router_bridge_1d_lag.sh: time stamp 2024-10-27 19:28:30 is 23751441.134873941 s in the future
 1464 02:05:11.915480  tar: ./net/forwarding/custom_multipath_hash.sh: time stamp 2024-10-27 19:28:30 is 23751440.901249107 s in the future
 1465 02:05:12.215798  tar: ./net/forwarding/mirror_gre_lag_lacp.sh: time stamp 2024-10-27 19:28:30 is 23751440.600728566 s in the future
 1466 02:05:12.473802  tar: ./net/forwarding/min_max_mtu.sh: time stamp 2024-10-27 19:28:30 is 23751440.342084566 s in the future
 1467 02:05:12.715215  tar: ./net/forwarding/sch_ets.sh: time stamp 2024-10-27 19:28:30 is 23751440.100180274 s in the future
 1468 02:05:12.964812  tar: ./net/forwarding/tc_flower_cfm.sh: time stamp 2024-10-27 19:28:30 is 23751439.850558107 s in the future
 1469 02:05:13.199467  tar: ./net/forwarding/router_bridge_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751439.616217857 s in the future
 1470 02:05:13.466084  tar: ./net/forwarding/local_termination.sh: time stamp 2024-10-27 19:28:30 is 23751439.349865357 s in the future
 1471 02:05:13.750457  tar: ./net/forwarding/mirror_gre_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751439.065587357 s in the future
 1472 02:05:13.985442  tar: ./net/forwarding/router_bridge_vlan_upper_pvid.sh: time stamp 2024-10-27 19:28:30 is 23751438.831968774 s in the future
 1473 02:05:14.225563  tar: ./net/forwarding/mirror_gre_changes.sh: time stamp 2024-10-27 19:28:30 is 23751438.589968107 s in the future
 1474 02:05:14.441268  tar: ./net/forwarding/tc_common.sh: time stamp 2024-10-27 19:28:30 is 23751438.374023857 s in the future
 1475 02:05:14.675834  tar: ./net/forwarding/router_vid_1.sh: time stamp 2024-10-27 19:28:30 is 23751438.13938244 s in the future
 1476 02:05:14.933892  tar: ./net/forwarding/bridge_mdb_host.sh: time stamp 2024-10-27 19:28:30 is 23751437.881754065 s in the future
 1477 02:05:15.168772  tar: ./net/forwarding/ipip_hier_gre_keys.sh: time stamp 2024-10-27 19:28:30 is 23751437.64705594 s in the future
 1478 02:05:15.418311  tar: ./net/forwarding/mirror_gre_topo_lib.sh: time stamp 2024-10-27 19:28:30 is 23751437.39815194 s in the future
 1479 02:05:15.661673  tar: ./net/forwarding/forwarding.config.sample: time stamp 2024-10-27 19:28:30 is 23751437.154848523 s in the future
 1480 02:05:15.910484  tar: ./net/forwarding/pedit_l4port.sh: time stamp 2024-10-27 19:28:30 is 23751436.905988232 s in the future
 1481 02:05:16.152694  tar: ./net/forwarding/lib_sh_test.sh: time stamp 2024-10-27 19:28:30 is 23751436.662488107 s in the future
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 1532 02:05:28.641686  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-6pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751424.176454772 s in the future
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 1534 02:05:29.123764  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-10-27 19:28:30 is 23751423.692553314 s in the future
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 1540 02:05:30.527111  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-1pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751422.290908313 s in the future
 1541 02:05:30.765139  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-10-27 19:28:30 is 23751422.05220298 s in the future
 1542 02:05:31.002642  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-5pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751421.81537548 s in the future
 1543 02:05:31.241400  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751421.576867397 s in the future
 1544 02:05:31.469135  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-4pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751421.348188897 s in the future
 1545 02:05:31.715878  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-idle.pkt: time stamp 2024-10-27 19:28:30 is 23751421.101204938 s in the future
 1546 02:05:31.960848  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-10-27 19:28:30 is 23751420.85606348 s in the future
 1547 02:05:32.189119  tar: ./net/packetdrill/tcp_inq_server.pkt: time stamp 2024-10-27 19:28:30 is 23751420.625495563 s in the future
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 1550 02:05:32.902412  tar: ./net/packetdrill/tcp_zerocopy_epoll_edge.pkt: time stamp 2024-10-27 19:28:30 is 23751419.91337998 s in the future
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 2063 02:07:12.001111  tar: ./tc-testing/tc-tests/qdiscs/etf.json: time stamp 2024-10-27 19:28:30 is 23751320.809036718 s in the future
 2064 02:07:12.134743  tar: ./tc-testing/tc-tests/qdiscs/cake.json: time stamp 2024-10-27 19:28:30 is 23751320.675448926 s in the future
 2065 02:07:12.268354  tar: ./tc-testing/tc-tests/qdiscs/taprio.json: time stamp 2024-10-27 19:28:30 is 23751320.541876343 s in the future
 2066 02:07:12.398598  tar: ./tc-testing/tc-tests/qdiscs/drr.json: time stamp 2024-10-27 19:28:30 is 23751320.410745051 s in the future
 2067 02:07:12.531270  tar: ./tc-testing/tc-tests/qdiscs/prio.json: time stamp 2024-10-27 19:28:30 is 23751320.279449968 s in the future
 2068 02:07:12.691124  tar: ./tc-testing/tc-tests/qdiscs/fq_pie.json: time stamp 2024-10-27 19:28:30 is 23751320.119349218 s in the future
 2069 02:07:12.857347  tar: ./tc-testing/tc-tests/qdiscs/mq.json: time stamp 2024-10-27 19:28:30 is 23751319.951842384 s in the future
 2070 02:07:12.982249  tar: ./tc-testing/tc-tests/qdiscs/plug.json: time stamp 2024-10-27 19:28:30 is 23751319.826697676 s in the future
 2071 02:07:13.141091  tar: ./tc-testing/tc-tests/qdiscs/mqprio.json: time stamp 2024-10-27 19:28:30 is 23751319.668986176 s in the future
 2072 02:07:13.195141  tar: ./tc-testing/tc-tests/qdiscs: time stamp 2024-10-27 19:28:30 is 23751319.613822718 s in the future
 2073 02:07:13.358413  tar: ./tc-testing/tc-tests/actions/sample.json: time stamp 2024-10-27 19:28:30 is 23751319.451350426 s in the future
 2074 02:07:13.483606  tar: ./tc-testing/tc-tests/actions/connmark.json: time stamp 2024-10-27 19:28:30 is 23751319.326122718 s in the future
 2075 02:07:13.624878  tar: ./tc-testing/tc-tests/actions/tunnel_key.json: time stamp 2024-10-27 19:28:30 is 23751319.185193093 s in the future
 2076 02:07:13.775213  tar: ./tc-testing/tc-tests/actions/mpls.json: time stamp 2024-10-27 19:28:30 is 23751319.034821093 s in the future
 2077 02:07:13.918340  tar: ./tc-testing/tc-tests/actions/skbedit.json: time stamp 2024-10-27 19:28:30 is 23751318.892241509 s in the future
 2078 02:07:14.065680  tar: ./tc-testing/tc-tests/actions/skbmod.json: time stamp 2024-10-27 19:28:30 is 23751318.744614718 s in the future
 2079 02:07:14.211927  tar: ./tc-testing/tc-tests/actions/ife.json: time stamp 2024-10-27 19:28:30 is 23751318.598210468 s in the future
 2080 02:07:14.359285  tar: ./tc-testing/tc-tests/actions/gact.json: time stamp 2024-10-27 19:28:30 is 23751318.451080134 s in the future
 2081 02:07:14.493024  tar: ./tc-testing/tc-tests/actions/gate.json: time stamp 2024-10-27 19:28:30 is 23751318.316917343 s in the future
 2082 02:07:14.637166  tar: ./tc-testing/tc-tests/actions/pedit.json: time stamp 2024-10-27 19:28:30 is 23751318.172620593 s in the future
 2083 02:07:14.784363  tar: ./tc-testing/tc-tests/actions/bpf.json: time stamp 2024-10-27 19:28:30 is 23751318.026059009 s in the future
 2084 02:07:14.943732  tar: ./tc-testing/tc-tests/actions/simple.json: time stamp 2024-10-27 19:28:30 is 23751317.867330218 s in the future
 2085 02:07:15.082338  tar: ./tc-testing/tc-tests/actions/police.json: time stamp 2024-10-27 19:28:30 is 23751317.728557468 s in the future
 2086 02:07:15.217180  tar: ./tc-testing/tc-tests/actions/nat.json: time stamp 2024-10-27 19:28:30 is 23751317.592645843 s in the future
 2087 02:07:15.368568  tar: ./tc-testing/tc-tests/actions/csum.json: time stamp 2024-10-27 19:28:30 is 23751317.441124301 s in the future
 2088 02:07:15.518968  tar: ./tc-testing/tc-tests/actions/ctinfo.json: time stamp 2024-10-27 19:28:30 is 23751317.291006634 s in the future
 2089 02:07:15.676877  tar: ./tc-testing/tc-tests/actions/vlan.json: time stamp 2024-10-27 19:28:30 is 23751317.132657759 s in the future
 2090 02:07:15.831737  tar: ./tc-testing/tc-tests/actions/mirred.json: time stamp 2024-10-27 19:28:30 is 23751316.978285259 s in the future
 2091 02:07:15.976967  tar: ./tc-testing/tc-tests/actions/ct.json: time stamp 2024-10-27 19:28:30 is 23751316.832918884 s in the future
 2092 02:07:16.026933  tar: ./tc-testing/tc-tests/actions: time stamp 2024-10-27 19:28:30 is 23751316.782115842 s in the future
 2093 02:07:16.084268  tar: ./tc-testing/tc-tests: time stamp 2024-10-27 19:28:30 is 23751316.724467051 s in the future
 2094 02:07:16.207010  tar: ./tc-testing/config: time stamp 2024-10-27 19:28:30 is 23751316.600872842 s in the future
 2095 02:07:16.359313  tar: ./tc-testing/TdcPlugin.py: time stamp 2024-10-27 19:28:30 is 23751316.449897967 s in the future
 2096 02:07:16.485300  tar: ./tc-testing/tdc_helper.py: time stamp 2024-10-27 19:28:30 is 23751316.323443051 s in the future
 2097 02:07:16.617502  tar: ./tc-testing/tdc.sh: time stamp 2024-10-27 19:28:30 is 23751316.189935426 s in the future
 2098 02:07:16.749636  tar: ./tc-testing/tdc_config.py: time stamp 2024-10-27 19:28:30 is 23751316.058131676 s in the future
 2099 02:07:16.885072  tar: ./tc-testing/settings: time stamp 2024-10-27 19:28:30 is 23751315.923780134 s in the future
 2100 02:07:17.045129  tar: ./tc-testing/plugin-lib/scapyPlugin.py: time stamp 2024-10-27 19:28:30 is 23751315.764503301 s in the future
 2101 02:07:17.176299  tar: ./tc-testing/plugin-lib/README-PLUGINS: time stamp 2024-10-27 19:28:30 is 23751315.632557926 s in the future
 2102 02:07:17.311959  tar: ./tc-testing/plugin-lib/rootPlugin.py: time stamp 2024-10-27 19:28:30 is 23751315.497664717 s in the future
 2103 02:07:17.437093  tar: ./tc-testing/plugin-lib/nsPlugin.py: time stamp 2024-10-27 19:28:30 is 23751315.372188801 s in the future
 2104 02:07:17.572687  tar: ./tc-testing/plugin-lib/valgrindPlugin.py: time stamp 2024-10-27 19:28:30 is 23751315.236573217 s in the future
 2105 02:07:17.634301  tar: ./tc-testing/plugin-lib: time stamp 2024-10-27 19:28:30 is 23751315.174565384 s in the future
 2106 02:07:17.761326  tar: ./tc-testing/action-ebpf: time stamp 2024-10-27 19:28:30 is 23751315.047130384 s in the future
 2107 02:07:17.940480  tar: ./tc-testing/scripts/taprio_wait_for_admin.sh: time stamp 2024-10-27 19:28:30 is 23751314.869652301 s in the future
 2108 02:07:17.998767  tar: ./tc-testing/scripts: time stamp 2024-10-27 19:28:30 is 23751314.809185967 s in the future
 2109 02:07:18.119700  tar: ./tc-testing/tdc_config_local_template.py: time stamp 2024-10-27 19:28:30 is 23751314.690141384 s in the future
 2110 02:07:18.245917  tar: ./tc-testing/tdc_batch.py: time stamp 2024-10-27 19:28:30 is 23751314.563236092 s in the future
 2111 02:07:18.395156  tar: ./tc-testing/tdc_multibatch.py: time stamp 2024-10-27 19:28:30 is 23751314.413073009 s in the future
 2112 02:07:18.514795  tar: ./tc-testing/plugins/__init__.py: time stamp 2024-10-27 19:28:30 is 23751314.294043009 s in the future
 2113 02:07:18.576377  tar: ./tc-testing/plugins: time stamp 2024-10-27 19:28:30 is 23751314.231441009 s in the future
 2114 02:07:18.637910  tar: ./tc-testing: time stamp 2024-11-01 00:54:22 is 24116466.1690528 s in the future
 2115 02:07:18.832484  tar: ./kselftest/runner.sh: time stamp 2024-11-01 00:54:07 is 24116450.974749342 s in the future
 2116 02:07:18.959356  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-27 19:28:30 is 23751313.848270009 s in the future
 2117 02:07:19.085294  tar: ./kselftest/module.sh: time stamp 2024-11-01 00:54:07 is 24116450.722648092 s in the future
 2118 02:07:19.212200  tar: ./kselftest/ksft.py: time stamp 2024-11-01 00:54:07 is 24116450.595712509 s in the future
 2119 02:07:19.353769  tar: ./kselftest/prefix.pl: time stamp 2024-11-01 00:54:07 is 24116450.45394405 s in the future
 2120 02:07:19.411105  tar: ./kselftest: time stamp 2024-10-27 19:28:30 is 23751313.3954168 s in the future
 2121 02:07:19.565667  tar: ./tty/tty_tstamp_update: time stamp 2024-11-01 00:53:50 is 24116433.243003009 s in the future
 2122 02:07:19.634424  tar: ./tty: time stamp 2024-11-01 00:54:23 is 24116466.171742884 s in the future
 2123 02:07:19.693704  tar: .: time stamp 2024-11-01 00:54:26 is 24116469.112251009 s in the future
 2124 02:07:19.997895  skiplist:
 2125 02:07:19.998320  ========================================
 2126 02:07:20.001996  ========================================
 2127 02:07:20.319201  dt:test_unprobed_devices.sh
 2128 02:07:20.433056  ============== Tests to run ===============
 2129 02:07:20.443433  dt:test_unprobed_devices.sh
 2130 02:07:20.447818  ===========End Tests to run ===============
 2131 02:07:20.497914  shardfile-dt pass
 2132 02:07:21.218560  <12>[  297.758542] kselftest: Running tests in dt
 2133 02:07:21.251632  TAP version 13
 2134 02:07:21.275201  1..1
 2135 02:07:21.331998  # timeout set to 45
 2136 02:07:21.332311  # selftests: dt: test_unprobed_devices.sh
 2137 02:07:22.185459  # TAP version 13
 2138 02:07:48.003389  # 1..257
 2139 02:07:48.191774  # ok 1 / # SKIP
 2140 02:07:48.211470  # ok 2 /clk_mcasp0
 2141 02:07:48.286178  # ok 3 /clk_mcasp0_fixed # SKIP
 2142 02:07:48.364055  # ok 4 /cpus/cpu@0 # SKIP
 2143 02:07:48.437995  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2144 02:07:48.458799  # ok 6 /fixedregulator0
 2145 02:07:48.483728  # ok 7 /leds
 2146 02:07:48.500951  # ok 8 /ocp
 2147 02:07:48.525715  # ok 9 /ocp/interconnect@44c00000
 2148 02:07:48.555162  # ok 10 /ocp/interconnect@44c00000/segment@0
 2149 02:07:48.575227  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2150 02:07:48.601968  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2151 02:07:48.681391  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2152 02:07:48.699327  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2153 02:07:48.730649  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2154 02:07:48.841658  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2155 02:07:48.919251  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2156 02:07:49.000768  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2157 02:07:49.069912  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2158 02:07:49.151978  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2159 02:07:49.225501  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2160 02:07:49.302078  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2161 02:07:49.378432  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2162 02:07:49.453855  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2163 02:07:49.529648  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2164 02:07:49.606014  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2165 02:07:49.682753  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2166 02:07:49.759536  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2167 02:07:49.835186  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2168 02:07:49.912750  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2169 02:07:49.988430  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2170 02:07:50.068201  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2171 02:07:50.142693  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2172 02:07:50.222376  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2173 02:07:50.296678  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2174 02:07:50.370956  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2175 02:07:50.448564  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2176 02:07:50.529565  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2177 02:07:50.602973  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2178 02:07:50.680858  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2179 02:07:50.756405  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2180 02:07:50.833090  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2181 02:07:50.911084  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2182 02:07:50.986794  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2183 02:07:51.064747  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2184 02:07:51.140267  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2185 02:07:51.217820  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2186 02:07:51.293476  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2187 02:07:51.370248  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2188 02:07:51.446781  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2189 02:07:51.527910  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2190 02:07:51.600161  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2191 02:07:51.676980  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2192 02:07:51.755057  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2193 02:07:51.829726  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2194 02:07:51.907543  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2195 02:07:51.987596  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2196 02:07:52.059774  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2197 02:07:52.136365  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2198 02:07:52.212012  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2199 02:07:52.379681  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2200 02:07:52.389108  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2201 02:07:52.449410  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2202 02:07:52.521948  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2203 02:07:52.597640  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2204 02:07:52.679680  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2205 02:07:52.751267  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2206 02:07:52.826937  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2207 02:07:52.907902  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2208 02:07:52.981614  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2209 02:07:53.059395  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2210 02:07:53.135257  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2211 02:07:53.210855  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2212 02:07:53.286339  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2213 02:07:53.358695  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2214 02:07:53.433489  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2215 02:07:53.507888  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2216 02:07:53.583578  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2217 02:07:53.657428  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2218 02:07:53.733202  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2219 02:07:53.809847  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2220 02:07:53.888971  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2221 02:07:53.957936  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2222 02:07:54.035860  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2223 02:07:54.106774  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2224 02:07:54.181296  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2225 02:07:54.253627  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2226 02:07:54.328051  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2227 02:07:54.402849  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2228 02:07:54.478726  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2229 02:07:54.548924  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2230 02:07:54.624868  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2231 02:07:54.700575  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2232 02:07:54.774284  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2233 02:07:54.794704  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2234 02:07:54.819381  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2235 02:07:54.842833  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2236 02:07:54.867603  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2237 02:07:54.895758  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2238 02:07:54.916406  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2239 02:07:54.939819  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2240 02:07:54.967703  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2241 02:07:55.070487  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2242 02:07:55.100648  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2243 02:07:55.122325  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2244 02:07:55.149274  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2245 02:07:55.252278  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2246 02:07:55.331167  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2247 02:07:55.403703  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2248 02:07:55.479651  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2249 02:07:55.552163  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2250 02:07:55.620619  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2251 02:07:55.694383  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2252 02:07:55.767933  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2253 02:07:55.842695  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2254 02:07:55.917489  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2255 02:07:55.991273  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2256 02:07:56.070487  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2257 02:07:56.138911  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2258 02:07:56.216149  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2259 02:07:56.289910  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2260 02:07:56.363943  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2261 02:07:56.386640  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2262 02:07:56.459019  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2263 02:07:56.530124  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2264 02:07:56.604312  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2265 02:07:56.625814  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2266 02:07:56.698901  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2267 02:07:56.722440  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2268 02:07:56.794576  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2269 02:07:56.817038  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2270 02:07:56.846935  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2271 02:07:56.870658  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2272 02:07:56.892087  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2273 02:07:56.915679  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2274 02:07:56.939307  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2275 02:07:56.966286  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 2276 02:07:57.042435  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 2277 02:07:57.067732  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2278 02:07:57.091574  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2279 02:07:57.160539  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2280 02:07:57.232947  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2281 02:07:57.255557  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2282 02:07:57.362362  # not ok 144 /ocp/interconnect@47c00000
 2283 02:07:57.436304  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2284 02:07:57.457358  # ok 146 /ocp/interconnect@48000000
 2285 02:07:57.481888  # ok 147 /ocp/interconnect@48000000/segment@0
 2286 02:07:57.503055  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2287 02:07:57.529801  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2288 02:07:57.549931  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2289 02:07:57.574430  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2290 02:07:57.597888  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2291 02:07:57.623381  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2292 02:07:57.644680  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2293 02:07:57.717812  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2294 02:07:57.791944  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2295 02:07:57.815332  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2296 02:07:57.839803  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2297 02:07:57.862029  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2298 02:07:57.885806  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2299 02:07:57.909040  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2300 02:07:57.938023  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2301 02:07:57.960839  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2302 02:07:57.986509  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2303 02:07:58.009880  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2304 02:07:58.032648  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2305 02:07:58.054176  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2306 02:07:58.077675  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2307 02:07:58.106674  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2308 02:07:58.130047  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2309 02:07:58.149294  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2310 02:07:58.174004  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2311 02:07:58.196670  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2312 02:07:58.226464  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2313 02:07:58.247651  # ok 175 /ocp/interconnect@48000000/segment@100000
 2314 02:07:58.267798  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2315 02:07:58.293037  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2316 02:07:58.370585  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 2317 02:07:58.444445  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 2318 02:07:58.516987  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 2319 02:07:58.587236  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 2320 02:07:58.658523  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 2321 02:07:58.736672  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 2322 02:07:58.805876  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 2323 02:07:58.880587  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 2324 02:07:58.901940  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2325 02:07:58.929789  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2326 02:07:58.949995  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2327 02:07:58.976947  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2328 02:07:59.000252  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2329 02:07:59.022764  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2330 02:07:59.046510  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2331 02:07:59.077504  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2332 02:07:59.100079  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2333 02:07:59.119454  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2334 02:07:59.148365  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2335 02:07:59.170904  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2336 02:07:59.188968  # ok 198 /ocp/interconnect@48000000/segment@200000
 2337 02:07:59.218777  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2338 02:07:59.290759  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2339 02:07:59.308673  # ok 201 /ocp/interconnect@48000000/segment@300000
 2340 02:07:59.334413  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2341 02:07:59.359813  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2342 02:07:59.383363  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2343 02:07:59.405805  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2344 02:07:59.429446  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2345 02:07:59.458384  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2346 02:07:59.530765  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2347 02:07:59.546553  # ok 209 /ocp/interconnect@4a000000
 2348 02:07:59.570590  # ok 210 /ocp/interconnect@4a000000/segment@0
 2349 02:07:59.600540  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2350 02:07:59.619780  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2351 02:07:59.650166  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2352 02:07:59.669672  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2353 02:07:59.744998  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2354 02:07:59.847772  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2355 02:07:59.922467  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2356 02:08:00.028667  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2357 02:08:00.099754  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2358 02:08:00.173881  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2359 02:08:00.275119  # not ok 221 /ocp/interconnect@4b140000
 2360 02:08:00.349221  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2361 02:08:00.426426  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2362 02:08:00.447445  # ok 224 /ocp/target-module@40300000
 2363 02:08:00.475342  # ok 225 /ocp/target-module@40300000/sram@0
 2364 02:08:00.543150  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2365 02:08:00.616277  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2366 02:08:00.636072  # ok 228 /ocp/target-module@47400000
 2367 02:08:00.665711  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2368 02:08:00.688058  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2369 02:08:00.707262  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2370 02:08:00.730429  # ok 232 /ocp/target-module@47400000/usb@1400
 2371 02:08:00.753511  # ok 233 /ocp/target-module@47400000/usb@1800
 2372 02:08:00.776867  # ok 234 /ocp/target-module@47810000
 2373 02:08:00.802109  # ok 235 /ocp/target-module@49000000
 2374 02:08:00.821782  # ok 236 /ocp/target-module@49000000/dma@0
 2375 02:08:00.847029  # ok 237 /ocp/target-module@49800000
 2376 02:08:00.872644  # ok 238 /ocp/target-module@49800000/dma@0
 2377 02:08:00.892438  # ok 239 /ocp/target-module@49900000
 2378 02:08:00.917683  # ok 240 /ocp/target-module@49900000/dma@0
 2379 02:08:00.943229  # ok 241 /ocp/target-module@49a00000
 2380 02:08:00.967587  # ok 242 /ocp/target-module@49a00000/dma@0
 2381 02:08:00.985078  # ok 243 /ocp/target-module@4c000000
 2382 02:08:01.063287  # not ok 244 /ocp/target-module@4c000000/emif@0
 2383 02:08:01.084325  # ok 245 /ocp/target-module@50000000
 2384 02:08:01.103062  # ok 246 /ocp/target-module@53100000
 2385 02:08:01.178025  # not ok 247 /ocp/target-module@53100000/sham@0
 2386 02:08:01.203447  # ok 248 /ocp/target-module@53500000
 2387 02:08:01.276336  # not ok 249 /ocp/target-module@53500000/aes@0
 2388 02:08:01.292878  # ok 250 /ocp/target-module@56000000
 2389 02:08:01.404849  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2390 02:08:01.471107  # ok 252 /opp-table # SKIP
 2391 02:08:01.545811  # ok 253 /soc # SKIP
 2392 02:08:01.563382  # ok 254 /sound
 2393 02:08:01.588593  # ok 255 /target-module@4b000000
 2394 02:08:01.617173  # ok 256 /target-module@4b000000/target-module@140000
 2395 02:08:01.635533  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2396 02:08:01.642434  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2397 02:08:01.651663  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2398 02:08:04.008811  dt_test_unprobed_devices_sh_ skip
 2399 02:08:04.013493  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2400 02:08:04.019603  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2401 02:08:04.019758  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2402 02:08:04.028185  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2403 02:08:04.034351  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2404 02:08:04.034504  dt_test_unprobed_devices_sh_leds pass
 2405 02:08:04.039168  dt_test_unprobed_devices_sh_ocp pass
 2406 02:08:04.043917  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2407 02:08:04.048976  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2408 02:08:04.057477  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2409 02:08:04.063595  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2410 02:08:04.074513  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2411 02:08:04.079478  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2412 02:08:04.085725  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2413 02:08:04.095410  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2414 02:08:04.106505  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2415 02:08:04.116171  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2416 02:08:04.127280  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2417 02:08:04.132128  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2418 02:08:04.147945  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2419 02:08:04.152888  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2420 02:08:04.162622  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2421 02:08:04.173628  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2422 02:08:04.183407  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2423 02:08:04.194420  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2424 02:08:04.204128  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2425 02:08:04.215373  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2426 02:08:04.225057  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2427 02:08:04.236059  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2428 02:08:04.245878  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2429 02:08:04.256890  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2430 02:08:04.266749  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2431 02:08:04.272882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2432 02:08:04.282499  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2433 02:08:04.293629  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2434 02:08:04.303290  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2435 02:08:04.314407  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2436 02:08:04.324056  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2437 02:08:04.335186  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2438 02:08:04.344844  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2439 02:08:04.355997  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2440 02:08:04.370748  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2441 02:08:04.381751  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2442 02:08:04.391502  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2443 02:08:04.402500  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2444 02:08:04.412377  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2445 02:08:04.423373  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2446 02:08:04.433064  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2447 02:08:04.444060  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2448 02:08:04.459937  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2449 02:08:04.469621  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2450 02:08:04.480754  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2451 02:08:04.490399  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2452 02:08:04.501499  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2453 02:08:04.516377  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2454 02:08:04.527369  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2455 02:08:04.537058  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2456 02:08:04.548057  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2457 02:08:04.557874  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2458 02:08:04.568888  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2459 02:08:04.578622  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2460 02:08:04.589622  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2461 02:08:04.599494  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2462 02:08:04.609295  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2463 02:08:04.620371  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2464 02:08:04.631371  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2465 02:08:04.641056  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2466 02:08:04.652054  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2467 02:08:04.661874  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2468 02:08:04.672883  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2469 02:08:04.688885  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2470 02:08:04.698491  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2471 02:08:04.709630  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2472 02:08:04.719309  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2473 02:08:04.730501  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2474 02:08:04.740057  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2475 02:08:04.751200  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2476 02:08:04.765866  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2477 02:08:04.776888  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2478 02:08:04.786622  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2479 02:08:04.797625  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2480 02:08:04.807497  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2481 02:08:04.817290  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2482 02:08:04.828371  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2483 02:08:04.839279  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2484 02:08:04.849206  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2485 02:08:04.855271  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2486 02:08:04.869874  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2487 02:08:04.881123  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2488 02:08:04.890833  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2489 02:08:04.901825  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2490 02:08:04.911618  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2491 02:08:04.927399  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2492 02:08:04.938501  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2493 02:08:04.943497  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2494 02:08:04.953246  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2495 02:08:04.964243  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2496 02:08:04.973951  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2497 02:08:04.980067  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2498 02:08:04.989716  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2499 02:08:05.000883  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2500 02:08:05.005749  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2501 02:08:05.015493  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2502 02:08:05.026493  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2503 02:08:05.036365  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2504 02:08:05.047367  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2505 02:08:05.059494  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2506 02:08:05.070491  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2507 02:08:05.081491  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2508 02:08:05.092497  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2509 02:08:05.108399  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2510 02:08:05.118046  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2511 02:08:05.129181  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2512 02:08:05.143819  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2513 02:08:05.154827  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2514 02:08:05.164608  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2515 02:08:05.180392  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2516 02:08:05.191490  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2517 02:08:05.206114  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2518 02:08:05.217371  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2519 02:08:05.233180  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2520 02:08:05.242822  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2521 02:08:05.253932  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2522 02:08:05.258819  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2523 02:08:05.268611  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2524 02:08:05.274744  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2525 02:08:05.284393  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2526 02:08:05.295492  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2527 02:08:05.305286  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2528 02:08:05.310369  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2529 02:08:05.321370  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2530 02:08:05.331053  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2531 02:08:05.337186  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2532 02:08:05.346818  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2533 02:08:05.351818  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2534 02:08:05.362817  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 2535 02:08:05.378744  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 2536 02:08:05.383609  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2537 02:08:05.393494  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2538 02:08:05.403283  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2539 02:08:05.414276  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2540 02:08:05.425398  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2541 02:08:05.430157  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2542 02:08:05.435194  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2543 02:08:05.441269  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2544 02:08:05.446113  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2545 02:08:05.456051  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2546 02:08:05.462121  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2547 02:08:05.471766  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2548 02:08:05.476882  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2549 02:08:05.487955  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2550 02:08:05.492729  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2551 02:08:05.503925  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2552 02:08:05.508878  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2553 02:08:05.518609  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2554 02:08:05.524738  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2555 02:08:05.534392  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2556 02:08:05.545492  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2557 02:08:05.550391  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2558 02:08:05.560193  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2559 02:08:05.571110  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2560 02:08:05.576045  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2561 02:08:05.587177  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2562 02:08:05.592044  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2563 02:08:05.601872  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2564 02:08:05.607985  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2565 02:08:05.617584  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2566 02:08:05.622735  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2567 02:08:05.633747  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2568 02:08:05.643489  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2569 02:08:05.649609  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2570 02:08:05.659277  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2571 02:08:05.670395  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2572 02:08:05.675364  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2573 02:08:05.685048  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2574 02:08:05.691177  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2575 02:08:05.700823  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 2576 02:08:05.711922  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 2577 02:08:05.721604  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 2578 02:08:05.732738  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 2579 02:08:05.747387  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 2580 02:08:05.758385  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 2581 02:08:05.768187  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 2582 02:08:05.779115  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 2583 02:08:05.784042  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2584 02:08:05.795175  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2585 02:08:05.800042  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2586 02:08:05.809865  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2587 02:08:05.820877  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2588 02:08:05.825579  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2589 02:08:05.836733  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2590 02:08:05.846389  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2591 02:08:05.851386  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2592 02:08:05.862485  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2593 02:08:05.872111  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2594 02:08:05.878236  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2595 02:08:05.883058  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2596 02:08:05.892866  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2597 02:08:05.903812  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2598 02:08:05.908605  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2599 02:08:05.913611  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2600 02:08:05.924733  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2601 02:08:05.934483  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2602 02:08:05.940604  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2603 02:08:05.950273  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2604 02:08:05.961390  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2605 02:08:05.966357  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2606 02:08:05.971234  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2607 02:08:05.976056  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2608 02:08:05.987042  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2609 02:08:05.996841  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2610 02:08:06.002904  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2611 02:08:06.012574  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2612 02:08:06.023669  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2613 02:08:06.028711  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2614 02:08:06.044593  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2615 02:08:06.049460  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2616 02:08:06.061916  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2617 02:08:06.072903  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2618 02:08:06.078948  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2619 02:08:06.083950  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2620 02:08:06.090108  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2621 02:08:06.094989  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2622 02:08:06.099820  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2623 02:08:06.104867  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2624 02:08:06.115930  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2625 02:08:06.120709  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2626 02:08:06.125745  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2627 02:08:06.131820  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2628 02:08:06.136730  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2629 02:08:06.146477  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2630 02:08:06.152624  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2631 02:08:06.157499  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2632 02:08:06.162315  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2633 02:08:06.167346  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2634 02:08:06.173497  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2635 02:08:06.178371  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2636 02:08:06.183057  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2637 02:08:06.194184  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2638 02:08:06.194338  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2639 02:08:06.203784  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2640 02:08:06.208879  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2641 02:08:06.214983  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2642 02:08:06.219922  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2643 02:08:06.224726  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2644 02:08:06.229731  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2645 02:08:06.235860  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2646 02:08:06.240659  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2647 02:08:06.245603  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2648 02:08:06.250607  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2649 02:08:06.256740  dt_test_unprobed_devices_sh_opp-table skip
 2650 02:08:06.261612  dt_test_unprobed_devices_sh_soc skip
 2651 02:08:06.261763  dt_test_unprobed_devices_sh_sound pass
 2652 02:08:06.271478  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2653 02:08:06.277486  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2654 02:08:06.282478  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2655 02:08:06.287130  dt_test_unprobed_devices_sh fail
 2656 02:08:06.290471  + ../../utils/send-to-lava.sh ./output/result.txt
 2657 02:08:06.407512  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2658 02:08:06.408070  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2660 02:08:06.654471  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2661 02:08:06.654899  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2663 02:08:06.839560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2664 02:08:06.839901  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2666 02:08:07.024670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2667 02:08:07.025153  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2669 02:08:07.224466  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2670 02:08:07.224926  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2672 02:08:07.413771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2673 02:08:07.414120  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2675 02:08:07.591347  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2676 02:08:07.591697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2678 02:08:07.758183  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2679 02:08:07.758520  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2681 02:08:07.954558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2682 02:08:07.955012  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2684 02:08:08.137587  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2685 02:08:08.138055  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2687 02:08:08.346269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2688 02:08:08.346695  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2690 02:08:08.558963  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2691 02:08:08.559395  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2693 02:08:08.748703  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2694 02:08:08.749107  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2696 02:08:08.941717  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2697 02:08:08.942187  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2699 02:08:09.302131  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2700 02:08:09.302598  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2702 02:08:09.500413  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2703 02:08:09.500750  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2705 02:08:09.682665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2706 02:08:09.683008  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2708 02:08:09.859700  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2709 02:08:09.860040  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2711 02:08:10.034754  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2712 02:08:10.035095  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2714 02:08:10.215483  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2715 02:08:10.215824  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2717 02:08:10.408554  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2718 02:08:10.408896  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2720 02:08:10.583810  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2721 02:08:10.584149  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2723 02:08:10.800134  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2724 02:08:10.800472  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2726 02:08:10.989063  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2727 02:08:10.989404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2729 02:08:11.201440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2730 02:08:11.201781  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2732 02:08:11.392551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2733 02:08:11.392889  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2735 02:08:11.582527  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2736 02:08:11.582866  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2738 02:08:11.791049  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2739 02:08:11.791397  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2741 02:08:12.102486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2742 02:08:12.103114  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2744 02:08:12.283121  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2745 02:08:12.283820  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2747 02:08:12.475051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2748 02:08:12.475678  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2750 02:08:12.683159  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2751 02:08:12.683780  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2753 02:08:12.879481  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2754 02:08:12.880114  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2756 02:08:13.063154  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2757 02:08:13.063775  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2759 02:08:13.251999  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2760 02:08:13.252624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2762 02:08:13.442001  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2763 02:08:13.442624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2765 02:08:13.641535  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2766 02:08:13.642156  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2768 02:08:13.835784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2769 02:08:13.836405  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2771 02:08:14.038509  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2772 02:08:14.039139  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2774 02:08:14.255042  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2775 02:08:14.255660  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2777 02:08:14.452608  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2778 02:08:14.453263  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2780 02:08:14.651271  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2781 02:08:14.651889  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2783 02:08:14.846775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2784 02:08:14.847404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2786 02:08:15.034610  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2787 02:08:15.035224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2789 02:08:15.222784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2790 02:08:15.223403  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2792 02:08:15.417203  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2793 02:08:15.417820  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2795 02:08:15.607323  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2796 02:08:15.607945  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2798 02:08:15.846138  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2799 02:08:15.846762  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2801 02:08:16.062752  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2802 02:08:16.063371  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2804 02:08:16.261522  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2805 02:08:16.262141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2807 02:08:16.451657  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2808 02:08:16.452280  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2810 02:08:16.658761  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2811 02:08:16.659385  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2813 02:08:16.864766  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2814 02:08:16.865413  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2816 02:08:17.073964  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2817 02:08:17.074588  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2819 02:08:17.271672  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2820 02:08:17.272297  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2822 02:08:17.488420  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2823 02:08:17.489065  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2825 02:08:17.685207  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2826 02:08:17.685827  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2828 02:08:17.896672  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2829 02:08:17.897319  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2831 02:08:18.104629  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2832 02:08:18.105278  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2834 02:08:18.298800  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2835 02:08:18.299417  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2837 02:08:18.503751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2838 02:08:18.504368  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2840 02:08:18.704632  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2841 02:08:18.705280  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2843 02:08:18.923282  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2844 02:08:18.923904  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2846 02:08:19.109163  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2847 02:08:19.109785  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2849 02:08:19.300238  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2850 02:08:19.300869  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2852 02:08:19.493463  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2853 02:08:19.494080  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2855 02:08:19.700578  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2856 02:08:19.701226  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2858 02:08:19.898190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2859 02:08:19.898804  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2861 02:08:20.138013  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2862 02:08:20.138630  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2864 02:08:20.327761  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2865 02:08:20.328386  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2867 02:08:20.544609  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2868 02:08:20.545260  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2870 02:08:20.753552  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2871 02:08:20.754171  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2873 02:08:20.955135  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2874 02:08:20.955753  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2876 02:08:21.164289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2877 02:08:21.164878  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2879 02:08:21.385948  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2880 02:08:21.386569  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2882 02:08:21.588830  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2883 02:08:21.589449  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2885 02:08:21.797955  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2886 02:08:21.798571  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2888 02:08:22.015623  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2889 02:08:22.016242  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2891 02:08:22.191919  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2892 02:08:22.192540  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2894 02:08:22.403137  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2895 02:08:22.403754  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2897 02:08:22.625866  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2898 02:08:22.626487  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2900 02:08:22.805437  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2901 02:08:22.806055  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2903 02:08:23.022802  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2904 02:08:23.023417  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2906 02:08:23.210829  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2907 02:08:23.211446  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2909 02:08:23.412636  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2910 02:08:23.413283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2912 02:08:23.612289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2913 02:08:23.612875  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2915 02:08:23.804569  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2916 02:08:23.805219  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2918 02:08:24.004061  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2919 02:08:24.004677  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2921 02:08:24.203550  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2922 02:08:24.204165  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2924 02:08:24.403289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2925 02:08:24.403908  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2927 02:08:24.586237  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2928 02:08:24.586857  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2930 02:08:24.774071  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2931 02:08:24.774733  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2933 02:08:24.982340  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2934 02:08:24.982965  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2936 02:08:25.171574  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2937 02:08:25.172200  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2939 02:08:25.362037  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2940 02:08:25.362657  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2942 02:08:25.559412  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2943 02:08:25.560036  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2945 02:08:25.741071  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2946 02:08:25.741692  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2948 02:08:25.929765  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2949 02:08:25.930391  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2951 02:08:26.128060  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2952 02:08:26.128682  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2954 02:08:26.322456  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2955 02:08:26.323076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2957 02:08:26.506931  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2958 02:08:26.507555  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2960 02:08:27.622573  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2961 02:08:27.623331  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2963 02:08:27.813260  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2964 02:08:27.813881  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2966 02:08:28.013693  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2967 02:08:28.014323  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2969 02:08:28.239607  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2970 02:08:28.240240  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 2972 02:08:28.429508  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 2973 02:08:28.430142  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 2975 02:08:28.624840  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 2976 02:08:28.625468  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 2978 02:08:28.806416  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 2979 02:08:28.807041  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 2981 02:08:29.001945  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 2982 02:08:29.002569  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 2984 02:08:29.201798  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 2985 02:08:29.202421  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 2987 02:08:29.401528  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 2988 02:08:29.402147  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 2990 02:08:29.593750  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 2991 02:08:29.594376  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 2993 02:08:29.777036  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 2994 02:08:29.777659  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 2996 02:08:29.967265  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 2997 02:08:29.967882  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 2999 02:08:30.159326  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3000 02:08:30.159948  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3002 02:08:30.356751  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3003 02:08:30.357392  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3005 02:08:30.554417  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3006 02:08:30.555036  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3008 02:08:30.748019  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3009 02:08:30.748640  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3011 02:08:30.930938  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3012 02:08:30.931571  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3014 02:08:31.124486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3015 02:08:31.125146  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3017 02:08:31.309831  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3019 02:08:31.312839  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3020 02:08:31.488736  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3022 02:08:31.491717  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3023 02:08:31.679109  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3025 02:08:31.682200  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3026 02:08:31.890010  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3027 02:08:31.890632  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3029 02:08:32.119165  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3030 02:08:32.119786  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3032 02:08:32.316336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3033 02:08:32.316957  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3035 02:08:32.484264  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3036 02:08:32.484876  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3038 02:08:32.678252  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3039 02:08:32.678868  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3041 02:08:32.897606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3042 02:08:32.898224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3044 02:08:33.088665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3045 02:08:33.089316  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3047 02:08:33.287821  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3048 02:08:33.288439  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3050 02:08:33.487368  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3051 02:08:33.487986  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3053 02:08:33.689799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3054 02:08:33.690418  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3056 02:08:33.881731  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3057 02:08:33.882350  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3059 02:08:34.072248  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3060 02:08:34.072877  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3062 02:08:34.258538  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3063 02:08:34.259158  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3065 02:08:34.454828  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3066 02:08:34.455446  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3068 02:08:34.659581  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 3069 02:08:34.660202  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 3071 02:08:34.853199  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 3072 02:08:34.853819  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 3074 02:08:35.068601  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3075 02:08:35.069257  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3077 02:08:35.259514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3078 02:08:35.260139  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3080 02:08:35.465339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3081 02:08:35.465963  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3083 02:08:35.669029  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3084 02:08:35.669647  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3086 02:08:35.864144  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3087 02:08:35.864767  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3089 02:08:36.065227  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3090 02:08:36.065841  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3092 02:08:36.258025  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3093 02:08:36.258640  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3095 02:08:36.448443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3096 02:08:36.449092  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3098 02:08:36.638921  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3099 02:08:36.639537  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3101 02:08:36.842460  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3102 02:08:36.843082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3104 02:08:37.036737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3105 02:08:37.037376  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3107 02:08:37.227371  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3108 02:08:37.227990  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3110 02:08:38.418664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3111 02:08:38.419420  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3113 02:08:38.623158  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3114 02:08:38.623779  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3116 02:08:38.825629  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3117 02:08:38.826262  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3119 02:08:39.026225  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3120 02:08:39.026854  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3122 02:08:39.217108  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3123 02:08:39.217727  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3125 02:08:39.407789  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3126 02:08:39.408414  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3128 02:08:39.615026  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3129 02:08:39.615650  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3131 02:08:39.809645  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3132 02:08:39.810271  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3134 02:08:39.998509  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3135 02:08:39.999130  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3137 02:08:40.197650  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3138 02:08:40.198269  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3140 02:08:40.397094  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3141 02:08:40.397715  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3143 02:08:40.586054  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3144 02:08:40.586669  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3146 02:08:40.769531  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3147 02:08:40.770149  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3149 02:08:40.949616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3150 02:08:40.950235  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3152 02:08:41.139399  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3153 02:08:41.140022  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3155 02:08:41.326230  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3156 02:08:41.326851  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3158 02:08:41.501349  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3159 02:08:41.501971  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3161 02:08:41.696502  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3162 02:08:41.697151  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3164 02:08:41.896778  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3165 02:08:41.897589  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3167 02:08:42.097190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3168 02:08:42.097898  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3170 02:08:42.285444  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3171 02:08:42.286123  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3173 02:08:42.461037  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3174 02:08:42.461717  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3176 02:08:42.637300  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3177 02:08:42.638004  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3179 02:08:43.745926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3180 02:08:43.746684  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3182 02:08:43.953361  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3183 02:08:43.953982  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3185 02:08:44.147745  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3186 02:08:44.148367  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3188 02:08:44.344491  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3189 02:08:44.345148  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3191 02:08:44.543964  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 3192 02:08:44.544589  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 3194 02:08:44.741662  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 3195 02:08:44.742286  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 3197 02:08:44.945425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 3198 02:08:44.946051  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 3200 02:08:45.170471  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 3201 02:08:45.171099  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 3203 02:08:45.379257  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 3204 02:08:45.379880  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 3206 02:08:45.573755  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 3207 02:08:45.574379  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 3209 02:08:45.749054  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 3210 02:08:45.749678  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 3212 02:08:45.944425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 3213 02:08:45.945074  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 3215 02:08:46.136277  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3216 02:08:46.136878  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3218 02:08:46.320171  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3219 02:08:46.320808  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3221 02:08:46.513990  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3222 02:08:46.514607  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3224 02:08:46.707810  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3225 02:08:46.708436  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3227 02:08:46.898768  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3228 02:08:46.899386  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3230 02:08:47.085496  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3231 02:08:47.086116  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3233 02:08:47.270418  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3234 02:08:47.271039  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3236 02:08:47.453649  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3237 02:08:47.454210  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3239 02:08:47.657610  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3240 02:08:47.658292  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3242 02:08:47.840738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3243 02:08:47.841493  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3245 02:08:48.019990  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3246 02:08:48.020742  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3248 02:08:48.196204  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3249 02:08:48.196889  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3251 02:08:48.369574  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3252 02:08:48.370330  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3254 02:08:48.558329  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3255 02:08:48.559050  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3257 02:08:48.777661  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3258 02:08:48.778371  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3260 02:08:48.964033  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3261 02:08:48.964803  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3263 02:08:49.141969  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3264 02:08:49.142653  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3266 02:08:49.326691  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3267 02:08:49.327372  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3269 02:08:49.517576  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3270 02:08:49.518252  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3272 02:08:49.707416  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3273 02:08:49.708109  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3275 02:08:49.876768  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3276 02:08:49.877566  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3278 02:08:50.048727  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3279 02:08:50.049443  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3281 02:08:50.251378  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3282 02:08:50.252061  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3284 02:08:50.457781  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3285 02:08:50.458451  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3287 02:08:50.650385  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3288 02:08:50.651105  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3290 02:08:50.830633  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3291 02:08:50.831308  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3293 02:08:51.000013  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3294 02:08:51.000730  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3296 02:08:51.203177  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3297 02:08:51.203806  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3299 02:08:51.384593  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3300 02:08:51.385264  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3302 02:08:51.588974  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3303 02:08:51.589591  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3305 02:08:51.771484  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3306 02:08:51.772103  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3308 02:08:51.958567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3309 02:08:51.959189  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3311 02:08:52.148523  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3312 02:08:52.149187  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3314 02:08:52.338442  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3315 02:08:52.339063  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3317 02:08:52.524348  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3318 02:08:52.524970  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3320 02:08:52.697835  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3321 02:08:52.698454  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3323 02:08:52.874689  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3324 02:08:52.875314  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3326 02:08:53.102312  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3327 02:08:53.102934  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3329 02:08:53.285254  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3330 02:08:53.285870  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3332 02:08:53.455649  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3333 02:08:53.456262  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3335 02:08:53.657932  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3336 02:08:53.658554  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3338 02:08:53.828949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3340 02:08:53.832009  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3341 02:08:54.013725  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3342 02:08:54.014340  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3344 02:08:54.204466  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3345 02:08:54.205110  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3347 02:08:54.390905  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3348 02:08:54.391518  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3350 02:08:54.564815  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3351 02:08:54.565441  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3353 02:08:54.744772  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3354 02:08:54.745415  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3356 02:08:54.943560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3357 02:08:54.944176  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3359 02:08:55.135065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3360 02:08:55.135685  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3362 02:08:55.331610  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3363 02:08:55.332234  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3365 02:08:55.528449  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3366 02:08:55.529109  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3368 02:08:55.704103  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3369 02:08:55.704724  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3371 02:08:55.899842  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3372 02:08:55.900457  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3374 02:08:56.123922  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3375 02:08:56.124544  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3377 02:08:56.295246  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3378 02:08:56.295865  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3380 02:08:56.464372  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3381 02:08:56.464992  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3383 02:08:56.651902  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3384 02:08:56.652517  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3386 02:08:56.838282  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3387 02:08:56.838902  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3389 02:08:57.079290  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3390 02:08:57.079906  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3392 02:08:57.262737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3393 02:08:57.263155  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3395 02:08:57.443292  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3396 02:08:57.443909  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3398 02:08:57.613658  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3399 02:08:57.614279  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3401 02:08:57.790349  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3402 02:08:57.790969  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3404 02:08:57.991473  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3405 02:08:57.992089  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3407 02:08:58.174784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3408 02:08:58.175406  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3410 02:08:58.671451  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3411 02:08:58.672086  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3413 02:08:58.857700  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3414 02:08:58.858316  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3416 02:08:59.042243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3417 02:08:59.042867  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3419 02:08:59.239667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3420 02:08:59.240283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3422 02:08:59.455926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3423 02:08:59.456546  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3425 02:08:59.654384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3426 02:08:59.655007  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3428 02:08:59.854591  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3429 02:08:59.855207  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3431 02:09:00.040440  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3432 02:09:00.041081  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3434 02:09:00.046853  + set +x
 3435 02:09:00.047531  Received signal: <ENDRUN> 1_kselftest-dt 1214616_1.6.2.4.5
 3436 02:09:00.047885  Ending use of test pattern.
 3437 02:09:00.048191  Ending test lava.1_kselftest-dt (1214616_1.6.2.4.5), duration 340.53
 3439 02:09:00.050106  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1214616_1.6.2.4.5>
 3440 02:09:00.103352  <LAVA_TEST_RUNNER EXIT>
 3441 02:09:00.103970  ok: lava_test_shell seems to have completed
 3442 02:09:00.111295  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3443 02:09:00.112741  end: 3.1 lava-test-shell (duration 00:05:42) [common]
 3444 02:09:00.113198  end: 3 lava-test-retry (duration 00:05:42) [common]
 3445 02:09:00.113621  start: 4 finalize (timeout 00:01:09) [common]
 3446 02:09:00.114043  start: 4.1 power-off (timeout 00:00:30) [common]
 3447 02:09:00.114529  Calling: 'drpm' 'lf-bbb-02' 'off'
 3448 02:09:00.522975  >> OFF

 3449 02:09:00.524265  Returned 0 in 0 seconds
 3450 02:09:00.625179  end: 4.1 power-off (duration 00:00:01) [common]
 3452 02:09:00.626325  start: 4.2 read-feedback (timeout 00:01:08) [common]
 3453 02:09:00.627185  Listened to connection for namespace 'common' for up to 1s
 3454 02:09:00.627863  Listened to connection for namespace 'common' for up to 1s
 3455 02:09:01.627426  Finalising connection for namespace 'common'
 3456 02:09:01.627910  Disconnecting from shell: Finalise
 3457 02:09:01.628290  / # 
 3458 02:09:01.729049  end: 4.2 read-feedback (duration 00:00:01) [common]
 3459 02:09:01.729557  end: 4 finalize (duration 00:00:02) [common]
 3460 02:09:01.730049  Cleaning after the job
 3461 02:09:01.730517  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/ramdisk
 3462 02:09:01.736554  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/kernel
 3463 02:09:01.741339  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/dtb
 3464 02:09:01.742074  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/nfsrootfs
 3465 02:09:01.849443  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214616/tftp-deploy-0fzdm02b/modules
 3466 02:09:01.854930  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1214616
 3467 02:09:02.995416  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1214616
 3468 02:09:02.995741  Job finished correctly