Boot log: beaglebone-black

    1 00:56:47.523817  lava-dispatcher, installed at version: 2023.08
    2 00:56:47.524190  start: 0 validate
    3 00:56:47.524424  Start time: 2024-11-01 00:56:47.524409+00:00 (UTC)
    4 00:56:47.524698  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 00:56:47.853031  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/kernel/zImage exists
    6 00:56:48.010782  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 00:56:48.166068  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 00:56:48.321327  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/modules.tar.xz exists
    9 00:56:48.484425  validate duration: 0.96
   11 00:56:48.485520  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 00:56:48.485991  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 00:56:48.486432  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 00:56:48.487144  Not decompressing ramdisk as can be used compressed.
   15 00:56:48.487577  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 00:56:48.487915  saving as /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/ramdisk/initrd.cpio.gz
   17 00:56:48.488259  total size: 4775763 (4 MB)
   18 00:56:48.798013  progress   0 % (0 MB)
   19 00:56:49.258289  progress   5 % (0 MB)
   20 00:56:49.410911  progress  10 % (0 MB)
   21 00:56:49.595788  progress  15 % (0 MB)
   22 00:56:49.606127  progress  20 % (0 MB)
   23 00:56:49.738628  progress  25 % (1 MB)
   24 00:56:49.759362  progress  30 % (1 MB)
   25 00:56:49.766950  progress  35 % (1 MB)
   26 00:56:49.872639  progress  40 % (1 MB)
   27 00:56:49.899235  progress  45 % (2 MB)
   28 00:56:50.035980  progress  50 % (2 MB)
   29 00:56:50.177750  progress  55 % (2 MB)
   30 00:56:50.210777  progress  60 % (2 MB)
   31 00:56:50.352135  progress  65 % (2 MB)
   32 00:56:50.492105  progress  70 % (3 MB)
   33 00:56:50.521705  progress  75 % (3 MB)
   34 00:56:50.662218  progress  80 % (3 MB)
   35 00:56:50.795543  progress  85 % (3 MB)
   36 00:56:50.830945  progress  90 % (4 MB)
   37 00:56:50.970109  progress  95 % (4 MB)
   38 00:56:51.100124  progress 100 % (4 MB)
   39 00:56:51.100560  4 MB downloaded in 2.61 s (1.74 MB/s)
   40 00:56:51.100889  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 00:56:51.101368  end: 1.1 download-retry (duration 00:00:03) [common]
   43 00:56:51.101539  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 00:56:51.101704  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 00:56:51.101975  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/kernel/zImage
   46 00:56:51.102104  saving as /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/kernel/zImage
   47 00:56:51.102226  total size: 12042752 (11 MB)
   48 00:56:51.102349  No compression specified
   49 00:56:51.259174  progress   0 % (0 MB)
   50 00:56:51.443087  progress   5 % (0 MB)
   51 00:56:51.874555  progress  10 % (1 MB)
   52 00:56:52.193915  progress  15 % (1 MB)
   53 00:56:52.502826  progress  20 % (2 MB)
   54 00:56:52.810795  progress  25 % (2 MB)
   55 00:56:53.120879  progress  30 % (3 MB)
   56 00:56:53.425801  progress  35 % (4 MB)
   57 00:56:53.736742  progress  40 % (4 MB)
   58 00:56:54.038631  progress  45 % (5 MB)
   59 00:56:54.342791  progress  50 % (5 MB)
   60 00:56:54.649627  progress  55 % (6 MB)
   61 00:56:54.953011  progress  60 % (6 MB)
   62 00:56:55.256294  progress  65 % (7 MB)
   63 00:56:55.562739  progress  70 % (8 MB)
   64 00:56:55.863322  progress  75 % (8 MB)
   65 00:56:56.169537  progress  80 % (9 MB)
   66 00:56:56.470093  progress  85 % (9 MB)
   67 00:56:56.769711  progress  90 % (10 MB)
   68 00:56:57.075389  progress  95 % (10 MB)
   69 00:56:57.374493  progress 100 % (11 MB)
   70 00:56:57.374976  11 MB downloaded in 6.27 s (1.83 MB/s)
   71 00:56:57.375297  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 00:56:57.375770  end: 1.2 download-retry (duration 00:00:06) [common]
   74 00:56:57.375946  start: 1.3 download-retry (timeout 00:09:51) [common]
   75 00:56:57.376113  start: 1.3.1 http-download (timeout 00:09:51) [common]
   76 00:56:57.376409  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
   77 00:56:57.376541  saving as /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/dtb/am335x-boneblack.dtb
   78 00:56:57.376665  total size: 70568 (0 MB)
   79 00:56:57.376795  No compression specified
   80 00:56:57.533428  progress  46 % (0 MB)
   81 00:56:57.536261  progress  92 % (0 MB)
   82 00:56:57.536824  progress 100 % (0 MB)
   83 00:56:57.537055  0 MB downloaded in 0.16 s (0.42 MB/s)
   84 00:56:57.537330  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 00:56:57.537785  end: 1.3 download-retry (duration 00:00:00) [common]
   87 00:56:57.537943  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 00:56:57.538107  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 00:56:57.538362  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 00:56:57.538491  saving as /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/nfsrootfs/full.rootfs.tar
   91 00:56:57.538612  total size: 117747780 (112 MB)
   92 00:56:57.538734  Using unxz to decompress xz
   93 00:56:57.695676  progress   0 % (0 MB)
   94 00:57:00.932042  progress   5 % (5 MB)
   95 00:57:03.843092  progress  10 % (11 MB)
   96 00:57:06.730198  progress  15 % (16 MB)
   97 00:57:09.208448  progress  20 % (22 MB)
   98 00:57:11.046421  progress  25 % (28 MB)
   99 00:57:12.483283  progress  30 % (33 MB)
  100 00:57:13.564897  progress  35 % (39 MB)
  101 00:57:14.473913  progress  40 % (44 MB)
  102 00:57:15.243386  progress  45 % (50 MB)
  103 00:57:16.051534  progress  50 % (56 MB)
  104 00:57:16.883563  progress  55 % (61 MB)
  105 00:57:17.902137  progress  60 % (67 MB)
  106 00:57:18.966677  progress  65 % (73 MB)
  107 00:57:20.196346  progress  70 % (78 MB)
  108 00:57:21.501244  progress  75 % (84 MB)
  109 00:57:22.740921  progress  80 % (89 MB)
  110 00:57:23.955079  progress  85 % (95 MB)
  111 00:57:25.150735  progress  90 % (101 MB)
  112 00:57:26.360896  progress  95 % (106 MB)
  113 00:57:27.568504  progress 100 % (112 MB)
  114 00:57:27.572228  112 MB downloaded in 30.03 s (3.74 MB/s)
  115 00:57:27.573258  end: 1.4.1 http-download (duration 00:00:30) [common]
  117 00:57:27.573864  end: 1.4 download-retry (duration 00:00:30) [common]
  118 00:57:27.574089  start: 1.5 download-retry (timeout 00:09:21) [common]
  119 00:57:27.574272  start: 1.5.1 http-download (timeout 00:09:21) [common]
  120 00:57:27.574753  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/modules.tar.xz
  121 00:57:27.574882  saving as /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/modules/modules.tar
  122 00:57:27.575016  total size: 6906668 (6 MB)
  123 00:57:27.575156  Using unxz to decompress xz
  124 00:57:27.737003  progress   0 % (0 MB)
  125 00:57:27.916615  progress   5 % (0 MB)
  126 00:57:27.943350  progress  10 % (0 MB)
  127 00:57:28.061294  progress  15 % (1 MB)
  128 00:57:28.094643  progress  20 % (1 MB)
  129 00:57:28.199314  progress  25 % (1 MB)
  130 00:57:28.246181  progress  30 % (2 MB)
  131 00:57:28.376778  progress  35 % (2 MB)
  132 00:57:28.502596  progress  40 % (2 MB)
  133 00:57:28.546610  progress  45 % (2 MB)
  134 00:57:28.679892  progress  50 % (3 MB)
  135 00:57:28.711296  progress  55 % (3 MB)
  136 00:57:28.845130  progress  60 % (3 MB)
  137 00:57:28.967063  progress  65 % (4 MB)
  138 00:57:29.008442  progress  70 % (4 MB)
  139 00:57:29.139270  progress  75 % (4 MB)
  140 00:57:29.172182  progress  80 % (5 MB)
  141 00:57:29.301699  progress  85 % (5 MB)
  142 00:57:29.376546  progress  90 % (5 MB)
  143 00:57:29.463037  progress  95 % (6 MB)
  144 00:57:29.577300  progress 100 % (6 MB)
  145 00:57:29.580872  6 MB downloaded in 2.01 s (3.28 MB/s)
  146 00:57:29.581175  end: 1.5.1 http-download (duration 00:00:02) [common]
  148 00:57:29.581630  end: 1.5 download-retry (duration 00:00:02) [common]
  149 00:57:29.581846  start: 1.6 prepare-tftp-overlay (timeout 00:09:19) [common]
  150 00:57:29.582083  start: 1.6.1 extract-nfsrootfs (timeout 00:09:19) [common]
  151 00:57:38.535695  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp
  152 00:57:38.536086  end: 1.6.1 extract-nfsrootfs (duration 00:00:09) [common]
  153 00:57:38.536264  start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
  154 00:57:38.536673  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz
  155 00:57:38.536950  makedir: /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin
  156 00:57:38.537164  makedir: /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/tests
  157 00:57:38.537368  makedir: /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/results
  158 00:57:38.537565  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-add-keys
  159 00:57:38.537864  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-add-sources
  160 00:57:38.538124  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-background-process-start
  161 00:57:38.538383  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-background-process-stop
  162 00:57:38.538661  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-common-functions
  163 00:57:38.538928  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-echo-ipv4
  164 00:57:38.539186  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-install-packages
  165 00:57:38.539441  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-installed-packages
  166 00:57:38.539704  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-os-build
  167 00:57:38.539956  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-probe-channel
  168 00:57:38.540206  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-probe-ip
  169 00:57:38.540454  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-target-ip
  170 00:57:38.540703  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-target-mac
  171 00:57:38.540960  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-target-storage
  172 00:57:38.541214  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-case
  173 00:57:38.541466  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-event
  174 00:57:38.541714  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-feedback
  175 00:57:38.541962  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-raise
  176 00:57:38.542211  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-reference
  177 00:57:38.542461  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-runner
  178 00:57:38.542713  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-set
  179 00:57:38.542967  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-test-shell
  180 00:57:38.543219  Updating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-add-keys (debian)
  181 00:57:38.543540  Updating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-add-sources (debian)
  182 00:57:38.543823  Updating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-install-packages (debian)
  183 00:57:38.544099  Updating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-installed-packages (debian)
  184 00:57:38.544374  Updating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/bin/lava-os-build (debian)
  185 00:57:38.544614  Creating /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/environment
  186 00:57:38.544921  LAVA metadata
  187 00:57:38.545055  - LAVA_JOB_ID=1214554
  188 00:57:38.545181  - LAVA_DISPATCHER_IP=172.16.3.3
  189 00:57:38.545377  start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
  190 00:57:38.545869  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 00:57:38.546035  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
  192 00:57:38.546155  skipped lava-vland-overlay
  193 00:57:38.546302  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 00:57:38.546457  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
  195 00:57:38.546584  skipped lava-multinode-overlay
  196 00:57:38.546731  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 00:57:38.546881  start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
  198 00:57:38.547016  Loading test definitions
  199 00:57:38.547176  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
  200 00:57:38.547305  Using /lava-1214554 at stage 0
  201 00:57:38.547965  uuid=1214554_1.6.2.4.1 testdef=None
  202 00:57:38.548132  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 00:57:38.548290  start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
  204 00:57:38.549166  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 00:57:38.549599  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
  207 00:57:38.550771  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 00:57:38.551206  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
  210 00:57:38.578342  runner path: /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/0/tests/0_timesync-off test_uuid 1214554_1.6.2.4.1
  211 00:57:38.578647  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 00:57:38.579091  start: 1.6.2.4.5 git-repo-action (timeout 00:09:10) [common]
  214 00:57:38.579228  Using /lava-1214554 at stage 0
  215 00:57:38.579420  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 00:57:38.579561  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/0/tests/1_kselftest-dt'
  217 00:57:43.750365  Running '/usr/bin/git checkout kernelci.org
  218 00:57:44.073992  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 00:57:44.074788  uuid=1214554_1.6.2.4.5 testdef=None
  220 00:57:44.074989  end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
  222 00:57:44.075412  start: 1.6.2.4.6 test-overlay (timeout 00:09:04) [common]
  223 00:57:44.076864  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 00:57:44.077304  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:04) [common]
  226 00:57:44.079246  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 00:57:44.079701  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:04) [common]
  229 00:57:44.091758  runner path: /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/0/tests/1_kselftest-dt test_uuid 1214554_1.6.2.4.5
  230 00:57:44.091918  BOARD='beaglebone-black'
  231 00:57:44.092046  BRANCH='mainline'
  232 00:57:44.092168  SKIPFILE='/dev/null'
  233 00:57:44.092290  SKIP_INSTALL='True'
  234 00:57:44.092407  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
  235 00:57:44.092525  TST_CASENAME=''
  236 00:57:44.092641  TST_CMDFILES='dt'
  237 00:57:44.092939  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 00:57:44.093344  Creating lava-test-runner.conf files
  240 00:57:44.093466  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1214554/lava-overlay-ur8s2ccz/lava-1214554/0 for stage 0
  241 00:57:44.093651  - 0_timesync-off
  242 00:57:44.093778  - 1_kselftest-dt
  243 00:57:44.093967  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 00:57:44.094126  start: 1.6.2.5 compress-overlay (timeout 00:09:04) [common]
  245 00:57:55.252259  end: 1.6.2.5 compress-overlay (duration 00:00:11) [common]
  246 00:57:55.252515  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:53) [common]
  247 00:57:55.252684  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 00:57:55.252864  end: 1.6.2 lava-overlay (duration 00:00:17) [common]
  249 00:57:55.253033  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:53) [common]
  250 00:57:55.421058  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 00:57:55.421335  start: 1.6.4 extract-modules (timeout 00:08:53) [common]
  252 00:57:55.421488  extracting modules file /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp
  253 00:57:55.904226  extracting modules file /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214554/extract-overlay-ramdisk-bktnml8w/ramdisk
  254 00:57:56.385627  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 00:57:56.385890  start: 1.6.5 apply-overlay-tftp (timeout 00:08:52) [common]
  256 00:57:56.386047  [common] Applying overlay to NFS
  257 00:57:56.386178  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1214554/compress-overlay-a870ybwm/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp
  258 00:57:58.016888  end: 1.6.5 apply-overlay-tftp (duration 00:00:02) [common]
  259 00:57:58.017143  start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
  260 00:57:58.017315  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
  261 00:57:58.017490  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 00:57:58.017649  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 00:57:58.017813  start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
  264 00:57:58.017974  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 00:57:58.018131  start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
  266 00:57:58.018272  Building ramdisk /var/lib/lava/dispatcher/tmp/1214554/extract-overlay-ramdisk-bktnml8w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1214554/extract-overlay-ramdisk-bktnml8w/ramdisk
  267 00:57:58.343742  >> 78981 blocks

  268 00:58:01.148308  Adding RAMdisk u-boot header.
  269 00:58:01.148850  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1214554/extract-overlay-ramdisk-bktnml8w/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1214554/extract-overlay-ramdisk-bktnml8w/ramdisk.cpio.gz.uboot
  270 00:58:01.406863  output: Image Name:   
  271 00:58:01.407247  output: Created:      Fri Nov  1 00:58:01 2024
  272 00:58:01.407568  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 00:58:01.407875  output: Data Size:    15351737 Bytes = 14991.93 KiB = 14.64 MiB
  274 00:58:01.408171  output: Load Address: 00000000
  275 00:58:01.408461  output: Entry Point:  00000000
  276 00:58:01.408750  output: 
  277 00:58:01.409057  rename /var/lib/lava/dispatcher/tmp/1214554/extract-overlay-ramdisk-bktnml8w/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot
  278 00:58:01.409557  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 00:58:01.409970  end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
  280 00:58:01.410379  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:47) [common]
  281 00:58:01.410695  No LXC device requested
  282 00:58:01.411070  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 00:58:01.411468  start: 1.8 deploy-device-env (timeout 00:08:47) [common]
  284 00:58:01.411846  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 00:58:01.412150  Checking files for TFTP limit of 4294967296 bytes.
  286 00:58:01.413842  end: 1 tftp-deploy (duration 00:01:13) [common]
  287 00:58:01.414267  start: 2 uboot-action (timeout 00:05:00) [common]
  288 00:58:01.414670  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 00:58:01.415050  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 00:58:01.415433  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 00:58:01.415992  substitutions:
  292 00:58:01.416300  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 00:58:01.416600  - {DTB_ADDR}: 0x88000000
  294 00:58:01.416878  - {DTB}: 1214554/tftp-deploy-29f6vuq7/dtb/am335x-boneblack.dtb
  295 00:58:01.416999  - {INITRD}: 1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot
  296 00:58:01.417212  - {KERNEL_ADDR}: 0x82000000
  297 00:58:01.417497  - {KERNEL}: 1214554/tftp-deploy-29f6vuq7/kernel/zImage
  298 00:58:01.417780  - {LAVA_MAC}: None
  299 00:58:01.418075  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp
  300 00:58:01.418360  - {NFS_SERVER_IP}: 172.16.3.3
  301 00:58:01.418636  - {PRESEED_CONFIG}: None
  302 00:58:01.418911  - {PRESEED_LOCAL}: None
  303 00:58:01.419187  - {RAMDISK_ADDR}: 0x83000000
  304 00:58:01.419462  - {RAMDISK}: 1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot
  305 00:58:01.419740  - {ROOT_PART}: None
  306 00:58:01.420012  - {ROOT}: None
  307 00:58:01.420283  - {SERVER_IP}: 172.16.3.3
  308 00:58:01.420554  - {TEE_ADDR}: 0x83000000
  309 00:58:01.420849  - {TEE}: None
  310 00:58:01.420963  Parsed boot commands:
  311 00:58:01.421130  - setenv autoload no
  312 00:58:01.421404  - setenv initrd_high 0xffffffff
  313 00:58:01.421676  - setenv fdt_high 0xffffffff
  314 00:58:01.421945  - dhcp
  315 00:58:01.422214  - setenv serverip 172.16.3.3
  316 00:58:01.422484  - tftp 0x82000000 1214554/tftp-deploy-29f6vuq7/kernel/zImage
  317 00:58:01.422757  - tftp 0x83000000 1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot
  318 00:58:01.423033  - setenv initrd_size ${filesize}
  319 00:58:01.423304  - tftp 0x88000000 1214554/tftp-deploy-29f6vuq7/dtb/am335x-boneblack.dtb
  320 00:58:01.423576  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 00:58:01.423859  - bootz 0x82000000 0x83000000 0x88000000
  322 00:58:01.424217  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 00:58:01.425022  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 00:58:01.425315  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 00:58:01.432806  Setting prompt string to ['lava-test: # ']
  327 00:58:01.433276  end: 2.3 connect-device (duration 00:00:00) [common]
  328 00:58:01.433473  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 00:58:01.433652  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 00:58:01.433825  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 00:58:01.434108  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 00:58:01.874574  >> OFF

  333 00:58:17.166617  >> ON

  334 00:58:17.167629  Returned 0 in 15 seconds
  335 00:58:17.268627  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 00:58:17.269801  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 00:58:17.270251  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 00:58:17.270652  Setting prompt string to ['Hit any key to stop autoboot']
  340 00:58:17.271009  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 00:58:17.271956  Trying 192.168.1.205...
  342 00:58:17.272273  Connected to ts5.
  343 00:58:17.272559  Escape character is '^]'.
  344 00:58:17.272867  
  345 00:58:17.273152  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [] (Debian GNU/Linux)
  346 00:58:17.273443  
  347 00:58:17.774894  
  348 00:58:17.782899  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 00:58:17.783299  Trying to boot from MMC2
  350 00:58:18.294923  
  351 00:58:18.295326  
  352 00:58:18.300927  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 00:58:18.301329  
  354 00:58:18.301658  CPU  : AM335X-GP rev 2.1
  355 00:58:18.307363  Model: TI AM335x BeagleBone Black
  356 00:58:18.307762  DRAM:  512 MiB
  357 00:58:18.387702  WDT:   Started with servicing (60s timeout)
  358 00:58:18.792695  NAND:  0 MiB
  359 00:58:18.803490  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 00:58:18.836964  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 00:58:18.867435  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 00:58:18.925173  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 00:58:18.925658  start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
  364 00:58:18.926031  Setting prompt string to ['=> ']
  365 00:58:18.926400  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:42)
  366 00:58:18.934977  Hit any key to stop autoboot:  2   0 
  367 00:58:18.935749  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 00:58:18.936138  Sending with 10 millisecond of delay
  370 00:58:20.072237  => setenv autoload no
  371 00:58:20.082823  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 00:58:20.085940  setenv autoload no
  373 00:58:20.086525  Sending with 10 millisecond of delay
  375 00:58:21.885756  => setenv initrd_high 0xffffffff
  376 00:58:21.896334  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:40)
  377 00:58:21.896986  setenv initrd_high 0xffffffff
  378 00:58:21.897555  Sending with 10 millisecond of delay
  380 00:58:23.515953  => setenv fdt_high 0xffffffff
  381 00:58:23.526514  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 00:58:23.527146  setenv fdt_high 0xffffffff
  383 00:58:23.527713  Sending with 10 millisecond of delay
  385 00:58:23.819513  => dhcp
  386 00:58:23.830074  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 00:58:23.830934  dhcp
  388 00:58:23.831268  link up on port 0, speed 100, full duplex
  389 00:58:23.831601  BOOTP broadcast 1
  390 00:58:23.878128  DHCP client bound to address 172.16.3.189 (41 ms)
  391 00:58:23.878788  Sending with 10 millisecond of delay
  393 00:58:25.496557  => setenv serverip 172.16.3.3
  394 00:58:25.507223  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 00:58:25.507882  setenv serverip 172.16.3.3
  396 00:58:25.508454  Sending with 10 millisecond of delay
  398 00:58:29.054999  => tftp 0x82000000 1214554/tftp-deploy-29f6vuq7/kernel/zImage
  399 00:58:29.065693  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 00:58:29.066368  tftp 0x82000000 1214554/tftp-deploy-29f6vuq7/kernel/zImage
  401 00:58:29.066691  link up on port 0, speed 100, full duplex
  402 00:58:29.072261  Using ethernet@4a100000 device
  403 00:58:29.077099  TFTP from server 172.16.3.3; our IP address is 172.16.3.189
  404 00:58:29.084926  Filename '1214554/tftp-deploy-29f6vuq7/kernel/zImage'.
  405 00:58:29.085132  Load address: 0x82000000
  406 00:58:31.997732  Loading: *##################################################  11.5 MiB
  407 00:58:31.998209  	 3.9 MiB/s
  408 00:58:31.998517  done
  409 00:58:32.000957  Bytes transferred = 12042752 (b7c200 hex)
  410 00:58:32.001606  Sending with 10 millisecond of delay
  412 00:58:36.514068  => tftp 0x83000000 1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot
  413 00:58:36.524710  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 00:58:36.525372  tftp 0x83000000 1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot
  415 00:58:36.525703  link up on port 0, speed 100, full duplex
  416 00:58:36.531484  Using ethernet@4a100000 device
  417 00:58:36.537397  TFTP from server 172.16.3.3; our IP address is 172.16.3.189
  418 00:58:36.545344  Filename '1214554/tftp-deploy-29f6vuq7/ramdisk/ramdisk.cpio.gz.uboot'.
  419 00:58:36.545547  Load address: 0x83000000
  420 00:58:40.418542  Loading: *##################################################  14.6 MiB
  421 00:58:40.418999  	 3.8 MiB/s
  422 00:58:40.419311  done
  423 00:58:40.422809  Bytes transferred = 15351801 (ea3ff9 hex)
  424 00:58:40.423464  Sending with 10 millisecond of delay
  426 00:58:42.283091  => setenv initrd_size ${filesize}
  427 00:58:42.293673  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:19)
  428 00:58:42.294307  setenv initrd_size ${filesize}
  429 00:58:42.294875  Sending with 10 millisecond of delay
  431 00:58:46.506155  => tftp 0x88000000 1214554/tftp-deploy-29f6vuq7/dtb/am335x-boneblack.dtb
  432 00:58:46.516743  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
  433 00:58:46.517396  tftp 0x88000000 1214554/tftp-deploy-29f6vuq7/dtb/am335x-boneblack.dtb
  434 00:58:46.517728  link up on port 0, speed 100, full duplex
  435 00:58:46.523587  Using ethernet@4a100000 device
  436 00:58:46.529365  TFTP from server 172.16.3.3; our IP address is 172.16.3.189
  437 00:58:46.538109  Filename '1214554/tftp-deploy-29f6vuq7/dtb/am335x-boneblack.dtb'.
  438 00:58:46.538314  Load address: 0x88000000
  439 00:58:46.555491  Loading: *##################################################  68.9 KiB
  440 00:58:46.558873  	 3.4 MiB/s
  441 00:58:46.559262  done
  442 00:58:46.564588  Bytes transferred = 70568 (113a8 hex)
  443 00:58:46.565192  Sending with 10 millisecond of delay
  445 00:58:59.937050  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 00:58:59.947752  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:01)
  447 00:58:59.948406  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 00:58:59.948989  Sending with 10 millisecond of delay
  450 00:59:02.290238  => bootz 0x82000000 0x83000000 0x88000000
  451 00:59:02.300844  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 00:59:02.301290  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:03:59)
  453 00:59:02.302029  bootz 0x82000000 0x83000000 0x88000000
  454 00:59:02.302342  Kernel image @ 0x82000000 [ 0x000000 - 0xb7c200 ]
  455 00:59:02.305039  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 00:59:02.309882     Image Name:   
  457 00:59:02.310270     Created:      2024-11-01   0:58:01 UTC
  458 00:59:02.318494     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 00:59:02.318877     Data Size:    15351737 Bytes = 14.6 MiB
  460 00:59:02.326448     Load Address: 00000000
  461 00:59:02.326829     Entry Point:  00000000
  462 00:59:02.501759     Verifying Checksum ... OK
  463 00:59:02.502147  ## Flattened Device Tree blob at 88000000
  464 00:59:02.509374     Booting using the fdt blob at 0x88000000
  465 00:59:02.512527     Using Device Tree in place at 88000000, end 880143a7
  466 00:59:02.526580  
  467 00:59:02.526977  Starting kernel ...
  468 00:59:02.527286  
  469 00:59:02.527974  end: 2.4.3 bootloader-commands (duration 00:00:44) [common]
  470 00:59:02.528417  start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
  471 00:59:02.528762  Setting prompt string to ['Linux version [0-9]']
  472 00:59:02.529128  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 00:59:02.529473  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 00:59:03.422853  [    0.000000] Booting Linux on physical CPU 0x0
  475 00:59:03.429302  start: 2.4.4.1 login-action (timeout 00:03:58) [common]
  476 00:59:03.429719  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 00:59:03.430063  Setting prompt string to []
  478 00:59:03.430420  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 00:59:03.430755  Using line separator: #'\n'#
  480 00:59:03.431049  No login prompt set.
  481 00:59:03.431358  Parsing kernel messages
  482 00:59:03.431635  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 00:59:03.432158  [login-action] Waiting for messages, (timeout 00:03:58)
  484 00:59:03.442337  [    0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j358357-arm-clang-16-multi-v7-defconfig-5swcm) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Fri Nov  1 00:29:01 UTC 2024
  485 00:59:03.448440  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 00:59:03.458161  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 00:59:03.463143  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 00:59:03.469262  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 00:59:03.475445  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 00:59:03.478883  [    0.000000] Memory policy: Data cache writeback
  491 00:59:03.485108  [    0.000000] efi: UEFI not found.
  492 00:59:03.489365  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 00:59:03.495759  [    0.000000] Zone ranges:
  494 00:59:03.501852  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 00:59:03.506855  [    0.000000]   Normal   empty
  496 00:59:03.507234  [    0.000000]   HighMem  empty
  497 00:59:03.510481  [    0.000000] Movable zone start for each node
  498 00:59:03.515486  [    0.000000] Early memory node ranges
  499 00:59:03.521590  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 00:59:03.529675  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 00:59:03.547844  [    0.000000] CPU: All CPU(s) started in SVC mode.
  502 00:59:03.553260  [    0.000000] AM335X ES2.1 (sgx neon)
  503 00:59:03.564496  [    0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
  504 00:59:03.586637  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  505 00:59:03.591445  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  506 00:59:03.602449  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  507 00:59:03.608682  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  508 00:59:03.615596  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  509 00:59:03.646049  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  510 00:59:03.651982  <6>[    0.000000] trace event string verifier disabled
  511 00:59:03.652372  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  512 00:59:03.659334  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  513 00:59:03.665530  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  514 00:59:03.671697  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  515 00:59:03.682084  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  516 00:59:03.696958  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  517 00:59:03.714727  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  518 00:59:03.721441  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  519 00:59:03.820341  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  520 00:59:03.830011  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  521 00:59:03.841392  <6>[    0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  522 00:59:03.851093  <6>[    0.019179] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  523 00:59:03.859382  <6>[    0.034209] Console: colour dummy device 80x30
  524 00:59:03.865708  Matched prompt #6: WARNING:
  525 00:59:03.866120  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  526 00:59:03.871539  <3>[    0.039108] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  527 00:59:03.873957  <3>[    0.046181] This ensures that you still see kernel messages. Please
  528 00:59:03.880850  <3>[    0.052909] update your kernel commandline.
  529 00:59:03.920647  <6>[    0.057518] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  530 00:59:03.926705  <6>[    0.096185] CPU: Testing write buffer coherency: ok
  531 00:59:03.929164  <6>[    0.101552] CPU0: Spectre v2: using BPIALL workaround
  532 00:59:03.934204  <6>[    0.107016] pid_max: default: 32768 minimum: 301
  533 00:59:03.940338  <6>[    0.112213] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  534 00:59:03.950073  <6>[    0.120039] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  535 00:59:03.956291  <6>[    0.129416] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  536 00:59:03.970803  <6>[    0.136440] Setting up static identity map for 0x80300000 - 0x803000ac
  537 00:59:03.976057  <6>[    0.146158] rcu: Hierarchical SRCU implementation.
  538 00:59:03.980380  <6>[    0.151446] rcu: 	Max phase no-delay instances is 1000.
  539 00:59:03.988698  <6>[    0.162846] EFI services will not be available.
  540 00:59:03.994883  <6>[    0.168144] smp: Bringing up secondary CPUs ...
  541 00:59:04.001058  <6>[    0.173204] smp: Brought up 1 node, 1 CPU
  542 00:59:04.008297  <6>[    0.177605] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  543 00:59:04.014482  <6>[    0.184376] CPU: All CPU(s) started in SVC mode.
  544 00:59:04.032506  <6>[    0.189582] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
  545 00:59:04.032937  <6>[    0.205874] devtmpfs: initialized
  546 00:59:04.055551  <6>[    0.224135] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  547 00:59:04.063964  <6>[    0.232739] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  548 00:59:04.073312  <6>[    0.243200] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  549 00:59:04.083845  <6>[    0.255534] pinctrl core: initialized pinctrl subsystem
  550 00:59:04.093448  <6>[    0.266415] DMI not present or invalid.
  551 00:59:04.102056  <6>[    0.272308] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  552 00:59:04.110367  <6>[    0.281299] DMA: preallocated 256 KiB pool for atomic coherent allocations
  553 00:59:04.126935  <6>[    0.292935] thermal_sys: Registered thermal governor 'step_wise'
  554 00:59:04.127129  <6>[    0.293111] cpuidle: using governor menu
  555 00:59:04.154522  <6>[    0.328525] No ATAGs?
  556 00:59:04.161281  <6>[    0.331264] hw-breakpoint: debug architecture 0x4 unsupported.
  557 00:59:04.170416  <6>[    0.343452] Serial: AMBA PL011 UART driver
  558 00:59:04.201170  <6>[    0.376084] iommu: Default domain type: Translated
  559 00:59:04.210555  <6>[    0.381439] iommu: DMA domain TLB invalidation policy: strict mode
  560 00:59:04.237629  <5>[    0.410527] SCSI subsystem initialized
  561 00:59:04.252349  <6>[    0.420128] usbcore: registered new interface driver usbfs
  562 00:59:04.258570  <6>[    0.426091] usbcore: registered new interface driver hub
  563 00:59:04.258954  <6>[    0.431944] usbcore: registered new device driver usb
  564 00:59:04.265994  <6>[    0.438496] pps_core: LinuxPPS API ver. 1 registered
  565 00:59:04.278346  <6>[    0.443934] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  566 00:59:04.281798  <6>[    0.453654] PTP clock support registered
  567 00:59:04.285079  <6>[    0.458110] EDAC MC: Ver: 3.0.0
  568 00:59:04.337585  <6>[    0.509936] scmi_core: SCMI protocol bus registered
  569 00:59:04.343380  <6>[    0.518120] vgaarb: loaded
  570 00:59:04.357257  <6>[    0.530997] clocksource: Switched to clocksource dmtimer
  571 00:59:04.395357  <6>[    0.569657] NET: Registered PF_INET protocol family
  572 00:59:04.408876  <6>[    0.575376] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  573 00:59:04.415107  <6>[    0.584388] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  574 00:59:04.426042  <6>[    0.593317] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  575 00:59:04.432126  <6>[    0.601579] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  576 00:59:04.443122  <6>[    0.609849] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  577 00:59:04.449226  <6>[    0.617576] TCP: Hash tables configured (established 4096 bind 4096)
  578 00:59:04.455337  <6>[    0.624496] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  579 00:59:04.460363  <6>[    0.631536] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  580 00:59:04.468367  <6>[    0.639116] NET: Registered PF_UNIX/PF_LOCAL protocol family
  581 00:59:04.549292  <6>[    0.718333] RPC: Registered named UNIX socket transport module.
  582 00:59:04.549677  <6>[    0.724786] RPC: Registered udp transport module.
  583 00:59:04.555324  <6>[    0.729893] RPC: Registered tcp transport module.
  584 00:59:04.564044  <6>[    0.735016] RPC: Registered tcp-with-tls transport module.
  585 00:59:04.570231  <6>[    0.740929] RPC: Registered tcp NFSv4.1 backchannel transport module.
  586 00:59:04.577247  <6>[    0.747853] PCI: CLS 0 bytes, default 64
  587 00:59:04.579718  <5>[    0.753737] Initialise system trusted keyrings
  588 00:59:04.603845  <6>[    0.774866] Trying to unpack rootfs image as initramfs...
  589 00:59:04.673333  <6>[    0.841473] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  590 00:59:04.677662  <6>[    0.848982] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  591 00:59:04.717850  <5>[    0.892362] NFS: Registering the id_resolver key type
  592 00:59:04.723910  <5>[    0.897955] Key type id_resolver registered
  593 00:59:04.730029  <5>[    0.902643] Key type id_legacy registered
  594 00:59:04.737303  <6>[    0.907090] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  595 00:59:04.745358  <6>[    0.914294] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  596 00:59:04.826570  <5>[    1.001592] Key type asymmetric registered
  597 00:59:04.832735  <5>[    1.006121] Asymmetric key parser 'x509' registered
  598 00:59:04.842340  <6>[    1.011621] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  599 00:59:04.847355  <6>[    1.019510] io scheduler mq-deadline registered
  600 00:59:04.855384  <6>[    1.024496] io scheduler kyber registered
  601 00:59:04.855779  <6>[    1.028949] io scheduler bfq registered
  602 00:59:04.963135  <6>[    1.133143] ledtrig-cpu: registered to indicate activity on CPUs
  603 00:59:05.302134  <6>[    1.472181] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  604 00:59:05.342339  <6>[    1.516245] msm_serial: driver initialized
  605 00:59:05.348326  <6>[    1.521243] SuperH (H)SCI(F) driver initialized
  606 00:59:05.354533  <6>[    1.526410] STMicroelectronics ASC driver initialized
  607 00:59:05.360174  <6>[    1.532088] STM32 USART driver initialized
  608 00:59:05.481189  <6>[    1.654525] brd: module loaded
  609 00:59:05.524010  <6>[    1.697619] loop: module loaded
  610 00:59:05.555765  <6>[    1.728777] CAN device driver interface
  611 00:59:05.561885  <6>[    1.733995] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  612 00:59:05.567851  <6>[    1.741043] e1000e: Intel(R) PRO/1000 Network Driver
  613 00:59:05.574315  <6>[    1.746434] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  614 00:59:05.580322  <6>[    1.752868] igb: Intel(R) Gigabit Ethernet Network Driver
  615 00:59:05.587193  <6>[    1.758690] igb: Copyright (c) 2007-2014 Intel Corporation.
  616 00:59:05.599782  <6>[    1.768079] pegasus: Pegasus/Pegasus II USB Ethernet driver
  617 00:59:05.605906  <6>[    1.774257] usbcore: registered new interface driver pegasus
  618 00:59:05.608210  <6>[    1.780388] usbcore: registered new interface driver asix
  619 00:59:05.613335  <6>[    1.786275] usbcore: registered new interface driver ax88179_178a
  620 00:59:05.624326  <6>[    1.792889] usbcore: registered new interface driver cdc_ether
  621 00:59:05.629047  <6>[    1.799189] usbcore: registered new interface driver smsc75xx
  622 00:59:05.633187  <6>[    1.805434] usbcore: registered new interface driver smsc95xx
  623 00:59:05.639286  <6>[    1.811673] usbcore: registered new interface driver net1080
  624 00:59:05.696890  <6>[    1.817792] usbcore: registered new interface driver cdc_subset
  625 00:59:05.697266  <6>[    1.824206] usbcore: registered new interface driver zaurus
  626 00:59:05.697577  <6>[    1.830250] usbcore: registered new interface driver cdc_ncm
  627 00:59:05.700191  <6>[    1.839900] usbcore: registered new interface driver usb-storage
  628 00:59:05.972322  <6>[    2.144081] i2c_dev: i2c /dev entries driver
  629 00:59:06.031295  <5>[    2.198356] cpuidle: enable-method property 'ti,am3352' found operations
  630 00:59:06.037422  <6>[    2.208071] sdhci: Secure Digital Host Controller Interface driver
  631 00:59:06.045944  <6>[    2.214872] sdhci: Copyright(c) Pierre Ossman
  632 00:59:06.052044  <6>[    2.221536] Synopsys Designware Multimedia Card Interface Driver
  633 00:59:06.058860  <6>[    2.229469] sdhci-pltfm: SDHCI platform and OF driver helper
  634 00:59:06.189262  <6>[    2.356969] usbcore: registered new interface driver usbhid
  635 00:59:06.189454  <6>[    2.363138] usbhid: USB HID core driver
  636 00:59:06.226161  <6>[    2.397973] NET: Registered PF_INET6 protocol family
  637 00:59:06.268427  <6>[    2.442681] Segment Routing with IPv6
  638 00:59:06.274539  <6>[    2.446832] In-situ OAM (IOAM) with IPv6
  639 00:59:06.280665  <6>[    2.451360] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  640 00:59:06.286835  <6>[    2.458658] NET: Registered PF_PACKET protocol family
  641 00:59:06.292938  <6>[    2.464232] can: controller area network core
  642 00:59:06.299054  <6>[    2.469061] NET: Registered PF_CAN protocol family
  643 00:59:06.299215  <6>[    2.474290] can: raw protocol
  644 00:59:06.303872  <6>[    2.477616] can: broadcast manager protocol
  645 00:59:06.310062  <6>[    2.482210] can: netlink gateway - max_hops=1
  646 00:59:06.315056  <5>[    2.487713] Key type dns_resolver registered
  647 00:59:06.321030  <6>[    2.492795] ThumbEE CPU extension supported.
  648 00:59:06.324583  <5>[    2.497489] Registering SWP/SWPB emulation handler
  649 00:59:06.332849  <3>[    2.503193] omap_voltage_late_init: Voltage driver support not added
  650 00:59:06.539500  <5>[    2.712088] Loading compiled-in X.509 certificates
  651 00:59:06.670052  <6>[    2.831872] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  652 00:59:06.678085  <6>[    2.848534] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  653 00:59:06.705033  <3>[    2.872823] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  654 00:59:06.903070  <3>[    3.071372] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  655 00:59:07.099374  <6>[    3.272069] OMAP GPIO hardware version 0.1
  656 00:59:07.120521  <6>[    3.291129] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  657 00:59:07.192287  <4>[    3.362638] at24 2-0054: supply vcc not found, using dummy regulator
  658 00:59:07.225158  <4>[    3.395980] at24 2-0055: supply vcc not found, using dummy regulator
  659 00:59:07.264654  <4>[    3.434746] at24 2-0056: supply vcc not found, using dummy regulator
  660 00:59:07.305858  <4>[    3.476196] at24 2-0057: supply vcc not found, using dummy regulator
  661 00:59:07.345051  <6>[    3.516012] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  662 00:59:07.386419  <3>[    3.554112] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  663 00:59:07.411604  <6>[    3.575374] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  664 00:59:07.434953  <4>[    3.602268] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  665 00:59:07.441742  <4>[    3.611245] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  666 00:59:07.502316  <6>[    3.674320] Freeing initrd memory: 14992K
  667 00:59:07.509209  <6>[    3.680204] omap_rng 48310000.rng: Random Number Generator ver. 20
  668 00:59:07.533199  <5>[    3.706978] random: crng init done
  669 00:59:07.581976  <6>[    3.750997] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  670 00:59:07.635840  <6>[    3.803471] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  671 00:59:07.640849  <6>[    3.813804] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  672 00:59:07.654215  <6>[    3.821141] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  673 00:59:07.660315  <6>[    3.828618] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  674 00:59:07.668947  <6>[    3.836755] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  675 00:59:07.681321  <6>[    3.848399] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  676 00:59:07.690418  <5>[    3.857529] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  677 00:59:07.718574  <3>[    3.887837] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  678 00:59:07.725311  <6>[    3.896435] edma 49000000.dma: TI EDMA DMA engine driver
  679 00:59:07.796306  <3>[    3.965122] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  680 00:59:07.811498  <6>[    3.979592] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  681 00:59:07.825199  <3>[    3.996900] l3-aon-clkctrl:0000:0: failed to disable
  682 00:59:07.882198  <6>[    4.049974] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  683 00:59:07.887019  <6>[    4.059503] printk: legacy console [ttyS0] enabled
  684 00:59:07.890521  <6>[    4.059503] printk: legacy console [ttyS0] enabled
  685 00:59:07.895557  <6>[    4.069837] printk: legacy bootconsole [omap8250] disabled
  686 00:59:07.904823  <6>[    4.069837] printk: legacy bootconsole [omap8250] disabled
  687 00:59:07.934281  <4>[    4.101827] tps65217-pmic: Failed to locate of_node [id: -1]
  688 00:59:07.937547  <4>[    4.109231] tps65217-bl: Failed to locate of_node [id: -1]
  689 00:59:07.954254  <6>[    4.129297] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  690 00:59:07.973986  <6>[    4.136302] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  691 00:59:07.985183  <6>[    4.149997] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  692 00:59:07.989649  <6>[    4.161888] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  693 00:59:08.012564  <6>[    4.181928] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  694 00:59:08.018629  <6>[    4.191099] sdhci-omap 48060000.mmc: Got CD GPIO
  695 00:59:08.026663  <4>[    4.196241] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  696 00:59:08.041314  <4>[    4.210017] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  697 00:59:08.047321  <4>[    4.218802] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  698 00:59:08.057926  <4>[    4.227419] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  699 00:59:08.158048  <6>[    4.328005] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  700 00:59:08.197335  <6>[    4.366721] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  701 00:59:08.246855  <6>[    4.414372] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  702 00:59:08.252435  <6>[    4.423423] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  703 00:59:08.317865  <6>[    4.481651] mmc1: new high speed MMC card at address 0001
  704 00:59:08.318250  <6>[    4.489758] mmcblk1: mmc1:0001 M62704 3.56 GiB
  705 00:59:08.328834  <6>[    4.501750]  mmcblk1: p1
  706 00:59:08.342098  <6>[    4.506135] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  707 00:59:08.346540  <6>[    4.518852] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  708 00:59:08.359318  <6>[    4.530319] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  709 00:59:08.373270  <6>[    4.543553] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  710 00:59:10.503314  <6>[    6.672054] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  711 00:59:10.627030  <5>[    6.701023] Sending DHCP requests ., OK
  712 00:59:10.637977  <6>[    6.805460] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.189
  713 00:59:10.638359  <6>[    6.813547] IP-Config: Complete:
  714 00:59:10.649081  <6>[    6.817086]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.189, mask=255.255.255.0, gw=172.16.3.3
  715 00:59:10.658881  <6>[    6.827530]      host=172.16.3.189, domain=denx.de, nis-domain=(none)
  716 00:59:10.665252  <6>[    6.834404]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  717 00:59:10.671504  <6>[    6.834444]      nameserver0=172.16.3.3
  718 00:59:10.671885  <6>[    6.845760]      ntpserver0=172.16.3.3
  719 00:59:10.677735  <6>[    6.851285] clk: Disabling unused clocks
  720 00:59:10.683297  <6>[    6.855905] PM: genpd: Disabling unused power domains
  721 00:59:10.701474  <6>[    6.872542] Freeing unused kernel image (initmem) memory: 2048K
  722 00:59:10.708297  <6>[    6.882406] Run /init as init process
  723 00:59:10.734395  Loading, please wait...
  724 00:59:10.811185  Starting systemd-udevd version 252.22-1~deb12u1
  725 00:59:13.917726  <4>[   10.085624] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  726 00:59:14.034342  <4>[   10.202611] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  727 00:59:14.227716  <6>[   10.402974] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  728 00:59:14.239407  <6>[   10.408651] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  729 00:59:14.458573  <6>[   10.632590] hub 1-0:1.0: USB hub found
  730 00:59:14.517289  <6>[   10.691346] hub 1-0:1.0: 1 port detected
  731 00:59:14.581411  <6>[   10.754494] tda998x 0-0070: found TDA19988
  732 00:59:17.404262  Begin: Loading essential drivers ... done.
  733 00:59:17.410260  Begin: Running /scripts/init-premount ... done.
  734 00:59:17.416432  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  735 00:59:17.429535  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  736 00:59:17.429923  Device /sys/class/net/eth0 found
  737 00:59:17.430233  done.
  738 00:59:17.523915  Begin: Waiting up to 180 secs for any network device to become available ... done.
  739 00:59:17.609517  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  740 00:59:17.648418  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  741 00:59:17.659664   address: 172.16.3.189     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  742 00:59:17.663275   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  743 00:59:17.668448   domain : denx.de                                                         
  744 00:59:17.674709   rootserver: 172.16.3.33 rootpath: 
  745 00:59:17.679056   filename  : this-host-is-not-configured.kpxe
  746 00:59:17.721526  done.
  747 00:59:17.736474  Begin: Running /scripts/nfs-bottom ... done.
  748 00:59:17.804487  Begin: Running /scripts/init-bottom ... done.
  749 00:59:19.307642  <30>[   15.478480] systemd[1]: System time before build time, advancing clock.
  750 00:59:19.549346  <30>[   15.694506] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  751 00:59:19.558771  <30>[   15.731382] systemd[1]: Detected architecture arm.
  752 00:59:19.571305  
  753 00:59:19.571693  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  754 00:59:19.572005  
  755 00:59:19.600972  <30>[   15.771752] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  756 00:59:21.921098  <30>[   18.090875] systemd[1]: Queued start job for default target graphical.target.
  757 00:59:21.937010  <30>[   18.106201] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  758 00:59:21.945168  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  759 00:59:21.975533  <30>[   18.144472] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  760 00:59:21.983887  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  761 00:59:22.005838  <30>[   18.174352] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  762 00:59:22.016297  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  763 00:59:22.034480  <30>[   18.203228] systemd[1]: Created slice user.slice - User and Session Slice.
  764 00:59:22.041210  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  765 00:59:22.069520  <30>[   18.232351] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  766 00:59:22.076297  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  767 00:59:22.094306  <30>[   18.262240] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  768 00:59:22.104810  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  769 00:59:22.137188  <30>[   18.292054] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  770 00:59:22.142308  <30>[   18.312683] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  771 00:59:22.150190           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  772 00:59:22.172189  <30>[   18.341493] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  773 00:59:22.180350  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  774 00:59:22.203580  <30>[   18.371933] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  775 00:59:22.210763  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  776 00:59:22.232675  <30>[   18.402071] systemd[1]: Reached target paths.target - Path Units.
  777 00:59:22.238301  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  778 00:59:22.262679  <30>[   18.431740] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  779 00:59:22.269328  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  780 00:59:22.292692  <30>[   18.461610] systemd[1]: Reached target slices.target - Slice Units.
  781 00:59:22.298129  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  782 00:59:22.322413  <30>[   18.491801] systemd[1]: Reached target swap.target - Swaps.
  783 00:59:22.326751  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  784 00:59:22.353194  <30>[   18.521887] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  785 00:59:22.361507  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  786 00:59:22.383435  <30>[   18.552683] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  787 00:59:22.391920  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  788 00:59:22.478227  <30>[   18.642938] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  789 00:59:22.492060  <30>[   18.660756] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  790 00:59:22.500403  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  791 00:59:22.524675  <30>[   18.692777] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  792 00:59:22.531353  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  793 00:59:22.556683  <30>[   18.724808] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  794 00:59:22.564046  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  795 00:59:22.588186  <30>[   18.756553] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  796 00:59:22.594284  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  797 00:59:22.626926  <30>[   18.794451] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  798 00:59:22.634162  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  799 00:59:22.660149  <30>[   18.822657] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  800 00:59:22.677050  <30>[   18.839171] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  801 00:59:22.726973  <30>[   18.896426] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  802 00:59:22.754667           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  803 00:59:22.802614  <30>[   18.972156] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  804 00:59:22.841956           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  805 00:59:22.954313  <30>[   19.122697] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  806 00:59:22.988302           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  807 00:59:23.044868  <30>[   19.213938] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  808 00:59:23.065178           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  809 00:59:23.122519  <30>[   19.292332] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  810 00:59:23.139700           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  811 00:59:23.162323  <30>[   19.332474] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  812 00:59:23.190911           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  813 00:59:23.244383  <30>[   19.412276] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  814 00:59:23.262457           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  815 00:59:23.298629  <30>[   19.468948] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  816 00:59:23.319043           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  817 00:59:23.375284  <30>[   19.544916] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  818 00:59:23.392420           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  819 00:59:23.420548  <28>[   19.583483] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  820 00:59:23.428481  <28>[   19.598136] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  821 00:59:23.482179  <30>[   19.652053] systemd[1]: Starting systemd-journald.service - Journal Service...
  822 00:59:23.490136           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  823 00:59:23.566490  <30>[   19.736226] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  824 00:59:23.585997           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  825 00:59:23.634393  <30>[   19.804215] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  826 00:59:23.678755           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  827 00:59:23.749018  <30>[   19.916904] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  828 00:59:23.786184           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  829 00:59:23.863732  <30>[   20.032641] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  830 00:59:23.911412           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  831 00:59:23.976079  <30>[   20.146526] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  832 00:59:24.033585  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  833 00:59:24.063486  <30>[   20.233436] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  834 00:59:24.093200  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  835 00:59:24.120258  <30>[   20.288606] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  836 00:59:24.147879  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  837 00:59:24.304231  <30>[   20.475531] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  838 00:59:24.343602  <30>[   20.512910] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  839 00:59:24.372427  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  840 00:59:24.392573  <30>[   20.563848] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  841 00:59:24.432571  <30>[   20.601548] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  842 00:59:24.440532  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  843 00:59:24.463572  <30>[   20.632791] systemd[1]: Started systemd-journald.service - Journal Service.
  844 00:59:24.470298  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  845 00:59:24.504599  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  846 00:59:24.527240  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  847 00:59:24.567746  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  848 00:59:24.605047  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  849 00:59:24.625599  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  850 00:59:24.652486  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  851 00:59:24.674949  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  852 00:59:24.707106  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  853 00:59:24.761175           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  854 00:59:24.802474           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  855 00:59:24.882999           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  856 00:59:24.967593           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  857 00:59:25.045992           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  858 00:59:25.204639  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  859 00:59:25.236600  <46>[   21.406728] systemd-journald[162]: Received client request to flush runtime journal.
  860 00:59:25.415269  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  861 00:59:25.445023  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  862 00:59:25.483228  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  863 00:59:25.544553           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  864 00:59:27.022574  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  865 00:59:27.043196  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  866 00:59:27.062514  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  867 00:59:27.132427           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  868 00:59:27.186623  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  869 00:59:27.242794           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  870 00:59:28.119425  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  871 00:59:28.198727           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  872 00:59:29.208093  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  873 00:59:30.305823  <5>[   26.475654] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  874 00:59:30.719983  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  875 00:59:31.409199  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  876 00:59:31.570632  <5>[   27.743358] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  877 00:59:31.688948  <5>[   27.859549] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  878 00:59:31.701675  <4>[   27.871760] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  879 00:59:31.707371  <6>[   27.880739] cfg80211: failed to load regulatory.db
  880 00:59:32.948819  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  881 00:59:40.595296  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  882 00:59:40.623227  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  883 00:59:40.646798  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  884 00:59:40.711387           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  885 00:59:40.762302           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  886 00:59:40.827051           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  887 00:59:40.871318           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  888 00:59:41.125988           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  889 00:59:41.207506           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  890 00:59:41.260598  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  891 00:59:41.303099  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  892 00:59:41.330941  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  893 00:59:41.361843  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  894 00:59:41.507744  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  895 00:59:41.983027  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  896 00:59:42.003253  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  897 00:59:42.023614  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  898 00:59:42.048298  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  899 00:59:42.172227  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  900 00:59:42.318232  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  901 00:59:42.344066  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  902 00:59:42.429865  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  903 00:59:42.523114  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  904 00:59:42.544391  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  905 00:59:42.578633  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  906 00:59:42.603232  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  907 00:59:42.624546  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  908 00:59:42.706189           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  909 00:59:42.755067           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  910 00:59:42.986101           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  911 00:59:43.207038           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  912 00:59:43.247210           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  913 00:59:43.275144  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  914 00:59:43.401951  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  915 00:59:43.423276  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  916 00:59:43.680993           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  917 00:59:43.705595  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  918 00:59:43.772130  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  919 00:59:43.872643  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  920 00:59:43.887655  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  921 00:59:43.947097  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  922 00:59:44.352574  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  923 00:59:44.489061  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  924 00:59:44.541136  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  925 00:59:44.568757  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  926 00:59:44.647192           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  927 00:59:44.933769  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  928 00:59:45.281120  
  929 00:59:45.286575  Debian GNU/Linux 12 debian-boodebian-bookworm-armhf login: root (automatic login)
  930 00:59:45.286961  
  931 00:59:45.661257  Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Fri Nov  1 00:29:01 UTC 2024 armv7l
  932 00:59:45.661667  
  933 00:59:45.664907  The programs included with the Debian GNU/Linux system are free software;
  934 00:59:45.671025  the exact distribution terms for each program are described in the
  935 00:59:45.674761  individual files in /usr/share/doc/*/copyright.
  936 00:59:45.675143  
  937 00:59:45.680927  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  938 00:59:45.685227  permitted by applicable law.
  939 00:59:50.533128  Unable to match end of the kernel message
  941 00:59:50.534144  Setting prompt string to ['/ #']
  942 00:59:50.534567  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  944 00:59:50.535506  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  945 00:59:50.535922  start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
  946 00:59:50.536277  Setting prompt string to ['/ #']
  947 00:59:50.536573  Forcing a shell prompt, looking for ['/ #']
  949 00:59:50.587345  / # 
  950 00:59:50.587865  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  951 00:59:50.588234  Waiting using forced prompt support (timeout 00:02:30)
  952 00:59:50.594855  
  953 00:59:50.600774  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  954 00:59:50.601269  start: 2.4.6 export-device-env (timeout 00:03:11) [common]
  955 00:59:50.601688  Sending with 10 millisecond of delay
  957 00:59:55.658895  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp'
  958 00:59:55.669651  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214554/extract-nfsrootfs-sp91tcrp'
  959 00:59:55.673112  Sending with 10 millisecond of delay
  961 00:59:57.714614  / # export NFS_SERVER_IP='172.16.3.3'
  962 00:59:57.725295  export NFS_SERVER_IP='172.16.3.3'
  963 00:59:57.728500  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  964 00:59:57.729013  end: 2.4 uboot-commands (duration 00:01:56) [common]
  965 00:59:57.729460  end: 2 uboot-action (duration 00:01:56) [common]
  966 00:59:57.729895  start: 3 lava-test-retry (timeout 00:06:51) [common]
  967 00:59:57.730329  start: 3.1 lava-test-shell (timeout 00:06:51) [common]
  968 00:59:57.730670  Using namespace: common
  970 00:59:57.831633  / # #
  971 00:59:57.832135  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  972 00:59:57.839487  #
  973 00:59:57.845358  Using /lava-1214554
  975 00:59:57.946416  / # export SHELL=/bin/bash
  976 00:59:57.953506  export SHELL=/bin/bash
  978 00:59:58.061136  / # . /lava-1214554/environment
  979 00:59:58.068597  . /lava-1214554/environment
  981 00:59:58.182463  / # /lava-1214554/bin/lava-test-runner /lava-1214554/0
  982 00:59:58.182976  Test shell timeout: 10s (minimum of the action and connection timeout)
  983 00:59:58.189361  /lava-1214554/bin/lava-test-runner /lava-1214554/0
  984 00:59:58.777231  + export TESTRUN_ID=0_timesync-off
  985 00:59:58.785164  + TESTRUN_ID=0_timesync-off
  986 00:59:58.785548  + cd /lava-1214554/0/tests/0_timesync-off
  987 00:59:58.785864  ++ cat uuid
  988 00:59:58.809521  + UUID=1214554_1.6.2.4.1
  989 00:59:58.809928  + set +x
  990 00:59:58.815612  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1214554_1.6.2.4.1>
  991 00:59:58.816267  Received signal: <STARTRUN> 0_timesync-off 1214554_1.6.2.4.1
  992 00:59:58.816610  Starting test lava.0_timesync-off (1214554_1.6.2.4.1)
  993 00:59:58.817027  Skipping test definition patterns.
  994 00:59:58.818822  + systemctl stop systemd-timesyncd
  995 00:59:59.126726  + set +x
  996 00:59:59.127344  Received signal: <ENDRUN> 0_timesync-off 1214554_1.6.2.4.1
  997 00:59:59.127717  Ending use of test pattern.
  998 00:59:59.128017  Ending test lava.0_timesync-off (1214554_1.6.2.4.1), duration 0.31
 1000 00:59:59.129944  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1214554_1.6.2.4.1>
 1001 00:59:59.441220  + export TESTRUN_ID=1_kselftest-dt
 1002 00:59:59.449336  + TESTRUN_ID=1_kselftest-dt
 1003 00:59:59.449743  + cd /lava-1214554/0/tests/1_kselftest-dt
 1004 00:59:59.450059  ++ cat uuid
 1005 00:59:59.471890  + UUID=1214554_1.6.2.4.5
 1006 00:59:59.472276  + set +x
 1007 00:59:59.476741  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1214554_1.6.2.4.5>
 1008 00:59:59.477196  + cd ./automated/linux/kselftest/
 1009 00:59:59.477817  Received signal: <STARTRUN> 1_kselftest-dt 1214554_1.6.2.4.5
 1010 00:59:59.478196  Starting test lava.1_kselftest-dt (1214554_1.6.2.4.5)
 1011 00:59:59.478636  Skipping test definition patterns.
 1012 00:59:59.506931  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1013 00:59:59.675451  INFO: install_deps skipped
 1014 01:00:00.314881  --2024-01-26 21:49:16--  http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
 1015 01:00:00.353758  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1016 01:00:00.510141  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1017 01:00:00.662250  HTTP request sent, awaiting response... 200 OK
 1018 01:00:00.662631  Length: 2730528 (2.6M) [application/octet-stream]
 1019 01:00:00.668316  Saving to: 'kselftest_armhf.tar.gz'
 1020 01:00:00.668693  
 1021 01:00:02.703444  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  49.92K   169KB/s               kselftest_armhf.tar   8%[>                   ] 214.89K   360KB/s               kselftest_armhf.tar  24%[===>                ] 656.01K   713KB/s               kselftest_armhf.tar  50%[=========>          ]   1.33M  1.10MB/s               kselftest_armhf.tar  66%[============>       ]   1.74M  1.15MB/s               kselftest_armhf.tar  83%[===============>    ]   2.17M  1.24MB/s               kselftest_armhf.tar  91%[=================>  ]   2.39M  1.23MB/s               kselftest_armhf.tar 100%[===================>]   2.60M  1.28MB/s    in 2.0s    
 1022 01:00:02.703901  
 1023 01:00:03.069750  2024-01-26 21:49:19 (1.28 MB/s) - 'kselftest_armhf.tar.gz' saved [2730528/2730528]
 1024 01:00:03.070173  
 1025 01:00:03.357287  tar: ./proc/fd-003-kthread: time stamp 2024-11-01 00:45:44 is 24116183.951182495 s in the future
 1026 01:00:03.471662  tar: ./proc/config: time stamp 2024-10-27 19:28:30 is 23751549.834285037 s in the future
 1027 01:00:03.606029  tar: ./proc/proc-tid0: time stamp 2024-11-01 00:45:45 is 24116184.70063712 s in the future
 1028 01:00:03.755461  tar: ./proc/proc-loadavg-001: time stamp 2024-11-01 00:45:44 is 24116183.552293745 s in the future
 1029 01:00:03.914209  tar: ./proc/proc-self-syscall: time stamp 2024-11-01 00:45:45 is 24116184.39244762 s in the future
 1030 01:00:04.038088  tar: ./proc/setns-dcache: time stamp 2024-11-01 00:45:46 is 24116185.26877712 s in the future
 1031 01:00:04.148088  tar: ./proc/setns-sysvipc: time stamp 2024-11-01 00:45:46 is 24116185.158548037 s in the future
 1032 01:00:04.280525  tar: ./proc/proc-uptime-001: time stamp 2024-11-01 00:45:46 is 24116185.026739412 s in the future
 1033 01:00:04.436261  tar: ./proc/fd-001-lookup: time stamp 2024-11-01 00:45:44 is 24116182.87064837 s in the future
 1034 01:00:04.564373  tar: ./proc/proc-uptime-002: time stamp 2024-11-01 00:45:46 is 24116184.743482328 s in the future
 1035 01:00:04.691501  tar: ./proc/fd-002-posix-eq: time stamp 2024-11-01 00:45:44 is 24116182.616314828 s in the future
 1036 01:00:04.815266  tar: ./proc/thread-self: time stamp 2024-11-01 00:45:46 is 24116184.49131987 s in the future
 1037 01:00:04.954632  tar: ./proc/read: time stamp 2024-11-01 00:45:46 is 24116184.35143987 s in the future
 1038 01:00:05.110916  tar: ./proc/self: time stamp 2024-11-01 00:45:46 is 24116184.194847995 s in the future
 1039 01:00:05.233889  tar: ./proc/proc-pid-vm: time stamp 2024-11-01 00:45:44 is 24116182.074006703 s in the future
 1040 01:00:05.382348  tar: ./proc/proc-multiple-procfs: time stamp 2024-11-01 00:45:46 is 24116183.925817287 s in the future
 1041 01:00:05.531629  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-11-01 00:45:45 is 24116182.776312412 s in the future
 1042 01:00:05.675552  tar: ./proc/proc-subset-pid: time stamp 2024-11-01 00:45:45 is 24116182.632365912 s in the future
 1043 01:00:05.859737  tar: ./proc/proc-self-map-files-001: time stamp 2024-11-01 00:45:45 is 24116182.447952787 s in the future
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 1200 01:00:27.862147  tar: ./lkdtm/REFCOUNT_DEC_ZERO.sh: time stamp 2024-11-01 00:45:09 is 24116124.444639867 s in the future
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 1202 01:00:28.120744  tar: ./lkdtm/REFCOUNT_DEC_SATURATED.sh: time stamp 2024-11-01 00:45:09 is 24116124.186051576 s in the future
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 1206 01:00:28.627738  tar: ./lkdtm/EXEC_STACK.sh: time stamp 2024-11-01 00:45:09 is 24116123.677929159 s in the future
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 1214 01:00:30.487949  tar: ./lkdtm/REFCOUNT_ADD_NOT_ZERO_SATURATED.sh: time stamp 2024-11-01 00:45:09 is 24116121.819785784 s in the future
 1215 01:00:30.605653  tar: ./lkdtm/WRITE_BUDDY_AFTER_FREE.sh: time stamp 2024-11-01 00:45:09 is 24116121.700450242 s in the future
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 1227 01:00:32.208875  tar: ./lkdtm/READ_BUDDY_AFTER_FREE.sh: time stamp 2024-11-01 00:45:09 is 24116120.097740408 s in the future
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 1245 01:00:35.306572  tar: ./lkdtm/USERCOPY_SLAB_WHITELIST_FROM.sh: time stamp 2024-11-01 00:45:09 is 24116117.0003052 s in the future
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 1247 01:00:35.587274  tar: ./lkdtm/USERCOPY_SLAB_SIZE_FROM.sh: time stamp 2024-11-01 00:45:09 is 24116116.719948033 s in the future
 1248 01:00:35.736572  tar: ./lkdtm/EXEC_KMALLOC.sh: time stamp 2024-11-01 00:45:09 is 24116116.5692052 s in the future
 1249 01:00:35.880596  tar: ./lkdtm/SMP_CALL_LOCKUP.sh: time stamp 2024-11-01 00:45:09 is 24116116.424882658 s in the future
 1250 01:00:36.017103  tar: ./lkdtm/REFCOUNT_TIMING.sh: time stamp 2024-11-01 00:45:09 is 24116116.288998616 s in the future
 1251 01:00:36.152418  tar: ./lkdtm/CORRUPT_LIST_ADD.sh: time stamp 2024-11-01 00:45:09 is 24116116.152575616 s in the future
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 1255 01:00:36.692410  tar: ./lkdtm/REFCOUNT_DEC_AND_TEST_SATURATED.sh: time stamp 2024-11-01 00:45:09 is 24116115.615027908 s in the future
 1256 01:00:36.846001  tar: ./lkdtm/DOUBLE_FAULT.sh: time stamp 2024-11-01 00:45:09 is 24116115.459941491 s in the future
 1257 01:00:36.983472  tar: ./lkdtm/WRITE_KERN.sh: time stamp 2024-11-01 00:45:09 is 24116115.321215783 s in the future
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 1261 01:00:37.517418  tar: ./lkdtm/USERCOPY_SLAB_WHITELIST_TO.sh: time stamp 2024-11-01 00:45:09 is 24116114.789788241 s in the future
 1262 01:00:37.665570  tar: ./lkdtm/HARDLOCKUP.sh: time stamp 2024-11-01 00:45:09 is 24116114.639204241 s in the future
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 1269 01:00:38.610610  tar: ./lkdtm/WRITE_RO.sh: time stamp 2024-11-01 00:45:09 is 24116113.694530283 s in the future
 1270 01:00:38.743779  tar: ./lkdtm/SOFTLOCKUP.sh: time stamp 2024-11-01 00:45:09 is 24116113.561142449 s in the future
 1271 01:00:38.869940  tar: ./lkdtm/REFCOUNT_INC_NOT_ZERO_SATURATED.sh: time stamp 2024-11-01 00:45:09 is 24116113.437716449 s in the future
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 1284 01:00:40.480124  tar: ./net/netfilter/nft_nat_zones.sh: time stamp 2024-10-27 19:28:30 is 23751512.825902616 s in the future
 1285 01:00:40.623318  tar: ./net/netfilter/conntrack_dump_flush: time stamp 2024-11-01 00:45:27 is 24116129.683870991 s in the future
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 1343 01:00:51.292424  tar: ./net/tcp_ao/bench-lookups_ipv4: time stamp 2024-11-01 00:45:30 is 24116122.01212399 s in the future
 1344 01:00:51.471171  tar: ./net/tcp_ao/connect_ipv4: time stamp 2024-11-01 00:45:30 is 24116121.834136115 s in the future
 1345 01:00:51.664913  tar: ./net/tcp_ao/self-connect_ipv4: time stamp 2024-11-01 00:45:32 is 24116123.639962323 s in the future
 1346 01:00:51.850110  tar: ./net/tcp_ao/connect_ipv6: time stamp 2024-11-01 00:45:34 is 24116125.454737656 s in the future
 1347 01:00:52.079727  tar: ./net/tcp_ao/key-management_ipv6: time stamp 2024-11-01 00:45:36 is 24116127.225166781 s in the future
 1348 01:00:52.254124  tar: ./net/tcp_ao/restore_ipv4: time stamp 2024-11-01 00:45:31 is 24116122.050040073 s in the future
 1349 01:00:52.455118  tar: ./net/tcp_ao/unsigned-md5_ipv6: time stamp 2024-11-01 00:45:39 is 24116129.850418489 s in the future
 1350 01:00:52.691145  tar: ./net/tcp_ao/restore_ipv6: time stamp 2024-11-01 00:45:36 is 24116126.614164989 s in the future
 1351 01:00:52.866771  tar: ./net/tcp_ao/icmps-accept_ipv6: time stamp 2024-11-01 00:45:35 is 24116125.438763989 s in the future
 1352 01:00:53.060392  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-11-01 00:45:32 is 24116122.244275739 s in the future
 1353 01:00:53.220068  tar: ./net/tcp_ao/config: time stamp 2024-10-27 19:28:30 is 23751500.083440156 s in the future
 1354 01:00:53.417136  tar: ./net/tcp_ao/setsockopt-closed_ipv6: time stamp 2024-11-01 00:45:38 is 24116127.888703823 s in the future
 1355 01:00:53.591680  tar: ./net/tcp_ao/unsigned-md5_ipv4: time stamp 2024-11-01 00:45:33 is 24116122.713498114 s in the future
 1356 01:00:53.781184  tar: ./net/tcp_ao/icmps-discard_ipv4: time stamp 2024-11-01 00:45:31 is 24116120.524664156 s in the future
 1357 01:00:53.973105  tar: ./net/tcp_ao/connect-deny_ipv4: time stamp 2024-11-01 00:45:30 is 24116119.332918823 s in the future
 1358 01:00:54.158318  tar: ./net/tcp_ao/setsockopt-closed_ipv4: time stamp 2024-11-01 00:45:32 is 24116121.146665489 s in the future
 1359 01:00:54.339140  tar: ./net/tcp_ao/rst_ipv6: time stamp 2024-11-01 00:45:36 is 24116124.964766198 s in the future
 1360 01:00:54.521194  tar: ./net/tcp_ao/seq-ext_ipv6: time stamp 2024-11-01 00:45:37 is 24116125.782856531 s in the future
 1361 01:00:54.646088  tar: ./net/tcp_ao/settings: time stamp 2024-10-27 19:28:30 is 23751498.657170447 s in the future
 1362 01:00:54.833529  tar: ./net/tcp_ao/icmps-discard_ipv6: time stamp 2024-11-01 00:45:35 is 24116123.471211614 s in the future
 1363 01:00:55.009169  tar: ./net/tcp_ao/connect-deny_ipv6: time stamp 2024-11-01 00:45:34 is 24116122.295695322 s in the future
 1364 01:00:55.246081  tar: ./net/tcp_ao/key-management_ipv4: time stamp 2024-11-01 00:45:31 is 24116119.059287781 s in the future
 1365 01:00:55.519065  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-11-01 00:45:30 is 24116117.786624572 s in the future
 1366 01:00:55.815105  tar: ./net/tcp_ao/bench-lookups_ipv6: time stamp 2024-11-01 00:45:33 is 24116120.489643989 s in the future
 1367 01:00:56.130110  tar: ./net/tcp_ao/self-connect_ipv6: time stamp 2024-11-01 00:45:37 is 24116124.175110947 s in the future
 1368 01:00:56.347823  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-11-01 00:45:31 is 24116117.956071489 s in the future
 1369 01:00:56.406175  tar: ./net/tcp_ao: time stamp 2024-11-01 00:46:33 is 24116179.896412989 s in the future
 1370 01:00:56.683134  tar: ./net/forwarding/q_in_vni.sh: time stamp 2024-10-27 19:28:30 is 23751496.621157364 s in the future
 1371 01:00:57.029118  tar: ./net/forwarding/router_mpath_nh_res.sh: time stamp 2024-10-27 19:28:30 is 23751496.277539281 s in the future
 1372 01:00:57.334593  tar: ./net/forwarding/vxlan_bridge_1q.sh: time stamp 2024-10-27 19:28:30 is 23751495.970230572 s in the future
 1373 01:00:57.548210  tar: ./net/forwarding/sch_tbf_etsprio.sh: time stamp 2024-10-27 19:28:30 is 23751495.756588697 s in the future
 1374 01:00:57.710120  tar: ./net/forwarding/router_bridge.sh: time stamp 2024-10-27 19:28:30 is 23751495.595005572 s in the future
 1375 01:00:57.884757  tar: ./net/forwarding/vxlan_symmetric.sh: time stamp 2024-10-27 19:28:30 is 23751495.420485864 s in the future
 1376 01:00:58.051143  tar: ./net/forwarding/ip6gre_hier.sh: time stamp 2024-11-01 00:06:48 is 24113793.25353253 s in the future
 1377 01:00:58.231025  tar: ./net/forwarding/sch_tbf_prio.sh: time stamp 2024-10-27 19:28:30 is 23751495.073197239 s in the future
 1378 01:00:58.420345  tar: ./net/forwarding/tc_actions.sh: time stamp 2024-10-27 19:28:30 is 23751494.88408278 s in the future
 1379 01:00:58.578234  tar: ./net/forwarding/tc_flower_port_range.sh: time stamp 2024-10-27 19:28:30 is 23751494.727885739 s in the future
 1380 01:00:58.733142  tar: ./net/forwarding/vxlan_bridge_1d_port_8472_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751494.573171989 s in the future
 1381 01:00:58.913275  tar: ./net/forwarding/gre_multipath_nh_res.sh: time stamp 2024-10-27 19:28:30 is 23751494.392411197 s in the future
 1382 01:00:59.063853  tar: ./net/forwarding/devlink_lib.sh: time stamp 2024-10-27 19:28:30 is 23751494.240852155 s in the future
 1383 01:00:59.210103  tar: ./net/forwarding/ipip_hier_gre_key.sh: time stamp 2024-10-27 19:28:30 is 23751494.094965405 s in the future
 1384 01:00:59.369132  tar: ./net/forwarding/tc_flower_router.sh: time stamp 2024-10-27 19:28:30 is 23751493.935655489 s in the future
 1385 01:00:59.554301  tar: ./net/forwarding/lib.sh: time stamp 2024-10-27 19:28:30 is 23751493.749323989 s in the future
 1386 01:00:59.723165  tar: ./net/forwarding/mirror_gre_bridge_1q_lag.sh: time stamp 2024-10-27 19:28:30 is 23751493.582852405 s in the future
 1387 01:00:59.883166  tar: ./net/forwarding/router_bridge_lag.sh: time stamp 2024-10-27 19:28:30 is 23751493.422966197 s in the future
 1388 01:01:00.032624  tar: ./net/forwarding/ipip_flat_gre.sh: time stamp 2024-10-27 19:28:30 is 23751493.272249405 s in the future
 1389 01:01:00.185191  tar: ./net/forwarding/sch_tbf_root.sh: time stamp 2024-10-27 19:28:30 is 23751493.11946403 s in the future
 1390 01:01:00.783039  tar: ./net/forwarding/skbedit_priority.sh: time stamp 2024-10-27 19:28:30 is 23751492.521230738 s in the future
 1391 01:01:00.955749  tar: ./net/forwarding/bridge_mdb_max.sh: time stamp 2024-10-27 19:28:30 is 23751492.34936903 s in the future
 1392 01:01:01.103046  tar: ./net/forwarding/ip6gre_custom_multipath_hash.sh: time stamp 2024-10-27 19:28:30 is 23751492.203158613 s in the future
 1393 01:01:01.348711  tar: ./net/forwarding/router_multicast.sh: time stamp 2024-10-27 19:28:30 is 23751491.956783113 s in the future
 1394 01:01:01.506813  tar: ./net/forwarding/mirror_gre_flower.sh: time stamp 2024-10-27 19:28:30 is 23751491.79897053 s in the future
 1395 01:01:01.623311  tar: ./net/forwarding/router_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751491.681446113 s in the future
 1396 01:01:01.767494  tar: ./net/forwarding/vxlan_bridge_1d_port_8472.sh: time stamp 2024-10-27 19:28:30 is 23751491.538230613 s in the future
 1397 01:01:01.916044  tar: ./net/forwarding/tc_shblocks.sh: time stamp 2024-10-27 19:28:30 is 23751491.389646655 s in the future
 1398 01:01:02.032234  tar: ./net/forwarding/config: time stamp 2024-10-27 19:28:30 is 23751491.271314072 s in the future
 1399 01:01:02.182986  tar: ./net/forwarding/dual_vxlan_bridge.sh: time stamp 2024-10-27 19:28:30 is 23751491.121401155 s in the future
 1400 01:01:02.316611  tar: ./net/forwarding/mirror_gre_vlan_bridge_1q.sh: time stamp 2024-10-27 19:28:30 is 23751490.989236947 s in the future
 1401 01:01:02.449255  tar: ./net/forwarding/sch_ets_tests.sh: time stamp 2024-10-27 19:28:30 is 23751490.85557128 s in the future
 1402 01:01:02.688738  tar: ./net/forwarding/ip6gre_inner_v4_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751490.61721103 s in the future
 1403 01:01:02.925457  tar: ./net/forwarding/mirror_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751490.378882238 s in the future
 1404 01:01:03.158269  tar: ./net/forwarding/fib_offload_lib.sh: time stamp 2024-10-27 19:28:30 is 23751490.146754363 s in the future
 1405 01:01:03.417330  tar: ./net/forwarding/bridge_mdb.sh: time stamp 2024-10-27 19:28:30 is 23751489.886805113 s in the future
 1406 01:01:03.635458  tar: ./net/forwarding/bridge_vlan_aware.sh: time stamp 2024-10-27 19:28:30 is 23751489.669819905 s in the future
 1407 01:01:03.776608  tar: ./net/forwarding/router_bridge_1d.sh: time stamp 2024-10-27 19:28:30 is 23751489.528930571 s in the future
 1408 01:01:03.900803  tar: ./net/forwarding/bridge_vlan_mcast.sh: time stamp 2024-10-27 19:28:30 is 23751489.404308905 s in the future
 1409 01:01:04.034183  tar: ./net/forwarding/router.sh: time stamp 2024-10-27 19:28:30 is 23751489.269318321 s in the future
 1410 01:01:04.168870  tar: ./net/forwarding/ipip_flat_gre_key.sh: time stamp 2024-10-27 19:28:30 is 23751489.13674928 s in the future
 1411 01:01:04.294074  tar: ./net/forwarding/vxlan_asymmetric_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751489.010858946 s in the future
 1412 01:01:04.436194  tar: ./net/forwarding/router_broadcast.sh: time stamp 2024-10-27 19:28:30 is 23751488.868904071 s in the future
 1413 01:01:04.551926  tar: ./net/forwarding/ip6gre_hier_key.sh: time stamp 2024-11-01 00:06:48 is 24113786.753185696 s in the future
 1414 01:01:04.669671  tar: ./net/forwarding/bridge_fdb_learning_limit.sh: time stamp 2024-10-27 19:28:30 is 23751488.635859446 s in the future
 1415 01:01:04.786443  tar: ./net/forwarding/ip6gre_flat_key.sh: time stamp 2024-11-01 00:06:48 is 24113786.518529696 s in the future
 1416 01:01:04.904202  tar: ./net/forwarding/tc_flower_l2_miss.sh: time stamp 2024-10-27 19:28:30 is 23751488.401770738 s in the future
 1417 01:01:05.028495  tar: ./net/forwarding/ip6gre_inner_v6_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751488.277440905 s in the future
 1418 01:01:05.135765  tar: ./net/forwarding/tc_tunnel_key.sh: time stamp 2024-10-27 19:28:30 is 23751488.168789488 s in the future
 1419 01:01:05.274538  tar: ./net/forwarding/no_forwarding.sh: time stamp 2024-10-27 19:28:30 is 23751488.030351196 s in the future
 1420 01:01:05.387051  tar: ./net/forwarding/router_mpath_seed.sh: time stamp 2024-10-27 19:28:30 is 23751487.917788905 s in the future
 1421 01:01:05.529121  tar: ./net/forwarding/vxlan_bridge_1q_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751487.776947571 s in the future
 1422 01:01:06.417013  tar: ./net/forwarding/vxlan_asymmetric.sh: time stamp 2024-10-27 19:28:30 is 23751486.888659571 s in the future
 1423 01:01:10.023226  tar: ./net/forwarding/sch_tbf_core.sh: time stamp 2024-10-27 19:28:30 is 23751483.281949862 s in the future
 1424 01:01:10.306542  tar: ./net/forwarding/gre_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751482.997885529 s in the future
 1425 01:01:10.542775  tar: ./net/forwarding/sch_ets_core.sh: time stamp 2024-10-27 19:28:30 is 23751482.762747154 s in the future
 1426 01:01:10.843001  tar: ./net/forwarding/gre_inner_v6_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751482.462535446 s in the future
 1427 01:01:11.050271  tar: ./net/forwarding/mirror_gre_lib.sh: time stamp 2024-10-27 19:28:30 is 23751482.254297737 s in the future
 1428 01:01:11.309473  tar: ./net/forwarding/sch_red.sh: time stamp 2024-10-27 19:28:30 is 23751481.994578862 s in the future
 1429 01:01:11.535938  tar: ./net/forwarding/ip6gre_flat_keys.sh: time stamp 2024-11-01 00:06:48 is 24113779.769385862 s in the future
 1430 01:01:11.727906  tar: ./net/forwarding/router_mpath_nh.sh: time stamp 2024-10-27 19:28:30 is 23751481.577196029 s in the future
 1431 01:01:11.843793  tar: ./net/forwarding/ipip_flat_gre_keys.sh: time stamp 2024-10-27 19:28:30 is 23751481.460468695 s in the future
 1432 01:01:11.967784  tar: ./net/forwarding/ip6gre_lib.sh: time stamp 2024-11-01 00:06:48 is 24113779.335520529 s in the future
 1433 01:01:12.094014  tar: ./net/forwarding/bridge_sticky_fdb.sh: time stamp 2024-10-27 19:28:30 is 23751481.21021282 s in the future
 1434 01:01:12.203742  tar: ./net/forwarding/vxlan_bridge_1q_port_8472_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751481.102744029 s in the future
 1435 01:01:12.310963  tar: ./net/forwarding/mirror_gre_bridge_1d_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751480.993504612 s in the future
 1436 01:01:12.452934  tar: ./net/forwarding/tc_police.sh: time stamp 2024-10-27 19:28:30 is 23751480.851389029 s in the future
 1437 01:01:12.586446  tar: ./net/forwarding/gre_multipath_nh.sh: time stamp 2024-10-27 19:28:30 is 23751480.718126779 s in the future
 1438 01:01:12.804561  tar: ./net/forwarding/vxlan_bridge_1d_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751480.500956029 s in the future
 1439 01:01:13.028702  tar: ./net/forwarding/q_in_vni_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751480.275698904 s in the future
 1440 01:01:13.246868  tar: ./net/forwarding/vxlan_bridge_1q_port_8472.sh: time stamp 2024-10-27 19:28:30 is 23751480.058811279 s in the future
 1441 01:01:13.495449  tar: ./net/forwarding/mirror_lib.sh: time stamp 2024-10-27 19:28:30 is 23751479.808509445 s in the future
 1442 01:01:13.729193  tar: ./net/forwarding/vxlan_symmetric_ipv6.sh: time stamp 2024-10-27 19:28:30 is 23751479.574945445 s in the future
 1443 01:01:13.988444  tar: ./net/forwarding/pedit_dsfield.sh: time stamp 2024-10-27 19:28:30 is 23751479.316131778 s in the future
 1444 01:01:14.271932  tar: ./net/forwarding/settings: time stamp 2024-10-27 19:28:30 is 23751479.032570862 s in the future
 1445 01:01:14.480387  tar: ./net/forwarding/mirror_gre_nh.sh: time stamp 2024-10-27 19:28:30 is 23751478.823840195 s in the future
 1446 01:01:14.729928  tar: ./net/forwarding/ip6gre_flat.sh: time stamp 2024-11-01 00:06:48 is 24113776.573471278 s in the future
 1447 01:01:14.853935  tar: ./net/forwarding/tc_chains.sh: time stamp 2024-10-27 19:28:30 is 23751478.449137612 s in the future
 1448 01:01:14.972756  tar: ./net/forwarding/bridge_mdb_port_down.sh: time stamp 2024-10-27 19:28:30 is 23751478.331660278 s in the future
 1449 01:01:15.113966  tar: ./net/forwarding/gre_custom_multipath_hash.sh: time stamp 2024-10-27 19:28:30 is 23751478.192153237 s in the future
 1450 01:01:15.247446  tar: ./net/forwarding/mirror_gre_bound.sh: time stamp 2024-10-27 19:28:30 is 23751478.056789237 s in the future
 1451 01:01:15.373760  tar: ./net/forwarding/ip6_forward_instats_vrf.sh: time stamp 2024-10-27 19:28:30 is 23751477.931176362 s in the future
 1452 01:01:15.495768  tar: ./net/forwarding/tc_vlan_modify.sh: time stamp 2024-10-27 19:28:30 is 23751477.808651195 s in the future
 1453 01:01:15.624074  tar: ./net/forwarding/bridge_vlan_unaware.sh: time stamp 2024-10-27 19:28:30 is 23751477.680463362 s in the future
 1454 01:01:15.772350  tar: ./net/forwarding/bridge_mld.sh: time stamp 2024-10-27 19:28:30 is 23751477.530998528 s in the future
 1455 01:01:15.881794  tar: ./net/forwarding/gre_inner_v4_multipath.sh: time stamp 2024-10-27 19:28:30 is 23751477.422351278 s in the future
 1456 01:01:15.998289  tar: ./net/forwarding/router_nh.sh: time stamp 2024-10-27 19:28:30 is 23751477.304978903 s in the future
 1457 01:01:16.115898  tar: ./net/forwarding/mirror_topo_lib.sh: time stamp 2024-10-27 19:28:30 is 23751477.188237237 s in the future
 1458 01:01:16.224137  tar: ./net/forwarding/bridge_port_isolation.sh: time stamp 2024-10-27 19:28:30 is 23751477.080006778 s in the future
 1459 01:01:16.349119  tar: ./net/forwarding/sch_tbf_ets.sh: time stamp 2024-10-27 19:28:30 is 23751476.954529028 s in the future
 1460 01:01:16.475470  tar: ./net/forwarding/router_bridge_vlan_upper.sh: time stamp 2024-10-27 19:28:30 is 23751476.829822153 s in the future
 1461 01:01:16.583852  tar: ./net/forwarding/router_bridge_1d_lag.sh: time stamp 2024-10-27 19:28:30 is 23751476.721431237 s in the future
 1462 01:01:16.732212  tar: ./net/forwarding/custom_multipath_hash.sh: time stamp 2024-10-27 19:28:30 is 23751476.572253487 s in the future
 1463 01:01:16.859539  tar: ./net/forwarding/mirror_gre_lag_lacp.sh: time stamp 2024-10-27 19:28:30 is 23751476.44549182 s in the future
 1464 01:01:16.983457  tar: ./net/forwarding/min_max_mtu.sh: time stamp 2024-10-27 19:28:30 is 23751476.320596403 s in the future
 1465 01:01:17.099001  tar: ./net/forwarding/sch_ets.sh: time stamp 2024-10-27 19:28:30 is 23751476.203761861 s in the future
 1466 01:01:17.250587  tar: ./net/forwarding/tc_flower_cfm.sh: time stamp 2024-10-27 19:28:30 is 23751476.053523445 s in the future
 1467 01:01:17.383965  tar: ./net/forwarding/router_bridge_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751475.919921778 s in the future
 1468 01:01:17.523980  tar: ./net/forwarding/local_termination.sh: time stamp 2024-10-27 19:28:30 is 23751475.779689945 s in the future
 1469 01:01:17.659721  tar: ./net/forwarding/mirror_gre_vlan.sh: time stamp 2024-10-27 19:28:30 is 23751475.644620028 s in the future
 1470 01:01:17.777401  tar: ./net/forwarding/router_bridge_vlan_upper_pvid.sh: time stamp 2024-10-27 19:28:30 is 23751475.527978445 s in the future
 1471 01:01:17.927980  tar: ./net/forwarding/mirror_gre_changes.sh: time stamp 2024-10-27 19:28:30 is 23751475.377739153 s in the future
 1472 01:01:18.042579  tar: ./net/forwarding/tc_common.sh: time stamp 2024-10-27 19:28:30 is 23751475.26087257 s in the future
 1473 01:01:18.181448  tar: ./net/forwarding/router_vid_1.sh: time stamp 2024-10-27 19:28:30 is 23751475.122402528 s in the future
 1474 01:01:18.301124  tar: ./net/forwarding/bridge_mdb_host.sh: time stamp 2024-10-27 19:28:30 is 23751475.00247082 s in the future
 1475 01:01:18.434760  tar: ./net/forwarding/ipip_hier_gre_keys.sh: time stamp 2024-10-27 19:28:30 is 23751474.868919695 s in the future
 1476 01:01:18.569579  tar: ./net/forwarding/mirror_gre_topo_lib.sh: time stamp 2024-10-27 19:28:30 is 23751474.735349278 s in the future
 1477 01:01:18.686323  tar: ./net/forwarding/forwarding.config.sample: time stamp 2024-10-27 19:28:30 is 23751474.618586445 s in the future
 1478 01:01:18.810477  tar: ./net/forwarding/pedit_l4port.sh: time stamp 2024-10-27 19:28:30 is 23751474.493446111 s in the future
 1479 01:01:18.957594  tar: ./net/forwarding/lib_sh_test.sh: time stamp 2024-10-27 19:28:30 is 23751474.346547778 s in the future
 1480 01:01:19.084638  tar: ./net/forwarding/ip6gre_hier_keys.sh: time stamp 2024-11-01 00:06:48 is 24113772.219525278 s in the future
 1481 01:01:19.203569  tar: ./net/forwarding/router_mpath_nh_lib.sh: time stamp 2024-10-27 19:28:30 is 23751474.101140736 s in the future
 1482 01:01:19.320432  tar: ./net/forwarding/mirror_gre_bridge_1q.sh: time stamp 2024-10-27 19:28:30 is 23751473.984504278 s in the future
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 1541 01:01:27.613822  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751465.691585902 s in the future
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 2066 01:02:39.992763  tar: ./tc-testing/tc-tests/qdiscs/fq_pie.json: time stamp 2024-10-27 19:28:30 is 23751393.307906393 s in the future
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 2068 01:02:40.244359  tar: ./tc-testing/tc-tests/qdiscs/plug.json: time stamp 2024-10-27 19:28:30 is 23751393.055012185 s in the future
 2069 01:02:40.389217  tar: ./tc-testing/tc-tests/qdiscs/mqprio.json: time stamp 2024-10-27 19:28:30 is 23751392.911654143 s in the future
 2070 01:02:40.445580  tar: ./tc-testing/tc-tests/qdiscs: time stamp 2024-10-27 19:28:30 is 23751392.85348206 s in the future
 2071 01:02:40.618197  tar: ./tc-testing/tc-tests/actions/sample.json: time stamp 2024-10-27 19:28:30 is 23751392.682887143 s in the future
 2072 01:02:40.763397  tar: ./tc-testing/tc-tests/actions/connmark.json: time stamp 2024-10-27 19:28:30 is 23751392.536985393 s in the future
 2073 01:02:40.898164  tar: ./tc-testing/tc-tests/actions/tunnel_key.json: time stamp 2024-10-27 19:28:30 is 23751392.402957893 s in the future
 2074 01:02:41.034794  tar: ./tc-testing/tc-tests/actions/mpls.json: time stamp 2024-10-27 19:28:30 is 23751392.265406851 s in the future
 2075 01:02:41.164175  tar: ./tc-testing/tc-tests/actions/skbedit.json: time stamp 2024-10-27 19:28:30 is 23751392.136388726 s in the future
 2076 01:02:41.296600  tar: ./tc-testing/tc-tests/actions/skbmod.json: time stamp 2024-10-27 19:28:30 is 23751392.003188476 s in the future
 2077 01:02:41.438428  tar: ./tc-testing/tc-tests/actions/ife.json: time stamp 2024-10-27 19:28:30 is 23751391.860962268 s in the future
 2078 01:02:41.573211  tar: ./tc-testing/tc-tests/actions/gact.json: time stamp 2024-10-27 19:28:30 is 23751391.727468268 s in the future
 2079 01:02:41.730884  tar: ./tc-testing/tc-tests/actions/gate.json: time stamp 2024-10-27 19:28:30 is 23751391.569054143 s in the future
 2080 01:02:41.892940  tar: ./tc-testing/tc-tests/actions/pedit.json: time stamp 2024-10-27 19:28:30 is 23751391.40703506 s in the future
 2081 01:02:42.035202  tar: ./tc-testing/tc-tests/actions/bpf.json: time stamp 2024-10-27 19:28:30 is 23751391.265221518 s in the future
 2082 01:02:42.174161  tar: ./tc-testing/tc-tests/actions/simple.json: time stamp 2024-10-27 19:28:30 is 23751391.12672881 s in the future
 2083 01:02:42.315262  tar: ./tc-testing/tc-tests/actions/police.json: time stamp 2024-10-27 19:28:30 is 23751390.985205393 s in the future
 2084 01:02:42.457281  tar: ./tc-testing/tc-tests/actions/nat.json: time stamp 2024-10-27 19:28:30 is 23751390.843319976 s in the future
 2085 01:02:42.593982  tar: ./tc-testing/tc-tests/actions/csum.json: time stamp 2024-10-27 19:28:30 is 23751390.706497351 s in the future
 2086 01:02:42.731880  tar: ./tc-testing/tc-tests/actions/ctinfo.json: time stamp 2024-10-27 19:28:30 is 23751390.568168476 s in the future
 2087 01:02:42.899230  tar: ./tc-testing/tc-tests/actions/vlan.json: time stamp 2024-10-27 19:28:30 is 23751390.401411268 s in the future
 2088 01:02:43.043411  tar: ./tc-testing/tc-tests/actions/mirred.json: time stamp 2024-10-27 19:28:30 is 23751390.256229685 s in the future
 2089 01:02:43.190743  tar: ./tc-testing/tc-tests/actions/ct.json: time stamp 2024-10-27 19:28:30 is 23751390.109403726 s in the future
 2090 01:02:43.248232  tar: ./tc-testing/tc-tests/actions: time stamp 2024-10-27 19:28:30 is 23751390.051032768 s in the future
 2091 01:02:43.305853  tar: ./tc-testing/tc-tests: time stamp 2024-10-27 19:28:30 is 23751389.99269456 s in the future
 2092 01:02:43.435080  tar: ./tc-testing/config: time stamp 2024-10-27 19:28:30 is 23751389.863348976 s in the future
 2093 01:02:43.560305  tar: ./tc-testing/TdcPlugin.py: time stamp 2024-10-27 19:28:30 is 23751389.739238809 s in the future
 2094 01:02:43.688529  tar: ./tc-testing/tdc_helper.py: time stamp 2024-10-27 19:28:30 is 23751389.610595893 s in the future
 2095 01:02:43.843297  tar: ./tc-testing/tdc.sh: time stamp 2024-10-27 19:28:30 is 23751389.454558518 s in the future
 2096 01:02:43.973498  tar: ./tc-testing/tdc_config.py: time stamp 2024-10-27 19:28:30 is 23751389.325370934 s in the future
 2097 01:02:44.101971  tar: ./tc-testing/settings: time stamp 2024-10-27 19:28:30 is 23751389.195979768 s in the future
 2098 01:02:44.250311  tar: ./tc-testing/plugin-lib/scapyPlugin.py: time stamp 2024-10-27 19:28:30 is 23751389.050183601 s in the future
 2099 01:02:44.384105  tar: ./tc-testing/plugin-lib/README-PLUGINS: time stamp 2024-10-27 19:28:30 is 23751388.916679351 s in the future
 2100 01:02:44.508366  tar: ./tc-testing/plugin-lib/rootPlugin.py: time stamp 2024-10-27 19:28:30 is 23751388.791526059 s in the future
 2101 01:02:44.665253  tar: ./tc-testing/plugin-lib/nsPlugin.py: time stamp 2024-10-27 19:28:30 is 23751388.633929643 s in the future
 2102 01:02:44.808291  tar: ./tc-testing/plugin-lib/valgrindPlugin.py: time stamp 2024-10-27 19:28:30 is 23751388.491416809 s in the future
 2103 01:02:44.857179  tar: ./tc-testing/plugin-lib: time stamp 2024-10-27 19:28:30 is 23751388.441450184 s in the future
 2104 01:02:44.991851  tar: ./tc-testing/action-ebpf: time stamp 2024-10-27 19:28:30 is 23751388.307699393 s in the future
 2105 01:02:45.139277  tar: ./tc-testing/scripts/taprio_wait_for_admin.sh: time stamp 2024-10-27 19:28:30 is 23751388.161739226 s in the future
 2106 01:02:45.197744  tar: ./tc-testing/scripts: time stamp 2024-10-27 19:28:30 is 23751388.100181101 s in the future
 2107 01:02:45.342946  tar: ./tc-testing/tdc_config_local_template.py: time stamp 2024-10-27 19:28:30 is 23751387.957652518 s in the future
 2108 01:02:45.457300  tar: ./tc-testing/tdc_batch.py: time stamp 2024-10-27 19:28:30 is 23751387.840724559 s in the future
 2109 01:02:45.583635  tar: ./tc-testing/tdc_multibatch.py: time stamp 2024-10-27 19:28:30 is 23751387.715505934 s in the future
 2110 01:02:45.720282  tar: ./tc-testing/plugins/__init__.py: time stamp 2024-10-27 19:28:30 is 23751387.579211559 s in the future
 2111 01:02:45.782035  tar: ./tc-testing/plugins: time stamp 2024-10-27 19:28:30 is 23751387.516768851 s in the future
 2112 01:02:45.840565  tar: ./tc-testing: time stamp 2024-11-01 00:46:40 is 24116077.457163143 s in the future
 2113 01:02:45.982318  tar: ./kselftest/runner.sh: time stamp 2024-11-01 00:46:23 is 24116060.315202726 s in the future
 2114 01:02:46.108297  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-27 19:28:30 is 23751387.190050643 s in the future
 2115 01:02:46.257702  tar: ./kselftest/module.sh: time stamp 2024-11-01 00:46:23 is 24116060.040799226 s in the future
 2116 01:02:46.383738  tar: ./kselftest/ksft.py: time stamp 2024-11-01 00:46:23 is 24116059.914927434 s in the future
 2117 01:02:46.500376  tar: ./kselftest/prefix.pl: time stamp 2024-11-01 00:46:23 is 24116059.798151351 s in the future
 2118 01:02:46.561939  tar: ./kselftest: time stamp 2024-10-27 19:28:30 is 23751386.735455642 s in the future
 2119 01:02:46.733423  tar: ./tty/tty_tstamp_update: time stamp 2024-11-01 00:46:07 is 24116043.564697184 s in the future
 2120 01:02:46.793744  tar: ./tty: time stamp 2024-11-01 00:46:42 is 24116078.503040476 s in the future
 2121 01:02:46.857287  tar: .: time stamp 2024-11-01 00:46:47 is 24116083.439687142 s in the future
 2122 01:02:47.116901  skiplist:
 2123 01:02:47.117282  ========================================
 2124 01:02:47.122612  ========================================
 2125 01:02:47.402845  dt:test_unprobed_devices.sh
 2126 01:02:47.512489  ============== Tests to run ===============
 2127 01:02:47.523058  dt:test_unprobed_devices.sh
 2128 01:02:47.526406  ===========End Tests to run ===============
 2129 01:02:47.564848  shardfile-dt pass
 2130 01:02:47.910643  <12>[  224.095510] kselftest: Running tests in dt
 2131 01:02:47.943981  TAP version 13
 2132 01:02:47.967555  1..1
 2133 01:02:48.023768  # timeout set to 45
 2134 01:02:48.027111  # selftests: dt: test_unprobed_devices.sh
 2135 01:02:48.912058  # TAP version 13
 2136 01:03:14.859642  # 1..257
 2137 01:03:15.061815  # ok 1 / # SKIP
 2138 01:03:15.082984  # ok 2 /clk_mcasp0
 2139 01:03:15.163547  # ok 3 /clk_mcasp0_fixed # SKIP
 2140 01:03:15.232859  # ok 4 /cpus/cpu@0 # SKIP
 2141 01:03:15.312059  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2142 01:03:15.329475  # ok 6 /fixedregulator0
 2143 01:03:15.351238  # ok 7 /leds
 2144 01:03:15.372741  # ok 8 /ocp
 2145 01:03:15.401982  # ok 9 /ocp/interconnect@44c00000
 2146 01:03:15.422939  # ok 10 /ocp/interconnect@44c00000/segment@0
 2147 01:03:15.450022  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2148 01:03:15.476908  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2149 01:03:15.547482  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2150 01:03:15.573001  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2151 01:03:15.596564  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2152 01:03:15.705475  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2153 01:03:15.783021  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2154 01:03:15.863166  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2155 01:03:15.935519  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2156 01:03:16.013091  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2157 01:03:16.087540  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2158 01:03:16.163227  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2159 01:03:16.243179  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2160 01:03:16.315781  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2161 01:03:16.391236  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2162 01:03:16.467329  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2163 01:03:16.542505  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2164 01:03:16.617034  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2165 01:03:16.698028  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2166 01:03:16.773798  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2167 01:03:16.845108  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2168 01:03:16.920307  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2169 01:03:16.995933  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2170 01:03:17.072643  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2171 01:03:17.148184  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2172 01:03:17.223688  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2173 01:03:17.303806  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2174 01:03:17.379406  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2175 01:03:17.456031  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2176 01:03:17.528503  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2177 01:03:17.604230  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2178 01:03:17.681229  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2179 01:03:17.760314  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2180 01:03:17.835260  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2181 01:03:17.911236  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2182 01:03:17.988110  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2183 01:03:18.066990  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2184 01:03:18.143774  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2185 01:03:18.221607  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2186 01:03:18.297220  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2187 01:03:18.375032  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2188 01:03:18.456053  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2189 01:03:18.530851  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2190 01:03:18.610138  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2191 01:03:18.688129  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2192 01:03:18.766111  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2193 01:03:18.844102  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2194 01:03:18.915327  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2195 01:03:18.994158  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2196 01:03:19.074704  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2197 01:03:19.147955  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2198 01:03:19.224977  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2199 01:03:19.302783  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2200 01:03:19.378531  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2201 01:03:19.453980  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2202 01:03:19.532763  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2203 01:03:19.609883  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2204 01:03:19.686677  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2205 01:03:19.762396  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2206 01:03:19.845214  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2207 01:03:19.919009  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2208 01:03:19.995671  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2209 01:03:20.072019  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2210 01:03:20.148896  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2211 01:03:20.226751  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2212 01:03:20.303575  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2213 01:03:20.381341  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2214 01:03:20.457517  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2215 01:03:20.535310  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2216 01:03:20.620809  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2217 01:03:20.694465  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2218 01:03:20.769221  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2219 01:03:20.842684  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2220 01:03:20.920500  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2221 01:03:20.998088  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2222 01:03:21.078103  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2223 01:03:21.152717  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2224 01:03:21.233852  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2225 01:03:21.311045  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2226 01:03:21.386915  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2227 01:03:21.461065  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2228 01:03:21.539068  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2229 01:03:21.617104  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2230 01:03:21.694147  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2231 01:03:21.715043  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2232 01:03:21.741814  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2233 01:03:21.766734  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2234 01:03:21.791508  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2235 01:03:21.816385  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2236 01:03:21.842163  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2237 01:03:21.866163  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2238 01:03:21.890542  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2239 01:03:22.004031  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2240 01:03:22.029234  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2241 01:03:22.058165  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2242 01:03:22.080806  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2243 01:03:22.264349  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2244 01:03:22.283179  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2245 01:03:22.354790  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2246 01:03:22.437277  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2247 01:03:22.511288  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2248 01:03:22.588071  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2249 01:03:22.665214  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2250 01:03:22.742819  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2251 01:03:22.820167  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2252 01:03:22.898216  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2253 01:03:22.975132  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2254 01:03:23.055663  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2255 01:03:23.126839  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2256 01:03:23.211382  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2257 01:03:23.285371  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2258 01:03:23.363538  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2259 01:03:23.386083  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2260 01:03:23.461278  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2261 01:03:23.535914  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2262 01:03:23.613143  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2263 01:03:23.636845  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2264 01:03:23.712058  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2265 01:03:23.735813  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2266 01:03:23.812142  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2267 01:03:23.836874  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2268 01:03:23.861586  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2269 01:03:23.885238  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2270 01:03:23.915188  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2271 01:03:23.936836  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2272 01:03:23.959771  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2273 01:03:23.987481  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 2274 01:03:24.070725  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 2275 01:03:24.096018  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2276 01:03:24.117105  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2277 01:03:24.191117  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2278 01:03:24.265900  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2279 01:03:24.289223  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2280 01:03:24.396837  # not ok 144 /ocp/interconnect@47c00000
 2281 01:03:24.473910  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2282 01:03:24.495649  # ok 146 /ocp/interconnect@48000000
 2283 01:03:24.519849  # ok 147 /ocp/interconnect@48000000/segment@0
 2284 01:03:24.546596  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2285 01:03:24.574382  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2286 01:03:24.595836  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2287 01:03:24.623362  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2288 01:03:24.646259  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2289 01:03:24.669638  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2290 01:03:24.691339  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2291 01:03:24.766948  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2292 01:03:24.844575  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2293 01:03:24.868137  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2294 01:03:24.893655  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2295 01:03:24.916451  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2296 01:03:24.942897  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2297 01:03:24.970865  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2298 01:03:24.991124  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2299 01:03:25.014615  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2300 01:03:25.040748  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2301 01:03:25.065760  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2302 01:03:25.090447  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2303 01:03:25.114124  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2304 01:03:25.139372  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2305 01:03:25.161964  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2306 01:03:25.188518  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2307 01:03:25.216226  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2308 01:03:25.236813  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2309 01:03:25.260201  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2310 01:03:25.285994  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2311 01:03:25.308287  # ok 175 /ocp/interconnect@48000000/segment@100000
 2312 01:03:25.336131  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2313 01:03:25.359671  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2314 01:03:25.436254  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 2315 01:03:25.514050  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 2316 01:03:25.589756  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 2317 01:03:25.665275  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 2318 01:03:25.740945  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 2319 01:03:25.818014  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 2320 01:03:25.892647  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 2321 01:03:25.975861  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 2322 01:03:25.992132  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2323 01:03:26.021992  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2324 01:03:26.045630  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2325 01:03:26.070236  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2326 01:03:26.094707  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2327 01:03:26.117183  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2328 01:03:26.144123  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2329 01:03:26.167516  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2330 01:03:26.190131  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2331 01:03:26.216802  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2332 01:03:26.239169  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2333 01:03:26.264943  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2334 01:03:26.286890  # ok 198 /ocp/interconnect@48000000/segment@200000
 2335 01:03:26.311676  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2336 01:03:26.393717  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2337 01:03:26.409577  # ok 201 /ocp/interconnect@48000000/segment@300000
 2338 01:03:26.434052  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2339 01:03:26.464682  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2340 01:03:26.486011  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2341 01:03:26.508179  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2342 01:03:26.533633  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2343 01:03:26.557169  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2344 01:03:26.633548  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2345 01:03:26.657944  # ok 209 /ocp/interconnect@4a000000
 2346 01:03:26.682123  # ok 210 /ocp/interconnect@4a000000/segment@0
 2347 01:03:26.704299  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2348 01:03:26.733321  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2349 01:03:26.756945  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2350 01:03:26.778078  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2351 01:03:26.853200  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2352 01:03:26.968953  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2353 01:03:27.045753  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2354 01:03:27.156184  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2355 01:03:27.228507  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2356 01:03:27.302348  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2357 01:03:27.408404  # not ok 221 /ocp/interconnect@4b140000
 2358 01:03:27.484541  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2359 01:03:27.563742  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2360 01:03:27.583776  # ok 224 /ocp/target-module@40300000
 2361 01:03:27.605650  # ok 225 /ocp/target-module@40300000/sram@0
 2362 01:03:27.685077  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2363 01:03:27.758101  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2364 01:03:27.778867  # ok 228 /ocp/target-module@47400000
 2365 01:03:27.809874  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2366 01:03:27.828944  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2367 01:03:27.852165  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2368 01:03:27.874980  # ok 232 /ocp/target-module@47400000/usb@1400
 2369 01:03:27.903501  # ok 233 /ocp/target-module@47400000/usb@1800
 2370 01:03:27.923529  # ok 234 /ocp/target-module@47810000
 2371 01:03:27.945283  # ok 235 /ocp/target-module@49000000
 2372 01:03:27.973851  # ok 236 /ocp/target-module@49000000/dma@0
 2373 01:03:27.993252  # ok 237 /ocp/target-module@49800000
 2374 01:03:28.020174  # ok 238 /ocp/target-module@49800000/dma@0
 2375 01:03:28.043368  # ok 239 /ocp/target-module@49900000
 2376 01:03:28.071405  # ok 240 /ocp/target-module@49900000/dma@0
 2377 01:03:28.092429  # ok 241 /ocp/target-module@49a00000
 2378 01:03:28.114708  # ok 242 /ocp/target-module@49a00000/dma@0
 2379 01:03:28.139980  # ok 243 /ocp/target-module@4c000000
 2380 01:03:28.214037  # not ok 244 /ocp/target-module@4c000000/emif@0
 2381 01:03:28.237204  # ok 245 /ocp/target-module@50000000
 2382 01:03:28.260739  # ok 246 /ocp/target-module@53100000
 2383 01:03:28.332003  # not ok 247 /ocp/target-module@53100000/sham@0
 2384 01:03:28.359355  # ok 248 /ocp/target-module@53500000
 2385 01:03:28.434321  # not ok 249 /ocp/target-module@53500000/aes@0
 2386 01:03:28.453219  # ok 250 /ocp/target-module@56000000
 2387 01:03:28.564162  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2388 01:03:28.640177  # ok 252 /opp-table # SKIP
 2389 01:03:28.711606  # ok 253 /soc # SKIP
 2390 01:03:28.737290  # ok 254 /sound
 2391 01:03:28.762608  # ok 255 /target-module@4b000000
 2392 01:03:28.784862  # ok 256 /target-module@4b000000/target-module@140000
 2393 01:03:28.805210  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2394 01:03:28.813218  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2395 01:03:28.822681  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2396 01:03:31.212109  dt_test_unprobed_devices_sh_ skip
 2397 01:03:31.218060  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2398 01:03:31.223215  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2399 01:03:31.223593  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2400 01:03:31.231714  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2401 01:03:31.232096  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2402 01:03:31.237887  dt_test_unprobed_devices_sh_leds pass
 2403 01:03:31.242773  dt_test_unprobed_devices_sh_ocp pass
 2404 01:03:31.247570  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2405 01:03:31.252558  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2406 01:03:31.258637  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2407 01:03:31.268344  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2408 01:03:31.273422  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2409 01:03:31.283618  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2410 01:03:31.289478  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2411 01:03:31.300838  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2412 01:03:31.305573  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2413 01:03:31.315407  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2414 01:03:31.326399  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2415 01:03:31.336171  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2416 01:03:31.347237  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2417 01:03:31.356981  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2418 01:03:31.368071  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2419 01:03:31.377836  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2420 01:03:31.388969  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2421 01:03:31.398650  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2422 01:03:31.409634  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2423 01:03:31.419409  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2424 01:03:31.430395  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2425 01:03:31.440339  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2426 01:03:31.446374  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2427 01:03:31.456129  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2428 01:03:31.467135  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2429 01:03:31.477084  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2430 01:03:31.488211  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2431 01:03:31.498130  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2432 01:03:31.507832  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2433 01:03:31.518735  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2434 01:03:31.528860  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2435 01:03:31.539650  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2436 01:03:31.550825  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2437 01:03:31.559917  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2438 01:03:31.571771  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2439 01:03:31.581346  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2440 01:03:31.592591  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2441 01:03:31.607142  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2442 01:03:31.618211  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2443 01:03:31.627982  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2444 01:03:31.638921  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2445 01:03:31.647631  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2446 01:03:31.659835  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2447 01:03:31.669705  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2448 01:03:31.680838  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2449 01:03:31.696776  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2450 01:03:31.707826  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2451 01:03:31.717601  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2452 01:03:31.729825  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2453 01:03:31.740805  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2454 01:03:31.751947  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2455 01:03:31.762956  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2456 01:03:31.767826  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2457 01:03:31.780017  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2458 01:03:31.794731  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2459 01:03:31.805710  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2460 01:03:31.815519  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2461 01:03:31.826448  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2462 01:03:31.836542  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2463 01:03:31.847526  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2464 01:03:31.857259  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2465 01:03:31.868188  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2466 01:03:31.878013  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2467 01:03:31.889097  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2468 01:03:31.898936  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2469 01:03:31.909926  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2470 01:03:31.925830  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2471 01:03:31.935640  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2472 01:03:31.946730  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2473 01:03:31.956392  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2474 01:03:31.967523  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2475 01:03:31.976582  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2476 01:03:31.988341  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2477 01:03:31.997956  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2478 01:03:32.009092  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2479 01:03:32.018744  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2480 01:03:32.029828  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2481 01:03:32.039490  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2482 01:03:32.050712  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2483 01:03:32.060272  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2484 01:03:32.071449  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2485 01:03:32.086050  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2486 01:03:32.092146  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2487 01:03:32.106775  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2488 01:03:32.117729  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2489 01:03:32.127825  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2490 01:03:32.138825  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2491 01:03:32.148485  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2492 01:03:32.159413  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2493 01:03:32.169403  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2494 01:03:32.175406  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2495 01:03:32.185263  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2496 01:03:32.196532  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2497 01:03:32.201361  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2498 01:03:32.211155  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2499 01:03:32.222160  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2500 01:03:32.231886  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2501 01:03:32.242945  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2502 01:03:32.252618  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2503 01:03:32.263763  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2504 01:03:32.273490  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2505 01:03:32.284528  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2506 01:03:32.300586  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2507 01:03:32.310163  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2508 01:03:32.321275  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2509 01:03:32.335940  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2510 01:03:32.346943  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2511 01:03:32.355651  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2512 01:03:32.372611  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2513 01:03:32.383652  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2514 01:03:32.394882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2515 01:03:32.404721  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2516 01:03:32.421919  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2517 01:03:32.433090  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2518 01:03:32.444084  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2519 01:03:32.455041  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2520 01:03:32.461202  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2521 01:03:32.472093  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2522 01:03:32.478208  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2523 01:03:32.489270  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2524 01:03:32.495381  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2525 01:03:32.503943  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2526 01:03:32.514939  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2527 01:03:32.520913  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2528 01:03:32.532030  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2529 01:03:32.541742  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2530 01:03:32.546690  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2531 01:03:32.557774  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2532 01:03:32.567430  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 2533 01:03:32.578517  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 2534 01:03:32.588241  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2535 01:03:32.599225  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2536 01:03:32.609185  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2537 01:03:32.620144  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2538 01:03:32.624952  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2539 01:03:32.629933  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2540 01:03:32.641074  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2541 01:03:32.641460  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2542 01:03:32.650835  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2543 01:03:32.656966  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2544 01:03:32.666577  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2545 01:03:32.671626  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2546 01:03:32.681627  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2547 01:03:32.692638  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2548 01:03:32.698716  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2549 01:03:32.703625  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2550 01:03:32.713344  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2551 01:03:32.724347  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2552 01:03:32.729125  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2553 01:03:32.740269  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2554 01:03:32.745206  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2555 01:03:32.754941  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2556 01:03:32.761029  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2557 01:03:32.770734  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2558 01:03:32.781819  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2559 01:03:32.786739  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2560 01:03:32.796543  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2561 01:03:32.802691  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2562 01:03:32.812276  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2563 01:03:32.823390  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2564 01:03:32.828256  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2565 01:03:32.838040  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2566 01:03:32.844198  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2567 01:03:32.853815  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2568 01:03:32.858821  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2569 01:03:32.869942  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2570 01:03:32.879721  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2571 01:03:32.885793  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2572 01:03:32.895509  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2573 01:03:32.906676  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 2574 01:03:32.916273  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 2575 01:03:32.927394  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 2576 01:03:32.937057  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 2577 01:03:32.948158  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 2578 01:03:32.957833  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 2579 01:03:32.968900  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 2580 01:03:32.978668  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 2581 01:03:32.989766  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2582 01:03:32.994657  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2583 01:03:33.004508  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2584 01:03:33.015470  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2585 01:03:33.020284  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2586 01:03:33.031506  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2587 01:03:33.041106  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2588 01:03:33.046118  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2589 01:03:33.057122  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2590 01:03:33.066885  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2591 01:03:33.073072  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2592 01:03:33.082661  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2593 01:03:33.087832  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2594 01:03:33.097607  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2595 01:03:33.103161  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2596 01:03:33.112476  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2597 01:03:33.122030  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2598 01:03:33.126916  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2599 01:03:33.137939  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2600 01:03:33.144063  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2601 01:03:33.153639  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2602 01:03:33.164949  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2603 01:03:33.168558  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2604 01:03:33.174560  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2605 01:03:33.179596  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2606 01:03:33.190534  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2607 01:03:33.200375  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2608 01:03:33.206444  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2609 01:03:33.216287  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2610 01:03:33.227388  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2611 01:03:33.232333  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2612 01:03:33.242071  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2613 01:03:33.253033  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2614 01:03:33.262893  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2615 01:03:33.273937  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2616 01:03:33.280133  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2617 01:03:33.286165  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2618 01:03:33.291067  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2619 01:03:33.297152  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2620 01:03:33.302053  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2621 01:03:33.308211  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2622 01:03:33.319205  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2623 01:03:33.325334  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2624 01:03:33.330270  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2625 01:03:33.336296  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2626 01:03:33.342441  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2627 01:03:33.347455  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2628 01:03:33.353646  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2629 01:03:33.358488  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2630 01:03:33.364551  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2631 01:03:33.370657  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2632 01:03:33.375562  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2633 01:03:33.381551  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2634 01:03:33.386487  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2635 01:03:33.392566  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2636 01:03:33.397543  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2637 01:03:33.403632  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2638 01:03:33.409779  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2639 01:03:33.414719  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2640 01:03:33.420915  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2641 01:03:33.425804  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2642 01:03:33.430674  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2643 01:03:33.436694  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2644 01:03:33.441771  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2645 01:03:33.447937  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2646 01:03:33.454014  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2647 01:03:33.458933  dt_test_unprobed_devices_sh_opp-table skip
 2648 01:03:33.464959  dt_test_unprobed_devices_sh_soc skip
 2649 01:03:33.465340  dt_test_unprobed_devices_sh_sound pass
 2650 01:03:33.470010  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2651 01:03:33.476110  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2652 01:03:33.487144  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2653 01:03:33.487528  dt_test_unprobed_devices_sh fail
 2654 01:03:33.493936  + ../../utils/send-to-lava.sh ./output/result.txt
 2655 01:03:33.629036  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2656 01:03:33.630220  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2658 01:03:33.847561  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2659 01:03:33.848186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2661 01:03:34.082296  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2662 01:03:34.082910  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2664 01:03:34.315784  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2665 01:03:34.316403  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2667 01:03:34.550502  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2668 01:03:34.551118  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2670 01:03:34.803172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2671 01:03:34.803790  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2673 01:03:35.018846  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2674 01:03:35.019470  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2676 01:03:35.273477  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2677 01:03:35.274100  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2679 01:03:35.462742  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2680 01:03:35.463367  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2682 01:03:35.726062  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2683 01:03:35.726683  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2685 01:03:35.985318  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2686 01:03:35.985976  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2688 01:03:36.187747  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2689 01:03:36.188370  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2691 01:03:36.415719  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2692 01:03:36.416342  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2694 01:03:36.632750  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2695 01:03:36.633394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2697 01:03:36.848811  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2698 01:03:36.849479  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2700 01:03:37.057008  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2701 01:03:37.057652  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2703 01:03:37.289636  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2704 01:03:37.290257  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2706 01:03:37.498763  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2707 01:03:37.499391  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2709 01:03:37.744702  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2710 01:03:37.745351  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2712 01:03:37.960455  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2713 01:03:37.961120  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2715 01:03:38.174778  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2716 01:03:38.175395  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2718 01:03:38.409895  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2719 01:03:38.410514  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2721 01:03:38.662255  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2722 01:03:38.662876  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2724 01:03:38.879728  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2725 01:03:38.880354  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2727 01:03:39.094068  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2728 01:03:39.094697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2730 01:03:39.354732  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2731 01:03:39.355356  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2733 01:03:39.585033  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2734 01:03:39.585655  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2736 01:03:39.828558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2737 01:03:39.829197  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2739 01:03:40.054551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2740 01:03:40.055166  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2742 01:03:40.290907  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2743 01:03:40.291526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2745 01:03:40.528434  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2746 01:03:40.529096  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2748 01:03:40.755432  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2749 01:03:40.756054  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2751 01:03:40.969675  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2752 01:03:40.970325  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2754 01:03:41.178811  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2755 01:03:41.179451  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2757 01:03:41.396438  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2758 01:03:41.397084  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2760 01:03:41.629790  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2761 01:03:41.630407  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2763 01:03:41.878966  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2764 01:03:41.879594  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2766 01:03:42.128908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2767 01:03:42.129570  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2769 01:03:42.348999  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2770 01:03:42.349633  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2772 01:03:42.574928  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2773 01:03:42.575546  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2775 01:03:42.800062  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2776 01:03:42.800679  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2778 01:03:43.033793  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2779 01:03:43.034409  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2781 01:03:43.261718  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2782 01:03:43.262353  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2784 01:03:43.493406  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2785 01:03:43.494026  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2787 01:03:43.709178  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2788 01:03:43.709798  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2790 01:03:43.924766  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2791 01:03:43.925405  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2793 01:03:44.163771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2794 01:03:44.164392  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2796 01:03:44.382698  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2797 01:03:44.383320  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2799 01:03:44.608883  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2800 01:03:44.609503  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2802 01:03:44.842754  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2803 01:03:44.843373  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2805 01:03:45.066399  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2806 01:03:45.067014  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2808 01:03:45.301049  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2809 01:03:45.301697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2811 01:03:45.526496  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2812 01:03:45.527141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2814 01:03:45.759904  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2815 01:03:45.760523  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2817 01:03:46.043127  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2818 01:03:46.043759  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2820 01:03:46.276836  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2821 01:03:46.277453  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2823 01:03:46.517696  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2824 01:03:46.518313  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2826 01:03:46.764063  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2827 01:03:46.764681  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2829 01:03:46.996443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2830 01:03:46.997079  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2832 01:03:47.219283  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2833 01:03:47.219898  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2835 01:03:47.467511  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2836 01:03:47.468131  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2838 01:03:47.713753  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2839 01:03:47.714373  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2841 01:03:47.952431  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2842 01:03:47.953092  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2844 01:03:48.187805  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2845 01:03:48.188424  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2847 01:03:48.414240  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2848 01:03:48.414858  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2850 01:03:48.654008  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2851 01:03:48.654628  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2853 01:03:48.879230  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2854 01:03:48.879846  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2856 01:03:49.087172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2857 01:03:49.087792  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2859 01:03:49.323982  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2860 01:03:49.324601  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2862 01:03:49.578679  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2863 01:03:49.579304  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2865 01:03:49.820660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2866 01:03:49.821306  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2868 01:03:50.040433  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2869 01:03:50.041089  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2871 01:03:50.265719  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2872 01:03:50.266335  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2874 01:03:50.506958  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2875 01:03:50.507576  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2877 01:03:50.740698  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2878 01:03:50.741355  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2880 01:03:50.941533  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2881 01:03:50.942151  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2883 01:03:51.231152  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2884 01:03:51.231769  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2886 01:03:51.456339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2887 01:03:51.456954  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2889 01:03:51.698489  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2890 01:03:51.699110  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2892 01:03:51.924518  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2893 01:03:51.925158  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2895 01:03:52.143456  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2896 01:03:52.144073  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2898 01:03:52.367304  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2899 01:03:52.367924  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2901 01:03:52.607136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2902 01:03:52.607752  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2904 01:03:52.817123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2905 01:03:52.817764  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2907 01:03:53.056894  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2908 01:03:53.057558  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2910 01:03:53.294469  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2911 01:03:53.295089  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2913 01:03:53.518355  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2914 01:03:53.518970  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2916 01:03:53.767713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2917 01:03:53.768328  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2919 01:03:54.010891  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2920 01:03:54.011506  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2922 01:03:54.254958  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2923 01:03:54.255576  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2925 01:03:54.471621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2926 01:03:54.472271  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2928 01:03:54.685247  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2929 01:03:54.685868  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2931 01:03:54.905271  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2932 01:03:54.905888  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2934 01:03:55.131447  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2935 01:03:55.132071  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2937 01:03:55.360942  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2938 01:03:55.361585  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2940 01:03:55.577000  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2941 01:03:55.577624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2943 01:03:55.792480  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2944 01:03:55.793128  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2946 01:03:56.017244  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2947 01:03:56.017863  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2949 01:03:56.269459  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2950 01:03:56.270093  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2952 01:03:56.473194  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2953 01:03:56.473820  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2955 01:03:56.680390  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2956 01:03:56.681010  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2958 01:03:56.907376  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2959 01:03:56.907993  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2961 01:03:57.117497  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2962 01:03:57.118116  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2964 01:03:57.337990  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2965 01:03:57.338618  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2967 01:03:57.564146  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2968 01:03:57.564764  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 2970 01:03:57.800655  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 2971 01:03:57.801308  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 2973 01:03:58.022577  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 2974 01:03:58.023199  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 2976 01:03:58.273632  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 2977 01:03:58.274275  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 2979 01:03:58.486584  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 2980 01:03:58.487226  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 2982 01:03:58.719507  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 2983 01:03:58.720149  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 2985 01:03:58.925571  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 2986 01:03:58.926205  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 2988 01:03:59.149572  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 2989 01:03:59.150194  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 2991 01:03:59.368702  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 2992 01:03:59.369348  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 2994 01:03:59.620040  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 2995 01:03:59.620658  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 2997 01:03:59.846628  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 2998 01:03:59.847246  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3000 01:04:00.062538  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3001 01:04:00.063170  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3003 01:04:00.277447  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3004 01:04:00.278076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3006 01:04:00.513347  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3007 01:04:00.513966  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3009 01:04:00.766126  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3010 01:04:00.766756  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3012 01:04:01.004754  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3013 01:04:01.005398  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3015 01:04:01.219605  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3017 01:04:01.222687  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3018 01:04:01.450042  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3020 01:04:01.453049  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3021 01:04:01.689143  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3023 01:04:01.691189  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3024 01:04:01.909683  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3025 01:04:01.910305  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3027 01:04:02.133576  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3028 01:04:02.134197  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3030 01:04:02.353130  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3031 01:04:02.353757  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3033 01:04:02.597825  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3034 01:04:02.598461  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3036 01:04:02.811968  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3037 01:04:02.812588  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3039 01:04:03.018917  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3040 01:04:03.019558  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3042 01:04:03.252815  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3043 01:04:03.253435  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3045 01:04:03.497416  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3046 01:04:03.498036  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3048 01:04:03.777786  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3049 01:04:03.778410  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3051 01:04:04.027964  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3052 01:04:04.028581  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3054 01:04:04.236817  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3055 01:04:04.237449  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3057 01:04:04.462321  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3058 01:04:04.462938  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3060 01:04:04.678603  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3061 01:04:04.679222  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3063 01:04:04.886528  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3064 01:04:04.887141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3066 01:04:05.107131  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 3067 01:04:05.107748  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 3069 01:04:05.332122  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 3070 01:04:05.332755  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 3072 01:04:05.562495  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3073 01:04:05.563115  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3075 01:04:05.787172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3076 01:04:05.787803  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3078 01:04:06.040524  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3079 01:04:06.041166  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3081 01:04:06.256688  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3082 01:04:06.257340  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3084 01:04:06.546871  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3085 01:04:06.547489  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3087 01:04:06.743483  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3088 01:04:06.744098  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3090 01:04:06.966647  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3091 01:04:06.967266  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3093 01:04:07.243205  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3094 01:04:07.243590  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3096 01:04:07.483434  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3097 01:04:07.483886  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3099 01:04:07.705101  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3100 01:04:07.705785  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3102 01:04:07.941629  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3103 01:04:07.942249  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3105 01:04:08.164952  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3106 01:04:08.165569  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3108 01:04:08.390626  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3109 01:04:08.391249  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3111 01:04:08.590759  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3112 01:04:08.591378  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3114 01:04:08.854314  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3115 01:04:08.854931  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3117 01:04:09.106226  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3118 01:04:09.106890  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3120 01:04:09.321344  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3121 01:04:09.321966  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3123 01:04:09.543082  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3124 01:04:09.543698  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3126 01:04:09.791821  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3127 01:04:09.792439  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3129 01:04:10.040565  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3130 01:04:10.041266  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3132 01:04:10.290637  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3133 01:04:10.291254  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3135 01:04:10.514862  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3136 01:04:10.515522  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3138 01:04:10.742584  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3139 01:04:10.743204  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3141 01:04:10.957935  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3142 01:04:10.958550  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3144 01:04:11.176402  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3145 01:04:11.177040  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3147 01:04:11.394335  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3148 01:04:11.394960  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3150 01:04:11.742830  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3151 01:04:11.743464  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3153 01:04:12.004425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3154 01:04:12.005072  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3156 01:04:12.211401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3157 01:04:12.212026  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3159 01:04:12.428454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3160 01:04:12.429092  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3162 01:04:12.675584  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3163 01:04:12.676201  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3165 01:04:12.887519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3166 01:04:12.888151  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3168 01:04:13.103658  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3169 01:04:13.104276  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3171 01:04:13.354588  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3172 01:04:13.355211  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3174 01:04:13.569909  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3175 01:04:13.570550  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3177 01:04:13.805842  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3178 01:04:13.806458  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3180 01:04:14.011287  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3181 01:04:14.011910  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3183 01:04:14.263383  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3184 01:04:14.264008  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3186 01:04:14.481935  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3187 01:04:14.482556  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3189 01:04:14.733799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 3190 01:04:14.734418  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 3192 01:04:14.990848  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 3193 01:04:14.991497  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 3195 01:04:15.232488  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 3196 01:04:15.233152  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 3198 01:04:15.460505  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 3199 01:04:15.461139  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 3201 01:04:15.674969  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 3202 01:04:15.675587  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 3204 01:04:15.926431  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 3205 01:04:15.927061  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 3207 01:04:16.165612  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 3208 01:04:16.166240  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 3210 01:04:16.376378  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 3211 01:04:16.377035  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 3213 01:04:16.584408  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3214 01:04:16.585162  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3216 01:04:16.841679  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3217 01:04:16.842311  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3219 01:04:17.067512  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3220 01:04:17.068135  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3222 01:04:17.317297  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3223 01:04:17.317915  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3225 01:04:17.573568  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3226 01:04:17.574187  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3228 01:04:17.793271  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3229 01:04:17.793912  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3231 01:04:18.023453  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3232 01:04:18.024070  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3234 01:04:18.227107  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3235 01:04:18.227725  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3237 01:04:18.464346  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3238 01:04:18.464962  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3240 01:04:18.694133  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3241 01:04:18.694747  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3243 01:04:18.918875  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3244 01:04:18.919494  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3246 01:04:19.154166  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3247 01:04:19.154786  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3249 01:04:19.392134  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3250 01:04:19.392813  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3252 01:04:19.611550  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3253 01:04:19.612172  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3255 01:04:19.895829  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3256 01:04:19.896446  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3258 01:04:20.141858  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3259 01:04:20.142473  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3261 01:04:20.361997  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3262 01:04:20.362613  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3264 01:04:20.601547  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3265 01:04:20.602161  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3267 01:04:20.841887  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3268 01:04:20.842532  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3270 01:04:21.096898  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3271 01:04:21.097516  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3273 01:04:21.369920  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3274 01:04:21.370534  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3276 01:04:21.604263  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3277 01:04:21.604878  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3279 01:04:21.837642  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3280 01:04:21.838284  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3282 01:04:22.050859  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3283 01:04:22.051476  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3285 01:04:22.334315  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3286 01:04:22.334933  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3288 01:04:22.573822  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3289 01:04:22.574464  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3291 01:04:22.828626  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3292 01:04:22.829011  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3294 01:04:23.082216  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3295 01:04:23.082693  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3297 01:04:23.300754  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3298 01:04:23.301426  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3300 01:04:23.524478  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3301 01:04:23.525116  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3303 01:04:23.731336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3304 01:04:23.731995  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3306 01:04:23.968931  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3307 01:04:23.969597  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3309 01:04:24.174672  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3310 01:04:24.175290  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3312 01:04:24.415217  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3313 01:04:24.415838  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3315 01:04:24.643257  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3316 01:04:24.643883  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3318 01:04:24.864196  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3319 01:04:24.864837  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3321 01:04:25.081263  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3322 01:04:25.081921  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3324 01:04:25.338188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3325 01:04:25.338806  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3327 01:04:25.554992  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3328 01:04:25.555610  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3330 01:04:25.773123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3331 01:04:25.773739  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3333 01:04:26.024198  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3334 01:04:26.024838  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3336 01:04:26.287283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3338 01:04:26.290275  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3339 01:04:26.497400  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3340 01:04:26.498016  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3342 01:04:26.725094  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3343 01:04:26.725751  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3345 01:04:26.923245  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3346 01:04:26.923881  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3348 01:04:27.147489  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3349 01:04:27.148106  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3351 01:04:27.360276  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3352 01:04:27.360875  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3354 01:04:27.575105  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3355 01:04:27.575724  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3357 01:04:27.808911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3358 01:04:27.809525  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3360 01:04:28.073174  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3361 01:04:28.073797  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3363 01:04:28.251268  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3364 01:04:28.251893  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3366 01:04:28.500663  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3367 01:04:28.501305  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3369 01:04:28.727042  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3370 01:04:28.727659  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3372 01:04:28.936465  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3373 01:04:28.937102  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3375 01:04:29.167155  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3376 01:04:29.167773  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3378 01:04:29.375423  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3379 01:04:29.376042  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3381 01:04:29.610255  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3382 01:04:29.610873  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3384 01:04:29.802883  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3385 01:04:29.803525  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3387 01:04:30.018674  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3388 01:04:30.019288  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3390 01:04:30.203987  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3391 01:04:30.204602  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3393 01:04:30.407237  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3394 01:04:30.407854  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3396 01:04:30.628167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3397 01:04:30.628856  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3399 01:04:30.852341  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3400 01:04:30.852961  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3402 01:04:31.061779  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3403 01:04:31.062394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3405 01:04:31.280729  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3406 01:04:31.281369  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3408 01:04:31.484898  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3409 01:04:31.485512  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3411 01:04:31.668664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3412 01:04:31.669304  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3414 01:04:31.887502  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3415 01:04:31.888119  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3417 01:04:32.279331  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3418 01:04:32.280100  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3420 01:04:32.510691  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3421 01:04:32.511309  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3423 01:04:32.699163  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3424 01:04:32.699782  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3426 01:04:32.917247  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3427 01:04:32.917901  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3429 01:04:33.110358  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3430 01:04:33.110972  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3432 01:04:33.116575  + set +x
 3433 01:04:33.117217  Received signal: <ENDRUN> 1_kselftest-dt 1214554_1.6.2.4.5
 3434 01:04:33.117557  Ending use of test pattern.
 3435 01:04:33.117858  Ending test lava.1_kselftest-dt (1214554_1.6.2.4.5), duration 273.64
 3437 01:04:33.119915  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1214554_1.6.2.4.5>
 3438 01:04:33.217308  <LAVA_TEST_RUNNER EXIT>
 3439 01:04:33.217922  ok: lava_test_shell seems to have completed
 3440 01:04:33.225507  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3441 01:04:33.226944  end: 3.1 lava-test-shell (duration 00:04:35) [common]
 3442 01:04:33.227354  end: 3 lava-test-retry (duration 00:04:35) [common]
 3443 01:04:33.227775  start: 4 finalize (timeout 00:02:15) [common]
 3444 01:04:33.228202  start: 4.1 power-off (timeout 00:00:30) [common]
 3445 01:04:33.228695  Calling: 'drpm' 'lf-bbb-02' 'off'
 3446 01:04:33.622725  >> OFF

 3447 01:04:33.624092  Returned 0 in 0 seconds
 3448 01:04:33.725090  end: 4.1 power-off (duration 00:00:00) [common]
 3450 01:04:33.726220  start: 4.2 read-feedback (timeout 00:02:15) [common]
 3451 01:04:33.727116  Listened to connection for namespace 'common' for up to 1s
 3452 01:04:33.727796  Listened to connection for namespace 'common' for up to 1s
 3453 01:04:34.727303  Finalising connection for namespace 'common'
 3454 01:04:34.727837  Disconnecting from shell: Finalise
 3455 01:04:34.728212  / # 
 3456 01:04:34.828986  end: 4.2 read-feedback (duration 00:00:01) [common]
 3457 01:04:34.829494  end: 4 finalize (duration 00:00:02) [common]
 3458 01:04:34.830022  Cleaning after the job
 3459 01:04:34.830476  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/ramdisk
 3460 01:04:34.836687  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/kernel
 3461 01:04:34.841702  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/dtb
 3462 01:04:34.842425  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/nfsrootfs
 3463 01:04:34.954303  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214554/tftp-deploy-29f6vuq7/modules
 3464 01:04:34.959568  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1214554
 3465 01:04:36.370313  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1214554
 3466 01:04:36.370648  Job finished correctly