Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 01:40:25.473063 lava-dispatcher, installed at version: 2023.08
2 01:40:25.473362 start: 0 validate
3 01:40:25.473558 Start time: 2024-11-01 01:40:25.473547+00:00 (UTC)
4 01:40:25.473786 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 01:40:25.976683 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 01:40:26.096023 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 01:40:26.209670 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 01:40:26.322919 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 01:40:26.441215 validate duration: 0.97
11 01:40:26.441976 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 01:40:26.442317 start: 1.1 download-retry (timeout 00:10:00) [common]
13 01:40:26.442625 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 01:40:26.443092 Not decompressing ramdisk as can be used compressed.
15 01:40:26.443388 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 01:40:26.443626 saving as /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/ramdisk/initrd.cpio.gz
17 01:40:26.443867 total size: 4775763 (4 MB)
18 01:40:26.670151 progress 0 % (0 MB)
19 01:40:27.006108 progress 5 % (0 MB)
20 01:40:27.119019 progress 10 % (0 MB)
21 01:40:27.255824 progress 15 % (0 MB)
22 01:40:27.342642 progress 20 % (0 MB)
23 01:40:27.366722 progress 25 % (1 MB)
24 01:40:27.371634 progress 30 % (1 MB)
25 01:40:27.577126 progress 35 % (1 MB)
26 01:40:27.581830 progress 40 % (1 MB)
27 01:40:27.672584 progress 45 % (2 MB)
28 01:40:27.701392 progress 50 % (2 MB)
29 01:40:27.806649 progress 55 % (2 MB)
30 01:40:27.908197 progress 60 % (2 MB)
31 01:40:27.931843 progress 65 % (2 MB)
32 01:40:28.037884 progress 70 % (3 MB)
33 01:40:28.137273 progress 75 % (3 MB)
34 01:40:28.237167 progress 80 % (3 MB)
35 01:40:28.262464 progress 85 % (3 MB)
36 01:40:28.365733 progress 90 % (4 MB)
37 01:40:28.464945 progress 95 % (4 MB)
38 01:40:28.488200 progress 100 % (4 MB)
39 01:40:28.488973 4 MB downloaded in 2.05 s (2.23 MB/s)
40 01:40:28.489462 end: 1.1.1 http-download (duration 00:00:02) [common]
42 01:40:28.490304 end: 1.1 download-retry (duration 00:00:02) [common]
43 01:40:28.490600 start: 1.2 download-retry (timeout 00:09:58) [common]
44 01:40:28.490886 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 01:40:28.491290 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 01:40:28.491519 saving as /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/kernel/zImage
47 01:40:28.491736 total size: 11440640 (10 MB)
48 01:40:28.491954 No compression specified
49 01:40:28.607379 progress 0 % (0 MB)
50 01:40:28.940296 progress 5 % (0 MB)
51 01:40:29.169665 progress 10 % (1 MB)
52 01:40:29.401715 progress 15 % (1 MB)
53 01:40:29.628869 progress 20 % (2 MB)
54 01:40:29.939934 progress 25 % (2 MB)
55 01:40:30.163678 progress 30 % (3 MB)
56 01:40:30.390643 progress 35 % (3 MB)
57 01:40:30.612722 progress 40 % (4 MB)
58 01:40:30.838433 progress 45 % (4 MB)
59 01:40:31.059583 progress 50 % (5 MB)
60 01:40:31.284246 progress 55 % (6 MB)
61 01:40:31.505998 progress 60 % (6 MB)
62 01:40:31.724462 progress 65 % (7 MB)
63 01:40:31.949814 progress 70 % (7 MB)
64 01:40:32.164196 progress 75 % (8 MB)
65 01:40:32.387863 progress 80 % (8 MB)
66 01:40:32.534204 progress 85 % (9 MB)
67 01:40:32.757205 progress 90 % (9 MB)
68 01:40:32.981234 progress 95 % (10 MB)
69 01:40:33.197419 progress 100 % (10 MB)
70 01:40:33.197803 10 MB downloaded in 4.71 s (2.32 MB/s)
71 01:40:33.198205 end: 1.2.1 http-download (duration 00:00:05) [common]
73 01:40:33.198925 end: 1.2 download-retry (duration 00:00:05) [common]
74 01:40:33.199188 start: 1.3 download-retry (timeout 00:09:53) [common]
75 01:40:33.199441 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 01:40:33.199796 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 01:40:33.199999 saving as /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/dtb/am335x-boneblack.dtb
78 01:40:33.200189 total size: 70568 (0 MB)
79 01:40:33.200380 No compression specified
80 01:40:33.318424 progress 46 % (0 MB)
81 01:40:33.321252 progress 92 % (0 MB)
82 01:40:33.322233 progress 100 % (0 MB)
83 01:40:33.322624 0 MB downloaded in 0.12 s (0.55 MB/s)
84 01:40:33.323030 end: 1.3.1 http-download (duration 00:00:00) [common]
86 01:40:33.323818 end: 1.3 download-retry (duration 00:00:00) [common]
87 01:40:33.324100 start: 1.4 download-retry (timeout 00:09:53) [common]
88 01:40:33.324384 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 01:40:33.324755 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 01:40:33.324982 saving as /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/nfsrootfs/full.rootfs.tar
91 01:40:33.325193 total size: 117747780 (112 MB)
92 01:40:33.325411 Using unxz to decompress xz
93 01:40:33.441472 progress 0 % (0 MB)
94 01:40:36.117742 progress 5 % (5 MB)
95 01:40:38.360903 progress 10 % (11 MB)
96 01:40:40.587463 progress 15 % (16 MB)
97 01:40:42.782121 progress 20 % (22 MB)
98 01:40:44.639092 progress 25 % (28 MB)
99 01:40:46.154737 progress 30 % (33 MB)
100 01:40:47.361152 progress 35 % (39 MB)
101 01:40:48.307338 progress 40 % (44 MB)
102 01:40:49.156641 progress 45 % (50 MB)
103 01:40:49.849705 progress 50 % (56 MB)
104 01:40:50.462708 progress 55 % (61 MB)
105 01:40:51.020973 progress 60 % (67 MB)
106 01:40:51.529085 progress 65 % (73 MB)
107 01:40:52.114713 progress 70 % (78 MB)
108 01:40:52.714262 progress 75 % (84 MB)
109 01:40:53.284028 progress 80 % (89 MB)
110 01:40:53.831708 progress 85 % (95 MB)
111 01:40:54.356057 progress 90 % (101 MB)
112 01:40:54.863304 progress 95 % (106 MB)
113 01:40:55.366470 progress 100 % (112 MB)
114 01:40:55.370158 112 MB downloaded in 22.04 s (5.09 MB/s)
115 01:40:55.370497 end: 1.4.1 http-download (duration 00:00:22) [common]
117 01:40:55.371097 end: 1.4 download-retry (duration 00:00:22) [common]
118 01:40:55.371313 start: 1.5 download-retry (timeout 00:09:31) [common]
119 01:40:55.371526 start: 1.5.1 http-download (timeout 00:09:31) [common]
120 01:40:55.371843 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 01:40:55.372003 saving as /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/modules/modules.tar
122 01:40:55.372166 total size: 6604344 (6 MB)
123 01:40:55.372332 Using unxz to decompress xz
124 01:40:55.487772 progress 0 % (0 MB)
125 01:40:55.718431 progress 5 % (0 MB)
126 01:40:55.934905 progress 10 % (0 MB)
127 01:40:55.964796 progress 15 % (0 MB)
128 01:40:56.043545 progress 20 % (1 MB)
129 01:40:56.073280 progress 25 % (1 MB)
130 01:40:56.098395 progress 30 % (1 MB)
131 01:40:56.268225 progress 35 % (2 MB)
132 01:40:56.298793 progress 40 % (2 MB)
133 01:40:56.324370 progress 45 % (2 MB)
134 01:40:56.348066 progress 50 % (3 MB)
135 01:40:56.516862 progress 55 % (3 MB)
136 01:40:56.542409 progress 60 % (3 MB)
137 01:40:56.568038 progress 65 % (4 MB)
138 01:40:56.640844 progress 70 % (4 MB)
139 01:40:56.734168 progress 75 % (4 MB)
140 01:40:56.817068 progress 80 % (5 MB)
141 01:40:56.866356 progress 85 % (5 MB)
142 01:40:56.959876 progress 90 % (5 MB)
143 01:40:57.046388 progress 95 % (6 MB)
144 01:40:57.087952 progress 100 % (6 MB)
145 01:40:57.091452 6 MB downloaded in 1.72 s (3.66 MB/s)
146 01:40:57.091836 end: 1.5.1 http-download (duration 00:00:02) [common]
148 01:40:57.092520 end: 1.5 download-retry (duration 00:00:02) [common]
149 01:40:57.092794 start: 1.6 prepare-tftp-overlay (timeout 00:09:29) [common]
150 01:40:57.093040 start: 1.6.1 extract-nfsrootfs (timeout 00:09:29) [common]
151 01:41:02.598034 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1
152 01:41:02.598340 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 01:41:02.598493 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
154 01:41:02.598788 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg
155 01:41:02.598977 makedir: /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin
156 01:41:02.599121 makedir: /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/tests
157 01:41:02.599273 makedir: /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/results
158 01:41:02.599434 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-add-keys
159 01:41:02.599658 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-add-sources
160 01:41:02.599837 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-background-process-start
161 01:41:02.600015 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-background-process-stop
162 01:41:02.600206 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-common-functions
163 01:41:02.600434 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-echo-ipv4
164 01:41:02.600654 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-install-packages
165 01:41:02.600882 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-installed-packages
166 01:41:02.601054 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-os-build
167 01:41:02.601226 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-probe-channel
168 01:41:02.601399 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-probe-ip
169 01:41:02.601571 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-target-ip
170 01:41:02.601745 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-target-mac
171 01:41:02.601926 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-target-storage
172 01:41:02.602106 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-case
173 01:41:02.602282 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-event
174 01:41:02.602455 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-feedback
175 01:41:02.602629 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-raise
176 01:41:02.602811 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-reference
177 01:41:02.602987 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-runner
178 01:41:02.603164 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-set
179 01:41:02.603338 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-test-shell
180 01:41:02.603516 Updating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-add-keys (debian)
181 01:41:02.603747 Updating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-add-sources (debian)
182 01:41:02.603947 Updating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-install-packages (debian)
183 01:41:02.604146 Updating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-installed-packages (debian)
184 01:41:02.604344 Updating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/bin/lava-os-build (debian)
185 01:41:02.604520 Creating /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/environment
186 01:41:02.604655 LAVA metadata
187 01:41:02.604766 - LAVA_JOB_ID=1214595
188 01:41:02.604866 - LAVA_DISPATCHER_IP=192.168.11.5
189 01:41:02.605016 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
190 01:41:02.605356 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 01:41:02.605508 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
192 01:41:02.605602 skipped lava-vland-overlay
193 01:41:02.605714 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 01:41:02.605833 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
195 01:41:02.605930 skipped lava-multinode-overlay
196 01:41:02.606042 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 01:41:02.606159 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
198 01:41:02.606260 Loading test definitions
199 01:41:02.606383 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
200 01:41:02.606483 Using /lava-1214595 at stage 0
201 01:41:02.606886 uuid=1214595_1.6.2.4.1 testdef=None
202 01:41:02.607015 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 01:41:02.607135 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
204 01:41:02.607747 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 01:41:02.608078 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
207 01:41:02.608898 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 01:41:02.609241 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
210 01:41:02.610027 runner path: /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/0/tests/0_timesync-off test_uuid 1214595_1.6.2.4.1
211 01:41:02.610225 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 01:41:02.610564 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
214 01:41:02.610664 Using /lava-1214595 at stage 0
215 01:41:02.610804 Fetching tests from https://github.com/kernelci/test-definitions.git
216 01:41:02.610908 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/0/tests/1_kselftest-dt'
217 01:41:07.291440 Running '/usr/bin/git checkout kernelci.org
218 01:41:07.511114 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 01:41:07.512053 uuid=1214595_1.6.2.4.5 testdef=None
220 01:41:07.512292 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 01:41:07.512868 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
223 01:41:07.514677 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 01:41:07.515250 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
226 01:41:07.517750 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 01:41:07.518344 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
229 01:41:07.520806 runner path: /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/0/tests/1_kselftest-dt test_uuid 1214595_1.6.2.4.5
230 01:41:07.521003 BOARD='beaglebone-black'
231 01:41:07.521162 BRANCH='mainline'
232 01:41:07.521313 SKIPFILE='/dev/null'
233 01:41:07.521462 SKIP_INSTALL='True'
234 01:41:07.521608 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 01:41:07.521759 TST_CASENAME=''
236 01:41:07.521905 TST_CMDFILES='dt'
237 01:41:07.522230 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 01:41:07.522761 Creating lava-test-runner.conf files
240 01:41:07.522912 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1214595/lava-overlay-kak3rssg/lava-1214595/0 for stage 0
241 01:41:07.523122 - 0_timesync-off
242 01:41:07.523281 - 1_kselftest-dt
243 01:41:07.523510 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 01:41:07.523710 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
245 01:41:15.968314 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 01:41:15.968520 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
247 01:41:15.968650 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 01:41:15.968805 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
249 01:41:15.968953 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
250 01:41:16.091721 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 01:41:16.092021 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
252 01:41:16.092190 extracting modules file /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1
253 01:41:16.394519 extracting modules file /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214595/extract-overlay-ramdisk-pcxbcw5v/ramdisk
254 01:41:16.698638 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 01:41:16.698858 start: 1.6.5 apply-overlay-tftp (timeout 00:09:10) [common]
256 01:41:16.698992 [common] Applying overlay to NFS
257 01:41:16.699099 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1214595/compress-overlay-nwlo1tbh/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1
258 01:41:17.887623 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 01:41:17.887839 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
260 01:41:17.887967 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
261 01:41:17.888096 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 01:41:17.888213 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 01:41:17.888332 start: 1.6.7 configure-preseed-file (timeout 00:09:09) [common]
264 01:41:17.888447 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 01:41:17.888564 start: 1.6.8 compress-ramdisk (timeout 00:09:09) [common]
266 01:41:17.888663 Building ramdisk /var/lib/lava/dispatcher/tmp/1214595/extract-overlay-ramdisk-pcxbcw5v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1214595/extract-overlay-ramdisk-pcxbcw5v/ramdisk
267 01:41:18.194042 >> 74899 blocks
268 01:41:20.133499 Adding RAMdisk u-boot header.
269 01:41:20.133787 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1214595/extract-overlay-ramdisk-pcxbcw5v/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1214595/extract-overlay-ramdisk-pcxbcw5v/ramdisk.cpio.gz.uboot
270 01:41:20.285548 output: Image Name:
271 01:41:20.285908 output: Created: Fri Nov 1 01:41:20 2024
272 01:41:20.286104 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 01:41:20.286311 output: Data Size: 14794737 Bytes = 14447.99 KiB = 14.11 MiB
274 01:41:20.286516 output: Load Address: 00000000
275 01:41:20.286726 output: Entry Point: 00000000
276 01:41:20.286933 output:
277 01:41:20.287279 rename /var/lib/lava/dispatcher/tmp/1214595/extract-overlay-ramdisk-pcxbcw5v/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot
278 01:41:20.287646 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 01:41:20.287949 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 01:41:20.288245 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
281 01:41:20.288471 No LXC device requested
282 01:41:20.288766 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 01:41:20.289068 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
284 01:41:20.289337 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 01:41:20.289544 Checking files for TFTP limit of 4294967296 bytes.
286 01:41:20.290874 end: 1 tftp-deploy (duration 00:00:54) [common]
287 01:41:20.291165 start: 2 uboot-action (timeout 00:05:00) [common]
288 01:41:20.291456 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 01:41:20.291723 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 01:41:20.292000 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 01:41:20.292414 substitutions:
292 01:41:20.292634 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 01:41:20.292890 - {DTB_ADDR}: 0x88000000
294 01:41:20.293109 - {DTB}: 1214595/tftp-deploy-t2u2o401/dtb/am335x-boneblack.dtb
295 01:41:20.293327 - {INITRD}: 1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot
296 01:41:20.293544 - {KERNEL_ADDR}: 0x82000000
297 01:41:20.293761 - {KERNEL}: 1214595/tftp-deploy-t2u2o401/kernel/zImage
298 01:41:20.293975 - {LAVA_MAC}: None
299 01:41:20.294201 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1
300 01:41:20.294417 - {NFS_SERVER_IP}: 192.168.11.5
301 01:41:20.294631 - {PRESEED_CONFIG}: None
302 01:41:20.294847 - {PRESEED_LOCAL}: None
303 01:41:20.295060 - {RAMDISK_ADDR}: 0x83000000
304 01:41:20.295273 - {RAMDISK}: 1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot
305 01:41:20.295482 - {ROOT_PART}: None
306 01:41:20.295688 - {ROOT}: None
307 01:41:20.295894 - {SERVER_IP}: 192.168.11.5
308 01:41:20.296098 - {TEE_ADDR}: 0x83000000
309 01:41:20.296305 - {TEE}: None
310 01:41:20.296514 Parsed boot commands:
311 01:41:20.296737 - setenv autoload no
312 01:41:20.296961 - setenv initrd_high 0xffffffff
313 01:41:20.297178 - setenv fdt_high 0xffffffff
314 01:41:20.297392 - dhcp
315 01:41:20.297607 - setenv serverip 192.168.11.5
316 01:41:20.297821 - tftp 0x82000000 1214595/tftp-deploy-t2u2o401/kernel/zImage
317 01:41:20.298037 - tftp 0x83000000 1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot
318 01:41:20.298255 - setenv initrd_size ${filesize}
319 01:41:20.298470 - tftp 0x88000000 1214595/tftp-deploy-t2u2o401/dtb/am335x-boneblack.dtb
320 01:41:20.298688 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 01:41:20.298912 - bootz 0x82000000 0x83000000 0x88000000
322 01:41:20.299204 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 01:41:20.299961 start: 2.3 connect-device (timeout 00:05:00) [common]
325 01:41:20.300182 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 01:41:20.660129 Setting prompt string to ['lava-test: # ']
327 01:41:20.660527 end: 2.3 connect-device (duration 00:00:00) [common]
328 01:41:20.660677 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 01:41:20.660867 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 01:41:20.661006 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 01:41:20.661322 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 01:41:21.026387 Returned 0 in 0 seconds
333 01:41:21.127292 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 01:41:21.128268 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 01:41:21.128618 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 01:41:21.128948 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 01:41:21.129234 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 01:41:21.130027 Trying 127.0.0.1...
340 01:41:21.130271 Connected to 127.0.0.1.
341 01:41:21.130529 Escape character is '^]'.
342 01:41:25.949537
343 01:41:25.953227 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 01:41:26.009918 Trying to boot from MMC2
345 01:41:26.058174 Loading Environment from EXT4... Card did not respond to voltage select!
346 01:41:26.125271
347 01:41:26.125606
348 01:41:26.130850 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 01:41:26.131173
350 01:41:26.135789 CPU : AM335X-GP rev 2.1
351 01:41:26.189715 I2C: ready
352 01:41:26.189991 DRAM: 512 MiB
353 01:41:26.243994 No match for driver 'omap_hsmmc'
354 01:41:26.249614 No match for driver 'omap_hsmmc'
355 01:41:26.249906 Some drivers were not found
356 01:41:26.255851 Reset Source: Power-on reset has occurred.
357 01:41:26.256132 RTC 32KCLK Source: External.
358 01:41:26.263401 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 01:41:26.276701 Loading Environment from EXT4... Card did not respond to voltage select!
360 01:41:26.341241 Board: BeagleBone Black
361 01:41:26.345084 <ethaddr> not set. Validating first E-fuse MAC
362 01:41:26.401775 BeagleBone Black:
363 01:41:26.402056 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 01:41:26.407236 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 01:41:26.413239 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 01:41:26.413520 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 01:41:26.418168 Net: eth0: MII MODE
368 01:41:26.427677 cpsw, usb_ether
369 01:41:26.427958 Press SPACE to abort autoboot in 2 seconds
370 01:41:26.478793 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 01:41:26.479189 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 01:41:26.479479 Setting prompt string to ['=> ']
373 01:41:26.479788 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 01:41:26.483150 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 01:41:26.483466 Sending with 10 millisecond of delay
377 01:41:27.618129 => setenv autoload no
378 01:41:27.628641 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 01:41:27.631046 setenv autoload no
380 01:41:27.631530 Sending with 10 millisecond of delay
382 01:41:29.428445 => setenv initrd_high 0xffffffff
383 01:41:29.438997 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 01:41:29.439515 setenv initrd_high 0xffffffff
385 01:41:29.439975 Sending with 10 millisecond of delay
387 01:41:31.056230 => setenv fdt_high 0xffffffff
388 01:41:31.066768 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 01:41:31.067225 setenv fdt_high 0xffffffff
390 01:41:31.067672 Sending with 10 millisecond of delay
392 01:41:31.359059 => dhcp
393 01:41:31.369468 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 01:41:31.369964 dhcp
395 01:41:31.370203 link up on port 0, speed 100, full duplex
396 01:41:31.370470 BOOTP broadcast 1
397 01:41:31.378437 DHCP client bound to address 192.168.11.6 (4 ms)
398 01:41:31.378883 Sending with 10 millisecond of delay
400 01:41:33.115659 => setenv serverip 192.168.11.5
401 01:41:33.126193 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 01:41:33.126724 setenv serverip 192.168.11.5
403 01:41:33.127212 Sending with 10 millisecond of delay
405 01:41:36.670031 => tftp 0x82000000 1214595/tftp-deploy-t2u2o401/kernel/zImage
406 01:41:36.680511 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 01:41:36.680990 tftp 0x82000000 1214595/tftp-deploy-t2u2o401/kernel/zImage
408 01:41:36.681222 link up on port 0, speed 100, full duplex
409 01:41:36.681434 Using cpsw device
410 01:41:36.684718 TFTP from server 192.168.11.5; our IP address is 192.168.11.6
411 01:41:36.690169 Filename '1214595/tftp-deploy-t2u2o401/kernel/zImage'.
412 01:41:36.789838 Load address: 0x82000000
413 01:41:36.874871 Loading: *#################################################################
414 01:41:37.050116 #################################################################
415 01:41:37.225837 #################################################################
416 01:41:37.400438 #################################################################
417 01:41:37.575437 #################################################################
418 01:41:37.761796 #################################################################
419 01:41:37.937525 #################################################################
420 01:41:38.113002 #################################################################
421 01:41:38.288897 #################################################################
422 01:41:38.486530 #################################################################
423 01:41:38.662511 #################################################################
424 01:41:38.825211 #################################################################
425 01:41:38.825487 5.1 MiB/s
426 01:41:38.825736 done
427 01:41:38.829102 Bytes transferred = 11440640 (ae9200 hex)
428 01:41:38.829569 Sending with 10 millisecond of delay
430 01:41:43.336126 => tftp 0x83000000 1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot
431 01:41:43.346615 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 01:41:43.347078 tftp 0x83000000 1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot
433 01:41:43.347325 link up on port 0, speed 100, full duplex
434 01:41:43.347559 Using cpsw device
435 01:41:43.350938 TFTP from server 192.168.11.5; our IP address is 192.168.11.6
436 01:41:43.411017 Filename '1214595/tftp-deploy-t2u2o401/ramdisk/ramdisk.cpio.gz.uboot'.
437 01:41:43.411290 Load address: 0x83000000
438 01:41:43.539254 Loading: *#################################################################
439 01:41:43.715540 #################################################################
440 01:41:43.891427 #################################################################
441 01:41:44.067129 #################################################################
442 01:41:44.264273 #################################################################
443 01:41:44.439788 #################################################################
444 01:41:44.613378 #################################################################
445 01:41:44.788375 #################################################################
446 01:41:44.964928 #################################################################
447 01:41:45.133328 #################################################################
448 01:41:45.306822 #################################################################
449 01:41:45.494623 #################################################################
450 01:41:45.664144 #################################################################
451 01:41:45.839233 #################################################################
452 01:41:46.012483 #################################################################
453 01:41:46.099746 #################################
454 01:41:46.100052 5.2 MiB/s
455 01:41:46.100319 done
456 01:41:46.103557 Bytes transferred = 14794801 (e1c031 hex)
457 01:41:46.104045 Sending with 10 millisecond of delay
459 01:41:47.961084 => setenv initrd_size ${filesize}
460 01:41:47.971598 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 01:41:47.972060 setenv initrd_size ${filesize}
462 01:41:47.972506 Sending with 10 millisecond of delay
464 01:41:52.177918 => tftp 0x88000000 1214595/tftp-deploy-t2u2o401/dtb/am335x-boneblack.dtb
465 01:41:52.188405 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 01:41:52.188887 tftp 0x88000000 1214595/tftp-deploy-t2u2o401/dtb/am335x-boneblack.dtb
467 01:41:52.189118 link up on port 0, speed 100, full duplex
468 01:41:52.189329 Using cpsw device
469 01:41:52.192650 TFTP from server 192.168.11.5; our IP address is 192.168.11.6
470 01:41:52.206133 Filename '1214595/tftp-deploy-t2u2o401/dtb/am335x-boneblack.dtb'.
471 01:41:52.206435 Load address: 0x88000000
472 01:41:52.221673 Loading: *#####
473 01:41:52.221906 4.8 MiB/s
474 01:41:52.222118 done
475 01:41:52.222325 Bytes transferred = 70568 (113a8 hex)
476 01:41:52.225185 Sending with 10 millisecond of delay
478 01:42:05.523809 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 01:42:05.534303 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 01:42:05.534756 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 01:42:05.535209 Sending with 10 millisecond of delay
483 01:42:07.874020 => bootz 0x82000000 0x83000000 0x88000000
484 01:42:07.884511 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 01:42:07.884846 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 01:42:07.885377 bootz 0x82000000 0x83000000 0x88000000
487 01:42:07.885615 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 01:42:07.886109 Image Name:
489 01:42:07.886406 Created: 2024-11-01 1:41:20 UTC
490 01:42:07.891744 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 01:42:07.895193 Data Size: 14794737 Bytes = 14.1 MiB
492 01:42:07.900825 Load Address: 00000000
493 01:42:07.901090 Entry Point: 00000000
494 01:42:08.041781 Verifying Checksum ... OK
495 01:42:08.042157 ## Flattened Device Tree blob at 88000000
496 01:42:08.048312 Booting using the fdt blob at 0x88000000
497 01:42:08.053263 Using Device Tree in place at 88000000, end 880143a7
498 01:42:08.060930
499 01:42:08.061207 Starting kernel ...
500 01:42:08.061429
501 01:42:08.061972 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 01:42:08.062270 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 01:42:08.062521 Setting prompt string to ['Linux version [0-9]']
504 01:42:08.062767 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 01:42:08.063023 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 01:42:08.901104 [ 0.000000] Booting Linux on physical CPU 0x0
507 01:42:08.907096 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 01:42:08.907418 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 01:42:08.907696 Setting prompt string to []
510 01:42:08.907963 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 01:42:08.908239 Using line separator: #'\n'#
512 01:42:08.908485 No login prompt set.
513 01:42:08.908753 Parsing kernel messages
514 01:42:08.908981 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 01:42:08.909427 [login-action] Waiting for messages, (timeout 00:04:11)
516 01:42:08.921321 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j358369-arm-gcc-12-multi-v7-defconfig-dqp9s) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov 1 00:32:11 UTC 2024
517 01:42:08.932684 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 01:42:08.938398 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 01:42:08.944143 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 01:42:08.949757 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 01:42:08.955518 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 01:42:08.962297 [ 0.000000] Memory policy: Data cache writeback
523 01:42:08.962553 [ 0.000000] efi: UEFI not found.
524 01:42:08.970458 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 01:42:08.976191 [ 0.000000] Zone ranges:
526 01:42:08.981903 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 01:42:08.987518 [ 0.000000] Normal empty
528 01:42:08.987775 [ 0.000000] HighMem empty
529 01:42:08.993300 [ 0.000000] Movable zone start for each node
530 01:42:08.993552 [ 0.000000] Early memory node ranges
531 01:42:09.004784 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 01:42:09.010116 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 01:42:09.035602 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 01:42:09.041253 [ 0.000000] AM335X ES2.1 (sgx neon)
535 01:42:09.053114 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
536 01:42:09.070700 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 01:42:09.082203 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 01:42:09.088072 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 01:42:09.093695 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 01:42:09.103869 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 01:42:09.132838 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 01:42:09.138819 <6>[ 0.000000] trace event string verifier disabled
543 01:42:09.139097 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 01:42:09.144570 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 01:42:09.156086 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 01:42:09.161693 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 01:42:09.168995 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 01:42:09.184139 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 01:42:09.201451 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 01:42:09.208125 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 01:42:09.301442 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 01:42:09.312813 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 01:42:09.319568 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 01:42:09.332637 <6>[ 0.019164] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 01:42:09.340089 <6>[ 0.034068] Console: colour dummy device 80x30
556 01:42:09.346136 Matched prompt #6: WARNING:
557 01:42:09.346431 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 01:42:09.351691 <3>[ 0.038967] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 01:42:09.357332 <3>[ 0.046038] This ensures that you still see kernel messages. Please
560 01:42:09.360647 <3>[ 0.052765] update your kernel commandline.
561 01:42:09.401192 <6>[ 0.057375] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 01:42:09.407064 <6>[ 0.096172] CPU: Testing write buffer coherency: ok
563 01:42:09.412987 <6>[ 0.101539] CPU0: Spectre v2: using BPIALL workaround
564 01:42:09.413265 <6>[ 0.107005] pid_max: default: 32768 minimum: 301
565 01:42:09.424309 <6>[ 0.112201] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 01:42:09.431325 <6>[ 0.120027] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 01:42:09.438435 <6>[ 0.129374] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 01:42:09.446848 <6>[ 0.136368] Setting up static identity map for 0x80300000 - 0x803000ac
569 01:42:09.452587 <6>[ 0.146024] rcu: Hierarchical SRCU implementation.
570 01:42:09.460289 <6>[ 0.151307] rcu: Max phase no-delay instances is 1000.
571 01:42:09.468860 <6>[ 0.162496] EFI services will not be available.
572 01:42:09.474688 <6>[ 0.167767] smp: Bringing up secondary CPUs ...
573 01:42:09.480435 <6>[ 0.172812] smp: Brought up 1 node, 1 CPU
574 01:42:09.486182 <6>[ 0.177212] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 01:42:09.492074 <6>[ 0.183981] CPU: All CPU(s) started in SVC mode.
576 01:42:09.512364 <6>[ 0.189163] Memory: 405992K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49056K reserved, 65536K cma-reserved, 0K highmem)
577 01:42:09.512651 <6>[ 0.205434] devtmpfs: initialized
578 01:42:09.534755 <6>[ 0.222524] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 01:42:09.546187 <6>[ 0.231099] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 01:42:09.552092 <6>[ 0.241564] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 01:42:09.562864 <6>[ 0.253890] pinctrl core: initialized pinctrl subsystem
582 01:42:09.572203 <6>[ 0.264571] DMI not present or invalid.
583 01:42:09.580535 <6>[ 0.270418] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 01:42:09.589978 <6>[ 0.279293] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 01:42:09.605130 <6>[ 0.290843] thermal_sys: Registered thermal governor 'step_wise'
586 01:42:09.605404 <6>[ 0.291008] cpuidle: using governor menu
587 01:42:09.632587 <6>[ 0.326579] No ATAGs?
588 01:42:09.638737 <6>[ 0.329225] hw-breakpoint: debug architecture 0x4 unsupported.
589 01:42:09.649131 <6>[ 0.341278] Serial: AMBA PL011 UART driver
590 01:42:09.681454 <6>[ 0.375360] iommu: Default domain type: Translated
591 01:42:09.690599 <6>[ 0.380711] iommu: DMA domain TLB invalidation policy: strict mode
592 01:42:09.717336 <5>[ 0.410629] SCSI subsystem initialized
593 01:42:09.723180 <6>[ 0.415512] usbcore: registered new interface driver usbfs
594 01:42:09.729044 <6>[ 0.421567] usbcore: registered new interface driver hub
595 01:42:09.735790 <6>[ 0.427355] usbcore: registered new device driver usb
596 01:42:09.741549 <6>[ 0.433870] pps_core: LinuxPPS API ver. 1 registered
597 01:42:09.753039 <6>[ 0.439257] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 01:42:09.760246 <6>[ 0.448984] PTP clock support registered
599 01:42:09.760481 <6>[ 0.453442] EDAC MC: Ver: 3.0.0
600 01:42:09.808886 <6>[ 0.500223] scmi_core: SCMI protocol bus registered
601 01:42:09.823880 <6>[ 0.517575] vgaarb: loaded
602 01:42:09.836579 <6>[ 0.530588] clocksource: Switched to clocksource dmtimer
603 01:42:09.873198 <6>[ 0.566744] NET: Registered PF_INET protocol family
604 01:42:09.885658 <6>[ 0.572440] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 01:42:09.892918 <6>[ 0.581292] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 01:42:09.898658 <6>[ 0.590182] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 01:42:09.907274 <6>[ 0.598459] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 01:42:09.918898 <6>[ 0.606746] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 01:42:09.924806 <6>[ 0.614473] TCP: Hash tables configured (established 4096 bind 4096)
610 01:42:09.930534 <6>[ 0.621396] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 01:42:09.936402 <6>[ 0.628406] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 01:42:09.945336 <6>[ 0.636019] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 01:42:10.036542 <6>[ 0.724793] RPC: Registered named UNIX socket transport module.
614 01:42:10.036956 <6>[ 0.731231] RPC: Registered udp transport module.
615 01:42:10.042291 <6>[ 0.736337] RPC: Registered tcp transport module.
616 01:42:10.048031 <6>[ 0.741456] RPC: Registered tcp-with-tls transport module.
617 01:42:10.061030 <6>[ 0.747365] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 01:42:10.061294 <6>[ 0.754286] PCI: CLS 0 bytes, default 64
619 01:42:10.068236 <5>[ 0.760070] Initialise system trusted keyrings
620 01:42:10.087764 <6>[ 0.778652] Trying to unpack rootfs image as initramfs...
621 01:42:10.173172 <6>[ 0.860907] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 01:42:10.177980 <6>[ 0.868384] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 01:42:10.197810 <5>[ 0.891723] NFS: Registering the id_resolver key type
624 01:42:10.203671 <5>[ 0.897314] Key type id_resolver registered
625 01:42:10.209411 <5>[ 0.902010] Key type id_legacy registered
626 01:42:10.215270 <6>[ 0.906453] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 01:42:10.224816 <6>[ 0.913670] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 01:42:10.294057 <5>[ 0.987967] Key type asymmetric registered
629 01:42:10.300023 <5>[ 0.992584] Asymmetric key parser 'x509' registered
630 01:42:10.311395 <6>[ 0.998012] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 01:42:10.311661 <6>[ 1.005938] io scheduler mq-deadline registered
632 01:42:10.317278 <6>[ 1.010885] io scheduler kyber registered
633 01:42:10.322815 <6>[ 1.015337] io scheduler bfq registered
634 01:42:10.440945 <6>[ 1.131102] ledtrig-cpu: registered to indicate activity on CPUs
635 01:42:10.726852 <6>[ 1.416790] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
636 01:42:10.761660 <6>[ 1.455371] msm_serial: driver initialized
637 01:42:10.767752 <6>[ 1.460155] SuperH (H)SCI(F) driver initialized
638 01:42:10.773613 <6>[ 1.465506] STMicroelectronics ASC driver initialized
639 01:42:10.778942 <6>[ 1.471179] STM32 USART driver initialized
640 01:42:10.907712 <6>[ 1.601045] brd: module loaded
641 01:42:10.958084 <6>[ 1.651286] loop: module loaded
642 01:42:10.995396 <6>[ 1.688402] CAN device driver interface
643 01:42:11.002106 <6>[ 1.693709] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
644 01:42:11.007853 <6>[ 1.700759] e1000e: Intel(R) PRO/1000 Network Driver
645 01:42:11.013639 <6>[ 1.706148] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
646 01:42:11.019354 <6>[ 1.712600] igb: Intel(R) Gigabit Ethernet Network Driver
647 01:42:11.027655 <6>[ 1.718421] igb: Copyright (c) 2007-2014 Intel Corporation.
648 01:42:11.039530 <6>[ 1.727752] pegasus: Pegasus/Pegasus II USB Ethernet driver
649 01:42:11.045324 <6>[ 1.733912] usbcore: registered new interface driver pegasus
650 01:42:11.051119 <6>[ 1.740039] usbcore: registered new interface driver asix
651 01:42:11.057018 <6>[ 1.745920] usbcore: registered new interface driver ax88179_178a
652 01:42:11.062645 <6>[ 1.752511] usbcore: registered new interface driver cdc_ether
653 01:42:11.068388 <6>[ 1.758806] usbcore: registered new interface driver smsc75xx
654 01:42:11.074242 <6>[ 1.765042] usbcore: registered new interface driver smsc95xx
655 01:42:11.080013 <6>[ 1.771278] usbcore: registered new interface driver net1080
656 01:42:11.085739 <6>[ 1.777396] usbcore: registered new interface driver cdc_subset
657 01:42:11.091512 <6>[ 1.783806] usbcore: registered new interface driver zaurus
658 01:42:11.099184 <6>[ 1.789847] usbcore: registered new interface driver cdc_ncm
659 01:42:11.109192 <6>[ 1.799457] usbcore: registered new interface driver usb-storage
660 01:42:11.393432 <6>[ 2.085576] i2c_dev: i2c /dev entries driver
661 01:42:11.451487 <5>[ 2.137363] cpuidle: enable-method property 'ti,am3352' found operations
662 01:42:11.457365 <6>[ 2.147037] sdhci: Secure Digital Host Controller Interface driver
663 01:42:11.464875 <6>[ 2.153809] sdhci: Copyright(c) Pierre Ossman
664 01:42:11.472239 <6>[ 2.160320] Synopsys Designware Multimedia Card Interface Driver
665 01:42:11.477639 <6>[ 2.168380] sdhci-pltfm: SDHCI platform and OF driver helper
666 01:42:11.605650 <6>[ 2.292271] usbcore: registered new interface driver usbhid
667 01:42:11.605929 <6>[ 2.298315] usbhid: USB HID core driver
668 01:42:11.656463 <6>[ 2.347792] NET: Registered PF_INET6 protocol family
669 01:42:11.697992 <6>[ 2.392020] Segment Routing with IPv6
670 01:42:11.703967 <6>[ 2.396167] In-situ OAM (IOAM) with IPv6
671 01:42:11.710583 <6>[ 2.400693] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 01:42:11.716456 <6>[ 2.407951] NET: Registered PF_PACKET protocol family
673 01:42:11.722206 <6>[ 2.413517] can: controller area network core
674 01:42:11.727957 <6>[ 2.418341] NET: Registered PF_CAN protocol family
675 01:42:11.728221 <6>[ 2.423570] can: raw protocol
676 01:42:11.733739 <6>[ 2.426897] can: broadcast manager protocol
677 01:42:11.740215 <6>[ 2.431498] can: netlink gateway - max_hops=1
678 01:42:11.746346 <5>[ 2.436963] Key type dns_resolver registered
679 01:42:11.752734 <6>[ 2.442015] ThumbEE CPU extension supported.
680 01:42:11.752989 <5>[ 2.446704] Registering SWP/SWPB emulation handler
681 01:42:11.762442 <3>[ 2.452446] omap_voltage_late_init: Voltage driver support not added
682 01:42:11.979707 <5>[ 2.671305] Loading compiled-in X.509 certificates
683 01:42:12.098571 <6>[ 2.779642] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 01:42:12.105754 <6>[ 2.796324] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 01:42:12.132049 <3>[ 2.819972] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 01:42:12.332365 <3>[ 3.020284] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 01:42:12.539811 <6>[ 3.232072] OMAP GPIO hardware version 0.1
688 01:42:12.560489 <6>[ 3.250765] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 01:42:12.642507 <4>[ 3.332477] at24 2-0054: supply vcc not found, using dummy regulator
690 01:42:12.676394 <4>[ 3.366335] at24 2-0055: supply vcc not found, using dummy regulator
691 01:42:12.714095 <4>[ 3.404134] at24 2-0056: supply vcc not found, using dummy regulator
692 01:42:12.753600 <4>[ 3.443637] at24 2-0057: supply vcc not found, using dummy regulator
693 01:42:12.794006 <6>[ 3.484825] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 01:42:12.869714 <3>[ 3.556586] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 01:42:12.894350 <6>[ 3.577426] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 01:42:12.915272 <4>[ 3.604057] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 01:42:12.932768 <4>[ 3.621508] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 01:42:13.011557 <6>[ 3.701742] omap_rng 48310000.rng: Random Number Generator ver. 20
699 01:42:13.035201 <5>[ 3.728122] random: crng init done
700 01:42:13.101997 <6>[ 3.795745] Freeing initrd memory: 14452K
701 01:42:13.111625 <6>[ 3.800385] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 01:42:13.165186 <6>[ 3.853004] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 01:42:13.171040 <6>[ 3.863348] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 01:42:13.182785 <6>[ 3.870688] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
705 01:42:13.188544 <6>[ 3.878133] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 01:42:13.200161 <6>[ 3.886260] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 01:42:13.207574 <6>[ 3.897900] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
708 01:42:13.220629 <5>[ 3.906930] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 01:42:13.248419 <3>[ 3.936649] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 01:42:13.254092 <6>[ 3.945241] edma 49000000.dma: TI EDMA DMA engine driver
711 01:42:13.325107 <3>[ 4.012708] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 01:42:13.339842 <6>[ 4.027067] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
713 01:42:13.352806 <3>[ 4.044153] l3-aon-clkctrl:0000:0: failed to disable
714 01:42:13.406072 <6>[ 4.094248] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 01:42:13.411675 <6>[ 4.103748] printk: legacy console [ttyS0] enabled
716 01:42:13.417421 <6>[ 4.103748] printk: legacy console [ttyS0] enabled
717 01:42:13.423035 <6>[ 4.114082] printk: legacy bootconsole [omap8250] disabled
718 01:42:13.428964 <6>[ 4.114082] printk: legacy bootconsole [omap8250] disabled
719 01:42:13.464033 <4>[ 4.151330] tps65217-pmic: Failed to locate of_node [id: -1]
720 01:42:13.467600 <4>[ 4.158717] tps65217-bl: Failed to locate of_node [id: -1]
721 01:42:13.484064 <6>[ 4.178295] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 01:42:13.502427 <6>[ 4.185234] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 01:42:13.514158 <6>[ 4.198918] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 01:42:13.519832 <6>[ 4.210796] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 01:42:13.541783 <6>[ 4.230291] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 01:42:13.547658 <6>[ 4.239489] sdhci-omap 48060000.mmc: Got CD GPIO
727 01:42:13.555583 <4>[ 4.244659] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 01:42:13.570215 <4>[ 4.258115] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 01:42:13.576548 <4>[ 4.266748] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 01:42:13.586396 <4>[ 4.275409] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 01:42:13.710014 <6>[ 4.399684] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 01:42:13.756210 <6>[ 4.443558] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 01:42:13.762707 <6>[ 4.452920] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 01:42:13.772054 <6>[ 4.461895] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 01:42:13.858276 <6>[ 4.542070] mmc1: new high speed MMC card at address 0001
736 01:42:13.858554 <6>[ 4.550385] mmcblk1: mmc1:0001 M62704 3.56 GiB
737 01:42:13.869242 <6>[ 4.561298] mmcblk1: p1
738 01:42:13.874630 <6>[ 4.566238] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
739 01:42:13.884972 <6>[ 4.576745] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
740 01:42:13.897422 <6>[ 4.584369] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 01:42:13.914880 <6>[ 4.605194] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
742 01:42:17.033257 <6>[ 7.721615] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 01:42:17.106622 <5>[ 7.760682] Sending DHCP requests ., OK
744 01:42:17.117945 <6>[ 7.805030] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.6
745 01:42:17.118216 <6>[ 7.813271] IP-Config: Complete:
746 01:42:17.129226 <6>[ 7.816812] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.6, mask=255.255.255.0, gw=192.168.11.1
747 01:42:17.134940 <6>[ 7.827404] host=192.168.11.6, domain=usen.ad.jp, nis-domain=(none)
748 01:42:17.147223 <6>[ 7.834483] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
749 01:42:17.147493 <6>[ 7.834518] nameserver0=192.168.11.1
750 01:42:17.153362 <6>[ 7.846809] clk: Disabling unused clocks
751 01:42:17.160013 <6>[ 7.851565] PM: genpd: Disabling unused power domains
752 01:42:17.179522 <6>[ 7.870258] Freeing unused kernel image (initmem) memory: 2048K
753 01:42:17.187010 <6>[ 7.879950] Run /init as init process
754 01:42:17.211882 Loading, please wait...
755 01:42:17.287563 Starting systemd-udevd version 252.22-1~deb12u1
756 01:42:20.477012 <4>[ 11.164045] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 01:42:20.623702 <4>[ 11.310822] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 01:42:20.805186 <6>[ 11.499829] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
759 01:42:20.816284 <6>[ 11.505648] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
760 01:42:20.970346 <6>[ 11.663163] tda998x 0-0070: found TDA19988
761 01:42:21.079275 <6>[ 11.772361] hub 1-0:1.0: USB hub found
762 01:42:21.128012 <6>[ 11.820866] hub 1-0:1.0: 1 port detected
763 01:42:23.773036 Begin: Loading essential drivers ... done.
764 01:42:23.778592 Begin: Running /scripts/init-premount ... done.
765 01:42:23.784086 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
766 01:42:23.797889 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
767 01:42:23.798159 Device /sys/class/net/eth0 found
768 01:42:23.798375 done.
769 01:42:23.871215 Begin: Waiting up to 180 secs for any network device to become available ... done.
770 01:42:23.971715 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
771 01:42:23.971996 IP-Config: eth0 guessed broadcast address 192.168.11.255
772 01:42:23.977233 IP-Config: eth0 complete (dhcp from 192.168.11.1):
773 01:42:23.988449 address: 192.168.11.6 broadcast: 192.168.11.255 netmask: 255.255.255.0
774 01:42:23.994074 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
775 01:42:23.999702 domain : usen.ad.jp
776 01:42:24.004641 rootserver: 192.168.11.1 rootpath:
777 01:42:24.004937 filename :
778 01:42:24.064016 done.
779 01:42:24.086649 Begin: Running /scripts/nfs-bottom ... done.
780 01:42:24.161554 Begin: Running /scripts/init-bottom ... done.
781 01:42:25.529348 <30>[ 16.219629] systemd[1]: System time before build time, advancing clock.
782 01:42:25.706792 <30>[ 16.370925] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
783 01:42:25.715393 <30>[ 16.407556] systemd[1]: Detected architecture arm.
784 01:42:25.729191
785 01:42:25.729467 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
786 01:42:25.729692
787 01:42:25.759777 <30>[ 16.450794] systemd[1]: Hostname set to <debian-bookworm-armhf>.
788 01:42:27.963483 <30>[ 18.653270] systemd[1]: Queued start job for default target graphical.target.
789 01:42:27.980068 <30>[ 18.667846] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
790 01:42:27.987620 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
791 01:42:28.019155 <30>[ 18.706447] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
792 01:42:28.026629 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
793 01:42:28.058740 <30>[ 18.746980] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
794 01:42:28.071867 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
795 01:42:28.093956 <30>[ 18.782450] systemd[1]: Created slice user.slice - User and Session Slice.
796 01:42:28.100620 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
797 01:42:28.129418 <30>[ 18.811962] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
798 01:42:28.135502 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
799 01:42:28.153431 <30>[ 18.841757] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
800 01:42:28.162444 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
801 01:42:28.194455 <30>[ 18.871753] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
802 01:42:28.200849 <30>[ 18.892261] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
803 01:42:28.209378 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
804 01:42:28.232577 <30>[ 18.921085] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
805 01:42:28.240765 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
806 01:42:28.263213 <30>[ 18.951468] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
807 01:42:28.271742 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
808 01:42:28.293176 <30>[ 18.981559] systemd[1]: Reached target paths.target - Path Units.
809 01:42:28.298179 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
810 01:42:28.322803 <30>[ 19.011249] systemd[1]: Reached target remote-fs.target - Remote File Systems.
811 01:42:28.330160 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
812 01:42:28.352550 <30>[ 19.041099] systemd[1]: Reached target slices.target - Slice Units.
813 01:42:28.357973 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
814 01:42:28.382926 <30>[ 19.071449] systemd[1]: Reached target swap.target - Swaps.
815 01:42:28.386958 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
816 01:42:28.413159 <30>[ 19.101438] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
817 01:42:28.421962 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
818 01:42:28.443907 <30>[ 19.132143] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
819 01:42:28.452206 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
820 01:42:28.532829 <30>[ 19.216349] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
821 01:42:28.545654 <30>[ 19.233877] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
822 01:42:28.554090 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
823 01:42:28.574404 <30>[ 19.262379] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
824 01:42:28.581824 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
825 01:42:28.611901 <30>[ 19.299375] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
826 01:42:28.620053 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
827 01:42:28.647648 <30>[ 19.334724] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
828 01:42:28.653157 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
829 01:42:28.686671 <30>[ 19.373817] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
830 01:42:28.694084 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
831 01:42:28.719774 <30>[ 19.402188] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
832 01:42:28.736449 <30>[ 19.418634] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
833 01:42:28.782645 <30>[ 19.471163] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
834 01:42:28.790080 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
835 01:42:28.832531 <30>[ 19.521112] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
836 01:42:28.840202 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
837 01:42:28.896190 <30>[ 19.584304] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
838 01:42:28.933473 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
839 01:42:28.993836 <30>[ 19.682537] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
840 01:42:29.011753 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
841 01:42:29.046435 <30>[ 19.735478] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
842 01:42:29.080971 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
843 01:42:29.133550 <30>[ 19.823117] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
844 01:42:29.153129 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
845 01:42:29.183691 <30>[ 19.872084] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
846 01:42:29.221687 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
847 01:42:29.262504 <30>[ 19.951791] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
848 01:42:29.273731 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
849 01:42:29.312911 <30>[ 20.002296] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
850 01:42:29.340827 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
851 01:42:29.371340 <28>[ 20.054632] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
852 01:42:29.379725 <28>[ 20.068275] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
853 01:42:29.422987 <30>[ 20.111649] systemd[1]: Starting systemd-journald.service - Journal Service...
854 01:42:29.429417 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
855 01:42:29.492949 <30>[ 20.182093] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
856 01:42:29.513194 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
857 01:42:29.536607 <30>[ 20.225974] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
858 01:42:29.561683 Starting [0;1;39msystemd-network-g… units from Kernel command line...
859 01:42:29.605549 <30>[ 20.293462] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
860 01:42:29.655175 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
861 01:42:29.716835 <30>[ 20.405495] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
862 01:42:29.772168 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
863 01:42:29.833158 <30>[ 20.522745] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
864 01:42:29.883673 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
865 01:42:29.903010 <30>[ 20.592391] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
866 01:42:29.953447 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
867 01:42:29.993650 <30>[ 20.681992] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
868 01:42:30.027776 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
869 01:42:30.173664 <30>[ 20.863715] systemd[1]: modprobe@configfs.service: Deactivated successfully.
870 01:42:30.203501 <30>[ 20.892513] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
871 01:42:30.232514 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
872 01:42:30.263128 <30>[ 20.953410] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
873 01:42:30.293127 <30>[ 20.982434] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
874 01:42:30.322508 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
875 01:42:30.342885 <30>[ 21.033437] systemd[1]: modprobe@drm.service: Deactivated successfully.
876 01:42:30.370135 <30>[ 21.059955] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
877 01:42:30.392491 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 01:42:30.413700 <30>[ 21.102347] systemd[1]: Started systemd-journald.service - Journal Service.
879 01:42:30.420529 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
880 01:42:30.454624 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 01:42:30.477244 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 01:42:30.514621 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 01:42:30.542738 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 01:42:30.565871 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 01:42:30.596002 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 01:42:30.632369 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 01:42:30.692117 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 01:42:30.731479 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 01:42:30.800190 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 01:42:30.851449 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 01:42:30.961700 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 01:42:31.102682 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 01:42:31.136700 <46>[ 21.826112] systemd-journald[162]: Received client request to flush runtime journal.
894 01:42:31.262950 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 01:42:31.371700 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 01:42:32.114198 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 01:42:32.186040 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 01:42:32.922779 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 01:42:33.104531 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 01:42:33.124500 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 01:42:33.143367 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 01:42:33.223614 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 01:42:33.264386 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 01:42:34.192858 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 01:42:34.261186 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 01:42:34.516733 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 01:42:34.638832 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 01:42:34.708058 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 01:42:36.632460 [[0m[0;31m* [0m] (1 of 5) Job systemd-timesyncd.service/start running (8s / 1min 36s)
910 01:42:36.664159 M[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
911 01:42:36.823726 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 01:42:37.554854 <5>[ 28.244699] cfg80211: Loading compiled-in X.509 certificates for regulatory database
913 01:42:37.752818 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
914 01:42:39.141196 <5>[ 29.833183] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
915 01:42:39.213323 <5>[ 29.901703] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
916 01:42:39.219073 <4>[ 29.910743] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
917 01:42:39.226782 <6>[ 29.919711] cfg80211: failed to load regulatory.db
918 01:42:39.517296 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
919 01:42:39.705659 <46>[ 30.385460] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
920 01:42:39.830289 <46>[ 30.513146] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
921 01:42:39.973651 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
922 01:42:48.519234 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
923 01:42:48.542973 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
924 01:42:48.564137 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
925 01:42:48.584386 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
926 01:42:48.642375 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
927 01:42:48.692971 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
928 01:42:48.732432 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
929 01:42:48.774585 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
930 01:42:48.853691 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
931 01:42:48.882828 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
932 01:42:48.922870 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
933 01:42:48.946228 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
934 01:42:48.968084 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
935 01:42:49.014565 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
936 01:42:49.060477 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
937 01:42:49.103299 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
938 01:42:49.144869 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
939 01:42:49.173943 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
940 01:42:49.192578 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
941 01:42:49.217789 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
942 01:42:49.253669 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
943 01:42:49.271218 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
944 01:42:49.294924 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
945 01:42:49.372687 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
946 01:42:49.412820 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
947 01:42:49.527056 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
948 01:42:49.635691 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
949 01:42:49.724725 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
950 01:42:49.789934 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
951 01:42:49.815396 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
952 01:42:49.976465 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
953 01:42:50.003523 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
954 01:42:50.142878 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
955 01:42:50.175740 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
956 01:42:50.202481 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
957 01:42:50.358018 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
958 01:42:50.607058 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
959 01:42:50.676838 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
960 01:42:50.712097 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
961 01:42:50.797715 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
962 01:42:50.962866 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
963 01:42:51.091867
964 01:42:51.092165 Debian GNU/Linux 12worm-armhf login: root (automatic login)
965 01:42:51.095255
966 01:42:51.388735 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Fri Nov 1 00:32:11 UTC 2024 armv7l
967 01:42:51.389080
968 01:42:51.394338 The programs included with the Debian GNU/Linux system are free software;
969 01:42:51.397635 the exact distribution terms for each program are described in the
970 01:42:51.403280 individual files in /usr/share/doc/*/copyright.
971 01:42:51.403571
972 01:42:51.408957 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
973 01:42:51.413491 permitted by applicable law.
974 01:42:55.997603 Unable to match end of the kernel message
976 01:42:55.998696 Setting prompt string to ['/ #']
977 01:42:55.999127 end: 2.4.4.1 login-action (duration 00:00:47) [common]
979 01:42:56.000202 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
980 01:42:56.000639 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
981 01:42:56.001043 Setting prompt string to ['/ #']
982 01:42:56.001382 Forcing a shell prompt, looking for ['/ #']
984 01:42:56.051950 / #
985 01:42:56.052320 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
986 01:42:56.052594 Waiting using forced prompt support (timeout 00:02:30)
987 01:42:56.056796
988 01:42:56.063588 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
989 01:42:56.063922 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
990 01:42:56.064179 Sending with 10 millisecond of delay
992 01:43:01.112658 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1'
993 01:43:01.123268 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214595/extract-nfsrootfs-laf4apt1'
994 01:43:01.124490 Sending with 10 millisecond of delay
996 01:43:03.282791 / # export NFS_SERVER_IP='192.168.11.5'
997 01:43:03.293385 export NFS_SERVER_IP='192.168.11.5'
998 01:43:03.294642 end: 2.4.6 export-device-env (duration 00:00:07) [common]
999 01:43:03.294983 end: 2.4 uboot-commands (duration 00:01:43) [common]
1000 01:43:03.295298 end: 2 uboot-action (duration 00:01:43) [common]
1001 01:43:03.295602 start: 3 lava-test-retry (timeout 00:07:23) [common]
1002 01:43:03.295909 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
1003 01:43:03.296154 Using namespace: common
1005 01:43:03.396853 / # #
1006 01:43:03.397232 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1007 01:43:03.401716 #
1008 01:43:03.408032 Using /lava-1214595
1010 01:43:03.508772 / # export SHELL=/bin/bash
1011 01:43:03.513574 export SHELL=/bin/bash
1013 01:43:03.620204 / # . /lava-1214595/environment
1014 01:43:03.625000 . /lava-1214595/environment
1016 01:43:03.738198 / # /lava-1214595/bin/lava-test-runner /lava-1214595/0
1017 01:43:03.738576 Test shell timeout: 10s (minimum of the action and connection timeout)
1018 01:43:03.742950 /lava-1214595/bin/lava-test-runner /lava-1214595/0
1019 01:43:04.139552 + export TESTRUN_ID=0_timesync-off
1020 01:43:04.147552 + TESTRUN_ID=0_timesync-off
1021 01:43:04.147797 + cd /lava-1214595/0/tests/0_timesync-off
1022 01:43:04.148025 ++ cat uuid
1023 01:43:04.163542 + UUID=1214595_1.6.2.4.1
1024 01:43:04.163883 + set +x
1025 01:43:04.169157 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1214595_1.6.2.4.1>
1026 01:43:04.169664 Received signal: <STARTRUN> 0_timesync-off 1214595_1.6.2.4.1
1027 01:43:04.169911 Starting test lava.0_timesync-off (1214595_1.6.2.4.1)
1028 01:43:04.170187 Skipping test definition patterns.
1029 01:43:04.172347 + systemctl stop systemd-timesyncd
1030 01:43:04.451744 + set +x
1031 01:43:04.452232 Received signal: <ENDRUN> 0_timesync-off 1214595_1.6.2.4.1
1032 01:43:04.452501 Ending use of test pattern.
1033 01:43:04.452738 Ending test lava.0_timesync-off (1214595_1.6.2.4.1), duration 0.28
1035 01:43:04.454824 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1214595_1.6.2.4.1>
1036 01:43:04.650758 + export TESTRUN_ID=1_kselftest-dt
1037 01:43:04.658755 + TESTRUN_ID=1_kselftest-dt
1038 01:43:04.658995 + cd /lava-1214595/0/tests/1_kselftest-dt
1039 01:43:04.659217 ++ cat uuid
1040 01:43:04.687584 + UUID=1214595_1.6.2.4.5
1041 01:43:04.687840 + set +x
1042 01:43:04.693203 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1214595_1.6.2.4.5>
1043 01:43:04.693454 + cd ./automated/linux/kselftest/
1044 01:43:04.693898 Received signal: <STARTRUN> 1_kselftest-dt 1214595_1.6.2.4.5
1045 01:43:04.694141 Starting test lava.1_kselftest-dt (1214595_1.6.2.4.5)
1046 01:43:04.694426 Skipping test definition patterns.
1047 01:43:04.721522 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1048 01:43:04.829943 INFO: install_deps skipped
1049 01:43:05.483188 --2024-11-01 01:43:05-- http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1050 01:43:05.502734 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1051 01:43:05.617440 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1052 01:43:05.729763 HTTP request sent, awaiting response... 200 OK
1053 01:43:05.730070 Length: 4113364 (3.9M) [application/octet-stream]
1054 01:43:05.735384 Saving to: 'kselftest_armhf.tar.gz'
1055 01:43:05.735692
1056 01:43:07.240281 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 221KB/s kselftest_armhf.tar 4%[ ] 194.76K 435KB/s kselftest_armhf.tar 15%[==> ] 616.64K 847KB/s kselftest_armhf.tar 39%[======> ] 1.55M 1.67MB/s kselftest_armhf.tar 61%[===========> ] 2.40M 2.11MB/s kselftest_armhf.tar 81%[===============> ] 3.18M 2.37MB/s kselftest_armhf.tar 100%[===================>] 3.92M 2.61MB/s in 1.5s
1057 01:43:07.240648
1058 01:43:07.858800 2024-11-01 01:43:07 (2.61 MB/s) - 'kselftest_armhf.tar.gz' saved [4113364/4113364]
1059 01:43:07.859159
1060 01:43:29.995903 skiplist:
1061 01:43:29.996307 ========================================
1062 01:43:30.001739 ========================================
1063 01:43:30.106499 dt:test_unprobed_devices.sh
1064 01:43:30.137881 ============== Tests to run ===============
1065 01:43:30.147550 dt:test_unprobed_devices.sh
1066 01:43:30.151440 ===========End Tests to run ===============
1067 01:43:30.160880 shardfile-dt pass
1068 01:43:30.391933 <12>[ 81.087458] kselftest: Running tests in dt
1069 01:43:30.420372 TAP version 13
1070 01:43:30.443951 1..1
1071 01:43:30.498882 # timeout set to 45
1072 01:43:30.499167 # selftests: dt: test_unprobed_devices.sh
1073 01:43:31.318132 # TAP version 13
1074 01:43:56.371683 # 1..257
1075 01:43:56.540139 # ok 1 / # SKIP
1076 01:43:56.567212 # ok 2 /clk_mcasp0
1077 01:43:56.639573 # ok 3 /clk_mcasp0_fixed # SKIP
1078 01:43:56.704627 # ok 4 /cpus/cpu@0 # SKIP
1079 01:43:56.777715 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1080 01:43:56.801844 # ok 6 /fixedregulator0
1081 01:43:56.817989 # ok 7 /leds
1082 01:43:56.839407 # ok 8 /ocp
1083 01:43:56.869792 # ok 9 /ocp/interconnect@44c00000
1084 01:43:56.893760 # ok 10 /ocp/interconnect@44c00000/segment@0
1085 01:43:56.914073 # ok 11 /ocp/interconnect@44c00000/segment@100000
1086 01:43:56.941286 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1087 01:43:57.013834 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1088 01:43:57.034419 # ok 14 /ocp/interconnect@44c00000/segment@200000
1089 01:43:57.053549 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1090 01:43:57.160155 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1091 01:43:57.232882 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1092 01:43:57.305379 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1093 01:43:57.381123 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1094 01:43:57.450590 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1095 01:43:57.523962 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1096 01:43:57.596945 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1097 01:43:57.669447 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1098 01:43:57.742598 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1099 01:43:57.814687 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1100 01:43:57.887172 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1101 01:43:57.964814 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1102 01:43:58.037182 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1103 01:43:58.108326 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1104 01:43:58.177618 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1105 01:43:58.250334 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1106 01:43:58.323293 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1107 01:43:58.396053 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1108 01:43:58.474910 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1109 01:43:58.542805 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1110 01:43:58.614405 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1111 01:43:58.688942 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1112 01:43:58.760787 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1113 01:43:58.833992 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1114 01:43:58.906664 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1115 01:43:58.980907 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1116 01:43:59.054306 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1117 01:43:59.127025 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1118 01:43:59.199412 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1119 01:43:59.275543 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1120 01:43:59.349324 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1121 01:43:59.418533 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1122 01:43:59.494922 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1123 01:43:59.569273 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1124 01:43:59.636882 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1125 01:43:59.708663 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1126 01:43:59.780650 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1127 01:43:59.853397 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1128 01:43:59.926257 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1129 01:43:59.997753 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1130 01:44:00.077393 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1131 01:44:00.148406 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1132 01:44:00.215266 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1133 01:44:00.287890 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1134 01:44:00.359844 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1135 01:44:00.436761 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1136 01:44:00.508549 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1137 01:44:00.577759 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1138 01:44:00.655293 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1139 01:44:00.726875 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1140 01:44:00.798914 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1141 01:44:00.875543 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1142 01:44:00.943253 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1143 01:44:01.017808 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1144 01:44:01.091630 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1145 01:44:01.165068 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1146 01:44:01.237960 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1147 01:44:01.311279 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1148 01:44:01.383576 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1149 01:44:01.457689 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1150 01:44:01.530309 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1151 01:44:01.603949 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1152 01:44:01.676869 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1153 01:44:01.753932 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1154 01:44:01.823274 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1155 01:44:01.895208 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1156 01:44:01.969909 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1157 01:44:02.041326 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1158 01:44:02.114402 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1159 01:44:02.187275 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1160 01:44:02.260459 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1161 01:44:02.332765 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1162 01:44:02.404882 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1163 01:44:02.479421 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1164 01:44:02.556538 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1165 01:44:02.626522 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1166 01:44:02.699752 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1167 01:44:02.769379 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1168 01:44:02.846263 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1169 01:44:02.866679 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1170 01:44:02.891157 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1171 01:44:02.915389 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1172 01:44:02.936493 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1173 01:44:02.959112 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1174 01:44:02.982515 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1175 01:44:03.008308 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1176 01:44:03.028494 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1177 01:44:03.136122 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1178 01:44:03.161022 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1179 01:44:03.184999 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1180 01:44:03.213000 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1181 01:44:03.317485 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1182 01:44:03.396308 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1183 01:44:03.468480 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1184 01:44:03.539791 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1185 01:44:03.609602 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1186 01:44:03.681592 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1187 01:44:03.754108 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1188 01:44:03.825871 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1189 01:44:03.898336 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1190 01:44:03.976095 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1191 01:44:04.044085 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1192 01:44:04.116453 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1193 01:44:04.187699 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1194 01:44:04.262617 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1195 01:44:04.335323 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1196 01:44:04.407702 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1197 01:44:04.435328 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1198 01:44:04.501343 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1199 01:44:04.571192 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1200 01:44:04.644580 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1201 01:44:04.671129 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1202 01:44:04.743962 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1203 01:44:04.766509 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1204 01:44:04.836601 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1205 01:44:04.861653 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1206 01:44:04.885705 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1207 01:44:04.907481 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1208 01:44:04.928698 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1209 01:44:04.951217 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1210 01:44:04.976088 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1211 01:44:05.001199 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1212 01:44:05.075957 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1213 01:44:05.101237 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1214 01:44:05.121457 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1215 01:44:05.197818 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1216 01:44:05.266566 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1217 01:44:05.291565 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1218 01:44:05.393077 # not ok 144 /ocp/interconnect@47c00000
1219 01:44:05.460226 # not ok 145 /ocp/interconnect@47c00000/segment@0
1220 01:44:05.481336 # ok 146 /ocp/interconnect@48000000
1221 01:44:05.509217 # ok 147 /ocp/interconnect@48000000/segment@0
1222 01:44:05.534093 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1223 01:44:05.555234 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1224 01:44:05.576524 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1225 01:44:05.604131 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1226 01:44:05.625381 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1227 01:44:05.652111 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1228 01:44:05.674638 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1229 01:44:05.745650 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1230 01:44:05.822729 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1231 01:44:05.839584 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1232 01:44:05.863835 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1233 01:44:05.891110 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1234 01:44:05.915476 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1235 01:44:05.935206 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1236 01:44:05.963079 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1237 01:44:05.985250 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1238 01:44:06.007480 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1239 01:44:06.027841 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1240 01:44:06.052799 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1241 01:44:06.080102 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1242 01:44:06.104739 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1243 01:44:06.125183 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1244 01:44:06.147703 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1245 01:44:06.170692 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1246 01:44:06.196012 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1247 01:44:06.218029 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1248 01:44:06.242668 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1249 01:44:06.263919 # ok 175 /ocp/interconnect@48000000/segment@100000
1250 01:44:06.288690 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1251 01:44:06.316062 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1252 01:44:06.386861 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1253 01:44:06.465771 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1254 01:44:06.533147 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1255 01:44:06.607357 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1256 01:44:06.677977 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1257 01:44:06.751837 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1258 01:44:06.822504 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1259 01:44:06.896100 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1260 01:44:06.917625 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1261 01:44:06.939681 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1262 01:44:06.962869 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1263 01:44:06.986375 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1264 01:44:07.014126 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1265 01:44:07.036105 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1266 01:44:07.061577 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1267 01:44:07.085737 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1268 01:44:07.105595 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1269 01:44:07.132244 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1270 01:44:07.155158 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1271 01:44:07.176085 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1272 01:44:07.199900 # ok 198 /ocp/interconnect@48000000/segment@200000
1273 01:44:07.223978 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1274 01:44:07.296371 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1275 01:44:07.318152 # ok 201 /ocp/interconnect@48000000/segment@300000
1276 01:44:07.343016 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1277 01:44:07.365571 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1278 01:44:07.387062 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1279 01:44:07.410006 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1280 01:44:07.433281 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1281 01:44:07.458161 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1282 01:44:07.534324 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1283 01:44:07.552635 # ok 209 /ocp/interconnect@4a000000
1284 01:44:07.580116 # ok 210 /ocp/interconnect@4a000000/segment@0
1285 01:44:07.598991 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1286 01:44:07.623409 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1287 01:44:07.652906 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1288 01:44:07.674794 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1289 01:44:07.746332 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1290 01:44:07.849558 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1291 01:44:07.927774 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1292 01:44:08.028553 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1293 01:44:08.100165 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1294 01:44:08.172557 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1295 01:44:08.271605 # not ok 221 /ocp/interconnect@4b140000
1296 01:44:08.348454 # not ok 222 /ocp/interconnect@4b140000/segment@0
1297 01:44:08.420677 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1298 01:44:08.437671 # ok 224 /ocp/target-module@40300000
1299 01:44:08.463188 # ok 225 /ocp/target-module@40300000/sram@0
1300 01:44:08.536008 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1301 01:44:08.608423 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1302 01:44:08.628165 # ok 228 /ocp/target-module@47400000
1303 01:44:08.652607 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1304 01:44:08.674207 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1305 01:44:08.701465 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1306 01:44:08.723340 # ok 232 /ocp/target-module@47400000/usb@1400
1307 01:44:08.743323 # ok 233 /ocp/target-module@47400000/usb@1800
1308 01:44:08.764325 # ok 234 /ocp/target-module@47810000
1309 01:44:08.786485 # ok 235 /ocp/target-module@49000000
1310 01:44:08.813089 # ok 236 /ocp/target-module@49000000/dma@0
1311 01:44:08.831389 # ok 237 /ocp/target-module@49800000
1312 01:44:08.854975 # ok 238 /ocp/target-module@49800000/dma@0
1313 01:44:08.876341 # ok 239 /ocp/target-module@49900000
1314 01:44:08.899451 # ok 240 /ocp/target-module@49900000/dma@0
1315 01:44:08.921413 # ok 241 /ocp/target-module@49a00000
1316 01:44:08.944938 # ok 242 /ocp/target-module@49a00000/dma@0
1317 01:44:08.970375 # ok 243 /ocp/target-module@4c000000
1318 01:44:09.043455 # not ok 244 /ocp/target-module@4c000000/emif@0
1319 01:44:09.060297 # ok 245 /ocp/target-module@50000000
1320 01:44:09.083013 # ok 246 /ocp/target-module@53100000
1321 01:44:09.159929 # not ok 247 /ocp/target-module@53100000/sham@0
1322 01:44:09.180920 # ok 248 /ocp/target-module@53500000
1323 01:44:09.253466 # not ok 249 /ocp/target-module@53500000/aes@0
1324 01:44:09.270845 # ok 250 /ocp/target-module@56000000
1325 01:44:09.381288 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1326 01:44:09.450248 # ok 252 /opp-table # SKIP
1327 01:44:09.515587 # ok 253 /soc # SKIP
1328 01:44:09.540793 # ok 254 /sound
1329 01:44:09.565524 # ok 255 /target-module@4b000000
1330 01:44:09.586955 # ok 256 /target-module@4b000000/target-module@140000
1331 01:44:09.607491 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1332 01:44:09.616110 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1333 01:44:09.623939 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1334 01:44:11.826195 dt_test_unprobed_devices_sh_ skip
1335 01:44:11.831820 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1336 01:44:11.837429 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1337 01:44:11.837733 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1338 01:44:11.842883 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1339 01:44:11.848540 dt_test_unprobed_devices_sh_fixedregulator0 pass
1340 01:44:11.854112 dt_test_unprobed_devices_sh_leds pass
1341 01:44:11.854362 dt_test_unprobed_devices_sh_ocp pass
1342 01:44:11.859735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1343 01:44:11.865373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1344 01:44:11.871002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1345 01:44:11.882130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1346 01:44:11.887731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1347 01:44:11.893369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1348 01:44:11.904684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1349 01:44:11.910289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1350 01:44:11.921519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1351 01:44:11.932783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1352 01:44:11.943995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1353 01:44:11.949512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1354 01:44:11.960779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1355 01:44:11.972019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1356 01:44:11.983268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1357 01:44:11.994366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1358 01:44:11.999993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1359 01:44:12.011140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1360 01:44:12.022369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1361 01:44:12.033494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1362 01:44:12.044752 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1363 01:44:12.050368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1364 01:44:12.061487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1365 01:44:12.072771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1366 01:44:12.083902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1367 01:44:12.089544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1368 01:44:12.100767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1369 01:44:12.111932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1370 01:44:12.123170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1371 01:44:12.134259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1372 01:44:12.139909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1373 01:44:12.151171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1374 01:44:12.162262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1375 01:44:12.173546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1376 01:44:12.184811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1377 01:44:12.195915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1378 01:44:12.207040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1379 01:44:12.218250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1380 01:44:12.229415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1381 01:44:12.240629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1382 01:44:12.251788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1383 01:44:12.262992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1384 01:44:12.274115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1385 01:44:12.285417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1386 01:44:12.296483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1387 01:44:12.307738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1388 01:44:12.318916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1389 01:44:12.330114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1390 01:44:12.341248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1391 01:44:12.352494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1392 01:44:12.363744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1393 01:44:12.374870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1394 01:44:12.386117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1395 01:44:12.397368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1396 01:44:12.408631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1397 01:44:12.419742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1398 01:44:12.425367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1399 01:44:12.436656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1400 01:44:12.447841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1401 01:44:12.458932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1402 01:44:12.470200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1403 01:44:12.481366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1404 01:44:12.492614 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1405 01:44:12.503741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1406 01:44:12.515042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1407 01:44:12.526266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1408 01:44:12.537424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1409 01:44:12.548807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1410 01:44:12.559919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1411 01:44:12.571189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1412 01:44:12.582299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1413 01:44:12.593544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1414 01:44:12.604778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1415 01:44:12.615881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1416 01:44:12.621506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1417 01:44:12.632699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1418 01:44:12.643903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1419 01:44:12.655030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1420 01:44:12.666278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1421 01:44:12.671903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1422 01:44:12.688670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1423 01:44:12.699773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1424 01:44:12.705414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1425 01:44:12.722150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1426 01:44:12.733402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1427 01:44:12.744572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1428 01:44:12.750152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1429 01:44:12.761400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1430 01:44:12.772668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1431 01:44:12.778147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1432 01:44:12.789405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1433 01:44:12.800564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1434 01:44:12.806147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1435 01:44:12.817401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1436 01:44:12.823022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1437 01:44:12.834145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1438 01:44:12.845395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1439 01:44:12.856522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1440 01:44:12.867770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1441 01:44:12.878894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1442 01:44:12.890122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1443 01:44:12.901270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1444 01:44:12.912519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1445 01:44:12.923777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1446 01:44:12.934894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1447 01:44:12.946018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1448 01:44:12.957267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1449 01:44:12.974020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1450 01:44:12.985267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1451 01:44:12.996409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1452 01:44:13.007641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1453 01:44:13.018767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1454 01:44:13.035643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1455 01:44:13.046765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1456 01:44:13.058013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1457 01:44:13.069137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1458 01:44:13.074762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1459 01:44:13.085890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1460 01:44:13.097223 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1461 01:44:13.102765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1462 01:44:13.113888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1463 01:44:13.119512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1464 01:44:13.130761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1465 01:44:13.136265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1466 01:44:13.147510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1467 01:44:13.153024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1468 01:44:13.164280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1469 01:44:13.169886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1470 01:44:13.181011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1471 01:44:13.192278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1472 01:44:13.203383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1473 01:44:13.214634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1474 01:44:13.225882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1475 01:44:13.231384 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1476 01:44:13.242631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1477 01:44:13.248258 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1478 01:44:13.253760 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1479 01:44:13.259381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1480 01:44:13.265021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1481 01:44:13.270629 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1482 01:44:13.281784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1483 01:44:13.287382 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1484 01:44:13.293021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1485 01:44:13.304135 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1486 01:44:13.309756 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1487 01:44:13.320982 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1488 01:44:13.326500 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1489 01:44:13.337713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1490 01:44:13.343337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1491 01:44:13.354461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1492 01:44:13.360086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1493 01:44:13.371333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1494 01:44:13.376982 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1495 01:44:13.388082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1496 01:44:13.393712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1497 01:44:13.404844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1498 01:44:13.410460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1499 01:44:13.416084 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1500 01:44:13.427207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1501 01:44:13.432844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1502 01:44:13.444083 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1503 01:44:13.449713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1504 01:44:13.460852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1505 01:44:13.466456 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1506 01:44:13.477707 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1507 01:44:13.483207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1508 01:44:13.488851 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1509 01:44:13.499956 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1510 01:44:13.505711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1511 01:44:13.516852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1512 01:44:13.527955 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1513 01:44:13.539201 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1514 01:44:13.550328 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1515 01:44:13.561575 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1516 01:44:13.572702 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1517 01:44:13.583949 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1518 01:44:13.595076 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1519 01:44:13.600720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1520 01:44:13.611953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1521 01:44:13.617492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1522 01:44:13.628696 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1523 01:44:13.634332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1524 01:44:13.645478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1525 01:44:13.651092 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1526 01:44:13.662326 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1527 01:44:13.667795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1528 01:44:13.679010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1529 01:44:13.684631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1530 01:44:13.695746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1531 01:44:13.701381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1532 01:44:13.712679 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1533 01:44:13.718180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1534 01:44:13.723806 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1535 01:44:13.735066 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1536 01:44:13.740681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1537 01:44:13.751806 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1538 01:44:13.757432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1539 01:44:13.768680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1540 01:44:13.774183 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1541 01:44:13.785302 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1542 01:44:13.790931 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1543 01:44:13.796553 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1544 01:44:13.802176 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1545 01:44:13.813304 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1546 01:44:13.824557 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1547 01:44:13.830053 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1548 01:44:13.835676 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1549 01:44:13.846938 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1550 01:44:13.858052 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1551 01:44:13.869314 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1552 01:44:13.880528 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1553 01:44:13.886181 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1554 01:44:13.891675 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1555 01:44:13.897311 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1556 01:44:13.902928 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1557 01:44:13.908549 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1558 01:44:13.914175 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1559 01:44:13.925306 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1560 01:44:13.930919 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1561 01:44:13.936651 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1562 01:44:13.942156 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1563 01:44:13.947781 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1564 01:44:13.958893 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1565 01:44:13.964522 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1566 01:44:13.970157 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1567 01:44:13.975770 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1568 01:44:13.981273 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1569 01:44:13.986898 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1570 01:44:13.992650 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1571 01:44:13.998143 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1572 01:44:14.003773 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1573 01:44:14.009396 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1574 01:44:14.014897 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1575 01:44:14.020650 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1576 01:44:14.026176 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1577 01:44:14.031797 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1578 01:44:14.037427 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1579 01:44:14.043022 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1580 01:44:14.048650 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1581 01:44:14.054144 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1582 01:44:14.059770 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1583 01:44:14.065395 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1584 01:44:14.070895 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1585 01:44:14.071141 dt_test_unprobed_devices_sh_opp-table skip
1586 01:44:14.076643 dt_test_unprobed_devices_sh_soc skip
1587 01:44:14.082146 dt_test_unprobed_devices_sh_sound pass
1588 01:44:14.087768 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1589 01:44:14.093394 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1590 01:44:14.099015 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1591 01:44:14.104628 dt_test_unprobed_devices_sh fail
1592 01:44:14.104890 + ../../utils/send-to-lava.sh ./output/result.txt
1593 01:44:14.110145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1594 01:44:14.110698 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1596 01:44:14.119329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1597 01:44:14.119752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1599 01:44:14.215495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1600 01:44:14.215976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1602 01:44:14.313815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1603 01:44:14.314338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1605 01:44:14.410813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1606 01:44:14.411337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1608 01:44:14.510432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1609 01:44:14.510916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1611 01:44:14.608599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1612 01:44:14.609103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1614 01:44:14.704442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1615 01:44:14.704895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1617 01:44:14.803552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1618 01:44:14.804025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1620 01:44:14.903193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1621 01:44:14.903667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1623 01:44:15.000452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1624 01:44:15.000942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1626 01:44:15.099698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1627 01:44:15.100177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1629 01:44:15.199955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1630 01:44:15.200427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1632 01:44:15.298565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1633 01:44:15.299082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1635 01:44:15.395962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1636 01:44:15.396483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1638 01:44:15.496820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1639 01:44:15.497292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1641 01:44:15.596894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1642 01:44:15.597371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1644 01:44:15.693815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1645 01:44:15.694296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1647 01:44:15.793925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1648 01:44:15.794423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1650 01:44:15.893848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1651 01:44:15.894345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1653 01:44:15.991765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1654 01:44:15.992258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1656 01:44:16.087815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1657 01:44:16.088301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1659 01:44:16.184914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1660 01:44:16.185398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1662 01:44:16.284832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1663 01:44:16.285370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1665 01:44:16.383444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1666 01:44:16.383978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1668 01:44:16.480416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1669 01:44:16.480900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1671 01:44:16.578414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1672 01:44:16.578900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1674 01:44:16.675402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1675 01:44:16.675892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1677 01:44:16.769555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1678 01:44:16.770042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1680 01:44:16.867747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1681 01:44:16.868221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1683 01:44:16.960256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1684 01:44:16.960755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1686 01:44:17.061446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1687 01:44:17.061933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1689 01:44:17.157461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1690 01:44:17.157933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1692 01:44:17.251561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1693 01:44:17.252037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1695 01:44:17.352592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1696 01:44:17.353158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1698 01:44:17.448087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1699 01:44:17.448580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1701 01:44:17.543297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1702 01:44:17.543791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1704 01:44:17.640968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1705 01:44:17.641468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1707 01:44:17.739395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1708 01:44:17.739883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1710 01:44:17.835324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1711 01:44:17.835819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1713 01:44:17.935241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1714 01:44:17.935729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1716 01:44:18.036012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1717 01:44:18.036539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1719 01:44:18.136270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1720 01:44:18.136770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1722 01:44:18.235474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1723 01:44:18.235970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1725 01:44:18.333864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1726 01:44:18.334441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1728 01:44:18.434601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1729 01:44:18.435143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1731 01:44:18.534263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1732 01:44:18.534763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1734 01:44:18.632699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1735 01:44:18.633257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1737 01:44:18.732635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1738 01:44:18.733168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1740 01:44:18.830563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1741 01:44:18.831065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1743 01:44:18.931510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1744 01:44:18.932025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1746 01:44:19.030199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1747 01:44:19.030700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1749 01:44:19.125055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1750 01:44:19.125543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1752 01:44:19.223764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1753 01:44:19.224256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1755 01:44:19.322654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1756 01:44:19.323235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1758 01:44:19.419612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1759 01:44:19.420181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1761 01:44:19.516763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1762 01:44:19.517253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1764 01:44:19.615979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1765 01:44:19.616503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1767 01:44:19.714135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1768 01:44:19.714651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1770 01:44:19.813949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1771 01:44:19.814442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1773 01:44:19.912543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1774 01:44:19.913056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1776 01:44:20.011196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1777 01:44:20.011683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1779 01:44:20.114781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1780 01:44:20.115267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1782 01:44:20.212529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1783 01:44:20.213043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1785 01:44:20.309533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1786 01:44:20.310086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1788 01:44:20.408070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1789 01:44:20.408624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1791 01:44:20.506450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1792 01:44:20.506936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1794 01:44:20.605583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1795 01:44:20.606083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1797 01:44:20.700376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1798 01:44:20.700863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1800 01:44:20.797943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1801 01:44:20.798430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1803 01:44:20.896600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1804 01:44:20.897113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1806 01:44:20.995169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1807 01:44:20.995656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1809 01:44:21.095253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1810 01:44:21.095748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1812 01:44:21.196132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1813 01:44:21.196625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1815 01:44:21.295189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1816 01:44:21.295775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1818 01:44:21.394899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1819 01:44:21.395434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1821 01:44:21.492705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1822 01:44:21.493226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1824 01:44:21.592679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1825 01:44:21.593197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1827 01:44:21.691715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1828 01:44:21.692210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1830 01:44:21.789107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1831 01:44:21.789600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1833 01:44:21.884135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1834 01:44:21.884668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1836 01:44:21.984899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1837 01:44:21.985395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1839 01:44:22.084235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1840 01:44:22.084738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1842 01:44:22.180520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1843 01:44:22.181020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1845 01:44:22.281457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1846 01:44:22.281936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1848 01:44:22.380499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1849 01:44:22.381116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1851 01:44:22.478208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1852 01:44:22.478691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1854 01:44:22.575128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1855 01:44:22.575624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1857 01:44:22.672966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1858 01:44:22.673467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1860 01:44:22.770119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1861 01:44:22.770605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1863 01:44:22.863119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1864 01:44:22.863602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1866 01:44:22.954874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1867 01:44:22.955370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1869 01:44:23.050727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1870 01:44:23.051224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1872 01:44:23.146551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1873 01:44:23.147048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1875 01:44:23.241354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1876 01:44:23.241840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1878 01:44:23.337437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1879 01:44:23.337999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1881 01:44:23.429904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1882 01:44:23.430392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1884 01:44:23.528425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1885 01:44:23.528938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1887 01:44:23.624859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1888 01:44:23.625354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1890 01:44:23.724542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1891 01:44:23.725056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1893 01:44:23.821111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1894 01:44:23.821594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1896 01:44:23.914747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1897 01:44:23.915215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1899 01:44:24.011912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1900 01:44:24.012422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1902 01:44:24.111219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1903 01:44:24.111711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1905 01:44:24.211466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1906 01:44:24.211961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1908 01:44:24.310844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1909 01:44:24.311373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1911 01:44:24.409380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1912 01:44:24.409883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1914 01:44:24.504453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1915 01:44:24.504949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1917 01:44:24.602799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1918 01:44:24.603315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1920 01:44:24.696657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1921 01:44:24.697206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1923 01:44:24.793138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1924 01:44:24.793636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1926 01:44:24.889901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1927 01:44:24.890438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1929 01:44:24.986533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1930 01:44:24.987034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1932 01:44:25.081971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1933 01:44:25.082457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1935 01:44:25.176300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1936 01:44:25.176840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1938 01:44:25.270405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1939 01:44:25.270905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1941 01:44:25.370355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1942 01:44:25.370944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1944 01:44:25.465691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1945 01:44:25.466170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1947 01:44:25.564972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1948 01:44:25.565473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1950 01:44:25.661717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1951 01:44:25.662209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1953 01:44:25.759144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1955 01:44:25.762176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1956 01:44:25.857594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1958 01:44:25.860702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1959 01:44:25.954587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1961 01:44:25.957684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1962 01:44:26.055431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1963 01:44:26.055924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1965 01:44:26.154452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1966 01:44:26.154941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1968 01:44:26.249073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1969 01:44:26.249576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1971 01:44:26.346985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1972 01:44:26.347569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1974 01:44:26.442320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1975 01:44:26.442850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1977 01:44:26.536830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1978 01:44:26.537337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1980 01:44:26.631746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1981 01:44:26.632226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1983 01:44:26.730844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1984 01:44:26.731360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1986 01:44:26.825311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1987 01:44:26.825795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1989 01:44:26.923727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1990 01:44:26.924243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1992 01:44:27.022340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1993 01:44:27.022858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1995 01:44:27.121783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1996 01:44:27.122255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1998 01:44:27.215013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1999 01:44:27.215489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2001 01:44:27.315728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2002 01:44:27.316261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2004 01:44:27.414211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2005 01:44:27.414759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2007 01:44:27.512473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2008 01:44:27.513003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2010 01:44:27.610946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2011 01:44:27.611448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2013 01:44:27.708321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2014 01:44:27.708830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2016 01:44:27.805620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2017 01:44:27.806126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2019 01:44:27.903928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2020 01:44:27.904445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2022 01:44:27.997558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2023 01:44:27.998043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2025 01:44:28.089766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2026 01:44:28.090251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2028 01:44:28.183487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2029 01:44:28.183937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2031 01:44:28.277481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2032 01:44:28.277941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2034 01:44:28.371487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2035 01:44:28.372016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2037 01:44:28.472463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2038 01:44:28.473022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2040 01:44:28.566458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2041 01:44:28.566938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2043 01:44:28.662630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2044 01:44:28.663156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2046 01:44:28.761381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2047 01:44:28.761875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2049 01:44:28.858676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2050 01:44:28.859154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2052 01:44:28.957957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2053 01:44:28.958445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2055 01:44:29.056877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2056 01:44:29.057372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2058 01:44:29.153245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2059 01:44:29.153731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2061 01:44:29.247320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2062 01:44:29.247820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2064 01:44:29.342487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2065 01:44:29.343050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2067 01:44:29.442448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2068 01:44:29.442998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2070 01:44:29.539732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2071 01:44:29.540218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2073 01:44:29.638708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2074 01:44:29.639200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2076 01:44:29.732245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2077 01:44:29.732759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2079 01:44:29.832122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2080 01:44:29.832610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2082 01:44:29.940747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2083 01:44:29.941238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2085 01:44:30.040533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2086 01:44:30.041036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2088 01:44:30.134296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2089 01:44:30.134771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2091 01:44:30.232661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2092 01:44:30.233151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2094 01:44:30.331167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2095 01:44:30.331690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2097 01:44:30.431856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2098 01:44:30.432373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2100 01:44:30.531251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2101 01:44:30.531735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2103 01:44:30.629720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2104 01:44:30.630207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2106 01:44:30.723057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2107 01:44:30.723547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2109 01:44:30.823616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2110 01:44:30.824117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2112 01:44:30.919716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2113 01:44:30.920195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2115 01:44:31.018490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2116 01:44:31.019005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2118 01:44:31.112457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2119 01:44:31.112967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2121 01:44:31.207201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2122 01:44:31.207678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2124 01:44:31.301445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2125 01:44:31.301919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2127 01:44:31.399244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2128 01:44:31.399793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2130 01:44:31.492586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2131 01:44:31.493084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2133 01:44:31.586693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2134 01:44:31.587168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2136 01:44:31.680826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2137 01:44:31.681305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2139 01:44:31.775078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2140 01:44:31.775554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2142 01:44:31.870303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2143 01:44:31.870777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2145 01:44:31.963046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2146 01:44:31.963519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2148 01:44:32.058301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2149 01:44:32.058778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2151 01:44:32.152288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2152 01:44:32.152767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2154 01:44:32.251946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2155 01:44:32.252414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2157 01:44:32.349431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2158 01:44:32.349952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2160 01:44:32.447073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2161 01:44:32.447618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2163 01:44:32.545600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2164 01:44:32.546121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2166 01:44:32.637773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2167 01:44:32.638254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2169 01:44:32.732179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2170 01:44:32.732656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2172 01:44:32.828560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2173 01:44:32.829079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2175 01:44:32.923384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2176 01:44:32.923900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2178 01:44:33.022499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2179 01:44:33.022997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2181 01:44:33.121752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2182 01:44:33.122250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2184 01:44:33.223364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2185 01:44:33.223861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2187 01:44:33.321393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2188 01:44:33.321942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2190 01:44:33.422484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2191 01:44:33.423023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2193 01:44:33.523364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2194 01:44:33.523859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2196 01:44:33.618443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2197 01:44:33.618938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2199 01:44:33.720225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2200 01:44:33.720730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2202 01:44:33.821352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2203 01:44:33.821846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2205 01:44:33.922715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2206 01:44:33.923209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2208 01:44:34.023093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2209 01:44:34.023588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2211 01:44:34.122532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2212 01:44:34.123028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2214 01:44:34.217908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2215 01:44:34.218402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2217 01:44:34.313620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2218 01:44:34.314106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2220 01:44:34.407083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2221 01:44:34.407653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2223 01:44:34.504702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2224 01:44:34.505215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2226 01:44:34.598692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2227 01:44:34.599179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2229 01:44:34.694286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2230 01:44:34.694776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2232 01:44:34.788351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2233 01:44:34.788854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2235 01:44:34.881223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2236 01:44:34.881707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2238 01:44:34.978305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2239 01:44:34.978789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2241 01:44:35.075303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2242 01:44:35.075788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2244 01:44:35.171651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2245 01:44:35.172138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2247 01:44:35.264051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2248 01:44:35.264536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2250 01:44:35.357882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2251 01:44:35.358423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2253 01:44:35.453915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2254 01:44:35.454449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2256 01:44:35.549458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2257 01:44:35.549941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2259 01:44:35.649539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2260 01:44:35.650030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2262 01:44:35.745103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2263 01:44:35.745597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2265 01:44:35.837907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2266 01:44:35.838391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2268 01:44:35.932904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2269 01:44:35.933404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2271 01:44:36.031901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2272 01:44:36.032416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2274 01:44:36.128049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2276 01:44:36.131021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2277 01:44:36.223994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2278 01:44:36.224482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2280 01:44:36.324135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2281 01:44:36.324622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2283 01:44:36.420332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2284 01:44:36.420877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2286 01:44:36.520574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2287 01:44:36.521089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2289 01:44:36.619699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2290 01:44:36.620188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2292 01:44:36.717245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2293 01:44:36.717732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2295 01:44:36.813692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2296 01:44:36.814177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2298 01:44:36.910433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2299 01:44:36.910916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2301 01:44:37.009808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2302 01:44:37.010294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2304 01:44:37.106211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2305 01:44:37.106697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2307 01:44:37.204730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2308 01:44:37.205216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2310 01:44:37.295929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2311 01:44:37.296414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2313 01:44:37.391579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2314 01:44:37.392127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2316 01:44:37.486165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2317 01:44:37.486649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2319 01:44:37.580838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2320 01:44:37.581151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2322 01:44:37.673908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2323 01:44:37.674405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2325 01:44:37.769586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2326 01:44:37.770072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2328 01:44:37.859708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2329 01:44:37.860192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2331 01:44:37.957423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2332 01:44:37.957909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2334 01:44:38.055266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2335 01:44:38.055755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2337 01:44:38.153151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2338 01:44:38.153634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2340 01:44:38.250008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2341 01:44:38.250494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2343 01:44:38.347269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2344 01:44:38.347805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2346 01:44:38.441410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2347 01:44:38.441934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2349 01:44:38.534014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2350 01:44:38.534487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2352 01:44:38.627636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2353 01:44:38.628123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2355 01:44:38.721486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2356 01:44:38.721963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2358 01:44:38.814471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2359 01:44:38.814974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2361 01:44:38.910939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2362 01:44:38.911429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2364 01:44:39.004859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2365 01:44:39.005347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2367 01:44:39.098195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2368 01:44:39.098509 + set +x
2369 01:44:39.098998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2371 01:44:39.107582 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1214595_1.6.2.4.5>
2372 01:44:39.107823 <LAVA_TEST_RUNNER EXIT>
2373 01:44:39.108285 Received signal: <ENDRUN> 1_kselftest-dt 1214595_1.6.2.4.5
2374 01:44:39.108535 Ending use of test pattern.
2375 01:44:39.108803 Ending test lava.1_kselftest-dt (1214595_1.6.2.4.5), duration 94.41
2377 01:44:39.109681 ok: lava_test_shell seems to have completed
2378 01:44:39.115611 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2379 01:44:39.116731 end: 3.1 lava-test-shell (duration 00:01:36) [common]
2380 01:44:39.117072 end: 3 lava-test-retry (duration 00:01:36) [common]
2381 01:44:39.117413 start: 4 finalize (timeout 00:05:47) [common]
2382 01:44:39.117762 start: 4.1 power-off (timeout 00:00:30) [common]
2383 01:44:39.118190 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2384 01:44:39.485084 Returned 0 in 0 seconds
2385 01:44:39.585980 end: 4.1 power-off (duration 00:00:00) [common]
2387 01:44:39.586894 start: 4.2 read-feedback (timeout 00:05:47) [common]
2388 01:44:39.587505 Listened to connection for namespace 'common' for up to 1s
2389 01:44:39.588054 Listened to connection for namespace 'common' for up to 1s
2390 01:44:40.588392 Finalising connection for namespace 'common'
2391 01:44:40.588838 Disconnecting from shell: Finalise
2392 01:44:40.589113 / #
2393 01:44:40.689664 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 01:44:40.690043 end: 4 finalize (duration 00:00:02) [common]
2395 01:44:40.690390 Cleaning after the job
2396 01:44:40.690710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/ramdisk
2397 01:44:40.694336 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/kernel
2398 01:44:40.697232 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/dtb
2399 01:44:40.697694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/nfsrootfs
2400 01:44:40.749029 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214595/tftp-deploy-t2u2o401/modules
2401 01:44:40.752479 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1214595
2402 01:44:41.411732 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1214595
2403 01:44:41.412015 Job finished correctly