Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:24:02.598933 lava-dispatcher, installed at version: 2024.01
2 01:24:02.599738 start: 0 validate
3 01:24:02.600255 Start time: 2024-11-01 01:24:02.600221+00:00 (UTC)
4 01:24:02.600800 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:24:02.601345 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:24:02.640741 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:24:02.641309 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 01:24:04.681508 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:24:04.682151 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:24:10.765050 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:24:10.765537 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 01:24:10.812341 validate duration: 8.21
14 01:24:10.813853 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:24:10.814459 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:24:10.815026 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:24:10.816047 Not decompressing ramdisk as can be used compressed.
18 01:24:10.816778 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:24:10.817272 saving as /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/ramdisk/rootfs.cpio.gz
20 01:24:10.817814 total size: 8181887 (7 MB)
21 01:24:10.865924 progress 0 % (0 MB)
22 01:24:10.876563 progress 5 % (0 MB)
23 01:24:10.886588 progress 10 % (0 MB)
24 01:24:10.897683 progress 15 % (1 MB)
25 01:24:10.905941 progress 20 % (1 MB)
26 01:24:10.911513 progress 25 % (1 MB)
27 01:24:10.916617 progress 30 % (2 MB)
28 01:24:10.922103 progress 35 % (2 MB)
29 01:24:10.927176 progress 40 % (3 MB)
30 01:24:10.932870 progress 45 % (3 MB)
31 01:24:10.938073 progress 50 % (3 MB)
32 01:24:10.943608 progress 55 % (4 MB)
33 01:24:10.948686 progress 60 % (4 MB)
34 01:24:10.954104 progress 65 % (5 MB)
35 01:24:10.959162 progress 70 % (5 MB)
36 01:24:10.964613 progress 75 % (5 MB)
37 01:24:10.969726 progress 80 % (6 MB)
38 01:24:10.975298 progress 85 % (6 MB)
39 01:24:10.980438 progress 90 % (7 MB)
40 01:24:10.985966 progress 95 % (7 MB)
41 01:24:10.990826 progress 100 % (7 MB)
42 01:24:10.991457 7 MB downloaded in 0.17 s (44.94 MB/s)
43 01:24:10.992014 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:24:10.992893 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:24:10.993179 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:24:10.993446 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:24:10.993937 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 01:24:10.994177 saving as /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/kernel/Image
50 01:24:10.994384 total size: 65665536 (62 MB)
51 01:24:10.994592 No compression specified
52 01:24:11.033522 progress 0 % (0 MB)
53 01:24:11.072981 progress 5 % (3 MB)
54 01:24:11.112019 progress 10 % (6 MB)
55 01:24:11.150590 progress 15 % (9 MB)
56 01:24:11.189086 progress 20 % (12 MB)
57 01:24:11.228342 progress 25 % (15 MB)
58 01:24:11.267965 progress 30 % (18 MB)
59 01:24:11.307534 progress 35 % (21 MB)
60 01:24:11.346933 progress 40 % (25 MB)
61 01:24:11.386395 progress 45 % (28 MB)
62 01:24:11.425997 progress 50 % (31 MB)
63 01:24:11.465893 progress 55 % (34 MB)
64 01:24:11.505984 progress 60 % (37 MB)
65 01:24:11.545699 progress 65 % (40 MB)
66 01:24:11.584297 progress 70 % (43 MB)
67 01:24:11.623004 progress 75 % (46 MB)
68 01:24:11.663461 progress 80 % (50 MB)
69 01:24:11.702411 progress 85 % (53 MB)
70 01:24:11.743682 progress 90 % (56 MB)
71 01:24:11.782687 progress 95 % (59 MB)
72 01:24:11.821268 progress 100 % (62 MB)
73 01:24:11.822103 62 MB downloaded in 0.83 s (75.66 MB/s)
74 01:24:11.822601 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:24:11.823414 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:24:11.823686 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:24:11.823949 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:24:11.824471 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:24:11.824754 saving as /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:24:11.824962 total size: 53209 (0 MB)
82 01:24:11.825170 No compression specified
83 01:24:11.858041 progress 61 % (0 MB)
84 01:24:11.858921 progress 100 % (0 MB)
85 01:24:11.859529 0 MB downloaded in 0.03 s (1.47 MB/s)
86 01:24:11.860104 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:24:11.861083 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:24:11.861413 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:24:11.861724 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:24:11.862342 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 01:24:11.862636 saving as /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/modules/modules.tar
93 01:24:11.862873 total size: 16419048 (15 MB)
94 01:24:11.863112 Using unxz to decompress xz
95 01:24:11.904540 progress 0 % (0 MB)
96 01:24:12.015540 progress 5 % (0 MB)
97 01:24:12.179288 progress 10 % (1 MB)
98 01:24:12.410460 progress 15 % (2 MB)
99 01:24:12.549080 progress 20 % (3 MB)
100 01:24:12.674082 progress 25 % (3 MB)
101 01:24:13.009029 progress 30 % (4 MB)
102 01:24:13.130295 progress 35 % (5 MB)
103 01:24:13.248237 progress 40 % (6 MB)
104 01:24:13.363852 progress 45 % (7 MB)
105 01:24:13.477591 progress 50 % (7 MB)
106 01:24:13.592160 progress 55 % (8 MB)
107 01:24:13.706658 progress 60 % (9 MB)
108 01:24:13.822869 progress 65 % (10 MB)
109 01:24:13.938426 progress 70 % (10 MB)
110 01:24:14.054019 progress 75 % (11 MB)
111 01:24:14.169230 progress 80 % (12 MB)
112 01:24:14.300361 progress 85 % (13 MB)
113 01:24:14.409057 progress 90 % (14 MB)
114 01:24:14.546108 progress 95 % (14 MB)
115 01:24:14.676120 progress 100 % (15 MB)
116 01:24:14.687877 15 MB downloaded in 2.82 s (5.54 MB/s)
117 01:24:14.688852 end: 1.4.1 http-download (duration 00:00:03) [common]
119 01:24:14.690505 end: 1.4 download-retry (duration 00:00:03) [common]
120 01:24:14.691043 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 01:24:14.691565 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 01:24:14.692115 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:24:14.692780 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 01:24:14.693920 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt
125 01:24:14.695029 makedir: /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin
126 01:24:14.695762 makedir: /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/tests
127 01:24:14.696433 makedir: /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/results
128 01:24:14.697048 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-add-keys
129 01:24:14.698065 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-add-sources
130 01:24:14.698995 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-background-process-start
131 01:24:14.699965 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-background-process-stop
132 01:24:14.701091 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-common-functions
133 01:24:14.702010 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-echo-ipv4
134 01:24:14.702907 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-install-packages
135 01:24:14.703780 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-installed-packages
136 01:24:14.704710 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-os-build
137 01:24:14.705587 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-probe-channel
138 01:24:14.706535 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-probe-ip
139 01:24:14.707591 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-target-ip
140 01:24:14.708548 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-target-mac
141 01:24:14.709439 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-target-storage
142 01:24:14.710338 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-case
143 01:24:14.711273 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-event
144 01:24:14.712191 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-feedback
145 01:24:14.713079 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-raise
146 01:24:14.713942 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-reference
147 01:24:14.714885 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-runner
148 01:24:14.715851 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-set
149 01:24:14.716789 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-test-shell
150 01:24:14.717698 Updating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-install-packages (oe)
151 01:24:14.718723 Updating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/bin/lava-installed-packages (oe)
152 01:24:14.719614 Creating /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/environment
153 01:24:14.720364 LAVA metadata
154 01:24:14.720840 - LAVA_JOB_ID=919757
155 01:24:14.721255 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:24:14.721911 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 01:24:14.723779 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:24:14.724401 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 01:24:14.724810 skipped lava-vland-overlay
160 01:24:14.725287 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:24:14.725780 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 01:24:14.726198 skipped lava-multinode-overlay
163 01:24:14.726667 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:24:14.727157 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 01:24:14.727620 Loading test definitions
166 01:24:14.728189 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 01:24:14.728623 Using /lava-919757 at stage 0
168 01:24:14.730912 uuid=919757_1.5.2.4.1 testdef=None
169 01:24:14.731492 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:24:14.732093 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 01:24:14.735648 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:24:14.737226 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 01:24:14.741680 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:24:14.743296 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 01:24:14.747575 runner path: /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/0/tests/0_dmesg test_uuid 919757_1.5.2.4.1
178 01:24:14.748681 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:24:14.750171 Creating lava-test-runner.conf files
181 01:24:14.750564 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919757/lava-overlay-fgw4p4rt/lava-919757/0 for stage 0
182 01:24:14.751189 - 0_dmesg
183 01:24:14.751831 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:24:14.752409 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 01:24:14.779588 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:24:14.780036 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 01:24:14.780303 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:24:14.780569 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:24:14.780831 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 01:24:15.752711 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:24:15.753155 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 01:24:15.753403 extracting modules file /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk
193 01:24:17.330150 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:24:17.330638 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
195 01:24:17.330918 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919757/compress-overlay-vd87bor5/overlay-1.5.2.5.tar.gz to ramdisk
196 01:24:17.331134 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919757/compress-overlay-vd87bor5/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk
197 01:24:17.361841 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:24:17.362291 start: 1.5.6 prepare-kernel (timeout 00:09:53) [common]
199 01:24:17.362563 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:53) [common]
200 01:24:17.362791 Converting downloaded kernel to a uImage
201 01:24:17.363098 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/kernel/Image /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/kernel/uImage
202 01:24:18.040283 output: Image Name:
203 01:24:18.040732 output: Created: Fri Nov 1 01:24:17 2024
204 01:24:18.041001 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:24:18.041262 output: Data Size: 65665536 Bytes = 64126.50 KiB = 62.62 MiB
206 01:24:18.041510 output: Load Address: 01080000
207 01:24:18.041754 output: Entry Point: 01080000
208 01:24:18.042000 output:
209 01:24:18.042398 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 01:24:18.042755 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 01:24:18.043114 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 01:24:18.043446 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:24:18.043775 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 01:24:18.044125 Building ramdisk /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk
215 01:24:21.736334 >> 257690 blocks
216 01:24:32.854400 Adding RAMdisk u-boot header.
217 01:24:32.854854 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk.cpio.gz.uboot
218 01:24:33.216316 output: Image Name:
219 01:24:33.216995 output: Created: Fri Nov 1 01:24:32 2024
220 01:24:33.217465 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:24:33.217925 output: Data Size: 34064079 Bytes = 33265.70 KiB = 32.49 MiB
222 01:24:33.218377 output: Load Address: 00000000
223 01:24:33.218818 output: Entry Point: 00000000
224 01:24:33.219255 output:
225 01:24:33.220196 rename /var/lib/lava/dispatcher/tmp/919757/extract-overlay-ramdisk-8e4au3cu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot
226 01:24:33.220965 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 01:24:33.221571 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 01:24:33.222161 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 01:24:33.222667 No LXC device requested
230 01:24:33.223231 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:24:33.223804 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 01:24:33.224398 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:24:33.224863 Checking files for TFTP limit of 4294967296 bytes.
234 01:24:33.227773 end: 1 tftp-deploy (duration 00:00:22) [common]
235 01:24:33.228445 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:24:33.229041 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:24:33.229600 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:24:33.230168 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:24:33.230761 Using kernel file from prepare-kernel: 919757/tftp-deploy-qie0wxel/kernel/uImage
240 01:24:33.231465 substitutions:
241 01:24:33.231934 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:24:33.232423 - {DTB_ADDR}: 0x01070000
243 01:24:33.232873 - {DTB}: 919757/tftp-deploy-qie0wxel/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:24:33.233325 - {INITRD}: 919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot
245 01:24:33.233767 - {KERNEL_ADDR}: 0x01080000
246 01:24:33.234204 - {KERNEL}: 919757/tftp-deploy-qie0wxel/kernel/uImage
247 01:24:33.234644 - {LAVA_MAC}: None
248 01:24:33.235130 - {PRESEED_CONFIG}: None
249 01:24:33.235574 - {PRESEED_LOCAL}: None
250 01:24:33.236042 - {RAMDISK_ADDR}: 0x08000000
251 01:24:33.236485 - {RAMDISK}: 919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot
252 01:24:33.236927 - {ROOT_PART}: None
253 01:24:33.237365 - {ROOT}: None
254 01:24:33.237800 - {SERVER_IP}: 192.168.6.2
255 01:24:33.238239 - {TEE_ADDR}: 0x83000000
256 01:24:33.238671 - {TEE}: None
257 01:24:33.239103 Parsed boot commands:
258 01:24:33.239524 - setenv autoload no
259 01:24:33.239952 - setenv initrd_high 0xffffffff
260 01:24:33.240415 - setenv fdt_high 0xffffffff
261 01:24:33.240844 - dhcp
262 01:24:33.241277 - setenv serverip 192.168.6.2
263 01:24:33.241706 - tftpboot 0x01080000 919757/tftp-deploy-qie0wxel/kernel/uImage
264 01:24:33.242138 - tftpboot 0x08000000 919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot
265 01:24:33.242570 - tftpboot 0x01070000 919757/tftp-deploy-qie0wxel/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:24:33.243000 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:24:33.243440 - bootm 0x01080000 0x08000000 0x01070000
268 01:24:33.244016 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:24:33.245678 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:24:33.246174 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:24:33.262876 Setting prompt string to ['lava-test: # ']
273 01:24:33.264503 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:24:33.265175 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:24:33.265784 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:24:33.266374 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:24:33.267644 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:24:33.302186 >> OK - accepted request
279 01:24:33.304367 Returned 0 in 0 seconds
280 01:24:33.405530 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:24:33.407284 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:24:33.407916 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:24:33.408538 Setting prompt string to ['Hit any key to stop autoboot']
285 01:24:33.409051 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:24:33.410766 Trying 192.168.56.21...
287 01:24:33.411298 Connected to conserv1.
288 01:24:33.411770 Escape character is '^]'.
289 01:24:33.412279
290 01:24:33.412763 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:24:33.413249
292 01:24:40.797328 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:24:40.798005 bl2_stage_init 0x01
294 01:24:40.798497 bl2_stage_init 0x81
295 01:24:40.802707 hw id: 0x0000 - pwm id 0x01
296 01:24:40.803220 bl2_stage_init 0xc1
297 01:24:40.808376 bl2_stage_init 0x02
298 01:24:40.808866
299 01:24:40.809335 L0:00000000
300 01:24:40.809792 L1:00000703
301 01:24:40.810233 L2:00008067
302 01:24:40.810667 L3:15000000
303 01:24:40.813872 S1:00000000
304 01:24:40.814350 B2:20282000
305 01:24:40.814793 B1:a0f83180
306 01:24:40.815227
307 01:24:40.815665 TE: 70993
308 01:24:40.816140
309 01:24:40.819555 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:24:40.820072
311 01:24:40.825272 Board ID = 1
312 01:24:40.825751 Set cpu clk to 24M
313 01:24:40.826196 Set clk81 to 24M
314 01:24:40.830698 Use GP1_pll as DSU clk.
315 01:24:40.831173 DSU clk: 1200 Mhz
316 01:24:40.831614 CPU clk: 1200 MHz
317 01:24:40.836438 Set clk81 to 166.6M
318 01:24:40.841887 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:24:40.842365 board id: 1
320 01:24:40.849082 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:24:40.860095 fw parse done
322 01:24:40.865981 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:24:40.909107 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:24:40.920263 PIEI prepare done
325 01:24:40.920753 fastboot data load
326 01:24:40.921209 fastboot data verify
327 01:24:40.925828 verify result: 266
328 01:24:40.931435 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:24:40.931923 LPDDR4 probe
330 01:24:40.932410 ddr clk to 1584MHz
331 01:24:40.939417 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:24:40.977149
333 01:24:40.977686 dmc_version 0001
334 01:24:40.984174 Check phy result
335 01:24:40.990203 INFO : End of CA training
336 01:24:40.990678 INFO : End of initialization
337 01:24:40.995732 INFO : Training has run successfully!
338 01:24:40.996287 Check phy result
339 01:24:41.001426 INFO : End of initialization
340 01:24:41.001896 INFO : End of read enable training
341 01:24:41.006913 INFO : End of fine write leveling
342 01:24:41.012498 INFO : End of Write leveling coarse delay
343 01:24:41.012976 INFO : Training has run successfully!
344 01:24:41.013420 Check phy result
345 01:24:41.018121 INFO : End of initialization
346 01:24:41.018607 INFO : End of read dq deskew training
347 01:24:41.023794 INFO : End of MPR read delay center optimization
348 01:24:41.029326 INFO : End of write delay center optimization
349 01:24:41.034915 INFO : End of read delay center optimization
350 01:24:41.035379 INFO : End of max read latency training
351 01:24:41.040562 INFO : Training has run successfully!
352 01:24:41.041029 1D training succeed
353 01:24:41.049708 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:24:41.097994 Check phy result
355 01:24:41.098476 INFO : End of initialization
356 01:24:41.125439 INFO : End of 2D read delay Voltage center optimization
357 01:24:41.149771 INFO : End of 2D read delay Voltage center optimization
358 01:24:41.206317 INFO : End of 2D write delay Voltage center optimization
359 01:24:41.260313 INFO : End of 2D write delay Voltage center optimization
360 01:24:41.265846 INFO : Training has run successfully!
361 01:24:41.266326
362 01:24:41.266775 channel==0
363 01:24:41.271550 RxClkDly_Margin_A0==88 ps 9
364 01:24:41.272067 TxDqDly_Margin_A0==98 ps 10
365 01:24:41.277062 RxClkDly_Margin_A1==88 ps 9
366 01:24:41.277546 TxDqDly_Margin_A1==98 ps 10
367 01:24:41.277990 TrainedVREFDQ_A0==77
368 01:24:41.282637 TrainedVREFDQ_A1==75
369 01:24:41.283103 VrefDac_Margin_A0==24
370 01:24:41.283544 DeviceVref_Margin_A0==37
371 01:24:41.288271 VrefDac_Margin_A1==23
372 01:24:41.288740 DeviceVref_Margin_A1==39
373 01:24:41.289187
374 01:24:41.289626
375 01:24:41.293815 channel==1
376 01:24:41.294285 RxClkDly_Margin_A0==78 ps 8
377 01:24:41.294726 TxDqDly_Margin_A0==98 ps 10
378 01:24:41.299480 RxClkDly_Margin_A1==88 ps 9
379 01:24:41.299960 TxDqDly_Margin_A1==88 ps 9
380 01:24:41.305040 TrainedVREFDQ_A0==77
381 01:24:41.305510 TrainedVREFDQ_A1==75
382 01:24:41.305959 VrefDac_Margin_A0==22
383 01:24:41.310657 DeviceVref_Margin_A0==37
384 01:24:41.311121 VrefDac_Margin_A1==22
385 01:24:41.316236 DeviceVref_Margin_A1==39
386 01:24:41.316699
387 01:24:41.317145 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:24:41.317581
389 01:24:41.349983 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000062
390 01:24:41.350547 2D training succeed
391 01:24:41.355583 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:24:41.361049 auto size-- 65535DDR cs0 size: 2048MB
393 01:24:41.361522 DDR cs1 size: 2048MB
394 01:24:41.366659 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:24:41.367130 cs0 DataBus test pass
396 01:24:41.372325 cs1 DataBus test pass
397 01:24:41.372837 cs0 AddrBus test pass
398 01:24:41.373296 cs1 AddrBus test pass
399 01:24:41.373736
400 01:24:41.377829 100bdlr_step_size ps== 471
401 01:24:41.378317 result report
402 01:24:41.383453 boot times 0Enable ddr reg access
403 01:24:41.388657 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:24:41.402530 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:24:42.060943 bl2z: ptr: 05129330, size: 00001e40
406 01:24:42.069309 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:24:42.069860 MVN_1=0x00000000
408 01:24:42.070136 MVN_2=0x00000000
409 01:24:42.080691 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:24:42.081072 OPS=0x04
411 01:24:42.081314 ring efuse init
412 01:24:42.086297 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:24:42.086634 [0.017354 Inits done]
414 01:24:42.086880 secure task start!
415 01:24:42.094184 high task start!
416 01:24:42.094519 low task start!
417 01:24:42.094753 run into bl31
418 01:24:42.102759 NOTICE: BL31: v1.3(release):4fc40b1
419 01:24:42.110611 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:24:42.110955 NOTICE: BL31: G12A normal boot!
421 01:24:42.126269 NOTICE: BL31: BL33 decompress pass
422 01:24:42.135041 ERROR: Error initializing runtime service opteed_fast
423 01:24:43.346092 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:24:43.346535 bl2_stage_init 0x01
425 01:24:43.346780 bl2_stage_init 0x81
426 01:24:43.351612 hw id: 0x0000 - pwm id 0x01
427 01:24:43.351968 bl2_stage_init 0xc1
428 01:24:43.357146 bl2_stage_init 0x02
429 01:24:43.357492
430 01:24:43.357731 L0:00000000
431 01:24:43.357968 L1:00000703
432 01:24:43.358197 L2:00008067
433 01:24:43.358435 L3:15000000
434 01:24:43.362775 S1:00000000
435 01:24:43.363117 B2:20282000
436 01:24:43.363351 B1:a0f83180
437 01:24:43.363572
438 01:24:43.363807 TE: 69500
439 01:24:43.364067
440 01:24:43.368362 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:24:43.368860
442 01:24:43.373964 Board ID = 1
443 01:24:43.374453 Set cpu clk to 24M
444 01:24:43.374900 Set clk81 to 24M
445 01:24:43.379579 Use GP1_pll as DSU clk.
446 01:24:43.380092 DSU clk: 1200 Mhz
447 01:24:43.380546 CPU clk: 1200 MHz
448 01:24:43.385181 Set clk81 to 166.6M
449 01:24:43.390811 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:24:43.391291 board id: 1
451 01:24:43.397951 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:24:43.408767 fw parse done
453 01:24:43.414654 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:24:43.457212 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:24:43.468277 PIEI prepare done
456 01:24:43.468843 fastboot data load
457 01:24:43.469364 fastboot data verify
458 01:24:43.473816 verify result: 266
459 01:24:43.479370 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:24:43.479832 LPDDR4 probe
461 01:24:43.480306 ddr clk to 1584MHz
462 01:24:44.850602 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, siz SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 01:24:44.851301 bl2_stage_init 0x01
464 01:24:44.851794 bl2_stage_init 0x81
465 01:24:44.856089 hw id: 0x0000 - pwm id 0x01
466 01:24:44.856680 bl2_stage_init 0xc1
467 01:24:44.861885 bl2_stage_init 0x02
468 01:24:44.862392
469 01:24:44.862852 L0:00000000
470 01:24:44.863336 L1:00000703
471 01:24:44.863855 L2:00008067
472 01:24:44.864400 L3:15000000
473 01:24:44.867801 S1:00000000
474 01:24:44.868379 B2:20282000
475 01:24:44.868842 B1:a0f83180
476 01:24:44.869304
477 01:24:44.869799 TE: 72891
478 01:24:44.870261
479 01:24:44.873088 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 01:24:44.873634
481 01:24:44.878511 Board ID = 1
482 01:24:44.879045 Set cpu clk to 24M
483 01:24:44.879523 Set clk81 to 24M
484 01:24:44.882006 Use GP1_pll as DSU clk.
485 01:24:44.882531 DSU clk: 1200 Mhz
486 01:24:44.887623 CPU clk: 1200 MHz
487 01:24:44.888161 Set clk81 to 166.6M
488 01:24:44.893206 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 01:24:44.893691 board id: 1
490 01:24:44.902498 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 01:24:44.913436 fw parse done
492 01:24:44.919465 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 01:24:44.962679 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 01:24:44.973651 PIEI prepare done
495 01:24:44.974228 fastboot data load
496 01:24:44.974687 fastboot data verify
497 01:24:44.979160 verify result: 266
498 01:24:44.984801 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 01:24:44.985360 LPDDR4 probe
500 01:24:44.985853 ddr clk to 1584MHz
501 01:24:44.992412 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 01:24:45.030555
503 01:24:45.031127 dmc_version 0001
504 01:24:45.036693 Check phy result
505 01:24:45.043608 INFO : End of CA training
506 01:24:45.044146 INFO : End of initialization
507 01:24:45.049176 INFO : Training has run successfully!
508 01:24:45.049693 Check phy result
509 01:24:45.055452 INFO : End of initialization
510 01:24:45.055965 INFO : End of read enable training
511 01:24:45.060450 INFO : End of fine write leveling
512 01:24:45.066078 INFO : End of Write leveling coarse delay
513 01:24:45.066584 INFO : Training has run successfully!
514 01:24:45.067033 Check phy result
515 01:24:45.071655 INFO : End of initialization
516 01:24:45.072205 INFO : End of read dq deskew training
517 01:24:45.077128 INFO : End of MPR read delay center optimization
518 01:24:45.082764 INFO : End of write delay center optimization
519 01:24:45.088378 INFO : End of read delay center optimization
520 01:24:45.088968 INFO : End of max read latency training
521 01:24:45.094040 INFO : Training has run successfully!
522 01:24:45.094607 1D training succeed
523 01:24:45.103235 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 01:24:45.153077 Check phy result
525 01:24:45.153787 INFO : End of initialization
526 01:24:45.179060 INFO : End of 2D read delay Voltage center optimization
527 01:24:45.203051 INFO : End of 2D read delay Voltage center optimization
528 01:24:45.259803 INFO : End of 2D write delay Voltage center optimization
529 01:24:45.313925 INFO : End of 2D write delay Voltage center optimization
530 01:24:45.319433 INFO : Training has run successfully!
531 01:24:45.319911
532 01:24:45.320268 channel==0
533 01:24:45.325112 RxClkDly_Margin_A0==88 ps 9
534 01:24:45.325755 TxDqDly_Margin_A0==98 ps 10
535 01:24:45.330402 RxClkDly_Margin_A1==88 ps 9
536 01:24:45.330744 TxDqDly_Margin_A1==88 ps 9
537 01:24:45.330951 TrainedVREFDQ_A0==75
538 01:24:45.336378 TrainedVREFDQ_A1==74
539 01:24:45.337003 VrefDac_Margin_A0==24
540 01:24:45.337428 DeviceVref_Margin_A0==39
541 01:24:45.342613 VrefDac_Margin_A1==22
542 01:24:45.343246 DeviceVref_Margin_A1==40
543 01:24:45.343679
544 01:24:45.344113
545 01:24:45.344514 channel==1
546 01:24:45.347420 RxClkDly_Margin_A0==78 ps 8
547 01:24:45.348044 TxDqDly_Margin_A0==98 ps 10
548 01:24:45.353119 RxClkDly_Margin_A1==88 ps 9
549 01:24:45.353992 TxDqDly_Margin_A1==88 ps 9
550 01:24:45.358606 TrainedVREFDQ_A0==78
551 01:24:45.359725 TrainedVREFDQ_A1==77
552 01:24:45.360218 VrefDac_Margin_A0==22
553 01:24:45.364363 DeviceVref_Margin_A0==36
554 01:24:45.364938 VrefDac_Margin_A1==20
555 01:24:45.369845 DeviceVref_Margin_A1==37
556 01:24:45.370426
557 01:24:45.370829 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 01:24:45.371224
559 01:24:45.403296 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 01:24:45.403750 2D training succeed
561 01:24:45.409132 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 01:24:45.414460 auto size-- 65535DDR cs0 size: 2048MB
563 01:24:45.414857 DDR cs1 size: 2048MB
564 01:24:45.420587 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 01:24:45.421012 cs0 DataBus test pass
566 01:24:45.425849 cs1 DataBus test pass
567 01:24:45.426245 cs0 AddrBus test pass
568 01:24:45.426607 cs1 AddrBus test pass
569 01:24:45.426828
570 01:24:45.431192 100bdlr_step_size ps== 485
571 01:24:45.431565 result report
572 01:24:45.436937 boot times 0Enable ddr reg access
573 01:24:45.442513 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 01:24:45.456086 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 01:24:46.115187 bl2z: ptr: 05129330, size: 00001e40
576 01:24:46.124403 0.0;M3 CHK:0;cm4_sp_mode 0
577 01:24:46.125086 MVN_1=0x00000000
578 01:24:46.125585 MVN_2=0x00000000
579 01:24:46.135598 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 01:24:46.136303 OPS=0x04
581 01:24:46.136760 ring efuse init
582 01:24:46.138423 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 01:24:46.144294 [0.017354 Inits done]
584 01:24:46.144977 secure task start!
585 01:24:46.145602 high task start!
586 01:24:46.146082 low task start!
587 01:24:46.148387 run into bl31
588 01:24:46.157114 NOTICE: BL31: v1.3(release):4fc40b1
589 01:24:46.164833 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 01:24:46.165253 NOTICE: BL31: G12A normal boot!
591 01:24:46.180723 NOTICE: BL31: BL33 decompress pass
592 01:24:47.397273 ERROR: Error initializing runtime servi SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
593 01:24:47.397935 bl2_stage_init 0x01
594 01:24:47.398478 bl2_stage_init 0x81
595 01:24:47.402683 hw id: 0x0000 - pwm id 0x01
596 01:24:47.403180 bl2_stage_init 0xc1
597 01:24:47.408294 bl2_stage_init 0x02
598 01:24:47.408768
599 01:24:47.409188 L0:00000000
600 01:24:47.409597 L1:00000703
601 01:24:47.410000 L2:00008067
602 01:24:47.410420 L3:15000000
603 01:24:47.413838 S1:00000000
604 01:24:47.414344 B2:20282000
605 01:24:47.414768 B1:a0f83180
606 01:24:47.415173
607 01:24:47.415578 TE: 70804
608 01:24:47.415976
609 01:24:47.419418 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
610 01:24:47.419855
611 01:24:47.425022 Board ID = 1
612 01:24:47.425485 Set cpu clk to 24M
613 01:24:47.425918 Set clk81 to 24M
614 01:24:47.430645 Use GP1_pll as DSU clk.
615 01:24:47.431168 DSU clk: 1200 Mhz
616 01:24:47.431616 CPU clk: 1200 MHz
617 01:24:47.436293 Set clk81 to 166.6M
618 01:24:47.441864 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
619 01:24:47.442362 board id: 1
620 01:24:47.449064 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
621 01:24:47.460075 fw parse done
622 01:24:47.465944 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
623 01:24:47.509096 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
624 01:24:47.520227 PIEI prepare done
625 01:24:47.520767 fastboot data load
626 01:24:47.521198 fastboot data verify
627 01:24:47.525837 verify result: 266
628 01:24:47.531415 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
629 01:24:47.532037 LPDDR4 probe
630 01:24:47.532452 ddr clk to 1584MHz
631 01:24:47.539447 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
632 01:24:47.577190
633 01:24:47.577814 dmc_version 0001
634 01:24:47.584111 Check phy result
635 01:24:47.590167 INFO : End of CA training
636 01:24:47.590660 INFO : End of initialization
637 01:24:47.595741 INFO : Training has run successfully!
638 01:24:47.596270 Check phy result
639 01:24:47.601357 INFO : End of initialization
640 01:24:47.601824 INFO : End of read enable training
641 01:24:47.606899 INFO : End of fine write leveling
642 01:24:47.612505 INFO : End of Write leveling coarse delay
643 01:24:47.612996 INFO : Training has run successfully!
644 01:24:47.613400 Check phy result
645 01:24:47.618087 INFO : End of initialization
646 01:24:47.618575 INFO : End of read dq deskew training
647 01:24:47.623713 INFO : End of MPR read delay center optimization
648 01:24:47.629408 INFO : End of write delay center optimization
649 01:24:47.634944 INFO : End of read delay center optimization
650 01:24:47.635430 INFO : End of max read latency training
651 01:24:47.640546 INFO : Training has run successfully!
652 01:24:47.641049 1D training succeed
653 01:24:47.649751 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
654 01:24:47.698018 Check phy result
655 01:24:47.698572 INFO : End of initialization
656 01:24:47.725596 INFO : End of 2D read delay Voltage center optimization
657 01:24:47.749741 INFO : End of 2D read delay Voltage center optimization
658 01:24:47.806336 INFO : End of 2D write delay Voltage center optimization
659 01:24:47.860348 INFO : End of 2D write delay Voltage center optimization
660 01:24:47.865792 INFO : Training has run successfully!
661 01:24:47.866320
662 01:24:47.866784 channel==0
663 01:24:47.871447 RxClkDly_Margin_A0==78 ps 8
664 01:24:47.871879 TxDqDly_Margin_A0==98 ps 10
665 01:24:47.876995 RxClkDly_Margin_A1==88 ps 9
666 01:24:47.877429 TxDqDly_Margin_A1==98 ps 10
667 01:24:47.877830 TrainedVREFDQ_A0==75
668 01:24:47.882688 TrainedVREFDQ_A1==74
669 01:24:47.883943 VrefDac_Margin_A0==24
670 01:24:47.889770 DeviceVref_Margin_A0==39
671 01:24:47.890537 VrefDac_Margin_A1==22
672 01:24:47.890968 DeviceVref_Margin_A1==40
673 01:24:47.891359
674 01:24:47.891753
675 01:24:47.893806 channel==1
676 01:24:47.894247 RxClkDly_Margin_A0==88 ps 9
677 01:24:47.894639 TxDqDly_Margin_A0==88 ps 9
678 01:24:47.899424 RxClkDly_Margin_A1==88 ps 9
679 01:24:47.899889 TxDqDly_Margin_A1==98 ps 10
680 01:24:47.905041 TrainedVREFDQ_A0==75
681 01:24:47.905473 TrainedVREFDQ_A1==78
682 01:24:47.905867 VrefDac_Margin_A0==22
683 01:24:47.912512 DeviceVref_Margin_A0==39
684 01:24:47.913146 VrefDac_Margin_A1==22
685 01:24:47.916237 DeviceVref_Margin_A1==36
686 01:24:47.916860
687 01:24:47.917396 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
688 01:24:47.917919
689 01:24:47.949826 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000016 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
690 01:24:47.950429 2D training succeed
691 01:24:47.955468 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
692 01:24:47.960987 auto size-- 65535DDR cs0 size: 2048MB
693 01:24:47.961477 DDR cs1 size: 2048MB
694 01:24:47.966618 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
695 01:24:47.967102 cs0 DataBus test pass
696 01:24:47.972316 cs1 DataBus test pass
697 01:24:47.972983 cs0 AddrBus test pass
698 01:24:47.973225 cs1 AddrBus test pass
699 01:24:47.973434
700 01:24:47.977809 100bdlr_step_size ps== 471
701 01:24:47.978190 result report
702 01:24:47.983427 boot times 0Enable ddr reg access
703 01:24:47.988722 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
704 01:24:48.002599 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
705 01:24:48.661903 bl2z: ptr: 05129330, size: 00001e40
706 01:24:48.669601 0.0;M3 CHK:0;cm4_sp_mode 0
707 01:24:48.670136 MVN_1=0x00000000
708 01:24:48.670539 MVN_2=0x00000000
709 01:24:48.680985 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
710 01:24:48.681897 OPS=0x04
711 01:24:48.682397 ring efuse init
712 01:24:48.683872 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
713 01:24:48.689922 [0.017354 Inits done]
714 01:24:48.690442 secure task start!
715 01:24:48.691074 high task start!
716 01:24:48.691728 low task start!
717 01:24:48.693718 run into bl31
718 01:24:48.702835 NOTICE: BL31: v1.3(release):4fc40b1
719 01:24:48.710667 NOTICE: BL31: Built : 15:57:33, May 22 2019
720 01:24:48.711258 NOTICE: BL31: G12A normal boot!
721 01:24:48.726228 NOTICE: BL31: BL33 decompress pass
722 01:24:48.731877 ERROR: Error initializing runtime service opteed_fast
723 01:24:49.527446
724 01:24:49.528288
725 01:24:49.532671 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
726 01:24:49.533201
727 01:24:49.536202 Model: Libre Computer AML-S905D3-CC Solitude
728 01:24:49.683325 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
729 01:24:49.698735 DRAM: 2 GiB (effective 3.8 GiB)
730 01:24:49.799690 Core: 406 devices, 33 uclasses, devicetree: separate
731 01:24:49.805491 WDT: Not starting watchdog@f0d0
732 01:24:49.830601 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
733 01:24:49.842794 Loading Environment from FAT... Card did not respond to voltage select! : -110
734 01:24:49.847749 ** Bad device specification mmc 0 **
735 01:24:49.857803 Card did not respond to voltage select! : -110
736 01:24:49.865445 ** Bad device specification mmc 0 **
737 01:24:49.865971 Couldn't find partition mmc 0
738 01:24:49.873750 Card did not respond to voltage select! : -110
739 01:24:49.879272 ** Bad device specification mmc 0 **
740 01:24:49.879782 Couldn't find partition mmc 0
741 01:24:49.884352 Error: could not access storage.
742 01:24:50.180884 Net: eth0: ethernet@ff3f0000
743 01:24:50.181554 starting USB...
744 01:24:50.425701 Bus usb@ff500000: Register 3000140 NbrPorts 3
745 01:24:50.426484 Starting the controller
746 01:24:50.432609 USB XHCI 1.10
747 01:24:51.986783 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
748 01:24:51.995004 scanning usb for storage devices... 0 Storage Device(s) found
750 01:24:52.046707 Hit any key to stop autoboot: 1
751 01:24:52.047698 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
752 01:24:52.048504 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
753 01:24:52.049023 Setting prompt string to ['=>']
754 01:24:52.049602 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
755 01:24:52.060992 0
756 01:24:52.062111 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
758 01:24:52.163751 => setenv autoload no
759 01:24:52.164781 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
760 01:24:52.171606 setenv autoload no
762 01:24:52.273575 => setenv initrd_high 0xffffffff
763 01:24:52.274621 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
764 01:24:52.279395 setenv initrd_high 0xffffffff
766 01:24:52.381035 => setenv fdt_high 0xffffffff
767 01:24:52.382078 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
768 01:24:52.386621 setenv fdt_high 0xffffffff
770 01:24:52.488344 => dhcp
771 01:24:52.489220 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
772 01:24:52.492679 dhcp
773 01:24:52.998901 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
774 01:24:52.999584 Speed: 1000, full duplex
775 01:24:53.000114 BOOTP broadcast 1
776 01:24:53.247204 BOOTP broadcast 2
777 01:24:53.273088 DHCP client bound to address 192.168.6.21 (273 ms)
779 01:24:53.375037 => setenv serverip 192.168.6.2
780 01:24:53.375924 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
781 01:24:53.380452 setenv serverip 192.168.6.2
783 01:24:53.482416 => tftpboot 0x01080000 919757/tftp-deploy-qie0wxel/kernel/uImage
784 01:24:53.483326 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
785 01:24:53.490068 tftpboot 0x01080000 919757/tftp-deploy-qie0wxel/kernel/uImage
786 01:24:53.490523 Speed: 1000, full duplex
787 01:24:53.490872 Using ethernet@ff3f0000 device
788 01:24:53.495553 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 01:24:53.501208 Filename '919757/tftp-deploy-qie0wxel/kernel/uImage'.
790 01:24:53.505119 Load address: 0x1080000
791 01:24:57.879955 Loading: *################################################## 62.6 MiB
792 01:24:57.880633 14.3 MiB/s
793 01:24:57.881038 done
794 01:24:57.884230 Bytes transferred = 65665600 (3e9fa40 hex)
796 01:24:57.985693 => tftpboot 0x08000000 919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot
797 01:24:57.986431 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
798 01:24:57.993174 tftpboot 0x08000000 919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot
799 01:24:57.993970 Speed: 1000, full duplex
800 01:24:57.994389 Using ethernet@ff3f0000 device
801 01:24:57.998790 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 01:24:58.008425 Filename '919757/tftp-deploy-qie0wxel/ramdisk/ramdisk.cpio.gz.uboot'.
803 01:24:58.008893 Load address: 0x8000000
804 01:25:01.325857 Loading: *############### UDP wrong checksum 000000ff 00001312
805 01:25:01.382934 UDP wrong checksum 000000ff 0000a404
806 01:25:05.308817 T ################################## UDP wrong checksum 00000007 000048cb
807 01:25:10.309999 T UDP wrong checksum 00000007 000048cb
808 01:25:20.312122 T T UDP wrong checksum 00000007 000048cb
809 01:25:40.316426 T T T T UDP wrong checksum 00000007 000048cb
810 01:25:48.701302 T UDP wrong checksum 000000ff 0000d01b
811 01:25:48.771731 UDP wrong checksum 000000ff 0000630e
812 01:25:55.319932 T
813 01:25:55.320405 Retry count exceeded; starting again
815 01:25:55.321325 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
818 01:25:55.322317 end: 2.4 uboot-commands (duration 00:01:22) [common]
820 01:25:55.323056 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 01:25:55.323624 end: 2 uboot-action (duration 00:01:22) [common]
824 01:25:55.324693 Cleaning after the job
825 01:25:55.325025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/ramdisk
826 01:25:55.325864 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/kernel
827 01:25:55.363739 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/dtb
828 01:25:55.364662 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919757/tftp-deploy-qie0wxel/modules
829 01:25:55.400357 start: 4.1 power-off (timeout 00:00:30) [common]
830 01:25:55.401061 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
831 01:25:55.435102 >> OK - accepted request
832 01:25:55.437191 Returned 0 in 0 seconds
833 01:25:55.537964 end: 4.1 power-off (duration 00:00:00) [common]
835 01:25:55.538960 start: 4.2 read-feedback (timeout 00:10:00) [common]
836 01:25:55.539624 Listened to connection for namespace 'common' for up to 1s
837 01:25:56.540573 Finalising connection for namespace 'common'
838 01:25:56.541062 Disconnecting from shell: Finalise
839 01:25:56.541347 =>
840 01:25:56.642157 end: 4.2 read-feedback (duration 00:00:01) [common]
841 01:25:56.642873 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919757
842 01:25:56.994163 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919757
843 01:25:56.994787 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.