Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:26:22.224827 lava-dispatcher, installed at version: 2024.01
2 01:26:22.225622 start: 0 validate
3 01:26:22.226086 Start time: 2024-11-01 01:26:22.226054+00:00 (UTC)
4 01:26:22.226669 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:26:22.227203 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:26:22.266669 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:26:22.267278 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 01:26:22.305096 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:26:22.305829 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:26:22.337128 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:26:22.337794 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:26:22.371512 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:26:22.372060 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 01:26:22.413829 validate duration: 0.19
16 01:26:22.414749 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:26:22.415123 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:26:22.415438 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:26:22.416113 Not decompressing ramdisk as can be used compressed.
20 01:26:22.416614 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 01:26:22.416894 saving as /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/ramdisk/initrd.cpio.gz
22 01:26:22.417182 total size: 5628182 (5 MB)
23 01:26:22.452221 progress 0 % (0 MB)
24 01:26:22.456283 progress 5 % (0 MB)
25 01:26:22.460356 progress 10 % (0 MB)
26 01:26:22.464063 progress 15 % (0 MB)
27 01:26:22.468074 progress 20 % (1 MB)
28 01:26:22.471662 progress 25 % (1 MB)
29 01:26:22.475709 progress 30 % (1 MB)
30 01:26:22.479767 progress 35 % (1 MB)
31 01:26:22.483356 progress 40 % (2 MB)
32 01:26:22.487397 progress 45 % (2 MB)
33 01:26:22.490970 progress 50 % (2 MB)
34 01:26:22.494998 progress 55 % (2 MB)
35 01:26:22.499173 progress 60 % (3 MB)
36 01:26:22.502801 progress 65 % (3 MB)
37 01:26:22.506826 progress 70 % (3 MB)
38 01:26:22.510559 progress 75 % (4 MB)
39 01:26:22.514541 progress 80 % (4 MB)
40 01:26:22.518109 progress 85 % (4 MB)
41 01:26:22.522179 progress 90 % (4 MB)
42 01:26:22.526048 progress 95 % (5 MB)
43 01:26:22.529469 progress 100 % (5 MB)
44 01:26:22.530234 5 MB downloaded in 0.11 s (47.49 MB/s)
45 01:26:22.530841 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:26:22.531836 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:26:22.532201 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:26:22.532504 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:26:22.533034 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 01:26:22.533309 saving as /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/kernel/Image
52 01:26:22.533526 total size: 65665536 (62 MB)
53 01:26:22.533748 No compression specified
54 01:26:22.581033 progress 0 % (0 MB)
55 01:26:22.622864 progress 5 % (3 MB)
56 01:26:22.664741 progress 10 % (6 MB)
57 01:26:22.706045 progress 15 % (9 MB)
58 01:26:22.746144 progress 20 % (12 MB)
59 01:26:22.786202 progress 25 % (15 MB)
60 01:26:22.825789 progress 30 % (18 MB)
61 01:26:22.865304 progress 35 % (21 MB)
62 01:26:22.904990 progress 40 % (25 MB)
63 01:26:22.944521 progress 45 % (28 MB)
64 01:26:22.984431 progress 50 % (31 MB)
65 01:26:23.024255 progress 55 % (34 MB)
66 01:26:23.063806 progress 60 % (37 MB)
67 01:26:23.103711 progress 65 % (40 MB)
68 01:26:23.144293 progress 70 % (43 MB)
69 01:26:23.185309 progress 75 % (46 MB)
70 01:26:23.232770 progress 80 % (50 MB)
71 01:26:23.278351 progress 85 % (53 MB)
72 01:26:23.320844 progress 90 % (56 MB)
73 01:26:23.363230 progress 95 % (59 MB)
74 01:26:23.403492 progress 100 % (62 MB)
75 01:26:23.404389 62 MB downloaded in 0.87 s (71.91 MB/s)
76 01:26:23.404931 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:26:23.405924 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:26:23.406279 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:26:23.406573 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:26:23.407134 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 01:26:23.407499 saving as /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 01:26:23.407767 total size: 53209 (0 MB)
84 01:26:23.408024 No compression specified
85 01:26:23.452950 progress 61 % (0 MB)
86 01:26:23.454165 progress 100 % (0 MB)
87 01:26:23.454960 0 MB downloaded in 0.05 s (1.08 MB/s)
88 01:26:23.455655 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:26:23.456662 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:26:23.456967 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:26:23.457242 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:26:23.457802 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 01:26:23.458089 saving as /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/nfsrootfs/full.rootfs.tar
95 01:26:23.458390 total size: 107552908 (102 MB)
96 01:26:23.458622 Using unxz to decompress xz
97 01:26:23.498659 progress 0 % (0 MB)
98 01:26:24.171126 progress 5 % (5 MB)
99 01:26:24.901977 progress 10 % (10 MB)
100 01:26:25.627163 progress 15 % (15 MB)
101 01:26:26.397425 progress 20 % (20 MB)
102 01:26:26.970984 progress 25 % (25 MB)
103 01:26:27.595712 progress 30 % (30 MB)
104 01:26:28.472938 progress 35 % (35 MB)
105 01:26:28.906151 progress 40 % (41 MB)
106 01:26:29.467485 progress 45 % (46 MB)
107 01:26:30.359814 progress 50 % (51 MB)
108 01:26:31.247742 progress 55 % (56 MB)
109 01:26:32.209134 progress 60 % (61 MB)
110 01:26:32.979879 progress 65 % (66 MB)
111 01:26:33.724137 progress 70 % (71 MB)
112 01:26:34.518012 progress 75 % (76 MB)
113 01:26:35.212602 progress 80 % (82 MB)
114 01:26:35.946717 progress 85 % (87 MB)
115 01:26:36.687952 progress 90 % (92 MB)
116 01:26:37.403891 progress 95 % (97 MB)
117 01:26:38.159188 progress 100 % (102 MB)
118 01:26:38.172128 102 MB downloaded in 14.71 s (6.97 MB/s)
119 01:26:38.172917 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:26:38.174060 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:26:38.174460 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:26:38.174824 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:26:38.175518 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 01:26:38.175878 saving as /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/modules/modules.tar
126 01:26:38.176191 total size: 16419048 (15 MB)
127 01:26:38.176489 Using unxz to decompress xz
128 01:26:38.213929 progress 0 % (0 MB)
129 01:26:38.330401 progress 5 % (0 MB)
130 01:26:38.448437 progress 10 % (1 MB)
131 01:26:38.561832 progress 15 % (2 MB)
132 01:26:38.676951 progress 20 % (3 MB)
133 01:26:38.787557 progress 25 % (3 MB)
134 01:26:38.906536 progress 30 % (4 MB)
135 01:26:39.020877 progress 35 % (5 MB)
136 01:26:39.136822 progress 40 % (6 MB)
137 01:26:39.254370 progress 45 % (7 MB)
138 01:26:39.369594 progress 50 % (7 MB)
139 01:26:39.491670 progress 55 % (8 MB)
140 01:26:39.607354 progress 60 % (9 MB)
141 01:26:39.724983 progress 65 % (10 MB)
142 01:26:39.842868 progress 70 % (10 MB)
143 01:26:39.960963 progress 75 % (11 MB)
144 01:26:40.076520 progress 80 % (12 MB)
145 01:26:40.207653 progress 85 % (13 MB)
146 01:26:40.317532 progress 90 % (14 MB)
147 01:26:40.455022 progress 95 % (14 MB)
148 01:26:40.585203 progress 100 % (15 MB)
149 01:26:40.597417 15 MB downloaded in 2.42 s (6.47 MB/s)
150 01:26:40.598026 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:26:40.598849 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:26:40.599121 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 01:26:40.599386 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 01:26:50.407650 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/919765/extract-nfsrootfs-0rqs8y2t
156 01:26:50.408297 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 01:26:50.408593 start: 1.6.2 lava-overlay (timeout 00:09:32) [common]
158 01:26:50.409220 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue
159 01:26:50.409644 makedir: /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin
160 01:26:50.409972 makedir: /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/tests
161 01:26:50.410291 makedir: /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/results
162 01:26:50.410628 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-add-keys
163 01:26:50.411164 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-add-sources
164 01:26:50.411675 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-background-process-start
165 01:26:50.412196 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-background-process-stop
166 01:26:50.412730 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-common-functions
167 01:26:50.413274 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-echo-ipv4
168 01:26:50.413780 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-install-packages
169 01:26:50.414266 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-installed-packages
170 01:26:50.414742 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-os-build
171 01:26:50.415215 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-probe-channel
172 01:26:50.415683 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-probe-ip
173 01:26:50.416181 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-target-ip
174 01:26:50.416663 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-target-mac
175 01:26:50.417161 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-target-storage
176 01:26:50.417681 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-case
177 01:26:50.418179 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-event
178 01:26:50.418666 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-feedback
179 01:26:50.419149 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-raise
180 01:26:50.419629 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-reference
181 01:26:50.420142 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-runner
182 01:26:50.420651 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-set
183 01:26:50.421144 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-test-shell
184 01:26:50.421722 Updating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-install-packages (oe)
185 01:26:50.422274 Updating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/bin/lava-installed-packages (oe)
186 01:26:50.422745 Creating /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/environment
187 01:26:50.423131 LAVA metadata
188 01:26:50.423400 - LAVA_JOB_ID=919765
189 01:26:50.423618 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:26:50.424016 start: 1.6.2.1 ssh-authorize (timeout 00:09:32) [common]
191 01:26:50.425037 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:26:50.425370 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:32) [common]
193 01:26:50.425583 skipped lava-vland-overlay
194 01:26:50.425830 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:26:50.426088 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:32) [common]
196 01:26:50.426310 skipped lava-multinode-overlay
197 01:26:50.426554 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:26:50.426808 start: 1.6.2.4 test-definition (timeout 00:09:32) [common]
199 01:26:50.427061 Loading test definitions
200 01:26:50.427340 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:32) [common]
201 01:26:50.427564 Using /lava-919765 at stage 0
202 01:26:50.428793 uuid=919765_1.6.2.4.1 testdef=None
203 01:26:50.429119 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:26:50.429387 start: 1.6.2.4.2 test-overlay (timeout 00:09:32) [common]
205 01:26:50.431189 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:26:50.432010 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:32) [common]
208 01:26:50.434321 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:26:50.435153 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:32) [common]
211 01:26:50.437336 runner path: /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/0/tests/0_dmesg test_uuid 919765_1.6.2.4.1
212 01:26:50.437887 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:26:50.438646 Creating lava-test-runner.conf files
215 01:26:50.438849 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919765/lava-overlay-rnv40zue/lava-919765/0 for stage 0
216 01:26:50.439185 - 0_dmesg
217 01:26:50.439523 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:26:50.439797 start: 1.6.2.5 compress-overlay (timeout 00:09:32) [common]
219 01:26:50.461509 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:26:50.461935 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:32) [common]
221 01:26:50.462201 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:26:50.462472 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:26:50.462736 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
224 01:26:51.082252 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:26:51.082715 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
226 01:26:51.082964 extracting modules file /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919765/extract-nfsrootfs-0rqs8y2t
227 01:26:52.635870 extracting modules file /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919765/extract-overlay-ramdisk-yjl8tgvs/ramdisk
228 01:26:54.229219 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:26:54.229693 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
230 01:26:54.229973 [common] Applying overlay to NFS
231 01:26:54.230187 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919765/compress-overlay-d72uvc7c/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919765/extract-nfsrootfs-0rqs8y2t
232 01:26:54.259355 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:26:54.259745 start: 1.6.6 prepare-kernel (timeout 00:09:28) [common]
234 01:26:54.260050 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:28) [common]
235 01:26:54.260288 Converting downloaded kernel to a uImage
236 01:26:54.260602 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/kernel/Image /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/kernel/uImage
237 01:26:54.923828 output: Image Name:
238 01:26:54.924291 output: Created: Fri Nov 1 01:26:54 2024
239 01:26:54.924508 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:26:54.924716 output: Data Size: 65665536 Bytes = 64126.50 KiB = 62.62 MiB
241 01:26:54.924921 output: Load Address: 01080000
242 01:26:54.925123 output: Entry Point: 01080000
243 01:26:54.925321 output:
244 01:26:54.925667 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 01:26:54.925945 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 01:26:54.926218 start: 1.6.7 configure-preseed-file (timeout 00:09:27) [common]
247 01:26:54.926476 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:26:54.926736 start: 1.6.8 compress-ramdisk (timeout 00:09:27) [common]
249 01:26:54.927012 Building ramdisk /var/lib/lava/dispatcher/tmp/919765/extract-overlay-ramdisk-yjl8tgvs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919765/extract-overlay-ramdisk-yjl8tgvs/ramdisk
250 01:26:58.032680 >> 242908 blocks
251 01:27:08.677678 Adding RAMdisk u-boot header.
252 01:27:08.678131 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919765/extract-overlay-ramdisk-yjl8tgvs/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919765/extract-overlay-ramdisk-yjl8tgvs/ramdisk.cpio.gz.uboot
253 01:27:09.001470 output: Image Name:
254 01:27:09.001910 output: Created: Fri Nov 1 01:27:08 2024
255 01:27:09.002164 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:27:09.002422 output: Data Size: 31443027 Bytes = 30706.08 KiB = 29.99 MiB
257 01:27:09.002665 output: Load Address: 00000000
258 01:27:09.002910 output: Entry Point: 00000000
259 01:27:09.003160 output:
260 01:27:09.003771 rename /var/lib/lava/dispatcher/tmp/919765/extract-overlay-ramdisk-yjl8tgvs/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot
261 01:27:09.004277 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 01:27:09.004779 end: 1.6 prepare-tftp-overlay (duration 00:00:28) [common]
263 01:27:09.005136 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
264 01:27:09.005435 No LXC device requested
265 01:27:09.005761 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:27:09.006071 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
267 01:27:09.006388 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:27:09.006658 Checking files for TFTP limit of 4294967296 bytes.
269 01:27:09.008212 end: 1 tftp-deploy (duration 00:00:47) [common]
270 01:27:09.008586 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:27:09.008931 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:27:09.009255 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:27:09.009577 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:27:09.009916 Using kernel file from prepare-kernel: 919765/tftp-deploy-ujb18u71/kernel/uImage
275 01:27:09.010303 substitutions:
276 01:27:09.010564 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:27:09.010807 - {DTB_ADDR}: 0x01070000
278 01:27:09.011190 - {DTB}: 919765/tftp-deploy-ujb18u71/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 01:27:09.011464 - {INITRD}: 919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot
280 01:27:09.011702 - {KERNEL_ADDR}: 0x01080000
281 01:27:09.011927 - {KERNEL}: 919765/tftp-deploy-ujb18u71/kernel/uImage
282 01:27:09.012182 - {LAVA_MAC}: None
283 01:27:09.012454 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/919765/extract-nfsrootfs-0rqs8y2t
284 01:27:09.012711 - {NFS_SERVER_IP}: 192.168.6.2
285 01:27:09.012942 - {PRESEED_CONFIG}: None
286 01:27:09.013168 - {PRESEED_LOCAL}: None
287 01:27:09.013408 - {RAMDISK_ADDR}: 0x08000000
288 01:27:09.013637 - {RAMDISK}: 919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot
289 01:27:09.013879 - {ROOT_PART}: None
290 01:27:09.014239 - {ROOT}: None
291 01:27:09.014644 - {SERVER_IP}: 192.168.6.2
292 01:27:09.014915 - {TEE_ADDR}: 0x83000000
293 01:27:09.015150 - {TEE}: None
294 01:27:09.015379 Parsed boot commands:
295 01:27:09.015596 - setenv autoload no
296 01:27:09.015839 - setenv initrd_high 0xffffffff
297 01:27:09.016086 - setenv fdt_high 0xffffffff
298 01:27:09.016325 - dhcp
299 01:27:09.016564 - setenv serverip 192.168.6.2
300 01:27:09.016800 - tftpboot 0x01080000 919765/tftp-deploy-ujb18u71/kernel/uImage
301 01:27:09.017030 - tftpboot 0x08000000 919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot
302 01:27:09.017268 - tftpboot 0x01070000 919765/tftp-deploy-ujb18u71/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 01:27:09.017500 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919765/extract-nfsrootfs-0rqs8y2t,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:27:09.017880 - bootm 0x01080000 0x08000000 0x01070000
305 01:27:09.018234 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:27:09.019122 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:27:09.019385 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 01:27:09.031966 Setting prompt string to ['lava-test: # ']
310 01:27:09.032972 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:27:09.033387 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:27:09.033744 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:27:09.034198 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:27:09.034896 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 01:27:09.066842 >> OK - accepted request
316 01:27:09.068836 Returned 0 in 0 seconds
317 01:27:09.170012 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:27:09.171761 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:27:09.172421 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:27:09.172963 Setting prompt string to ['Hit any key to stop autoboot']
322 01:27:09.173448 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:27:09.175004 Trying 192.168.56.21...
324 01:27:09.175492 Connected to conserv1.
325 01:27:09.175918 Escape character is '^]'.
326 01:27:09.176384
327 01:27:09.176818 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:27:09.177238
329 01:27:16.547740 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 01:27:16.548411 bl2_stage_init 0x01
331 01:27:16.548843 bl2_stage_init 0x81
332 01:27:16.553285 hw id: 0x0000 - pwm id 0x01
333 01:27:16.553753 bl2_stage_init 0xc1
334 01:27:16.558087 bl2_stage_init 0x02
335 01:27:16.558540
336 01:27:16.558959 L0:00000000
337 01:27:16.559364 L1:00000703
338 01:27:16.559779 L2:00008067
339 01:27:16.563740 L3:15000000
340 01:27:16.564232 S1:00000000
341 01:27:16.564650 B2:20282000
342 01:27:16.565072 B1:a0f83180
343 01:27:16.565472
344 01:27:16.565871 TE: 70686
345 01:27:16.566270
346 01:27:16.574971 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 01:27:16.575435
348 01:27:16.575845 Board ID = 1
349 01:27:16.576282 Set cpu clk to 24M
350 01:27:16.576683 Set clk81 to 24M
351 01:27:16.580471 Use GP1_pll as DSU clk.
352 01:27:16.580916 DSU clk: 1200 Mhz
353 01:27:16.581323 CPU clk: 1200 MHz
354 01:27:16.585991 Set clk81 to 166.6M
355 01:27:16.591611 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 01:27:16.592086 board id: 1
357 01:27:16.599575 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:27:16.610216 fw parse done
359 01:27:16.616212 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:27:16.658011 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:27:16.670015 PIEI prepare done
362 01:27:16.670502 fastboot data load
363 01:27:16.670922 fastboot data verify
364 01:27:16.675485 verify result: 266
365 01:27:16.681069 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 01:27:16.681693 LPDDR4 probe
367 01:27:16.682218 ddr clk to 1584MHz
368 01:27:16.689118 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:27:16.726292
370 01:27:16.726812 dmc_version 0001
371 01:27:16.733074 Check phy result
372 01:27:16.738953 INFO : End of CA training
373 01:27:16.739416 INFO : End of initialization
374 01:27:16.744518 INFO : Training has run successfully!
375 01:27:16.744985 Check phy result
376 01:27:16.750070 INFO : End of initialization
377 01:27:16.750528 INFO : End of read enable training
378 01:27:16.755737 INFO : End of fine write leveling
379 01:27:16.761280 INFO : End of Write leveling coarse delay
380 01:27:16.761745 INFO : Training has run successfully!
381 01:27:16.762152 Check phy result
382 01:27:16.766992 INFO : End of initialization
383 01:27:16.767474 INFO : End of read dq deskew training
384 01:27:16.772489 INFO : End of MPR read delay center optimization
385 01:27:16.778127 INFO : End of write delay center optimization
386 01:27:16.783723 INFO : End of read delay center optimization
387 01:27:16.784218 INFO : End of max read latency training
388 01:27:16.789334 INFO : Training has run successfully!
389 01:27:16.789816 1D training succeed
390 01:27:16.798480 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:27:16.846088 Check phy result
392 01:27:16.846597 INFO : End of initialization
393 01:27:16.868475 INFO : End of 2D read delay Voltage center optimization
394 01:27:16.887702 INFO : End of 2D read delay Voltage center optimization
395 01:27:16.939654 INFO : End of 2D write delay Voltage center optimization
396 01:27:16.988903 INFO : End of 2D write delay Voltage center optimization
397 01:27:16.994277 INFO : Training has run successfully!
398 01:27:16.994746
399 01:27:16.995168 channel==0
400 01:27:17.000060 RxClkDly_Margin_A0==78 ps 8
401 01:27:17.000561 TxDqDly_Margin_A0==98 ps 10
402 01:27:17.003210 RxClkDly_Margin_A1==78 ps 8
403 01:27:17.003668 TxDqDly_Margin_A1==98 ps 10
404 01:27:17.008806 TrainedVREFDQ_A0==74
405 01:27:17.009289 TrainedVREFDQ_A1==74
406 01:27:17.014365 VrefDac_Margin_A0==24
407 01:27:17.014826 DeviceVref_Margin_A0==40
408 01:27:17.015238 VrefDac_Margin_A1==23
409 01:27:17.020058 DeviceVref_Margin_A1==40
410 01:27:17.020524
411 01:27:17.020939
412 01:27:17.021343 channel==1
413 01:27:17.021738 RxClkDly_Margin_A0==78 ps 8
414 01:27:17.023395 TxDqDly_Margin_A0==88 ps 9
415 01:27:17.029034 RxClkDly_Margin_A1==78 ps 8
416 01:27:17.029499 TxDqDly_Margin_A1==88 ps 9
417 01:27:17.029907 TrainedVREFDQ_A0==75
418 01:27:17.034569 TrainedVREFDQ_A1==75
419 01:27:17.035032 VrefDac_Margin_A0==22
420 01:27:17.038812 DeviceVref_Margin_A0==38
421 01:27:17.042014 VrefDac_Margin_A1==22
422 01:27:17.042468 DeviceVref_Margin_A1==39
423 01:27:17.042870
424 01:27:17.047624 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:27:17.048112
426 01:27:17.075563 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
427 01:27:17.081163 2D training succeed
428 01:27:17.086734 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:27:17.087175 auto size-- 65535DDR cs0 size: 2048MB
430 01:27:17.092330 DDR cs1 size: 2048MB
431 01:27:17.092768 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:27:17.097943 cs0 DataBus test pass
433 01:27:17.098378 cs1 DataBus test pass
434 01:27:17.098791 cs0 AddrBus test pass
435 01:27:17.103523 cs1 AddrBus test pass
436 01:27:17.103952
437 01:27:17.104407 100bdlr_step_size ps== 478
438 01:27:17.104813 result report
439 01:27:17.109125 boot times 0Enable ddr reg access
440 01:27:17.117023 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:27:17.130828 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 01:27:17.786767 bl2z: ptr: 05129330, size: 00001e40
443 01:27:17.793310 0.0;M3 CHK:0;cm4_sp_mode 0
444 01:27:17.793626 MVN_1=0x00000000
445 01:27:17.793846 MVN_2=0x00000000
446 01:27:17.804771 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 01:27:17.805216 OPS=0x04
448 01:27:17.805464 ring efuse init
449 01:27:17.807670 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 01:27:17.813544 [0.017319 Inits done]
451 01:27:17.813837 secure task start!
452 01:27:17.814053 high task start!
453 01:27:17.814260 low task start!
454 01:27:17.817643 run into bl31
455 01:27:17.826233 NOTICE: BL31: v1.3(release):4fc40b1
456 01:27:17.834265 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 01:27:17.834746 NOTICE: BL31: G12A normal boot!
458 01:27:17.849554 NOTICE: BL31: BL33 decompress pass
459 01:27:17.855457 ERROR: Error initializing runtime service opteed_fast
460 01:27:19.096443 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 01:27:19.096883 bl2_stage_init 0x01
462 01:27:19.097112 bl2_stage_init 0x81
463 01:27:19.102013 hw id: 0x0000 - pwm id 0x01
464 01:27:19.102425 bl2_stage_init 0xc1
465 01:27:19.107634 bl2_stage_init 0x02
466 01:27:19.108068
467 01:27:19.108424 L0:00000000
468 01:27:19.108671 L1:00000703
469 01:27:19.108885 L2:00008067
470 01:27:19.109090 L3:15000000
471 01:27:19.113257 S1:00000000
472 01:27:19.113669 B2:20282000
473 01:27:19.114012 B1:a0f83180
474 01:27:19.114332
475 01:27:19.114650 TE: 69298
476 01:27:19.114966
477 01:27:19.118830 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 01:27:19.119220
479 01:27:19.124400 Board ID = 1
480 01:27:19.124690 Set cpu clk to 24M
481 01:27:19.124906 Set clk81 to 24M
482 01:27:19.130374 Use GP1_pll as DSU clk.
483 01:27:19.130817 DSU clk: 1200 Mhz
484 01:27:19.131150 CPU clk: 1200 MHz
485 01:27:19.135680 Set clk81 to 166.6M
486 01:27:19.141301 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 01:27:19.141834 board id: 1
488 01:27:19.148571 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 01:27:19.159129 fw parse done
490 01:27:19.165009 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 01:27:19.207666 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 01:27:19.218561 PIEI prepare done
493 01:27:19.219094 fastboot data load
494 01:27:19.219495 fastboot data verify
495 01:27:19.224209 verify result: 266
496 01:27:19.229724 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 01:27:19.230154 LPDDR4 probe
498 01:27:19.230547 ddr clk to 1584MHz
499 01:27:20.595572 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 01:27:20.596183 bl2_stage_init 0x01
501 01:27:20.596617 bl2_stage_init 0x81
502 01:27:20.600997 hw id: 0x0000 - pwm id 0x01
503 01:27:20.601453 bl2_stage_init 0xc1
504 01:27:20.606290 bl2_stage_init 0x02
505 01:27:20.606733
506 01:27:20.607148 L0:00000000
507 01:27:20.607555 L1:00000703
508 01:27:20.607960 L2:00008067
509 01:27:20.608411 L3:15000000
510 01:27:20.611808 S1:00000000
511 01:27:20.612287 B2:20282000
512 01:27:20.612702 B1:a0f83180
513 01:27:20.613105
514 01:27:20.613511 TE: 68503
515 01:27:20.613914
516 01:27:20.617474 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 01:27:20.623087
518 01:27:20.623535 Board ID = 1
519 01:27:20.623944 Set cpu clk to 24M
520 01:27:20.624383 Set clk81 to 24M
521 01:27:20.626679 Use GP1_pll as DSU clk.
522 01:27:20.627115 DSU clk: 1200 Mhz
523 01:27:20.631943 CPU clk: 1200 MHz
524 01:27:20.632416 Set clk81 to 166.6M
525 01:27:20.637555 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 01:27:20.638002 board id: 1
527 01:27:20.648299 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 01:27:20.658313 fw parse done
529 01:27:20.663532 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 01:27:20.707399 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 01:27:20.718558 PIEI prepare done
532 01:27:20.719058 fastboot data load
533 01:27:20.719490 fastboot data verify
534 01:27:20.724176 verify result: 266
535 01:27:20.729696 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 01:27:20.730193 LPDDR4 probe
537 01:27:20.730616 ddr clk to 1584MHz
538 01:27:20.737653 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 01:27:20.775443
540 01:27:20.775945 dmc_version 0001
541 01:27:20.782721 Check phy result
542 01:27:20.788530 INFO : End of CA training
543 01:27:20.789050 INFO : End of initialization
544 01:27:20.794023 INFO : Training has run successfully!
545 01:27:20.794518 Check phy result
546 01:27:20.799661 INFO : End of initialization
547 01:27:20.800192 INFO : End of read enable training
548 01:27:20.805253 INFO : End of fine write leveling
549 01:27:20.810864 INFO : End of Write leveling coarse delay
550 01:27:20.811357 INFO : Training has run successfully!
551 01:27:20.811782 Check phy result
552 01:27:20.816524 INFO : End of initialization
553 01:27:20.817019 INFO : End of read dq deskew training
554 01:27:20.822027 INFO : End of MPR read delay center optimization
555 01:27:20.827643 INFO : End of write delay center optimization
556 01:27:20.833240 INFO : End of read delay center optimization
557 01:27:20.833731 INFO : End of max read latency training
558 01:27:20.838847 INFO : Training has run successfully!
559 01:27:20.839343 1D training succeed
560 01:27:20.847571 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 01:27:20.895547 Check phy result
562 01:27:20.896095 INFO : End of initialization
563 01:27:20.923722 INFO : End of 2D read delay Voltage center optimization
564 01:27:20.948038 INFO : End of 2D read delay Voltage center optimization
565 01:27:21.004661 INFO : End of 2D write delay Voltage center optimization
566 01:27:21.058711 INFO : End of 2D write delay Voltage center optimization
567 01:27:21.064263 INFO : Training has run successfully!
568 01:27:21.064765
569 01:27:21.065207 channel==0
570 01:27:21.069901 RxClkDly_Margin_A0==78 ps 8
571 01:27:21.070398 TxDqDly_Margin_A0==88 ps 9
572 01:27:21.073176 RxClkDly_Margin_A1==88 ps 9
573 01:27:21.073665 TxDqDly_Margin_A1==88 ps 9
574 01:27:21.078696 TrainedVREFDQ_A0==74
575 01:27:21.079196 TrainedVREFDQ_A1==74
576 01:27:21.079620 VrefDac_Margin_A0==24
577 01:27:21.084324 DeviceVref_Margin_A0==40
578 01:27:21.084807 VrefDac_Margin_A1==23
579 01:27:21.089882 DeviceVref_Margin_A1==40
580 01:27:21.090372
581 01:27:21.090789
582 01:27:21.091192 channel==1
583 01:27:21.091588 RxClkDly_Margin_A0==88 ps 9
584 01:27:21.093377 TxDqDly_Margin_A0==98 ps 10
585 01:27:21.098904 RxClkDly_Margin_A1==88 ps 9
586 01:27:21.099392 TxDqDly_Margin_A1==88 ps 9
587 01:27:21.099809 TrainedVREFDQ_A0==78
588 01:27:21.104622 TrainedVREFDQ_A1==75
589 01:27:21.105131 VrefDac_Margin_A0==22
590 01:27:21.110111 DeviceVref_Margin_A0==36
591 01:27:21.110610 VrefDac_Margin_A1==20
592 01:27:21.111020 DeviceVref_Margin_A1==39
593 01:27:21.111422
594 01:27:21.119064 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 01:27:21.119560
596 01:27:21.147065 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000018 00000019 00000015 00000018 00000015 00000016 00000017 00000019 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
597 01:27:21.147588 2D training succeed
598 01:27:21.152594 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 01:27:21.158150 auto size-- 65535DDR cs0 size: 2048MB
600 01:27:21.158637 DDR cs1 size: 2048MB
601 01:27:21.163786 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 01:27:21.164302 cs0 DataBus test pass
603 01:27:21.169501 cs1 DataBus test pass
604 01:27:21.169995 cs0 AddrBus test pass
605 01:27:21.170411 cs1 AddrBus test pass
606 01:27:21.174940
607 01:27:21.175427 100bdlr_step_size ps== 471
608 01:27:21.175852 result report
609 01:27:21.180572 boot times 0Enable ddr reg access
610 01:27:21.186787 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 01:27:21.200622 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 01:27:21.860020 bl2z: ptr: 05129330, size: 00001e40
613 01:27:21.868321 0.0;M3 CHK:0;cm4_sp_mode 0
614 01:27:21.868831 MVN_1=0x00000000
615 01:27:21.869256 MVN_2=0x00000000
616 01:27:21.879697 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 01:27:21.880220 OPS=0x04
618 01:27:21.880660 ring efuse init
619 01:27:21.885358 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 01:27:21.885869 [0.017354 Inits done]
621 01:27:21.886285 secure task start!
622 01:27:21.893252 high task start!
623 01:27:21.893739 low task start!
624 01:27:21.894154 run into bl31
625 01:27:21.901831 NOTICE: BL31: v1.3(release):4fc40b1
626 01:27:21.909666 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 01:27:21.910153 NOTICE: BL31: G12A normal boot!
628 01:27:21.925291 NOTICE: BL31: BL33 decompress pass
629 01:27:21.930912 ERROR: Error initializing runtime service opteed_fast
630 01:27:23.150054 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 01:27:23.150653 bl2_stage_init 0x01
632 01:27:23.151139 bl2_stage_init 0x81
633 01:27:23.155758 hw id: 0x0000 - pwm id 0x01
634 01:27:23.156309 bl2_stage_init 0xc1
635 01:27:23.156733 bl2_stage_init 0x02
636 01:27:23.157164
637 01:27:23.161332 L0:00000000
638 01:27:23.161825 L1:00000703
639 01:27:23.162272 L2:00008067
640 01:27:23.162696 L3:15000000
641 01:27:23.163096 S1:00000000
642 01:27:23.166914 B2:20282000
643 01:27:23.167412 B1:a0f83180
644 01:27:23.167828
645 01:27:23.168300 TE: 72326
646 01:27:23.168743
647 01:27:23.172504 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 01:27:23.172989
649 01:27:23.178109 Board ID = 1
650 01:27:23.178621 Set cpu clk to 24M
651 01:27:23.179064 Set clk81 to 24M
652 01:27:23.184055 Use GP1_pll as DSU clk.
653 01:27:23.184564 DSU clk: 1200 Mhz
654 01:27:23.185027 CPU clk: 1200 MHz
655 01:27:23.185466 Set clk81 to 166.6M
656 01:27:23.194874 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 01:27:23.195366 board id: 1
658 01:27:23.201302 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 01:27:23.212014 fw parse done
660 01:27:23.217959 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 01:27:23.260642 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 01:27:23.271534 PIEI prepare done
663 01:27:23.272046 fastboot data load
664 01:27:23.272466 fastboot data verify
665 01:27:23.277180 verify result: 266
666 01:27:23.282829 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 01:27:23.283304 LPDDR4 probe
668 01:27:23.283716 ddr clk to 1584MHz
669 01:27:23.290760 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 01:27:23.327786
671 01:27:23.328315 dmc_version 0001
672 01:27:23.334683 Check phy result
673 01:27:23.340616 INFO : End of CA training
674 01:27:23.341088 INFO : End of initialization
675 01:27:23.346181 INFO : Training has run successfully!
676 01:27:23.346649 Check phy result
677 01:27:23.351806 INFO : End of initialization
678 01:27:23.352308 INFO : End of read enable training
679 01:27:23.357382 INFO : End of fine write leveling
680 01:27:23.363000 INFO : End of Write leveling coarse delay
681 01:27:23.363468 INFO : Training has run successfully!
682 01:27:23.363882 Check phy result
683 01:27:23.368584 INFO : End of initialization
684 01:27:23.369052 INFO : End of read dq deskew training
685 01:27:23.374198 INFO : End of MPR read delay center optimization
686 01:27:23.379804 INFO : End of write delay center optimization
687 01:27:23.385381 INFO : End of read delay center optimization
688 01:27:23.385851 INFO : End of max read latency training
689 01:27:23.391024 INFO : Training has run successfully!
690 01:27:23.391496 1D training succeed
691 01:27:23.400191 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 01:27:23.447712 Check phy result
693 01:27:23.448224 INFO : End of initialization
694 01:27:23.471386 INFO : End of 2D read delay Voltage center optimization
695 01:27:23.489279 INFO : End of 2D read delay Voltage center optimization
696 01:27:23.541142 INFO : End of 2D write delay Voltage center optimization
697 01:27:23.590370 INFO : End of 2D write delay Voltage center optimization
698 01:27:23.595924 INFO : Training has run successfully!
699 01:27:23.596441
700 01:27:23.596867 channel==0
701 01:27:23.601516 RxClkDly_Margin_A0==78 ps 8
702 01:27:23.601991 TxDqDly_Margin_A0==98 ps 10
703 01:27:23.604862 RxClkDly_Margin_A1==88 ps 9
704 01:27:23.605336 TxDqDly_Margin_A1==88 ps 9
705 01:27:23.610420 TrainedVREFDQ_A0==75
706 01:27:23.610895 TrainedVREFDQ_A1==74
707 01:27:23.611313 VrefDac_Margin_A0==22
708 01:27:23.616022 DeviceVref_Margin_A0==39
709 01:27:23.616491 VrefDac_Margin_A1==22
710 01:27:23.621660 DeviceVref_Margin_A1==40
711 01:27:23.622130
712 01:27:23.622549
713 01:27:23.622954 channel==1
714 01:27:23.623351 RxClkDly_Margin_A0==88 ps 9
715 01:27:23.627246 TxDqDly_Margin_A0==88 ps 9
716 01:27:23.627717 RxClkDly_Margin_A1==78 ps 8
717 01:27:23.632848 TxDqDly_Margin_A1==88 ps 9
718 01:27:23.633330 TrainedVREFDQ_A0==75
719 01:27:23.633750 TrainedVREFDQ_A1==78
720 01:27:23.638428 VrefDac_Margin_A0==22
721 01:27:23.638897 DeviceVref_Margin_A0==38
722 01:27:23.639304 VrefDac_Margin_A1==22
723 01:27:23.644028 DeviceVref_Margin_A1==36
724 01:27:23.644497
725 01:27:23.649637 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 01:27:23.650102
727 01:27:23.677621 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
728 01:27:23.683249 2D training succeed
729 01:27:23.688906 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 01:27:23.689436 auto size-- 65535DDR cs0 size: 2048MB
731 01:27:23.694434 DDR cs1 size: 2048MB
732 01:27:23.694913 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 01:27:23.700049 cs0 DataBus test pass
734 01:27:23.700529 cs1 DataBus test pass
735 01:27:23.700949 cs0 AddrBus test pass
736 01:27:23.705644 cs1 AddrBus test pass
737 01:27:23.706113
738 01:27:23.706527 100bdlr_step_size ps== 464
739 01:27:23.706943 result report
740 01:27:23.711218 boot times 0Enable ddr reg access
741 01:27:23.718618 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 01:27:23.731449 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 01:27:24.387594 bl2z: ptr: 05129330, size: 00001e40
744 01:27:24.395072 0.0;M3 CHK:0;cm4_sp_mode 0
745 01:27:24.395592 MVN_1=0x00000000
746 01:27:24.396034 MVN_2=0x00000000
747 01:27:24.406547 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 01:27:24.407074 OPS=0x04
749 01:27:24.407473 ring efuse init
750 01:27:24.412176 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 01:27:24.412665 [0.017310 Inits done]
752 01:27:24.413070 secure task start!
753 01:27:24.418726 high task start!
754 01:27:24.419194 low task start!
755 01:27:24.419591 run into bl31
756 01:27:24.428245 NOTICE: BL31: v1.3(release):4fc40b1
757 01:27:24.436033 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 01:27:24.436507 NOTICE: BL31: G12A normal boot!
759 01:27:24.451440 NOTICE: BL31: BL33 decompress pass
760 01:27:24.456203 ERROR: Error initializing runtime service opteed_fast
761 01:27:25.252487
762 01:27:25.253080
763 01:27:25.258089 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 01:27:25.258578
765 01:27:25.261452 Model: Libre Computer AML-S905D3-CC Solitude
766 01:27:25.408448 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 01:27:25.423766 DRAM: 2 GiB (effective 3.8 GiB)
768 01:27:25.524802 Core: 406 devices, 33 uclasses, devicetree: separate
769 01:27:25.530706 WDT: Not starting watchdog@f0d0
770 01:27:25.555812 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 01:27:25.568070 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 01:27:25.573009 ** Bad device specification mmc 0 **
773 01:27:25.583137 Card did not respond to voltage select! : -110
774 01:27:25.590712 ** Bad device specification mmc 0 **
775 01:27:25.591243 Couldn't find partition mmc 0
776 01:27:25.599104 Card did not respond to voltage select! : -110
777 01:27:25.604532 ** Bad device specification mmc 0 **
778 01:27:25.604999 Couldn't find partition mmc 0
779 01:27:25.609572 Error: could not access storage.
780 01:27:25.906089 Net: eth0: ethernet@ff3f0000
781 01:27:25.906704 starting USB...
782 01:27:26.150695 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 01:27:26.151278 Starting the controller
784 01:27:26.157864 USB XHCI 1.10
785 01:27:27.711976 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 01:27:27.720286 scanning usb for storage devices... 0 Storage Device(s) found
788 01:27:27.771757 Hit any key to stop autoboot: 1
789 01:27:27.772911 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
790 01:27:27.773552 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
791 01:27:27.774031 Setting prompt string to ['=>']
792 01:27:27.774512 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
793 01:27:27.786327 0
794 01:27:27.787214 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 01:27:27.888438 => setenv autoload no
797 01:27:27.889351 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
798 01:27:27.894451 setenv autoload no
800 01:27:27.995916 => setenv initrd_high 0xffffffff
801 01:27:27.996812 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 01:27:28.001520 setenv initrd_high 0xffffffff
804 01:27:28.102952 => setenv fdt_high 0xffffffff
805 01:27:28.103832 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 01:27:28.108532 setenv fdt_high 0xffffffff
808 01:27:28.210018 => dhcp
809 01:27:28.211010 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 01:27:28.215308 dhcp
811 01:27:28.920753 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
812 01:27:28.921404 Speed: 1000, full duplex
813 01:27:28.921834 BOOTP broadcast 1
814 01:27:28.929601 DHCP client bound to address 192.168.6.21 (9 ms)
816 01:27:29.031534 => setenv serverip 192.168.6.2
817 01:27:29.032383 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
818 01:27:29.036510 setenv serverip 192.168.6.2
820 01:27:29.138101 => tftpboot 0x01080000 919765/tftp-deploy-ujb18u71/kernel/uImage
821 01:27:29.139609 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
822 01:27:29.145940 tftpboot 0x01080000 919765/tftp-deploy-ujb18u71/kernel/uImage
823 01:27:29.146475 Speed: 1000, full duplex
824 01:27:29.146879 Using ethernet@ff3f0000 device
825 01:27:29.151391 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
826 01:27:29.156854 Filename '919765/tftp-deploy-ujb18u71/kernel/uImage'.
827 01:27:29.161113 Load address: 0x1080000
828 01:27:33.425913 Loading: *################################################## 62.6 MiB
829 01:27:33.426512 14.7 MiB/s
830 01:27:33.426938 done
831 01:27:33.430131 Bytes transferred = 65665600 (3e9fa40 hex)
833 01:27:33.531680 => tftpboot 0x08000000 919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot
834 01:27:33.533162 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
835 01:27:33.539427 tftpboot 0x08000000 919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot
836 01:27:33.540022 Speed: 1000, full duplex
837 01:27:33.540439 Using ethernet@ff3f0000 device
838 01:27:33.544963 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
839 01:27:33.554595 Filename '919765/tftp-deploy-ujb18u71/ramdisk/ramdisk.cpio.gz.uboot'.
840 01:27:33.555153 Load address: 0x8000000
841 01:27:40.421158 Loading: *###################T ################# UDP wrong checksum 00000007 000048cb
842 01:27:41.049576 ############# UDP wrong checksum 00000007 0000441d
843 01:27:46.051500 T UDP wrong checksum 00000007 0000441d
844 01:27:52.856394 T UDP wrong checksum 000000ff 0000b553
845 01:27:52.867696 UDP wrong checksum 000000ff 00004946
846 01:27:56.053590 T UDP wrong checksum 00000007 0000441d
847 01:28:16.057518 T T T T UDP wrong checksum 00000007 0000441d
848 01:28:31.061306 T T
849 01:28:31.061945 Retry count exceeded; starting again
851 01:28:31.063377 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
854 01:28:31.065313 end: 2.4 uboot-commands (duration 00:01:22) [common]
856 01:28:31.066741 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
858 01:28:31.067754 end: 2 uboot-action (duration 00:01:22) [common]
860 01:28:31.069356 Cleaning after the job
861 01:28:31.069938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/ramdisk
862 01:28:31.071293 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/kernel
863 01:28:31.126896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/dtb
864 01:28:31.127760 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/nfsrootfs
865 01:28:31.286211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919765/tftp-deploy-ujb18u71/modules
866 01:28:31.317324 start: 4.1 power-off (timeout 00:00:30) [common]
867 01:28:31.318023 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
868 01:28:31.353326 >> OK - accepted request
869 01:28:31.355244 Returned 0 in 0 seconds
870 01:28:31.456032 end: 4.1 power-off (duration 00:00:00) [common]
872 01:28:31.456996 start: 4.2 read-feedback (timeout 00:10:00) [common]
873 01:28:31.457649 Listened to connection for namespace 'common' for up to 1s
874 01:28:32.458597 Finalising connection for namespace 'common'
875 01:28:32.459088 Disconnecting from shell: Finalise
876 01:28:32.459371 =>
877 01:28:32.560069 end: 4.2 read-feedback (duration 00:00:01) [common]
878 01:28:32.560476 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919765
879 01:28:34.430942 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919765
880 01:28:34.431661 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.