Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:44:20.784545 lava-dispatcher, installed at version: 2024.01
2 00:44:20.785389 start: 0 validate
3 00:44:20.785896 Start time: 2024-11-01 00:44:20.785864+00:00 (UTC)
4 00:44:20.786437 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:44:20.786982 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:44:20.827550 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:44:20.828353 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:44:20.856929 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:44:20.857783 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 00:44:20.892159 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:44:20.892855 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:44:20.922430 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:44:20.922925 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:44:20.960607 validate duration: 0.17
16 00:44:20.961477 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:44:20.961831 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:44:20.962148 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:44:20.962782 Not decompressing ramdisk as can be used compressed.
20 00:44:20.963245 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 00:44:20.963544 saving as /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/ramdisk/initrd.cpio.gz
22 00:44:20.963830 total size: 5628182 (5 MB)
23 00:44:21.001433 progress 0 % (0 MB)
24 00:44:21.005865 progress 5 % (0 MB)
25 00:44:21.010067 progress 10 % (0 MB)
26 00:44:21.013734 progress 15 % (0 MB)
27 00:44:21.017753 progress 20 % (1 MB)
28 00:44:21.021388 progress 25 % (1 MB)
29 00:44:21.025445 progress 30 % (1 MB)
30 00:44:21.029524 progress 35 % (1 MB)
31 00:44:21.033178 progress 40 % (2 MB)
32 00:44:21.037170 progress 45 % (2 MB)
33 00:44:21.040755 progress 50 % (2 MB)
34 00:44:21.044748 progress 55 % (2 MB)
35 00:44:21.048691 progress 60 % (3 MB)
36 00:44:21.052322 progress 65 % (3 MB)
37 00:44:21.056291 progress 70 % (3 MB)
38 00:44:21.059779 progress 75 % (4 MB)
39 00:44:21.063697 progress 80 % (4 MB)
40 00:44:21.067270 progress 85 % (4 MB)
41 00:44:21.071189 progress 90 % (4 MB)
42 00:44:21.074868 progress 95 % (5 MB)
43 00:44:21.078169 progress 100 % (5 MB)
44 00:44:21.078842 5 MB downloaded in 0.11 s (46.68 MB/s)
45 00:44:21.079390 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:44:21.080325 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:44:21.080621 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:44:21.080894 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:44:21.081371 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/kernel/Image
51 00:44:21.081620 saving as /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/kernel/Image
52 00:44:21.081828 total size: 45713920 (43 MB)
53 00:44:21.082039 No compression specified
54 00:44:21.167592 progress 0 % (0 MB)
55 00:44:21.196319 progress 5 % (2 MB)
56 00:44:21.224540 progress 10 % (4 MB)
57 00:44:21.252890 progress 15 % (6 MB)
58 00:44:21.281597 progress 20 % (8 MB)
59 00:44:21.309267 progress 25 % (10 MB)
60 00:44:21.337196 progress 30 % (13 MB)
61 00:44:21.364995 progress 35 % (15 MB)
62 00:44:21.393406 progress 40 % (17 MB)
63 00:44:21.421037 progress 45 % (19 MB)
64 00:44:21.448985 progress 50 % (21 MB)
65 00:44:21.476930 progress 55 % (24 MB)
66 00:44:21.505287 progress 60 % (26 MB)
67 00:44:21.533080 progress 65 % (28 MB)
68 00:44:21.560952 progress 70 % (30 MB)
69 00:44:21.591148 progress 75 % (32 MB)
70 00:44:21.620329 progress 80 % (34 MB)
71 00:44:21.647834 progress 85 % (37 MB)
72 00:44:21.675540 progress 90 % (39 MB)
73 00:44:21.708802 progress 95 % (41 MB)
74 00:44:21.740122 progress 100 % (43 MB)
75 00:44:21.740768 43 MB downloaded in 0.66 s (66.16 MB/s)
76 00:44:21.741283 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:44:21.742103 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:44:21.742378 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:44:21.742645 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:44:21.743125 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 00:44:21.744028 saving as /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 00:44:21.744272 total size: 53209 (0 MB)
84 00:44:21.744484 No compression specified
85 00:44:21.778086 progress 61 % (0 MB)
86 00:44:21.778964 progress 100 % (0 MB)
87 00:44:21.779523 0 MB downloaded in 0.04 s (1.44 MB/s)
88 00:44:21.780026 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:44:21.780855 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:44:21.781123 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:44:21.781384 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:44:21.781845 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 00:44:21.782091 saving as /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/nfsrootfs/full.rootfs.tar
95 00:44:21.782297 total size: 107552908 (102 MB)
96 00:44:21.782506 Using unxz to decompress xz
97 00:44:21.826303 progress 0 % (0 MB)
98 00:44:22.477607 progress 5 % (5 MB)
99 00:44:23.274318 progress 10 % (10 MB)
100 00:44:24.000701 progress 15 % (15 MB)
101 00:44:24.760617 progress 20 % (20 MB)
102 00:44:25.364137 progress 25 % (25 MB)
103 00:44:26.016144 progress 30 % (30 MB)
104 00:44:26.755678 progress 35 % (35 MB)
105 00:44:27.119201 progress 40 % (41 MB)
106 00:44:27.551218 progress 45 % (46 MB)
107 00:44:28.243704 progress 50 % (51 MB)
108 00:44:28.928458 progress 55 % (56 MB)
109 00:44:29.772265 progress 60 % (61 MB)
110 00:44:30.555660 progress 65 % (66 MB)
111 00:44:31.290162 progress 70 % (71 MB)
112 00:44:32.072312 progress 75 % (76 MB)
113 00:44:32.785688 progress 80 % (82 MB)
114 00:44:33.537480 progress 85 % (87 MB)
115 00:44:34.278742 progress 90 % (92 MB)
116 00:44:34.995874 progress 95 % (97 MB)
117 00:44:35.737464 progress 100 % (102 MB)
118 00:44:35.750474 102 MB downloaded in 13.97 s (7.34 MB/s)
119 00:44:35.751433 end: 1.4.1 http-download (duration 00:00:14) [common]
121 00:44:35.753302 end: 1.4 download-retry (duration 00:00:14) [common]
122 00:44:35.753896 start: 1.5 download-retry (timeout 00:09:45) [common]
123 00:44:35.754477 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 00:44:35.755353 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/modules.tar.xz
125 00:44:35.755864 saving as /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/modules/modules.tar
126 00:44:35.756364 total size: 11592552 (11 MB)
127 00:44:35.756842 Using unxz to decompress xz
128 00:44:35.801277 progress 0 % (0 MB)
129 00:44:35.871040 progress 5 % (0 MB)
130 00:44:35.947918 progress 10 % (1 MB)
131 00:44:36.030930 progress 15 % (1 MB)
132 00:44:36.108400 progress 20 % (2 MB)
133 00:44:36.188251 progress 25 % (2 MB)
134 00:44:36.272587 progress 30 % (3 MB)
135 00:44:36.355012 progress 35 % (3 MB)
136 00:44:36.445865 progress 40 % (4 MB)
137 00:44:36.541820 progress 45 % (5 MB)
138 00:44:36.627729 progress 50 % (5 MB)
139 00:44:36.720233 progress 55 % (6 MB)
140 00:44:36.810797 progress 60 % (6 MB)
141 00:44:36.899668 progress 65 % (7 MB)
142 00:44:36.989769 progress 70 % (7 MB)
143 00:44:37.079682 progress 75 % (8 MB)
144 00:44:37.170458 progress 80 % (8 MB)
145 00:44:37.253902 progress 85 % (9 MB)
146 00:44:37.333492 progress 90 % (9 MB)
147 00:44:37.442218 progress 95 % (10 MB)
148 00:44:37.543191 progress 100 % (11 MB)
149 00:44:37.559674 11 MB downloaded in 1.80 s (6.13 MB/s)
150 00:44:37.560685 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:44:37.562355 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:44:37.562912 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 00:44:37.563455 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 00:44:47.581604 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/919374/extract-nfsrootfs-u2d5ph0f
156 00:44:47.582214 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 00:44:47.582506 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 00:44:47.583111 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8
159 00:44:47.583564 makedir: /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin
160 00:44:47.583898 makedir: /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/tests
161 00:44:47.584259 makedir: /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/results
162 00:44:47.584596 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-add-keys
163 00:44:47.585132 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-add-sources
164 00:44:47.585634 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-background-process-start
165 00:44:47.586130 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-background-process-stop
166 00:44:47.586692 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-common-functions
167 00:44:47.587225 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-echo-ipv4
168 00:44:47.587717 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-install-packages
169 00:44:47.588262 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-installed-packages
170 00:44:47.588756 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-os-build
171 00:44:47.589265 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-probe-channel
172 00:44:47.589773 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-probe-ip
173 00:44:47.590286 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-target-ip
174 00:44:47.590766 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-target-mac
175 00:44:47.591247 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-target-storage
176 00:44:47.591743 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-case
177 00:44:47.592265 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-event
178 00:44:47.592751 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-feedback
179 00:44:47.593233 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-raise
180 00:44:47.593736 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-reference
181 00:44:47.594223 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-runner
182 00:44:47.594710 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-set
183 00:44:47.595190 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-test-shell
184 00:44:47.595680 Updating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-install-packages (oe)
185 00:44:47.596253 Updating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/bin/lava-installed-packages (oe)
186 00:44:47.596715 Creating /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/environment
187 00:44:47.597097 LAVA metadata
188 00:44:47.597359 - LAVA_JOB_ID=919374
189 00:44:47.597574 - LAVA_DISPATCHER_IP=192.168.6.2
190 00:44:47.597946 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 00:44:47.598929 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 00:44:47.599248 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 00:44:47.599456 skipped lava-vland-overlay
194 00:44:47.599698 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 00:44:47.599951 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 00:44:47.600201 skipped lava-multinode-overlay
197 00:44:47.600446 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 00:44:47.600698 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 00:44:47.600949 Loading test definitions
200 00:44:47.601228 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 00:44:47.601450 Using /lava-919374 at stage 0
202 00:44:47.602783 uuid=919374_1.6.2.4.1 testdef=None
203 00:44:47.603108 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 00:44:47.603373 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 00:44:47.605263 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 00:44:47.606060 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 00:44:47.608372 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 00:44:47.609196 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 00:44:47.611382 runner path: /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/0/tests/0_dmesg test_uuid 919374_1.6.2.4.1
212 00:44:47.611972 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 00:44:47.612764 Creating lava-test-runner.conf files
215 00:44:47.612966 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919374/lava-overlay-9x2kk5b8/lava-919374/0 for stage 0
216 00:44:47.613319 - 0_dmesg
217 00:44:47.613663 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 00:44:47.613937 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 00:44:47.636195 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 00:44:47.636622 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 00:44:47.636886 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 00:44:47.637155 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 00:44:47.637419 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 00:44:48.386886 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 00:44:48.387359 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 00:44:48.387606 extracting modules file /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919374/extract-nfsrootfs-u2d5ph0f
227 00:44:50.061344 extracting modules file /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919374/extract-overlay-ramdisk-iwvjxo50/ramdisk
228 00:44:51.651840 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 00:44:51.652347 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
230 00:44:51.652628 [common] Applying overlay to NFS
231 00:44:51.652842 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919374/compress-overlay-4637v3sf/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919374/extract-nfsrootfs-u2d5ph0f
232 00:44:51.682890 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 00:44:51.683315 start: 1.6.6 prepare-kernel (timeout 00:09:29) [common]
234 00:44:51.683589 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:29) [common]
235 00:44:51.683820 Converting downloaded kernel to a uImage
236 00:44:51.684154 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/kernel/Image /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/kernel/uImage
237 00:44:52.150978 output: Image Name:
238 00:44:52.151440 output: Created: Fri Nov 1 00:44:51 2024
239 00:44:52.151693 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 00:44:52.151915 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 00:44:52.152164 output: Load Address: 01080000
242 00:44:52.152379 output: Entry Point: 01080000
243 00:44:52.152584 output:
244 00:44:52.152933 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 00:44:52.153227 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 00:44:52.153520 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 00:44:52.153793 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 00:44:52.154068 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 00:44:52.154351 Building ramdisk /var/lib/lava/dispatcher/tmp/919374/extract-overlay-ramdisk-iwvjxo50/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919374/extract-overlay-ramdisk-iwvjxo50/ramdisk
250 00:44:54.427924 >> 166820 blocks
251 00:45:02.155301 Adding RAMdisk u-boot header.
252 00:45:02.155722 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919374/extract-overlay-ramdisk-iwvjxo50/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919374/extract-overlay-ramdisk-iwvjxo50/ramdisk.cpio.gz.uboot
253 00:45:02.412262 output: Image Name:
254 00:45:02.412923 output: Created: Fri Nov 1 00:45:02 2024
255 00:45:02.413390 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 00:45:02.413842 output: Data Size: 23433419 Bytes = 22884.20 KiB = 22.35 MiB
257 00:45:02.414283 output: Load Address: 00000000
258 00:45:02.414723 output: Entry Point: 00000000
259 00:45:02.415159 output:
260 00:45:02.416213 rename /var/lib/lava/dispatcher/tmp/919374/extract-overlay-ramdisk-iwvjxo50/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot
261 00:45:02.416998 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 00:45:02.417598 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 00:45:02.418178 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 00:45:02.418673 No LXC device requested
265 00:45:02.419219 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 00:45:02.419780 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 00:45:02.420367 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 00:45:02.420820 Checking files for TFTP limit of 4294967296 bytes.
269 00:45:02.423719 end: 1 tftp-deploy (duration 00:00:41) [common]
270 00:45:02.424378 start: 2 uboot-action (timeout 00:05:00) [common]
271 00:45:02.424961 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 00:45:02.425510 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 00:45:02.426062 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 00:45:02.426635 Using kernel file from prepare-kernel: 919374/tftp-deploy-tf8zq5ks/kernel/uImage
275 00:45:02.427323 substitutions:
276 00:45:02.427772 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 00:45:02.428254 - {DTB_ADDR}: 0x01070000
278 00:45:02.428700 - {DTB}: 919374/tftp-deploy-tf8zq5ks/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 00:45:02.429139 - {INITRD}: 919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot
280 00:45:02.429580 - {KERNEL_ADDR}: 0x01080000
281 00:45:02.430011 - {KERNEL}: 919374/tftp-deploy-tf8zq5ks/kernel/uImage
282 00:45:02.430446 - {LAVA_MAC}: None
283 00:45:02.430920 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/919374/extract-nfsrootfs-u2d5ph0f
284 00:45:02.431362 - {NFS_SERVER_IP}: 192.168.6.2
285 00:45:02.431794 - {PRESEED_CONFIG}: None
286 00:45:02.432251 - {PRESEED_LOCAL}: None
287 00:45:02.432683 - {RAMDISK_ADDR}: 0x08000000
288 00:45:02.433109 - {RAMDISK}: 919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot
289 00:45:02.433541 - {ROOT_PART}: None
290 00:45:02.433972 - {ROOT}: None
291 00:45:02.434400 - {SERVER_IP}: 192.168.6.2
292 00:45:02.434826 - {TEE_ADDR}: 0x83000000
293 00:45:02.435253 - {TEE}: None
294 00:45:02.435685 Parsed boot commands:
295 00:45:02.436127 - setenv autoload no
296 00:45:02.436558 - setenv initrd_high 0xffffffff
297 00:45:02.436984 - setenv fdt_high 0xffffffff
298 00:45:02.437408 - dhcp
299 00:45:02.437831 - setenv serverip 192.168.6.2
300 00:45:02.438257 - tftpboot 0x01080000 919374/tftp-deploy-tf8zq5ks/kernel/uImage
301 00:45:02.438686 - tftpboot 0x08000000 919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot
302 00:45:02.439115 - tftpboot 0x01070000 919374/tftp-deploy-tf8zq5ks/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 00:45:02.439544 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919374/extract-nfsrootfs-u2d5ph0f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 00:45:02.440007 - bootm 0x01080000 0x08000000 0x01070000
305 00:45:02.440569 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 00:45:02.442219 start: 2.3 connect-device (timeout 00:05:00) [common]
308 00:45:02.442679 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 00:45:02.462518 Setting prompt string to ['lava-test: # ']
310 00:45:02.464176 end: 2.3 connect-device (duration 00:00:00) [common]
311 00:45:02.464845 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 00:45:02.465449 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 00:45:02.466019 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 00:45:02.467247 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 00:45:02.501679 >> OK - accepted request
316 00:45:02.503723 Returned 0 in 0 seconds
317 00:45:02.604685 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 00:45:02.605673 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 00:45:02.605974 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 00:45:02.606249 Setting prompt string to ['Hit any key to stop autoboot']
322 00:45:02.606492 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 00:45:02.607392 Trying 192.168.56.21...
324 00:45:02.607661 Connected to conserv1.
325 00:45:02.607874 Escape character is '^]'.
326 00:45:02.608170
327 00:45:02.608396 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 00:45:02.608616
329 00:45:10.120854 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 00:45:10.121531 bl2_stage_init 0x01
331 00:45:10.121989 bl2_stage_init 0x81
332 00:45:10.126535 hw id: 0x0000 - pwm id 0x01
333 00:45:10.127034 bl2_stage_init 0xc1
334 00:45:10.130651 bl2_stage_init 0x02
335 00:45:10.131122
336 00:45:10.131573 L0:00000000
337 00:45:10.132059 L1:00000703
338 00:45:10.132497 L2:00008067
339 00:45:10.140246 L3:15000000
340 00:45:10.140729 S1:00000000
341 00:45:10.141168 B2:20282000
342 00:45:10.141604 B1:a0f83180
343 00:45:10.142034
344 00:45:10.142777 TE: 69823
345 00:45:10.143241
346 00:45:10.147436 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 00:45:10.147929
348 00:45:10.148406 Board ID = 1
349 00:45:10.148838 Set cpu clk to 24M
350 00:45:10.150995 Set clk81 to 24M
351 00:45:10.151476 Use GP1_pll as DSU clk.
352 00:45:10.156544 DSU clk: 1200 Mhz
353 00:45:10.157028 CPU clk: 1200 MHz
354 00:45:10.157462 Set clk81 to 166.6M
355 00:45:10.162099 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 00:45:10.167701 board id: 1
357 00:45:10.171767 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 00:45:10.183517 fw parse done
359 00:45:10.189418 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 00:45:10.232227 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 00:45:10.242992 PIEI prepare done
362 00:45:10.243455 fastboot data load
363 00:45:10.243900 fastboot data verify
364 00:45:10.248604 verify result: 266
365 00:45:10.254159 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 00:45:10.254621 LPDDR4 probe
367 00:45:10.255058 ddr clk to 1584MHz
368 00:45:10.262182 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 00:45:10.299455
370 00:45:10.299924 dmc_version 0001
371 00:45:10.306129 Check phy result
372 00:45:10.312019 INFO : End of CA training
373 00:45:10.312483 INFO : End of initialization
374 00:45:10.317621 INFO : Training has run successfully!
375 00:45:10.318081 Check phy result
376 00:45:10.323240 INFO : End of initialization
377 00:45:10.323696 INFO : End of read enable training
378 00:45:10.326679 INFO : End of fine write leveling
379 00:45:10.332211 INFO : End of Write leveling coarse delay
380 00:45:10.337728 INFO : Training has run successfully!
381 00:45:10.338184 Check phy result
382 00:45:10.338619 INFO : End of initialization
383 00:45:10.343276 INFO : End of read dq deskew training
384 00:45:10.349018 INFO : End of MPR read delay center optimization
385 00:45:10.349489 INFO : End of write delay center optimization
386 00:45:10.354566 INFO : End of read delay center optimization
387 00:45:10.360186 INFO : End of max read latency training
388 00:45:10.360642 INFO : Training has run successfully!
389 00:45:10.365722 1D training succeed
390 00:45:10.371636 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 00:45:10.419173 Check phy result
392 00:45:10.419642 INFO : End of initialization
393 00:45:10.441537 INFO : End of 2D read delay Voltage center optimization
394 00:45:10.460741 INFO : End of 2D read delay Voltage center optimization
395 00:45:10.512698 INFO : End of 2D write delay Voltage center optimization
396 00:45:10.561851 INFO : End of 2D write delay Voltage center optimization
397 00:45:10.567372 INFO : Training has run successfully!
398 00:45:10.567832
399 00:45:10.568312 channel==0
400 00:45:10.572878 RxClkDly_Margin_A0==88 ps 9
401 00:45:10.573354 TxDqDly_Margin_A0==98 ps 10
402 00:45:10.576217 RxClkDly_Margin_A1==88 ps 9
403 00:45:10.576676 TxDqDly_Margin_A1==98 ps 10
404 00:45:10.581743 TrainedVREFDQ_A0==74
405 00:45:10.582207 TrainedVREFDQ_A1==74
406 00:45:10.587359 VrefDac_Margin_A0==23
407 00:45:10.587812 DeviceVref_Margin_A0==40
408 00:45:10.588285 VrefDac_Margin_A1==23
409 00:45:10.592909 DeviceVref_Margin_A1==40
410 00:45:10.593365
411 00:45:10.593803
412 00:45:10.594238 channel==1
413 00:45:10.594668 RxClkDly_Margin_A0==78 ps 8
414 00:45:10.596402 TxDqDly_Margin_A0==98 ps 10
415 00:45:10.602614 RxClkDly_Margin_A1==78 ps 8
416 00:45:10.603075 TxDqDly_Margin_A1==88 ps 9
417 00:45:10.605718 TrainedVREFDQ_A0==78
418 00:45:10.606176 TrainedVREFDQ_A1==78
419 00:45:10.606611 VrefDac_Margin_A0==22
420 00:45:10.611431 DeviceVref_Margin_A0==36
421 00:45:10.611888 VrefDac_Margin_A1==22
422 00:45:10.616884 DeviceVref_Margin_A1==36
423 00:45:10.617346
424 00:45:10.622624 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 00:45:10.623084
426 00:45:10.650693 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
427 00:45:10.651236 2D training succeed
428 00:45:10.656199 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 00:45:10.661625 auto size-- 65535DDR cs0 size: 2048MB
430 00:45:10.662086 DDR cs1 size: 2048MB
431 00:45:10.667274 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 00:45:10.667730 cs0 DataBus test pass
433 00:45:10.672818 cs1 DataBus test pass
434 00:45:10.673277 cs0 AddrBus test pass
435 00:45:10.673707 cs1 AddrBus test pass
436 00:45:10.674133
437 00:45:10.678512 100bdlr_step_size ps== 478
438 00:45:10.678978 result report
439 00:45:10.684027 boot times 0Enable ddr reg access
440 00:45:10.690071 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 00:45:10.703894 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 00:45:11.359460 bl2z: ptr: 05129330, size: 00001e40
443 00:45:11.364802 0.0;M3 CHK:0;cm4_sp_mode 0
444 00:45:11.365290 MVN_1=0x00000000
445 00:45:11.365726 MVN_2=0x00000000
446 00:45:11.370583 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 00:45:11.371048 OPS=0x04
448 00:45:11.376344 ring efuse init
449 00:45:11.381929 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 00:45:11.382396 [0.017310 Inits done]
451 00:45:11.382828 secure task start!
452 00:45:11.388132 high task start!
453 00:45:11.388603 low task start!
454 00:45:11.389037 run into bl31
455 00:45:11.396719 NOTICE: BL31: v1.3(release):4fc40b1
456 00:45:11.404540 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 00:45:11.405018 NOTICE: BL31: G12A normal boot!
458 00:45:11.420079 NOTICE: BL31: BL33 decompress pass
459 00:45:11.425731 ERROR: Error initializing runtime service opteed_fast
460 00:45:12.672757 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 00:45:12.673391 bl2_stage_init 0x01
462 00:45:12.673860 bl2_stage_init 0x81
463 00:45:12.678250 hw id: 0x0000 - pwm id 0x01
464 00:45:12.678753 bl2_stage_init 0xc1
465 00:45:12.683848 bl2_stage_init 0x02
466 00:45:12.684411
467 00:45:12.684856 L0:00000000
468 00:45:12.685283 L1:00000703
469 00:45:12.685713 L2:00008067
470 00:45:12.686137 L3:15000000
471 00:45:12.689497 S1:00000000
472 00:45:12.689953 B2:20282000
473 00:45:12.690377 B1:a0f83180
474 00:45:12.690800
475 00:45:12.691227 TE: 70313
476 00:45:12.691654
477 00:45:12.695030 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 00:45:12.695485
479 00:45:12.700741 Board ID = 1
480 00:45:12.701187 Set cpu clk to 24M
481 00:45:12.701614 Set clk81 to 24M
482 00:45:12.706247 Use GP1_pll as DSU clk.
483 00:45:12.706701 DSU clk: 1200 Mhz
484 00:45:12.707126 CPU clk: 1200 MHz
485 00:45:12.711837 Set clk81 to 166.6M
486 00:45:12.717521 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 00:45:12.717974 board id: 1
488 00:45:12.724637 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 00:45:12.735307 fw parse done
490 00:45:12.741272 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 00:45:12.783927 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 00:45:12.794920 PIEI prepare done
493 00:45:12.795370 fastboot data load
494 00:45:12.795797 fastboot data verify
495 00:45:12.800501 verify result: 266
496 00:45:12.806052 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 00:45:12.806504 LPDDR4 probe
498 00:45:12.806931 ddr clk to 1584MHz
499 00:45:14.168864 Load ddrfw from SPI, src: 0x00018000, des: 0xfff SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 00:45:14.169522 bl2_stage_init 0x01
501 00:45:14.169984 bl2_stage_init 0x81
502 00:45:14.174417 hw id: 0x0000 - pwm id 0x01
503 00:45:14.174898 bl2_stage_init 0xc1
504 00:45:14.179444 bl2_stage_init 0x02
505 00:45:14.179912
506 00:45:14.180417 L0:00000000
507 00:45:14.180860 L1:00000703
508 00:45:14.181297 L2:00008067
509 00:45:14.185037 L3:15000000
510 00:45:14.185508 S1:00000000
511 00:45:14.185954 B2:20282000
512 00:45:14.186396 B1:a0f83180
513 00:45:14.186836
514 00:45:14.187272 TE: 68088
515 00:45:14.187712
516 00:45:14.196191 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 00:45:14.196675
518 00:45:14.197127 Board ID = 1
519 00:45:14.197567 Set cpu clk to 24M
520 00:45:14.198002 Set clk81 to 24M
521 00:45:14.201838 Use GP1_pll as DSU clk.
522 00:45:14.202302 DSU clk: 1200 Mhz
523 00:45:14.202746 CPU clk: 1200 MHz
524 00:45:14.207409 Set clk81 to 166.6M
525 00:45:14.213028 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 00:45:14.213502 board id: 1
527 00:45:14.220708 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 00:45:14.231767 fw parse done
529 00:45:14.237658 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 00:45:14.280237 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 00:45:14.292092 PIEI prepare done
532 00:45:14.292567 fastboot data load
533 00:45:14.293014 fastboot data verify
534 00:45:14.297498 verify result: 266
535 00:45:14.303088 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 00:45:14.303557 LPDDR4 probe
537 00:45:14.304028 ddr clk to 1584MHz
538 00:45:14.311120 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 00:45:14.348797
540 00:45:14.349272 dmc_version 0001
541 00:45:14.355880 Check phy result
542 00:45:14.361848 INFO : End of CA training
543 00:45:14.362313 INFO : End of initialization
544 00:45:14.367433 INFO : Training has run successfully!
545 00:45:14.367905 Check phy result
546 00:45:14.373066 INFO : End of initialization
547 00:45:14.373530 INFO : End of read enable training
548 00:45:14.378601 INFO : End of fine write leveling
549 00:45:14.384241 INFO : End of Write leveling coarse delay
550 00:45:14.384709 INFO : Training has run successfully!
551 00:45:14.385155 Check phy result
552 00:45:14.389862 INFO : End of initialization
553 00:45:14.390333 INFO : End of read dq deskew training
554 00:45:14.395444 INFO : End of MPR read delay center optimization
555 00:45:14.401083 INFO : End of write delay center optimization
556 00:45:14.406613 INFO : End of read delay center optimization
557 00:45:14.407077 INFO : End of max read latency training
558 00:45:14.412222 INFO : Training has run successfully!
559 00:45:14.412684 1D training succeed
560 00:45:14.421406 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 00:45:14.469663 Check phy result
562 00:45:14.470127 INFO : End of initialization
563 00:45:14.497154 INFO : End of 2D read delay Voltage center optimization
564 00:45:14.521257 INFO : End of 2D read delay Voltage center optimization
565 00:45:14.577907 INFO : End of 2D write delay Voltage center optimization
566 00:45:14.631942 INFO : End of 2D write delay Voltage center optimization
567 00:45:14.637530 INFO : Training has run successfully!
568 00:45:14.637998
569 00:45:14.638462 channel==0
570 00:45:14.643141 RxClkDly_Margin_A0==78 ps 8
571 00:45:14.643605 TxDqDly_Margin_A0==98 ps 10
572 00:45:14.648738 RxClkDly_Margin_A1==88 ps 9
573 00:45:14.649203 TxDqDly_Margin_A1==98 ps 10
574 00:45:14.649650 TrainedVREFDQ_A0==74
575 00:45:14.654330 TrainedVREFDQ_A1==75
576 00:45:14.654802 VrefDac_Margin_A0==23
577 00:45:14.655242 DeviceVref_Margin_A0==40
578 00:45:14.659941 VrefDac_Margin_A1==22
579 00:45:14.660432 DeviceVref_Margin_A1==39
580 00:45:14.660874
581 00:45:14.661312
582 00:45:14.665551 channel==1
583 00:45:14.666013 RxClkDly_Margin_A0==78 ps 8
584 00:45:14.666454 TxDqDly_Margin_A0==88 ps 9
585 00:45:14.671142 RxClkDly_Margin_A1==78 ps 8
586 00:45:14.671606 TxDqDly_Margin_A1==88 ps 9
587 00:45:14.676740 TrainedVREFDQ_A0==75
588 00:45:14.677212 TrainedVREFDQ_A1==75
589 00:45:14.677655 VrefDac_Margin_A0==22
590 00:45:14.682318 DeviceVref_Margin_A0==39
591 00:45:14.682783 VrefDac_Margin_A1==20
592 00:45:14.687913 DeviceVref_Margin_A1==39
593 00:45:14.688407
594 00:45:14.688853 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 00:45:14.689292
596 00:45:14.721543 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000060
597 00:45:14.722045 2D training succeed
598 00:45:14.727143 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 00:45:14.732751 auto size-- 65535DDR cs0 size: 2048MB
600 00:45:14.733219 DDR cs1 size: 2048MB
601 00:45:14.738317 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 00:45:14.738780 cs0 DataBus test pass
603 00:45:14.743930 cs1 DataBus test pass
604 00:45:14.744432 cs0 AddrBus test pass
605 00:45:14.744880 cs1 AddrBus test pass
606 00:45:14.745315
607 00:45:14.749527 100bdlr_step_size ps== 471
608 00:45:14.750004 result report
609 00:45:14.755156 boot times 0Enable ddr reg access
610 00:45:14.760308 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 00:45:14.774181 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 00:45:15.433571 bl2z: ptr: 05129330, size: 00001e40
613 00:45:15.442772 0.0;M3 CHK:0;cm4_sp_mode 0
614 00:45:15.443287 MVN_1=0x00000000
615 00:45:15.443738 MVN_2=0x00000000
616 00:45:15.454251 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 00:45:15.454734 OPS=0x04
618 00:45:15.455181 ring efuse init
619 00:45:15.459856 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 00:45:15.460366 [0.017354 Inits done]
621 00:45:15.460811 secure task start!
622 00:45:15.467788 high task start!
623 00:45:15.468288 low task start!
624 00:45:15.468730 run into bl31
625 00:45:15.476425 NOTICE: BL31: v1.3(release):4fc40b1
626 00:45:15.484289 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 00:45:15.484766 NOTICE: BL31: G12A normal boot!
628 00:45:15.499853 NOTICE: BL31: BL33 decompress pass
629 00:45:15.505579 ERROR: Error initializing runtime service opteed_fast
630 00:45:16.721677 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 00:45:16.722289 bl2_stage_init 0x01
632 00:45:16.722751 bl2_stage_init 0x81
633 00:45:16.727264 hw id: 0x0000 - pwm id 0x01
634 00:45:16.727743 bl2_stage_init 0xc1
635 00:45:16.732745 bl2_stage_init 0x02
636 00:45:16.733221
637 00:45:16.733674 L0:00000000
638 00:45:16.734114 L1:00000703
639 00:45:16.734550 L2:00008067
640 00:45:16.734983 L3:15000000
641 00:45:16.738512 S1:00000000
642 00:45:16.738976 B2:20282000
643 00:45:16.739421 B1:a0f83180
644 00:45:16.739858
645 00:45:16.740339 TE: 70525
646 00:45:16.740782
647 00:45:16.743971 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 00:45:16.744477
649 00:45:16.749600 Board ID = 1
650 00:45:16.750069 Set cpu clk to 24M
651 00:45:16.750513 Set clk81 to 24M
652 00:45:16.755190 Use GP1_pll as DSU clk.
653 00:45:16.755661 DSU clk: 1200 Mhz
654 00:45:16.756140 CPU clk: 1200 MHz
655 00:45:16.760772 Set clk81 to 166.6M
656 00:45:16.766451 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 00:45:16.766921 board id: 1
658 00:45:16.773560 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 00:45:16.784197 fw parse done
660 00:45:16.790207 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 00:45:16.832082 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 00:45:16.843736 PIEI prepare done
663 00:45:16.844253 fastboot data load
664 00:45:16.844703 fastboot data verify
665 00:45:16.849353 verify result: 266
666 00:45:16.855039 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 00:45:16.855513 LPDDR4 probe
668 00:45:16.855955 ddr clk to 1584MHz
669 00:45:16.861988 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 00:45:16.900184
671 00:45:16.900663 dmc_version 0001
672 00:45:16.906837 Check phy result
673 00:45:16.912721 INFO : End of CA training
674 00:45:16.913185 INFO : End of initialization
675 00:45:16.918435 INFO : Training has run successfully!
676 00:45:16.918904 Check phy result
677 00:45:16.923962 INFO : End of initialization
678 00:45:16.924464 INFO : End of read enable training
679 00:45:16.927283 INFO : End of fine write leveling
680 00:45:16.932763 INFO : End of Write leveling coarse delay
681 00:45:16.938506 INFO : Training has run successfully!
682 00:45:16.938969 Check phy result
683 00:45:16.939413 INFO : End of initialization
684 00:45:16.943946 INFO : End of read dq deskew training
685 00:45:16.949522 INFO : End of MPR read delay center optimization
686 00:45:16.949994 INFO : End of write delay center optimization
687 00:45:16.955161 INFO : End of read delay center optimization
688 00:45:16.960717 INFO : End of max read latency training
689 00:45:16.961188 INFO : Training has run successfully!
690 00:45:16.966411 1D training succeed
691 00:45:16.972293 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 00:45:17.019822 Check phy result
693 00:45:17.020364 INFO : End of initialization
694 00:45:17.042259 INFO : End of 2D read delay Voltage center optimization
695 00:45:17.061386 INFO : End of 2D read delay Voltage center optimization
696 00:45:17.113335 INFO : End of 2D write delay Voltage center optimization
697 00:45:17.162453 INFO : End of 2D write delay Voltage center optimization
698 00:45:17.168044 INFO : Training has run successfully!
699 00:45:17.168523
700 00:45:17.168973 channel==0
701 00:45:17.173626 RxClkDly_Margin_A0==78 ps 8
702 00:45:17.174093 TxDqDly_Margin_A0==98 ps 10
703 00:45:17.179202 RxClkDly_Margin_A1==88 ps 9
704 00:45:17.179671 TxDqDly_Margin_A1==98 ps 10
705 00:45:17.180158 TrainedVREFDQ_A0==74
706 00:45:17.184849 TrainedVREFDQ_A1==74
707 00:45:17.185325 VrefDac_Margin_A0==23
708 00:45:17.185767 DeviceVref_Margin_A0==40
709 00:45:17.190431 VrefDac_Margin_A1==23
710 00:45:17.190900 DeviceVref_Margin_A1==40
711 00:45:17.191344
712 00:45:17.191789
713 00:45:17.196039 channel==1
714 00:45:17.196510 RxClkDly_Margin_A0==78 ps 8
715 00:45:17.196965 TxDqDly_Margin_A0==98 ps 10
716 00:45:17.201621 RxClkDly_Margin_A1==88 ps 9
717 00:45:17.202087 TxDqDly_Margin_A1==88 ps 9
718 00:45:17.207208 TrainedVREFDQ_A0==78
719 00:45:17.207678 TrainedVREFDQ_A1==75
720 00:45:17.208166 VrefDac_Margin_A0==22
721 00:45:17.212821 DeviceVref_Margin_A0==36
722 00:45:17.213290 VrefDac_Margin_A1==21
723 00:45:17.218453 DeviceVref_Margin_A1==39
724 00:45:17.218916
725 00:45:17.219357 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 00:45:17.219793
727 00:45:17.252012 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000060
728 00:45:17.252524 2D training succeed
729 00:45:17.257605 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 00:45:17.263207 auto size-- 65535DDR cs0 size: 2048MB
731 00:45:17.263682 DDR cs1 size: 2048MB
732 00:45:17.268796 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 00:45:17.269263 cs0 DataBus test pass
734 00:45:17.274459 cs1 DataBus test pass
735 00:45:17.274926 cs0 AddrBus test pass
736 00:45:17.275375 cs1 AddrBus test pass
737 00:45:17.275815
738 00:45:17.280047 100bdlr_step_size ps== 478
739 00:45:17.280532 result report
740 00:45:17.285609 boot times 0Enable ddr reg access
741 00:45:17.290858 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 00:45:17.304711 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 00:45:17.959223 bl2z: ptr: 05129330, size: 00001e40
744 00:45:17.967332 0.0;M3 CHK:0;cm4_sp_mode 0
745 00:45:17.967900 MVN_1=0x00000000
746 00:45:17.968401 MVN_2=0x00000000
747 00:45:17.978707 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 00:45:17.979023 OPS=0x04
749 00:45:17.979253 ring efuse init
750 00:45:17.984435 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 00:45:17.985233 [0.017310 Inits done]
752 00:45:17.985898 secure task start!
753 00:45:17.991367 high task start!
754 00:45:17.992144 low task start!
755 00:45:17.992806 run into bl31
756 00:45:18.000951 NOTICE: BL31: v1.3(release):4fc40b1
757 00:45:18.008332 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 00:45:18.009100 NOTICE: BL31: G12A normal boot!
759 00:45:18.024388 NOTICE: BL31: BL33 decompress pass
760 00:45:18.029379 ERROR: Error initializing runtime service opteed_fast
761 00:45:18.824066
762 00:45:18.824754
763 00:45:18.829485 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 00:45:18.830052
765 00:45:18.832653 Model: Libre Computer AML-S905D3-CC Solitude
766 00:45:18.979589 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 00:45:18.994535 DRAM: 2 GiB (effective 3.8 GiB)
768 00:45:19.096090 Core: 406 devices, 33 uclasses, devicetree: separate
769 00:45:19.100953 WDT: Not starting watchdog@f0d0
770 00:45:19.127006 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 00:45:19.139247 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 00:45:19.143762 ** Bad device specification mmc 0 **
773 00:45:19.154310 Card did not respond to voltage select! : -110
774 00:45:19.161066 ** Bad device specification mmc 0 **
775 00:45:19.161342 Couldn't find partition mmc 0
776 00:45:19.170334 Card did not respond to voltage select! : -110
777 00:45:19.175811 ** Bad device specification mmc 0 **
778 00:45:19.176105 Couldn't find partition mmc 0
779 00:45:19.180255 Error: could not access storage.
780 00:45:19.476382 Net: eth0: ethernet@ff3f0000
781 00:45:19.476765 starting USB...
782 00:45:19.721989 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 00:45:19.722365 Starting the controller
784 00:45:19.728484 USB XHCI 1.10
785 00:45:21.282880 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 00:45:21.290400 scanning usb for storage devices... 0 Storage Device(s) found
788 00:45:21.341992 Hit any key to stop autoboot: 1
789 00:45:21.342934 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
790 00:45:21.343599 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
791 00:45:21.344171 Setting prompt string to ['=>']
792 00:45:21.344716 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
793 00:45:21.356171 0
794 00:45:21.357255 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 00:45:21.458562 => setenv autoload no
797 00:45:21.459048 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
798 00:45:21.462778 setenv autoload no
800 00:45:21.563771 => setenv initrd_high 0xffffffff
801 00:45:21.564422 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 00:45:21.568695 setenv initrd_high 0xffffffff
804 00:45:21.670228 => setenv fdt_high 0xffffffff
805 00:45:21.670973 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 00:45:21.675415 setenv fdt_high 0xffffffff
808 00:45:21.776994 => dhcp
809 00:45:21.777734 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 00:45:21.780810 dhcp
811 00:45:22.687660 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
812 00:45:22.688280 Speed: 1000, full duplex
813 00:45:22.688743 BOOTP broadcast 1
814 00:45:22.720974 DHCP client bound to address 192.168.6.21 (33 ms)
816 00:45:22.822438 => setenv serverip 192.168.6.2
817 00:45:22.823112 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
818 00:45:22.827050 setenv serverip 192.168.6.2
820 00:45:22.928245 => tftpboot 0x01080000 919374/tftp-deploy-tf8zq5ks/kernel/uImage
821 00:45:22.928851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
822 00:45:22.935574 tftpboot 0x01080000 919374/tftp-deploy-tf8zq5ks/kernel/uImage
823 00:45:22.936249 Speed: 1000, full duplex
824 00:45:22.936929 Using ethernet@ff3f0000 device
825 00:45:22.940983 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
826 00:45:22.946590 Filename '919374/tftp-deploy-tf8zq5ks/kernel/uImage'.
827 00:45:22.950276 Load address: 0x1080000
828 00:45:25.834788 Loading: *################################################## 43.6 MiB
829 00:45:25.835442 15.1 MiB/s
830 00:45:25.835894 done
831 00:45:25.839286 Bytes transferred = 45713984 (2b98a40 hex)
833 00:45:25.940999 => tftpboot 0x08000000 919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot
834 00:45:25.941740 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
835 00:45:25.948691 tftpboot 0x08000000 919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot
836 00:45:25.949220 Speed: 1000, full duplex
837 00:45:25.949663 Using ethernet@ff3f0000 device
838 00:45:25.954200 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
839 00:45:25.963826 Filename '919374/tftp-deploy-tf8zq5ks/ramdisk/ramdisk.cpio.gz.uboot'.
840 00:45:25.964157 Load address: 0x8000000
841 00:45:27.383933 Loading: *################################################# UDP wrong checksum 00000005 000036d4
842 00:45:31.971463 UDP wrong checksum 000000ff 00005538
843 00:45:31.991467 UDP wrong checksum 000000ff 0000ec2a
844 00:45:32.385261 T UDP wrong checksum 00000005 000036d4
845 00:45:42.387445 T T UDP wrong checksum 00000005 000036d4
846 00:45:49.978352 T UDP wrong checksum 000000ff 00003db8
847 00:45:49.992980 UDP wrong checksum 000000ff 0000d3aa
848 00:46:02.391129 T T T UDP wrong checksum 00000005 000036d4
849 00:46:15.956048 T T UDP wrong checksum 000000ff 00005bc3
850 00:46:15.994057 UDP wrong checksum 000000ff 0000ebb5
851 00:46:22.396356 T
852 00:46:22.397033 Retry count exceeded; starting again
854 00:46:22.398576 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
857 00:46:22.400632 end: 2.4 uboot-commands (duration 00:01:20) [common]
859 00:46:22.402178 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
861 00:46:22.403304 end: 2 uboot-action (duration 00:01:20) [common]
863 00:46:22.405089 Cleaning after the job
864 00:46:22.405702 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/ramdisk
865 00:46:22.407106 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/kernel
866 00:46:22.456088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/dtb
867 00:46:22.457409 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/nfsrootfs
868 00:46:22.616246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919374/tftp-deploy-tf8zq5ks/modules
869 00:46:22.637668 start: 4.1 power-off (timeout 00:00:30) [common]
870 00:46:22.638347 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
871 00:46:22.669482 >> OK - accepted request
872 00:46:22.671500 Returned 0 in 0 seconds
873 00:46:22.772365 end: 4.1 power-off (duration 00:00:00) [common]
875 00:46:22.773392 start: 4.2 read-feedback (timeout 00:10:00) [common]
876 00:46:22.774057 Listened to connection for namespace 'common' for up to 1s
877 00:46:23.774438 Finalising connection for namespace 'common'
878 00:46:23.774916 Disconnecting from shell: Finalise
879 00:46:23.775203 =>
880 00:46:23.875857 end: 4.2 read-feedback (duration 00:00:01) [common]
881 00:46:23.876368 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919374
882 00:46:25.929432 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919374
883 00:46:25.930051 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.