Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:45:42.949899 lava-dispatcher, installed at version: 2024.01
2 01:45:42.950646 start: 0 validate
3 01:45:42.951102 Start time: 2024-11-01 01:45:42.951071+00:00 (UTC)
4 01:45:42.951628 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:45:42.952185 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:45:42.994651 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:45:42.995196 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:45:43.025272 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:45:43.026210 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:45:43.059156 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:45:43.059670 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:45:43.098681 validate duration: 0.15
14 01:45:43.099515 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:45:43.099856 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:45:43.100200 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:45:43.100788 Not decompressing ramdisk as can be used compressed.
18 01:45:43.101217 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:45:43.101458 saving as /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/ramdisk/rootfs.cpio.gz
20 01:45:43.101713 total size: 47897469 (45 MB)
21 01:45:43.142565 progress 0 % (0 MB)
22 01:45:43.172942 progress 5 % (2 MB)
23 01:45:43.201854 progress 10 % (4 MB)
24 01:45:43.230948 progress 15 % (6 MB)
25 01:45:43.260168 progress 20 % (9 MB)
26 01:45:43.289271 progress 25 % (11 MB)
27 01:45:43.318334 progress 30 % (13 MB)
28 01:45:43.347506 progress 35 % (16 MB)
29 01:45:43.376651 progress 40 % (18 MB)
30 01:45:43.405705 progress 45 % (20 MB)
31 01:45:43.434893 progress 50 % (22 MB)
32 01:45:43.463855 progress 55 % (25 MB)
33 01:45:43.493178 progress 60 % (27 MB)
34 01:45:43.522141 progress 65 % (29 MB)
35 01:45:43.551248 progress 70 % (32 MB)
36 01:45:43.580221 progress 75 % (34 MB)
37 01:45:43.610528 progress 80 % (36 MB)
38 01:45:43.644462 progress 85 % (38 MB)
39 01:45:43.677936 progress 90 % (41 MB)
40 01:45:43.706882 progress 95 % (43 MB)
41 01:45:43.734816 progress 100 % (45 MB)
42 01:45:43.735533 45 MB downloaded in 0.63 s (72.07 MB/s)
43 01:45:43.736103 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:45:43.736990 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:45:43.737282 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:45:43.737548 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:45:43.738021 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/kernel/Image
49 01:45:43.738260 saving as /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/kernel/Image
50 01:45:43.738468 total size: 45713920 (43 MB)
51 01:45:43.738677 No compression specified
52 01:45:43.778884 progress 0 % (0 MB)
53 01:45:43.806864 progress 5 % (2 MB)
54 01:45:43.834388 progress 10 % (4 MB)
55 01:45:43.861813 progress 15 % (6 MB)
56 01:45:43.889716 progress 20 % (8 MB)
57 01:45:43.916788 progress 25 % (10 MB)
58 01:45:43.944219 progress 30 % (13 MB)
59 01:45:43.971586 progress 35 % (15 MB)
60 01:45:43.999300 progress 40 % (17 MB)
61 01:45:44.026608 progress 45 % (19 MB)
62 01:45:44.053985 progress 50 % (21 MB)
63 01:45:44.081695 progress 55 % (24 MB)
64 01:45:44.109569 progress 60 % (26 MB)
65 01:45:44.136745 progress 65 % (28 MB)
66 01:45:44.164391 progress 70 % (30 MB)
67 01:45:44.192199 progress 75 % (32 MB)
68 01:45:44.219665 progress 80 % (34 MB)
69 01:45:44.246960 progress 85 % (37 MB)
70 01:45:44.274493 progress 90 % (39 MB)
71 01:45:44.302366 progress 95 % (41 MB)
72 01:45:44.329119 progress 100 % (43 MB)
73 01:45:44.329624 43 MB downloaded in 0.59 s (73.75 MB/s)
74 01:45:44.330102 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:45:44.330916 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:45:44.331190 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:45:44.331453 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:45:44.331918 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:45:44.332210 saving as /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:45:44.332421 total size: 54703 (0 MB)
82 01:45:44.332628 No compression specified
83 01:45:44.374362 progress 59 % (0 MB)
84 01:45:44.375226 progress 100 % (0 MB)
85 01:45:44.375776 0 MB downloaded in 0.04 s (1.20 MB/s)
86 01:45:44.376286 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:45:44.377098 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:45:44.377362 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:45:44.377625 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:45:44.378087 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/modules.tar.xz
92 01:45:44.378324 saving as /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/modules/modules.tar
93 01:45:44.378528 total size: 11592552 (11 MB)
94 01:45:44.378736 Using unxz to decompress xz
95 01:45:44.417005 progress 0 % (0 MB)
96 01:45:44.485667 progress 5 % (0 MB)
97 01:45:44.561292 progress 10 % (1 MB)
98 01:45:44.643734 progress 15 % (1 MB)
99 01:45:44.719565 progress 20 % (2 MB)
100 01:45:44.799044 progress 25 % (2 MB)
101 01:45:44.878129 progress 30 % (3 MB)
102 01:45:44.949871 progress 35 % (3 MB)
103 01:45:45.028671 progress 40 % (4 MB)
104 01:45:45.118338 progress 45 % (5 MB)
105 01:45:45.196016 progress 50 % (5 MB)
106 01:45:45.278901 progress 55 % (6 MB)
107 01:45:45.359444 progress 60 % (6 MB)
108 01:45:45.438900 progress 65 % (7 MB)
109 01:45:45.518783 progress 70 % (7 MB)
110 01:45:45.602466 progress 75 % (8 MB)
111 01:45:45.694010 progress 80 % (8 MB)
112 01:45:45.769316 progress 85 % (9 MB)
113 01:45:45.841586 progress 90 % (9 MB)
114 01:45:45.940353 progress 95 % (10 MB)
115 01:45:46.031760 progress 100 % (11 MB)
116 01:45:46.046227 11 MB downloaded in 1.67 s (6.63 MB/s)
117 01:45:46.046923 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:45:46.047935 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:45:46.048669 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:45:46.049378 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:45:46.050016 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:45:46.050659 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:45:46.051927 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r
125 01:45:46.053022 makedir: /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin
126 01:45:46.053852 makedir: /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/tests
127 01:45:46.054649 makedir: /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/results
128 01:45:46.055420 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-add-keys
129 01:45:46.056645 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-add-sources
130 01:45:46.057887 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-background-process-start
131 01:45:46.059111 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-background-process-stop
132 01:45:46.060390 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-common-functions
133 01:45:46.061555 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-echo-ipv4
134 01:45:46.062745 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-install-packages
135 01:45:46.064012 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-installed-packages
136 01:45:46.065190 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-os-build
137 01:45:46.066348 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-probe-channel
138 01:45:46.067586 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-probe-ip
139 01:45:46.068816 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-target-ip
140 01:45:46.069965 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-target-mac
141 01:45:46.071095 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-target-storage
142 01:45:46.072291 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-case
143 01:45:46.073442 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-event
144 01:45:46.074606 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-feedback
145 01:45:46.075761 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-raise
146 01:45:46.076950 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-reference
147 01:45:46.078088 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-runner
148 01:45:46.079211 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-set
149 01:45:46.080385 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-test-shell
150 01:45:46.081585 Updating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-install-packages (oe)
151 01:45:46.082810 Updating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/bin/lava-installed-packages (oe)
152 01:45:46.083850 Creating /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/environment
153 01:45:46.084540 LAVA metadata
154 01:45:46.084881 - LAVA_JOB_ID=919444
155 01:45:46.085165 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:45:46.085610 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:45:46.086856 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:45:46.087276 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:45:46.087538 skipped lava-vland-overlay
160 01:45:46.087837 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:45:46.088196 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:45:46.088470 skipped lava-multinode-overlay
163 01:45:46.088778 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:45:46.089087 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:45:46.089399 Loading test definitions
166 01:45:46.089741 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:45:46.090021 Using /lava-919444 at stage 0
168 01:45:46.091508 uuid=919444_1.5.2.4.1 testdef=None
169 01:45:46.091942 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:45:46.092302 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:45:46.094462 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:45:46.095451 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:45:46.098080 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:45:46.099088 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:45:46.101653 runner path: /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/0/tests/0_igt-gpu-panfrost test_uuid 919444_1.5.2.4.1
178 01:45:46.102366 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:45:46.103366 Creating lava-test-runner.conf files
181 01:45:46.103621 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919444/lava-overlay-s92x8f2r/lava-919444/0 for stage 0
182 01:45:46.104066 - 0_igt-gpu-panfrost
183 01:45:46.104517 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:45:46.104865 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:45:46.132919 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:45:46.133386 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:45:46.133715 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:45:46.134044 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:45:46.134360 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:45:53.247455 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 01:45:53.247903 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 01:45:53.248193 extracting modules file /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk
193 01:45:54.668978 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:45:54.669459 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 01:45:54.669739 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919444/compress-overlay-c_6gtlla/overlay-1.5.2.5.tar.gz to ramdisk
196 01:45:54.669965 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919444/compress-overlay-c_6gtlla/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk
197 01:45:54.700465 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:45:54.700859 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 01:45:54.701127 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 01:45:54.701350 Converting downloaded kernel to a uImage
201 01:45:54.701652 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/kernel/Image /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/kernel/uImage
202 01:45:55.199940 output: Image Name:
203 01:45:55.200368 output: Created: Fri Nov 1 01:45:54 2024
204 01:45:55.200577 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:45:55.200779 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 01:45:55.200980 output: Load Address: 01080000
207 01:45:55.201180 output: Entry Point: 01080000
208 01:45:55.201378 output:
209 01:45:55.201708 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 01:45:55.201969 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 01:45:55.202237 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:45:55.202491 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:45:55.202745 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:45:55.203001 Building ramdisk /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk
215 01:46:02.052773 >> 502407 blocks
216 01:46:22.716274 Adding RAMdisk u-boot header.
217 01:46:22.716695 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk.cpio.gz.uboot
218 01:46:23.508966 output: Image Name:
219 01:46:23.509372 output: Created: Fri Nov 1 01:46:22 2024
220 01:46:23.509580 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:46:23.509781 output: Data Size: 65721565 Bytes = 64181.22 KiB = 62.68 MiB
222 01:46:23.509981 output: Load Address: 00000000
223 01:46:23.510179 output: Entry Point: 00000000
224 01:46:23.510374 output:
225 01:46:23.511001 rename /var/lib/lava/dispatcher/tmp/919444/extract-overlay-ramdisk-hkqw0veu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot
226 01:46:23.511427 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 01:46:23.511711 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 01:46:23.512010 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 01:46:23.512468 No LXC device requested
230 01:46:23.512967 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:46:23.513473 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 01:46:23.513956 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:46:23.514369 Checking files for TFTP limit of 4294967296 bytes.
234 01:46:23.517018 end: 1 tftp-deploy (duration 00:00:40) [common]
235 01:46:23.517585 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:46:23.518099 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:46:23.518592 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:46:23.519085 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:46:23.519604 Using kernel file from prepare-kernel: 919444/tftp-deploy-l_ig1t0h/kernel/uImage
240 01:46:23.520234 substitutions:
241 01:46:23.520644 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:46:23.521047 - {DTB_ADDR}: 0x01070000
243 01:46:23.521444 - {DTB}: 919444/tftp-deploy-l_ig1t0h/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:46:23.521842 - {INITRD}: 919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot
245 01:46:23.522236 - {KERNEL_ADDR}: 0x01080000
246 01:46:23.522624 - {KERNEL}: 919444/tftp-deploy-l_ig1t0h/kernel/uImage
247 01:46:23.523015 - {LAVA_MAC}: None
248 01:46:23.523443 - {PRESEED_CONFIG}: None
249 01:46:23.523836 - {PRESEED_LOCAL}: None
250 01:46:23.524257 - {RAMDISK_ADDR}: 0x08000000
251 01:46:23.524645 - {RAMDISK}: 919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot
252 01:46:23.525039 - {ROOT_PART}: None
253 01:46:23.525421 - {ROOT}: None
254 01:46:23.525808 - {SERVER_IP}: 192.168.6.2
255 01:46:23.526199 - {TEE_ADDR}: 0x83000000
256 01:46:23.526582 - {TEE}: None
257 01:46:23.526965 Parsed boot commands:
258 01:46:23.527339 - setenv autoload no
259 01:46:23.527723 - setenv initrd_high 0xffffffff
260 01:46:23.528142 - setenv fdt_high 0xffffffff
261 01:46:23.528530 - dhcp
262 01:46:23.528916 - setenv serverip 192.168.6.2
263 01:46:23.529299 - tftpboot 0x01080000 919444/tftp-deploy-l_ig1t0h/kernel/uImage
264 01:46:23.529683 - tftpboot 0x08000000 919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot
265 01:46:23.530070 - tftpboot 0x01070000 919444/tftp-deploy-l_ig1t0h/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:46:23.530454 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:46:23.530844 - bootm 0x01080000 0x08000000 0x01070000
268 01:46:23.531343 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:46:23.532838 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:46:23.533280 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:46:23.548011 Setting prompt string to ['lava-test: # ']
273 01:46:23.549509 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:46:23.550107 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:46:23.550641 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:46:23.551148 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:46:23.552305 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:46:23.588948 >> OK - accepted request
279 01:46:23.591033 Returned 0 in 0 seconds
280 01:46:23.692125 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:46:23.693715 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:46:23.694280 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:46:23.694778 Setting prompt string to ['Hit any key to stop autoboot']
285 01:46:23.695226 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:46:23.696776 Trying 192.168.56.21...
287 01:46:23.697259 Connected to conserv1.
288 01:46:23.697680 Escape character is '^]'.
289 01:46:23.698092
290 01:46:23.698506 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:46:23.698932
292 01:46:35.167821 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:46:35.168254 bl2_stage_init 0x01
294 01:46:35.168485 bl2_stage_init 0x81
295 01:46:35.173254 hw id: 0x0000 - pwm id 0x01
296 01:46:35.173574 bl2_stage_init 0xc1
297 01:46:35.173797 bl2_stage_init 0x02
298 01:46:35.174004
299 01:46:35.178737 L0:00000000
300 01:46:35.179007 L1:20000703
301 01:46:35.179216 L2:00008067
302 01:46:35.179417 L3:14000000
303 01:46:35.181693 B2:00402000
304 01:46:35.181954 B1:e0f83180
305 01:46:35.182156
306 01:46:35.182361 TE: 58124
307 01:46:35.182565
308 01:46:35.192901 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:46:35.193187
310 01:46:35.193394 Board ID = 1
311 01:46:35.193596 Set A53 clk to 24M
312 01:46:35.193794 Set A73 clk to 24M
313 01:46:35.198908 Set clk81 to 24M
314 01:46:35.199181 A53 clk: 1200 MHz
315 01:46:35.199383 A73 clk: 1200 MHz
316 01:46:35.201961 CLK81: 166.6M
317 01:46:35.202219 smccc: 00012a92
318 01:46:35.207549 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:46:35.213213 board id: 1
320 01:46:35.217433 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:46:35.228912 fw parse done
322 01:46:35.234928 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:46:35.277643 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:46:35.288434 PIEI prepare done
325 01:46:35.288718 fastboot data load
326 01:46:35.288933 fastboot data verify
327 01:46:35.294126 verify result: 266
328 01:46:35.299572 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:46:35.299862 LPDDR4 probe
330 01:46:35.300108 ddr clk to 1584MHz
331 01:46:35.307598 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:46:35.344155
333 01:46:35.344720 dmc_version 0001
334 01:46:35.351602 Check phy result
335 01:46:35.357477 INFO : End of CA training
336 01:46:35.358117 INFO : End of initialization
337 01:46:35.363024 INFO : Training has run successfully!
338 01:46:35.363480 Check phy result
339 01:46:35.368615 INFO : End of initialization
340 01:46:35.369048 INFO : End of read enable training
341 01:46:35.371969 INFO : End of fine write leveling
342 01:46:35.377610 INFO : End of Write leveling coarse delay
343 01:46:35.383134 INFO : Training has run successfully!
344 01:46:35.383573 Check phy result
345 01:46:35.384000 INFO : End of initialization
346 01:46:35.388801 INFO : End of read dq deskew training
347 01:46:35.394518 INFO : End of MPR read delay center optimization
348 01:46:35.394961 INFO : End of write delay center optimization
349 01:46:35.399973 INFO : End of read delay center optimization
350 01:46:35.405528 INFO : End of max read latency training
351 01:46:35.405962 INFO : Training has run successfully!
352 01:46:35.411128 1D training succeed
353 01:46:35.417074 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:46:35.464635 Check phy result
355 01:46:35.465100 INFO : End of initialization
356 01:46:35.486386 INFO : End of 2D read delay Voltage center optimization
357 01:46:35.506658 INFO : End of 2D read delay Voltage center optimization
358 01:46:35.558784 INFO : End of 2D write delay Voltage center optimization
359 01:46:35.608271 INFO : End of 2D write delay Voltage center optimization
360 01:46:35.613613 INFO : Training has run successfully!
361 01:46:35.614054
362 01:46:35.614462 channel==0
363 01:46:35.619273 RxClkDly_Margin_A0==88 ps 9
364 01:46:35.619709 TxDqDly_Margin_A0==98 ps 10
365 01:46:35.624809 RxClkDly_Margin_A1==88 ps 9
366 01:46:35.625237 TxDqDly_Margin_A1==98 ps 10
367 01:46:35.625641 TrainedVREFDQ_A0==74
368 01:46:35.630397 TrainedVREFDQ_A1==74
369 01:46:35.630827 VrefDac_Margin_A0==25
370 01:46:35.631227 DeviceVref_Margin_A0==40
371 01:46:35.636175 VrefDac_Margin_A1==25
372 01:46:35.636609 DeviceVref_Margin_A1==40
373 01:46:35.637008
374 01:46:35.637409
375 01:46:35.641673 channel==1
376 01:46:35.642099 RxClkDly_Margin_A0==98 ps 10
377 01:46:35.642500 TxDqDly_Margin_A0==88 ps 9
378 01:46:35.647242 RxClkDly_Margin_A1==98 ps 10
379 01:46:35.647671 TxDqDly_Margin_A1==98 ps 10
380 01:46:35.652875 TrainedVREFDQ_A0==77
381 01:46:35.653314 TrainedVREFDQ_A1==77
382 01:46:35.653719 VrefDac_Margin_A0==22
383 01:46:35.658478 DeviceVref_Margin_A0==37
384 01:46:35.658904 VrefDac_Margin_A1==22
385 01:46:35.664082 DeviceVref_Margin_A1==37
386 01:46:35.664516
387 01:46:35.664920 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:46:35.669608
389 01:46:35.697560 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 01:46:35.698078 2D training succeed
391 01:46:35.703160 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:46:35.708759 auto size-- 65535DDR cs0 size: 2048MB
393 01:46:35.709193 DDR cs1 size: 2048MB
394 01:46:35.714386 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:46:35.714815 cs0 DataBus test pass
396 01:46:35.719972 cs1 DataBus test pass
397 01:46:35.720441 cs0 AddrBus test pass
398 01:46:35.720843 cs1 AddrBus test pass
399 01:46:35.721233
400 01:46:35.725530 100bdlr_step_size ps== 420
401 01:46:35.725972 result report
402 01:46:35.731128 boot times 0Enable ddr reg access
403 01:46:35.736630 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:46:35.750112 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:46:36.323901 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:46:36.324537 MVN_1=0x00000000
407 01:46:36.329146 MVN_2=0x00000000
408 01:46:36.334979 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:46:36.335423 OPS=0x10
410 01:46:36.335833 ring efuse init
411 01:46:36.336266 chipver efuse init
412 01:46:36.340564 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:46:36.346135 [0.018961 Inits done]
414 01:46:36.346574 secure task start!
415 01:46:36.346974 high task start!
416 01:46:36.350703 low task start!
417 01:46:36.351133 run into bl31
418 01:46:36.357367 NOTICE: BL31: v1.3(release):4fc40b1
419 01:46:36.365181 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:46:36.365641 NOTICE: BL31: G12A normal boot!
421 01:46:36.390514 NOTICE: BL31: BL33 decompress pass
422 01:46:36.396215 ERROR: Error initializing runtime service opteed_fast
423 01:46:37.629119
424 01:46:37.629731
425 01:46:37.637476 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:46:37.637928
427 01:46:37.638339 Model: Libre Computer AML-A311D-CC Alta
428 01:46:37.846085 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:46:37.868275 DRAM: 2 GiB (effective 3.8 GiB)
430 01:46:38.012500 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:46:38.018149 WDT: Not starting watchdog@f0d0
432 01:46:38.050388 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:46:38.062884 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:46:38.067817 ** Bad device specification mmc 0 **
435 01:46:38.078265 Card did not respond to voltage select! : -110
436 01:46:38.085838 ** Bad device specification mmc 0 **
437 01:46:38.086274 Couldn't find partition mmc 0
438 01:46:38.094230 Card did not respond to voltage select! : -110
439 01:46:38.099676 ** Bad device specification mmc 0 **
440 01:46:38.100133 Couldn't find partition mmc 0
441 01:46:38.104736 Error: could not access storage.
442 01:46:39.367863 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 01:46:39.368708 bl2_stage_init 0x01
444 01:46:39.369277 bl2_stage_init 0x81
445 01:46:39.373439 hw id: 0x0000 - pwm id 0x01
446 01:46:39.374004 bl2_stage_init 0xc1
447 01:46:39.374540 bl2_stage_init 0x02
448 01:46:39.375058
449 01:46:39.379010 L0:00000000
450 01:46:39.379561 L1:20000703
451 01:46:39.380115 L2:00008067
452 01:46:39.380645 L3:14000000
453 01:46:39.384619 B2:00402000
454 01:46:39.385178 B1:e0f83180
455 01:46:39.385699
456 01:46:39.386225 TE: 58167
457 01:46:39.386738
458 01:46:39.390233 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 01:46:39.390807
460 01:46:39.391342 Board ID = 1
461 01:46:39.395801 Set A53 clk to 24M
462 01:46:39.396371 Set A73 clk to 24M
463 01:46:39.396906 Set clk81 to 24M
464 01:46:39.401466 A53 clk: 1200 MHz
465 01:46:39.402027 A73 clk: 1200 MHz
466 01:46:39.402552 CLK81: 166.6M
467 01:46:39.403064 smccc: 00012abe
468 01:46:39.407006 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 01:46:39.412624 board id: 1
470 01:46:39.418529 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 01:46:39.429218 fw parse done
472 01:46:39.435074 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 01:46:39.477725 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 01:46:39.488611 PIEI prepare done
475 01:46:39.489208 fastboot data load
476 01:46:39.489746 fastboot data verify
477 01:46:39.494328 verify result: 266
478 01:46:39.499883 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 01:46:39.500475 LPDDR4 probe
480 01:46:39.500993 ddr clk to 1584MHz
481 01:46:39.507872 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 01:46:39.545124
483 01:46:39.545714 dmc_version 0001
484 01:46:39.551794 Check phy result
485 01:46:39.557658 INFO : End of CA training
486 01:46:39.558210 INFO : End of initialization
487 01:46:39.563289 INFO : Training has run successfully!
488 01:46:39.563835 Check phy result
489 01:46:39.568875 INFO : End of initialization
490 01:46:39.569422 INFO : End of read enable training
491 01:46:39.572223 INFO : End of fine write leveling
492 01:46:39.577792 INFO : End of Write leveling coarse delay
493 01:46:39.583524 INFO : Training has run successfully!
494 01:46:39.584112 Check phy result
495 01:46:39.584649 INFO : End of initialization
496 01:46:39.589014 INFO : End of read dq deskew training
497 01:46:39.594593 INFO : End of MPR read delay center optimization
498 01:46:39.595127 INFO : End of write delay center optimization
499 01:46:39.600204 INFO : End of read delay center optimization
500 01:46:39.605770 INFO : End of max read latency training
501 01:46:39.606332 INFO : Training has run successfully!
502 01:46:39.611378 1D training succeed
503 01:46:39.617235 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 01:46:39.664859 Check phy result
505 01:46:39.665428 INFO : End of initialization
506 01:46:39.687427 INFO : End of 2D read delay Voltage center optimization
507 01:46:39.707672 INFO : End of 2D read delay Voltage center optimization
508 01:46:39.759768 INFO : End of 2D write delay Voltage center optimization
509 01:46:39.809103 INFO : End of 2D write delay Voltage center optimization
510 01:46:39.814668 INFO : Training has run successfully!
511 01:46:39.815221
512 01:46:39.815782 channel==0
513 01:46:39.820326 RxClkDly_Margin_A0==88 ps 9
514 01:46:39.820914 TxDqDly_Margin_A0==98 ps 10
515 01:46:39.823567 RxClkDly_Margin_A1==88 ps 9
516 01:46:39.824158 TxDqDly_Margin_A1==88 ps 9
517 01:46:39.835560 TrainedVREFDQ_A0==74
518 01:46:39.836171 TrainedVREFDQ_A1==74
519 01:46:39.836701 VrefDac_Margin_A0==24
520 01:46:39.837212 DeviceVref_Margin_A0==40
521 01:46:39.838086 VrefDac_Margin_A1==24
522 01:46:39.838635 DeviceVref_Margin_A1==40
523 01:46:39.839151
524 01:46:39.839661
525 01:46:39.840218 channel==1
526 01:46:39.843547 RxClkDly_Margin_A0==98 ps 10
527 01:46:39.844146 TxDqDly_Margin_A0==98 ps 10
528 01:46:39.849064 RxClkDly_Margin_A1==88 ps 9
529 01:46:39.849622 TxDqDly_Margin_A1==88 ps 9
530 01:46:39.854660 TrainedVREFDQ_A0==77
531 01:46:39.855218 TrainedVREFDQ_A1==77
532 01:46:39.855740 VrefDac_Margin_A0==22
533 01:46:39.860330 DeviceVref_Margin_A0==37
534 01:46:39.860877 VrefDac_Margin_A1==24
535 01:46:39.861391 DeviceVref_Margin_A1==37
536 01:46:39.861901
537 01:46:39.865831 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 01:46:39.866378
539 01:46:39.899577 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 01:46:39.900238 2D training succeed
541 01:46:39.905074 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 01:46:39.910641 auto size-- 65535DDR cs0 size: 2048MB
543 01:46:39.911208 DDR cs1 size: 2048MB
544 01:46:39.916308 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 01:46:39.916908 cs0 DataBus test pass
546 01:46:39.917456 cs1 DataBus test pass
547 01:46:39.921811 cs0 AddrBus test pass
548 01:46:39.922389 cs1 AddrBus test pass
549 01:46:39.922930
550 01:46:39.927589 100bdlr_step_size ps== 420
551 01:46:39.928237 result report
552 01:46:39.928783 boot times 0Enable ddr reg access
553 01:46:39.937647 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 01:46:39.951015 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 01:46:40.524758 0.0;M3 CHK:0;cm4_sp_mode 0
556 01:46:40.525398 MVN_1=0x00000000
557 01:46:40.530108 MVN_2=0x00000000
558 01:46:40.535850 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 01:46:40.536357 OPS=0x10
560 01:46:40.536769 ring efuse init
561 01:46:40.537178 chipver efuse init
562 01:46:40.544245 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 01:46:40.544758 [0.018960 Inits done]
564 01:46:40.545149 secure task start!
565 01:46:40.551635 high task start!
566 01:46:40.552094 low task start!
567 01:46:40.552484 run into bl31
568 01:46:40.558338 NOTICE: BL31: v1.3(release):4fc40b1
569 01:46:40.566087 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 01:46:40.566522 NOTICE: BL31: G12A normal boot!
571 01:46:40.591445 NOTICE: BL31: BL33 decompress pass
572 01:46:40.597151 ERROR: Error initializing runtime service opteed_fast
573 01:46:41.830048
574 01:46:41.830628
575 01:46:41.837468 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 01:46:41.837948
577 01:46:41.838366 Model: Libre Computer AML-A311D-CC Alta
578 01:46:42.045948 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 01:46:42.070243 DRAM: 2 GiB (effective 3.8 GiB)
580 01:46:42.213242 Core: 408 devices, 31 uclasses, devicetree: separate
581 01:46:42.219067 WDT: Not starting watchdog@f0d0
582 01:46:42.251298 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 01:46:42.263864 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 01:46:42.268752 ** Bad device specification mmc 0 **
585 01:46:42.279091 Card did not respond to voltage select! : -110
586 01:46:42.286740 ** Bad device specification mmc 0 **
587 01:46:42.287308 Couldn't find partition mmc 0
588 01:46:42.295095 Card did not respond to voltage select! : -110
589 01:46:42.300622 ** Bad device specification mmc 0 **
590 01:46:42.301211 Couldn't find partition mmc 0
591 01:46:42.305635 Error: could not access storage.
592 01:46:42.649212 Net: eth0: ethernet@ff3f0000
593 01:46:42.649793 starting USB...
594 01:46:42.901077 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 01:46:42.901667 Starting the controller
596 01:46:42.908050 USB XHCI 1.10
597 01:46:44.567936 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 01:46:44.568550 bl2_stage_init 0x01
599 01:46:44.568967 bl2_stage_init 0x81
600 01:46:44.573525 hw id: 0x0000 - pwm id 0x01
601 01:46:44.573979 bl2_stage_init 0xc1
602 01:46:44.574391 bl2_stage_init 0x02
603 01:46:44.574794
604 01:46:44.579139 L0:00000000
605 01:46:44.579574 L1:20000703
606 01:46:44.579977 L2:00008067
607 01:46:44.580405 L3:14000000
608 01:46:44.584682 B2:00402000
609 01:46:44.585110 B1:e0f83180
610 01:46:44.585510
611 01:46:44.585907 TE: 58167
612 01:46:44.586308
613 01:46:44.590279 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 01:46:44.590714
615 01:46:44.591116 Board ID = 1
616 01:46:44.595892 Set A53 clk to 24M
617 01:46:44.596376 Set A73 clk to 24M
618 01:46:44.596781 Set clk81 to 24M
619 01:46:44.601516 A53 clk: 1200 MHz
620 01:46:44.601958 A73 clk: 1200 MHz
621 01:46:44.602365 CLK81: 166.6M
622 01:46:44.602761 smccc: 00012abe
623 01:46:44.607130 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 01:46:44.612695 board id: 1
625 01:46:44.618598 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 01:46:44.629266 fw parse done
627 01:46:44.635212 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 01:46:44.677862 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 01:46:44.688711 PIEI prepare done
630 01:46:44.689137 fastboot data load
631 01:46:44.689540 fastboot data verify
632 01:46:44.694380 verify result: 266
633 01:46:44.700064 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 01:46:44.700496 LPDDR4 probe
635 01:46:44.700901 ddr clk to 1584MHz
636 01:46:44.708062 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 01:46:44.745353
638 01:46:44.745795 dmc_version 0001
639 01:46:44.751917 Check phy result
640 01:46:44.757782 INFO : End of CA training
641 01:46:44.758210 INFO : End of initialization
642 01:46:44.763373 INFO : Training has run successfully!
643 01:46:44.763794 Check phy result
644 01:46:44.768964 INFO : End of initialization
645 01:46:44.769389 INFO : End of read enable training
646 01:46:44.774553 INFO : End of fine write leveling
647 01:46:44.780214 INFO : End of Write leveling coarse delay
648 01:46:44.780638 INFO : Training has run successfully!
649 01:46:44.781034 Check phy result
650 01:46:44.785746 INFO : End of initialization
651 01:46:44.786167 INFO : End of read dq deskew training
652 01:46:44.791375 INFO : End of MPR read delay center optimization
653 01:46:44.796975 INFO : End of write delay center optimization
654 01:46:44.802562 INFO : End of read delay center optimization
655 01:46:44.802985 INFO : End of max read latency training
656 01:46:44.808227 INFO : Training has run successfully!
657 01:46:44.808646 1D training succeed
658 01:46:44.817362 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 01:46:44.864996 Check phy result
660 01:46:44.865432 INFO : End of initialization
661 01:46:44.885690 INFO : End of 2D read delay Voltage center optimization
662 01:46:44.906899 INFO : End of 2D read delay Voltage center optimization
663 01:46:44.958911 INFO : End of 2D write delay Voltage center optimization
664 01:46:45.008306 INFO : End of 2D write delay Voltage center optimization
665 01:46:45.013897 INFO : Training has run successfully!
666 01:46:45.014320
667 01:46:45.014725 channel==0
668 01:46:45.019503 RxClkDly_Margin_A0==88 ps 9
669 01:46:45.019922 TxDqDly_Margin_A0==98 ps 10
670 01:46:45.025093 RxClkDly_Margin_A1==88 ps 9
671 01:46:45.025515 TxDqDly_Margin_A1==98 ps 10
672 01:46:45.025922 TrainedVREFDQ_A0==74
673 01:46:45.030700 TrainedVREFDQ_A1==74
674 01:46:45.031127 VrefDac_Margin_A0==25
675 01:46:45.031528 DeviceVref_Margin_A0==40
676 01:46:45.036302 VrefDac_Margin_A1==25
677 01:46:45.036725 DeviceVref_Margin_A1==40
678 01:46:45.037122
679 01:46:45.037516
680 01:46:45.041897 channel==1
681 01:46:45.042321 RxClkDly_Margin_A0==98 ps 10
682 01:46:45.042719 TxDqDly_Margin_A0==98 ps 10
683 01:46:45.047482 RxClkDly_Margin_A1==98 ps 10
684 01:46:45.047904 TxDqDly_Margin_A1==88 ps 9
685 01:46:45.053072 TrainedVREFDQ_A0==77
686 01:46:45.053499 TrainedVREFDQ_A1==77
687 01:46:45.053901 VrefDac_Margin_A0==22
688 01:46:45.058683 DeviceVref_Margin_A0==37
689 01:46:45.059106 VrefDac_Margin_A1==22
690 01:46:45.064299 DeviceVref_Margin_A1==37
691 01:46:45.064717
692 01:46:45.065118 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 01:46:45.069904
694 01:46:45.097905 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 01:46:45.098350 2D training succeed
696 01:46:45.103477 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 01:46:45.109067 auto size-- 65535DDR cs0 size: 2048MB
698 01:46:45.109492 DDR cs1 size: 2048MB
699 01:46:45.114674 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 01:46:45.115092 cs0 DataBus test pass
701 01:46:45.120319 cs1 DataBus test pass
702 01:46:45.120739 cs0 AddrBus test pass
703 01:46:45.121135 cs1 AddrBus test pass
704 01:46:45.121527
705 01:46:45.125912 100bdlr_step_size ps== 420
706 01:46:45.126341 result report
707 01:46:45.131477 boot times 0Enable ddr reg access
708 01:46:45.136920 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 01:46:45.150381 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 01:46:45.723381 0.0;M3 CHK:0;cm4_sp_mode 0
711 01:46:45.723920 MVN_1=0x00000000
712 01:46:45.728930 MVN_2=0x00000000
713 01:46:45.734692 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 01:46:45.735192 OPS=0x10
715 01:46:45.735617 ring efuse init
716 01:46:45.736065 chipver efuse init
717 01:46:45.740285 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 01:46:46.050089 [0.018961 Inits done]
719 01:46:46.050676 secure task start!
720 01:46:46.051089 high task start!
721 01:46:46.051490 low task start!
722 01:46:46.051887 run into bl31
723 01:46:46.052344 NOTICE: BL31: v1.3(release):4fc40b1
724 01:46:46.052755 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 01:46:46.053158 NOTICE: BL31: G12A normal boot!
726 01:46:46.053558 NOTICE: BL31: BL33 decompress pass
727 01:46:46.054301 ERROR: Error initializing runtime service opteed_fast
728 01:46:47.029021
729 01:46:47.029569
730 01:46:47.037459 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 01:46:47.037899
732 01:46:47.038301 Model: Libre Computer AML-A311D-CC Alta
733 01:46:47.245892 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 01:46:47.269312 DRAM: 2 GiB (effective 3.8 GiB)
735 01:46:47.412253 Core: 408 devices, 31 uclasses, devicetree: separate
736 01:46:47.418112 WDT: Not starting watchdog@f0d0
737 01:46:47.450348 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 01:46:47.462754 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 01:46:47.467699 ** Bad device specification mmc 0 **
740 01:46:47.478017 Card did not respond to voltage select! : -110
741 01:46:47.485726 ** Bad device specification mmc 0 **
742 01:46:47.486180 Couldn't find partition mmc 0
743 01:46:47.494112 Card did not respond to voltage select! : -110
744 01:46:47.499580 ** Bad device specification mmc 0 **
745 01:46:47.500042 Couldn't find partition mmc 0
746 01:46:47.504617 Error: could not access storage.
747 01:46:47.847169 Net: eth0: ethernet@ff3f0000
748 01:46:47.847681 starting USB...
749 01:46:48.099161 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 01:46:48.099693 Starting the controller
751 01:46:48.106027 USB XHCI 1.10
752 01:46:50.268331 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 01:46:50.268921 bl2_stage_init 0x01
754 01:46:50.269333 bl2_stage_init 0x81
755 01:46:50.273894 hw id: 0x0000 - pwm id 0x01
756 01:46:50.274333 bl2_stage_init 0xc1
757 01:46:50.274739 bl2_stage_init 0x02
758 01:46:50.275139
759 01:46:50.279408 L0:00000000
760 01:46:50.279839 L1:20000703
761 01:46:50.280295 L2:00008067
762 01:46:50.280694 L3:14000000
763 01:46:50.282319 B2:00402000
764 01:46:50.282747 B1:e0f83180
765 01:46:50.283144
766 01:46:50.283544 TE: 58124
767 01:46:50.283941
768 01:46:50.293477 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 01:46:50.293933
770 01:46:50.294338 Board ID = 1
771 01:46:50.294733 Set A53 clk to 24M
772 01:46:50.295125 Set A73 clk to 24M
773 01:46:50.299094 Set clk81 to 24M
774 01:46:50.299530 A53 clk: 1200 MHz
775 01:46:50.299933 A73 clk: 1200 MHz
776 01:46:50.304668 CLK81: 166.6M
777 01:46:50.305133 smccc: 00012a91
778 01:46:50.310244 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 01:46:50.310689 board id: 1
780 01:46:50.318953 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 01:46:50.329446 fw parse done
782 01:46:50.335397 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 01:46:50.377995 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 01:46:50.388957 PIEI prepare done
785 01:46:50.389396 fastboot data load
786 01:46:50.389814 fastboot data verify
787 01:46:50.394636 verify result: 266
788 01:46:50.400213 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 01:46:50.400660 LPDDR4 probe
790 01:46:50.401071 ddr clk to 1584MHz
791 01:46:50.408213 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 01:46:50.445440
793 01:46:50.445886 dmc_version 0001
794 01:46:50.452169 Check phy result
795 01:46:50.457946 INFO : End of CA training
796 01:46:50.458386 INFO : End of initialization
797 01:46:50.463576 INFO : Training has run successfully!
798 01:46:50.464071 Check phy result
799 01:46:50.469194 INFO : End of initialization
800 01:46:50.469648 INFO : End of read enable training
801 01:46:50.474801 INFO : End of fine write leveling
802 01:46:50.480373 INFO : End of Write leveling coarse delay
803 01:46:50.480825 INFO : Training has run successfully!
804 01:46:50.481236 Check phy result
805 01:46:50.485900 INFO : End of initialization
806 01:46:50.486358 INFO : End of read dq deskew training
807 01:46:50.491583 INFO : End of MPR read delay center optimization
808 01:46:50.497201 INFO : End of write delay center optimization
809 01:46:50.502824 INFO : End of read delay center optimization
810 01:46:50.503272 INFO : End of max read latency training
811 01:46:50.508378 INFO : Training has run successfully!
812 01:46:50.508824 1D training succeed
813 01:46:50.517611 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 01:46:50.565154 Check phy result
815 01:46:50.565619 INFO : End of initialization
816 01:46:50.586748 INFO : End of 2D read delay Voltage center optimization
817 01:46:50.606900 INFO : End of 2D read delay Voltage center optimization
818 01:46:50.658812 INFO : End of 2D write delay Voltage center optimization
819 01:46:50.708054 INFO : End of 2D write delay Voltage center optimization
820 01:46:50.713642 INFO : Training has run successfully!
821 01:46:50.714100
822 01:46:50.714524 channel==0
823 01:46:50.719247 RxClkDly_Margin_A0==88 ps 9
824 01:46:50.719749 TxDqDly_Margin_A0==108 ps 11
825 01:46:50.722489 RxClkDly_Margin_A1==88 ps 9
826 01:46:50.722953 TxDqDly_Margin_A1==98 ps 10
827 01:46:50.728161 TrainedVREFDQ_A0==74
828 01:46:50.728612 TrainedVREFDQ_A1==74
829 01:46:50.733737 VrefDac_Margin_A0==25
830 01:46:50.734262 DeviceVref_Margin_A0==40
831 01:46:50.734661 VrefDac_Margin_A1==25
832 01:46:50.739283 DeviceVref_Margin_A1==40
833 01:46:50.739810
834 01:46:50.740344
835 01:46:50.740775 channel==1
836 01:46:50.741168 RxClkDly_Margin_A0==98 ps 10
837 01:46:50.742738 TxDqDly_Margin_A0==88 ps 9
838 01:46:50.748222 RxClkDly_Margin_A1==88 ps 9
839 01:46:50.748663 TxDqDly_Margin_A1==88 ps 9
840 01:46:50.749059 TrainedVREFDQ_A0==76
841 01:46:50.753917 TrainedVREFDQ_A1==77
842 01:46:50.754352 VrefDac_Margin_A0==22
843 01:46:50.759458 DeviceVref_Margin_A0==38
844 01:46:50.759887 VrefDac_Margin_A1==24
845 01:46:50.760311 DeviceVref_Margin_A1==37
846 01:46:50.760695
847 01:46:50.765018 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 01:46:50.765450
849 01:46:50.798624 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 01:46:50.799102 2D training succeed
851 01:46:50.804226 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 01:46:50.809825 auto size-- 65535DDR cs0 size: 2048MB
853 01:46:50.810261 DDR cs1 size: 2048MB
854 01:46:50.815399 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 01:46:50.815827 cs0 DataBus test pass
856 01:46:50.816256 cs1 DataBus test pass
857 01:46:50.820996 cs0 AddrBus test pass
858 01:46:50.821426 cs1 AddrBus test pass
859 01:46:50.821816
860 01:46:50.826581 100bdlr_step_size ps== 420
861 01:46:50.827017 result report
862 01:46:50.827399 boot times 0Enable ddr reg access
863 01:46:50.836504 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 01:46:50.850037 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 01:46:51.422078 0.0;M3 CHK:0;cm4_sp_mode 0
866 01:46:51.422620 MVN_1=0x00000000
867 01:46:51.427452 MVN_2=0x00000000
868 01:46:51.433229 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 01:46:51.433707 OPS=0x10
870 01:46:51.434131 ring efuse init
871 01:46:51.434541 chipver efuse init
872 01:46:51.438881 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 01:46:51.444400 [0.018961 Inits done]
874 01:46:51.444854 secure task start!
875 01:46:51.445269 high task start!
876 01:46:51.449084 low task start!
877 01:46:51.449537 run into bl31
878 01:46:51.455661 NOTICE: BL31: v1.3(release):4fc40b1
879 01:46:51.463454 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 01:46:51.463927 NOTICE: BL31: G12A normal boot!
881 01:46:51.488891 NOTICE: BL31: BL33 decompress pass
882 01:46:51.494531 ERROR: Error initializing runtime service opteed_fast
883 01:46:52.727408
884 01:46:52.728057
885 01:46:52.735791 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 01:46:52.736294
887 01:46:52.736720 Model: Libre Computer AML-A311D-CC Alta
888 01:46:52.944367 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 01:46:52.967669 DRAM: 2 GiB (effective 3.8 GiB)
890 01:46:53.110637 Core: 408 devices, 31 uclasses, devicetree: separate
891 01:46:53.116486 WDT: Not starting watchdog@f0d0
892 01:46:53.148741 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 01:46:53.161246 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 01:46:53.166256 ** Bad device specification mmc 0 **
895 01:46:53.176487 Card did not respond to voltage select! : -110
896 01:46:53.184258 ** Bad device specification mmc 0 **
897 01:46:53.184728 Couldn't find partition mmc 0
898 01:46:53.192463 Card did not respond to voltage select! : -110
899 01:46:53.198067 ** Bad device specification mmc 0 **
900 01:46:53.198526 Couldn't find partition mmc 0
901 01:46:53.203137 Error: could not access storage.
902 01:46:53.546685 Net: eth0: ethernet@ff3f0000
903 01:46:53.547358 starting USB...
904 01:46:53.798451 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 01:46:53.799103 Starting the controller
906 01:46:53.805421 USB XHCI 1.10
907 01:46:55.359491 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 01:46:55.367832 scanning usb for storage devices... 0 Storage Device(s) found
910 01:46:55.419560 Hit any key to stop autoboot: 1
911 01:46:55.420757 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 01:46:55.421472 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 01:46:55.422012 Setting prompt string to ['=>']
914 01:46:55.422549 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 01:46:55.434277 0
916 01:46:55.435267 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 01:46:55.435823 Sending with 10 millisecond of delay
919 01:46:56.571415 => setenv autoload no
920 01:46:56.582344 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 01:46:56.587753 setenv autoload no
922 01:46:56.588593 Sending with 10 millisecond of delay
924 01:46:58.396753 => setenv initrd_high 0xffffffff
925 01:46:58.407583 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 01:46:58.408580 setenv initrd_high 0xffffffff
927 01:46:58.409336 Sending with 10 millisecond of delay
929 01:47:00.025793 => setenv fdt_high 0xffffffff
930 01:47:00.036631 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 01:47:00.037522 setenv fdt_high 0xffffffff
932 01:47:00.038285 Sending with 10 millisecond of delay
934 01:47:00.330206 => dhcp
935 01:47:00.340994 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 01:47:00.341874 dhcp
937 01:47:00.342351 Speed: 1000, full duplex
938 01:47:00.342804 BOOTP broadcast 1
939 01:47:00.520772 DHCP client bound to address 192.168.6.27 (179 ms)
940 01:47:00.521657 Sending with 10 millisecond of delay
942 01:47:02.198349 => setenv serverip 192.168.6.2
943 01:47:02.209186 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 01:47:02.210133 setenv serverip 192.168.6.2
945 01:47:02.210871 Sending with 10 millisecond of delay
947 01:47:05.934561 => tftpboot 0x01080000 919444/tftp-deploy-l_ig1t0h/kernel/uImage
948 01:47:05.945384 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 01:47:05.946280 tftpboot 0x01080000 919444/tftp-deploy-l_ig1t0h/kernel/uImage
950 01:47:05.946767 Speed: 1000, full duplex
951 01:47:05.947224 Using ethernet@ff3f0000 device
952 01:47:05.948311 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 01:47:05.953845 Filename '919444/tftp-deploy-l_ig1t0h/kernel/uImage'.
954 01:47:05.957630 Load address: 0x1080000
955 01:47:08.742357 Loading: *################################################## 43.6 MiB
956 01:47:08.743015 15.6 MiB/s
957 01:47:08.743490 done
958 01:47:08.746980 Bytes transferred = 45713984 (2b98a40 hex)
959 01:47:08.747826 Sending with 10 millisecond of delay
961 01:47:13.434320 => tftpboot 0x08000000 919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot
962 01:47:13.445011 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 01:47:13.445491 tftpboot 0x08000000 919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot
964 01:47:13.445722 Speed: 1000, full duplex
965 01:47:13.445928 Using ethernet@ff3f0000 device
966 01:47:13.447481 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 01:47:13.456164 Filename '919444/tftp-deploy-l_ig1t0h/ramdisk/ramdisk.cpio.gz.uboot'.
968 01:47:13.456560 Load address: 0x8000000
969 01:47:24.090659 Loading: *########T ######################################### UDP wrong checksum 0000000f 0000c995
970 01:47:29.091461 T UDP wrong checksum 0000000f 0000c995
971 01:47:39.094380 T T UDP wrong checksum 0000000f 0000c995
972 01:47:59.098410 T T T T UDP wrong checksum 0000000f 0000c995
973 01:48:06.622324 T UDP wrong checksum 000000ff 0000a79d
974 01:48:06.634289 UDP wrong checksum 000000ff 00003e90
975 01:48:12.008917 T UDP wrong checksum 000000ff 00007dff
976 01:48:12.018408 UDP wrong checksum 000000ff 000011f2
977 01:48:14.102858
978 01:48:14.103519 Retry count exceeded; starting again
980 01:48:14.105038 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
983 01:48:14.107011 end: 2.4 uboot-commands (duration 00:01:51) [common]
985 01:48:14.108542 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 01:48:14.109653 end: 2 uboot-action (duration 00:01:51) [common]
989 01:48:14.111307 Cleaning after the job
990 01:48:14.111907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/ramdisk
991 01:48:14.113280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/kernel
992 01:48:14.159939 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/dtb
993 01:48:14.160779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919444/tftp-deploy-l_ig1t0h/modules
994 01:48:14.177954 start: 4.1 power-off (timeout 00:00:30) [common]
995 01:48:14.178582 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 01:48:14.215260 >> OK - accepted request
997 01:48:14.217477 Returned 0 in 0 seconds
998 01:48:14.318749 end: 4.1 power-off (duration 00:00:00) [common]
1000 01:48:14.320565 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 01:48:14.321810 Listened to connection for namespace 'common' for up to 1s
1002 01:48:15.322600 Finalising connection for namespace 'common'
1003 01:48:15.323379 Disconnecting from shell: Finalise
1004 01:48:15.323960 =>
1005 01:48:15.425089 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 01:48:15.425804 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919444
1007 01:48:16.090163 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919444
1008 01:48:16.090756 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.