Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:50:00.997676 lava-dispatcher, installed at version: 2024.01
2 00:50:00.998497 start: 0 validate
3 00:50:00.998975 Start time: 2024-11-01 00:50:00.998944+00:00 (UTC)
4 00:50:00.999671 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:50:01.000260 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:50:01.037817 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:50:01.038358 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:50:01.072560 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:50:01.073165 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 00:50:01.101005 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:50:01.101528 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 00:50:01.143960 validate duration: 0.15
14 00:50:01.144870 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:50:01.145242 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:50:01.145571 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:50:01.146186 Not decompressing ramdisk as can be used compressed.
18 00:50:01.146645 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:50:01.146928 saving as /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/ramdisk/rootfs.cpio.gz
20 00:50:01.147230 total size: 47897469 (45 MB)
21 00:50:01.188774 progress 0 % (0 MB)
22 00:50:01.222373 progress 5 % (2 MB)
23 00:50:01.257040 progress 10 % (4 MB)
24 00:50:01.289154 progress 15 % (6 MB)
25 00:50:01.319479 progress 20 % (9 MB)
26 00:50:01.349829 progress 25 % (11 MB)
27 00:50:01.380244 progress 30 % (13 MB)
28 00:50:01.410089 progress 35 % (16 MB)
29 00:50:01.440879 progress 40 % (18 MB)
30 00:50:01.470614 progress 45 % (20 MB)
31 00:50:01.501089 progress 50 % (22 MB)
32 00:50:01.530881 progress 55 % (25 MB)
33 00:50:01.561050 progress 60 % (27 MB)
34 00:50:01.591643 progress 65 % (29 MB)
35 00:50:01.621360 progress 70 % (32 MB)
36 00:50:01.651915 progress 75 % (34 MB)
37 00:50:01.681434 progress 80 % (36 MB)
38 00:50:01.711809 progress 85 % (38 MB)
39 00:50:01.741848 progress 90 % (41 MB)
40 00:50:01.771584 progress 95 % (43 MB)
41 00:50:01.801560 progress 100 % (45 MB)
42 00:50:01.802305 45 MB downloaded in 0.66 s (69.73 MB/s)
43 00:50:01.802856 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:50:01.803732 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:50:01.804049 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:50:01.804329 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:50:01.804808 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/kernel/Image
49 00:50:01.805048 saving as /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/kernel/Image
50 00:50:01.805256 total size: 45713920 (43 MB)
51 00:50:01.805467 No compression specified
52 00:50:01.842041 progress 0 % (0 MB)
53 00:50:01.871786 progress 5 % (2 MB)
54 00:50:01.901913 progress 10 % (4 MB)
55 00:50:01.930234 progress 15 % (6 MB)
56 00:50:01.959688 progress 20 % (8 MB)
57 00:50:01.987855 progress 25 % (10 MB)
58 00:50:02.016338 progress 30 % (13 MB)
59 00:50:02.045434 progress 35 % (15 MB)
60 00:50:02.073836 progress 40 % (17 MB)
61 00:50:02.102387 progress 45 % (19 MB)
62 00:50:02.130668 progress 50 % (21 MB)
63 00:50:02.159179 progress 55 % (24 MB)
64 00:50:02.188478 progress 60 % (26 MB)
65 00:50:02.216362 progress 65 % (28 MB)
66 00:50:02.245387 progress 70 % (30 MB)
67 00:50:02.274184 progress 75 % (32 MB)
68 00:50:02.302874 progress 80 % (34 MB)
69 00:50:02.331618 progress 85 % (37 MB)
70 00:50:02.360405 progress 90 % (39 MB)
71 00:50:02.389653 progress 95 % (41 MB)
72 00:50:02.418099 progress 100 % (43 MB)
73 00:50:02.418643 43 MB downloaded in 0.61 s (71.08 MB/s)
74 00:50:02.419130 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:50:02.419953 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:50:02.420264 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:50:02.420533 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:50:02.421014 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 00:50:02.421294 saving as /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 00:50:02.421504 total size: 53209 (0 MB)
82 00:50:02.421713 No compression specified
83 00:50:02.460646 progress 61 % (0 MB)
84 00:50:02.461499 progress 100 % (0 MB)
85 00:50:02.462035 0 MB downloaded in 0.04 s (1.25 MB/s)
86 00:50:02.462522 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:50:02.463330 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:50:02.463591 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:50:02.463859 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:50:02.464357 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/modules.tar.xz
92 00:50:02.464608 saving as /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/modules/modules.tar
93 00:50:02.464814 total size: 11592552 (11 MB)
94 00:50:02.465027 Using unxz to decompress xz
95 00:50:02.499148 progress 0 % (0 MB)
96 00:50:02.565424 progress 5 % (0 MB)
97 00:50:02.639584 progress 10 % (1 MB)
98 00:50:02.718991 progress 15 % (1 MB)
99 00:50:02.794042 progress 20 % (2 MB)
100 00:50:02.870195 progress 25 % (2 MB)
101 00:50:02.949206 progress 30 % (3 MB)
102 00:50:03.021220 progress 35 % (3 MB)
103 00:50:03.100979 progress 40 % (4 MB)
104 00:50:03.185555 progress 45 % (5 MB)
105 00:50:03.261524 progress 50 % (5 MB)
106 00:50:03.343790 progress 55 % (6 MB)
107 00:50:03.423857 progress 60 % (6 MB)
108 00:50:03.502295 progress 65 % (7 MB)
109 00:50:03.581834 progress 70 % (7 MB)
110 00:50:03.662818 progress 75 % (8 MB)
111 00:50:03.744569 progress 80 % (8 MB)
112 00:50:03.819839 progress 85 % (9 MB)
113 00:50:03.892047 progress 90 % (9 MB)
114 00:50:03.991245 progress 95 % (10 MB)
115 00:50:04.082952 progress 100 % (11 MB)
116 00:50:04.096622 11 MB downloaded in 1.63 s (6.78 MB/s)
117 00:50:04.097340 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:50:04.098345 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:50:04.098678 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 00:50:04.099008 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 00:50:04.099311 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:50:04.099626 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 00:50:04.100693 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a
125 00:50:04.101802 makedir: /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin
126 00:50:04.102625 makedir: /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/tests
127 00:50:04.103406 makedir: /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/results
128 00:50:04.104229 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-add-keys
129 00:50:04.105464 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-add-sources
130 00:50:04.106683 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-background-process-start
131 00:50:04.107910 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-background-process-stop
132 00:50:04.109206 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-common-functions
133 00:50:04.110363 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-echo-ipv4
134 00:50:04.111507 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-install-packages
135 00:50:04.112693 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-installed-packages
136 00:50:04.113812 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-os-build
137 00:50:04.114935 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-probe-channel
138 00:50:04.116302 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-probe-ip
139 00:50:04.117480 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-target-ip
140 00:50:04.118623 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-target-mac
141 00:50:04.119744 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-target-storage
142 00:50:04.121055 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-case
143 00:50:04.122224 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-event
144 00:50:04.123342 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-feedback
145 00:50:04.124563 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-raise
146 00:50:04.125730 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-reference
147 00:50:04.126926 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-runner
148 00:50:04.128121 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-set
149 00:50:04.128760 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-test-shell
150 00:50:04.129417 Updating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-install-packages (oe)
151 00:50:04.130154 Updating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/bin/lava-installed-packages (oe)
152 00:50:04.130725 Creating /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/environment
153 00:50:04.131207 LAVA metadata
154 00:50:04.131535 - LAVA_JOB_ID=919379
155 00:50:04.131806 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:50:04.132284 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:50:04.133500 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:50:04.133903 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:50:04.134162 skipped lava-vland-overlay
160 00:50:04.134468 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:50:04.134782 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:50:04.135054 skipped lava-multinode-overlay
163 00:50:04.135349 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:50:04.135658 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:50:04.135968 Loading test definitions
166 00:50:04.136345 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:50:04.136620 Using /lava-919379 at stage 0
168 00:50:04.138016 uuid=919379_1.5.2.4.1 testdef=None
169 00:50:04.138394 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:50:04.138724 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:50:04.140850 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:50:04.141865 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:50:04.144583 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:50:04.145640 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 00:50:04.148187 runner path: /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/0/tests/0_igt-gpu-panfrost test_uuid 919379_1.5.2.4.1
178 00:50:04.148921 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:50:04.149903 Creating lava-test-runner.conf files
181 00:50:04.150163 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919379/lava-overlay-rfmv152a/lava-919379/0 for stage 0
182 00:50:04.150564 - 0_igt-gpu-panfrost
183 00:50:04.151002 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:50:04.151347 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 00:50:04.179644 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:50:04.180141 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 00:50:04.180476 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:50:04.180806 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:50:04.181131 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 00:50:11.274787 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 00:50:11.275268 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 00:50:11.275527 extracting modules file /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk
193 00:50:12.702326 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 00:50:12.702814 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 00:50:12.703096 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919379/compress-overlay-pftmrwx5/overlay-1.5.2.5.tar.gz to ramdisk
196 00:50:12.703313 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919379/compress-overlay-pftmrwx5/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk
197 00:50:12.733388 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:50:12.733800 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 00:50:12.734075 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 00:50:12.734306 Converting downloaded kernel to a uImage
201 00:50:12.734613 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/kernel/Image /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/kernel/uImage
202 00:50:13.295085 output: Image Name:
203 00:50:13.295483 output: Created: Fri Nov 1 00:50:12 2024
204 00:50:13.295696 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:50:13.295901 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 00:50:13.296142 output: Load Address: 01080000
207 00:50:13.296346 output: Entry Point: 01080000
208 00:50:13.296547 output:
209 00:50:13.296882 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 00:50:13.297147 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 00:50:13.297417 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 00:50:13.297672 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:50:13.297930 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 00:50:13.298191 Building ramdisk /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk
215 00:50:20.887258 >> 502407 blocks
216 00:50:41.481394 Adding RAMdisk u-boot header.
217 00:50:41.482260 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk.cpio.gz.uboot
218 00:50:42.155414 output: Image Name:
219 00:50:42.155933 output: Created: Fri Nov 1 00:50:41 2024
220 00:50:42.156488 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:50:42.157052 output: Data Size: 65716409 Bytes = 64176.18 KiB = 62.67 MiB
222 00:50:42.157608 output: Load Address: 00000000
223 00:50:42.158143 output: Entry Point: 00000000
224 00:50:42.158658 output:
225 00:50:42.159888 rename /var/lib/lava/dispatcher/tmp/919379/extract-overlay-ramdisk-s79j2k9j/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot
226 00:50:42.160859 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 00:50:42.161580 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 00:50:42.162303 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 00:50:42.162924 No LXC device requested
230 00:50:42.163602 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:50:42.164436 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 00:50:42.165198 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:50:42.165772 Checking files for TFTP limit of 4294967296 bytes.
234 00:50:42.169300 end: 1 tftp-deploy (duration 00:00:41) [common]
235 00:50:42.170097 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:50:42.170815 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:50:42.171481 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:50:42.172203 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:50:42.172915 Using kernel file from prepare-kernel: 919379/tftp-deploy-b6f7syqn/kernel/uImage
240 00:50:42.173736 substitutions:
241 00:50:42.174287 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:50:42.174847 - {DTB_ADDR}: 0x01070000
243 00:50:42.175390 - {DTB}: 919379/tftp-deploy-b6f7syqn/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 00:50:42.175922 - {INITRD}: 919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot
245 00:50:42.176495 - {KERNEL_ADDR}: 0x01080000
246 00:50:42.177026 - {KERNEL}: 919379/tftp-deploy-b6f7syqn/kernel/uImage
247 00:50:42.177544 - {LAVA_MAC}: None
248 00:50:42.178124 - {PRESEED_CONFIG}: None
249 00:50:42.178645 - {PRESEED_LOCAL}: None
250 00:50:42.179158 - {RAMDISK_ADDR}: 0x08000000
251 00:50:42.179666 - {RAMDISK}: 919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot
252 00:50:42.180232 - {ROOT_PART}: None
253 00:50:42.180779 - {ROOT}: None
254 00:50:42.181306 - {SERVER_IP}: 192.168.6.2
255 00:50:42.181822 - {TEE_ADDR}: 0x83000000
256 00:50:42.182365 - {TEE}: None
257 00:50:42.182898 Parsed boot commands:
258 00:50:42.183401 - setenv autoload no
259 00:50:42.183934 - setenv initrd_high 0xffffffff
260 00:50:42.184490 - setenv fdt_high 0xffffffff
261 00:50:42.185000 - dhcp
262 00:50:42.185509 - setenv serverip 192.168.6.2
263 00:50:42.186016 - tftpboot 0x01080000 919379/tftp-deploy-b6f7syqn/kernel/uImage
264 00:50:42.186525 - tftpboot 0x08000000 919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot
265 00:50:42.187046 - tftpboot 0x01070000 919379/tftp-deploy-b6f7syqn/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 00:50:42.187570 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:50:42.187860 - bootm 0x01080000 0x08000000 0x01070000
268 00:50:42.188247 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:50:42.189310 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:50:42.189662 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 00:50:42.204065 Setting prompt string to ['lava-test: # ']
273 00:50:42.205970 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:50:42.206754 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:50:42.207468 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:50:42.208183 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:50:42.209620 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 00:50:42.248534 >> OK - accepted request
279 00:50:42.250866 Returned 0 in 0 seconds
280 00:50:42.352265 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:50:42.354309 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:50:42.355054 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:50:42.355688 Setting prompt string to ['Hit any key to stop autoboot']
285 00:50:42.356306 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:50:42.358384 Trying 192.168.56.21...
287 00:50:42.359013 Connected to conserv1.
288 00:50:42.359572 Escape character is '^]'.
289 00:50:42.360168
290 00:50:42.360745 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 00:50:42.361311
292 00:50:50.302807 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 00:50:50.303629 bl2_stage_init 0x01
294 00:50:50.304268 bl2_stage_init 0x81
295 00:50:50.308282 hw id: 0x0000 - pwm id 0x01
296 00:50:50.308881 bl2_stage_init 0xc1
297 00:50:50.313936 bl2_stage_init 0x02
298 00:50:50.314527
299 00:50:50.315091 L0:00000000
300 00:50:50.315631 L1:00000703
301 00:50:50.316201 L2:00008067
302 00:50:50.316741 L3:15000000
303 00:50:50.319805 S1:00000000
304 00:50:50.320409 B2:20282000
305 00:50:50.320965 B1:a0f83180
306 00:50:50.321500
307 00:50:50.322021 TE: 69668
308 00:50:50.322551
309 00:50:50.325267 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 00:50:50.325842
311 00:50:50.330986 Board ID = 1
312 00:50:50.331535 Set cpu clk to 24M
313 00:50:50.332088 Set clk81 to 24M
314 00:50:50.334541 Use GP1_pll as DSU clk.
315 00:50:50.335081 DSU clk: 1200 Mhz
316 00:50:50.340036 CPU clk: 1200 MHz
317 00:50:50.340584 Set clk81 to 166.6M
318 00:50:50.345516 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 00:50:50.346069 board id: 1
320 00:50:50.353854 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 00:50:50.365617 fw parse done
322 00:50:50.370823 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 00:50:50.414623 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 00:50:50.425704 PIEI prepare done
325 00:50:50.426290 fastboot data load
326 00:50:50.426834 fastboot data verify
327 00:50:50.431293 verify result: 266
328 00:50:50.436868 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 00:50:50.437431 LPDDR4 probe
330 00:50:50.437959 ddr clk to 1584MHz
331 00:50:50.444869 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 00:50:50.481798
333 00:50:50.482478 dmc_version 0001
334 00:50:50.488710 Check phy result
335 00:50:50.495626 INFO : End of CA training
336 00:50:50.496274 INFO : End of initialization
337 00:50:50.501258 INFO : Training has run successfully!
338 00:50:50.501849 Check phy result
339 00:50:50.506896 INFO : End of initialization
340 00:50:50.507487 INFO : End of read enable training
341 00:50:50.510173 INFO : End of fine write leveling
342 00:50:50.515587 INFO : End of Write leveling coarse delay
343 00:50:50.521191 INFO : Training has run successfully!
344 00:50:50.521774 Check phy result
345 00:50:50.522319 INFO : End of initialization
346 00:50:50.526851 INFO : End of read dq deskew training
347 00:50:50.532479 INFO : End of MPR read delay center optimization
348 00:50:50.533046 INFO : End of write delay center optimization
349 00:50:50.537991 INFO : End of read delay center optimization
350 00:50:50.543563 INFO : End of max read latency training
351 00:50:50.544148 INFO : Training has run successfully!
352 00:50:50.549166 1D training succeed
353 00:50:50.555220 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 00:50:50.602785 Check phy result
355 00:50:50.603415 INFO : End of initialization
356 00:50:50.630893 INFO : End of 2D read delay Voltage center optimization
357 00:50:50.654217 INFO : End of 2D read delay Voltage center optimization
358 00:50:50.710850 INFO : End of 2D write delay Voltage center optimization
359 00:50:50.765741 INFO : End of 2D write delay Voltage center optimization
360 00:50:50.771305 INFO : Training has run successfully!
361 00:50:50.771884
362 00:50:50.772473 channel==0
363 00:50:50.776906 RxClkDly_Margin_A0==88 ps 9
364 00:50:50.777462 TxDqDly_Margin_A0==98 ps 10
365 00:50:50.780250 RxClkDly_Margin_A1==69 ps 7
366 00:50:50.780800 TxDqDly_Margin_A1==88 ps 9
367 00:50:50.785762 TrainedVREFDQ_A0==74
368 00:50:50.786355 TrainedVREFDQ_A1==74
369 00:50:50.786918 VrefDac_Margin_A0==23
370 00:50:50.791344 DeviceVref_Margin_A0==40
371 00:50:50.791906 VrefDac_Margin_A1==23
372 00:50:50.796947 DeviceVref_Margin_A1==40
373 00:50:50.797410
374 00:50:50.797832
375 00:50:50.798243 channel==1
376 00:50:50.798648 RxClkDly_Margin_A0==78 ps 8
377 00:50:50.802664 TxDqDly_Margin_A0==98 ps 10
378 00:50:50.803106 RxClkDly_Margin_A1==78 ps 8
379 00:50:50.808239 TxDqDly_Margin_A1==88 ps 9
380 00:50:50.808680 TrainedVREFDQ_A0==78
381 00:50:50.809090 TrainedVREFDQ_A1==78
382 00:50:50.813747 VrefDac_Margin_A0==23
383 00:50:50.814178 DeviceVref_Margin_A0==36
384 00:50:50.819327 VrefDac_Margin_A1==22
385 00:50:50.819756 DeviceVref_Margin_A1==36
386 00:50:50.820211
387 00:50:50.824949 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 00:50:50.825385
389 00:50:50.852944 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000060
390 00:50:50.858573 2D training succeed
391 00:50:50.864156 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 00:50:50.864594 auto size-- 65535DDR cs0 size: 2048MB
393 00:50:50.869736 DDR cs1 size: 2048MB
394 00:50:50.870175 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 00:50:50.875307 cs0 DataBus test pass
396 00:50:50.875753 cs1 DataBus test pass
397 00:50:50.876217 cs0 AddrBus test pass
398 00:50:50.880929 cs1 AddrBus test pass
399 00:50:50.881365
400 00:50:50.881772 100bdlr_step_size ps== 471
401 00:50:50.882183 result report
402 00:50:50.886592 boot times 0Enable ddr reg access
403 00:50:50.894076 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 00:50:50.906992 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 00:50:51.567566 bl2z: ptr: 05129330, size: 00001e40
406 00:50:51.579880 0.0;M3 CHK:0;cm4_sp_mode 0
407 00:50:51.580461 MVN_1=0x00000000
408 00:50:51.580893 MVN_2=0x00000000
409 00:50:51.588041 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 00:50:51.588675 OPS=0x04
411 00:50:51.589111 ring efuse init
412 00:50:51.590879 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 00:50:51.599656 [0.017354 Inits done]
414 00:50:51.600305 secure task start!
415 00:50:51.600751 high task start!
416 00:50:51.601169 low task start!
417 00:50:51.601927 run into bl31
418 00:50:51.611372 NOTICE: BL31: v1.3(release):4fc40b1
419 00:50:51.617539 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 00:50:51.618001 NOTICE: BL31: G12A normal boot!
421 00:50:51.634054 NOTICE: BL31: BL33 decompress pass
422 00:50:51.638807 ERROR: Error initializing runtime service opteed_fast
423 00:50:52.853959 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 00:50:52.854551 bl2_stage_init 0x01
425 00:50:52.854995 bl2_stage_init 0x81
426 00:50:52.859589 hw id: 0x0000 - pwm id 0x01
427 00:50:52.860162 bl2_stage_init 0xc1
428 00:50:52.865179 bl2_stage_init 0x02
429 00:50:52.865699
430 00:50:52.866101 L0:00000000
431 00:50:52.866493 L1:00000703
432 00:50:52.866877 L2:00008067
433 00:50:52.867264 L3:15000000
434 00:50:52.870727 S1:00000000
435 00:50:52.871171 B2:20282000
436 00:50:52.871560 B1:a0f83180
437 00:50:52.871944
438 00:50:52.872371 TE: 70780
439 00:50:52.872761
440 00:50:52.876348 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 00:50:52.876809
442 00:50:52.881916 Board ID = 1
443 00:50:52.882346 Set cpu clk to 24M
444 00:50:52.882735 Set clk81 to 24M
445 00:50:52.887546 Use GP1_pll as DSU clk.
446 00:50:52.888024 DSU clk: 1200 Mhz
447 00:50:52.888424 CPU clk: 1200 MHz
448 00:50:52.893148 Set clk81 to 166.6M
449 00:50:52.898756 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 00:50:52.899189 board id: 1
451 00:50:52.904974 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 00:50:52.916649 fw parse done
453 00:50:52.921665 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 00:50:52.965200 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 00:50:52.976283 PIEI prepare done
456 00:50:52.976753 fastboot data load
457 00:50:52.977142 fastboot data verify
458 00:50:52.981889 verify result: 266
459 00:50:52.987385 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 00:50:52.987846 LPDDR4 probe
461 00:50:52.988285 ddr clk to 1584MHz
462 00:50:54.355763 Load ddrfw from SPI, src: 0x00018000, des: 0xff� SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 00:50:54.356216 bl2_stage_init 0x01
464 00:50:54.356443 bl2_stage_init 0x81
465 00:50:54.361317 hw id: 0x0000 - pwm id 0x01
466 00:50:54.361717 bl2_stage_init 0xc1
467 00:50:54.362042 bl2_stage_init 0x02
468 00:50:54.362353
469 00:50:54.366899 L0:00000000
470 00:50:54.367264 L1:00000703
471 00:50:54.367504 L2:00008067
472 00:50:54.367710 L3:15000000
473 00:50:54.367908 S1:00000000
474 00:50:54.372493 B2:20282000
475 00:50:54.372786 B1:a0f83180
476 00:50:54.372997
477 00:50:54.373211 TE: 70580
478 00:50:54.373417
479 00:50:54.378090 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 00:50:54.378459
481 00:50:54.383715 Board ID = 1
482 00:50:54.384106 Set cpu clk to 24M
483 00:50:54.384354 Set clk81 to 24M
484 00:50:54.389244 Use GP1_pll as DSU clk.
485 00:50:54.389524 DSU clk: 1200 Mhz
486 00:50:54.389736 CPU clk: 1200 MHz
487 00:50:54.389936 Set clk81 to 166.6M
488 00:50:54.400407 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 00:50:54.400791 board id: 1
490 00:50:54.406877 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 00:50:54.417739 fw parse done
492 00:50:54.423718 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 00:50:54.467001 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 00:50:54.478026 PIEI prepare done
495 00:50:54.478535 fastboot data load
496 00:50:54.479001 fastboot data verify
497 00:50:54.483600 verify result: 266
498 00:50:54.489213 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 00:50:54.489699 LPDDR4 probe
500 00:50:54.490153 ddr clk to 1584MHz
501 00:50:54.497166 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 00:50:54.534913
503 00:50:54.535397 dmc_version 0001
504 00:50:54.542062 Check phy result
505 00:50:54.548040 INFO : End of CA training
506 00:50:54.548517 INFO : End of initialization
507 00:50:54.553504 INFO : Training has run successfully!
508 00:50:54.553980 Check phy result
509 00:50:54.559148 INFO : End of initialization
510 00:50:54.559628 INFO : End of read enable training
511 00:50:54.564704 INFO : End of fine write leveling
512 00:50:54.570322 INFO : End of Write leveling coarse delay
513 00:50:54.570801 INFO : Training has run successfully!
514 00:50:54.571250 Check phy result
515 00:50:54.576009 INFO : End of initialization
516 00:50:54.576506 INFO : End of read dq deskew training
517 00:50:54.581522 INFO : End of MPR read delay center optimization
518 00:50:54.587115 INFO : End of write delay center optimization
519 00:50:54.592780 INFO : End of read delay center optimization
520 00:50:54.593259 INFO : End of max read latency training
521 00:50:54.598346 INFO : Training has run successfully!
522 00:50:54.598818 1D training succeed
523 00:50:54.606693 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 00:50:54.655844 Check phy result
525 00:50:54.656404 INFO : End of initialization
526 00:50:54.682174 INFO : End of 2D read delay Voltage center optimization
527 00:50:54.706367 INFO : End of 2D read delay Voltage center optimization
528 00:50:54.764119 INFO : End of 2D write delay Voltage center optimization
529 00:50:54.817849 INFO : End of 2D write delay Voltage center optimization
530 00:50:54.823457 INFO : Training has run successfully!
531 00:50:54.823968
532 00:50:54.824494 channel==0
533 00:50:54.829036 RxClkDly_Margin_A0==78 ps 8
534 00:50:54.829542 TxDqDly_Margin_A0==98 ps 10
535 00:50:54.834649 RxClkDly_Margin_A1==88 ps 9
536 00:50:54.835140 TxDqDly_Margin_A1==98 ps 10
537 00:50:54.835599 TrainedVREFDQ_A0==74
538 00:50:54.840216 TrainedVREFDQ_A1==74
539 00:50:54.840710 VrefDac_Margin_A0==24
540 00:50:54.841162 DeviceVref_Margin_A0==40
541 00:50:54.845828 VrefDac_Margin_A1==23
542 00:50:54.846328 DeviceVref_Margin_A1==40
543 00:50:54.846783
544 00:50:54.847233
545 00:50:54.851424 channel==1
546 00:50:54.851918 RxClkDly_Margin_A0==88 ps 9
547 00:50:54.852407 TxDqDly_Margin_A0==98 ps 10
548 00:50:54.857038 RxClkDly_Margin_A1==78 ps 8
549 00:50:54.857548 TxDqDly_Margin_A1==88 ps 9
550 00:50:54.862739 TrainedVREFDQ_A0==78
551 00:50:54.863233 TrainedVREFDQ_A1==78
552 00:50:54.863683 VrefDac_Margin_A0==22
553 00:50:54.868229 DeviceVref_Margin_A0==36
554 00:50:54.868726 VrefDac_Margin_A1==22
555 00:50:54.873856 DeviceVref_Margin_A1==36
556 00:50:54.874355
557 00:50:54.874834 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 00:50:54.875303
559 00:50:54.907442 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 00:50:54.908093 2D training succeed
561 00:50:54.913033 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 00:50:54.918587 auto size-- 65535DDR cs0 size: 2048MB
563 00:50:54.919094 DDR cs1 size: 2048MB
564 00:50:54.924204 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 00:50:54.924720 cs0 DataBus test pass
566 00:50:54.929801 cs1 DataBus test pass
567 00:50:54.930303 cs0 AddrBus test pass
568 00:50:54.930759 cs1 AddrBus test pass
569 00:50:54.931205
570 00:50:54.935418 100bdlr_step_size ps== 471
571 00:50:54.935931 result report
572 00:50:54.941045 boot times 0Enable ddr reg access
573 00:50:54.945342 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 00:50:54.959261 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 00:50:55.618644 bl2z: ptr: 05129330, size: 00001e40
576 00:50:55.626479 0.0;M3 CHK:0;cm4_sp_mode 0
577 00:50:55.627058 MVN_1=0x00000000
578 00:50:55.627531 MVN_2=0x00000000
579 00:50:55.637960 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 00:50:55.638528 OPS=0x04
581 00:50:55.639001 ring efuse init
582 00:50:55.643662 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 00:50:55.644261 [0.017354 Inits done]
584 00:50:55.644731 secure task start!
585 00:50:55.649763 high task start!
586 00:50:55.650304 low task start!
587 00:50:55.650760 run into bl31
588 00:50:55.659428 NOTICE: BL31: v1.3(release):4fc40b1
589 00:50:55.667372 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 00:50:55.668114 NOTICE: BL31: G12A normal boot!
591 00:50:55.682741 NOTICE: BL31: BL33 decompress pass
592 00:50:55.688446 ERROR: Error initializing runtime service opteed_fast
593 00:50:56.903108 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 00:50:56.903794 bl2_stage_init 0x01
595 00:50:56.904577 bl2_stage_init 0x81
596 00:50:56.908639 hw id: 0x0000 - pwm id 0x01
597 00:50:56.909206 bl2_stage_init 0xc1
598 00:50:56.914302 bl2_stage_init 0x02
599 00:50:56.914855
600 00:50:56.915336 L0:00000000
601 00:50:56.915805 L1:00000703
602 00:50:56.916325 L2:00008067
603 00:50:56.916792 L3:15000000
604 00:50:56.919727 S1:00000000
605 00:50:56.920326 B2:20282000
606 00:50:56.920807 B1:a0f83180
607 00:50:56.921280
608 00:50:56.921736 TE: 69856
609 00:50:56.922232
610 00:50:56.925383 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 00:50:56.925932
612 00:50:56.930933 Board ID = 1
613 00:50:56.931470 Set cpu clk to 24M
614 00:50:56.931942 Set clk81 to 24M
615 00:50:56.936570 Use GP1_pll as DSU clk.
616 00:50:56.937118 DSU clk: 1200 Mhz
617 00:50:56.937593 CPU clk: 1200 MHz
618 00:50:56.942290 Set clk81 to 166.6M
619 00:50:56.947758 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 00:50:56.948334 board id: 1
621 00:50:56.955036 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 00:50:56.965905 fw parse done
623 00:50:56.971798 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 00:50:57.014977 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 00:50:57.026114 PIEI prepare done
626 00:50:57.026661 fastboot data load
627 00:50:57.027130 fastboot data verify
628 00:50:57.031668 verify result: 266
629 00:50:57.037379 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 00:50:57.037923 LPDDR4 probe
631 00:50:57.038389 ddr clk to 1584MHz
632 00:50:57.045379 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 00:50:57.083156
634 00:50:57.083723 dmc_version 0001
635 00:50:57.090145 Check phy result
636 00:50:57.096686 INFO : End of CA training
637 00:50:57.097358 INFO : End of initialization
638 00:50:57.101789 INFO : Training has run successfully!
639 00:50:57.102468 Check phy result
640 00:50:57.107372 INFO : End of initialization
641 00:50:57.107807 INFO : End of read enable training
642 00:50:57.113018 INFO : End of fine write leveling
643 00:50:57.118546 INFO : End of Write leveling coarse delay
644 00:50:57.118972 INFO : Training has run successfully!
645 00:50:57.119195 Check phy result
646 00:50:57.124133 INFO : End of initialization
647 00:50:57.124541 INFO : End of read dq deskew training
648 00:50:57.129668 INFO : End of MPR read delay center optimization
649 00:50:57.135523 INFO : End of write delay center optimization
650 00:50:57.141001 INFO : End of read delay center optimization
651 00:50:57.141423 INFO : End of max read latency training
652 00:50:57.146545 INFO : Training has run successfully!
653 00:50:57.147148 1D training succeed
654 00:50:57.155687 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 00:50:57.204023 Check phy result
656 00:50:57.204451 INFO : End of initialization
657 00:50:57.231393 INFO : End of 2D read delay Voltage center optimization
658 00:50:57.255599 INFO : End of 2D read delay Voltage center optimization
659 00:50:57.312305 INFO : End of 2D write delay Voltage center optimization
660 00:50:57.366210 INFO : End of 2D write delay Voltage center optimization
661 00:50:57.371697 INFO : Training has run successfully!
662 00:50:57.372259
663 00:50:57.372752 channel==0
664 00:50:57.377401 RxClkDly_Margin_A0==88 ps 9
665 00:50:57.377904 TxDqDly_Margin_A0==98 ps 10
666 00:50:57.382909 RxClkDly_Margin_A1==88 ps 9
667 00:50:57.383401 TxDqDly_Margin_A1==98 ps 10
668 00:50:57.383865 TrainedVREFDQ_A0==74
669 00:50:57.388507 TrainedVREFDQ_A1==74
670 00:50:57.389009 VrefDac_Margin_A0==23
671 00:50:57.389464 DeviceVref_Margin_A0==40
672 00:50:57.394097 VrefDac_Margin_A1==23
673 00:50:57.394591 DeviceVref_Margin_A1==40
674 00:50:57.395045
675 00:50:57.395495
676 00:50:57.399670 channel==1
677 00:50:57.400213 RxClkDly_Margin_A0==78 ps 8
678 00:50:57.400679 TxDqDly_Margin_A0==98 ps 10
679 00:50:57.405347 RxClkDly_Margin_A1==78 ps 8
680 00:50:57.405842 TxDqDly_Margin_A1==88 ps 9
681 00:50:57.410851 TrainedVREFDQ_A0==78
682 00:50:57.411346 TrainedVREFDQ_A1==75
683 00:50:57.411804 VrefDac_Margin_A0==22
684 00:50:57.416455 DeviceVref_Margin_A0==36
685 00:50:57.416949 VrefDac_Margin_A1==20
686 00:50:57.422046 DeviceVref_Margin_A1==39
687 00:50:57.422535
688 00:50:57.422990 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 00:50:57.423438
690 00:50:57.455668 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
691 00:50:57.456223 2D training succeed
692 00:50:57.461368 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 00:50:57.466853 auto size-- 65535DDR cs0 size: 2048MB
694 00:50:57.467339 DDR cs1 size: 2048MB
695 00:50:57.472411 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 00:50:57.472900 cs0 DataBus test pass
697 00:50:57.478027 cs1 DataBus test pass
698 00:50:57.478525 cs0 AddrBus test pass
699 00:50:57.478982 cs1 AddrBus test pass
700 00:50:57.479425
701 00:50:57.483669 100bdlr_step_size ps== 471
702 00:50:57.484220 result report
703 00:50:57.489364 boot times 0Enable ddr reg access
704 00:50:57.494527 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 00:50:57.507511 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 00:50:58.167723 bl2z: ptr: 05129330, size: 00001e40
707 00:50:58.175485 0.0;M3 CHK:0;cm4_sp_mode 0
708 00:50:58.176089 MVN_1=0x00000000
709 00:50:58.176537 MVN_2=0x00000000
710 00:50:58.186893 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 00:50:58.187474 OPS=0x04
712 00:50:58.187915 ring efuse init
713 00:50:58.192435 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 00:50:58.192934 [0.017354 Inits done]
715 00:50:58.193366 secure task start!
716 00:50:58.199067 high task start!
717 00:50:58.199547 low task start!
718 00:50:58.199975 run into bl31
719 00:50:58.208562 NOTICE: BL31: v1.3(release):4fc40b1
720 00:50:58.216520 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 00:50:58.216997 NOTICE: BL31: G12A normal boot!
722 00:50:58.231977 NOTICE: BL31: BL33 decompress pass
723 00:50:58.237803 ERROR: Error initializing runtime service opteed_fast
724 00:50:59.032981
725 00:50:59.033608
726 00:50:59.038565 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 00:50:59.039072
728 00:50:59.041903 Model: Libre Computer AML-S905D3-CC Solitude
729 00:50:59.188957 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 00:50:59.204368 DRAM: 2 GiB (effective 3.8 GiB)
731 00:50:59.305297 Core: 406 devices, 33 uclasses, devicetree: separate
732 00:50:59.311179 WDT: Not starting watchdog@f0d0
733 00:50:59.336263 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 00:50:59.348608 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 00:50:59.353503 ** Bad device specification mmc 0 **
736 00:50:59.363623 Card did not respond to voltage select! : -110
737 00:50:59.371178 ** Bad device specification mmc 0 **
738 00:50:59.371675 Couldn't find partition mmc 0
739 00:50:59.379586 Card did not respond to voltage select! : -110
740 00:50:59.385057 ** Bad device specification mmc 0 **
741 00:50:59.385558 Couldn't find partition mmc 0
742 00:50:59.390067 Error: could not access storage.
743 00:50:59.686542 Net: eth0: ethernet@ff3f0000
744 00:50:59.687105 starting USB...
745 00:50:59.931264 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 00:50:59.931886 Starting the controller
747 00:50:59.937424 USB XHCI 1.10
748 00:51:01.492595 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 00:51:01.501017 scanning usb for storage devices... 0 Storage Device(s) found
751 00:51:01.552658 Hit any key to stop autoboot: 1
752 00:51:01.553590 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 00:51:01.554272 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 00:51:01.554811 Setting prompt string to ['=>']
755 00:51:01.555345 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 00:51:01.567036 0
757 00:51:01.568042 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 00:51:01.669351 => setenv autoload no
760 00:51:01.670023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
761 00:51:01.675347 setenv autoload no
763 00:51:01.776933 => setenv initrd_high 0xffffffff
764 00:51:01.777571 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
765 00:51:01.782345 setenv initrd_high 0xffffffff
767 00:51:01.884079 => setenv fdt_high 0xffffffff
768 00:51:01.884862 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 00:51:01.889457 setenv fdt_high 0xffffffff
771 00:51:01.991039 => dhcp
772 00:51:01.991857 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 00:51:01.996155 dhcp
774 00:51:03.001955 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 00:51:03.002588 Speed: 1000, full duplex
776 00:51:03.002997 BOOTP broadcast 1
777 00:51:03.010415 DHCP client bound to address 192.168.6.21 (8 ms)
779 00:51:03.111841 => setenv serverip 192.168.6.2
780 00:51:03.112626 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
781 00:51:03.117165 setenv serverip 192.168.6.2
783 00:51:03.218577 => tftpboot 0x01080000 919379/tftp-deploy-b6f7syqn/kernel/uImage
784 00:51:03.219287 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
785 00:51:03.226144 tftpboot 0x01080000 919379/tftp-deploy-b6f7syqn/kernel/uImage
786 00:51:03.226778 Speed: 1000, full duplex
787 00:51:03.227306 Using ethernet@ff3f0000 device
788 00:51:03.231644 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 00:51:03.237118 Filename '919379/tftp-deploy-b6f7syqn/kernel/uImage'.
790 00:51:03.240946 Load address: 0x1080000
791 00:51:05.352043 Loading: *################################### UDP wrong checksum 00000005 000075cd
792 00:51:06.187498 ############### 43.6 MiB
793 00:51:06.188142 14.8 MiB/s
794 00:51:06.188560 done
795 00:51:06.191824 Bytes transferred = 45713984 (2b98a40 hex)
797 00:51:06.293300 => tftpboot 0x08000000 919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot
798 00:51:06.294052 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 00:51:06.300721 tftpboot 0x08000000 919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot
800 00:51:06.301231 Speed: 1000, full duplex
801 00:51:06.301631 Using ethernet@ff3f0000 device
802 00:51:06.306187 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 00:51:06.315923 Filename '919379/tftp-deploy-b6f7syqn/ramdisk/ramdisk.cpio.gz.uboot'.
804 00:51:06.316428 Load address: 0x8000000
805 00:51:15.882401 Loading: *########################T ######################### UDP wrong checksum 0000000f 00002535
806 00:51:20.882988 T UDP wrong checksum 0000000f 00002535
807 00:51:28.447404 T UDP wrong checksum 000000ff 00005a77
808 00:51:28.461171 UDP wrong checksum 000000ff 0000f069
809 00:51:30.884555 UDP wrong checksum 0000000f 00002535
810 00:51:50.888942 T T T T T UDP wrong checksum 0000000f 00002535
811 00:52:05.892754 T T
812 00:52:05.893184 Retry count exceeded; starting again
814 00:52:05.894058 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
817 00:52:05.895012 end: 2.4 uboot-commands (duration 00:01:24) [common]
819 00:52:05.895720 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
821 00:52:05.896342 end: 2 uboot-action (duration 00:01:24) [common]
823 00:52:05.897182 Cleaning after the job
824 00:52:05.897491 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/ramdisk
825 00:52:05.898306 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/kernel
826 00:52:05.913326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/dtb
827 00:52:05.914116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919379/tftp-deploy-b6f7syqn/modules
828 00:52:05.930415 start: 4.1 power-off (timeout 00:00:30) [common]
829 00:52:05.931079 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
830 00:52:05.962117 >> OK - accepted request
831 00:52:05.964064 Returned 0 in 0 seconds
832 00:52:06.064836 end: 4.1 power-off (duration 00:00:00) [common]
834 00:52:06.065828 start: 4.2 read-feedback (timeout 00:10:00) [common]
835 00:52:06.066528 Listened to connection for namespace 'common' for up to 1s
836 00:52:07.066900 Finalising connection for namespace 'common'
837 00:52:07.067397 Disconnecting from shell: Finalise
838 00:52:07.067689 =>
839 00:52:07.168343 end: 4.2 read-feedback (duration 00:00:01) [common]
840 00:52:07.168796 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919379
841 00:52:07.777492 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919379
842 00:52:07.778346 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.