Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:38:22.696580 lava-dispatcher, installed at version: 2024.01
2 01:38:22.697351 start: 0 validate
3 01:38:22.697818 Start time: 2024-11-01 01:38:22.697789+00:00 (UTC)
4 01:38:22.698342 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:38:22.698880 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:38:22.742112 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:38:22.742655 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:38:22.773135 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:38:22.774047 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:38:22.805183 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:38:22.805688 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:38:22.835848 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:38:22.836350 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:38:22.878114 validate duration: 0.18
16 01:38:22.879557 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:38:22.880167 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:38:22.880744 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:38:22.881682 Not decompressing ramdisk as can be used compressed.
20 01:38:22.882429 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:38:22.882928 saving as /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/ramdisk/initrd.cpio.gz
22 01:38:22.883429 total size: 5628169 (5 MB)
23 01:38:22.922736 progress 0 % (0 MB)
24 01:38:22.930602 progress 5 % (0 MB)
25 01:38:22.938621 progress 10 % (0 MB)
26 01:38:22.942970 progress 15 % (0 MB)
27 01:38:22.947060 progress 20 % (1 MB)
28 01:38:22.950714 progress 25 % (1 MB)
29 01:38:22.954775 progress 30 % (1 MB)
30 01:38:22.960095 progress 35 % (1 MB)
31 01:38:22.964445 progress 40 % (2 MB)
32 01:38:22.969264 progress 45 % (2 MB)
33 01:38:22.973502 progress 50 % (2 MB)
34 01:38:22.978308 progress 55 % (2 MB)
35 01:38:22.983067 progress 60 % (3 MB)
36 01:38:22.987309 progress 65 % (3 MB)
37 01:38:22.992132 progress 70 % (3 MB)
38 01:38:22.996402 progress 75 % (4 MB)
39 01:38:23.001141 progress 80 % (4 MB)
40 01:38:23.005428 progress 85 % (4 MB)
41 01:38:23.010033 progress 90 % (4 MB)
42 01:38:23.014375 progress 95 % (5 MB)
43 01:38:23.018267 progress 100 % (5 MB)
44 01:38:23.019030 5 MB downloaded in 0.14 s (39.58 MB/s)
45 01:38:23.019680 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:38:23.020783 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:38:23.021141 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:38:23.021469 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:38:23.022032 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/kernel/Image
51 01:38:23.022336 saving as /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/kernel/Image
52 01:38:23.022588 total size: 45713920 (43 MB)
53 01:38:23.022839 No compression specified
54 01:38:23.058225 progress 0 % (0 MB)
55 01:38:23.086524 progress 5 % (2 MB)
56 01:38:23.114594 progress 10 % (4 MB)
57 01:38:23.142705 progress 15 % (6 MB)
58 01:38:23.171163 progress 20 % (8 MB)
59 01:38:23.198892 progress 25 % (10 MB)
60 01:38:23.227008 progress 30 % (13 MB)
61 01:38:23.254876 progress 35 % (15 MB)
62 01:38:23.283042 progress 40 % (17 MB)
63 01:38:23.310874 progress 45 % (19 MB)
64 01:38:23.338851 progress 50 % (21 MB)
65 01:38:23.367224 progress 55 % (24 MB)
66 01:38:23.395529 progress 60 % (26 MB)
67 01:38:23.423039 progress 65 % (28 MB)
68 01:38:23.451239 progress 70 % (30 MB)
69 01:38:23.479616 progress 75 % (32 MB)
70 01:38:23.507834 progress 80 % (34 MB)
71 01:38:23.537934 progress 85 % (37 MB)
72 01:38:23.566242 progress 90 % (39 MB)
73 01:38:23.594462 progress 95 % (41 MB)
74 01:38:23.621907 progress 100 % (43 MB)
75 01:38:23.622428 43 MB downloaded in 0.60 s (72.68 MB/s)
76 01:38:23.622924 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:38:23.623759 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:38:23.624057 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:38:23.624332 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:38:23.624811 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:38:23.625096 saving as /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:38:23.625307 total size: 54703 (0 MB)
84 01:38:23.625513 No compression specified
85 01:38:23.664609 progress 59 % (0 MB)
86 01:38:23.665474 progress 100 % (0 MB)
87 01:38:23.666038 0 MB downloaded in 0.04 s (1.28 MB/s)
88 01:38:23.666530 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:38:23.667359 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:38:23.667629 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:38:23.667891 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:38:23.668388 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:38:23.668649 saving as /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/nfsrootfs/full.rootfs.tar
95 01:38:23.668855 total size: 120894716 (115 MB)
96 01:38:23.669065 Using unxz to decompress xz
97 01:38:23.703850 progress 0 % (0 MB)
98 01:38:24.494856 progress 5 % (5 MB)
99 01:38:25.333252 progress 10 % (11 MB)
100 01:38:26.127690 progress 15 % (17 MB)
101 01:38:26.866108 progress 20 % (23 MB)
102 01:38:27.457291 progress 25 % (28 MB)
103 01:38:28.312303 progress 30 % (34 MB)
104 01:38:29.108092 progress 35 % (40 MB)
105 01:38:29.452245 progress 40 % (46 MB)
106 01:38:29.825618 progress 45 % (51 MB)
107 01:38:30.551003 progress 50 % (57 MB)
108 01:38:31.451845 progress 55 % (63 MB)
109 01:38:32.237363 progress 60 % (69 MB)
110 01:38:32.995167 progress 65 % (74 MB)
111 01:38:33.779199 progress 70 % (80 MB)
112 01:38:34.596704 progress 75 % (86 MB)
113 01:38:35.382177 progress 80 % (92 MB)
114 01:38:36.143457 progress 85 % (98 MB)
115 01:38:37.002354 progress 90 % (103 MB)
116 01:38:37.786124 progress 95 % (109 MB)
117 01:38:38.702015 progress 100 % (115 MB)
118 01:38:38.715202 115 MB downloaded in 15.05 s (7.66 MB/s)
119 01:38:38.716174 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:38:38.717915 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:38:38.718473 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:38:38.719029 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:38:38.720180 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/modules.tar.xz
125 01:38:38.720706 saving as /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/modules/modules.tar
126 01:38:38.721158 total size: 11592552 (11 MB)
127 01:38:38.721612 Using unxz to decompress xz
128 01:38:38.763036 progress 0 % (0 MB)
129 01:38:38.843477 progress 5 % (0 MB)
130 01:38:38.927591 progress 10 % (1 MB)
131 01:38:39.009995 progress 15 % (1 MB)
132 01:38:39.085676 progress 20 % (2 MB)
133 01:38:39.161521 progress 25 % (2 MB)
134 01:38:39.240319 progress 30 % (3 MB)
135 01:38:39.312194 progress 35 % (3 MB)
136 01:38:39.390530 progress 40 % (4 MB)
137 01:38:39.474465 progress 45 % (5 MB)
138 01:38:39.549517 progress 50 % (5 MB)
139 01:38:39.634247 progress 55 % (6 MB)
140 01:38:39.714117 progress 60 % (6 MB)
141 01:38:39.792483 progress 65 % (7 MB)
142 01:38:39.871684 progress 70 % (7 MB)
143 01:38:39.952116 progress 75 % (8 MB)
144 01:38:40.033425 progress 80 % (8 MB)
145 01:38:40.108296 progress 85 % (9 MB)
146 01:38:40.179874 progress 90 % (9 MB)
147 01:38:40.278753 progress 95 % (10 MB)
148 01:38:40.370227 progress 100 % (11 MB)
149 01:38:40.384478 11 MB downloaded in 1.66 s (6.65 MB/s)
150 01:38:40.385401 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:38:40.387564 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:38:40.388321 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 01:38:40.389013 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 01:38:57.738389 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/919431/extract-nfsrootfs-djv4um6u
156 01:38:57.739007 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 01:38:57.739333 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 01:38:57.740042 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h
159 01:38:57.740531 makedir: /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin
160 01:38:57.740926 makedir: /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/tests
161 01:38:57.741294 makedir: /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/results
162 01:38:57.741662 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-add-keys
163 01:38:57.742203 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-add-sources
164 01:38:57.742729 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-background-process-start
165 01:38:57.743290 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-background-process-stop
166 01:38:57.743809 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-common-functions
167 01:38:57.744339 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-echo-ipv4
168 01:38:57.744817 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-install-packages
169 01:38:57.745286 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-installed-packages
170 01:38:57.745751 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-os-build
171 01:38:57.746219 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-probe-channel
172 01:38:57.746684 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-probe-ip
173 01:38:57.747169 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-target-ip
174 01:38:57.747651 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-target-mac
175 01:38:57.748139 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-target-storage
176 01:38:57.748624 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-case
177 01:38:57.749098 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-event
178 01:38:57.749646 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-feedback
179 01:38:57.750129 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-raise
180 01:38:57.750599 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-reference
181 01:38:57.751088 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-runner
182 01:38:57.751579 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-set
183 01:38:57.752070 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-test-shell
184 01:38:57.752570 Updating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-add-keys (debian)
185 01:38:57.753094 Updating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-add-sources (debian)
186 01:38:57.753585 Updating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-install-packages (debian)
187 01:38:57.754072 Updating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-installed-packages (debian)
188 01:38:57.754553 Updating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/bin/lava-os-build (debian)
189 01:38:57.754978 Creating /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/environment
190 01:38:57.755337 LAVA metadata
191 01:38:57.755590 - LAVA_JOB_ID=919431
192 01:38:57.755802 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:38:57.756203 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 01:38:57.757144 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:38:57.757445 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 01:38:57.757649 skipped lava-vland-overlay
197 01:38:57.757886 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:38:57.758135 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 01:38:57.758357 skipped lava-multinode-overlay
200 01:38:57.758628 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:38:57.758880 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 01:38:57.759125 Loading test definitions
203 01:38:57.759397 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 01:38:57.759612 Using /lava-919431 at stage 0
205 01:38:57.760721 uuid=919431_1.6.2.4.1 testdef=None
206 01:38:57.761021 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:38:57.761279 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 01:38:57.762785 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:38:57.763556 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 01:38:57.765456 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:38:57.766264 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 01:38:57.768077 runner path: /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/0/tests/0_timesync-off test_uuid 919431_1.6.2.4.1
215 01:38:57.768642 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:38:57.769449 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 01:38:57.769668 Using /lava-919431 at stage 0
219 01:38:57.770011 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:38:57.770293 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/0/tests/1_kselftest-alsa'
221 01:39:01.294268 Running '/usr/bin/git checkout kernelci.org
222 01:39:01.529574 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 01:39:01.531019 uuid=919431_1.6.2.4.5 testdef=None
224 01:39:01.531360 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:39:01.532127 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 01:39:01.534957 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:39:01.535770 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 01:39:01.539456 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:39:01.540333 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 01:39:01.543875 runner path: /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/0/tests/1_kselftest-alsa test_uuid 919431_1.6.2.4.5
234 01:39:01.544178 BOARD='meson-g12b-a311d-libretech-cc'
235 01:39:01.544383 BRANCH='mainline'
236 01:39:01.544578 SKIPFILE='/dev/null'
237 01:39:01.544774 SKIP_INSTALL='True'
238 01:39:01.544967 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 01:39:01.545164 TST_CASENAME=''
240 01:39:01.545357 TST_CMDFILES='alsa'
241 01:39:01.545878 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:39:01.546657 Creating lava-test-runner.conf files
244 01:39:01.546859 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919431/lava-overlay-0fkjer9h/lava-919431/0 for stage 0
245 01:39:01.547201 - 0_timesync-off
246 01:39:01.547435 - 1_kselftest-alsa
247 01:39:01.547757 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:39:01.548050 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 01:39:24.828375 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 01:39:24.828796 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 01:39:24.829060 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:39:24.829329 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 01:39:24.829591 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 01:39:25.440722 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:39:25.441197 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 01:39:25.441447 extracting modules file /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919431/extract-nfsrootfs-djv4um6u
257 01:39:26.969939 extracting modules file /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919431/extract-overlay-ramdisk-1xlpl7kz/ramdisk
258 01:39:28.354835 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:39:28.355316 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 01:39:28.355593 [common] Applying overlay to NFS
261 01:39:28.355808 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919431/compress-overlay-nzggy1ph/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919431/extract-nfsrootfs-djv4um6u
262 01:39:31.063875 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:39:31.064378 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 01:39:31.064653 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 01:39:31.064883 Converting downloaded kernel to a uImage
266 01:39:31.065193 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/kernel/Image /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/kernel/uImage
267 01:39:31.639402 output: Image Name:
268 01:39:31.639824 output: Created: Fri Nov 1 01:39:31 2024
269 01:39:31.640085 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:39:31.640306 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 01:39:31.640515 output: Load Address: 01080000
272 01:39:31.640722 output: Entry Point: 01080000
273 01:39:31.640923 output:
274 01:39:31.641262 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 01:39:31.641543 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 01:39:31.641825 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 01:39:31.642092 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:39:31.642364 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 01:39:31.642632 Building ramdisk /var/lib/lava/dispatcher/tmp/919431/extract-overlay-ramdisk-1xlpl7kz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919431/extract-overlay-ramdisk-1xlpl7kz/ramdisk
280 01:39:33.795280 >> 166820 blocks
281 01:39:41.655161 Adding RAMdisk u-boot header.
282 01:39:41.655841 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919431/extract-overlay-ramdisk-1xlpl7kz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919431/extract-overlay-ramdisk-1xlpl7kz/ramdisk.cpio.gz.uboot
283 01:39:41.900678 output: Image Name:
284 01:39:41.901108 output: Created: Fri Nov 1 01:39:41 2024
285 01:39:41.901594 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:39:41.902010 output: Data Size: 23435013 Bytes = 22885.75 KiB = 22.35 MiB
287 01:39:41.902437 output: Load Address: 00000000
288 01:39:41.902841 output: Entry Point: 00000000
289 01:39:41.903242 output:
290 01:39:41.904250 rename /var/lib/lava/dispatcher/tmp/919431/extract-overlay-ramdisk-1xlpl7kz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot
291 01:39:41.904971 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 01:39:41.905532 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 01:39:41.906065 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 01:39:41.906532 No LXC device requested
295 01:39:41.907043 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:39:41.907563 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 01:39:41.908101 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:39:41.908529 Checking files for TFTP limit of 4294967296 bytes.
299 01:39:41.911170 end: 1 tftp-deploy (duration 00:01:19) [common]
300 01:39:41.911745 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:39:41.912313 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:39:41.912823 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:39:41.913335 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:39:41.913867 Using kernel file from prepare-kernel: 919431/tftp-deploy-v766ve5i/kernel/uImage
305 01:39:41.914501 substitutions:
306 01:39:41.914914 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:39:41.915317 - {DTB_ADDR}: 0x01070000
308 01:39:41.915721 - {DTB}: 919431/tftp-deploy-v766ve5i/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:39:41.916172 - {INITRD}: 919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot
310 01:39:41.916579 - {KERNEL_ADDR}: 0x01080000
311 01:39:41.916976 - {KERNEL}: 919431/tftp-deploy-v766ve5i/kernel/uImage
312 01:39:41.917369 - {LAVA_MAC}: None
313 01:39:41.917832 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/919431/extract-nfsrootfs-djv4um6u
314 01:39:41.918238 - {NFS_SERVER_IP}: 192.168.6.2
315 01:39:41.918627 - {PRESEED_CONFIG}: None
316 01:39:41.919021 - {PRESEED_LOCAL}: None
317 01:39:41.919410 - {RAMDISK_ADDR}: 0x08000000
318 01:39:41.919799 - {RAMDISK}: 919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot
319 01:39:41.920235 - {ROOT_PART}: None
320 01:39:41.920635 - {ROOT}: None
321 01:39:41.921027 - {SERVER_IP}: 192.168.6.2
322 01:39:41.921415 - {TEE_ADDR}: 0x83000000
323 01:39:41.921801 - {TEE}: None
324 01:39:41.922187 Parsed boot commands:
325 01:39:41.922562 - setenv autoload no
326 01:39:41.922946 - setenv initrd_high 0xffffffff
327 01:39:41.923329 - setenv fdt_high 0xffffffff
328 01:39:41.923709 - dhcp
329 01:39:41.924124 - setenv serverip 192.168.6.2
330 01:39:41.924520 - tftpboot 0x01080000 919431/tftp-deploy-v766ve5i/kernel/uImage
331 01:39:41.924912 - tftpboot 0x08000000 919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot
332 01:39:41.925302 - tftpboot 0x01070000 919431/tftp-deploy-v766ve5i/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:39:41.925692 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919431/extract-nfsrootfs-djv4um6u,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:39:41.926091 - bootm 0x01080000 0x08000000 0x01070000
335 01:39:41.926588 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:39:41.928098 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:39:41.928527 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:39:41.943165 Setting prompt string to ['lava-test: # ']
340 01:39:41.944699 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:39:41.945334 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:39:41.946193 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:39:41.946823 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:39:41.947974 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:39:41.984949 >> OK - accepted request
346 01:39:41.987136 Returned 0 in 0 seconds
347 01:39:42.088070 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:39:42.089674 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:39:42.090252 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:39:42.090767 Setting prompt string to ['Hit any key to stop autoboot']
352 01:39:42.091221 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:39:42.092793 Trying 192.168.56.21...
354 01:39:42.093277 Connected to conserv1.
355 01:39:42.093704 Escape character is '^]'.
356 01:39:42.094124
357 01:39:42.094546 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 01:39:42.094969
359 01:39:53.284990 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:39:53.285561 bl2_stage_init 0x01
361 01:39:53.285982 bl2_stage_init 0x81
362 01:39:53.290631 hw id: 0x0000 - pwm id 0x01
363 01:39:53.291119 bl2_stage_init 0xc1
364 01:39:53.291525 bl2_stage_init 0x02
365 01:39:53.291907
366 01:39:53.296170 L0:00000000
367 01:39:53.296635 L1:20000703
368 01:39:53.297040 L2:00008067
369 01:39:53.297442 L3:14000000
370 01:39:53.299107 B2:00402000
371 01:39:53.299539 B1:e0f83180
372 01:39:53.299943
373 01:39:53.300367 TE: 58124
374 01:39:53.300755
375 01:39:53.310306 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:39:53.310731
377 01:39:53.311120 Board ID = 1
378 01:39:53.311499 Set A53 clk to 24M
379 01:39:53.311879 Set A73 clk to 24M
380 01:39:53.315812 Set clk81 to 24M
381 01:39:53.316253 A53 clk: 1200 MHz
382 01:39:53.316639 A73 clk: 1200 MHz
383 01:39:53.319377 CLK81: 166.6M
384 01:39:53.319783 smccc: 00012a92
385 01:39:53.324855 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:39:53.330515 board id: 1
387 01:39:53.335697 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:39:53.346265 fw parse done
389 01:39:53.352314 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:39:53.394754 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:39:53.405763 PIEI prepare done
392 01:39:53.406168 fastboot data load
393 01:39:53.406550 fastboot data verify
394 01:39:53.411355 verify result: 266
395 01:39:53.416896 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:39:53.417312 LPDDR4 probe
397 01:39:53.417695 ddr clk to 1584MHz
398 01:39:53.424897 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:39:53.462145
400 01:39:53.462560 dmc_version 0001
401 01:39:53.468821 Check phy result
402 01:39:53.474709 INFO : End of CA training
403 01:39:53.475119 INFO : End of initialization
404 01:39:53.480389 INFO : Training has run successfully!
405 01:39:53.480799 Check phy result
406 01:39:53.485883 INFO : End of initialization
407 01:39:53.486290 INFO : End of read enable training
408 01:39:53.491481 INFO : End of fine write leveling
409 01:39:53.497112 INFO : End of Write leveling coarse delay
410 01:39:53.497519 INFO : Training has run successfully!
411 01:39:53.497910 Check phy result
412 01:39:53.502695 INFO : End of initialization
413 01:39:53.503107 INFO : End of read dq deskew training
414 01:39:53.508355 INFO : End of MPR read delay center optimization
415 01:39:53.513876 INFO : End of write delay center optimization
416 01:39:53.519483 INFO : End of read delay center optimization
417 01:39:53.519892 INFO : End of max read latency training
418 01:39:53.525083 INFO : Training has run successfully!
419 01:39:53.525493 1D training succeed
420 01:39:53.534425 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:39:53.581953 Check phy result
422 01:39:53.582415 INFO : End of initialization
423 01:39:53.603583 INFO : End of 2D read delay Voltage center optimization
424 01:39:53.623833 INFO : End of 2D read delay Voltage center optimization
425 01:39:53.675873 INFO : End of 2D write delay Voltage center optimization
426 01:39:53.725291 INFO : End of 2D write delay Voltage center optimization
427 01:39:53.730845 INFO : Training has run successfully!
428 01:39:53.731324
429 01:39:53.731739 channel==0
430 01:39:53.736526 RxClkDly_Margin_A0==88 ps 9
431 01:39:53.736953 TxDqDly_Margin_A0==108 ps 11
432 01:39:53.742051 RxClkDly_Margin_A1==88 ps 9
433 01:39:53.742509 TxDqDly_Margin_A1==98 ps 10
434 01:39:53.742905 TrainedVREFDQ_A0==74
435 01:39:53.747607 TrainedVREFDQ_A1==74
436 01:39:53.748059 VrefDac_Margin_A0==25
437 01:39:53.753203 DeviceVref_Margin_A0==40
438 01:39:53.753621 VrefDac_Margin_A1==25
439 01:39:53.754010 DeviceVref_Margin_A1==40
440 01:39:53.754396
441 01:39:53.754785
442 01:39:53.758812 channel==1
443 01:39:53.759224 RxClkDly_Margin_A0==98 ps 10
444 01:39:53.759612 TxDqDly_Margin_A0==88 ps 9
445 01:39:53.764504 RxClkDly_Margin_A1==98 ps 10
446 01:39:53.764926 TxDqDly_Margin_A1==88 ps 9
447 01:39:53.769991 TrainedVREFDQ_A0==76
448 01:39:53.770406 TrainedVREFDQ_A1==77
449 01:39:53.770794 VrefDac_Margin_A0==22
450 01:39:53.775622 DeviceVref_Margin_A0==38
451 01:39:53.776061 VrefDac_Margin_A1==22
452 01:39:53.781245 DeviceVref_Margin_A1==37
453 01:39:53.781661
454 01:39:53.782054 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:39:53.786812
456 01:39:53.814787 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 01:39:53.815289 2D training succeed
458 01:39:53.820405 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:39:53.826042 auto size-- 65535DDR cs0 size: 2048MB
460 01:39:53.826492 DDR cs1 size: 2048MB
461 01:39:53.831613 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:39:53.832064 cs0 DataBus test pass
463 01:39:53.837261 cs1 DataBus test pass
464 01:39:53.837672 cs0 AddrBus test pass
465 01:39:53.838059 cs1 AddrBus test pass
466 01:39:53.838442
467 01:39:53.842808 100bdlr_step_size ps== 420
468 01:39:53.843232 result report
469 01:39:53.848408 boot times 0Enable ddr reg access
470 01:39:53.853870 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:39:53.867311 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:39:54.440311 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:39:54.440772 MVN_1=0x00000000
474 01:39:54.445817 MVN_2=0x00000000
475 01:39:54.451562 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:39:54.452053 OPS=0x10
477 01:39:54.452475 ring efuse init
478 01:39:54.452882 chipver efuse init
479 01:39:54.457174 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:39:54.462761 [0.018961 Inits done]
481 01:39:54.463185 secure task start!
482 01:39:54.463586 high task start!
483 01:39:54.467385 low task start!
484 01:39:54.467811 run into bl31
485 01:39:54.473965 NOTICE: BL31: v1.3(release):4fc40b1
486 01:39:54.481806 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:39:54.482238 NOTICE: BL31: G12A normal boot!
488 01:39:54.507149 NOTICE: BL31: BL33 decompress pass
489 01:39:54.512834 ERROR: Error initializing runtime service opteed_fast
490 01:39:55.745721
491 01:39:55.746228
492 01:39:55.754144 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:39:55.754582
494 01:39:55.754993 Model: Libre Computer AML-A311D-CC Alta
495 01:39:55.962541 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:39:55.985908 DRAM: 2 GiB (effective 3.8 GiB)
497 01:39:56.128985 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:39:56.134865 WDT: Not starting watchdog@f0d0
499 01:39:56.167105 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:39:56.179490 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:39:56.184498 ** Bad device specification mmc 0 **
502 01:39:56.194803 Card did not respond to voltage select! : -110
503 01:39:56.202466 ** Bad device specification mmc 0 **
504 01:39:56.202896 Couldn't find partition mmc 0
505 01:39:56.210802 Card did not respond to voltage select! : -110
506 01:39:56.216312 ** Bad device specification mmc 0 **
507 01:39:56.216760 Couldn't find partition mmc 0
508 01:39:56.221560 Error: could not access storage.
509 01:39:57.485273 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:39:57.485825 bl2_stage_init 0x01
511 01:39:57.486258 bl2_stage_init 0x81
512 01:39:57.490872 hw id: 0x0000 - pwm id 0x01
513 01:39:57.491321 bl2_stage_init 0xc1
514 01:39:57.491784 bl2_stage_init 0x02
515 01:39:57.492296
516 01:39:57.496485 L0:00000000
517 01:39:57.496930 L1:20000703
518 01:39:57.497337 L2:00008067
519 01:39:57.497737 L3:14000000
520 01:39:57.502055 B2:00402000
521 01:39:57.502493 B1:e0f83180
522 01:39:57.502897
523 01:39:57.503297 TE: 58124
524 01:39:57.503695
525 01:39:57.507667 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:39:57.508144
527 01:39:57.508555 Board ID = 1
528 01:39:57.513264 Set A53 clk to 24M
529 01:39:57.513704 Set A73 clk to 24M
530 01:39:57.514107 Set clk81 to 24M
531 01:39:57.518869 A53 clk: 1200 MHz
532 01:39:57.519304 A73 clk: 1200 MHz
533 01:39:57.519703 CLK81: 166.6M
534 01:39:57.520138 smccc: 00012a92
535 01:39:57.524446 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:39:57.530040 board id: 1
537 01:39:57.535925 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:39:57.546580 fw parse done
539 01:39:57.552570 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:39:57.595250 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:39:57.606086 PIEI prepare done
542 01:39:57.606540 fastboot data load
543 01:39:57.606950 fastboot data verify
544 01:39:57.611795 verify result: 266
545 01:39:57.617376 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:39:57.617842 LPDDR4 probe
547 01:39:57.618249 ddr clk to 1584MHz
548 01:39:57.625356 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:39:57.662600
550 01:39:57.663061 dmc_version 0001
551 01:39:57.669360 Check phy result
552 01:39:57.675193 INFO : End of CA training
553 01:39:57.675652 INFO : End of initialization
554 01:39:57.680775 INFO : Training has run successfully!
555 01:39:57.681232 Check phy result
556 01:39:57.686383 INFO : End of initialization
557 01:39:57.686838 INFO : End of read enable training
558 01:39:57.692024 INFO : End of fine write leveling
559 01:39:57.697591 INFO : End of Write leveling coarse delay
560 01:39:57.698061 INFO : Training has run successfully!
561 01:39:57.698470 Check phy result
562 01:39:57.703198 INFO : End of initialization
563 01:39:57.703652 INFO : End of read dq deskew training
564 01:39:57.708780 INFO : End of MPR read delay center optimization
565 01:39:57.714387 INFO : End of write delay center optimization
566 01:39:57.720032 INFO : End of read delay center optimization
567 01:39:57.720492 INFO : End of max read latency training
568 01:39:57.725592 INFO : Training has run successfully!
569 01:39:57.726045 1D training succeed
570 01:39:57.734727 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:39:57.782443 Check phy result
572 01:39:57.782980 INFO : End of initialization
573 01:39:57.804265 INFO : End of 2D read delay Voltage center optimization
574 01:39:57.824405 INFO : End of 2D read delay Voltage center optimization
575 01:39:57.876463 INFO : End of 2D write delay Voltage center optimization
576 01:39:57.925820 INFO : End of 2D write delay Voltage center optimization
577 01:39:57.931321 INFO : Training has run successfully!
578 01:39:57.931865
579 01:39:57.932427 channel==0
580 01:39:57.936933 RxClkDly_Margin_A0==88 ps 9
581 01:39:57.937473 TxDqDly_Margin_A0==98 ps 10
582 01:39:57.940290 RxClkDly_Margin_A1==88 ps 9
583 01:39:57.940822 TxDqDly_Margin_A1==98 ps 10
584 01:39:57.945744 TrainedVREFDQ_A0==74
585 01:39:57.946269 TrainedVREFDQ_A1==75
586 01:39:57.951366 VrefDac_Margin_A0==25
587 01:39:57.951890 DeviceVref_Margin_A0==40
588 01:39:57.952389 VrefDac_Margin_A1==25
589 01:39:57.956952 DeviceVref_Margin_A1==39
590 01:39:57.957469
591 01:39:57.957931
592 01:39:57.958383 channel==1
593 01:39:57.958821 RxClkDly_Margin_A0==98 ps 10
594 01:39:57.962555 TxDqDly_Margin_A0==98 ps 10
595 01:39:57.963090 RxClkDly_Margin_A1==88 ps 9
596 01:39:57.968260 TxDqDly_Margin_A1==88 ps 9
597 01:39:57.968790 TrainedVREFDQ_A0==77
598 01:39:57.969246 TrainedVREFDQ_A1==77
599 01:39:57.973755 VrefDac_Margin_A0==22
600 01:39:57.974276 DeviceVref_Margin_A0==37
601 01:39:57.979364 VrefDac_Margin_A1==24
602 01:39:57.979881 DeviceVref_Margin_A1==37
603 01:39:57.980372
604 01:39:57.984968 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:39:57.985498
606 01:39:58.012881 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 01:39:58.018555 2D training succeed
608 01:39:58.024259 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:39:58.024798 auto size-- 65535DDR cs0 size: 2048MB
610 01:39:58.029766 DDR cs1 size: 2048MB
611 01:39:58.030314 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:39:58.035354 cs0 DataBus test pass
613 01:39:58.035889 cs1 DataBus test pass
614 01:39:58.036412 cs0 AddrBus test pass
615 01:39:58.040992 cs1 AddrBus test pass
616 01:39:58.041517
617 01:39:58.041972 100bdlr_step_size ps== 420
618 01:39:58.042422 result report
619 01:39:58.046555 boot times 0Enable ddr reg access
620 01:39:58.054318 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:39:58.067698 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:39:58.641446 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:39:58.642007 MVN_1=0x00000000
624 01:39:58.647134 MVN_2=0x00000000
625 01:39:58.652931 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:39:58.653486 OPS=0x10
627 01:39:58.653977 ring efuse init
628 01:39:58.654447 chipver efuse init
629 01:39:58.661023 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:39:58.661595 [0.018961 Inits done]
631 01:39:58.662040 secure task start!
632 01:39:58.668627 high task start!
633 01:39:58.669148 low task start!
634 01:39:58.669586 run into bl31
635 01:39:58.675122 NOTICE: BL31: v1.3(release):4fc40b1
636 01:39:58.683036 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:39:58.683560 NOTICE: BL31: G12A normal boot!
638 01:39:58.708368 NOTICE: BL31: BL33 decompress pass
639 01:39:58.714112 ERROR: Error initializing runtime service opteed_fast
640 01:39:59.946941
641 01:39:59.947505
642 01:39:59.955444 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:39:59.955971
644 01:39:59.956486 Model: Libre Computer AML-A311D-CC Alta
645 01:40:00.163711 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:40:00.187177 DRAM: 2 GiB (effective 3.8 GiB)
647 01:40:00.330109 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:40:00.336146 WDT: Not starting watchdog@f0d0
649 01:40:00.368259 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:40:00.380775 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:40:00.385716 ** Bad device specification mmc 0 **
652 01:40:00.396109 Card did not respond to voltage select! : -110
653 01:40:00.403714 ** Bad device specification mmc 0 **
654 01:40:00.404261 Couldn't find partition mmc 0
655 01:40:00.411968 Card did not respond to voltage select! : -110
656 01:40:00.417665 ** Bad device specification mmc 0 **
657 01:40:00.418180 Couldn't find partition mmc 0
658 01:40:00.422734 Error: could not access storage.
659 01:40:00.765129 Net: eth0: ethernet@ff3f0000
660 01:40:00.765663 starting USB...
661 01:40:01.016823 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:40:01.017368 Starting the controller
663 01:40:01.023961 USB XHCI 1.10
664 01:40:02.735581 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:40:02.736244 bl2_stage_init 0x01
666 01:40:02.736720 bl2_stage_init 0x81
667 01:40:02.741203 hw id: 0x0000 - pwm id 0x01
668 01:40:02.741733 bl2_stage_init 0xc1
669 01:40:02.742193 bl2_stage_init 0x02
670 01:40:02.742638
671 01:40:02.746859 L0:00000000
672 01:40:02.747380 L1:20000703
673 01:40:02.747835 L2:00008067
674 01:40:02.748319 L3:14000000
675 01:40:02.752379 B2:00402000
676 01:40:02.752900 B1:e0f83180
677 01:40:02.753352
678 01:40:02.753800 TE: 58159
679 01:40:02.754242
680 01:40:02.757963 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:40:02.758495
682 01:40:02.758955 Board ID = 1
683 01:40:02.763589 Set A53 clk to 24M
684 01:40:02.764143 Set A73 clk to 24M
685 01:40:02.764603 Set clk81 to 24M
686 01:40:02.769182 A53 clk: 1200 MHz
687 01:40:02.769710 A73 clk: 1200 MHz
688 01:40:02.770166 CLK81: 166.6M
689 01:40:02.770612 smccc: 00012ab5
690 01:40:02.774796 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:40:02.780335 board id: 1
692 01:40:02.786204 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:40:02.796854 fw parse done
694 01:40:02.802861 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:40:02.845456 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:40:02.856379 PIEI prepare done
697 01:40:02.856900 fastboot data load
698 01:40:02.857363 fastboot data verify
699 01:40:02.862060 verify result: 266
700 01:40:02.867665 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:40:02.868263 LPDDR4 probe
702 01:40:02.868751 ddr clk to 1584MHz
703 01:40:02.876462 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:40:02.913165
705 01:40:02.914044 dmc_version 0001
706 01:40:02.920166 Check phy result
707 01:40:02.925655 INFO : End of CA training
708 01:40:02.926223 INFO : End of initialization
709 01:40:02.931013 INFO : Training has run successfully!
710 01:40:02.931550 Check phy result
711 01:40:02.936615 INFO : End of initialization
712 01:40:02.937140 INFO : End of read enable training
713 01:40:02.942350 INFO : End of fine write leveling
714 01:40:02.947966 INFO : End of Write leveling coarse delay
715 01:40:02.948547 INFO : Training has run successfully!
716 01:40:02.949011 Check phy result
717 01:40:02.953738 INFO : End of initialization
718 01:40:02.954276 INFO : End of read dq deskew training
719 01:40:02.959220 INFO : End of MPR read delay center optimization
720 01:40:02.964949 INFO : End of write delay center optimization
721 01:40:02.970574 INFO : End of read delay center optimization
722 01:40:02.971131 INFO : End of max read latency training
723 01:40:02.976027 INFO : Training has run successfully!
724 01:40:02.976561 1D training succeed
725 01:40:02.985177 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:40:03.032930 Check phy result
727 01:40:03.033641 INFO : End of initialization
728 01:40:03.054828 INFO : End of 2D read delay Voltage center optimization
729 01:40:03.074457 INFO : End of 2D read delay Voltage center optimization
730 01:40:03.126263 INFO : End of 2D write delay Voltage center optimization
731 01:40:03.175368 INFO : End of 2D write delay Voltage center optimization
732 01:40:03.180976 INFO : Training has run successfully!
733 01:40:03.181491
734 01:40:03.181957 channel==0
735 01:40:03.186547 RxClkDly_Margin_A0==88 ps 9
736 01:40:03.187047 TxDqDly_Margin_A0==108 ps 11
737 01:40:03.192215 RxClkDly_Margin_A1==88 ps 9
738 01:40:03.192707 TxDqDly_Margin_A1==88 ps 9
739 01:40:03.193164 TrainedVREFDQ_A0==74
740 01:40:03.197898 TrainedVREFDQ_A1==74
741 01:40:03.198531 VrefDac_Margin_A0==25
742 01:40:03.199075 DeviceVref_Margin_A0==40
743 01:40:03.203372 VrefDac_Margin_A1==25
744 01:40:03.203926 DeviceVref_Margin_A1==40
745 01:40:03.204446
746 01:40:03.204904
747 01:40:03.208956 channel==1
748 01:40:03.209456 RxClkDly_Margin_A0==98 ps 10
749 01:40:03.209907 TxDqDly_Margin_A0==88 ps 9
750 01:40:03.214539 RxClkDly_Margin_A1==88 ps 9
751 01:40:03.215087 TxDqDly_Margin_A1==88 ps 9
752 01:40:03.220202 TrainedVREFDQ_A0==77
753 01:40:03.220703 TrainedVREFDQ_A1==77
754 01:40:03.221159 VrefDac_Margin_A0==22
755 01:40:03.225846 DeviceVref_Margin_A0==37
756 01:40:03.226347 VrefDac_Margin_A1==24
757 01:40:03.231376 DeviceVref_Margin_A1==37
758 01:40:03.231866
759 01:40:03.232368 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:40:03.232821
761 01:40:03.264980 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 01:40:03.265504 2D training succeed
763 01:40:03.270524 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:40:03.276165 auto size-- 65535DDR cs0 size: 2048MB
765 01:40:03.276662 DDR cs1 size: 2048MB
766 01:40:03.281857 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:40:03.282346 cs0 DataBus test pass
768 01:40:03.287328 cs1 DataBus test pass
769 01:40:03.287820 cs0 AddrBus test pass
770 01:40:03.288306 cs1 AddrBus test pass
771 01:40:03.288751
772 01:40:03.292979 100bdlr_step_size ps== 420
773 01:40:03.293481 result report
774 01:40:03.298529 boot times 0Enable ddr reg access
775 01:40:03.303919 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:40:03.317293 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:40:03.889274 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:40:03.889867 MVN_1=0x00000000
779 01:40:03.894771 MVN_2=0x00000000
780 01:40:03.900561 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:40:03.901126 OPS=0x10
782 01:40:03.901567 ring efuse init
783 01:40:03.901995 chipver efuse init
784 01:40:03.906134 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:40:03.911747 [0.018961 Inits done]
786 01:40:03.912273 secure task start!
787 01:40:03.912710 high task start!
788 01:40:03.916281 low task start!
789 01:40:03.916751 run into bl31
790 01:40:03.922938 NOTICE: BL31: v1.3(release):4fc40b1
791 01:40:03.930728 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:40:03.931219 NOTICE: BL31: G12A normal boot!
793 01:40:03.956083 NOTICE: BL31: BL33 decompress pass
794 01:40:03.961732 ERROR: Error initializing runtime service opteed_fast
795 01:40:05.194655
796 01:40:05.195283
797 01:40:05.203219 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:40:05.203829
799 01:40:05.204397 Model: Libre Computer AML-A311D-CC Alta
800 01:40:05.411458 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:40:05.434855 DRAM: 2 GiB (effective 3.8 GiB)
802 01:40:05.577804 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:40:05.583706 WDT: Not starting watchdog@f0d0
804 01:40:05.616010 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:40:05.628441 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:40:05.633415 ** Bad device specification mmc 0 **
807 01:40:05.643729 Card did not respond to voltage select! : -110
808 01:40:05.651381 ** Bad device specification mmc 0 **
809 01:40:05.651864 Couldn't find partition mmc 0
810 01:40:05.659733 Card did not respond to voltage select! : -110
811 01:40:05.665229 ** Bad device specification mmc 0 **
812 01:40:05.665709 Couldn't find partition mmc 0
813 01:40:05.670280 Error: could not access storage.
814 01:40:06.012767 Net: eth0: ethernet@ff3f0000
815 01:40:06.013321 starting USB...
816 01:40:06.264691 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:40:06.265346 Starting the controller
818 01:40:06.271527 USB XHCI 1.10
819 01:40:08.437419 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 01:40:08.438144 bl2_stage_init 0x81
821 01:40:08.442867 hw id: 0x0000 - pwm id 0x01
822 01:40:08.443383 bl2_stage_init 0xc1
823 01:40:08.443840 bl2_stage_init 0x02
824 01:40:08.444364
825 01:40:08.448648 L0:00000000
826 01:40:08.449159 L1:20000703
827 01:40:08.449615 L2:00008067
828 01:40:08.450057 L3:14000000
829 01:40:08.450499 B2:00402000
830 01:40:08.454104 B1:e0f83180
831 01:40:08.454590
832 01:40:08.455043 TE: 58150
833 01:40:08.455491
834 01:40:08.459649 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 01:40:08.460180
836 01:40:08.460634 Board ID = 1
837 01:40:08.465345 Set A53 clk to 24M
838 01:40:08.465823 Set A73 clk to 24M
839 01:40:08.466269 Set clk81 to 24M
840 01:40:08.470874 A53 clk: 1200 MHz
841 01:40:08.471365 A73 clk: 1200 MHz
842 01:40:08.471811 CLK81: 166.6M
843 01:40:08.472298 smccc: 00012aac
844 01:40:08.476461 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 01:40:08.482063 board id: 1
846 01:40:08.487848 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 01:40:08.498494 fw parse done
848 01:40:08.504596 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 01:40:08.547013 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 01:40:08.557891 PIEI prepare done
851 01:40:08.558387 fastboot data load
852 01:40:08.558845 fastboot data verify
853 01:40:08.563674 verify result: 266
854 01:40:08.569167 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 01:40:08.569659 LPDDR4 probe
856 01:40:08.570107 ddr clk to 1584MHz
857 01:40:08.577133 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 01:40:08.614383
859 01:40:08.614872 dmc_version 0001
860 01:40:08.621058 Check phy result
861 01:40:08.626929 INFO : End of CA training
862 01:40:08.627407 INFO : End of initialization
863 01:40:08.632614 INFO : Training has run successfully!
864 01:40:08.633097 Check phy result
865 01:40:08.638147 INFO : End of initialization
866 01:40:08.638670 INFO : End of read enable training
867 01:40:08.643755 INFO : End of fine write leveling
868 01:40:08.649370 INFO : End of Write leveling coarse delay
869 01:40:08.649850 INFO : Training has run successfully!
870 01:40:08.650299 Check phy result
871 01:40:08.654983 INFO : End of initialization
872 01:40:08.655464 INFO : End of read dq deskew training
873 01:40:08.660675 INFO : End of MPR read delay center optimization
874 01:40:08.666250 INFO : End of write delay center optimization
875 01:40:08.671730 INFO : End of read delay center optimization
876 01:40:08.672252 INFO : End of max read latency training
877 01:40:08.677342 INFO : Training has run successfully!
878 01:40:08.677821 1D training succeed
879 01:40:08.686626 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 01:40:08.734869 Check phy result
881 01:40:08.735358 INFO : End of initialization
882 01:40:08.756768 INFO : End of 2D read delay Voltage center optimization
883 01:40:08.776922 INFO : End of 2D read delay Voltage center optimization
884 01:40:08.828918 INFO : End of 2D write delay Voltage center optimization
885 01:40:08.878395 INFO : End of 2D write delay Voltage center optimization
886 01:40:08.883952 INFO : Training has run successfully!
887 01:40:08.884500
888 01:40:08.884962 channel==0
889 01:40:08.889544 RxClkDly_Margin_A0==88 ps 9
890 01:40:08.890028 TxDqDly_Margin_A0==98 ps 10
891 01:40:08.892887 RxClkDly_Margin_A1==88 ps 9
892 01:40:08.893407 TxDqDly_Margin_A1==88 ps 9
893 01:40:08.898496 TrainedVREFDQ_A0==74
894 01:40:08.899028 TrainedVREFDQ_A1==74
895 01:40:08.899461 VrefDac_Margin_A0==24
896 01:40:08.903970 DeviceVref_Margin_A0==40
897 01:40:08.904473 VrefDac_Margin_A1==25
898 01:40:08.909681 DeviceVref_Margin_A1==40
899 01:40:08.910153
900 01:40:08.910584
901 01:40:08.911013 channel==1
902 01:40:08.911432 RxClkDly_Margin_A0==98 ps 10
903 01:40:08.915127 TxDqDly_Margin_A0==88 ps 9
904 01:40:08.915600 RxClkDly_Margin_A1==88 ps 9
905 01:40:08.920791 TxDqDly_Margin_A1==88 ps 9
906 01:40:08.921279 TrainedVREFDQ_A0==75
907 01:40:08.921713 TrainedVREFDQ_A1==77
908 01:40:08.926411 VrefDac_Margin_A0==22
909 01:40:08.926878 DeviceVref_Margin_A0==39
910 01:40:08.931974 VrefDac_Margin_A1==24
911 01:40:08.932473 DeviceVref_Margin_A1==37
912 01:40:08.932897
913 01:40:08.937713 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 01:40:08.938235
915 01:40:08.965487 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 01:40:08.971020 2D training succeed
917 01:40:08.976656 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 01:40:08.977133 auto size-- 65535DDR cs0 size: 2048MB
919 01:40:08.982244 DDR cs1 size: 2048MB
920 01:40:08.982714 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 01:40:08.987835 cs0 DataBus test pass
922 01:40:08.988356 cs1 DataBus test pass
923 01:40:08.988784 cs0 AddrBus test pass
924 01:40:08.993499 cs1 AddrBus test pass
925 01:40:08.993968
926 01:40:08.994394 100bdlr_step_size ps== 420
927 01:40:08.994831 result report
928 01:40:08.999030 boot times 0Enable ddr reg access
929 01:40:09.006565 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 01:40:09.020077 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 01:40:09.593801 0.0;M3 CHK:0;cm4_sp_mode 0
932 01:40:09.594439 MVN_1=0x00000000
933 01:40:09.599223 MVN_2=0x00000000
934 01:40:09.605020 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 01:40:09.605517 OPS=0x10
936 01:40:09.605973 ring efuse init
937 01:40:09.606414 chipver efuse init
938 01:40:09.610634 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 01:40:09.616229 [0.018960 Inits done]
940 01:40:09.616710 secure task start!
941 01:40:09.617162 high task start!
942 01:40:09.620771 low task start!
943 01:40:09.621251 run into bl31
944 01:40:09.627463 NOTICE: BL31: v1.3(release):4fc40b1
945 01:40:09.635269 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 01:40:09.635760 NOTICE: BL31: G12A normal boot!
947 01:40:09.660672 NOTICE: BL31: BL33 decompress pass
948 01:40:09.666262 ERROR: Error initializing runtime service opteed_fast
949 01:40:10.899348
950 01:40:10.900049
951 01:40:10.907608 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 01:40:10.908131
953 01:40:10.908599 Model: Libre Computer AML-A311D-CC Alta
954 01:40:11.116070 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 01:40:11.139363 DRAM: 2 GiB (effective 3.8 GiB)
956 01:40:11.282425 Core: 408 devices, 31 uclasses, devicetree: separate
957 01:40:11.288262 WDT: Not starting watchdog@f0d0
958 01:40:11.320492 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 01:40:11.333082 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 01:40:11.337943 ** Bad device specification mmc 0 **
961 01:40:11.348320 Card did not respond to voltage select! : -110
962 01:40:11.355951 ** Bad device specification mmc 0 **
963 01:40:11.356470 Couldn't find partition mmc 0
964 01:40:11.364307 Card did not respond to voltage select! : -110
965 01:40:11.369943 ** Bad device specification mmc 0 **
966 01:40:11.370416 Couldn't find partition mmc 0
967 01:40:11.374956 Error: could not access storage.
968 01:40:11.717361 Net: eth0: ethernet@ff3f0000
969 01:40:11.717915 starting USB...
970 01:40:11.969190 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 01:40:11.969729 Starting the controller
972 01:40:11.976179 USB XHCI 1.10
973 01:40:13.530276 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 01:40:13.538461 scanning usb for storage devices... 0 Storage Device(s) found
976 01:40:13.590130 Hit any key to stop autoboot: 1
977 01:40:13.591001 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 01:40:13.591638 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 01:40:13.592197 Setting prompt string to ['=>']
980 01:40:13.592738 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 01:40:13.605912 0
982 01:40:13.606797 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 01:40:13.607320 Sending with 10 millisecond of delay
985 01:40:14.742188 => setenv autoload no
986 01:40:14.752927 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 01:40:14.758245 setenv autoload no
988 01:40:14.759004 Sending with 10 millisecond of delay
990 01:40:16.556085 => setenv initrd_high 0xffffffff
991 01:40:16.566884 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 01:40:16.567759 setenv initrd_high 0xffffffff
993 01:40:16.568603 Sending with 10 millisecond of delay
995 01:40:18.185140 => setenv fdt_high 0xffffffff
996 01:40:18.195873 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
997 01:40:18.196736 setenv fdt_high 0xffffffff
998 01:40:18.197487 Sending with 10 millisecond of delay
1000 01:40:18.489375 => dhcp
1001 01:40:18.500069 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 01:40:18.500899 dhcp
1003 01:40:18.501374 Speed: 1000, full duplex
1004 01:40:18.501823 BOOTP broadcast 1
1005 01:40:18.509959 DHCP client bound to address 192.168.6.27 (10 ms)
1006 01:40:18.510719 Sending with 10 millisecond of delay
1008 01:40:20.187338 => setenv serverip 192.168.6.2
1009 01:40:20.198090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1010 01:40:20.198990 setenv serverip 192.168.6.2
1011 01:40:20.199722 Sending with 10 millisecond of delay
1013 01:40:23.923569 => tftpboot 0x01080000 919431/tftp-deploy-v766ve5i/kernel/uImage
1014 01:40:23.934466 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 01:40:23.935331 tftpboot 0x01080000 919431/tftp-deploy-v766ve5i/kernel/uImage
1016 01:40:23.935820 Speed: 1000, full duplex
1017 01:40:23.936323 Using ethernet@ff3f0000 device
1018 01:40:23.939462 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 01:40:23.946890 Filename '919431/tftp-deploy-v766ve5i/kernel/uImage'.
1020 01:40:23.947389 Load address: 0x1080000
1021 01:40:26.903679 Loading: *################################################## 43.6 MiB
1022 01:40:26.904410 14.7 MiB/s
1023 01:40:26.904891 done
1024 01:40:26.908102 Bytes transferred = 45713984 (2b98a40 hex)
1025 01:40:26.908956 Sending with 10 millisecond of delay
1027 01:40:31.595441 => tftpboot 0x08000000 919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot
1028 01:40:31.606272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1029 01:40:31.607113 tftpboot 0x08000000 919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot
1030 01:40:31.607597 Speed: 1000, full duplex
1031 01:40:31.608083 Using ethernet@ff3f0000 device
1032 01:40:31.609001 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 01:40:31.617624 Filename '919431/tftp-deploy-v766ve5i/ramdisk/ramdisk.cpio.gz.uboot'.
1034 01:40:31.618111 Load address: 0x8000000
1035 01:40:38.586218 Loading: *###############T ################################## UDP wrong checksum 00000005 00002203
1036 01:40:43.587165 T UDP wrong checksum 00000005 00002203
1037 01:40:53.590174 T T UDP wrong checksum 00000005 00002203
1038 01:41:13.593206 T T T UDP wrong checksum 00000005 00002203
1039 01:41:28.599427 T T T
1040 01:41:28.600138 Retry count exceeded; starting again
1042 01:41:28.601656 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1045 01:41:28.603783 end: 2.4 uboot-commands (duration 00:01:47) [common]
1047 01:41:28.605355 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1049 01:41:28.606459 end: 2 uboot-action (duration 00:01:47) [common]
1051 01:41:28.608132 Cleaning after the job
1052 01:41:28.608734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/ramdisk
1053 01:41:28.610232 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/kernel
1054 01:41:28.655973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/dtb
1055 01:41:28.656781 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/nfsrootfs
1056 01:41:28.829592 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919431/tftp-deploy-v766ve5i/modules
1057 01:41:28.851077 start: 4.1 power-off (timeout 00:00:30) [common]
1058 01:41:28.851726 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1059 01:41:28.886032 >> OK - accepted request
1060 01:41:28.888103 Returned 0 in 0 seconds
1061 01:41:28.988891 end: 4.1 power-off (duration 00:00:00) [common]
1063 01:41:28.989900 start: 4.2 read-feedback (timeout 00:10:00) [common]
1064 01:41:28.990634 Listened to connection for namespace 'common' for up to 1s
1065 01:41:29.991075 Finalising connection for namespace 'common'
1066 01:41:29.991575 Disconnecting from shell: Finalise
1067 01:41:29.991880 =>
1068 01:41:30.092855 end: 4.2 read-feedback (duration 00:00:01) [common]
1069 01:41:30.093341 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919431
1070 01:41:33.153370 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919431
1071 01:41:33.154042 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.