Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:34:42.748483 lava-dispatcher, installed at version: 2024.01
2 01:34:42.749272 start: 0 validate
3 01:34:42.749766 Start time: 2024-11-01 01:34:42.749735+00:00 (UTC)
4 01:34:42.750312 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:34:42.751065 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:34:42.786854 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:34:42.787737 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:34:42.819224 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:34:42.819856 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:34:42.860792 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:34:42.861284 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:34:42.893575 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:34:42.894056 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-161-g90602c251cda%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:34:42.929345 validate duration: 0.18
16 01:34:42.930218 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:34:42.930552 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:34:42.930870 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:34:42.931456 Not decompressing ramdisk as can be used compressed.
20 01:34:42.931901 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:34:42.932215 saving as /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/ramdisk/initrd.cpio.gz
22 01:34:42.932492 total size: 5628140 (5 MB)
23 01:34:42.976918 progress 0 % (0 MB)
24 01:34:42.984669 progress 5 % (0 MB)
25 01:34:42.993044 progress 10 % (0 MB)
26 01:34:43.000331 progress 15 % (0 MB)
27 01:34:43.004544 progress 20 % (1 MB)
28 01:34:43.008283 progress 25 % (1 MB)
29 01:34:43.012383 progress 30 % (1 MB)
30 01:34:43.016630 progress 35 % (1 MB)
31 01:34:43.020567 progress 40 % (2 MB)
32 01:34:43.024682 progress 45 % (2 MB)
33 01:34:43.028458 progress 50 % (2 MB)
34 01:34:43.032954 progress 55 % (2 MB)
35 01:34:43.037271 progress 60 % (3 MB)
36 01:34:43.041002 progress 65 % (3 MB)
37 01:34:43.045238 progress 70 % (3 MB)
38 01:34:43.049543 progress 75 % (4 MB)
39 01:34:43.053696 progress 80 % (4 MB)
40 01:34:43.057471 progress 85 % (4 MB)
41 01:34:43.061699 progress 90 % (4 MB)
42 01:34:43.065755 progress 95 % (5 MB)
43 01:34:43.069124 progress 100 % (5 MB)
44 01:34:43.069806 5 MB downloaded in 0.14 s (39.09 MB/s)
45 01:34:43.070366 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:34:43.071259 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:34:43.071553 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:34:43.071829 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:34:43.072361 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/kernel/Image
51 01:34:43.072630 saving as /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/kernel/Image
52 01:34:43.072841 total size: 45713920 (43 MB)
53 01:34:43.073051 No compression specified
54 01:34:43.110605 progress 0 % (0 MB)
55 01:34:43.140379 progress 5 % (2 MB)
56 01:34:43.170204 progress 10 % (4 MB)
57 01:34:43.199913 progress 15 % (6 MB)
58 01:34:43.229942 progress 20 % (8 MB)
59 01:34:43.258630 progress 25 % (10 MB)
60 01:34:43.288160 progress 30 % (13 MB)
61 01:34:43.317345 progress 35 % (15 MB)
62 01:34:43.346818 progress 40 % (17 MB)
63 01:34:43.376017 progress 45 % (19 MB)
64 01:34:43.406103 progress 50 % (21 MB)
65 01:34:43.435535 progress 55 % (24 MB)
66 01:34:43.464899 progress 60 % (26 MB)
67 01:34:43.493621 progress 65 % (28 MB)
68 01:34:43.522962 progress 70 % (30 MB)
69 01:34:43.552780 progress 75 % (32 MB)
70 01:34:43.585044 progress 80 % (34 MB)
71 01:34:43.615136 progress 85 % (37 MB)
72 01:34:43.644306 progress 90 % (39 MB)
73 01:34:43.673620 progress 95 % (41 MB)
74 01:34:43.702245 progress 100 % (43 MB)
75 01:34:43.702805 43 MB downloaded in 0.63 s (69.21 MB/s)
76 01:34:43.703313 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:34:43.704208 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:34:43.704516 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:34:43.704803 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:34:43.705295 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:34:43.705557 saving as /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:34:43.705779 total size: 54703 (0 MB)
84 01:34:43.705997 No compression specified
85 01:34:43.744698 progress 59 % (0 MB)
86 01:34:43.745575 progress 100 % (0 MB)
87 01:34:43.746141 0 MB downloaded in 0.04 s (1.29 MB/s)
88 01:34:43.746634 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:34:43.747652 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:34:43.747958 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:34:43.748270 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:34:43.748752 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:34:43.749023 saving as /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/nfsrootfs/full.rootfs.tar
95 01:34:43.749236 total size: 474398908 (452 MB)
96 01:34:43.749452 Using unxz to decompress xz
97 01:34:43.783951 progress 0 % (0 MB)
98 01:34:44.895268 progress 5 % (22 MB)
99 01:34:46.351840 progress 10 % (45 MB)
100 01:34:46.818187 progress 15 % (67 MB)
101 01:34:47.679163 progress 20 % (90 MB)
102 01:34:48.230681 progress 25 % (113 MB)
103 01:34:48.596072 progress 30 % (135 MB)
104 01:34:49.212339 progress 35 % (158 MB)
105 01:34:50.165683 progress 40 % (181 MB)
106 01:34:51.012333 progress 45 % (203 MB)
107 01:34:51.696058 progress 50 % (226 MB)
108 01:34:52.345436 progress 55 % (248 MB)
109 01:34:53.564604 progress 60 % (271 MB)
110 01:34:55.066549 progress 65 % (294 MB)
111 01:34:56.752049 progress 70 % (316 MB)
112 01:34:59.826536 progress 75 % (339 MB)
113 01:35:02.273305 progress 80 % (361 MB)
114 01:35:05.270899 progress 85 % (384 MB)
115 01:35:08.477951 progress 90 % (407 MB)
116 01:35:11.688407 progress 95 % (429 MB)
117 01:35:14.879207 progress 100 % (452 MB)
118 01:35:14.893087 452 MB downloaded in 31.14 s (14.53 MB/s)
119 01:35:14.893654 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:35:14.894487 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:35:14.894756 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:35:14.895017 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:35:14.895481 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-161-g90602c251cda/arm64/defconfig/gcc-12/modules.tar.xz
125 01:35:14.895723 saving as /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/modules/modules.tar
126 01:35:14.895929 total size: 11592552 (11 MB)
127 01:35:14.896571 Using unxz to decompress xz
128 01:35:14.937244 progress 0 % (0 MB)
129 01:35:15.005738 progress 5 % (0 MB)
130 01:35:15.087579 progress 10 % (1 MB)
131 01:35:15.170535 progress 15 % (1 MB)
132 01:35:15.246325 progress 20 % (2 MB)
133 01:35:15.322380 progress 25 % (2 MB)
134 01:35:15.401387 progress 30 % (3 MB)
135 01:35:15.473250 progress 35 % (3 MB)
136 01:35:15.554414 progress 40 % (4 MB)
137 01:35:15.646193 progress 45 % (5 MB)
138 01:35:15.725665 progress 50 % (5 MB)
139 01:35:15.808194 progress 55 % (6 MB)
140 01:35:15.889933 progress 60 % (6 MB)
141 01:35:15.968632 progress 65 % (7 MB)
142 01:35:16.047725 progress 70 % (7 MB)
143 01:35:16.127552 progress 75 % (8 MB)
144 01:35:16.208529 progress 80 % (8 MB)
145 01:35:16.282975 progress 85 % (9 MB)
146 01:35:16.354329 progress 90 % (9 MB)
147 01:35:16.452163 progress 95 % (10 MB)
148 01:35:16.543664 progress 100 % (11 MB)
149 01:35:16.558169 11 MB downloaded in 1.66 s (6.65 MB/s)
150 01:35:16.559190 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:35:16.561020 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:35:16.561602 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 01:35:16.562178 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 01:35:32.021478 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/919392/extract-nfsrootfs-sxbvlz_z
156 01:35:32.022089 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 01:35:32.022383 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:35:32.023086 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix
159 01:35:32.023542 makedir: /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin
160 01:35:32.023870 makedir: /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/tests
161 01:35:32.024236 makedir: /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/results
162 01:35:32.024581 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-add-keys
163 01:35:32.025110 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-add-sources
164 01:35:32.025620 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-background-process-start
165 01:35:32.026131 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-background-process-stop
166 01:35:32.026705 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-common-functions
167 01:35:32.027205 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-echo-ipv4
168 01:35:32.027681 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-install-packages
169 01:35:32.028193 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-installed-packages
170 01:35:32.028681 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-os-build
171 01:35:32.029156 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-probe-channel
172 01:35:32.029712 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-probe-ip
173 01:35:32.030304 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-target-ip
174 01:35:32.030831 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-target-mac
175 01:35:32.031313 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-target-storage
176 01:35:32.031792 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-case
177 01:35:32.032324 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-event
178 01:35:32.032810 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-feedback
179 01:35:32.033290 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-raise
180 01:35:32.033759 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-reference
181 01:35:32.034253 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-runner
182 01:35:32.034772 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-set
183 01:35:32.035251 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-test-shell
184 01:35:32.035736 Updating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-install-packages (oe)
185 01:35:32.036295 Updating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/bin/lava-installed-packages (oe)
186 01:35:32.036738 Creating /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/environment
187 01:35:32.037107 LAVA metadata
188 01:35:32.037367 - LAVA_JOB_ID=919392
189 01:35:32.037581 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:35:32.037936 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:35:32.038874 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:35:32.039183 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:35:32.039390 skipped lava-vland-overlay
194 01:35:32.039631 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:35:32.039881 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:35:32.040124 skipped lava-multinode-overlay
197 01:35:32.040372 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:35:32.040623 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:35:32.040870 Loading test definitions
200 01:35:32.041148 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:35:32.041366 Using /lava-919392 at stage 0
202 01:35:32.042520 uuid=919392_1.6.2.4.1 testdef=None
203 01:35:32.042826 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:35:32.043084 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:35:32.044822 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:35:32.045614 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:35:32.047790 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:35:32.048677 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:35:32.050728 runner path: /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 919392_1.6.2.4.1
212 01:35:32.051294 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:35:32.052081 Creating lava-test-runner.conf files
215 01:35:32.052283 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/919392/lava-overlay-lqtvfuix/lava-919392/0 for stage 0
216 01:35:32.052613 - 0_v4l2-decoder-conformance-vp9
217 01:35:32.052952 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:35:32.053224 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:35:32.074741 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:35:32.075123 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:35:32.075382 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:35:32.075646 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:35:32.075907 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:35:32.686485 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:35:32.686955 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:35:32.687205 extracting modules file /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919392/extract-nfsrootfs-sxbvlz_z
227 01:35:34.111550 extracting modules file /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/919392/extract-overlay-ramdisk-fw2cr0zb/ramdisk
228 01:35:35.744052 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:35:35.744743 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 01:35:35.745194 [common] Applying overlay to NFS
231 01:35:35.745515 [common] Applying overlay /var/lib/lava/dispatcher/tmp/919392/compress-overlay-boj26_st/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/919392/extract-nfsrootfs-sxbvlz_z
232 01:35:35.789920 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:35:35.790571 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 01:35:35.791022 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 01:35:35.791368 Converting downloaded kernel to a uImage
236 01:35:35.791856 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/kernel/Image /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/kernel/uImage
237 01:35:36.338688 output: Image Name:
238 01:35:36.339152 output: Created: Fri Nov 1 01:35:35 2024
239 01:35:36.339419 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:35:36.339706 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 01:35:36.340035 output: Load Address: 01080000
242 01:35:36.340429 output: Entry Point: 01080000
243 01:35:36.340783 output:
244 01:35:36.341194 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 01:35:36.341696 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 01:35:36.342110 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 01:35:36.342467 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:35:36.342830 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 01:35:36.343180 Building ramdisk /var/lib/lava/dispatcher/tmp/919392/extract-overlay-ramdisk-fw2cr0zb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/919392/extract-overlay-ramdisk-fw2cr0zb/ramdisk
250 01:35:38.526945 >> 166820 blocks
251 01:35:46.252979 Adding RAMdisk u-boot header.
252 01:35:46.253645 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/919392/extract-overlay-ramdisk-fw2cr0zb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/919392/extract-overlay-ramdisk-fw2cr0zb/ramdisk.cpio.gz.uboot
253 01:35:46.499763 output: Image Name:
254 01:35:46.500379 output: Created: Fri Nov 1 01:35:46 2024
255 01:35:46.500807 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:35:46.501239 output: Data Size: 23432711 Bytes = 22883.51 KiB = 22.35 MiB
257 01:35:46.501643 output: Load Address: 00000000
258 01:35:46.502039 output: Entry Point: 00000000
259 01:35:46.502433 output:
260 01:35:46.503398 rename /var/lib/lava/dispatcher/tmp/919392/extract-overlay-ramdisk-fw2cr0zb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot
261 01:35:46.504149 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:35:46.504697 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 01:35:46.505222 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 01:35:46.505677 No LXC device requested
265 01:35:46.506172 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:35:46.506675 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 01:35:46.507167 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:35:46.507576 Checking files for TFTP limit of 4294967296 bytes.
269 01:35:46.510232 end: 1 tftp-deploy (duration 00:01:04) [common]
270 01:35:46.510797 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:35:46.511317 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:35:46.511811 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:35:46.512344 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:35:46.512867 Using kernel file from prepare-kernel: 919392/tftp-deploy-b1r4wf5g/kernel/uImage
275 01:35:46.513487 substitutions:
276 01:35:46.513888 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:35:46.514286 - {DTB_ADDR}: 0x01070000
278 01:35:46.514681 - {DTB}: 919392/tftp-deploy-b1r4wf5g/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:35:46.515074 - {INITRD}: 919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot
280 01:35:46.515468 - {KERNEL_ADDR}: 0x01080000
281 01:35:46.515857 - {KERNEL}: 919392/tftp-deploy-b1r4wf5g/kernel/uImage
282 01:35:46.516328 - {LAVA_MAC}: None
283 01:35:46.516762 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/919392/extract-nfsrootfs-sxbvlz_z
284 01:35:46.517162 - {NFS_SERVER_IP}: 192.168.6.2
285 01:35:46.517554 - {PRESEED_CONFIG}: None
286 01:35:46.517938 - {PRESEED_LOCAL}: None
287 01:35:46.518326 - {RAMDISK_ADDR}: 0x08000000
288 01:35:46.518709 - {RAMDISK}: 919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot
289 01:35:46.519095 - {ROOT_PART}: None
290 01:35:46.519479 - {ROOT}: None
291 01:35:46.519862 - {SERVER_IP}: 192.168.6.2
292 01:35:46.520324 - {TEE_ADDR}: 0x83000000
293 01:35:46.520717 - {TEE}: None
294 01:35:46.521105 Parsed boot commands:
295 01:35:46.521484 - setenv autoload no
296 01:35:46.521869 - setenv initrd_high 0xffffffff
297 01:35:46.522253 - setenv fdt_high 0xffffffff
298 01:35:46.522638 - dhcp
299 01:35:46.523020 - setenv serverip 192.168.6.2
300 01:35:46.523403 - tftpboot 0x01080000 919392/tftp-deploy-b1r4wf5g/kernel/uImage
301 01:35:46.523788 - tftpboot 0x08000000 919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot
302 01:35:46.524200 - tftpboot 0x01070000 919392/tftp-deploy-b1r4wf5g/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:35:46.524586 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/919392/extract-nfsrootfs-sxbvlz_z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:35:46.524981 - bootm 0x01080000 0x08000000 0x01070000
305 01:35:46.525470 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:35:46.526944 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:35:46.527360 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:35:46.542008 Setting prompt string to ['lava-test: # ']
310 01:35:46.543478 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:35:46.544101 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:35:46.544645 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:35:46.545159 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:35:46.546287 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:35:46.582790 >> OK - accepted request
316 01:35:46.585049 Returned 0 in 0 seconds
317 01:35:46.686148 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:35:46.687749 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:35:46.688350 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:35:46.688872 Setting prompt string to ['Hit any key to stop autoboot']
322 01:35:46.689331 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:35:46.690865 Trying 192.168.56.21...
324 01:35:46.691334 Connected to conserv1.
325 01:35:46.691748 Escape character is '^]'.
326 01:35:46.692200
327 01:35:46.692620 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:35:46.693035
329 01:35:58.383919 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:35:58.384358 bl2_stage_init 0x01
331 01:35:58.384579 bl2_stage_init 0x81
332 01:35:58.389415 hw id: 0x0000 - pwm id 0x01
333 01:35:58.389689 bl2_stage_init 0xc1
334 01:35:58.389900 bl2_stage_init 0x02
335 01:35:58.390114
336 01:35:58.394955 L0:00000000
337 01:35:58.395201 L1:20000703
338 01:35:58.395404 L2:00008067
339 01:35:58.395604 L3:14000000
340 01:35:58.400579 B2:00402000
341 01:35:58.400836 B1:e0f83180
342 01:35:58.401046
343 01:35:58.401250 TE: 58159
344 01:35:58.401453
345 01:35:58.406274 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:35:58.406519
347 01:35:58.406726 Board ID = 1
348 01:35:58.411731 Set A53 clk to 24M
349 01:35:58.411970 Set A73 clk to 24M
350 01:35:58.412339 Set clk81 to 24M
351 01:35:58.417431 A53 clk: 1200 MHz
352 01:35:58.417844 A73 clk: 1200 MHz
353 01:35:58.418233 CLK81: 166.6M
354 01:35:58.418615 smccc: 00012ab5
355 01:35:58.422936 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:35:58.428587 board id: 1
357 01:35:58.434292 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:35:58.445218 fw parse done
359 01:35:58.451123 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:35:58.493045 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:35:58.504564 PIEI prepare done
362 01:35:58.504986 fastboot data load
363 01:35:58.505374 fastboot data verify
364 01:35:58.510320 verify result: 266
365 01:35:58.515830 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:35:58.516285 LPDDR4 probe
367 01:35:58.516676 ddr clk to 1584MHz
368 01:35:58.523830 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:35:58.561068
370 01:35:58.561505 dmc_version 0001
371 01:35:58.567756 Check phy result
372 01:35:58.573627 INFO : End of CA training
373 01:35:58.574047 INFO : End of initialization
374 01:35:58.579270 INFO : Training has run successfully!
375 01:35:58.579685 Check phy result
376 01:35:58.584827 INFO : End of initialization
377 01:35:58.585238 INFO : End of read enable training
378 01:35:58.590427 INFO : End of fine write leveling
379 01:35:58.596039 INFO : End of Write leveling coarse delay
380 01:35:58.596454 INFO : Training has run successfully!
381 01:35:58.596842 Check phy result
382 01:35:58.601634 INFO : End of initialization
383 01:35:58.602039 INFO : End of read dq deskew training
384 01:35:58.607251 INFO : End of MPR read delay center optimization
385 01:35:58.612792 INFO : End of write delay center optimization
386 01:35:58.618412 INFO : End of read delay center optimization
387 01:35:58.618824 INFO : End of max read latency training
388 01:35:58.624066 INFO : Training has run successfully!
389 01:35:58.624525 1D training succeed
390 01:35:58.633256 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:35:58.680809 Check phy result
392 01:35:58.681268 INFO : End of initialization
393 01:35:58.702548 INFO : End of 2D read delay Voltage center optimization
394 01:35:58.722815 INFO : End of 2D read delay Voltage center optimization
395 01:35:58.774793 INFO : End of 2D write delay Voltage center optimization
396 01:35:58.824248 INFO : End of 2D write delay Voltage center optimization
397 01:35:58.829802 INFO : Training has run successfully!
398 01:35:58.830216
399 01:35:58.830612 channel==0
400 01:35:58.835389 RxClkDly_Margin_A0==88 ps 9
401 01:35:58.835814 TxDqDly_Margin_A0==98 ps 10
402 01:35:58.841017 RxClkDly_Margin_A1==88 ps 9
403 01:35:58.841431 TxDqDly_Margin_A1==88 ps 9
404 01:35:58.841825 TrainedVREFDQ_A0==74
405 01:35:58.846578 TrainedVREFDQ_A1==74
406 01:35:58.846991 VrefDac_Margin_A0==25
407 01:35:58.847377 DeviceVref_Margin_A0==40
408 01:35:58.852247 VrefDac_Margin_A1==25
409 01:35:58.852660 DeviceVref_Margin_A1==40
410 01:35:58.853043
411 01:35:58.853428
412 01:35:58.853822 channel==1
413 01:35:58.857690 RxClkDly_Margin_A0==98 ps 10
414 01:35:58.858108 TxDqDly_Margin_A0==88 ps 9
415 01:35:58.863371 RxClkDly_Margin_A1==88 ps 9
416 01:35:58.863781 TxDqDly_Margin_A1==88 ps 9
417 01:35:58.869007 TrainedVREFDQ_A0==76
418 01:35:58.869427 TrainedVREFDQ_A1==77
419 01:35:58.869821 VrefDac_Margin_A0==22
420 01:35:58.874508 DeviceVref_Margin_A0==38
421 01:35:58.874915 VrefDac_Margin_A1==24
422 01:35:58.880187 DeviceVref_Margin_A1==37
423 01:35:58.880593
424 01:35:58.880982 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:35:58.881365
426 01:35:58.913644 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:35:58.914144 2D training succeed
428 01:35:58.919240 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:35:58.924883 auto size-- 65535DDR cs0 size: 2048MB
430 01:35:58.925300 DDR cs1 size: 2048MB
431 01:35:58.930457 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:35:58.930867 cs0 DataBus test pass
433 01:35:58.936173 cs1 DataBus test pass
434 01:35:58.936583 cs0 AddrBus test pass
435 01:35:58.936971 cs1 AddrBus test pass
436 01:35:58.937354
437 01:35:58.941665 100bdlr_step_size ps== 420
438 01:35:58.942082 result report
439 01:35:58.947273 boot times 0Enable ddr reg access
440 01:35:58.952411 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:35:58.965933 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:35:59.539521 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:35:59.540081 MVN_1=0x00000000
444 01:35:59.545059 MVN_2=0x00000000
445 01:35:59.550827 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:35:59.551242 OPS=0x10
447 01:35:59.551632 ring efuse init
448 01:35:59.552048 chipver efuse init
449 01:35:59.556416 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:35:59.562004 [0.018960 Inits done]
451 01:35:59.562413 secure task start!
452 01:35:59.562799 high task start!
453 01:35:59.566607 low task start!
454 01:35:59.567023 run into bl31
455 01:35:59.573281 NOTICE: BL31: v1.3(release):4fc40b1
456 01:35:59.580158 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:35:59.580596 NOTICE: BL31: G12A normal boot!
458 01:35:59.606353 NOTICE: BL31: BL33 decompress pass
459 01:35:59.612054 ERROR: Error initializing runtime service opteed_fast
460 01:36:00.844849
461 01:36:00.845403
462 01:36:00.853307 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:36:00.853733
464 01:36:00.854144 Model: Libre Computer AML-A311D-CC Alta
465 01:36:01.061669 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:36:01.084153 DRAM: 2 GiB (effective 3.8 GiB)
467 01:36:01.228084 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:36:01.233949 WDT: Not starting watchdog@f0d0
469 01:36:01.266196 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:36:01.278660 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:36:01.283634 ** Bad device specification mmc 0 **
472 01:36:01.293976 Card did not respond to voltage select! : -110
473 01:36:01.301638 ** Bad device specification mmc 0 **
474 01:36:01.302054 Couldn't find partition mmc 0
475 01:36:01.309970 Card did not respond to voltage select! : -110
476 01:36:01.315507 ** Bad device specification mmc 0 **
477 01:36:01.315918 Couldn't find partition mmc 0
478 01:36:01.320593 Error: could not access storage.
479 01:36:02.584240 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:36:02.584674 bl2_stage_init 0x01
481 01:36:02.584979 bl2_stage_init 0x81
482 01:36:02.589723 hw id: 0x0000 - pwm id 0x01
483 01:36:02.590109 bl2_stage_init 0xc1
484 01:36:02.590318 bl2_stage_init 0x02
485 01:36:02.590519
486 01:36:02.595316 L0:00000000
487 01:36:02.595712 L1:20000703
488 01:36:02.595920 L2:00008067
489 01:36:02.596167 L3:14000000
490 01:36:02.598139 B2:00402000
491 01:36:02.598437 B1:e0f83180
492 01:36:02.598640
493 01:36:02.598841 TE: 58124
494 01:36:02.599040
495 01:36:02.609434 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:36:02.610117
497 01:36:02.610598 Board ID = 1
498 01:36:02.611056 Set A53 clk to 24M
499 01:36:02.611512 Set A73 clk to 24M
500 01:36:02.615041 Set clk81 to 24M
501 01:36:02.615578 A53 clk: 1200 MHz
502 01:36:02.616080 A73 clk: 1200 MHz
503 01:36:02.620633 CLK81: 166.6M
504 01:36:02.621167 smccc: 00012a92
505 01:36:02.626197 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:36:02.626703 board id: 1
507 01:36:02.634915 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:36:02.645486 fw parse done
509 01:36:02.650521 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:36:02.694113 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:36:02.704994 PIEI prepare done
512 01:36:02.705547 fastboot data load
513 01:36:02.706014 fastboot data verify
514 01:36:02.710662 verify result: 266
515 01:36:02.716365 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:36:02.716925 LPDDR4 probe
517 01:36:02.717386 ddr clk to 1584MHz
518 01:36:02.724197 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:36:02.761600
520 01:36:02.762206 dmc_version 0001
521 01:36:02.768069 Check phy result
522 01:36:02.774026 INFO : End of CA training
523 01:36:02.774540 INFO : End of initialization
524 01:36:02.779591 INFO : Training has run successfully!
525 01:36:02.780132 Check phy result
526 01:36:02.785236 INFO : End of initialization
527 01:36:02.785783 INFO : End of read enable training
528 01:36:02.790856 INFO : End of fine write leveling
529 01:36:02.796397 INFO : End of Write leveling coarse delay
530 01:36:02.796936 INFO : Training has run successfully!
531 01:36:02.797390 Check phy result
532 01:36:02.802020 INFO : End of initialization
533 01:36:02.802512 INFO : End of read dq deskew training
534 01:36:02.807624 INFO : End of MPR read delay center optimization
535 01:36:02.813221 INFO : End of write delay center optimization
536 01:36:02.818811 INFO : End of read delay center optimization
537 01:36:02.819298 INFO : End of max read latency training
538 01:36:02.824401 INFO : Training has run successfully!
539 01:36:02.824897 1D training succeed
540 01:36:02.833586 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:36:02.881337 Check phy result
542 01:36:02.881912 INFO : End of initialization
543 01:36:02.903685 INFO : End of 2D read delay Voltage center optimization
544 01:36:02.923719 INFO : End of 2D read delay Voltage center optimization
545 01:36:02.975787 INFO : End of 2D write delay Voltage center optimization
546 01:36:03.024960 INFO : End of 2D write delay Voltage center optimization
547 01:36:03.030457 INFO : Training has run successfully!
548 01:36:03.030975
549 01:36:03.031450 channel==0
550 01:36:03.036083 RxClkDly_Margin_A0==88 ps 9
551 01:36:03.036619 TxDqDly_Margin_A0==98 ps 10
552 01:36:03.041679 RxClkDly_Margin_A1==88 ps 9
553 01:36:03.042177 TxDqDly_Margin_A1==98 ps 10
554 01:36:03.042632 TrainedVREFDQ_A0==74
555 01:36:03.047277 TrainedVREFDQ_A1==74
556 01:36:03.047790 VrefDac_Margin_A0==25
557 01:36:03.048287 DeviceVref_Margin_A0==40
558 01:36:03.052916 VrefDac_Margin_A1==24
559 01:36:03.053432 DeviceVref_Margin_A1==40
560 01:36:03.053890
561 01:36:03.054336
562 01:36:03.058434 channel==1
563 01:36:03.058951 RxClkDly_Margin_A0==98 ps 10
564 01:36:03.059401 TxDqDly_Margin_A0==98 ps 10
565 01:36:03.064078 RxClkDly_Margin_A1==98 ps 10
566 01:36:03.064591 TxDqDly_Margin_A1==88 ps 9
567 01:36:03.069644 TrainedVREFDQ_A0==77
568 01:36:03.070143 TrainedVREFDQ_A1==77
569 01:36:03.070629 VrefDac_Margin_A0==22
570 01:36:03.075275 DeviceVref_Margin_A0==37
571 01:36:03.075814 VrefDac_Margin_A1==22
572 01:36:03.080911 DeviceVref_Margin_A1==37
573 01:36:03.081403
574 01:36:03.081855 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:36:03.086463
576 01:36:03.114445 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 01:36:03.115070 2D training succeed
578 01:36:03.120079 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:36:03.125663 auto size-- 65535DDR cs0 size: 2048MB
580 01:36:03.126178 DDR cs1 size: 2048MB
581 01:36:03.131288 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:36:03.131820 cs0 DataBus test pass
583 01:36:03.136936 cs1 DataBus test pass
584 01:36:03.137453 cs0 AddrBus test pass
585 01:36:03.137907 cs1 AddrBus test pass
586 01:36:03.138355
587 01:36:03.142460 100bdlr_step_size ps== 420
588 01:36:03.142975 result report
589 01:36:03.148064 boot times 0Enable ddr reg access
590 01:36:03.153478 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:36:03.166961 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:36:03.739075 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:36:03.739754 MVN_1=0x00000000
594 01:36:03.744521 MVN_2=0x00000000
595 01:36:03.750246 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:36:03.750785 OPS=0x10
597 01:36:03.751247 ring efuse init
598 01:36:03.751698 chipver efuse init
599 01:36:03.755796 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:36:03.761377 [0.018961 Inits done]
601 01:36:03.761888 secure task start!
602 01:36:03.762323 high task start!
603 01:36:03.765980 low task start!
604 01:36:03.766469 run into bl31
605 01:36:03.772533 NOTICE: BL31: v1.3(release):4fc40b1
606 01:36:03.780432 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:36:03.780937 NOTICE: BL31: G12A normal boot!
608 01:36:03.805846 NOTICE: BL31: BL33 decompress pass
609 01:36:03.811450 ERROR: Error initializing runtime service opteed_fast
610 01:36:05.044484
611 01:36:05.045162
612 01:36:05.052946 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:36:05.053493
614 01:36:05.053957 Model: Libre Computer AML-A311D-CC Alta
615 01:36:05.261394 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:36:05.284686 DRAM: 2 GiB (effective 3.8 GiB)
617 01:36:05.427770 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:36:05.433576 WDT: Not starting watchdog@f0d0
619 01:36:05.465747 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:36:05.478434 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:36:05.483422 ** Bad device specification mmc 0 **
622 01:36:05.493533 Card did not respond to voltage select! : -110
623 01:36:05.501263 ** Bad device specification mmc 0 **
624 01:36:05.501775 Couldn't find partition mmc 0
625 01:36:05.509538 Card did not respond to voltage select! : -110
626 01:36:05.515027 ** Bad device specification mmc 0 **
627 01:36:05.515538 Couldn't find partition mmc 0
628 01:36:05.520178 Error: could not access storage.
629 01:36:05.862700 Net: eth0: ethernet@ff3f0000
630 01:36:05.863319 starting USB...
631 01:36:06.114555 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:36:06.115149 Starting the controller
633 01:36:06.121498 USB XHCI 1.10
634 01:36:07.836117 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:36:07.836799 bl2_stage_init 0x01
636 01:36:07.837265 bl2_stage_init 0x81
637 01:36:07.841803 hw id: 0x0000 - pwm id 0x01
638 01:36:07.842309 bl2_stage_init 0xc1
639 01:36:07.842763 bl2_stage_init 0x02
640 01:36:07.843211
641 01:36:07.847271 L0:00000000
642 01:36:07.847779 L1:20000703
643 01:36:07.848268 L2:00008067
644 01:36:07.848711 L3:14000000
645 01:36:07.850172 B2:00402000
646 01:36:07.850664 B1:e0f83180
647 01:36:07.851108
648 01:36:07.851547 TE: 58124
649 01:36:07.852016
650 01:36:07.861229 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:36:07.861740
652 01:36:07.862192 Board ID = 1
653 01:36:07.862632 Set A53 clk to 24M
654 01:36:07.863066 Set A73 clk to 24M
655 01:36:07.866792 Set clk81 to 24M
656 01:36:07.867291 A53 clk: 1200 MHz
657 01:36:07.867739 A73 clk: 1200 MHz
658 01:36:07.870478 CLK81: 166.6M
659 01:36:07.870970 smccc: 00012a92
660 01:36:07.875969 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:36:07.881760 board id: 1
662 01:36:07.886642 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:36:07.897277 fw parse done
664 01:36:07.903197 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:36:07.945062 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:36:07.956864 PIEI prepare done
667 01:36:07.957378 fastboot data load
668 01:36:07.957837 fastboot data verify
669 01:36:07.962500 verify result: 266
670 01:36:07.968087 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:36:07.968595 LPDDR4 probe
672 01:36:07.969048 ddr clk to 1584MHz
673 01:36:07.976047 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:36:08.013258
675 01:36:08.013776 dmc_version 0001
676 01:36:08.020004 Check phy result
677 01:36:08.025860 INFO : End of CA training
678 01:36:08.026368 INFO : End of initialization
679 01:36:08.031427 INFO : Training has run successfully!
680 01:36:08.031928 Check phy result
681 01:36:08.037026 INFO : End of initialization
682 01:36:08.037526 INFO : End of read enable training
683 01:36:08.042625 INFO : End of fine write leveling
684 01:36:08.048288 INFO : End of Write leveling coarse delay
685 01:36:08.048796 INFO : Training has run successfully!
686 01:36:08.049243 Check phy result
687 01:36:08.053812 INFO : End of initialization
688 01:36:08.054310 INFO : End of read dq deskew training
689 01:36:08.059419 INFO : End of MPR read delay center optimization
690 01:36:08.065036 INFO : End of write delay center optimization
691 01:36:08.070627 INFO : End of read delay center optimization
692 01:36:08.071118 INFO : End of max read latency training
693 01:36:08.076249 INFO : Training has run successfully!
694 01:36:08.076745 1D training succeed
695 01:36:08.085530 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:36:08.133032 Check phy result
697 01:36:08.133567 INFO : End of initialization
698 01:36:08.154742 INFO : End of 2D read delay Voltage center optimization
699 01:36:08.174755 INFO : End of 2D read delay Voltage center optimization
700 01:36:08.226622 INFO : End of 2D write delay Voltage center optimization
701 01:36:08.275863 INFO : End of 2D write delay Voltage center optimization
702 01:36:08.281461 INFO : Training has run successfully!
703 01:36:08.281959
704 01:36:08.282407 channel==0
705 01:36:08.287044 RxClkDly_Margin_A0==88 ps 9
706 01:36:08.287542 TxDqDly_Margin_A0==98 ps 10
707 01:36:08.290370 RxClkDly_Margin_A1==88 ps 9
708 01:36:08.290865 TxDqDly_Margin_A1==98 ps 10
709 01:36:08.295905 TrainedVREFDQ_A0==74
710 01:36:08.296435 TrainedVREFDQ_A1==74
711 01:36:08.301526 VrefDac_Margin_A0==25
712 01:36:08.302018 DeviceVref_Margin_A0==40
713 01:36:08.302465 VrefDac_Margin_A1==25
714 01:36:08.307100 DeviceVref_Margin_A1==40
715 01:36:08.307596
716 01:36:08.308074
717 01:36:08.308522 channel==1
718 01:36:08.308957 RxClkDly_Margin_A0==98 ps 10
719 01:36:08.312724 TxDqDly_Margin_A0==88 ps 9
720 01:36:08.313220 RxClkDly_Margin_A1==88 ps 9
721 01:36:08.318293 TxDqDly_Margin_A1==88 ps 9
722 01:36:08.318789 TrainedVREFDQ_A0==77
723 01:36:08.319237 TrainedVREFDQ_A1==77
724 01:36:08.323881 VrefDac_Margin_A0==22
725 01:36:08.324414 DeviceVref_Margin_A0==37
726 01:36:08.329554 VrefDac_Margin_A1==24
727 01:36:08.330055 DeviceVref_Margin_A1==37
728 01:36:08.330497
729 01:36:08.335105 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:36:08.335609
731 01:36:08.363057 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 01:36:08.368664 2D training succeed
733 01:36:08.374271 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:36:08.374775 auto size-- 65535DDR cs0 size: 2048MB
735 01:36:08.379849 DDR cs1 size: 2048MB
736 01:36:08.380386 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:36:08.385471 cs0 DataBus test pass
738 01:36:08.385966 cs1 DataBus test pass
739 01:36:08.386416 cs0 AddrBus test pass
740 01:36:08.391082 cs1 AddrBus test pass
741 01:36:08.391585
742 01:36:08.392078 100bdlr_step_size ps== 420
743 01:36:08.392541 result report
744 01:36:08.396685 boot times 0Enable ddr reg access
745 01:36:08.404298 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:36:08.417743 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:36:08.989764 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:36:08.990367 MVN_1=0x00000000
749 01:36:08.995229 MVN_2=0x00000000
750 01:36:09.000947 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:36:09.001507 OPS=0x10
752 01:36:09.001958 ring efuse init
753 01:36:09.002395 chipver efuse init
754 01:36:09.006659 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:36:09.012174 [0.018961 Inits done]
756 01:36:09.012660 secure task start!
757 01:36:09.013093 high task start!
758 01:36:09.016740 low task start!
759 01:36:09.017223 run into bl31
760 01:36:09.023393 NOTICE: BL31: v1.3(release):4fc40b1
761 01:36:09.030989 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:36:09.031489 NOTICE: BL31: G12A normal boot!
763 01:36:09.056657 NOTICE: BL31: BL33 decompress pass
764 01:36:09.062265 ERROR: Error initializing runtime service opteed_fast
765 01:36:10.295146
766 01:36:10.295780
767 01:36:10.303600 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:36:10.304142
769 01:36:10.304619 Model: Libre Computer AML-A311D-CC Alta
770 01:36:10.512042 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:36:10.535370 DRAM: 2 GiB (effective 3.8 GiB)
772 01:36:10.678347 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:36:10.684254 WDT: Not starting watchdog@f0d0
774 01:36:10.716472 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:36:10.728896 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:36:10.733964 ** Bad device specification mmc 0 **
777 01:36:10.744311 Card did not respond to voltage select! : -110
778 01:36:10.752009 ** Bad device specification mmc 0 **
779 01:36:10.752519 Couldn't find partition mmc 0
780 01:36:10.760233 Card did not respond to voltage select! : -110
781 01:36:10.765775 ** Bad device specification mmc 0 **
782 01:36:10.766276 Couldn't find partition mmc 0
783 01:36:10.770871 Error: could not access storage.
784 01:36:11.113282 Net: eth0: ethernet@ff3f0000
785 01:36:11.113859 starting USB...
786 01:36:11.365083 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:36:11.365656 Starting the controller
788 01:36:11.372100 USB XHCI 1.10
789 01:36:13.534577 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:36:13.535212 bl2_stage_init 0x01
791 01:36:13.535674 bl2_stage_init 0x81
792 01:36:13.540196 hw id: 0x0000 - pwm id 0x01
793 01:36:13.540700 bl2_stage_init 0xc1
794 01:36:13.541150 bl2_stage_init 0x02
795 01:36:13.541593
796 01:36:13.545770 L0:00000000
797 01:36:13.546273 L1:20000703
798 01:36:13.546721 L2:00008067
799 01:36:13.547162 L3:14000000
800 01:36:13.551386 B2:00402000
801 01:36:13.551887 B1:e0f83180
802 01:36:13.552383
803 01:36:13.552831 TE: 58167
804 01:36:13.553271
805 01:36:13.556974 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:36:13.557482
807 01:36:13.557936 Board ID = 1
808 01:36:13.562566 Set A53 clk to 24M
809 01:36:13.563060 Set A73 clk to 24M
810 01:36:13.563510 Set clk81 to 24M
811 01:36:13.568190 A53 clk: 1200 MHz
812 01:36:13.568689 A73 clk: 1200 MHz
813 01:36:13.569136 CLK81: 166.6M
814 01:36:13.569573 smccc: 00012abe
815 01:36:13.573783 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:36:13.579362 board id: 1
817 01:36:13.585249 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:36:13.595902 fw parse done
819 01:36:13.600917 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:36:13.643542 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:36:13.655387 PIEI prepare done
822 01:36:13.655885 fastboot data load
823 01:36:13.656374 fastboot data verify
824 01:36:13.661089 verify result: 266
825 01:36:13.666712 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:36:13.667232 LPDDR4 probe
827 01:36:13.667694 ddr clk to 1584MHz
828 01:36:13.674649 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:36:13.711900
830 01:36:13.712440 dmc_version 0001
831 01:36:13.718603 Check phy result
832 01:36:13.724490 INFO : End of CA training
833 01:36:13.724984 INFO : End of initialization
834 01:36:13.730070 INFO : Training has run successfully!
835 01:36:13.730566 Check phy result
836 01:36:13.735668 INFO : End of initialization
837 01:36:13.736192 INFO : End of read enable training
838 01:36:13.741274 INFO : End of fine write leveling
839 01:36:13.746880 INFO : End of Write leveling coarse delay
840 01:36:13.747382 INFO : Training has run successfully!
841 01:36:13.747830 Check phy result
842 01:36:13.752549 INFO : End of initialization
843 01:36:13.753072 INFO : End of read dq deskew training
844 01:36:13.758083 INFO : End of MPR read delay center optimization
845 01:36:13.763664 INFO : End of write delay center optimization
846 01:36:13.769286 INFO : End of read delay center optimization
847 01:36:13.769787 INFO : End of max read latency training
848 01:36:13.774835 INFO : Training has run successfully!
849 01:36:13.775332 1D training succeed
850 01:36:13.783009 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:36:13.831670 Check phy result
852 01:36:13.832232 INFO : End of initialization
853 01:36:13.853407 INFO : End of 2D read delay Voltage center optimization
854 01:36:13.872662 INFO : End of 2D read delay Voltage center optimization
855 01:36:13.924746 INFO : End of 2D write delay Voltage center optimization
856 01:36:13.975039 INFO : End of 2D write delay Voltage center optimization
857 01:36:13.980600 INFO : Training has run successfully!
858 01:36:13.981094
859 01:36:13.981543 channel==0
860 01:36:13.986223 RxClkDly_Margin_A0==88 ps 9
861 01:36:13.986727 TxDqDly_Margin_A0==98 ps 10
862 01:36:13.991821 RxClkDly_Margin_A1==88 ps 9
863 01:36:13.992363 TxDqDly_Margin_A1==98 ps 10
864 01:36:13.992831 TrainedVREFDQ_A0==74
865 01:36:13.997484 TrainedVREFDQ_A1==75
866 01:36:13.998007 VrefDac_Margin_A0==25
867 01:36:13.998453 DeviceVref_Margin_A0==40
868 01:36:14.003020 VrefDac_Margin_A1==25
869 01:36:14.003529 DeviceVref_Margin_A1==39
870 01:36:14.003957
871 01:36:14.004423
872 01:36:14.008567 channel==1
873 01:36:14.009047 RxClkDly_Margin_A0==98 ps 10
874 01:36:14.009474 TxDqDly_Margin_A0==98 ps 10
875 01:36:14.014222 RxClkDly_Margin_A1==88 ps 9
876 01:36:14.014726 TxDqDly_Margin_A1==88 ps 9
877 01:36:14.019813 TrainedVREFDQ_A0==77
878 01:36:14.020345 TrainedVREFDQ_A1==77
879 01:36:14.020779 VrefDac_Margin_A0==22
880 01:36:14.025459 DeviceVref_Margin_A0==37
881 01:36:14.025949 VrefDac_Margin_A1==24
882 01:36:14.030985 DeviceVref_Margin_A1==37
883 01:36:14.031467
884 01:36:14.031894 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:36:14.032359
886 01:36:14.064550 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 01:36:14.065074 2D training succeed
888 01:36:14.070198 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:36:14.075807 auto size-- 65535DDR cs0 size: 2048MB
890 01:36:14.076324 DDR cs1 size: 2048MB
891 01:36:14.081471 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:36:14.081957 cs0 DataBus test pass
893 01:36:14.086994 cs1 DataBus test pass
894 01:36:14.087478 cs0 AddrBus test pass
895 01:36:14.087907 cs1 AddrBus test pass
896 01:36:14.088368
897 01:36:14.092605 100bdlr_step_size ps== 420
898 01:36:14.093100 result report
899 01:36:14.098190 boot times 0Enable ddr reg access
900 01:36:14.103567 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:36:14.117009 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:36:14.690593 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:36:14.691239 MVN_1=0x00000000
904 01:36:14.696176 MVN_2=0x00000000
905 01:36:14.701860 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:36:14.702367 OPS=0x10
907 01:36:14.702828 ring efuse init
908 01:36:14.703272 chipver efuse init
909 01:36:14.710010 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:36:14.710529 [0.018960 Inits done]
911 01:36:14.716703 secure task start!
912 01:36:14.717198 high task start!
913 01:36:14.717648 low task start!
914 01:36:14.718090 run into bl31
915 01:36:14.724359 NOTICE: BL31: v1.3(release):4fc40b1
916 01:36:14.732191 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:36:14.732703 NOTICE: BL31: G12A normal boot!
918 01:36:14.757547 NOTICE: BL31: BL33 decompress pass
919 01:36:14.762274 ERROR: Error initializing runtime service opteed_fast
920 01:36:15.996116
921 01:36:15.996754
922 01:36:16.003690 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:36:16.004246
924 01:36:16.004713 Model: Libre Computer AML-A311D-CC Alta
925 01:36:16.212353 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:36:16.235739 DRAM: 2 GiB (effective 3.8 GiB)
927 01:36:16.379402 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:36:16.384883 WDT: Not starting watchdog@f0d0
929 01:36:16.417408 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:36:16.429800 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:36:16.434105 ** Bad device specification mmc 0 **
932 01:36:16.445148 Card did not respond to voltage select! : -110
933 01:36:16.452321 ** Bad device specification mmc 0 **
934 01:36:16.452818 Couldn't find partition mmc 0
935 01:36:16.461135 Card did not respond to voltage select! : -110
936 01:36:16.466679 ** Bad device specification mmc 0 **
937 01:36:16.467180 Couldn't find partition mmc 0
938 01:36:16.470850 Error: could not access storage.
939 01:36:16.813435 Net: eth0: ethernet@ff3f0000
940 01:36:16.814000 starting USB...
941 01:36:17.065958 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:36:17.066510 Starting the controller
943 01:36:17.072438 USB XHCI 1.10
944 01:36:18.934488 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:36:18.935135 bl2_stage_init 0x01
946 01:36:18.935601 bl2_stage_init 0x81
947 01:36:18.940062 hw id: 0x0000 - pwm id 0x01
948 01:36:18.940596 bl2_stage_init 0xc1
949 01:36:18.941058 bl2_stage_init 0x02
950 01:36:18.941504
951 01:36:18.945569 L0:00000000
952 01:36:18.946072 L1:20000703
953 01:36:18.946523 L2:00008067
954 01:36:18.946963 L3:14000000
955 01:36:18.951130 B2:00402000
956 01:36:18.951635 B1:e0f83180
957 01:36:18.952120
958 01:36:18.952573 TE: 58159
959 01:36:18.953021
960 01:36:18.956803 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:36:18.957309
962 01:36:18.957761 Board ID = 1
963 01:36:18.962390 Set A53 clk to 24M
964 01:36:18.962891 Set A73 clk to 24M
965 01:36:18.963341 Set clk81 to 24M
966 01:36:18.967958 A53 clk: 1200 MHz
967 01:36:18.968479 A73 clk: 1200 MHz
968 01:36:18.968935 CLK81: 166.6M
969 01:36:18.969378 smccc: 00012ab5
970 01:36:18.973547 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:36:18.979220 board id: 1
972 01:36:18.984924 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:36:18.995696 fw parse done
974 01:36:19.000908 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:36:19.043349 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:36:19.055094 PIEI prepare done
977 01:36:19.055586 fastboot data load
978 01:36:19.056064 fastboot data verify
979 01:36:19.060792 verify result: 266
980 01:36:19.066371 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:36:19.066863 LPDDR4 probe
982 01:36:19.067291 ddr clk to 1584MHz
983 01:36:19.073472 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:36:19.111096
985 01:36:19.111582 dmc_version 0001
986 01:36:19.117309 Check phy result
987 01:36:19.124227 INFO : End of CA training
988 01:36:19.124720 INFO : End of initialization
989 01:36:19.129754 INFO : Training has run successfully!
990 01:36:19.130245 Check phy result
991 01:36:19.135406 INFO : End of initialization
992 01:36:19.135921 INFO : End of read enable training
993 01:36:19.141034 INFO : End of fine write leveling
994 01:36:19.146547 INFO : End of Write leveling coarse delay
995 01:36:19.147045 INFO : Training has run successfully!
996 01:36:19.147490 Check phy result
997 01:36:19.152167 INFO : End of initialization
998 01:36:19.152659 INFO : End of read dq deskew training
999 01:36:19.157778 INFO : End of MPR read delay center optimization
1000 01:36:19.163359 INFO : End of write delay center optimization
1001 01:36:19.168955 INFO : End of read delay center optimization
1002 01:36:19.169457 INFO : End of max read latency training
1003 01:36:19.174571 INFO : Training has run successfully!
1004 01:36:19.175071 1D training succeed
1005 01:36:19.183289 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:36:19.231260 Check phy result
1007 01:36:19.231786 INFO : End of initialization
1008 01:36:19.252648 INFO : End of 2D read delay Voltage center optimization
1009 01:36:19.272507 INFO : End of 2D read delay Voltage center optimization
1010 01:36:19.324480 INFO : End of 2D write delay Voltage center optimization
1011 01:36:19.374171 INFO : End of 2D write delay Voltage center optimization
1012 01:36:19.379766 INFO : Training has run successfully!
1013 01:36:19.380302
1014 01:36:19.380774 channel==0
1015 01:36:19.385381 RxClkDly_Margin_A0==88 ps 9
1016 01:36:19.385892 TxDqDly_Margin_A0==98 ps 10
1017 01:36:19.390984 RxClkDly_Margin_A1==88 ps 9
1018 01:36:19.391482 TxDqDly_Margin_A1==88 ps 9
1019 01:36:19.391938 TrainedVREFDQ_A0==74
1020 01:36:19.396532 TrainedVREFDQ_A1==74
1021 01:36:19.397037 VrefDac_Margin_A0==25
1022 01:36:19.397488 DeviceVref_Margin_A0==40
1023 01:36:19.402172 VrefDac_Margin_A1==25
1024 01:36:19.402671 DeviceVref_Margin_A1==40
1025 01:36:19.403117
1026 01:36:19.403557
1027 01:36:19.404023 channel==1
1028 01:36:19.407760 RxClkDly_Margin_A0==98 ps 10
1029 01:36:19.408303 TxDqDly_Margin_A0==88 ps 9
1030 01:36:19.413385 RxClkDly_Margin_A1==88 ps 9
1031 01:36:19.413895 TxDqDly_Margin_A1==88 ps 9
1032 01:36:19.418971 TrainedVREFDQ_A0==77
1033 01:36:19.419472 TrainedVREFDQ_A1==77
1034 01:36:19.419921 VrefDac_Margin_A0==22
1035 01:36:19.424591 DeviceVref_Margin_A0==37
1036 01:36:19.425091 VrefDac_Margin_A1==24
1037 01:36:19.430204 DeviceVref_Margin_A1==37
1038 01:36:19.430698
1039 01:36:19.431148 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:36:19.431588
1041 01:36:19.463723 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 01:36:19.464286 2D training succeed
1043 01:36:19.469377 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:36:19.474979 auto size-- 65535DDR cs0 size: 2048MB
1045 01:36:19.475479 DDR cs1 size: 2048MB
1046 01:36:19.480562 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:36:19.481057 cs0 DataBus test pass
1048 01:36:19.486188 cs1 DataBus test pass
1049 01:36:19.486680 cs0 AddrBus test pass
1050 01:36:19.487134 cs1 AddrBus test pass
1051 01:36:19.487580
1052 01:36:19.491768 100bdlr_step_size ps== 420
1053 01:36:19.492306 result report
1054 01:36:19.497342 boot times 0Enable ddr reg access
1055 01:36:19.502085 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:36:19.515781 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:36:20.087957 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:36:20.088633 MVN_1=0x00000000
1059 01:36:20.093594 MVN_2=0x00000000
1060 01:36:20.099188 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:36:20.099685 OPS=0x10
1062 01:36:20.100181 ring efuse init
1063 01:36:20.100638 chipver efuse init
1064 01:36:20.104748 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:36:20.110387 [0.018961 Inits done]
1066 01:36:20.110879 secure task start!
1067 01:36:20.111349 high task start!
1068 01:36:20.114302 low task start!
1069 01:36:20.114790 run into bl31
1070 01:36:20.121556 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:36:20.128635 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:36:20.129119 NOTICE: BL31: G12A normal boot!
1073 01:36:20.154816 NOTICE: BL31: BL33 decompress pass
1074 01:36:20.160485 ERROR: Error initializing runtime service opteed_fast
1075 01:36:21.393451
1076 01:36:21.394029
1077 01:36:21.401743 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:36:21.402205
1079 01:36:21.402643 Model: Libre Computer AML-A311D-CC Alta
1080 01:36:21.610171 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:36:21.633610 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:36:21.776567 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:36:21.782477 WDT: Not starting watchdog@f0d0
1084 01:36:21.814670 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:36:21.827221 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:36:21.832162 ** Bad device specification mmc 0 **
1087 01:36:21.842477 Card did not respond to voltage select! : -110
1088 01:36:21.850124 ** Bad device specification mmc 0 **
1089 01:36:21.850580 Couldn't find partition mmc 0
1090 01:36:21.858479 Card did not respond to voltage select! : -110
1091 01:36:21.864044 ** Bad device specification mmc 0 **
1092 01:36:21.864501 Couldn't find partition mmc 0
1093 01:36:21.869057 Error: could not access storage.
1094 01:36:22.212574 Net: eth0: ethernet@ff3f0000
1095 01:36:22.213104 starting USB...
1096 01:36:22.464385 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:36:22.464891 Starting the controller
1098 01:36:22.471311 USB XHCI 1.10
1099 01:36:24.025750 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:36:24.034058 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:36:24.085712 Hit any key to stop autoboot: 1
1103 01:36:24.086483 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:36:24.087078 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1105 01:36:24.087540 Setting prompt string to ['=>']
1106 01:36:24.088044 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1107 01:36:24.101482 0
1108 01:36:24.102404 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:36:24.102895 Sending with 10 millisecond of delay
1111 01:36:25.237348 => setenv autoload no
1112 01:36:25.248146 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 01:36:25.253050 setenv autoload no
1114 01:36:25.253808 Sending with 10 millisecond of delay
1116 01:36:27.050370 => setenv initrd_high 0xffffffff
1117 01:36:27.061116 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1118 01:36:27.061964 setenv initrd_high 0xffffffff
1119 01:36:27.062677 Sending with 10 millisecond of delay
1121 01:36:28.678575 => setenv fdt_high 0xffffffff
1122 01:36:28.689301 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:36:28.690128 setenv fdt_high 0xffffffff
1124 01:36:28.690827 Sending with 10 millisecond of delay
1126 01:36:28.982568 => dhcp
1127 01:36:28.993268 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:36:28.993901 dhcp
1129 01:36:28.994345 Speed: 1000, full duplex
1130 01:36:28.994752 BOOTP broadcast 1
1131 01:36:29.000764 DHCP client bound to address 192.168.6.27 (8 ms)
1132 01:36:29.001499 Sending with 10 millisecond of delay
1134 01:36:30.677554 => setenv serverip 192.168.6.2
1135 01:36:30.688332 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 01:36:30.689202 setenv serverip 192.168.6.2
1137 01:36:30.689882 Sending with 10 millisecond of delay
1139 01:36:34.412387 => tftpboot 0x01080000 919392/tftp-deploy-b1r4wf5g/kernel/uImage
1140 01:36:34.423132 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 01:36:34.423957 tftpboot 0x01080000 919392/tftp-deploy-b1r4wf5g/kernel/uImage
1142 01:36:34.424459 Speed: 1000, full duplex
1143 01:36:34.424873 Using ethernet@ff3f0000 device
1144 01:36:34.425706 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 01:36:34.431238 Filename '919392/tftp-deploy-b1r4wf5g/kernel/uImage'.
1146 01:36:34.435168 Load address: 0x1080000
1147 01:36:37.349788 Loading: *################################################## 43.6 MiB
1148 01:36:37.350214 14.9 MiB/s
1149 01:36:37.350422 done
1150 01:36:37.354385 Bytes transferred = 45713984 (2b98a40 hex)
1151 01:36:37.354884 Sending with 10 millisecond of delay
1153 01:36:42.038991 => tftpboot 0x08000000 919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot
1154 01:36:42.049581 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1155 01:36:42.050037 tftpboot 0x08000000 919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot
1156 01:36:42.050274 Speed: 1000, full duplex
1157 01:36:42.050487 Using ethernet@ff3f0000 device
1158 01:36:42.052394 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 01:36:42.061027 Filename '919392/tftp-deploy-b1r4wf5g/ramdisk/ramdisk.cpio.gz.uboot'.
1160 01:36:42.061296 Load address: 0x8000000
1161 01:36:43.460249 Loading: *##################### UDP wrong checksum 000000ff 000083df
1162 01:36:43.489189 UDP wrong checksum 000000ff 00001ad2
1163 01:36:48.018382 T ######## UDP wrong checksum 000000ff 00002955
1164 01:36:48.081733 # UDP wrong checksum 000000ff 0000ae47
1165 01:36:48.909023 ################### UDP wrong checksum 00000005 0000e09d
1166 01:36:53.909541 T UDP wrong checksum 00000005 0000e09d
1167 01:37:03.911537 T T UDP wrong checksum 00000005 0000e09d
1168 01:37:23.915596 T T T T UDP wrong checksum 00000005 0000e09d
1169 01:37:38.919696 T T
1170 01:37:38.920430 Retry count exceeded; starting again
1172 01:37:38.921958 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 01:37:38.923972 end: 2.4 uboot-commands (duration 00:01:52) [common]
1177 01:37:38.925563 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 01:37:38.926602 end: 2 uboot-action (duration 00:01:52) [common]
1181 01:37:38.928271 Cleaning after the job
1182 01:37:38.928830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/ramdisk
1183 01:37:38.930108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/kernel
1184 01:37:38.979554 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/dtb
1185 01:37:38.980450 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/nfsrootfs
1186 01:37:39.288772 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/919392/tftp-deploy-b1r4wf5g/modules
1187 01:37:39.310895 start: 4.1 power-off (timeout 00:00:30) [common]
1188 01:37:39.311578 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 01:37:39.355704 >> OK - accepted request
1190 01:37:39.358038 Returned 0 in 0 seconds
1191 01:37:39.458987 end: 4.1 power-off (duration 00:00:00) [common]
1193 01:37:39.460126 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 01:37:39.461013 Listened to connection for namespace 'common' for up to 1s
1195 01:37:40.461744 Finalising connection for namespace 'common'
1196 01:37:40.462246 Disconnecting from shell: Finalise
1197 01:37:40.462546 =>
1198 01:37:40.563265 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 01:37:40.563755 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/919392
1200 01:37:43.100928 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/919392
1201 01:37:43.101588 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.