Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 59
1 05:37:29.143070 lava-dispatcher, installed at version: 2024.01
2 05:37:29.143828 start: 0 validate
3 05:37:29.144339 Start time: 2024-11-02 05:37:29.144308+00:00 (UTC)
4 05:37:29.144873 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:37:29.145426 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 05:37:29.191008 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:37:29.191580 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 05:37:29.223649 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:37:29.224295 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 05:37:29.254714 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:37:29.255195 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 05:37:29.285185 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:37:29.285735 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 05:37:29.325585 validate duration: 0.18
16 05:37:29.327134 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:37:29.327794 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:37:29.328405 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:37:29.329363 Not decompressing ramdisk as can be used compressed.
20 05:37:29.330011 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 05:37:29.330478 saving as /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/ramdisk/initrd.cpio.gz
22 05:37:29.330975 total size: 4775763 (4 MB)
23 05:37:29.368518 progress 0 % (0 MB)
24 05:37:29.372317 progress 5 % (0 MB)
25 05:37:29.375626 progress 10 % (0 MB)
26 05:37:29.381457 progress 15 % (0 MB)
27 05:37:29.386362 progress 20 % (0 MB)
28 05:37:29.389471 progress 25 % (1 MB)
29 05:37:29.392548 progress 30 % (1 MB)
30 05:37:29.395963 progress 35 % (1 MB)
31 05:37:29.398993 progress 40 % (1 MB)
32 05:37:29.402132 progress 45 % (2 MB)
33 05:37:29.405233 progress 50 % (2 MB)
34 05:37:29.408969 progress 55 % (2 MB)
35 05:37:29.412397 progress 60 % (2 MB)
36 05:37:29.415783 progress 65 % (2 MB)
37 05:37:29.419225 progress 70 % (3 MB)
38 05:37:29.422263 progress 75 % (3 MB)
39 05:37:29.425167 progress 80 % (3 MB)
40 05:37:29.428136 progress 85 % (3 MB)
41 05:37:29.431296 progress 90 % (4 MB)
42 05:37:29.434105 progress 95 % (4 MB)
43 05:37:29.436961 progress 100 % (4 MB)
44 05:37:29.437612 4 MB downloaded in 0.11 s (42.71 MB/s)
45 05:37:29.438199 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:37:29.439205 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:37:29.439549 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:37:29.439882 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:37:29.440442 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 05:37:29.440731 saving as /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/kernel/zImage
52 05:37:29.440963 total size: 12050944 (11 MB)
53 05:37:29.441211 No compression specified
54 05:37:29.475920 progress 0 % (0 MB)
55 05:37:29.483412 progress 5 % (0 MB)
56 05:37:29.491301 progress 10 % (1 MB)
57 05:37:29.499283 progress 15 % (1 MB)
58 05:37:29.506835 progress 20 % (2 MB)
59 05:37:29.514451 progress 25 % (2 MB)
60 05:37:29.522453 progress 30 % (3 MB)
61 05:37:29.532115 progress 35 % (4 MB)
62 05:37:29.539694 progress 40 % (4 MB)
63 05:37:29.546879 progress 45 % (5 MB)
64 05:37:29.554135 progress 50 % (5 MB)
65 05:37:29.561750 progress 55 % (6 MB)
66 05:37:29.568968 progress 60 % (6 MB)
67 05:37:29.576534 progress 65 % (7 MB)
68 05:37:29.583787 progress 70 % (8 MB)
69 05:37:29.591079 progress 75 % (8 MB)
70 05:37:29.598683 progress 80 % (9 MB)
71 05:37:29.605940 progress 85 % (9 MB)
72 05:37:29.613139 progress 90 % (10 MB)
73 05:37:29.620383 progress 95 % (10 MB)
74 05:37:29.627219 progress 100 % (11 MB)
75 05:37:29.627892 11 MB downloaded in 0.19 s (61.49 MB/s)
76 05:37:29.628409 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:37:29.629244 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:37:29.629523 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:37:29.629795 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:37:29.630266 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 05:37:29.630550 saving as /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/dtb/am335x-boneblack.dtb
83 05:37:29.630762 total size: 70568 (0 MB)
84 05:37:29.630975 No compression specified
85 05:37:29.667403 progress 46 % (0 MB)
86 05:37:29.668279 progress 92 % (0 MB)
87 05:37:29.668960 progress 100 % (0 MB)
88 05:37:29.669357 0 MB downloaded in 0.04 s (1.74 MB/s)
89 05:37:29.669875 end: 1.3.1 http-download (duration 00:00:00) [common]
91 05:37:29.671156 end: 1.3 download-retry (duration 00:00:00) [common]
92 05:37:29.671453 start: 1.4 download-retry (timeout 00:10:00) [common]
93 05:37:29.671728 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 05:37:29.672235 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 05:37:29.672514 saving as /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/nfsrootfs/full.rootfs.tar
96 05:37:29.672723 total size: 117747780 (112 MB)
97 05:37:29.672939 Using unxz to decompress xz
98 05:37:29.708767 progress 0 % (0 MB)
99 05:37:30.454370 progress 5 % (5 MB)
100 05:37:31.194067 progress 10 % (11 MB)
101 05:37:31.959789 progress 15 % (16 MB)
102 05:37:32.673153 progress 20 % (22 MB)
103 05:37:33.256461 progress 25 % (28 MB)
104 05:37:34.068618 progress 30 % (33 MB)
105 05:37:34.869962 progress 35 % (39 MB)
106 05:37:35.195257 progress 40 % (44 MB)
107 05:37:35.560597 progress 45 % (50 MB)
108 05:37:36.214020 progress 50 % (56 MB)
109 05:37:37.024814 progress 55 % (61 MB)
110 05:37:37.747425 progress 60 % (67 MB)
111 05:37:38.458184 progress 65 % (73 MB)
112 05:37:39.206727 progress 70 % (78 MB)
113 05:37:39.973375 progress 75 % (84 MB)
114 05:37:40.809626 progress 80 % (89 MB)
115 05:37:41.538535 progress 85 % (95 MB)
116 05:37:42.350333 progress 90 % (101 MB)
117 05:37:43.260827 progress 95 % (106 MB)
118 05:37:44.233259 progress 100 % (112 MB)
119 05:37:44.247836 112 MB downloaded in 14.58 s (7.70 MB/s)
120 05:37:44.248749 end: 1.4.1 http-download (duration 00:00:15) [common]
122 05:37:44.250347 end: 1.4 download-retry (duration 00:00:15) [common]
123 05:37:44.250858 start: 1.5 download-retry (timeout 00:09:45) [common]
124 05:37:44.251359 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 05:37:44.252256 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 05:37:44.252531 saving as /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/modules/modules.tar
127 05:37:44.252747 total size: 6909812 (6 MB)
128 05:37:44.252962 Using unxz to decompress xz
129 05:37:44.297878 progress 0 % (0 MB)
130 05:37:44.333571 progress 5 % (0 MB)
131 05:37:44.380604 progress 10 % (0 MB)
132 05:37:44.425354 progress 15 % (1 MB)
133 05:37:44.473021 progress 20 % (1 MB)
134 05:37:44.517876 progress 25 % (1 MB)
135 05:37:44.567069 progress 30 % (2 MB)
136 05:37:44.610391 progress 35 % (2 MB)
137 05:37:44.658444 progress 40 % (2 MB)
138 05:37:44.702657 progress 45 % (2 MB)
139 05:37:44.751069 progress 50 % (3 MB)
140 05:37:44.794101 progress 55 % (3 MB)
141 05:37:44.841988 progress 60 % (3 MB)
142 05:37:44.888953 progress 65 % (4 MB)
143 05:37:44.930490 progress 70 % (4 MB)
144 05:37:44.981392 progress 75 % (4 MB)
145 05:37:45.027429 progress 80 % (5 MB)
146 05:37:45.076257 progress 85 % (5 MB)
147 05:37:45.119821 progress 90 % (5 MB)
148 05:37:45.171621 progress 95 % (6 MB)
149 05:37:45.215022 progress 100 % (6 MB)
150 05:37:45.229127 6 MB downloaded in 0.98 s (6.75 MB/s)
151 05:37:45.230112 end: 1.5.1 http-download (duration 00:00:01) [common]
153 05:37:45.231835 end: 1.5 download-retry (duration 00:00:01) [common]
154 05:37:45.232490 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 05:37:45.233084 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 05:38:02.221856 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk
157 05:38:02.222479 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 05:38:02.222770 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 05:38:02.223499 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c
160 05:38:02.223964 makedir: /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin
161 05:38:02.224367 makedir: /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/tests
162 05:38:02.224816 makedir: /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/results
163 05:38:02.225203 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-add-keys
164 05:38:02.225745 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-add-sources
165 05:38:02.226263 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-background-process-start
166 05:38:02.226780 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-background-process-stop
167 05:38:02.227351 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-common-functions
168 05:38:02.227888 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-echo-ipv4
169 05:38:02.228451 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-install-packages
170 05:38:02.228946 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-installed-packages
171 05:38:02.229458 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-os-build
172 05:38:02.229984 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-probe-channel
173 05:38:02.230501 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-probe-ip
174 05:38:02.231006 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-target-ip
175 05:38:02.231599 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-target-mac
176 05:38:02.232146 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-target-storage
177 05:38:02.232684 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-case
178 05:38:02.233218 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-event
179 05:38:02.233708 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-feedback
180 05:38:02.234201 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-raise
181 05:38:02.234700 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-reference
182 05:38:02.235197 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-runner
183 05:38:02.235700 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-set
184 05:38:02.236230 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-test-shell
185 05:38:02.236765 Updating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-add-keys (debian)
186 05:38:02.237359 Updating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-add-sources (debian)
187 05:38:02.237904 Updating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-install-packages (debian)
188 05:38:02.238417 Updating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-installed-packages (debian)
189 05:38:02.238918 Updating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/bin/lava-os-build (debian)
190 05:38:02.239360 Creating /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/environment
191 05:38:02.239787 LAVA metadata
192 05:38:02.240090 - LAVA_JOB_ID=927075
193 05:38:02.240313 - LAVA_DISPATCHER_IP=192.168.6.2
194 05:38:02.240705 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 05:38:02.241687 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 05:38:02.242011 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 05:38:02.242220 skipped lava-vland-overlay
198 05:38:02.242466 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 05:38:02.242722 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 05:38:02.242945 skipped lava-multinode-overlay
201 05:38:02.243188 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 05:38:02.243438 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 05:38:02.243690 Loading test definitions
204 05:38:02.243969 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 05:38:02.244232 Using /lava-927075 at stage 0
206 05:38:02.245389 uuid=927075_1.6.2.4.1 testdef=None
207 05:38:02.245708 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 05:38:02.245975 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 05:38:02.247541 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 05:38:02.248360 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 05:38:02.250331 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 05:38:02.251176 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 05:38:02.253134 runner path: /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/0/tests/0_timesync-off test_uuid 927075_1.6.2.4.1
216 05:38:02.253710 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 05:38:02.254535 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 05:38:02.254764 Using /lava-927075 at stage 0
220 05:38:02.255128 Fetching tests from https://github.com/kernelci/test-definitions.git
221 05:38:02.255427 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/0/tests/1_kselftest-dt'
222 05:38:05.703607 Running '/usr/bin/git checkout kernelci.org
223 05:38:06.166998 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 05:38:06.168495 uuid=927075_1.6.2.4.5 testdef=None
225 05:38:06.168855 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 05:38:06.169607 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 05:38:06.172482 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 05:38:06.173306 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 05:38:06.177060 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 05:38:06.177923 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 05:38:06.181535 runner path: /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/0/tests/1_kselftest-dt test_uuid 927075_1.6.2.4.5
235 05:38:06.181831 BOARD='beaglebone-black'
236 05:38:06.182037 BRANCH='mainline'
237 05:38:06.182234 SKIPFILE='/dev/null'
238 05:38:06.182432 SKIP_INSTALL='True'
239 05:38:06.182624 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 05:38:06.182823 TST_CASENAME=''
241 05:38:06.183016 TST_CMDFILES='dt'
242 05:38:06.183581 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 05:38:06.184404 Creating lava-test-runner.conf files
245 05:38:06.184612 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927075/lava-overlay-h18las_c/lava-927075/0 for stage 0
246 05:38:06.184977 - 0_timesync-off
247 05:38:06.185229 - 1_kselftest-dt
248 05:38:06.185569 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 05:38:06.185856 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 05:38:29.639048 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 05:38:29.639510 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 05:38:29.639809 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 05:38:29.640152 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 05:38:29.640456 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 05:38:30.001743 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 05:38:30.002238 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 05:38:30.002597 extracting modules file /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk
258 05:38:31.046877 extracting modules file /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927075/extract-overlay-ramdisk-1m54hu3e/ramdisk
259 05:38:31.958416 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 05:38:31.958916 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 05:38:31.959221 [common] Applying overlay to NFS
262 05:38:31.959453 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927075/compress-overlay-yip8oqk6/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk
263 05:38:34.697502 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 05:38:34.697947 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 05:38:34.698252 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 05:38:34.698566 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 05:38:34.698846 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 05:38:34.699119 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 05:38:34.699392 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 05:38:34.699668 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 05:38:34.699931 Building ramdisk /var/lib/lava/dispatcher/tmp/927075/extract-overlay-ramdisk-1m54hu3e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927075/extract-overlay-ramdisk-1m54hu3e/ramdisk
272 05:38:35.756689 >> 79010 blocks
273 05:38:40.780668 Adding RAMdisk u-boot header.
274 05:38:40.781127 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927075/extract-overlay-ramdisk-1m54hu3e/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927075/extract-overlay-ramdisk-1m54hu3e/ramdisk.cpio.gz.uboot
275 05:38:40.959743 output: Image Name:
276 05:38:40.960307 output: Created: Sat Nov 2 05:38:40 2024
277 05:38:40.960776 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 05:38:40.961230 output: Data Size: 15354092 Bytes = 14994.23 KiB = 14.64 MiB
279 05:38:40.961676 output: Load Address: 00000000
280 05:38:40.962113 output: Entry Point: 00000000
281 05:38:40.962548 output:
282 05:38:40.963700 rename /var/lib/lava/dispatcher/tmp/927075/extract-overlay-ramdisk-1m54hu3e/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot
283 05:38:40.964514 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 05:38:40.965115 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 05:38:40.965696 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 05:38:40.966196 No LXC device requested
287 05:38:40.966744 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 05:38:40.967305 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 05:38:40.967850 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 05:38:40.968346 Checking files for TFTP limit of 4294967296 bytes.
291 05:38:40.971248 end: 1 tftp-deploy (duration 00:01:12) [common]
292 05:38:40.971876 start: 2 uboot-action (timeout 00:05:00) [common]
293 05:38:40.972497 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 05:38:40.973047 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 05:38:40.973597 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 05:38:40.974410 substitutions:
297 05:38:40.974870 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 05:38:40.975314 - {DTB_ADDR}: 0x88000000
299 05:38:40.975754 - {DTB}: 927075/tftp-deploy-abo80gkx/dtb/am335x-boneblack.dtb
300 05:38:40.976229 - {INITRD}: 927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot
301 05:38:40.976671 - {KERNEL_ADDR}: 0x82000000
302 05:38:40.977105 - {KERNEL}: 927075/tftp-deploy-abo80gkx/kernel/zImage
303 05:38:40.977539 - {LAVA_MAC}: None
304 05:38:40.978013 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk
305 05:38:40.978453 - {NFS_SERVER_IP}: 192.168.6.2
306 05:38:40.978886 - {PRESEED_CONFIG}: None
307 05:38:40.979316 - {PRESEED_LOCAL}: None
308 05:38:40.979746 - {RAMDISK_ADDR}: 0x83000000
309 05:38:40.980210 - {RAMDISK}: 927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot
310 05:38:40.980649 - {ROOT_PART}: None
311 05:38:40.981077 - {ROOT}: None
312 05:38:40.981504 - {SERVER_IP}: 192.168.6.2
313 05:38:40.981931 - {TEE_ADDR}: 0x83000000
314 05:38:40.982355 - {TEE}: None
315 05:38:40.982786 Parsed boot commands:
316 05:38:40.983201 - setenv autoload no
317 05:38:40.983624 - setenv initrd_high 0xffffffff
318 05:38:40.984071 - setenv fdt_high 0xffffffff
319 05:38:40.984499 - dhcp
320 05:38:40.984924 - setenv serverip 192.168.6.2
321 05:38:40.985349 - tftp 0x82000000 927075/tftp-deploy-abo80gkx/kernel/zImage
322 05:38:40.985775 - tftp 0x83000000 927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot
323 05:38:40.986200 - setenv initrd_size ${filesize}
324 05:38:40.986621 - tftp 0x88000000 927075/tftp-deploy-abo80gkx/dtb/am335x-boneblack.dtb
325 05:38:40.987044 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 05:38:40.987482 - bootz 0x82000000 0x83000000 0x88000000
327 05:38:40.988042 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 05:38:40.989669 start: 2.3 connect-device (timeout 00:05:00) [common]
330 05:38:40.990130 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 05:38:41.006971 Setting prompt string to ['lava-test: # ']
332 05:38:41.008604 end: 2.3 connect-device (duration 00:00:00) [common]
333 05:38:41.009257 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 05:38:41.009863 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 05:38:41.010437 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 05:38:41.011705 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 05:38:41.049474 >> OK - accepted request
338 05:38:41.051612 Returned 0 in 0 seconds
339 05:38:41.152842 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 05:38:41.154551 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 05:38:41.155163 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 05:38:41.155734 Setting prompt string to ['Hit any key to stop autoboot']
344 05:38:41.156312 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 05:38:41.158001 Trying 192.168.56.22...
346 05:38:41.158525 Connected to conserv3.
347 05:38:41.158986 Escape character is '^]'.
348 05:38:41.159436
349 05:38:41.159893 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 05:38:41.160384
351 05:39:19.038987
352 05:39:19.045878 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 05:39:19.046390 Trying to boot from MMC1
354 05:39:19.621476
355 05:39:19.622143
356 05:39:19.626750 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 05:39:19.627252
358 05:39:19.627701 CPU : AM335X-GP rev 2.0
359 05:39:19.631862 Model: TI AM335x BeagleBone Black
360 05:39:19.632386 DRAM: 512 MiB
361 05:39:19.716394 Core: 160 devices, 18 uclasses, devicetree: separate
362 05:39:19.730230 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 05:39:20.130295 NAND: 0 MiB
364 05:39:20.140977 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 05:39:20.215882 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 05:39:20.237024 <ethaddr> not set. Validating first E-fuse MAC
367 05:39:20.266900 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 05:39:20.325432 Hit any key to stop autoboot: 2
370 05:39:20.326281 end: 2.4.2 bootloader-interrupt (duration 00:00:39) [common]
371 05:39:20.326998 start: 2.4.3 bootloader-commands (timeout 00:04:21) [common]
372 05:39:20.327527 Setting prompt string to ['=>']
373 05:39:20.328113 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:21)
374 05:39:20.335223 0
375 05:39:20.336199 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 05:39:20.336765 Sending with 10 millisecond of delay
378 05:39:21.471582 => setenv autoload no
379 05:39:21.482441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
380 05:39:21.487800 setenv autoload no
381 05:39:21.488628 Sending with 10 millisecond of delay
383 05:39:23.286445 => setenv initrd_high 0xffffffff
384 05:39:23.297703 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
385 05:39:23.299070 setenv initrd_high 0xffffffff
386 05:39:23.300210 Sending with 10 millisecond of delay
388 05:39:24.918277 => setenv fdt_high 0xffffffff
389 05:39:24.928815 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
390 05:39:24.929386 setenv fdt_high 0xffffffff
391 05:39:24.930264 Sending with 10 millisecond of delay
393 05:39:25.221821 => dhcp
394 05:39:25.232632 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
395 05:39:25.233536 dhcp
396 05:39:25.234007 link up on port 0, speed 100, full duplex
397 05:39:25.234455 BOOTP broadcast 1
398 05:39:25.330570 DHCP client bound to address 192.168.6.16 (92 ms)
399 05:39:25.331419 Sending with 10 millisecond of delay
401 05:39:27.008388 => setenv serverip 192.168.6.2
402 05:39:27.019252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
403 05:39:27.020262 setenv serverip 192.168.6.2
404 05:39:27.021038 Sending with 10 millisecond of delay
406 05:39:30.505203 => tftp 0x82000000 927075/tftp-deploy-abo80gkx/kernel/zImage
407 05:39:30.516031 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
408 05:39:30.516930 tftp 0x82000000 927075/tftp-deploy-abo80gkx/kernel/zImage
409 05:39:30.517365 link up on port 0, speed 100, full duplex
410 05:39:30.520860 Using ethernet@4a100000 device
411 05:39:30.526439 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 05:39:30.526872 Filename '927075/tftp-deploy-abo80gkx/kernel/zImage'.
413 05:39:30.529931 Load address: 0x82000000
414 05:39:32.813313 Loading: *################################################## 11.5 MiB
415 05:39:32.813757 5 MiB/s
416 05:39:32.814012 done
417 05:39:32.817375 Bytes transferred = 12050944 (b7e200 hex)
418 05:39:32.818060 Sending with 10 millisecond of delay
420 05:39:37.265503 => tftp 0x83000000 927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot
421 05:39:37.278325 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
422 05:39:37.279228 tftp 0x83000000 927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot
423 05:39:37.279674 link up on port 0, speed 100, full duplex
424 05:39:37.283216 Using ethernet@4a100000 device
425 05:39:37.288991 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 05:39:37.292168 Filename '927075/tftp-deploy-abo80gkx/ramdisk/ramdisk.cpio.gz.uboot'.
427 05:39:37.297194 Load address: 0x83000000
428 05:39:40.342814 Loading: *################################################## 14.6 MiB
429 05:39:40.343432 4.8 MiB/s
430 05:39:40.343864 done
431 05:39:40.347003 Bytes transferred = 15354156 (ea492c hex)
432 05:39:40.347754 Sending with 10 millisecond of delay
434 05:39:42.205370 => setenv initrd_size ${filesize}
435 05:39:42.216195 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
436 05:39:42.217035 setenv initrd_size ${filesize}
437 05:39:42.217757 Sending with 10 millisecond of delay
439 05:39:46.363720 => tftp 0x88000000 927075/tftp-deploy-abo80gkx/dtb/am335x-boneblack.dtb
440 05:39:46.374703 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:55)
441 05:39:46.375772 tftp 0x88000000 927075/tftp-deploy-abo80gkx/dtb/am335x-boneblack.dtb
442 05:39:46.376326 link up on port 0, speed 100, full duplex
443 05:39:46.379502 Using ethernet@4a100000 device
444 05:39:46.385099 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 05:39:46.393411 Filename '927075/tftp-deploy-abo80gkx/dtb/am335x-boneblack.dtb'.
446 05:39:46.393822 Load address: 0x88000000
447 05:39:46.405808 Loading: *################################################## 68.9 KiB
448 05:39:46.413822 4.5 MiB/s
449 05:39:46.414251 done
450 05:39:46.414471 Bytes transferred = 70568 (113a8 hex)
451 05:39:46.414956 Sending with 10 millisecond of delay
453 05:39:59.587204 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 05:39:59.598021 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
455 05:39:59.598914 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 05:39:59.599626 Sending with 10 millisecond of delay
458 05:40:01.937798 => bootz 0x82000000 0x83000000 0x88000000
459 05:40:01.948600 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 05:40:01.949150 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
461 05:40:01.950133 bootz 0x82000000 0x83000000 0x88000000
462 05:40:01.950735 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
463 05:40:01.951253 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 05:40:01.956291 Image Name:
465 05:40:01.956779 Created: 2024-11-02 5:38:40 UTC
466 05:40:01.961846 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 05:40:01.967482 Data Size: 15354092 Bytes = 14.6 MiB
468 05:40:01.967949 Load Address: 00000000
469 05:40:01.973570 Entry Point: 00000000
470 05:40:02.148110 Verifying Checksum ... OK
471 05:40:02.148640 ## Flattened Device Tree blob at 88000000
472 05:40:02.154639 Booting using the fdt blob at 0x88000000
473 05:40:02.155118 Working FDT set to 88000000
474 05:40:02.160230 Using Device Tree in place at 88000000, end 880143a7
475 05:40:02.164561 Working FDT set to 88000000
476 05:40:02.177812
477 05:40:02.178313 Starting kernel ...
478 05:40:02.178725
479 05:40:02.179601 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 05:40:02.180245 start: 2.4.4 auto-login-action (timeout 00:03:39) [common]
481 05:40:02.180729 Setting prompt string to ['Linux version [0-9]']
482 05:40:02.181199 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 05:40:02.181668 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 05:40:03.067913 [ 0.000000] Booting Linux on physical CPU 0x0
485 05:40:03.073921 start: 2.4.4.1 login-action (timeout 00:03:38) [common]
486 05:40:03.074489 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 05:40:03.074956 Setting prompt string to []
488 05:40:03.075433 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 05:40:03.075885 Using line separator: #'\n'#
490 05:40:03.076332 No login prompt set.
491 05:40:03.076767 Parsing kernel messages
492 05:40:03.077166 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 05:40:03.077926 [login-action] Waiting for messages, (timeout 00:03:38)
494 05:40:03.078374 Waiting using forced prompt support (timeout 00:01:49)
495 05:40:03.085049 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j359649-arm-clang-15-multi-v7-defconfig-ccbz4) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sat Nov 2 04:26:45 UTC 2024
496 05:40:03.090717 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 05:40:03.102110 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 05:40:03.107977 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 05:40:03.113682 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 05:40:03.119408 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 05:40:03.126213 [ 0.000000] Memory policy: Data cache writeback
502 05:40:03.126677 [ 0.000000] efi: UEFI not found.
503 05:40:03.133785 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 05:40:03.139505 [ 0.000000] Zone ranges:
505 05:40:03.145283 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 05:40:03.150945 [ 0.000000] Normal empty
507 05:40:03.151408 [ 0.000000] HighMem empty
508 05:40:03.156697 [ 0.000000] Movable zone start for each node
509 05:40:03.157166 [ 0.000000] Early memory node ranges
510 05:40:03.168150 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 05:40:03.173430 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 05:40:03.191537 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 05:40:03.196406 [ 0.000000] AM335X ES2.0 (sgx neon)
514 05:40:03.208897 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
515 05:40:03.226582 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 05:40:03.238160 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 05:40:03.243873 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 05:40:03.249646 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 05:40:03.259641 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 05:40:03.289051 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 05:40:03.295103 <6>[ 0.000000] trace event string verifier disabled
522 05:40:03.295598 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 05:40:03.300797 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 05:40:03.312264 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 05:40:03.318016 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 05:40:03.325288 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 05:40:03.340360 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 05:40:03.357932 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 05:40:03.364762 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 05:40:03.464310 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 05:40:03.475774 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 05:40:03.482552 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 05:40:03.495096 <6>[ 0.019177] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 05:40:03.503203 <6>[ 0.034198] Console: colour dummy device 80x30
535 05:40:03.509293 Matched prompt #6: WARNING:
536 05:40:03.509842 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 05:40:03.514730 <3>[ 0.039096] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 05:40:03.520475 <3>[ 0.046171] This ensures that you still see kernel messages. Please
539 05:40:03.523692 <3>[ 0.052898] update your kernel commandline.
540 05:40:03.564094 <6>[ 0.057513] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 05:40:03.569888 <6>[ 0.096181] CPU: Testing write buffer coherency: ok
542 05:40:03.575822 <6>[ 0.101550] CPU0: Spectre v2: using BPIALL workaround
543 05:40:03.576319 <6>[ 0.107016] pid_max: default: 32768 minimum: 301
544 05:40:03.587305 <6>[ 0.112208] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 05:40:03.594377 <6>[ 0.120032] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 05:40:03.601377 <6>[ 0.129418] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 05:40:03.609911 <6>[ 0.136437] Setting up static identity map for 0x80300000 - 0x803000ac
548 05:40:03.615652 <6>[ 0.146147] rcu: Hierarchical SRCU implementation.
549 05:40:03.623307 <6>[ 0.151434] rcu: Max phase no-delay instances is 1000.
550 05:40:03.632020 <6>[ 0.162750] EFI services will not be available.
551 05:40:03.637858 <6>[ 0.168042] smp: Bringing up secondary CPUs ...
552 05:40:03.643649 <6>[ 0.173099] smp: Brought up 1 node, 1 CPU
553 05:40:03.649390 <6>[ 0.177501] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 05:40:03.655370 <6>[ 0.184274] CPU: All CPU(s) started in SVC mode.
555 05:40:03.674681 <6>[ 0.189492] Memory: 404428K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50620K reserved, 65536K cma-reserved, 0K highmem)
556 05:40:03.675147 <6>[ 0.205774] devtmpfs: initialized
557 05:40:03.698668 <6>[ 0.223638] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 05:40:03.710204 <6>[ 0.232259] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 05:40:03.716271 <6>[ 0.242724] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 05:40:03.726949 <6>[ 0.255047] pinctrl core: initialized pinctrl subsystem
561 05:40:03.736448 <6>[ 0.265889] DMI not present or invalid.
562 05:40:03.744831 <6>[ 0.271779] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 05:40:03.754400 <6>[ 0.280786] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 05:40:03.769552 <6>[ 0.292450] thermal_sys: Registered thermal governor 'step_wise'
565 05:40:03.770029 <6>[ 0.292625] cpuidle: using governor menu
566 05:40:03.797109 <6>[ 0.328077] No ATAGs?
567 05:40:03.803361 <6>[ 0.330815] hw-breakpoint: debug architecture 0x4 unsupported.
568 05:40:03.813761 <6>[ 0.343002] Serial: AMBA PL011 UART driver
569 05:40:03.844696 <6>[ 0.375658] iommu: Default domain type: Translated
570 05:40:03.853811 <6>[ 0.381013] iommu: DMA domain TLB invalidation policy: strict mode
571 05:40:03.880143 <5>[ 0.410432] SCSI subsystem initialized
572 05:40:03.885864 <6>[ 0.415359] usbcore: registered new interface driver usbfs
573 05:40:03.891792 <6>[ 0.421430] usbcore: registered new interface driver hub
574 05:40:03.898641 <6>[ 0.427218] usbcore: registered new device driver usb
575 05:40:03.904379 <6>[ 0.433780] pps_core: LinuxPPS API ver. 1 registered
576 05:40:03.915810 <6>[ 0.439166] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 05:40:03.923087 <6>[ 0.448898] PTP clock support registered
578 05:40:03.923561 <6>[ 0.453361] EDAC MC: Ver: 3.0.0
579 05:40:03.980002 <6>[ 0.509281] scmi_core: SCMI protocol bus registered
580 05:40:03.986765 <6>[ 0.517489] vgaarb: loaded
581 05:40:03.999167 <6>[ 0.530289] clocksource: Switched to clocksource dmtimer
582 05:40:04.038505 <6>[ 0.568977] NET: Registered PF_INET protocol family
583 05:40:04.050895 <6>[ 0.574712] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 05:40:04.057987 <6>[ 0.583726] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 05:40:04.069455 <6>[ 0.592658] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 05:40:04.072433 <6>[ 0.600919] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 05:40:04.083852 <6>[ 0.609188] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 05:40:04.089858 <6>[ 0.616907] TCP: Hash tables configured (established 4096 bind 4096)
589 05:40:04.098392 <6>[ 0.623826] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 05:40:04.104312 <6>[ 0.630871] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 05:40:04.110780 <6>[ 0.638454] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 05:40:04.192411 <6>[ 0.717806] RPC: Registered named UNIX socket transport module.
593 05:40:04.192959 <6>[ 0.724253] RPC: Registered udp transport module.
594 05:40:04.198344 <6>[ 0.729359] RPC: Registered tcp transport module.
595 05:40:04.204010 <6>[ 0.734492] RPC: Registered tcp-with-tls transport module.
596 05:40:04.217105 <6>[ 0.740418] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 05:40:04.217597 <6>[ 0.747326] PCI: CLS 0 bytes, default 64
598 05:40:04.224266 <5>[ 0.753194] Initialise system trusted keyrings
599 05:40:04.246273 <6>[ 0.774265] Trying to unpack rootfs image as initramfs...
600 05:40:04.316833 <6>[ 0.841656] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 05:40:04.321667 <6>[ 0.849176] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 05:40:04.360446 <5>[ 0.891513] NFS: Registering the id_resolver key type
603 05:40:04.366536 <5>[ 0.897117] Key type id_resolver registered
604 05:40:04.372209 <5>[ 0.901821] Key type id_legacy registered
605 05:40:04.377996 <6>[ 0.906268] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 05:40:04.387460 <6>[ 0.913476] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 05:40:04.470101 <5>[ 1.001179] Key type asymmetric registered
608 05:40:04.476204 <5>[ 1.005706] Asymmetric key parser 'x509' registered
609 05:40:04.484457 <6>[ 1.011275] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 05:40:04.490373 <6>[ 1.019165] io scheduler mq-deadline registered
611 05:40:04.498995 <6>[ 1.024149] io scheduler kyber registered
612 05:40:04.499469 <6>[ 1.028600] io scheduler bfq registered
613 05:40:04.595610 <6>[ 1.122983] ledtrig-cpu: registered to indicate activity on CPUs
614 05:40:04.887625 <6>[ 1.414733] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 05:40:04.918171 <6>[ 1.448814] msm_serial: driver initialized
616 05:40:04.924209 <6>[ 1.453858] SuperH (H)SCI(F) driver initialized
617 05:40:04.930076 <6>[ 1.458983] STMicroelectronics ASC driver initialized
618 05:40:04.935349 <6>[ 1.464668] STM32 USART driver initialized
619 05:40:05.053666 <6>[ 1.584088] brd: module loaded
620 05:40:05.084722 <6>[ 1.615059] loop: module loaded
621 05:40:05.118187 <6>[ 1.648258] CAN device driver interface
622 05:40:05.124940 <6>[ 1.653575] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 05:40:05.130687 <6>[ 1.660680] e1000e: Intel(R) PRO/1000 Network Driver
624 05:40:05.137379 <6>[ 1.666071] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 05:40:05.143121 <6>[ 1.672530] igb: Intel(R) Gigabit Ethernet Network Driver
626 05:40:05.150512 <6>[ 1.678353] igb: Copyright (c) 2007-2014 Intel Corporation.
627 05:40:05.162311 <6>[ 1.687603] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 05:40:05.168102 <6>[ 1.693780] usbcore: registered new interface driver pegasus
629 05:40:05.173896 <6>[ 1.699910] usbcore: registered new interface driver asix
630 05:40:05.179718 <6>[ 1.705798] usbcore: registered new interface driver ax88179_178a
631 05:40:05.185456 <6>[ 1.712389] usbcore: registered new interface driver cdc_ether
632 05:40:05.191201 <6>[ 1.718688] usbcore: registered new interface driver smsc75xx
633 05:40:05.197005 <6>[ 1.724919] usbcore: registered new interface driver smsc95xx
634 05:40:05.202795 <6>[ 1.731162] usbcore: registered new interface driver net1080
635 05:40:05.208534 <6>[ 1.737284] usbcore: registered new interface driver cdc_subset
636 05:40:05.214352 <6>[ 1.743696] usbcore: registered new interface driver zaurus
637 05:40:05.221979 <6>[ 1.749742] usbcore: registered new interface driver cdc_ncm
638 05:40:05.231752 <6>[ 1.759209] usbcore: registered new interface driver usb-storage
639 05:40:05.535506 <6>[ 2.064648] i2c_dev: i2c /dev entries driver
640 05:40:05.603730 <5>[ 2.126805] cpuidle: enable-method property 'ti,am3352' found operations
641 05:40:05.609560 <6>[ 2.136446] sdhci: Secure Digital Host Controller Interface driver
642 05:40:05.616995 <6>[ 2.143225] sdhci: Copyright(c) Pierre Ossman
643 05:40:05.624199 <6>[ 2.149663] Synopsys Designware Multimedia Card Interface Driver
644 05:40:05.629707 <6>[ 2.157609] sdhci-pltfm: SDHCI platform and OF driver helper
645 05:40:05.757621 <6>[ 2.281320] usbcore: registered new interface driver usbhid
646 05:40:05.758244 <6>[ 2.287360] usbhid: USB HID core driver
647 05:40:05.808260 <6>[ 2.336843] NET: Registered PF_INET6 protocol family
648 05:40:05.850004 <6>[ 2.381218] Segment Routing with IPv6
649 05:40:05.855808 <6>[ 2.385369] In-situ OAM (IOAM) with IPv6
650 05:40:05.862646 <6>[ 2.389769] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 05:40:05.868535 <6>[ 2.397187] NET: Registered PF_PACKET protocol family
652 05:40:05.874281 <6>[ 2.402761] can: controller area network core
653 05:40:05.880061 <6>[ 2.407585] NET: Registered PF_CAN protocol family
654 05:40:05.880520 <6>[ 2.412814] can: raw protocol
655 05:40:05.885867 <6>[ 2.416142] can: broadcast manager protocol
656 05:40:05.892336 <6>[ 2.420742] can: netlink gateway - max_hops=1
657 05:40:05.898588 <5>[ 2.426231] Key type dns_resolver registered
658 05:40:05.904828 <6>[ 2.431334] ThumbEE CPU extension supported.
659 05:40:05.905284 <5>[ 2.436033] Registering SWP/SWPB emulation handler
660 05:40:05.914665 <3>[ 2.441781] omap_voltage_late_init: Voltage driver support not added
661 05:40:06.128908 <5>[ 2.657598] Loading compiled-in X.509 certificates
662 05:40:06.259118 <6>[ 2.777278] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 05:40:06.266355 <6>[ 2.794043] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 05:40:06.293050 <3>[ 2.818183] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 05:40:06.497484 <3>[ 3.022510] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 05:40:06.692061 <6>[ 3.221187] OMAP GPIO hardware version 0.1
667 05:40:06.713031 <6>[ 3.240190] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 05:40:06.805449 <4>[ 3.332440] at24 2-0054: supply vcc not found, using dummy regulator
669 05:40:06.838890 <4>[ 3.365924] at24 2-0055: supply vcc not found, using dummy regulator
670 05:40:06.877010 <4>[ 3.403895] at24 2-0056: supply vcc not found, using dummy regulator
671 05:40:06.917048 <4>[ 3.444130] at24 2-0057: supply vcc not found, using dummy regulator
672 05:40:06.955588 <6>[ 3.483375] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 05:40:07.009729 <3>[ 3.533516] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 05:40:07.034612 <6>[ 3.554741] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 05:40:07.056069 <4>[ 3.581826] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 05:40:07.076005 <4>[ 3.601750] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 05:40:07.143643 <6>[ 3.673612] Freeing initrd memory: 14996K
678 05:40:07.151959 <6>[ 3.679172] omap_rng 48310000.rng: Random Number Generator ver. 20
679 05:40:07.175949 <5>[ 3.706082] random: crng init done
680 05:40:07.224624 <6>[ 3.750306] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 05:40:07.277845 <6>[ 3.802760] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 05:40:07.283820 <6>[ 3.813092] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 05:40:07.295483 <6>[ 3.820433] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 05:40:07.301235 <6>[ 3.827899] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 05:40:07.312868 <6>[ 3.836030] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 05:40:07.320215 <6>[ 3.847678] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 05:40:07.333409 <5>[ 3.856787] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 05:40:07.361861 <3>[ 3.887216] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 05:40:07.367610 <6>[ 3.895842] edma 49000000.dma: TI EDMA DMA engine driver
690 05:40:07.440206 <3>[ 3.964768] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 05:40:07.455017 <6>[ 3.979266] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 05:40:07.468199 <3>[ 3.996638] l3-aon-clkctrl:0000:0: failed to disable
693 05:40:07.523774 <6>[ 4.049034] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 05:40:07.529498 <6>[ 4.058549] printk: legacy console [ttyS0] enabled
695 05:40:07.535119 <6>[ 4.058549] printk: legacy console [ttyS0] enabled
696 05:40:07.540872 <6>[ 4.068885] printk: legacy bootconsole [omap8250] disabled
697 05:40:07.546678 <6>[ 4.068885] printk: legacy bootconsole [omap8250] disabled
698 05:40:07.576897 <4>[ 4.101115] tps65217-pmic: Failed to locate of_node [id: -1]
699 05:40:07.580416 <4>[ 4.108525] tps65217-bl: Failed to locate of_node [id: -1]
700 05:40:07.597307 <6>[ 4.128677] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 05:40:07.615865 <6>[ 4.135694] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 05:40:07.627552 <6>[ 4.149400] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 05:40:07.633217 <6>[ 4.161286] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 05:40:07.656120 <6>[ 4.181830] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 05:40:07.661943 <6>[ 4.191016] sdhci-omap 48060000.mmc: Got CD GPIO
706 05:40:07.670028 <4>[ 4.196172] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 05:40:07.684820 <4>[ 4.209750] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 05:40:07.691165 <4>[ 4.218550] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 05:40:07.701048 <4>[ 4.227198] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 05:40:07.825718 <6>[ 4.352540] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 05:40:07.871866 <6>[ 4.394689] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
712 05:40:07.878299 <6>[ 4.405660] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
713 05:40:07.887441 <6>[ 4.414652] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 05:40:07.937982 <6>[ 4.459792] mmc0: new high speed SDHC card at address 0001
715 05:40:07.938446 <6>[ 4.467328] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 05:40:07.944697 <6>[ 4.475921] mmcblk0: p1
717 05:40:07.963354 <4>[ 4.487901] mmc1: unexpected status 0x2000980 after switch
718 05:40:07.970099 <6>[ 4.495011] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
719 05:40:07.975720 <4>[ 4.506995] mmc1: unexpected status 0x2000900 after switch
720 05:40:07.985958 <4>[ 4.514097] mmc1: unexpected status 0x2000900 after switch
721 05:40:07.999130 <4>[ 4.524915] mmc1: unexpected status 0x2000900 after switch
722 05:40:08.008832 <6>[ 4.530819] mmc1: new high speed MMC card at address 0001
723 05:40:08.009278 <6>[ 4.538122] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 05:40:09.704627 <4>[ 6.228607] mmc1: unexpected status 0x2000980 after switch
725 05:40:09.711192 <4>[ 6.236361] mmc1: unexpected status 0x2000900 after switch
726 05:40:09.718375 <4>[ 6.243076] mmc1: unexpected status 0x2000900 after switch
727 05:40:09.721672 <4>[ 6.250019] mmc1: unexpected status 0x2000900 after switch
728 05:40:10.145919 <6>[ 6.671395] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 05:40:10.269257 <5>[ 6.700312] Sending DHCP requests ., OK
730 05:40:10.280526 <6>[ 6.804735] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 05:40:10.280994 <6>[ 6.812901] IP-Config: Complete:
732 05:40:10.291805 <6>[ 6.816441] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 05:40:10.297568 <6>[ 6.826953] host=192.168.6.16, domain=, nis-domain=(none)
734 05:40:10.310051 <6>[ 6.833223] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 05:40:10.310517 <6>[ 6.833260] nameserver0=10.255.253.1
736 05:40:10.316244 <6>[ 6.845899] clk: Disabling unused clocks
737 05:40:10.322010 <6>[ 6.850673] PM: genpd: Disabling unused power domains
738 05:40:10.340861 <6>[ 6.868648] Freeing unused kernel image (initmem) memory: 2048K
739 05:40:10.347533 <6>[ 6.878533] Run /init as init process
740 05:40:10.373768 Loading, please wait...
741 05:40:10.455451 <3>[ 6.980749] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
742 05:40:10.486765 Starting systemd-udevd version 252.22-1~deb12u1
743 05:40:11.190262 <3>[ 7.715540] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 05:40:11.949283 <3>[ 8.474608] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 05:40:12.682910 <3>[ 9.208216] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 05:40:13.443726 <3>[ 9.968455] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 05:40:13.719789 <4>[ 10.244871] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 05:40:13.887391 <4>[ 10.411573] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 05:40:14.107011 <6>[ 10.637682] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 05:40:14.116021 <6>[ 10.643509] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 05:40:14.196451 <3>[ 10.721765] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
752 05:40:14.253055 <6>[ 10.782859] tda998x 0-0070: found TDA19988
753 05:40:14.321662 <6>[ 10.851833] hub 1-0:1.0: USB hub found
754 05:40:14.339865 <6>[ 10.869743] hub 1-0:1.0: 1 port detected
755 05:40:14.967184 <3>[ 11.492727] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 05:40:15.283157 <6>[ 11.810606] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 05:40:15.452071 <3>[ 11.980546] usb 1-1: device descriptor read/64, error -71
758 05:40:15.701044 <3>[ 12.227066] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
759 05:40:15.709146 <3>[ 12.235999] Buffer I/O error on dev mmcblk1, logical block 0, async page read
760 05:40:15.782360 <3>[ 12.310970] usb 1-1: device descriptor read/64, error -71
761 05:40:16.023148 <6>[ 12.550636] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 05:40:16.172044 <3>[ 12.700603] usb 1-1: device descriptor read/64, error -71
763 05:40:16.496550 <3>[ 13.025167] usb 1-1: device descriptor read/64, error -71
764 05:40:16.611257 <6>[ 13.140660] usb usb1-port1: attempt power cycle
765 05:40:16.793150 <6>[ 13.320594] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 05:40:17.405247 <6>[ 13.932753] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 05:40:17.893731 Begin: Loading essential drivers ... done.
768 05:40:17.899154 Begin: Running /scripts/init-premount ... done.
769 05:40:17.904980 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 05:40:17.914999 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 05:40:17.925410 Device /sys/class/net/eth0 found
772 05:40:17.925867 done.
773 05:40:18.061078 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 05:40:18.142191 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
775 05:40:18.237947 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 05:40:18.243372 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 05:40:18.249057 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 05:40:18.260241 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 05:40:18.260779 rootserver: 192.168.6.1 rootpath:
780 05:40:18.263849 filename :
781 05:40:18.385078 done.
782 05:40:18.396504 Begin: Running /scripts/nfs-bottom ... done.
783 05:40:18.473979 Begin: Running /scripts/init-bottom ... done.
784 05:40:18.774646 <3>[ 15.300092] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
785 05:40:19.509238 <3>[ 16.034678] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
786 05:40:20.071608 <30>[ 16.599024] systemd[1]: System time before build time, advancing clock.
787 05:40:20.269204 <3>[ 16.794878] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
788 05:40:20.321976 <30>[ 16.823272] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
789 05:40:20.331158 <30>[ 16.860481] systemd[1]: Detected architecture arm.
790 05:40:20.346061
791 05:40:20.346531 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
792 05:40:20.346950
793 05:40:20.371748 <30>[ 16.899846] systemd[1]: Hostname set to <debian-bookworm-armhf>.
794 05:40:21.064943 <3>[ 17.590665] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 05:40:21.798469 <3>[ 18.324181] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 05:40:22.531858 <3>[ 19.057538] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
797 05:40:22.656734 <30>[ 19.183709] systemd[1]: Queued start job for default target graphical.target.
798 05:40:22.673593 <30>[ 19.198390] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
799 05:40:22.681189 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
800 05:40:22.712292 <30>[ 19.236549] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
801 05:40:22.719748 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
802 05:40:22.749171 <30>[ 19.273105] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
803 05:40:22.756545 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
804 05:40:22.790089 <30>[ 19.314571] systemd[1]: Created slice user.slice - User and Session Slice.
805 05:40:22.796922 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
806 05:40:22.821995 <30>[ 19.341555] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
807 05:40:22.828038 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
808 05:40:22.846035 <30>[ 19.371376] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
809 05:40:22.854024 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
810 05:40:22.884650 <30>[ 19.401380] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
811 05:40:22.896678 <30>[ 19.422140] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
812 05:40:22.902286 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
813 05:40:22.925307 <30>[ 19.450835] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
814 05:40:22.933594 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
815 05:40:22.956031 <30>[ 19.481257] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
816 05:40:22.964456 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
817 05:40:22.985806 <30>[ 19.511330] systemd[1]: Reached target paths.target - Path Units.
818 05:40:22.991049 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
819 05:40:23.015453 <30>[ 19.540950] systemd[1]: Reached target remote-fs.target - Remote File Systems.
820 05:40:23.023872 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
821 05:40:23.045357 <30>[ 19.570854] systemd[1]: Reached target slices.target - Slice Units.
822 05:40:23.050840 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
823 05:40:23.075613 <30>[ 19.601155] systemd[1]: Reached target swap.target - Swaps.
824 05:40:23.079730 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
825 05:40:23.105908 <30>[ 19.631195] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
826 05:40:23.114831 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
827 05:40:23.136701 <30>[ 19.661887] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
828 05:40:23.145001 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
829 05:40:23.238473 <30>[ 19.758952] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
830 05:40:23.272646 <3>[ 19.798389] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
831 05:40:23.285658 <30>[ 19.811075] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
832 05:40:23.294172 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
833 05:40:23.317406 <30>[ 19.842087] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
834 05:40:23.324822 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
835 05:40:23.349713 <30>[ 19.873684] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
836 05:40:23.356827 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
837 05:40:23.392353 <30>[ 19.918316] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
838 05:40:23.405757 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
839 05:40:23.427391 <30>[ 19.952343] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
840 05:40:23.435965 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
841 05:40:23.463115 <30>[ 19.982150] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
842 05:40:23.479591 <30>[ 19.998889] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
843 05:40:23.529908 <30>[ 20.056087] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
844 05:40:23.555475 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
845 05:40:23.590449 <30>[ 20.116482] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
846 05:40:23.620942 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
847 05:40:23.695554 <30>[ 20.221506] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
848 05:40:23.724409 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
849 05:40:23.776442 <30>[ 20.302108] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
850 05:40:23.794515 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
851 05:40:23.856274 <30>[ 20.382249] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
852 05:40:23.874541 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
853 05:40:23.897875 <30>[ 20.424505] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
854 05:40:23.921862 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
855 05:40:24.005573 <3>[ 20.531700] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
856 05:40:24.011309 <3>[ 20.540667] Buffer I/O error on dev mmcblk1, logical block 0, async page read
857 05:40:24.017601 <6>[ 20.548235] mmcblk1: unable to read partition table
858 05:40:24.024867 <6>[ 20.554151] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
859 05:40:24.042800 <30>[ 20.566715] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
860 05:40:24.048981 <6>[ 20.578298] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
861 05:40:24.068890 <6>[ 20.592840] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
862 05:40:24.074676 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
863 05:40:24.127798 <30>[ 20.654243] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
864 05:40:24.154403 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
865 05:40:24.215747 <30>[ 20.741345] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
866 05:40:24.223090 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
867 05:40:24.251358 <28>[ 20.772603] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
868 05:40:24.272427 <28>[ 20.798015] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
869 05:40:24.305872 <30>[ 20.831490] systemd[1]: Starting systemd-journald.service - Journal Service...
870 05:40:24.312361 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
871 05:40:24.375600 <30>[ 20.901802] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
872 05:40:24.394580 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
873 05:40:24.430904 <30>[ 20.957320] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
874 05:40:24.489758 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 05:40:24.550079 <30>[ 21.074948] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 05:40:24.594357 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 05:40:24.677829 <30>[ 21.203502] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 05:40:24.715367 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 05:40:24.791366 <30>[ 21.317824] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 05:40:24.838384 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 05:40:24.876284 <30>[ 21.402628] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 05:40:24.915270 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 05:40:24.939904 <30>[ 21.465195] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 05:40:24.957324 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 05:40:25.156681 <30>[ 21.683488] systemd[1]: Started systemd-journald.service - Journal Service.
886 05:40:25.174703 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
887 05:40:25.216748 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 05:40:25.245651 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
889 05:40:25.276493 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
890 05:40:25.308382 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
891 05:40:25.346485 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
892 05:40:25.376444 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
893 05:40:25.399004 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
894 05:40:25.416829 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
895 05:40:25.438101 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
896 05:40:25.465370 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
897 05:40:25.524992 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
898 05:40:25.575603 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
899 05:40:25.630024 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
900 05:40:25.719399 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
901 05:40:25.790192 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
902 05:40:25.946651 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
903 05:40:25.954850 <46>[ 22.480175] systemd-journald[164]: Received client request to flush runtime journal.
904 05:40:26.097695 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
905 05:40:26.919084 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
906 05:40:26.962466 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
907 05:40:27.045696 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
908 05:40:27.830738 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
909 05:40:27.987507 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
910 05:40:28.007299 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
911 05:40:28.025140 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
912 05:40:28.108018 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
913 05:40:28.139618 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
914 05:40:29.077559 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
915 05:40:29.183491 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
916 05:40:29.253680 <4>[ 25.782363] mmc1: unexpected status 0x2000980 after switch
917 05:40:29.273350 <4>[ 25.802004] mmc1: unexpected status 0x2000900 after switch
918 05:40:29.303178 <4>[ 25.831922] mmc1: unexpected status 0x2000900 after switch
919 05:40:29.333273 <4>[ 25.862004] mmc1: unexpected status 0x2000900 after switch
920 05:40:29.464592 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
921 05:40:29.545376 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
922 05:40:29.583827 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
923 05:40:30.759164 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
924 05:40:31.426226 <5>[ 27.952834] cfg80211: Loading compiled-in X.509 certificates for regulatory database
925 05:40:32.211285 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
926 05:40:32.434020 <3>[ 28.959455] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
927 05:40:32.613949 <5>[ 29.142744] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
928 05:40:32.692941 <5>[ 29.221147] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
929 05:40:32.706010 <4>[ 29.232504] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
930 05:40:32.710964 <6>[ 29.241619] cfg80211: failed to load regulatory.db
931 05:40:33.188438 <3>[ 29.713538] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
932 05:40:33.634136 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
933 05:40:33.937824 <3>[ 30.464143] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
934 05:40:34.201331 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
935 05:40:34.515584 <46>[ 31.032401] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
936 05:40:34.610799 <46>[ 31.130756] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
937 05:40:34.686007 <3>[ 31.211351] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
938 05:40:35.453280 <3>[ 31.978609] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
939 05:40:36.201248 <3>[ 32.726680] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
940 05:40:36.497110 [[0m[0;31m* [0m] Job dev-ttyS0.device/start running (13s / 1min 30s)
941 05:40:36.938523 <3>[ 33.463797] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
942 05:40:36.979809 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
943 05:40:37.422496 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
944 05:40:37.676020 <3>[ 34.201252] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
945 05:40:37.837145 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
946 05:40:38.246944 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
947 05:40:38.688324 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
948 05:40:39.131907 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
949 05:40:39.550856 M
[K[ [0;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
950 05:40:40.106911 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
951 05:40:40.452763 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
952 05:40:40.778972 <3>[ 37.305279] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
953 05:40:40.802975 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
954 05:40:41.144538 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
955 05:40:41.465977 M
[K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
956 05:40:41.506623 [K[[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
957 05:40:41.514653 <3>[ 38.039619] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
958 05:40:41.526778 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
959 05:40:41.585121 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
960 05:40:41.634912 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
961 05:40:41.696868 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
962 05:40:41.738325 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
963 05:40:41.799975 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
964 05:40:41.825121 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
965 05:40:41.850159 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
966 05:40:41.890935 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
967 05:40:41.918298 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
968 05:40:41.965178 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
969 05:40:41.988500 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
970 05:40:42.022447 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
971 05:40:42.050033 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
972 05:40:42.084876 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
973 05:40:42.108624 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
974 05:40:42.133590 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
975 05:40:42.172135 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
976 05:40:42.193143 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
977 05:40:42.243459 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
978 05:40:42.251313 <3>[ 38.776450] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
979 05:40:42.304444 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
980 05:40:42.348552 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
981 05:40:42.447473 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
982 05:40:42.545950 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
983 05:40:42.584590 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
984 05:40:42.646568 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
985 05:40:42.665874 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
986 05:40:42.855186 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
987 05:40:42.916525 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
988 05:40:42.986113 <3>[ 39.512625] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
989 05:40:43.058148 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
990 05:40:43.387406 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
991 05:40:43.721093 <3>[ 40.246860] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
992 05:40:43.742092 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
993 05:40:44.490131 <3>[ 41.015793] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
994 05:40:45.259229 <3>[ 41.784893] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
995 05:40:46.027359 <3>[ 42.554035] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
996 05:40:46.036174 <3>[ 42.563541] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
997 05:40:46.058720 [[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (23s / 1min 30s)
998 05:40:46.994987 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (24s / 1min 30s)
999 05:40:47.855136 M
[K[[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1000 05:40:48.799379 [K[[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1001 05:40:48.912373 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1002 05:40:48.970074 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1003 05:40:49.020067 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1004 05:40:49.169606 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1005 05:40:49.317280 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1006 05:40:49.611870
1007 05:40:49.612630 Debian GNU/Linux 12 debian-bookworm-armhf ttyS0
1008 05:40:49.613095
1009 05:40:49.617966 dworm-armhf login: root (automatic login)
1010 05:40:49.618574
1011 05:40:49.930729 <3>[ 46.457263] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1012 05:40:50.124052 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sat Nov 2 04:26:45 UTC 2024 armv7l
1013 05:40:50.124648
1014 05:40:50.129729 The programs included with the Debian GNU/Linux system are free software;
1015 05:40:50.133060 the exact distribution terms for each program are described in the
1016 05:40:50.138438 individual files in /usr/share/doc/*/copyright.
1017 05:40:50.138959
1018 05:40:50.144187 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1019 05:40:50.148772 permitted by applicable law.
1020 05:40:50.667841 <3>[ 47.193895] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1021 05:40:51.402598 <3>[ 47.928391] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1022 05:40:52.136629 <3>[ 48.662748] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1023 05:40:52.870305 <3>[ 49.396876] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1024 05:40:53.604809 <3>[ 50.131027] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1025 05:40:54.338628 <3>[ 50.865161] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1026 05:40:55.072916 <3>[ 51.599378] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1027 05:40:55.203719 Unable to match end of the kernel message
1029 05:40:55.204672 Setting prompt string to ['/ #']
1030 05:40:55.205002 end: 2.4.4.1 login-action (duration 00:00:52) [common]
1032 05:40:55.205775 end: 2.4.4 auto-login-action (duration 00:00:53) [common]
1033 05:40:55.206092 start: 2.4.5 expect-shell-connection (timeout 00:02:46) [common]
1034 05:40:55.206345 Setting prompt string to ['/ #']
1035 05:40:55.206580 Forcing a shell prompt, looking for ['/ #']
1037 05:40:55.257161 / #
1038 05:40:55.257876 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1039 05:40:55.258181 Waiting using forced prompt support (timeout 00:02:30)
1040 05:40:55.262297
1041 05:40:55.275488 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1042 05:40:55.275931 start: 2.4.6 export-device-env (timeout 00:02:46) [common]
1043 05:40:55.276234 Sending with 10 millisecond of delay
1045 05:41:00.266248 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/927075/extract-nfsrootfs-7z2f_bmk'
1046 05:41:00.277274 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/9<3>[ 54.828280] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1047 05:41:00.277846 27075/extrac<3>[ 55.597360] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1048 05:41:00.278317 t-nfsrootfs-7<3>[ 56.366452] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1049 05:41:00.278770 z2f_bmk'
1050 05:41:00.279546 Sending with 10 millisecond of delay
1052 05:41:02.377767 / # export NFS_SERVER_IP='192.168.6.2'
1053 05:41:02.388743 expo<3>[ 57.135633] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1054 05:41:02.389255 rt NFS_SERVER<3>[ 57.904729] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1055 05:41:02.389758 _IP='192.168<3>[ 58.673848] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1056 05:41:02.390226 .6.2'
1057 05:41:02.391154 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1058 05:41:02.391781 end: 2.4 uboot-commands (duration 00:02:21) [common]
1059 05:41:02.392487 end: 2 uboot-action (duration 00:02:21) [common]
1060 05:41:02.393121 start: 3 lava-test-retry (timeout 00:06:27) [common]
1061 05:41:02.393749 start: 3.1 lava-test-shell (timeout 00:06:27) [common]
1062 05:41:02.394261 Using namespace: common
1064 05:41:02.495498 / # #
1065 05:41:02.496212 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1066 05:41:02.500537 #
1067 05:41:02.507187 Using /lava-927075
1069 05:41:02.608446 / # export SHELL=/bin/bash
1070 05:41:02.613745 export SHELL=/bin/bash
1072 05:41:02.721261 / # . /lava-927075/environment
1073 05:41:02.726704 . /lava-927075/environment
1075 05:41:02.843066 / # /lava-927075/bin/lava-test-runner /lava-927075/0
1076 05:41:02.843809 Test shell timeout: 10s (minimum of the action and connection timeout)
1077 05:41:02.917348 /lava-927075/bin/lava-test-runner /lava-927075/0<3>[ 59.442996] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1078 05:41:02.917936
1079 05:41:03.328179 + export TESTRUN_ID=0_timesync-off
1080 05:41:03.336178 + TESTRUN_ID=0_timesync-off
1081 05:41:03.336493 + cd /lava-927075/0/tests/0_timesync-off
1082 05:41:03.336723 ++ cat uuid
1083 05:41:03.353591 + UUID=927075_1.6.2.4.1
1084 05:41:03.353901 + set +x
1085 05:41:03.361838 <LAVA_SIGNAL_STARTRUN 0_timesync-off 927075_1.6.2.4.1>
1086 05:41:03.362072 + systemctl stop systemd-timesyncd
1087 05:41:03.362512 Received signal: <STARTRUN> 0_timesync-off 927075_1.6.2.4.1
1088 05:41:03.362736 Starting test lava.0_timesync-off (927075_1.6.2.4.1)
1089 05:41:03.363011 Skipping test definition patterns.
1090 05:41:03.661547 <3>[ 60.188808] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1091 05:41:03.669939 <3>[ 60.198368] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1092 05:41:03.738296 + set +x
1093 05:41:03.738869 <LAVA_SIGNAL_ENDRUN 0_timesync-off 927075_1.6.2.4.1>
1094 05:41:03.739600 Received signal: <ENDRUN> 0_timesync-off 927075_1.6.2.4.1
1095 05:41:03.740211 Ending use of test pattern.
1096 05:41:03.740665 Ending test lava.0_timesync-off (927075_1.6.2.4.1), duration 0.38
1098 05:41:03.937318 + export TESTRUN_ID=1_kselftest-dt
1099 05:41:03.945391 + TESTRUN_ID=1_kselftest-dt
1100 05:41:03.945883 + cd /lava-927075/0/tests/1_kselftest-dt
1101 05:41:03.946335 ++ cat uuid
1102 05:41:03.962750 + UUID=927075_1.6.2.4.5
1103 05:41:03.963230 + set +x
1104 05:41:03.968368 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 927075_1.6.2.4.5>
1105 05:41:03.968841 + cd ./automated/linux/kselftest/
1106 05:41:03.969558 Received signal: <STARTRUN> 1_kselftest-dt 927075_1.6.2.4.5
1107 05:41:03.970019 Starting test lava.1_kselftest-dt (927075_1.6.2.4.5)
1108 05:41:03.970551 Skipping test definition patterns.
1109 05:41:03.996861 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1110 05:41:04.108436 INFO: install_deps skipped
1111 05:41:04.669872 --2024-11-02 05:41:04-- http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1112 05:41:04.934404 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1113 05:41:05.075720 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1114 05:41:05.215928 HTTP request sent, awaiting response... 200 OK
1115 05:41:05.216616 Length: 2715020 (2.6M) [application/octet-stream]
1116 05:41:05.221398 Saving to: 'kselftest_armhf.tar.gz'
1117 05:41:05.221880
1118 05:41:07.060523
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kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
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kselftest_armhf.tar 16%[==> ] 431.45K 521KB/s
kselftest_armhf.tar 44%[=======> ] 1.16M 1.12MB/s
kselftest_armhf.tar 60%[===========> ] 1.57M 1.26MB/s
kselftest_armhf.tar 73%[=============> ] 1.91M 1.30MB/s
kselftest_armhf.tar 96%[==================> ] 2.51M 1.40MB/s
kselftest_armhf.tar 100%[===================>] 2.59M 1.41MB/s in 1.8s
1119 05:41:07.061250
1120 05:41:07.556666 2024-11-02 05:41:07 (1.41 MB/s) - 'kselftest_armhf.tar.gz' saved [2715020/2715020]
1121 05:41:07.557153
1122 05:41:19.082333 skiplist:
1123 05:41:19.083018 ========================================
1124 05:41:19.088140 ========================================
1125 05:41:19.194063 dt:test_unprobed_devices.sh
1126 05:41:19.225647 ============== Tests to run ===============
1127 05:41:19.234632 dt:test_unprobed_devices.sh
1128 05:41:19.238559 ===========End Tests to run ===============
1129 05:41:19.250195 shardfile-dt pass
1130 05:41:19.485236 <12>[ 76.017130] kselftest: Running tests in dt
1131 05:41:19.513776 TAP version 13
1132 05:41:19.538759 1..1
1133 05:41:19.594419 # timeout set to 45
1134 05:41:19.594985 # selftests: dt: test_unprobed_devices.sh
1135 05:41:20.488413 # TAP version 13
1136 05:41:45.910330 # 1..257
1137 05:41:46.089044 # ok 1 / # SKIP
1138 05:41:46.112756 # ok 2 /clk_mcasp0
1139 05:41:46.186571 # ok 3 /clk_mcasp0_fixed # SKIP
1140 05:41:46.262440 # ok 4 /cpus/cpu@0 # SKIP
1141 05:41:46.335723 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1142 05:41:46.355444 # ok 6 /fixedregulator0
1143 05:41:46.373507 # ok 7 /leds
1144 05:41:46.400077 # ok 8 /ocp
1145 05:41:46.424812 # ok 9 /ocp/interconnect@44c00000
1146 05:41:46.444288 # ok 10 /ocp/interconnect@44c00000/segment@0
1147 05:41:46.472498 # ok 11 /ocp/interconnect@44c00000/segment@100000
1148 05:41:46.497395 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1149 05:41:46.570167 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1150 05:41:46.592569 # ok 14 /ocp/interconnect@44c00000/segment@200000
1151 05:41:46.613372 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1152 05:41:46.721211 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1153 05:41:46.801379 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1154 05:41:46.871230 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1155 05:41:46.943353 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1156 05:41:47.021735 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1157 05:41:47.089869 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1158 05:41:47.164532 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1159 05:41:47.238107 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1160 05:41:47.311938 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1161 05:41:47.385120 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1162 05:41:47.457308 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1163 05:41:47.536825 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1164 05:41:47.606579 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1165 05:41:47.680313 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1166 05:41:47.753233 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1167 05:41:47.826312 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1168 05:41:47.898900 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1169 05:41:47.974041 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1170 05:41:48.045275 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1171 05:41:48.119623 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1172 05:41:48.194954 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1173 05:41:48.269503 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1174 05:41:48.348300 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1175 05:41:48.422073 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1176 05:41:48.492256 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1177 05:41:48.564681 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1178 05:41:48.639789 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1179 05:41:48.719130 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1180 05:41:48.792774 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1181 05:41:48.869108 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1182 05:41:48.937746 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1183 05:41:49.011196 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1184 05:41:49.084999 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1185 05:41:49.158181 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1186 05:41:49.231167 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1187 05:41:49.305787 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1188 05:41:49.379311 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1189 05:41:49.453823 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1190 05:41:49.527759 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1191 05:41:49.599772 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1192 05:41:49.679006 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1193 05:41:49.752795 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1194 05:41:49.824258 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1195 05:41:49.896552 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1196 05:41:49.970597 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1197 05:41:50.044538 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1198 05:41:50.119307 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1199 05:41:50.198501 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1200 05:41:50.272223 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1201 05:41:50.340762 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1202 05:41:50.415715 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1203 05:41:50.489536 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1204 05:41:50.567381 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1205 05:41:50.640282 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1206 05:41:50.712450 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1207 05:41:50.788891 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1208 05:41:50.862329 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1209 05:41:50.932467 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1210 05:41:51.005890 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1211 05:41:51.080426 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1212 05:41:51.158813 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1213 05:41:51.232556 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1214 05:41:51.302169 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1215 05:41:51.380757 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1216 05:41:51.452321 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1217 05:41:51.528652 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1218 05:41:51.602218 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1219 05:41:51.674386 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1220 05:41:51.743802 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1221 05:41:51.819254 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1222 05:41:51.896031 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1223 05:41:51.970164 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1224 05:41:52.048064 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1225 05:41:52.123298 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1226 05:41:52.193616 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1227 05:41:52.264240 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1228 05:41:52.340194 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1229 05:41:52.421212 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1230 05:41:52.493232 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1231 05:41:52.514396 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1232 05:41:52.535610 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1233 05:41:52.560197 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1234 05:41:52.588210 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1235 05:41:52.610042 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1236 05:41:52.633010 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1237 05:41:52.660153 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1238 05:41:52.679771 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1239 05:41:52.790122 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1240 05:41:52.819170 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1241 05:41:52.841032 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1242 05:41:52.868587 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1243 05:41:52.976243 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1244 05:41:53.052267 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1245 05:41:53.123324 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1246 05:41:53.194958 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1247 05:41:53.269244 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1248 05:41:53.343512 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1249 05:41:53.416749 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1250 05:41:53.491334 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1251 05:41:53.566021 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1252 05:41:53.640816 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1253 05:41:53.719886 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1254 05:41:53.789764 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1255 05:41:53.862916 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1256 05:41:53.938109 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1257 05:41:54.013042 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1258 05:41:54.087289 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1259 05:41:54.109160 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1260 05:41:54.181615 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1261 05:41:54.251562 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1262 05:41:54.326700 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1263 05:41:54.350907 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1264 05:41:54.427363 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1265 05:41:54.449174 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1266 05:41:54.519686 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1267 05:41:54.546937 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1268 05:41:54.569671 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1269 05:41:54.591111 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1270 05:41:54.619930 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1271 05:41:54.647304 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1272 05:41:54.668911 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1273 05:41:54.696889 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1274 05:41:54.768247 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1275 05:41:54.789921 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1276 05:41:54.814162 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1277 05:41:54.886951 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1278 05:41:54.959378 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1279 05:41:54.981247 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1280 05:41:55.083951 # not ok 144 /ocp/interconnect@47c00000
1281 05:41:55.157569 # not ok 145 /ocp/interconnect@47c00000/segment@0
1282 05:41:55.182853 # ok 146 /ocp/interconnect@48000000
1283 05:41:55.206342 # ok 147 /ocp/interconnect@48000000/segment@0
1284 05:41:55.227188 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1285 05:41:55.254883 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1286 05:41:55.278457 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1287 05:41:55.297857 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1288 05:41:55.326055 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1289 05:41:55.349432 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1290 05:41:55.369524 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1291 05:41:55.442656 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1292 05:41:55.516840 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1293 05:41:55.543953 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1294 05:41:55.568229 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1295 05:41:55.588953 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1296 05:41:55.612966 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1297 05:41:55.638824 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1298 05:41:55.660469 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1299 05:41:55.683192 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1300 05:41:55.707710 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1301 05:41:55.730806 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1302 05:41:55.759468 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1303 05:41:55.778830 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1304 05:41:55.806698 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1305 05:41:55.828742 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1306 05:41:55.853697 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1307 05:41:55.877360 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1308 05:41:55.899570 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1309 05:41:55.924990 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1310 05:41:55.949693 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1311 05:41:55.966962 # ok 175 /ocp/interconnect@48000000/segment@100000
1312 05:41:55.992653 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1313 05:41:56.017237 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1314 05:41:56.091352 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1315 05:41:56.165764 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1316 05:41:56.237104 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1317 05:41:56.311694 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1318 05:41:56.382699 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1319 05:41:56.458496 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1320 05:41:56.529664 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1321 05:41:56.609378 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1322 05:41:56.625824 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1323 05:41:56.651018 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1324 05:41:56.677839 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1325 05:41:56.699175 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1326 05:41:56.721327 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1327 05:41:56.749884 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1328 05:41:56.772971 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1329 05:41:56.798534 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1330 05:41:56.819154 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1331 05:41:56.842143 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1332 05:41:56.884594 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1333 05:41:56.897283 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1334 05:41:56.917302 # ok 198 /ocp/interconnect@48000000/segment@200000
1335 05:41:56.943211 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1336 05:41:57.018522 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1337 05:41:57.037361 # ok 201 /ocp/interconnect@48000000/segment@300000
1338 05:41:57.060608 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1339 05:41:57.084605 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1340 05:41:57.109647 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1341 05:41:57.136711 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1342 05:41:57.159000 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1343 05:41:57.180111 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1344 05:41:57.254116 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1345 05:41:57.272896 # ok 209 /ocp/interconnect@4a000000
1346 05:41:57.302009 # ok 210 /ocp/interconnect@4a000000/segment@0
1347 05:41:57.327280 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1348 05:41:57.348586 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1349 05:41:57.378263 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1350 05:41:57.398727 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1351 05:41:57.469253 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1352 05:41:57.581116 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1353 05:41:57.650869 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1354 05:41:57.757318 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1355 05:41:57.829968 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1356 05:41:57.903379 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1357 05:41:58.003794 # not ok 221 /ocp/interconnect@4b140000
1358 05:41:58.077848 # not ok 222 /ocp/interconnect@4b140000/segment@0
1359 05:41:58.150544 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1360 05:41:58.176181 # ok 224 /ocp/target-module@40300000
1361 05:41:58.196881 # ok 225 /ocp/target-module@40300000/sram@0
1362 05:41:58.270210 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1363 05:41:58.349075 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1364 05:41:58.364167 # ok 228 /ocp/target-module@47400000
1365 05:41:58.392911 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1366 05:41:58.416105 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1367 05:41:58.434909 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1368 05:41:58.457459 # ok 232 /ocp/target-module@47400000/usb@1400
1369 05:41:58.484744 # ok 233 /ocp/target-module@47400000/usb@1800
1370 05:41:58.502400 # ok 234 /ocp/target-module@47810000
1371 05:41:58.526118 # ok 235 /ocp/target-module@49000000
1372 05:41:58.548794 # ok 236 /ocp/target-module@49000000/dma@0
1373 05:41:58.574653 # ok 237 /ocp/target-module@49800000
1374 05:41:58.596601 # ok 238 /ocp/target-module@49800000/dma@0
1375 05:41:58.620952 # ok 239 /ocp/target-module@49900000
1376 05:41:58.644474 # ok 240 /ocp/target-module@49900000/dma@0
1377 05:41:58.662489 # ok 241 /ocp/target-module@49a00000
1378 05:41:58.686596 # ok 242 /ocp/target-module@49a00000/dma@0
1379 05:41:58.712831 # ok 243 /ocp/target-module@4c000000
1380 05:41:58.786096 # not ok 244 /ocp/target-module@4c000000/emif@0
1381 05:41:58.803496 # ok 245 /ocp/target-module@50000000
1382 05:41:58.830659 # ok 246 /ocp/target-module@53100000
1383 05:41:58.904583 # not ok 247 /ocp/target-module@53100000/sham@0
1384 05:41:58.921854 # ok 248 /ocp/target-module@53500000
1385 05:41:58.997082 # not ok 249 /ocp/target-module@53500000/aes@0
1386 05:41:59.021548 # ok 250 /ocp/target-module@56000000
1387 05:41:59.127439 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1388 05:41:59.200693 # ok 252 /opp-table # SKIP
1389 05:41:59.267281 # ok 253 /soc # SKIP
1390 05:41:59.293737 # ok 254 /sound
1391 05:41:59.315851 # ok 255 /target-module@4b000000
1392 05:41:59.339391 # ok 256 /target-module@4b000000/target-module@140000
1393 05:41:59.360706 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1394 05:41:59.369310 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1395 05:41:59.377233 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1396 05:42:01.657922 dt_test_unprobed_devices_sh_ skip
1397 05:42:01.663265 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1398 05:42:01.668875 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1399 05:42:01.669384 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1400 05:42:01.678025 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1401 05:42:01.678459 dt_test_unprobed_devices_sh_fixedregulator0 pass
1402 05:42:01.683608 dt_test_unprobed_devices_sh_leds pass
1403 05:42:01.689136 dt_test_unprobed_devices_sh_ocp pass
1404 05:42:01.689564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1405 05:42:01.698358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1406 05:42:01.703971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1407 05:42:01.715154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1408 05:42:01.720772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1409 05:42:01.726317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1410 05:42:01.737544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1411 05:42:01.743271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1412 05:42:01.754279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1413 05:42:01.765523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1414 05:42:01.771109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1415 05:42:01.782332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1416 05:42:01.793519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1417 05:42:01.804783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1418 05:42:01.816005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1419 05:42:01.821572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1420 05:42:01.832764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1421 05:42:01.843937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1422 05:42:01.855159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1423 05:42:01.866346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1424 05:42:01.871949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1425 05:42:01.883154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1426 05:42:01.894326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1427 05:42:01.905553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1428 05:42:01.911140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1429 05:42:01.922323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1430 05:42:01.933513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1431 05:42:01.944762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1432 05:42:01.950322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1433 05:42:01.961506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1434 05:42:01.972687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1435 05:42:01.983858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1436 05:42:01.995078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1437 05:42:02.006336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1438 05:42:02.017509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1439 05:42:02.028702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1440 05:42:02.039893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1441 05:42:02.051077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1442 05:42:02.062244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1443 05:42:02.073462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1444 05:42:02.084731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1445 05:42:02.095849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1446 05:42:02.107016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1447 05:42:02.118206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1448 05:42:02.129393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1449 05:42:02.140591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1450 05:42:02.151765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1451 05:42:02.162982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1452 05:42:02.174179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1453 05:42:02.185365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1454 05:42:02.196564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1455 05:42:02.207763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1456 05:42:02.218940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1457 05:42:02.224567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1458 05:42:02.235758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1459 05:42:02.246945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1460 05:42:02.258205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1461 05:42:02.269301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1462 05:42:02.280522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1463 05:42:02.291759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1464 05:42:02.302893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1465 05:42:02.314138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1466 05:42:02.325354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1467 05:42:02.336450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1468 05:42:02.347676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1469 05:42:02.358884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1470 05:42:02.370042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1471 05:42:02.381245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1472 05:42:02.392434 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1473 05:42:02.403707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1474 05:42:02.414820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1475 05:42:02.420417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1476 05:42:02.431629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1477 05:42:02.442900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1478 05:42:02.454027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1479 05:42:02.465195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1480 05:42:02.476370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1481 05:42:02.487518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1482 05:42:02.493216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1483 05:42:02.504442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1484 05:42:02.515550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1485 05:42:02.526778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1486 05:42:02.537928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1487 05:42:02.549140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1488 05:42:02.560310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1489 05:42:02.577112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1490 05:42:02.582790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1491 05:42:02.593879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1492 05:42:02.605177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1493 05:42:02.610877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1494 05:42:02.621919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1495 05:42:02.633100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1496 05:42:02.638818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1497 05:42:02.649927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1498 05:42:02.655478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1499 05:42:02.666695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1500 05:42:02.677900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1501 05:42:02.689078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1502 05:42:02.694684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1503 05:42:02.705826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1504 05:42:02.722746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1505 05:42:02.733854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1506 05:42:02.745038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1507 05:42:02.756220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1508 05:42:02.767414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1509 05:42:02.778604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1510 05:42:02.789804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1511 05:42:02.801013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1512 05:42:02.817771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1513 05:42:02.829060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1514 05:42:02.840205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1515 05:42:02.851372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1516 05:42:02.868166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1517 05:42:02.879349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1518 05:42:02.890563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1519 05:42:02.901838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1520 05:42:02.907349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1521 05:42:02.918526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1522 05:42:02.924172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1523 05:42:02.935421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1524 05:42:02.940954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1525 05:42:02.952175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1526 05:42:02.957734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1527 05:42:02.968929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1528 05:42:02.974521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1529 05:42:02.985716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1530 05:42:02.996885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1531 05:42:03.002495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1532 05:42:03.013687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1533 05:42:03.024882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1534 05:42:03.036137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1535 05:42:03.041745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1536 05:42:03.053014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1537 05:42:03.064214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1538 05:42:03.075390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1539 05:42:03.080908 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1540 05:42:03.086481 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1541 05:42:03.092101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1542 05:42:03.097677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1543 05:42:03.103307 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1544 05:42:03.108937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1545 05:42:03.120097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1546 05:42:03.125674 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1547 05:42:03.136931 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1548 05:42:03.142558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1549 05:42:03.153654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1550 05:42:03.159245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1551 05:42:03.170441 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1552 05:42:03.176071 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1553 05:42:03.181643 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1554 05:42:03.192861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1555 05:42:03.198432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1556 05:42:03.209748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1557 05:42:03.215272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1558 05:42:03.226387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1559 05:42:03.232033 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1560 05:42:03.243174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1561 05:42:03.248899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1562 05:42:03.260005 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1563 05:42:03.265573 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1564 05:42:03.276755 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1565 05:42:03.282473 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1566 05:42:03.288151 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1567 05:42:03.299206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1568 05:42:03.304779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1569 05:42:03.315943 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1570 05:42:03.321584 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1571 05:42:03.332763 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1572 05:42:03.338354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1573 05:42:03.349554 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1574 05:42:03.360752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1575 05:42:03.371934 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1576 05:42:03.383119 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1577 05:42:03.394301 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1578 05:42:03.405508 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1579 05:42:03.416709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1580 05:42:03.427898 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1581 05:42:03.433507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1582 05:42:03.444666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1583 05:42:03.450294 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1584 05:42:03.461522 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1585 05:42:03.467108 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1586 05:42:03.478286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1587 05:42:03.483914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1588 05:42:03.495061 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1589 05:42:03.500802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1590 05:42:03.511908 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1591 05:42:03.517508 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1592 05:42:03.528711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1593 05:42:03.534311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1594 05:42:03.539913 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1595 05:42:03.551115 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1596 05:42:03.556728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1597 05:42:03.567950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1598 05:42:03.573543 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1599 05:42:03.584708 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1600 05:42:03.590308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1601 05:42:03.601585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1602 05:42:03.607149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1603 05:42:03.618288 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1604 05:42:03.618733 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1605 05:42:03.629495 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1606 05:42:03.635086 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1607 05:42:03.646268 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1608 05:42:03.651915 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1609 05:42:03.663091 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1610 05:42:03.668680 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1611 05:42:03.679923 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1612 05:42:03.691037 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1613 05:42:03.702244 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1614 05:42:03.708120 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1615 05:42:03.719114 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1616 05:42:03.724727 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1617 05:42:03.730346 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1618 05:42:03.736055 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1619 05:42:03.741551 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1620 05:42:03.747262 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1621 05:42:03.752831 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1622 05:42:03.763929 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1623 05:42:03.769581 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1624 05:42:03.775147 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1625 05:42:03.781231 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1626 05:42:03.786371 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1627 05:42:03.792097 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1628 05:42:03.803121 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1629 05:42:03.808778 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1630 05:42:03.809279 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1631 05:42:03.819961 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1632 05:42:03.820483 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1633 05:42:03.831260 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1634 05:42:03.831763 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1635 05:42:03.842480 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1636 05:42:03.842964 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1637 05:42:03.853662 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1638 05:42:03.854144 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1639 05:42:03.865144 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1640 05:42:03.865664 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1641 05:42:03.870662 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1642 05:42:03.876259 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1643 05:42:03.883030 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1644 05:42:03.887296 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1645 05:42:03.892907 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1646 05:42:03.898486 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1647 05:42:03.904082 dt_test_unprobed_devices_sh_opp-table skip
1648 05:42:03.912484 dt_test_unprobed_devices_sh_soc skip
1649 05:42:03.912973 dt_test_unprobed_devices_sh_sound pass
1650 05:42:03.916360 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1651 05:42:03.928114 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1652 05:42:03.934463 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1653 05:42:03.935088 dt_test_unprobed_devices_sh fail
1654 05:42:03.938548 + ../../utils/send-to-lava.sh ./output/result.txt
1655 05:42:03.945649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1656 05:42:03.946596 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1658 05:42:03.980114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1659 05:42:03.980883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1661 05:42:04.085071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1662 05:42:04.085976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1664 05:42:04.185147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1665 05:42:04.185796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1667 05:42:04.279299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1668 05:42:04.280126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1670 05:42:04.375767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1671 05:42:04.376574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1673 05:42:04.470980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1674 05:42:04.471788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1676 05:42:04.558588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1677 05:42:04.559383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1679 05:42:04.646902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1680 05:42:04.647763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1682 05:42:04.742822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1683 05:42:04.743572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1685 05:42:04.837683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1686 05:42:04.838420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1688 05:42:04.927016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1689 05:42:04.927760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1691 05:42:05.017381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1692 05:42:05.018135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1694 05:42:05.112266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1695 05:42:05.113028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1697 05:42:05.199168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1698 05:42:05.199946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1700 05:42:05.289087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1701 05:42:05.289851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1703 05:42:05.384347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1704 05:42:05.385131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1706 05:42:05.480191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1707 05:42:05.481050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1709 05:42:05.573961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1710 05:42:05.574807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1712 05:42:05.662829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1713 05:42:05.663627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1715 05:42:05.751881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1716 05:42:05.752649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1718 05:42:05.845891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1719 05:42:05.846613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1721 05:42:05.934084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1722 05:42:05.934805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1724 05:42:06.024412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1725 05:42:06.025145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1727 05:42:06.119046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1728 05:42:06.119773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1730 05:42:06.208195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1731 05:42:06.208912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1733 05:42:06.301582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1734 05:42:06.302305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1736 05:42:06.391087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1737 05:42:06.391810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1739 05:42:06.485558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1740 05:42:06.486281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1742 05:42:06.573978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1743 05:42:06.574704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1745 05:42:06.662321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1746 05:42:06.663050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1748 05:42:06.757299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1749 05:42:06.758073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1751 05:42:06.846052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1752 05:42:06.846783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1754 05:42:06.934380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1755 05:42:06.935131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1757 05:42:07.028493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1758 05:42:07.029233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1760 05:42:07.118484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1761 05:42:07.119216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1763 05:42:07.208436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1764 05:42:07.209186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1766 05:42:07.302806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1767 05:42:07.303538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1769 05:42:07.398329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1770 05:42:07.399063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1772 05:42:07.494785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1773 05:42:07.495516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1775 05:42:07.589762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1776 05:42:07.590506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1778 05:42:07.679008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1779 05:42:07.679750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1781 05:42:07.773794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1782 05:42:07.774544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1784 05:42:07.870188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1785 05:42:07.870940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1787 05:42:07.963742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1788 05:42:07.964518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1790 05:42:08.058350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1791 05:42:08.059114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1793 05:42:08.148043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1794 05:42:08.148832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1796 05:42:08.242808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1797 05:42:08.243587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1799 05:42:08.332202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1800 05:42:08.332985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1802 05:42:08.428210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1803 05:42:08.428983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1805 05:42:08.516518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1806 05:42:08.517278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1808 05:42:08.605487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1809 05:42:08.606258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1811 05:42:08.701069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1812 05:42:08.701831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1814 05:42:08.795713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1815 05:42:08.796532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1817 05:42:08.892071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1818 05:42:08.892833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1820 05:42:08.985987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1821 05:42:08.986746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1823 05:42:09.075491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1824 05:42:09.076279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1826 05:42:09.164426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1827 05:42:09.165167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1829 05:42:09.258151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1830 05:42:09.258886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1832 05:42:09.351748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1833 05:42:09.352626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1835 05:42:09.449613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1836 05:42:09.450509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1838 05:42:09.547735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1839 05:42:09.548449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1841 05:42:09.648469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1842 05:42:09.649383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1844 05:42:09.745684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1845 05:42:09.746772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1847 05:42:09.848383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1848 05:42:09.849503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1850 05:42:09.942841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1851 05:42:09.943693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1853 05:42:10.032255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1854 05:42:10.033009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1856 05:42:10.125842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1857 05:42:10.126580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1859 05:42:10.220460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1860 05:42:10.221206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1862 05:42:10.308648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1863 05:42:10.309371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1865 05:42:10.403221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1866 05:42:10.403954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1868 05:42:10.499314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1869 05:42:10.500065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1871 05:42:10.589403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1872 05:42:10.590146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1874 05:42:10.679815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1875 05:42:10.680633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1877 05:42:10.772804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1878 05:42:10.773585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1880 05:42:10.866359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1881 05:42:10.867163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1883 05:42:10.961521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1884 05:42:10.962274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1886 05:42:11.055362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1887 05:42:11.056108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1889 05:42:11.144601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1890 05:42:11.145325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1892 05:42:11.233249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1893 05:42:11.233977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1895 05:42:11.326831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1896 05:42:11.327548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1898 05:42:11.416253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1899 05:42:11.417028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1901 05:42:11.505210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1902 05:42:11.505956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1904 05:42:11.599311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1905 05:42:11.600059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1907 05:42:11.688500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1908 05:42:11.689233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1910 05:42:11.782430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1911 05:42:11.783177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1913 05:42:11.872236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1914 05:42:11.872949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1916 05:42:11.967782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1917 05:42:11.968555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1919 05:42:12.061560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1920 05:42:12.062305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1922 05:42:12.158133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1923 05:42:12.158917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1925 05:42:12.254875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1926 05:42:12.255676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1928 05:42:12.346593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1929 05:42:12.347405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1931 05:42:12.436058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1932 05:42:12.436861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1934 05:42:12.530597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1935 05:42:12.531392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1937 05:42:12.619448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1938 05:42:12.620210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1940 05:42:12.708715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1941 05:42:12.709533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1943 05:42:12.803799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1944 05:42:12.804707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1946 05:42:12.892947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1947 05:42:12.893718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1949 05:42:12.988324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1950 05:42:12.989090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1952 05:42:13.077151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1953 05:42:13.077937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1955 05:42:13.166813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1956 05:42:13.167606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1958 05:42:13.262546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1959 05:42:13.263326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1961 05:42:13.355848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1962 05:42:13.356646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1964 05:42:13.451532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1965 05:42:13.452343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1967 05:42:13.548611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1968 05:42:13.549387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1970 05:42:13.642104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1971 05:42:13.642876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1973 05:42:13.736484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1974 05:42:13.737258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1976 05:42:13.832076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1977 05:42:13.832848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1979 05:42:13.929210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1980 05:42:13.929989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1982 05:42:14.023311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1983 05:42:14.024097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1985 05:42:14.112438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1986 05:42:14.113211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1988 05:42:14.202937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1989 05:42:14.203884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1991 05:42:14.296448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1992 05:42:14.297259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1994 05:42:14.386764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1995 05:42:14.387542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1997 05:42:14.474941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1998 05:42:14.475698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2000 05:42:14.571048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2001 05:42:14.571809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2003 05:42:14.665759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2004 05:42:14.666526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2006 05:42:14.754738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2007 05:42:14.755490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2009 05:42:14.843768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2010 05:42:14.844568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2012 05:42:14.936695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2013 05:42:14.937457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2015 05:42:15.029150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2017 05:42:15.032578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2018 05:42:15.126242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2020 05:42:15.129410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2021 05:42:15.221426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2023 05:42:15.224680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2024 05:42:15.316013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2025 05:42:15.316819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2027 05:42:15.404610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2028 05:42:15.405411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2030 05:42:15.492973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2031 05:42:15.493756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2033 05:42:15.588319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2034 05:42:15.589214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2036 05:42:15.675475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2037 05:42:15.676292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2039 05:42:15.770876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2040 05:42:15.771650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2042 05:42:15.859748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2043 05:42:15.860668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2045 05:42:15.950985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2046 05:42:15.951806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2048 05:42:16.044515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2049 05:42:16.045281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2051 05:42:16.141128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2052 05:42:16.141860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2054 05:42:16.234778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2055 05:42:16.235501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2057 05:42:16.330392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2058 05:42:16.331116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2060 05:42:16.418480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2061 05:42:16.419208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2063 05:42:16.508591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2064 05:42:16.509312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2066 05:42:16.604610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2067 05:42:16.605331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2069 05:42:16.694938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2070 05:42:16.695663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2072 05:42:16.788468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2073 05:42:16.789216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2075 05:42:16.877066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2076 05:42:16.877778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2078 05:42:16.968232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2079 05:42:16.968980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2081 05:42:17.061756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2082 05:42:17.062504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2084 05:42:17.148502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2085 05:42:17.149219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2087 05:42:17.239121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2088 05:42:17.239845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2090 05:42:17.328660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2091 05:42:17.329369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2093 05:42:17.423499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2094 05:42:17.424224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2096 05:42:17.512937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2097 05:42:17.513661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2099 05:42:17.603542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2100 05:42:17.604307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2102 05:42:17.697941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2103 05:42:17.698677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2105 05:42:17.791611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2106 05:42:17.792377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2108 05:42:17.886224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2109 05:42:17.886936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2111 05:42:17.976779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2112 05:42:17.977496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2114 05:42:18.068462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2115 05:42:18.069188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2117 05:42:18.156684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2118 05:42:18.157411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2120 05:42:18.248080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2121 05:42:18.248793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2123 05:42:18.342237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2124 05:42:18.342955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2126 05:42:18.436150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2127 05:42:18.436872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2129 05:42:18.524643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2130 05:42:18.525361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2132 05:42:18.611368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2133 05:42:18.612097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2135 05:42:18.707825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2136 05:42:18.708587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2138 05:42:18.801152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2139 05:42:18.801862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2141 05:42:18.890153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2142 05:42:18.890855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2144 05:42:18.978432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2145 05:42:18.979144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2147 05:42:19.074178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2148 05:42:19.074903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2150 05:42:19.163193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2151 05:42:19.163912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2153 05:42:19.252484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2154 05:42:19.253206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2156 05:42:19.346621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2157 05:42:19.347336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2159 05:42:19.434841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2160 05:42:19.435565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2162 05:42:19.525535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2163 05:42:19.526267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2165 05:42:19.618532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2166 05:42:19.619253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2168 05:42:19.712475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2169 05:42:19.713193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2171 05:42:19.808484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2172 05:42:19.809199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2174 05:42:19.902764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2175 05:42:19.903477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2177 05:42:19.992381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2178 05:42:19.993143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2180 05:42:20.078752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2181 05:42:20.079500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2183 05:42:20.174540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2184 05:42:20.175337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2186 05:42:20.264138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2187 05:42:20.264920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2189 05:42:20.360634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2190 05:42:20.361435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2192 05:42:20.450004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2193 05:42:20.450821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2195 05:42:20.538287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2196 05:42:20.539099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2198 05:42:20.634072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2199 05:42:20.634929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2201 05:42:20.722538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2202 05:42:20.723351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2204 05:42:20.819753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2205 05:42:20.820576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2207 05:42:20.911434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2208 05:42:20.912218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2210 05:42:21.007444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2211 05:42:21.008211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2213 05:42:21.092883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2214 05:42:21.093657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2216 05:42:21.180915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2217 05:42:21.181705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2219 05:42:21.274721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2220 05:42:21.275485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2222 05:42:21.369686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2223 05:42:21.370516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2225 05:42:21.465566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2226 05:42:21.466347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2228 05:42:21.559896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2229 05:42:21.560740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2231 05:42:21.648605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2232 05:42:21.649387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2234 05:42:21.738286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2235 05:42:21.739056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2237 05:42:21.831716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2238 05:42:21.832592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2240 05:42:21.920620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2241 05:42:21.921376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2243 05:42:22.010412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2244 05:42:22.011253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2246 05:42:22.106186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2247 05:42:22.106964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2249 05:42:22.197815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2250 05:42:22.198609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2252 05:42:22.293870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2253 05:42:22.294659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2255 05:42:22.383459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2256 05:42:22.384332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2258 05:42:22.470698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2259 05:42:22.471440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2261 05:42:22.566013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2262 05:42:22.566754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2264 05:42:22.661341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2265 05:42:22.662170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2267 05:42:22.751123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2268 05:42:22.751918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2270 05:42:22.840012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2271 05:42:22.840804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2273 05:42:22.935069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2274 05:42:22.935854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2276 05:42:23.028984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2277 05:42:23.029791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2279 05:42:23.123907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2280 05:42:23.124745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2282 05:42:23.207734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2283 05:42:23.208565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2285 05:42:23.298059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2286 05:42:23.298839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2288 05:42:23.393960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2289 05:42:23.394744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2291 05:42:23.483339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2292 05:42:23.484133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2294 05:42:23.573390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2295 05:42:23.574171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2297 05:42:23.666928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2298 05:42:23.667717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2300 05:42:23.755694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2301 05:42:23.756519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2303 05:42:23.850648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2304 05:42:23.851429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2306 05:42:23.940677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2307 05:42:23.941464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2309 05:42:24.033347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2310 05:42:24.034153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2312 05:42:24.121958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2313 05:42:24.122751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2315 05:42:24.210646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2316 05:42:24.211437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2318 05:42:24.299917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2319 05:42:24.300743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2321 05:42:24.394759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2322 05:42:24.395543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2324 05:42:24.484517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2325 05:42:24.485339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2327 05:42:24.575930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2328 05:42:24.576786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2330 05:42:24.669911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2331 05:42:24.670719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2333 05:42:24.765834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2334 05:42:24.766641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2336 05:42:24.851857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2338 05:42:24.855019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2339 05:42:24.945497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2340 05:42:24.946303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2342 05:42:25.041516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2343 05:42:25.042356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2345 05:42:25.135171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2346 05:42:25.136017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2348 05:42:25.353941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2349 05:42:25.354767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2351 05:42:25.464758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2352 05:42:25.465560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2354 05:42:25.557184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2355 05:42:25.557952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2357 05:42:25.650204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2358 05:42:25.650981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2360 05:42:25.738877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2361 05:42:25.739643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2363 05:42:25.828082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2364 05:42:25.828851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2366 05:42:25.920398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2367 05:42:25.921157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2369 05:42:26.009865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2370 05:42:26.010632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2372 05:42:26.102443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2373 05:42:26.103224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2375 05:42:26.191930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2376 05:42:26.192736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2378 05:42:26.279181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2379 05:42:26.279944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2381 05:42:26.375074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2382 05:42:26.375838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2384 05:42:26.462169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2385 05:42:26.462938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2387 05:42:26.551266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2388 05:42:26.552066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2390 05:42:26.639600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2391 05:42:26.640410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2393 05:42:26.733546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2394 05:42:26.734312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2396 05:42:26.822344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2397 05:42:26.823114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2399 05:42:26.910775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2400 05:42:26.911563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2402 05:42:27.005315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2403 05:42:27.006065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2405 05:42:27.099834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2406 05:42:27.100671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2408 05:42:27.189132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2409 05:42:27.189908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2411 05:42:27.274977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2412 05:42:27.275739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2414 05:42:27.369694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2415 05:42:27.370456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2417 05:42:27.458014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2418 05:42:27.458779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2420 05:42:27.547805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2421 05:42:27.548598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2423 05:42:27.643738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2424 05:42:27.644554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2426 05:42:27.731691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2427 05:42:27.732496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2429 05:42:27.816413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2430 05:42:27.816926 + set +x
2431 05:42:27.817607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2433 05:42:27.820663 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 927075_1.6.2.4.5>
2434 05:42:27.821417 Received signal: <ENDRUN> 1_kselftest-dt 927075_1.6.2.4.5
2435 05:42:27.821884 Ending use of test pattern.
2436 05:42:27.822304 Ending test lava.1_kselftest-dt (927075_1.6.2.4.5), duration 83.85
2438 05:42:27.826904 <LAVA_TEST_RUNNER EXIT>
2439 05:42:27.827651 ok: lava_test_shell seems to have completed
2440 05:42:27.840488 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2441 05:42:27.842409 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2442 05:42:27.843004 end: 3 lava-test-retry (duration 00:01:25) [common]
2443 05:42:27.843596 start: 4 finalize (timeout 00:05:01) [common]
2444 05:42:27.844210 start: 4.1 power-off (timeout 00:00:30) [common]
2445 05:42:27.845226 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2446 05:42:27.878810 >> OK - accepted request
2447 05:42:27.880565 Returned 0 in 0 seconds
2448 05:42:27.981689 end: 4.1 power-off (duration 00:00:00) [common]
2450 05:42:27.983371 start: 4.2 read-feedback (timeout 00:05:01) [common]
2451 05:42:27.984542 Listened to connection for namespace 'common' for up to 1s
2452 05:42:27.985430 Listened to connection for namespace 'common' for up to 1s
2453 05:42:28.787661 Listened to connection for namespace 'common' for up to 1s
2454 05:42:28.984457 Finalising connection for namespace 'common'
2455 05:42:28.985122 Disconnecting from shell: Finalise
2456 05:42:28.985659 / # <3>[ 14
2457 05:42:29.086651 end: 4.2 read-feedback (duration 00:00:01) [common]
2458 05:42:29.087436 end: 4 finalize (duration 00:00:01) [common]
2459 05:42:29.088178 Cleaning after the job
2460 05:42:29.088845 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/ramdisk
2461 05:42:29.091448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/kernel
2462 05:42:29.093387 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/dtb
2463 05:42:29.094532 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/nfsrootfs
2464 05:42:29.140913 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927075/tftp-deploy-abo80gkx/modules
2465 05:42:29.144535 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927075
2466 05:42:31.966319 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927075
2467 05:42:31.966900 Job finished correctly