Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 05:59:49.919177 lava-dispatcher, installed at version: 2024.01
2 05:59:49.920083 start: 0 validate
3 05:59:49.920603 Start time: 2024-11-02 05:59:49.920570+00:00 (UTC)
4 05:59:49.921174 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:59:49.921773 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 05:59:49.966651 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:59:49.967215 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fkernel%2FzImage exists
8 05:59:50.003943 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:59:50.004632 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 05:59:50.039310 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:59:50.039827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 05:59:50.073493 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:59:50.074031 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fmodules.tar.xz exists
14 05:59:50.119082 validate duration: 0.20
16 05:59:50.120733 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:59:50.121358 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:59:50.121948 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:59:50.122953 Not decompressing ramdisk as can be used compressed.
20 05:59:50.123651 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 05:59:50.124186 saving as /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/ramdisk/initrd.cpio.gz
22 05:59:50.124709 total size: 4775763 (4 MB)
23 05:59:50.166811 progress 0 % (0 MB)
24 05:59:50.174660 progress 5 % (0 MB)
25 05:59:50.182128 progress 10 % (0 MB)
26 05:59:50.189539 progress 15 % (0 MB)
27 05:59:50.197713 progress 20 % (0 MB)
28 05:59:50.204095 progress 25 % (1 MB)
29 05:59:50.207529 progress 30 % (1 MB)
30 05:59:50.211382 progress 35 % (1 MB)
31 05:59:50.214874 progress 40 % (1 MB)
32 05:59:50.218330 progress 45 % (2 MB)
33 05:59:50.221752 progress 50 % (2 MB)
34 05:59:50.225570 progress 55 % (2 MB)
35 05:59:50.229064 progress 60 % (2 MB)
36 05:59:50.232467 progress 65 % (2 MB)
37 05:59:50.236333 progress 70 % (3 MB)
38 05:59:50.239613 progress 75 % (3 MB)
39 05:59:50.243161 progress 80 % (3 MB)
40 05:59:50.246585 progress 85 % (3 MB)
41 05:59:50.250493 progress 90 % (4 MB)
42 05:59:50.253700 progress 95 % (4 MB)
43 05:59:50.256717 progress 100 % (4 MB)
44 05:59:50.257423 4 MB downloaded in 0.13 s (34.32 MB/s)
45 05:59:50.257972 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:59:50.258856 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:59:50.259151 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:59:50.259419 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:59:50.259909 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-16/kernel/zImage
51 05:59:50.260537 saving as /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/kernel/zImage
52 05:59:50.261018 total size: 12042752 (11 MB)
53 05:59:50.261333 No compression specified
54 05:59:50.297323 progress 0 % (0 MB)
55 05:59:50.305317 progress 5 % (0 MB)
56 05:59:50.313199 progress 10 % (1 MB)
57 05:59:50.321480 progress 15 % (1 MB)
58 05:59:50.329336 progress 20 % (2 MB)
59 05:59:50.337107 progress 25 % (2 MB)
60 05:59:50.345251 progress 30 % (3 MB)
61 05:59:50.353195 progress 35 % (4 MB)
62 05:59:50.361389 progress 40 % (4 MB)
63 05:59:50.369131 progress 45 % (5 MB)
64 05:59:50.376877 progress 50 % (5 MB)
65 05:59:50.385191 progress 55 % (6 MB)
66 05:59:50.392968 progress 60 % (6 MB)
67 05:59:50.400697 progress 65 % (7 MB)
68 05:59:50.409182 progress 70 % (8 MB)
69 05:59:50.416994 progress 75 % (8 MB)
70 05:59:50.425079 progress 80 % (9 MB)
71 05:59:50.432794 progress 85 % (9 MB)
72 05:59:50.440507 progress 90 % (10 MB)
73 05:59:50.448650 progress 95 % (10 MB)
74 05:59:50.455933 progress 100 % (11 MB)
75 05:59:50.456537 11 MB downloaded in 0.20 s (58.74 MB/s)
76 05:59:50.457015 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:59:50.457838 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:59:50.458109 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:59:50.458369 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:59:50.458820 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
82 05:59:50.459087 saving as /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/dtb/am335x-boneblack.dtb
83 05:59:50.459296 total size: 70568 (0 MB)
84 05:59:50.459505 No compression specified
85 05:59:50.495317 progress 46 % (0 MB)
86 05:59:50.496409 progress 92 % (0 MB)
87 05:59:50.497104 progress 100 % (0 MB)
88 05:59:50.497516 0 MB downloaded in 0.04 s (1.76 MB/s)
89 05:59:50.497991 end: 1.3.1 http-download (duration 00:00:00) [common]
91 05:59:50.498823 end: 1.3 download-retry (duration 00:00:00) [common]
92 05:59:50.499102 start: 1.4 download-retry (timeout 00:10:00) [common]
93 05:59:50.499376 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 05:59:50.499827 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 05:59:50.500115 saving as /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/nfsrootfs/full.rootfs.tar
96 05:59:50.500334 total size: 117747780 (112 MB)
97 05:59:50.500554 Using unxz to decompress xz
98 05:59:50.536112 progress 0 % (0 MB)
99 05:59:51.276663 progress 5 % (5 MB)
100 05:59:52.005282 progress 10 % (11 MB)
101 05:59:52.766318 progress 15 % (16 MB)
102 05:59:53.471479 progress 20 % (22 MB)
103 05:59:54.045147 progress 25 % (28 MB)
104 05:59:54.836453 progress 30 % (33 MB)
105 05:59:55.629467 progress 35 % (39 MB)
106 05:59:55.976125 progress 40 % (44 MB)
107 05:59:56.326531 progress 45 % (50 MB)
108 05:59:56.966884 progress 50 % (56 MB)
109 05:59:57.763167 progress 55 % (61 MB)
110 05:59:58.480786 progress 60 % (67 MB)
111 05:59:59.192496 progress 65 % (73 MB)
112 05:59:59.952955 progress 70 % (78 MB)
113 06:00:00.702274 progress 75 % (84 MB)
114 06:00:01.419302 progress 80 % (89 MB)
115 06:00:02.113928 progress 85 % (95 MB)
116 06:00:02.881913 progress 90 % (101 MB)
117 06:00:03.628081 progress 95 % (106 MB)
118 06:00:04.431243 progress 100 % (112 MB)
119 06:00:04.443657 112 MB downloaded in 13.94 s (8.05 MB/s)
120 06:00:04.444359 end: 1.4.1 http-download (duration 00:00:14) [common]
122 06:00:04.445960 end: 1.4 download-retry (duration 00:00:14) [common]
123 06:00:04.446467 start: 1.5 download-retry (timeout 00:09:46) [common]
124 06:00:04.446966 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 06:00:04.447753 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-16/modules.tar.xz
126 06:00:04.448249 saving as /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/modules/modules.tar
127 06:00:04.448659 total size: 6909296 (6 MB)
128 06:00:04.449070 Using unxz to decompress xz
129 06:00:04.492774 progress 0 % (0 MB)
130 06:00:04.528021 progress 5 % (0 MB)
131 06:00:04.574802 progress 10 % (0 MB)
132 06:00:04.618899 progress 15 % (1 MB)
133 06:00:04.666313 progress 20 % (1 MB)
134 06:00:04.709424 progress 25 % (1 MB)
135 06:00:04.756899 progress 30 % (2 MB)
136 06:00:04.799526 progress 35 % (2 MB)
137 06:00:04.846645 progress 40 % (2 MB)
138 06:00:04.890417 progress 45 % (2 MB)
139 06:00:04.938028 progress 50 % (3 MB)
140 06:00:04.980429 progress 55 % (3 MB)
141 06:00:05.027282 progress 60 % (3 MB)
142 06:00:05.073744 progress 65 % (4 MB)
143 06:00:05.114716 progress 70 % (4 MB)
144 06:00:05.165047 progress 75 % (4 MB)
145 06:00:05.210528 progress 80 % (5 MB)
146 06:00:05.258427 progress 85 % (5 MB)
147 06:00:05.301342 progress 90 % (5 MB)
148 06:00:05.352313 progress 95 % (6 MB)
149 06:00:05.394942 progress 100 % (6 MB)
150 06:00:05.408658 6 MB downloaded in 0.96 s (6.86 MB/s)
151 06:00:05.409241 end: 1.5.1 http-download (duration 00:00:01) [common]
153 06:00:05.410076 end: 1.5 download-retry (duration 00:00:01) [common]
154 06:00:05.410346 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 06:00:05.410611 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 06:00:21.513904 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69
157 06:00:21.514517 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 06:00:21.514804 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 06:00:21.515494 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a
160 06:00:21.515938 makedir: /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin
161 06:00:21.516354 makedir: /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/tests
162 06:00:21.516686 makedir: /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/results
163 06:00:21.517018 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-add-keys
164 06:00:21.517536 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-add-sources
165 06:00:21.518039 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-background-process-start
166 06:00:21.518538 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-background-process-stop
167 06:00:21.519069 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-common-functions
168 06:00:21.519578 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-echo-ipv4
169 06:00:21.520091 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-install-packages
170 06:00:21.520579 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-installed-packages
171 06:00:21.521048 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-os-build
172 06:00:21.521521 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-probe-channel
173 06:00:21.521992 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-probe-ip
174 06:00:21.522458 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-target-ip
175 06:00:21.522974 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-target-mac
176 06:00:21.523492 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-target-storage
177 06:00:21.524003 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-case
178 06:00:21.524512 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-event
179 06:00:21.524988 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-feedback
180 06:00:21.525468 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-raise
181 06:00:21.525940 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-reference
182 06:00:21.526430 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-runner
183 06:00:21.526955 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-set
184 06:00:21.527471 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-test-shell
185 06:00:21.527964 Updating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-add-keys (debian)
186 06:00:21.528540 Updating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-add-sources (debian)
187 06:00:21.529071 Updating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-install-packages (debian)
188 06:00:21.529595 Updating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-installed-packages (debian)
189 06:00:21.530095 Updating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/bin/lava-os-build (debian)
190 06:00:21.530528 Creating /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/environment
191 06:00:21.530916 LAVA metadata
192 06:00:21.531172 - LAVA_JOB_ID=927182
193 06:00:21.531385 - LAVA_DISPATCHER_IP=192.168.6.2
194 06:00:21.531743 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 06:00:21.532720 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 06:00:21.533034 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 06:00:21.533237 skipped lava-vland-overlay
198 06:00:21.533474 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 06:00:21.533726 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 06:00:21.533941 skipped lava-multinode-overlay
201 06:00:21.534178 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 06:00:21.534422 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 06:00:21.534665 Loading test definitions
204 06:00:21.534936 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 06:00:21.535153 Using /lava-927182 at stage 0
206 06:00:21.536245 uuid=927182_1.6.2.4.1 testdef=None
207 06:00:21.536558 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 06:00:21.536819 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 06:00:21.538370 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 06:00:21.539141 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 06:00:21.541074 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 06:00:21.541891 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 06:00:21.543712 runner path: /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/0/tests/0_timesync-off test_uuid 927182_1.6.2.4.1
216 06:00:21.544285 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 06:00:21.545099 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 06:00:21.545320 Using /lava-927182 at stage 0
220 06:00:21.545666 Fetching tests from https://github.com/kernelci/test-definitions.git
221 06:00:21.545954 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/0/tests/1_kselftest-dt'
222 06:00:24.971485 Running '/usr/bin/git checkout kernelci.org
223 06:00:25.421831 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 06:00:25.423276 uuid=927182_1.6.2.4.5 testdef=None
225 06:00:25.423623 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 06:00:25.424419 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 06:00:25.427263 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 06:00:25.428122 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 06:00:25.431803 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 06:00:25.432667 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 06:00:25.436251 runner path: /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/0/tests/1_kselftest-dt test_uuid 927182_1.6.2.4.5
235 06:00:25.436537 BOARD='beaglebone-black'
236 06:00:25.436739 BRANCH='mainline'
237 06:00:25.436934 SKIPFILE='/dev/null'
238 06:00:25.437129 SKIP_INSTALL='True'
239 06:00:25.437321 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
240 06:00:25.437520 TST_CASENAME=''
241 06:00:25.437712 TST_CMDFILES='dt'
242 06:00:25.438262 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 06:00:25.439043 Creating lava-test-runner.conf files
245 06:00:25.439246 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927182/lava-overlay-u7kaii6a/lava-927182/0 for stage 0
246 06:00:25.439661 - 0_timesync-off
247 06:00:25.439908 - 1_kselftest-dt
248 06:00:25.440266 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 06:00:25.440547 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 06:00:48.574224 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 06:00:48.574693 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
252 06:00:48.574958 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 06:00:48.575233 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 06:00:48.575496 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
255 06:00:48.934059 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 06:00:48.934541 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 06:00:48.934811 extracting modules file /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69
258 06:00:49.811337 extracting modules file /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927182/extract-overlay-ramdisk-ri_32i07/ramdisk
259 06:00:50.714176 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 06:00:50.714650 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 06:00:50.714923 [common] Applying overlay to NFS
262 06:00:50.715137 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927182/compress-overlay-v3rk_fx9/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69
263 06:00:53.511704 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 06:00:53.512209 start: 1.6.6 prepare-kernel (timeout 00:08:57) [common]
265 06:00:53.512489 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:57) [common]
266 06:00:53.512768 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 06:00:53.513022 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 06:00:53.513279 start: 1.6.7 configure-preseed-file (timeout 00:08:57) [common]
269 06:00:53.513527 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 06:00:53.513782 start: 1.6.8 compress-ramdisk (timeout 00:08:57) [common]
271 06:00:53.514033 Building ramdisk /var/lib/lava/dispatcher/tmp/927182/extract-overlay-ramdisk-ri_32i07/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927182/extract-overlay-ramdisk-ri_32i07/ramdisk
272 06:00:54.540935 >> 78981 blocks
273 06:00:59.616748 Adding RAMdisk u-boot header.
274 06:00:59.617493 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927182/extract-overlay-ramdisk-ri_32i07/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927182/extract-overlay-ramdisk-ri_32i07/ramdisk.cpio.gz.uboot
275 06:00:59.805023 output: Image Name:
276 06:00:59.805446 output: Created: Sat Nov 2 06:00:59 2024
277 06:00:59.805657 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 06:00:59.805862 output: Data Size: 15349010 Bytes = 14989.27 KiB = 14.64 MiB
279 06:00:59.806064 output: Load Address: 00000000
280 06:00:59.806263 output: Entry Point: 00000000
281 06:00:59.806462 output:
282 06:00:59.807106 rename /var/lib/lava/dispatcher/tmp/927182/extract-overlay-ramdisk-ri_32i07/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot
283 06:00:59.807531 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 06:00:59.807819 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 06:00:59.808297 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 06:00:59.808811 No LXC device requested
287 06:00:59.809385 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 06:00:59.809945 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 06:00:59.810485 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 06:00:59.810938 Checking files for TFTP limit of 4294967296 bytes.
291 06:00:59.813877 end: 1 tftp-deploy (duration 00:01:10) [common]
292 06:00:59.814511 start: 2 uboot-action (timeout 00:05:00) [common]
293 06:00:59.815085 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 06:00:59.815632 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 06:00:59.816216 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 06:00:59.817042 substitutions:
297 06:00:59.817507 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 06:00:59.817971 - {DTB_ADDR}: 0x88000000
299 06:00:59.818411 - {DTB}: 927182/tftp-deploy-dbbtyzeq/dtb/am335x-boneblack.dtb
300 06:00:59.818848 - {INITRD}: 927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot
301 06:00:59.819285 - {KERNEL_ADDR}: 0x82000000
302 06:00:59.819717 - {KERNEL}: 927182/tftp-deploy-dbbtyzeq/kernel/zImage
303 06:00:59.820183 - {LAVA_MAC}: None
304 06:00:59.820663 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69
305 06:00:59.821102 - {NFS_SERVER_IP}: 192.168.6.2
306 06:00:59.821532 - {PRESEED_CONFIG}: None
307 06:00:59.821961 - {PRESEED_LOCAL}: None
308 06:00:59.822387 - {RAMDISK_ADDR}: 0x83000000
309 06:00:59.822818 - {RAMDISK}: 927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot
310 06:00:59.823249 - {ROOT_PART}: None
311 06:00:59.823673 - {ROOT}: None
312 06:00:59.824124 - {SERVER_IP}: 192.168.6.2
313 06:00:59.824553 - {TEE_ADDR}: 0x83000000
314 06:00:59.824980 - {TEE}: None
315 06:00:59.825401 Parsed boot commands:
316 06:00:59.825811 - setenv autoload no
317 06:00:59.826231 - setenv initrd_high 0xffffffff
318 06:00:59.826655 - setenv fdt_high 0xffffffff
319 06:00:59.827074 - dhcp
320 06:00:59.827492 - setenv serverip 192.168.6.2
321 06:00:59.827914 - tftp 0x82000000 927182/tftp-deploy-dbbtyzeq/kernel/zImage
322 06:00:59.828371 - tftp 0x83000000 927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot
323 06:00:59.828797 - setenv initrd_size ${filesize}
324 06:00:59.829217 - tftp 0x88000000 927182/tftp-deploy-dbbtyzeq/dtb/am335x-boneblack.dtb
325 06:00:59.829639 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 06:00:59.830077 - bootz 0x82000000 0x83000000 0x88000000
327 06:00:59.830620 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 06:00:59.832255 start: 2.3 connect-device (timeout 00:05:00) [common]
330 06:00:59.832720 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 06:00:59.848198 Setting prompt string to ['lava-test: # ']
332 06:00:59.849789 end: 2.3 connect-device (duration 00:00:00) [common]
333 06:00:59.850434 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 06:00:59.851033 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 06:00:59.851609 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 06:00:59.852950 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 06:00:59.891045 >> OK - accepted request
338 06:00:59.893161 Returned 0 in 0 seconds
339 06:00:59.994330 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 06:00:59.996105 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 06:00:59.996729 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 06:00:59.997285 Setting prompt string to ['Hit any key to stop autoboot']
344 06:00:59.997780 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 06:00:59.999487 Trying 192.168.56.21...
346 06:01:00.000066 Connected to conserv1.
347 06:01:00.000525 Escape character is '^]'.
348 06:01:00.000975
349 06:01:00.001420 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 06:01:00.001872
351 06:01:07.094282
352 06:01:07.094928 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 06:01:07.098669 Trying to boot from MMC1
354 06:01:07.671477
355 06:01:07.672105
356 06:01:07.672558 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 06:01:07.672995
358 06:01:07.676911 CPU : AM335X-GP rev 2.1
359 06:01:07.677401 Model: TI AM335x BeagleBone Black
360 06:01:07.681102 DRAM: 512 MiB
361 06:01:07.763719 Core: 160 devices, 18 uclasses, devicetree: separate
362 06:01:07.773387 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 06:01:11.142819 7[r[999;999H[6n8NAND:
364 06:01:11.143486 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 06:01:11.147867 Trying to boot from MMC1
366 06:01:11.720236
367 06:01:11.720804
368 06:01:11.721273 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 06:01:11.721731
370 06:01:11.725645 CPU : AM335X-GP rev 2.1
371 06:01:11.726124 Model: TI AM335x BeagleBone Black
372 06:01:11.729840 DRAM: 512 MiB
373 06:01:11.812554 Core: 160 devices, 18 uclasses, devicetree: separate
374 06:01:11.822279 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 06:01:13.841801 7[r[999;999H[6n8NAND:
376 06:01:13.842444 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 06:01:13.846215 Trying to boot from MMC1
378 06:01:14.419200
379 06:01:14.419823
380 06:01:14.420342 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 06:01:14.420795
382 06:01:14.424679 CPU : AM335X-GP rev 2.1
383 06:01:14.425180 Model: TI AM335x BeagleBone Black
384 06:01:14.428488 DRAM: 512 MiB
385 06:01:14.510473 Core: 160 devices, 18 uclasses, devicetree: separate
386 06:01:14.521049 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 06:01:15.025381 7[r[999;999H[6n8NAND: 0 MiB
388 06:01:15.036307 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 06:01:15.109151 Loading Environment from FAT... Unable to use mmc 0:1...
390 06:01:15.129617 <ethaddr> not set. Validating first E-fuse MAC
391 06:01:15.160391 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 06:01:15.219598 Hit any key to stop autoboot: 2
394 06:01:15.220496 end: 2.4.2 bootloader-interrupt (duration 00:00:15) [common]
395 06:01:15.221145 start: 2.4.3 bootloader-commands (timeout 00:04:45) [common]
396 06:01:15.221669 Setting prompt string to ['=>']
397 06:01:15.222200 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:45)
398 06:01:15.228493 0
399 06:01:15.229402 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 06:01:15.229942 Sending with 10 millisecond of delay
402 06:01:16.364692 => setenv autoload no
403 06:01:16.375537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 06:01:16.381021 setenv autoload no
405 06:01:16.381793 Sending with 10 millisecond of delay
407 06:01:18.179146 => setenv initrd_high 0xffffffff
408 06:01:18.189982 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
409 06:01:18.190934 setenv initrd_high 0xffffffff
410 06:01:18.191700 Sending with 10 millisecond of delay
412 06:01:19.808218 => setenv fdt_high 0xffffffff
413 06:01:19.819041 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
414 06:01:19.819950 setenv fdt_high 0xffffffff
415 06:01:19.820781 Sending with 10 millisecond of delay
417 06:01:20.112672 => dhcp
418 06:01:20.123434 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
419 06:01:20.124370 dhcp
420 06:01:20.124857 link up on port 0, speed 100, full duplex
421 06:01:20.125311 BOOTP broadcast 1
422 06:01:20.151599 DHCP client bound to address 192.168.6.12 (23 ms)
423 06:01:20.152405 Sending with 10 millisecond of delay
425 06:01:21.828908 => setenv serverip 192.168.6.2
426 06:01:21.839753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
427 06:01:21.840739 setenv serverip 192.168.6.2
428 06:01:21.841480 Sending with 10 millisecond of delay
430 06:01:25.325133 => tftp 0x82000000 927182/tftp-deploy-dbbtyzeq/kernel/zImage
431 06:01:25.335712 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 06:01:25.336279 tftp 0x82000000 927182/tftp-deploy-dbbtyzeq/kernel/zImage
433 06:01:25.336556 link up on port 0, speed 100, full duplex
434 06:01:25.340410 Using ethernet@4a100000 device
435 06:01:25.346051 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 06:01:25.346342 Filename '927182/tftp-deploy-dbbtyzeq/kernel/zImage'.
437 06:01:25.349590 Load address: 0x82000000
438 06:01:27.856379 Loading: *################################################## 11.5 MiB
439 06:01:27.856981 4.6 MiB/s
440 06:01:27.857418 done
441 06:01:27.859827 Bytes transferred = 12042752 (b7c200 hex)
442 06:01:27.860652 Sending with 10 millisecond of delay
444 06:01:32.305919 => tftp 0x83000000 927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot
445 06:01:32.316661 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 06:01:32.317470 tftp 0x83000000 927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot
447 06:01:32.317930 link up on port 0, speed 100, full duplex
448 06:01:32.321376 Using ethernet@4a100000 device
449 06:01:32.326970 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 06:01:32.330237 Filename '927182/tftp-deploy-dbbtyzeq/ramdisk/ramdisk.cpio.gz.uboot'.
451 06:01:32.334425 Load address: 0x83000000
452 06:01:35.391370 Loading: *################################################## 14.6 MiB
453 06:01:35.391967 4.8 MiB/s
454 06:01:35.392442 done
455 06:01:35.395541 Bytes transferred = 15349074 (ea3552 hex)
456 06:01:35.396456 Sending with 10 millisecond of delay
458 06:01:37.253048 => setenv initrd_size ${filesize}
459 06:01:37.263755 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
460 06:01:37.264594 setenv initrd_size ${filesize}
461 06:01:37.265314 Sending with 10 millisecond of delay
463 06:01:41.408909 => tftp 0x88000000 927182/tftp-deploy-dbbtyzeq/dtb/am335x-boneblack.dtb
464 06:01:41.419675 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 06:01:41.420605 tftp 0x88000000 927182/tftp-deploy-dbbtyzeq/dtb/am335x-boneblack.dtb
466 06:01:41.421037 link up on port 0, speed 100, full duplex
467 06:01:41.424427 Using ethernet@4a100000 device
468 06:01:41.430041 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 06:01:41.442212 Filename '927182/tftp-deploy-dbbtyzeq/dtb/am335x-boneblack.dtb'.
470 06:01:41.442650 Load address: 0x88000000
471 06:01:41.453534 Loading: *################################################## 68.9 KiB
472 06:01:41.453979 4.5 MiB/s
473 06:01:41.454371 done
474 06:01:41.460172 Bytes transferred = 70568 (113a8 hex)
475 06:01:41.460868 Sending with 10 millisecond of delay
477 06:01:54.632842 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 06:01:54.643629 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 06:01:54.644529 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 06:01:54.645235 Sending with 10 millisecond of delay
482 06:01:56.983774 => bootz 0x82000000 0x83000000 0x88000000
483 06:01:56.994615 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 06:01:56.995145 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
485 06:01:56.996157 bootz 0x82000000 0x83000000 0x88000000
486 06:01:56.996599 Kernel image @ 0x82000000 [ 0x000000 - 0xb7c200 ]
487 06:01:56.997092 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 06:01:57.002172 Image Name:
489 06:01:57.002612 Created: 2024-11-02 6:00:59 UTC
490 06:01:57.011046 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 06:01:57.011482 Data Size: 15349010 Bytes = 14.6 MiB
492 06:01:57.019424 Load Address: 00000000
493 06:01:57.019851 Entry Point: 00000000
494 06:01:57.194166 Verifying Checksum ... OK
495 06:01:57.194642 ## Flattened Device Tree blob at 88000000
496 06:01:57.200669 Booting using the fdt blob at 0x88000000
497 06:01:57.205601 Using Device Tree in place at 88000000, end 880143a7
498 06:01:57.219243
499 06:01:57.219680 Starting kernel ...
500 06:01:57.220126
501 06:01:57.220986 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 06:01:57.221568 start: 2.4.4 auto-login-action (timeout 00:04:03) [common]
503 06:01:57.222035 Setting prompt string to ['Linux version [0-9]']
504 06:01:57.222493 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 06:01:57.222960 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 06:01:58.115669 [ 0.000000] Booting Linux on physical CPU 0x0
507 06:01:58.121451 start: 2.4.4.1 login-action (timeout 00:04:02) [common]
508 06:01:58.121996 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 06:01:58.122456 Setting prompt string to []
510 06:01:58.122938 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 06:01:58.123398 Using line separator: #'\n'#
512 06:01:58.123800 No login prompt set.
513 06:01:58.124265 Parsing kernel messages
514 06:01:58.124660 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 06:01:58.125418 [login-action] Waiting for messages, (timeout 00:04:02)
516 06:01:58.125859 Waiting using forced prompt support (timeout 00:02:01)
517 06:01:58.132533 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j359728-arm-clang-16-multi-v7-defconfig-px8jk) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Sat Nov 2 04:46:02 UTC 2024
518 06:01:58.143944 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 06:01:58.149749 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 06:01:58.155415 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 06:01:58.161045 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 06:01:58.166787 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 06:01:58.172466 [ 0.000000] Memory policy: Data cache writeback
524 06:01:58.179155 [ 0.000000] efi: UEFI not found.
525 06:01:58.179572 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 06:01:58.187906 [ 0.000000] Zone ranges:
527 06:01:58.193628 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 06:01:58.199375 [ 0.000000] Normal empty
529 06:01:58.199795 [ 0.000000] HighMem empty
530 06:01:58.205197 [ 0.000000] Movable zone start for each node
531 06:01:58.205626 [ 0.000000] Early memory node ranges
532 06:01:58.216613 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 06:01:58.221914 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 06:01:58.240034 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 06:01:58.245680 [ 0.000000] AM335X ES2.1 (sgx neon)
536 06:01:58.257407 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
537 06:01:58.275094 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 06:01:58.286639 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 06:01:58.292374 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 06:01:58.298118 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 06:01:58.308218 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 06:01:58.337490 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 06:01:58.343409 <6>[ 0.000000] trace event string verifier disabled
544 06:01:58.343836 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 06:01:58.351544 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 06:01:58.357302 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 06:01:58.368710 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 06:01:58.373575 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 06:01:58.388714 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 06:01:58.406375 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 06:01:58.413099 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 06:01:58.513052 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 06:01:58.524514 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 06:01:58.531282 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 06:01:58.544333 <6>[ 0.019185] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 06:01:58.551894 <6>[ 0.034220] Console: colour dummy device 80x30
557 06:01:58.558022 Matched prompt #6: WARNING:
558 06:01:58.558486 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 06:01:58.563438 <3>[ 0.039119] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 06:01:58.566302 <3>[ 0.046195] This ensures that you still see kernel messages. Please
561 06:01:58.572431 <3>[ 0.052923] update your kernel commandline.
562 06:01:58.612874 <6>[ 0.057534] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 06:01:58.618602 <6>[ 0.096198] CPU: Testing write buffer coherency: ok
564 06:01:58.624554 <6>[ 0.101561] CPU0: Spectre v2: using BPIALL workaround
565 06:01:58.624975 <6>[ 0.107023] pid_max: default: 32768 minimum: 301
566 06:01:58.636070 <6>[ 0.112223] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 06:01:58.642989 <6>[ 0.120047] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 06:01:58.650134 <6>[ 0.129417] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 06:01:58.658602 <6>[ 0.136446] Setting up static identity map for 0x80300000 - 0x803000ac
570 06:01:58.664402 <6>[ 0.146170] rcu: Hierarchical SRCU implementation.
571 06:01:58.672048 <6>[ 0.151455] rcu: Max phase no-delay instances is 1000.
572 06:01:58.680846 <6>[ 0.162864] EFI services will not be available.
573 06:01:58.686660 <6>[ 0.168158] smp: Bringing up secondary CPUs ...
574 06:01:58.692430 <6>[ 0.173216] smp: Brought up 1 node, 1 CPU
575 06:01:58.698310 <6>[ 0.177615] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 06:01:58.704200 <6>[ 0.184386] CPU: All CPU(s) started in SVC mode.
577 06:01:58.724516 <6>[ 0.189592] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
578 06:01:58.724949 <6>[ 0.205890] devtmpfs: initialized
579 06:01:58.748295 <6>[ 0.224516] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 06:01:58.759824 <6>[ 0.233122] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 06:01:58.765799 <6>[ 0.243586] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 06:01:58.776473 <6>[ 0.255865] pinctrl core: initialized pinctrl subsystem
583 06:01:58.786019 <6>[ 0.266713] DMI not present or invalid.
584 06:01:58.794382 <6>[ 0.272605] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 06:01:58.803897 <6>[ 0.281595] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 06:01:58.819158 <6>[ 0.293208] thermal_sys: Registered thermal governor 'step_wise'
587 06:01:58.819583 <6>[ 0.293386] cpuidle: using governor menu
588 06:01:58.846518 <6>[ 0.328798] No ATAGs?
589 06:01:58.852733 <6>[ 0.331535] hw-breakpoint: debug architecture 0x4 unsupported.
590 06:01:58.863056 <6>[ 0.343627] Serial: AMBA PL011 UART driver
591 06:01:58.893935 <6>[ 0.376188] iommu: Default domain type: Translated
592 06:01:58.903135 <6>[ 0.381539] iommu: DMA domain TLB invalidation policy: strict mode
593 06:01:58.929664 <5>[ 0.410589] SCSI subsystem initialized
594 06:01:58.943523 <6>[ 0.420172] usbcore: registered new interface driver usbfs
595 06:01:58.950492 <6>[ 0.426136] usbcore: registered new interface driver hub
596 06:01:58.950918 <6>[ 0.431986] usbcore: registered new device driver usb
597 06:01:58.956336 <6>[ 0.438537] pps_core: LinuxPPS API ver. 1 registered
598 06:01:58.967781 <6>[ 0.443973] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 06:01:58.976574 <6>[ 0.453694] PTP clock support registered
600 06:01:58.976991 <6>[ 0.458146] EDAC MC: Ver: 3.0.0
601 06:01:59.030477 <6>[ 0.509959] scmi_core: SCMI protocol bus registered
602 06:01:59.036193 <6>[ 0.518147] vgaarb: loaded
603 06:01:59.048584 <6>[ 0.530985] clocksource: Switched to clocksource dmtimer
604 06:01:59.087712 <6>[ 0.569689] NET: Registered PF_INET protocol family
605 06:01:59.100482 <6>[ 0.575397] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 06:01:59.106359 <6>[ 0.584407] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 06:01:59.117739 <6>[ 0.593336] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 06:01:59.123468 <6>[ 0.601596] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 06:01:59.135028 <6>[ 0.609864] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 06:01:59.140924 <6>[ 0.617587] TCP: Hash tables configured (established 4096 bind 4096)
611 06:01:59.146682 <6>[ 0.624508] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 06:01:59.152566 <6>[ 0.631542] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 06:01:59.160176 <6>[ 0.639129] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 06:01:59.241724 <6>[ 0.718346] RPC: Registered named UNIX socket transport module.
615 06:01:59.242162 <6>[ 0.724799] RPC: Registered udp transport module.
616 06:01:59.247492 <6>[ 0.729905] RPC: Registered tcp transport module.
617 06:01:59.256096 <6>[ 0.735028] RPC: Registered tcp-with-tls transport module.
618 06:01:59.261828 <6>[ 0.740954] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 06:01:59.269150 <6>[ 0.747860] PCI: CLS 0 bytes, default 64
620 06:01:59.271500 <5>[ 0.753719] Initialise system trusted keyrings
621 06:01:59.295586 <6>[ 0.774851] Trying to unpack rootfs image as initramfs...
622 06:01:59.365067 <6>[ 0.841149] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 06:01:59.369852 <6>[ 0.848667] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 06:01:59.409948 <5>[ 0.892255] NFS: Registering the id_resolver key type
625 06:01:59.415782 <5>[ 0.897846] Key type id_resolver registered
626 06:01:59.421567 <5>[ 0.902537] Key type id_legacy registered
627 06:01:59.430019 <6>[ 0.906980] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 06:01:59.436951 <6>[ 0.914186] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 06:01:59.519222 <5>[ 1.001561] Key type asymmetric registered
630 06:01:59.525173 <5>[ 1.006088] Asymmetric key parser 'x509' registered
631 06:01:59.536687 <6>[ 1.011639] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 06:01:59.537119 <6>[ 1.019530] io scheduler mq-deadline registered
633 06:01:59.542477 <6>[ 1.024509] io scheduler kyber registered
634 06:01:59.548059 <6>[ 1.028961] io scheduler bfq registered
635 06:01:59.642892 <6>[ 1.121525] ledtrig-cpu: registered to indicate activity on CPUs
636 06:01:59.955577 <6>[ 1.434020] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 06:01:59.983893 <6>[ 1.466109] msm_serial: driver initialized
638 06:01:59.990030 <6>[ 1.470889] SuperH (H)SCI(F) driver initialized
639 06:01:59.995960 <6>[ 1.476235] STMicroelectronics ASC driver initialized
640 06:02:00.001172 <6>[ 1.481906] STM32 USART driver initialized
641 06:02:00.111943 <6>[ 1.593688] brd: module loaded
642 06:02:00.165661 <6>[ 1.647341] loop: module loaded
643 06:02:00.215211 <6>[ 1.696696] CAN device driver interface
644 06:02:00.221746 <6>[ 1.701930] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 06:02:00.227596 <6>[ 1.708851] e1000e: Intel(R) PRO/1000 Network Driver
646 06:02:00.233449 <6>[ 1.714335] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 06:02:00.239143 <6>[ 1.720762] igb: Intel(R) Gigabit Ethernet Network Driver
648 06:02:00.247401 <6>[ 1.726616] igb: Copyright (c) 2007-2014 Intel Corporation.
649 06:02:00.259198 <6>[ 1.735853] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 06:02:00.265023 <6>[ 1.742014] usbcore: registered new interface driver pegasus
651 06:02:00.270818 <6>[ 1.748140] usbcore: registered new interface driver asix
652 06:02:00.276568 <6>[ 1.754029] usbcore: registered new interface driver ax88179_178a
653 06:02:00.282395 <6>[ 1.760598] usbcore: registered new interface driver cdc_ether
654 06:02:00.288201 <6>[ 1.766931] usbcore: registered new interface driver smsc75xx
655 06:02:00.293936 <6>[ 1.773164] usbcore: registered new interface driver smsc95xx
656 06:02:00.299716 <6>[ 1.779385] usbcore: registered new interface driver net1080
657 06:02:00.305518 <6>[ 1.785530] usbcore: registered new interface driver cdc_subset
658 06:02:00.311291 <6>[ 1.791959] usbcore: registered new interface driver zaurus
659 06:02:00.318940 <6>[ 1.798006] usbcore: registered new interface driver cdc_ncm
660 06:02:00.328789 <6>[ 1.807476] usbcore: registered new interface driver usb-storage
661 06:02:00.604865 <6>[ 2.085323] i2c_dev: i2c /dev entries driver
662 06:02:00.662381 <5>[ 2.136771] cpuidle: enable-method property 'ti,am3352' found operations
663 06:02:00.668208 <6>[ 2.146345] sdhci: Secure Digital Host Controller Interface driver
664 06:02:00.675649 <6>[ 2.153120] sdhci: Copyright(c) Pierre Ossman
665 06:02:00.682870 <6>[ 2.159540] Synopsys Designware Multimedia Card Interface Driver
666 06:02:00.688335 <6>[ 2.167482] sdhci-pltfm: SDHCI platform and OF driver helper
667 06:02:00.817143 <6>[ 2.292128] usbcore: registered new interface driver usbhid
668 06:02:00.817582 <6>[ 2.298170] usbhid: USB HID core driver
669 06:02:00.869621 <6>[ 2.349357] NET: Registered PF_INET6 protocol family
670 06:02:00.919547 <6>[ 2.402015] Segment Routing with IPv6
671 06:02:00.925422 <6>[ 2.406166] In-situ OAM (IOAM) with IPv6
672 06:02:00.932188 <6>[ 2.410566] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 06:02:00.939651 <6>[ 2.417995] NET: Registered PF_PACKET protocol family
674 06:02:00.945554 <6>[ 2.423570] can: controller area network core
675 06:02:00.945985 <6>[ 2.428399] NET: Registered PF_CAN protocol family
676 06:02:00.951286 <6>[ 2.433628] can: raw protocol
677 06:02:00.957055 <6>[ 2.436954] can: broadcast manager protocol
678 06:02:00.964063 <6>[ 2.441551] can: netlink gateway - max_hops=1
679 06:02:00.964486 <5>[ 2.447076] Key type dns_resolver registered
680 06:02:00.969795 <6>[ 2.452206] ThumbEE CPU extension supported.
681 06:02:00.976070 <5>[ 2.456895] Registering SWP/SWPB emulation handler
682 06:02:00.984224 <3>[ 2.462598] omap_voltage_late_init: Voltage driver support not added
683 06:02:01.181400 <5>[ 2.661311] Loading compiled-in X.509 certificates
684 06:02:01.321020 <6>[ 2.790403] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 06:02:01.328215 <6>[ 2.807115] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 06:02:01.355071 <3>[ 2.831386] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 06:02:01.555067 <3>[ 3.031369] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 06:02:01.740876 <6>[ 3.221403] OMAP GPIO hardware version 0.1
689 06:02:01.761700 <6>[ 3.240311] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 06:02:01.859496 <4>[ 3.337894] at24 2-0054: supply vcc not found, using dummy regulator
691 06:02:01.897028 <4>[ 3.375429] at24 2-0055: supply vcc not found, using dummy regulator
692 06:02:01.936196 <4>[ 3.414549] at24 2-0056: supply vcc not found, using dummy regulator
693 06:02:01.977268 <4>[ 3.455682] at24 2-0057: supply vcc not found, using dummy regulator
694 06:02:02.022835 <6>[ 3.501931] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 06:02:02.072840 <3>[ 3.548020] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 06:02:02.097590 <6>[ 3.569075] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 06:02:02.118491 <4>[ 3.595644] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 06:02:02.134840 <4>[ 3.611923] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 06:02:02.192785 <6>[ 3.674085] Freeing initrd memory: 14992K
700 06:02:02.201147 <6>[ 3.679736] omap_rng 48310000.rng: Random Number Generator ver. 20
701 06:02:02.225104 <5>[ 3.706550] random: crng init done
702 06:02:02.273914 <6>[ 3.750980] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 06:02:02.327245 <6>[ 3.803445] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 06:02:02.333070 <6>[ 3.813762] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 06:02:02.344811 <6>[ 3.821094] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 06:02:02.350679 <6>[ 3.828571] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 06:02:02.362193 <6>[ 3.836709] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 06:02:02.369685 <6>[ 3.848355] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 06:02:02.382883 <5>[ 3.857460] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 06:02:02.411106 <3>[ 3.887778] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 06:02:02.416892 <6>[ 3.896378] edma 49000000.dma: TI EDMA DMA engine driver
712 06:02:02.489031 <3>[ 3.965053] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 06:02:02.503944 <6>[ 3.979497] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 06:02:02.516983 <3>[ 3.996816] l3-aon-clkctrl:0000:0: failed to disable
715 06:02:02.573375 <6>[ 4.049990] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 06:02:02.579077 <6>[ 4.059503] printk: legacy console [ttyS0] enabled
717 06:02:02.584843 <6>[ 4.059503] printk: legacy console [ttyS0] enabled
718 06:02:02.590424 <6>[ 4.069843] printk: legacy bootconsole [omap8250] disabled
719 06:02:02.596267 <6>[ 4.069843] printk: legacy bootconsole [omap8250] disabled
720 06:02:02.626145 <4>[ 4.101811] tps65217-pmic: Failed to locate of_node [id: -1]
721 06:02:02.629774 <4>[ 4.109204] tps65217-bl: Failed to locate of_node [id: -1]
722 06:02:02.646564 <6>[ 4.129262] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 06:02:02.667010 <6>[ 4.136263] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 06:02:02.678719 <6>[ 4.149963] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 06:02:02.681437 <6>[ 4.161846] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 06:02:02.705306 <6>[ 4.182293] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 06:02:02.711136 <6>[ 4.191461] sdhci-omap 48060000.mmc: Got CD GPIO
728 06:02:02.719220 <4>[ 4.196607] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 06:02:02.733942 <4>[ 4.210129] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 06:02:02.740307 <4>[ 4.218946] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 06:02:02.750195 <4>[ 4.227574] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 06:02:02.799553 <6>[ 4.277614] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 06:02:02.839497 <6>[ 4.316698] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 06:02:02.859893 <6>[ 4.336061] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 06:02:02.866521 <6>[ 4.344955] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 06:02:02.908408 <6>[ 4.381044] mmc0: new high speed SDHC card at address 1234
737 06:02:02.908865 <6>[ 4.389018] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 06:02:02.915625 <6>[ 4.398086] mmcblk0: p1
739 06:02:02.948013 <6>[ 4.422267] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 06:02:02.970189 <6>[ 4.443822] mmc1: new high speed MMC card at address 0001
741 06:02:02.970626 <6>[ 4.450763] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 06:02:02.978928 <6>[ 4.458863] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 06:02:02.987142 <6>[ 4.466738] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 06:02:02.992772 <6>[ 4.474568] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 06:02:05.115456 <6>[ 6.592043] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 06:02:05.188665 <5>[ 6.631118] Sending DHCP requests ., OK
747 06:02:05.200074 <6>[ 6.675513] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 06:02:05.200514 <6>[ 6.683647] IP-Config: Complete:
749 06:02:05.214239 <6>[ 6.687185] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 06:02:05.219954 <6>[ 6.697725] host=192.168.6.12, domain=, nis-domain=(none)
751 06:02:05.223213 <6>[ 6.703941] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 06:02:05.229752 <6>[ 6.703978] nameserver0=10.255.253.1
753 06:02:05.235922 <6>[ 6.716613] clk: Disabling unused clocks
754 06:02:05.241467 <6>[ 6.721400] PM: genpd: Disabling unused power domains
755 06:02:05.259152 <6>[ 6.738193] Freeing unused kernel image (initmem) memory: 2048K
756 06:02:05.266707 <6>[ 6.748077] Run /init as init process
757 06:02:05.290276 Loading, please wait...
758 06:02:05.367700 Starting systemd-udevd version 252.22-1~deb12u1
759 06:02:08.477029 <4>[ 9.952547] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 06:02:08.709720 <4>[ 10.185232] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 06:02:08.896092 <6>[ 10.379118] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 06:02:08.906980 <6>[ 10.384944] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 06:02:09.042353 <6>[ 10.523556] tda998x 0-0070: found TDA19988
764 06:02:09.114442 <6>[ 10.595965] hub 1-0:1.0: USB hub found
765 06:02:09.140272 <6>[ 10.621683] hub 1-0:1.0: 1 port detected
766 06:02:12.203604 Begin: Loading essential drivers ... done.
767 06:02:12.209047 Begin: Running /scripts/init-premount ... done.
768 06:02:12.214598 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 06:02:12.225603 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 06:02:12.230568 Device /sys/class/net/eth0 found
771 06:02:12.230983 done.
772 06:02:12.291139 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 06:02:12.361599 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 06:02:12.385234 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 06:02:12.390795 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 06:02:12.396396 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 06:02:12.407517 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 06:02:12.407955 rootserver: 192.168.6.1 rootpath:
779 06:02:12.411130 filename :
780 06:02:12.532506 done.
781 06:02:12.539056 Begin: Running /scripts/nfs-bottom ... done.
782 06:02:12.607520 Begin: Running /scripts/init-bottom ... done.
783 06:02:14.221299 <30>[ 15.699953] systemd[1]: System time before build time, advancing clock.
784 06:02:14.404076 <30>[ 15.856620] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 06:02:14.412786 <30>[ 15.893426] systemd[1]: Detected architecture arm.
786 06:02:14.425247
787 06:02:14.425689 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 06:02:14.426100
789 06:02:14.452140 <30>[ 15.931444] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 06:02:16.650060 <30>[ 18.128310] systemd[1]: Queued start job for default target graphical.target.
791 06:02:16.667368 <30>[ 18.143484] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 06:02:16.674966 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 06:02:16.699738 <30>[ 18.177352] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 06:02:16.712936 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 06:02:16.738001 <30>[ 18.213444] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 06:02:16.745361 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 06:02:16.766579 <30>[ 18.245271] systemd[1]: Created slice user.slice - User and Session Slice.
798 06:02:16.778649 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 06:02:16.812146 <30>[ 18.282131] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 06:02:16.818177 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 06:02:16.848089 <30>[ 18.323122] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 06:02:16.860949 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 06:02:16.896219 <30>[ 18.362132] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 06:02:16.902716 <30>[ 18.382625] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 06:02:16.911255 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 06:02:16.934468 <30>[ 18.411504] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 06:02:16.942712 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 06:02:16.966237 <30>[ 18.442852] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 06:02:16.978834 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 06:02:17.004737 <30>[ 18.481809] systemd[1]: Reached target paths.target - Path Units.
811 06:02:17.009845 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 06:02:17.034885 <30>[ 18.511720] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 06:02:17.042138 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 06:02:17.064564 <30>[ 18.541581] systemd[1]: Reached target slices.target - Slice Units.
815 06:02:17.070058 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 06:02:17.094901 <30>[ 18.571868] systemd[1]: Reached target swap.target - Swaps.
817 06:02:17.098964 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 06:02:17.125077 <30>[ 18.601863] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 06:02:17.133030 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 06:02:17.155910 <30>[ 18.632566] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 06:02:17.164213 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 06:02:17.244721 <30>[ 18.716589] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 06:02:17.257562 <30>[ 18.734342] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 06:02:17.266043 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 06:02:17.287940 <30>[ 18.763890] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 06:02:17.295451 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 06:02:17.317457 <30>[ 18.794190] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 06:02:17.325666 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 06:02:17.349203 <30>[ 18.825816] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 06:02:17.354928 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 06:02:17.387405 <30>[ 18.862835] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 06:02:17.394007 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 06:02:17.422090 <30>[ 18.892937] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 06:02:17.441002 <30>[ 18.911668] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 06:02:17.485007 <30>[ 18.962607] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 06:02:17.504895 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 06:02:17.566786 <30>[ 19.044229] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 06:02:17.590686 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 06:02:17.677843 <30>[ 19.154368] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 06:02:17.698664 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 06:02:17.765542 <30>[ 19.242608] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 06:02:17.788106 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 06:02:17.846995 <30>[ 19.324512] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 06:02:17.873447 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 06:02:17.924257 <30>[ 19.402252] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 06:02:17.942243 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 06:02:17.995443 <30>[ 19.472260] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 06:02:18.024640 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 06:02:18.076686 <30>[ 19.554537] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 06:02:18.102843 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 06:02:18.157309 <30>[ 19.635146] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 06:02:18.182814 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 06:02:18.213243 <28>[ 19.685060] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 06:02:18.221776 <28>[ 19.698794] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 06:02:18.264980 <30>[ 19.742036] systemd[1]: Starting systemd-journald.service - Journal Service...
856 06:02:18.271430 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 06:02:18.311222 <30>[ 19.788858] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 06:02:18.335329 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 06:02:18.386462 <30>[ 19.864360] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 06:02:18.437231 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 06:02:18.518137 <30>[ 19.994381] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 06:02:18.564825 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 06:02:18.639838 <30>[ 20.116890] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 06:02:18.694584 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 06:02:18.769436 <30>[ 20.247403] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 06:02:18.810310 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 06:02:18.826302 <30>[ 20.304029] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 06:02:18.849936 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 06:02:18.879843 <30>[ 20.356551] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 06:02:18.896902 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 06:02:19.085207 <30>[ 20.563625] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 06:02:19.115626 <30>[ 20.592921] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 06:02:19.144550 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 06:02:19.175357 <30>[ 20.653868] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 06:02:19.205020 <30>[ 20.682825] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 06:02:19.234410 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 06:02:19.255574 <30>[ 20.732724] systemd[1]: Started systemd-journald.service - Journal Service.
878 06:02:19.262417 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 06:02:19.280231 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 06:02:19.306858 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 06:02:19.329311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 06:02:19.368186 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 06:02:19.397360 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 06:02:19.426857 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 06:02:19.447055 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 06:02:19.474653 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 06:02:19.524754 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 06:02:19.574362 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 06:02:19.638686 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 06:02:19.739426 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 06:02:19.840462 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 06:02:19.951749 <46>[ 21.429579] systemd-journald[163]: Received client request to flush runtime journal.
893 06:02:19.972345 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
894 06:02:20.060038 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 06:02:20.936586 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 06:02:21.318652 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 06:02:21.386806 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 06:02:21.729267 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 06:02:21.966718 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 06:02:21.986632 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 06:02:22.004218 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 06:02:22.076932 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 06:02:22.123546 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 06:02:23.066131 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 06:02:23.132775 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 06:02:23.412558 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 06:02:23.485992 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 06:02:23.537599 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 06:02:25.509561 <5>[ 26.987898] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 06:02:25.543744 [[0m[0;31m* [0m] (1 of 5) Job systemd-update-utmp.service/start running (8s / no limit)
911 06:02:25.756236 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 06:02:26.404603 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
913 06:02:27.194203 <5>[ 28.674539] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 06:02:27.262661 <5>[ 28.739504] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
915 06:02:27.268401 <4>[ 28.748480] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
916 06:02:27.276305 <6>[ 28.757594] cfg80211: failed to load regulatory.db
917 06:02:27.392066 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
918 06:02:28.516536 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
919 06:02:28.557540 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
920 06:02:28.795708 <46>[ 30.264967] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 06:02:28.834776 <46>[ 30.306228] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
922 06:02:37.697350 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
923 06:02:37.728512 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
924 06:02:37.755958 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
925 06:02:37.776099 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
926 06:02:37.848671 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
927 06:02:37.892621 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
928 06:02:37.946095 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
929 06:02:38.033627 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
930 06:02:38.078729 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
931 06:02:38.114084 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
932 06:02:38.139899 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
933 06:02:38.170735 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
934 06:02:38.210889 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
935 06:02:38.243610 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
936 06:02:38.278664 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
937 06:02:38.308665 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
938 06:02:38.343224 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
939 06:02:38.369433 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
940 06:02:38.399098 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
941 06:02:38.424340 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
942 06:02:38.455266 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
943 06:02:38.474027 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
944 06:02:38.496921 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
945 06:02:38.574164 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
946 06:02:38.616368 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
947 06:02:38.733475 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
948 06:02:38.809546 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
949 06:02:38.878352 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
950 06:02:38.909533 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
951 06:02:38.924054 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
952 06:02:39.120699 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
953 06:02:39.195039 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
954 06:02:39.228237 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
955 06:02:39.261454 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
956 06:02:39.290246 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
957 06:02:39.545825 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
958 06:02:39.956996 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
959 06:02:40.011068 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
960 06:02:40.038294 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
961 06:02:40.128542 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
962 06:02:40.323294 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
963 06:02:40.478453
964 06:02:40.481913 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
965 06:02:40.482424
966 06:02:40.812919 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sat Nov 2 04:46:02 UTC 2024 armv7l
967 06:02:40.813521
968 06:02:40.818574 The programs included with the Debian GNU/Linux system are free software;
969 06:02:40.822017 the exact distribution terms for each program are described in the
970 06:02:40.827632 individual files in /usr/share/doc/*/copyright.
971 06:02:40.828171
972 06:02:40.833296 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
973 06:02:40.837764 permitted by applicable law.
974 06:02:45.556448 Unable to match end of the kernel message
976 06:02:45.558129 Setting prompt string to ['/ #']
977 06:02:45.558747 end: 2.4.4.1 login-action (duration 00:00:47) [common]
979 06:02:45.560298 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
980 06:02:45.560908 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
981 06:02:45.561430 Setting prompt string to ['/ #']
982 06:02:45.561908 Forcing a shell prompt, looking for ['/ #']
984 06:02:45.612961 / #
985 06:02:45.613631 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
986 06:02:45.614191 Waiting using forced prompt support (timeout 00:02:30)
987 06:02:45.618544
988 06:02:45.625033 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
989 06:02:45.625673 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
990 06:02:45.626170 Sending with 10 millisecond of delay
992 06:02:50.613944 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69'
993 06:02:50.624947 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/927182/extract-nfsrootfs-vwcueg69'
994 06:02:50.626885 Sending with 10 millisecond of delay
996 06:02:52.724859 / # export NFS_SERVER_IP='192.168.6.2'
997 06:02:52.735845 export NFS_SERVER_IP='192.168.6.2'
998 06:02:52.737680 end: 2.4.6 export-device-env (duration 00:00:07) [common]
999 06:02:52.738347 end: 2.4 uboot-commands (duration 00:01:53) [common]
1000 06:02:52.739005 end: 2 uboot-action (duration 00:01:53) [common]
1001 06:02:52.739613 start: 3 lava-test-retry (timeout 00:06:57) [common]
1002 06:02:52.740273 start: 3.1 lava-test-shell (timeout 00:06:57) [common]
1003 06:02:52.740784 Using namespace: common
1005 06:02:52.842022 / # #
1006 06:02:52.842970 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1007 06:02:52.847664 #
1008 06:02:52.853740 Using /lava-927182
1010 06:02:52.955003 / # export SHELL=/bin/bash
1011 06:02:52.959665 export SHELL=/bin/bash
1013 06:02:53.069453 / # . /lava-927182/environment
1014 06:02:53.075160 . /lava-927182/environment
1016 06:02:53.191102 / # /lava-927182/bin/lava-test-runner /lava-927182/0
1017 06:02:53.191817 Test shell timeout: 10s (minimum of the action and connection timeout)
1018 06:02:53.196538 /lava-927182/bin/lava-test-runner /lava-927182/0
1019 06:02:53.585535 + export TESTRUN_ID=0_timesync-off
1020 06:02:53.593338 + TESTRUN_ID=0_timesync-off
1021 06:02:53.593861 + cd /lava-927182/0/tests/0_timesync-off
1022 06:02:53.594337 ++ cat uuid
1023 06:02:53.610357 + UUID=927182_1.6.2.4.1
1024 06:02:53.610863 + set +x
1025 06:02:53.618857 <LAVA_SIGNAL_STARTRUN 0_timesync-off 927182_1.6.2.4.1>
1026 06:02:53.619354 + systemctl stop systemd-timesyncd
1027 06:02:53.620134 Received signal: <STARTRUN> 0_timesync-off 927182_1.6.2.4.1
1028 06:02:53.620613 Starting test lava.0_timesync-off (927182_1.6.2.4.1)
1029 06:02:53.621182 Skipping test definition patterns.
1030 06:02:53.897229 + set +x
1031 06:02:53.897659 <LAVA_SIGNAL_ENDRUN 0_timesync-off 927182_1.6.2.4.1>
1032 06:02:53.898118 Received signal: <ENDRUN> 0_timesync-off 927182_1.6.2.4.1
1033 06:02:53.898408 Ending use of test pattern.
1034 06:02:53.898635 Ending test lava.0_timesync-off (927182_1.6.2.4.1), duration 0.28
1036 06:02:54.081238 + export TESTRUN_ID=1_kselftest-dt
1037 06:02:54.088852 + TESTRUN_ID=1_kselftest-dt
1038 06:02:54.089495 + cd /lava-927182/0/tests/1_kselftest-dt
1039 06:02:54.090090 ++ cat uuid
1040 06:02:54.105583 + UUID=927182_1.6.2.4.5
1041 06:02:54.106124 + set +x
1042 06:02:54.111261 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 927182_1.6.2.4.5>
1043 06:02:54.111893 + cd ./automated/linux/kselftest/
1044 06:02:54.112866 Received signal: <STARTRUN> 1_kselftest-dt 927182_1.6.2.4.5
1045 06:02:54.113449 Starting test lava.1_kselftest-dt (927182_1.6.2.4.5)
1046 06:02:54.114117 Skipping test definition patterns.
1047 06:02:54.139457 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1048 06:02:54.255274 INFO: install_deps skipped
1049 06:02:54.919768 --2024-11-02 06:02:54-- http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1050 06:02:55.192862 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1051 06:02:55.338344 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1052 06:02:55.482280 HTTP request sent, awaiting response... 200 OK
1053 06:02:55.482760 Length: 2729964 (2.6M) [application/octet-stream]
1054 06:02:55.488052 Saving to: 'kselftest_armhf.tar.gz'
1055 06:02:55.488515
1056 06:02:56.860869
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 47.54K 167KB/s
kselftest_armhf.tar 8%[> ] 218.67K 382KB/s
kselftest_armhf.tar 33%[=====> ] 889.89K 1.02MB/s
kselftest_armhf.tar 44%[=======> ] 1.16M 1.08MB/s
kselftest_armhf.tar 83%[===============> ] 2.16M 1.69MB/s
kselftest_armhf.tar 100%[===================>] 2.60M 1.90MB/s in 1.4s
1057 06:02:56.861520
1058 06:02:57.399016 2024-11-02 06:02:56 (1.90 MB/s) - 'kselftest_armhf.tar.gz' saved [2729964/2729964]
1059 06:02:57.399630
1060 06:03:08.827169 skiplist:
1061 06:03:08.827806 ========================================
1062 06:03:08.832625 ========================================
1063 06:03:08.932132 dt:test_unprobed_devices.sh
1064 06:03:08.980450 ============== Tests to run ===============
1065 06:03:08.990369 dt:test_unprobed_devices.sh
1066 06:03:08.994360 ===========End Tests to run ===============
1067 06:03:09.002352 shardfile-dt pass
1068 06:03:09.227771 <12>[ 70.711688] kselftest: Running tests in dt
1069 06:03:09.256784 TAP version 13
1070 06:03:09.280676 1..1
1071 06:03:09.336700 # timeout set to 45
1072 06:03:09.337227 # selftests: dt: test_unprobed_devices.sh
1073 06:03:10.276854 # TAP version 13
1074 06:03:35.742472 # 1..257
1075 06:03:35.944492 # ok 1 / # SKIP
1076 06:03:35.967688 # ok 2 /clk_mcasp0
1077 06:03:36.043505 # ok 3 /clk_mcasp0_fixed # SKIP
1078 06:03:36.116166 # ok 4 /cpus/cpu@0 # SKIP
1079 06:03:36.209336 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1080 06:03:36.230003 # ok 6 /fixedregulator0
1081 06:03:36.245365 # ok 7 /leds
1082 06:03:36.272102 # ok 8 /ocp
1083 06:03:36.295623 # ok 9 /ocp/interconnect@44c00000
1084 06:03:36.315112 # ok 10 /ocp/interconnect@44c00000/segment@0
1085 06:03:36.338046 # ok 11 /ocp/interconnect@44c00000/segment@100000
1086 06:03:36.367142 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1087 06:03:36.437309 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1088 06:03:36.458252 # ok 14 /ocp/interconnect@44c00000/segment@200000
1089 06:03:36.487097 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1090 06:03:36.590324 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1091 06:03:36.664490 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1092 06:03:36.738562 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1093 06:03:36.813080 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1094 06:03:36.886187 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1095 06:03:36.959207 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1096 06:03:37.032889 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1097 06:03:37.105804 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1098 06:03:37.179135 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1099 06:03:37.252596 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1100 06:03:37.325045 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1101 06:03:37.399160 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1102 06:03:37.472692 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1103 06:03:37.545360 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1104 06:03:37.618242 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1105 06:03:37.692251 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1106 06:03:37.764741 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1107 06:03:37.838714 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1108 06:03:37.911620 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1109 06:03:37.989757 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1110 06:03:38.059127 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1111 06:03:38.132300 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1112 06:03:38.205993 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1113 06:03:38.279313 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1114 06:03:38.352615 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1115 06:03:38.425928 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1116 06:03:38.499972 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1117 06:03:38.573448 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1118 06:03:38.646624 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1119 06:03:38.720376 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1120 06:03:38.798492 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1121 06:03:38.870779 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1122 06:03:38.946381 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1123 06:03:39.016531 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1124 06:03:39.090090 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1125 06:03:39.167679 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1126 06:03:39.240579 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1127 06:03:39.310234 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1128 06:03:39.384681 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1129 06:03:39.460563 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1130 06:03:39.536475 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1131 06:03:39.605494 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1132 06:03:39.678512 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1133 06:03:39.756383 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1134 06:03:39.830264 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1135 06:03:39.902500 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1136 06:03:39.975781 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1137 06:03:40.050018 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1138 06:03:40.123232 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1139 06:03:40.196248 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1140 06:03:40.274992 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1141 06:03:40.349594 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1142 06:03:40.420109 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1143 06:03:40.496146 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1144 06:03:40.570342 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1145 06:03:40.643136 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1146 06:03:40.717795 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1147 06:03:40.797061 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1148 06:03:40.870311 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1149 06:03:40.945689 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1150 06:03:41.015324 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1151 06:03:41.089499 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1152 06:03:41.164055 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1153 06:03:41.237244 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1154 06:03:41.311379 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1155 06:03:41.385629 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1156 06:03:41.461212 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1157 06:03:41.563640 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1158 06:03:41.647617 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1159 06:03:41.721714 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1160 06:03:41.795635 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1161 06:03:41.872905 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1162 06:03:41.943715 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1163 06:03:42.019798 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1164 06:03:42.095194 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1165 06:03:42.166741 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1166 06:03:42.243144 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1167 06:03:42.317207 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1168 06:03:42.392437 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1169 06:03:42.413700 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1170 06:03:42.441901 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1171 06:03:42.467294 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1172 06:03:42.487870 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1173 06:03:42.516271 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1174 06:03:42.537979 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1175 06:03:42.565569 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1176 06:03:42.586877 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1177 06:03:42.693256 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1178 06:03:42.720897 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1179 06:03:42.742945 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1180 06:03:42.767756 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1181 06:03:42.876366 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1182 06:03:42.957851 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1183 06:03:43.031109 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1184 06:03:43.102367 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1185 06:03:43.177113 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1186 06:03:43.254015 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1187 06:03:43.326064 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1188 06:03:43.399545 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1189 06:03:43.474500 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1190 06:03:43.549315 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1191 06:03:43.624183 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1192 06:03:43.697781 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1193 06:03:43.773916 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1194 06:03:43.847803 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1195 06:03:43.922013 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1196 06:03:43.995952 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1197 06:03:44.017523 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1198 06:03:44.090219 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1199 06:03:44.161266 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1200 06:03:44.238356 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1201 06:03:44.258858 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1202 06:03:44.332029 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1203 06:03:44.354908 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1204 06:03:44.432157 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1205 06:03:44.455779 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1206 06:03:44.477377 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1207 06:03:44.504385 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1208 06:03:44.527466 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1209 06:03:44.552935 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1210 06:03:44.577293 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1211 06:03:44.604249 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1212 06:03:44.679844 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1213 06:03:44.698316 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1214 06:03:44.726208 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1215 06:03:44.799073 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1216 06:03:44.870683 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1217 06:03:44.890162 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1218 06:03:44.997401 # not ok 144 /ocp/interconnect@47c00000
1219 06:03:45.072425 # not ok 145 /ocp/interconnect@47c00000/segment@0
1220 06:03:45.093971 # ok 146 /ocp/interconnect@48000000
1221 06:03:45.118595 # ok 147 /ocp/interconnect@48000000/segment@0
1222 06:03:45.140495 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1223 06:03:45.166751 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1224 06:03:45.188342 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1225 06:03:45.212209 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1226 06:03:45.235898 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1227 06:03:45.265209 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1228 06:03:45.286405 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1229 06:03:45.359009 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1230 06:03:45.433594 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1231 06:03:45.456137 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1232 06:03:45.480869 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1233 06:03:45.506468 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1234 06:03:45.528874 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1235 06:03:45.551898 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1236 06:03:45.581422 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1237 06:03:45.600603 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1238 06:03:45.625147 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1239 06:03:45.648605 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1240 06:03:45.679877 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1241 06:03:45.703185 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1242 06:03:45.726904 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1243 06:03:45.749407 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1244 06:03:45.775759 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1245 06:03:45.796535 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1246 06:03:45.824599 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1247 06:03:45.846575 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1248 06:03:45.873686 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1249 06:03:45.895225 # ok 175 /ocp/interconnect@48000000/segment@100000
1250 06:03:45.921155 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1251 06:03:45.946362 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1252 06:03:46.019300 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1253 06:03:46.093360 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1254 06:03:46.164390 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1255 06:03:46.495147 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1256 06:03:46.496229 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1257 06:03:46.496698 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1258 06:03:46.498884 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1259 06:03:46.533262 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1260 06:03:46.553193 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1261 06:03:46.581770 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1262 06:03:46.605628 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1263 06:03:46.626810 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1264 06:03:46.649653 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1265 06:03:46.674940 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1266 06:03:46.702002 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1267 06:03:46.726969 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1268 06:03:46.746765 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1269 06:03:46.774439 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1270 06:03:46.796751 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1271 06:03:46.824946 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1272 06:03:46.841893 # ok 198 /ocp/interconnect@48000000/segment@200000
1273 06:03:46.867402 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1274 06:03:46.943013 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1275 06:03:46.963835 # ok 201 /ocp/interconnect@48000000/segment@300000
1276 06:03:46.989212 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1277 06:03:47.016720 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1278 06:03:47.039158 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1279 06:03:47.062681 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1280 06:03:47.088921 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1281 06:03:47.109732 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1282 06:03:47.184842 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1283 06:03:47.207637 # ok 209 /ocp/interconnect@4a000000
1284 06:03:47.232291 # ok 210 /ocp/interconnect@4a000000/segment@0
1285 06:03:47.256567 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1286 06:03:47.279163 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1287 06:03:47.304345 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1288 06:03:47.332390 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1289 06:03:47.400954 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1290 06:03:47.515002 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1291 06:03:47.588519 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1292 06:03:47.690856 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1293 06:03:47.768394 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1294 06:03:47.845591 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1295 06:03:47.941295 # not ok 221 /ocp/interconnect@4b140000
1296 06:03:48.019839 # not ok 222 /ocp/interconnect@4b140000/segment@0
1297 06:03:48.092457 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1298 06:03:48.113748 # ok 224 /ocp/target-module@40300000
1299 06:03:48.138172 # ok 225 /ocp/target-module@40300000/sram@0
1300 06:03:48.214691 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1301 06:03:48.286781 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1302 06:03:48.309565 # ok 228 /ocp/target-module@47400000
1303 06:03:48.334969 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1304 06:03:48.353270 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1305 06:03:48.380985 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1306 06:03:48.399284 # ok 232 /ocp/target-module@47400000/usb@1400
1307 06:03:48.424608 # ok 233 /ocp/target-module@47400000/usb@1800
1308 06:03:48.445123 # ok 234 /ocp/target-module@47810000
1309 06:03:48.471645 # ok 235 /ocp/target-module@49000000
1310 06:03:48.494431 # ok 236 /ocp/target-module@49000000/dma@0
1311 06:03:48.519359 # ok 237 /ocp/target-module@49800000
1312 06:03:48.537197 # ok 238 /ocp/target-module@49800000/dma@0
1313 06:03:48.560178 # ok 239 /ocp/target-module@49900000
1314 06:03:48.583875 # ok 240 /ocp/target-module@49900000/dma@0
1315 06:03:48.610639 # ok 241 /ocp/target-module@49a00000
1316 06:03:48.634327 # ok 242 /ocp/target-module@49a00000/dma@0
1317 06:03:48.656241 # ok 243 /ocp/target-module@4c000000
1318 06:03:48.728653 # not ok 244 /ocp/target-module@4c000000/emif@0
1319 06:03:48.753773 # ok 245 /ocp/target-module@50000000
1320 06:03:48.773549 # ok 246 /ocp/target-module@53100000
1321 06:03:48.851658 # not ok 247 /ocp/target-module@53100000/sham@0
1322 06:03:48.873118 # ok 248 /ocp/target-module@53500000
1323 06:03:48.942276 # not ok 249 /ocp/target-module@53500000/aes@0
1324 06:03:48.964490 # ok 250 /ocp/target-module@56000000
1325 06:03:49.074970 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1326 06:03:49.148666 # ok 252 /opp-table # SKIP
1327 06:03:49.216144 # ok 253 /soc # SKIP
1328 06:03:49.242005 # ok 254 /sound
1329 06:03:49.261819 # ok 255 /target-module@4b000000
1330 06:03:49.287965 # ok 256 /target-module@4b000000/target-module@140000
1331 06:03:49.309025 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1332 06:03:49.319194 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1333 06:03:49.327046 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1334 06:03:51.593551 dt_test_unprobed_devices_sh_ skip
1335 06:03:51.599020 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1336 06:03:51.604560 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1337 06:03:51.605115 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1338 06:03:51.610132 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1339 06:03:51.615717 dt_test_unprobed_devices_sh_fixedregulator0 pass
1340 06:03:51.621321 dt_test_unprobed_devices_sh_leds pass
1341 06:03:51.621796 dt_test_unprobed_devices_sh_ocp pass
1342 06:03:51.626918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1343 06:03:51.632679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1344 06:03:51.638353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1345 06:03:51.649434 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1346 06:03:51.654918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1347 06:03:51.660502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1348 06:03:51.671713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1349 06:03:51.677343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1350 06:03:51.688672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1351 06:03:51.699831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1352 06:03:51.711063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1353 06:03:51.716706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1354 06:03:51.727858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1355 06:03:51.739172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1356 06:03:51.750300 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1357 06:03:51.761480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1358 06:03:51.767093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1359 06:03:51.778267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1360 06:03:51.789449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1361 06:03:51.800730 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1362 06:03:51.811827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1363 06:03:51.817451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1364 06:03:51.828712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1365 06:03:51.839915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1366 06:03:51.851050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1367 06:03:51.856642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1368 06:03:51.867820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1369 06:03:51.878983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1370 06:03:51.890253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1371 06:03:51.901537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1372 06:03:51.907007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1373 06:03:51.918158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1374 06:03:51.929529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1375 06:03:51.940610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1376 06:03:51.951816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1377 06:03:51.962963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1378 06:03:51.974121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1379 06:03:51.985317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1380 06:03:51.996496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1381 06:03:52.007764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1382 06:03:52.018907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1383 06:03:52.030146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1384 06:03:52.041380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1385 06:03:52.052515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1386 06:03:52.063754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1387 06:03:52.074864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1388 06:03:52.086067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1389 06:03:52.097288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1390 06:03:52.108463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1391 06:03:52.119663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1392 06:03:52.130951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1393 06:03:52.142213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1394 06:03:52.153405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1395 06:03:52.164527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1396 06:03:52.175604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1397 06:03:52.186764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1398 06:03:52.192371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1399 06:03:52.203689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1400 06:03:52.214832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1401 06:03:52.225969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1402 06:03:52.237167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1403 06:03:52.248360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1404 06:03:52.259583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1405 06:03:52.270936 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1406 06:03:52.281928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1407 06:03:52.293234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1408 06:03:52.304327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1409 06:03:52.316195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1410 06:03:52.326739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1411 06:03:52.337953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1412 06:03:52.349117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1413 06:03:52.360343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1414 06:03:52.371549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1415 06:03:52.382764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1416 06:03:52.388462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1417 06:03:52.399973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1418 06:03:52.410848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1419 06:03:52.422011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1420 06:03:52.433265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1421 06:03:52.438929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1422 06:03:52.455701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1423 06:03:52.466923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1424 06:03:52.472575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1425 06:03:52.489313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1426 06:03:52.500569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1427 06:03:52.511913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1428 06:03:52.517350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1429 06:03:52.528526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1430 06:03:52.539654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1431 06:03:52.545366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1432 06:03:52.556474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1433 06:03:52.567634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1434 06:03:52.573330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1435 06:03:52.584406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1436 06:03:52.590101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1437 06:03:52.601288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1438 06:03:52.612556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1439 06:03:52.623664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1440 06:03:52.635279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1441 06:03:52.646119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1442 06:03:52.657201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1443 06:03:52.668384 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1444 06:03:52.679746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1445 06:03:52.690814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1446 06:03:52.702043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1447 06:03:52.713515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1448 06:03:52.724879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1449 06:03:52.741597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1450 06:03:52.752631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1451 06:03:52.763737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1452 06:03:52.774977 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1453 06:03:52.786705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1454 06:03:52.802997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1455 06:03:52.814661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1456 06:03:52.825324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1457 06:03:52.836527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1458 06:03:52.842117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1459 06:03:52.853353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1460 06:03:52.864466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1461 06:03:52.870010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1462 06:03:52.881179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1463 06:03:52.886835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1464 06:03:52.898205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1465 06:03:52.903628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1466 06:03:52.914941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1467 06:03:52.920471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1468 06:03:52.931655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1469 06:03:52.937246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1470 06:03:52.948508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1471 06:03:52.959766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1472 06:03:52.970868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1473 06:03:52.982021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1474 06:03:52.993184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1475 06:03:52.998759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1476 06:03:53.009926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1477 06:03:53.015527 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1478 06:03:53.021123 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1479 06:03:53.026712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1480 06:03:53.032329 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1481 06:03:53.037894 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1482 06:03:53.049049 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1483 06:03:53.054784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1484 06:03:53.060388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1485 06:03:53.071558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1486 06:03:53.077223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1487 06:03:53.088363 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1488 06:03:53.094036 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1489 06:03:53.105173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1490 06:03:53.110812 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1491 06:03:53.121957 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1492 06:03:53.127590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1493 06:03:53.138741 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1494 06:03:53.144389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1495 06:03:53.155499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1496 06:03:53.161150 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1497 06:03:53.172328 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1498 06:03:53.178043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1499 06:03:53.183537 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1500 06:03:53.194697 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1501 06:03:53.200331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1502 06:03:53.211486 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1503 06:03:53.217109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1504 06:03:53.228269 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1505 06:03:53.233886 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1506 06:03:53.245085 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1507 06:03:53.250704 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1508 06:03:53.256339 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1509 06:03:53.267443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1510 06:03:53.273087 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1511 06:03:53.284260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1512 06:03:53.295443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1513 06:03:53.306612 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1514 06:03:53.317810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1515 06:03:53.329010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1516 06:03:53.340229 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1517 06:03:53.351400 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1518 06:03:53.362588 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1519 06:03:53.368271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1520 06:03:53.379372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1521 06:03:53.385021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1522 06:03:53.396199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1523 06:03:53.401802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1524 06:03:53.413007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1525 06:03:53.418589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1526 06:03:53.429740 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1527 06:03:53.435370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1528 06:03:53.446485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1529 06:03:53.452172 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1530 06:03:53.463273 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1531 06:03:53.468948 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1532 06:03:53.480082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1533 06:03:53.485706 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1534 06:03:53.491320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1535 06:03:53.502474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1536 06:03:53.508127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1537 06:03:53.519243 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1538 06:03:53.524884 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1539 06:03:53.536067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1540 06:03:53.541680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1541 06:03:53.552822 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1542 06:03:53.558455 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1543 06:03:53.564081 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1544 06:03:53.569664 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1545 06:03:53.580828 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1546 06:03:53.592036 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1547 06:03:53.597657 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1548 06:03:53.603240 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1549 06:03:53.614390 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1550 06:03:53.625576 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1551 06:03:53.636823 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1552 06:03:53.648040 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1553 06:03:53.653649 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1554 06:03:53.659252 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1555 06:03:53.664858 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1556 06:03:53.670467 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1557 06:03:53.676158 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1558 06:03:53.681695 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1559 06:03:53.692861 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1560 06:03:53.698488 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1561 06:03:53.704198 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1562 06:03:53.709701 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1563 06:03:53.715302 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1564 06:03:53.726481 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1565 06:03:53.732122 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1566 06:03:53.737826 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1567 06:03:53.743447 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1568 06:03:53.748967 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1569 06:03:53.754624 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1570 06:03:53.760140 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1571 06:03:53.765681 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1572 06:03:53.771335 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1573 06:03:53.776937 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1574 06:03:53.782571 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1575 06:03:53.788109 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1576 06:03:53.793757 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1577 06:03:53.799361 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1578 06:03:53.804947 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1579 06:03:53.810475 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1580 06:03:53.816104 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1581 06:03:53.821701 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1582 06:03:53.827309 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1583 06:03:53.832938 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1584 06:03:53.838510 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1585 06:03:53.839020 dt_test_unprobed_devices_sh_opp-table skip
1586 06:03:53.844172 dt_test_unprobed_devices_sh_soc skip
1587 06:03:53.849723 dt_test_unprobed_devices_sh_sound pass
1588 06:03:53.855341 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1589 06:03:53.860964 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1590 06:03:53.866563 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1591 06:03:53.872161 dt_test_unprobed_devices_sh fail
1592 06:03:53.872671 + ../../utils/send-to-lava.sh ./output/result.txt
1593 06:03:53.880067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1594 06:03:53.881064 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1596 06:03:53.933497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1597 06:03:53.934294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1599 06:03:54.022543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1600 06:03:54.023369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1602 06:03:54.116887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1603 06:03:54.117732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1605 06:03:54.210360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1606 06:03:54.211224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1608 06:03:54.305810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1609 06:03:54.306723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1611 06:03:54.393859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1612 06:03:54.394758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1614 06:03:54.482026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1615 06:03:54.482932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1617 06:03:54.575565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1618 06:03:54.576478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1620 06:03:54.666300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1621 06:03:54.667218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1623 06:03:54.755508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1624 06:03:54.756444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1626 06:03:54.849819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1627 06:03:54.850698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1629 06:03:54.939532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1630 06:03:54.940428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1632 06:03:55.028549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1633 06:03:55.029413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1635 06:03:55.120300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1636 06:03:55.121143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1638 06:03:55.215936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1639 06:03:55.216820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1641 06:03:55.304234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1642 06:03:55.305056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1644 06:03:55.392354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1645 06:03:55.393179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1647 06:03:55.487349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1648 06:03:55.488169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1650 06:03:55.575236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1651 06:03:55.576085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1653 06:03:55.665383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1654 06:03:55.666211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1656 06:03:55.760182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1657 06:03:55.761017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1659 06:03:55.856204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1660 06:03:55.857025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1662 06:03:55.944411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1663 06:03:55.945245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1665 06:03:56.032572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1666 06:03:56.033405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1668 06:03:56.126453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1669 06:03:56.127250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1671 06:03:56.213992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1672 06:03:56.214796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1674 06:03:56.303351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1675 06:03:56.304195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1677 06:03:56.399907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1678 06:03:56.400825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1680 06:03:56.493647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1681 06:03:56.494542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1683 06:03:56.587248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1684 06:03:56.588079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1686 06:03:56.682457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1687 06:03:56.683302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1689 06:03:56.775076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1690 06:03:56.775967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1692 06:03:56.867108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1693 06:03:56.868026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1695 06:03:56.959413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1696 06:03:56.960508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1698 06:03:57.057215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1699 06:03:57.058103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1701 06:03:57.144729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1702 06:03:57.145586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1704 06:03:57.239567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1705 06:03:57.240472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1707 06:03:57.328568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1708 06:03:57.329390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1710 06:03:57.423064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1711 06:03:57.423901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1713 06:03:57.517580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1714 06:03:57.518452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1716 06:03:57.611801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1717 06:03:57.612720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1719 06:03:57.701725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1720 06:03:57.702612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1722 06:03:57.797011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1723 06:03:57.797944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1725 06:03:57.890879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1726 06:03:57.891768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1728 06:03:57.986683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1729 06:03:57.987571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1731 06:03:58.076035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1732 06:03:58.076987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1734 06:03:58.170668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1735 06:03:58.171606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1737 06:03:58.259960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1738 06:03:58.260956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1740 06:03:58.372410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1741 06:03:58.373235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1743 06:03:58.469304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1744 06:03:58.470135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1746 06:03:58.562565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1747 06:03:58.563396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1749 06:03:58.651616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1750 06:03:58.652471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1752 06:03:58.741700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1753 06:03:58.742538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1755 06:03:58.838613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1756 06:03:58.839487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1758 06:03:58.932543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1759 06:03:58.933450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1761 06:03:59.027134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1762 06:03:59.028056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1764 06:03:59.115478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1765 06:03:59.116396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1767 06:03:59.306139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1768 06:03:59.307030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1770 06:03:59.425930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1771 06:03:59.426752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1773 06:03:59.522138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1774 06:03:59.523023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1776 06:03:59.609757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1777 06:03:59.610600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1779 06:03:59.698434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1780 06:03:59.699296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1782 06:03:59.820914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1783 06:03:59.821851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1785 06:03:59.914801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1786 06:03:59.915701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1788 06:04:00.008504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1789 06:04:00.009445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1791 06:04:00.099372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1792 06:04:00.100195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1794 06:04:00.189020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1795 06:04:00.189841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1797 06:04:00.282240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1798 06:04:00.283061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1800 06:04:00.371342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1801 06:04:00.372174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1803 06:04:00.467588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1804 06:04:00.468467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1806 06:04:00.556105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1807 06:04:00.556985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1809 06:04:00.652368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1810 06:04:00.653191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1812 06:04:00.741472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1813 06:04:00.742249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1815 06:04:00.831163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1816 06:04:00.831928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1818 06:04:00.926176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1819 06:04:00.926981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1821 06:04:01.022630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1822 06:04:01.023419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1824 06:04:01.118557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1825 06:04:01.119319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1827 06:04:01.212472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1828 06:04:01.213296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1830 06:04:01.302165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1831 06:04:01.302956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1833 06:04:01.390790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1834 06:04:01.391599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1836 06:04:01.486573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1837 06:04:01.487371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1839 06:04:01.579827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1840 06:04:01.580628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1842 06:04:01.676341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1843 06:04:01.677102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1845 06:04:01.769110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1846 06:04:01.769885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1848 06:04:01.864089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1849 06:04:01.864916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1851 06:04:01.954181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1852 06:04:01.954923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1854 06:04:02.048362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1855 06:04:02.049174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1857 06:04:02.136498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1858 06:04:02.137262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1860 06:04:02.226683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1861 06:04:02.227444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1863 06:04:02.321366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1864 06:04:02.322138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1866 06:04:02.408028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1867 06:04:02.408836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1869 06:04:02.503506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1870 06:04:02.504311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1872 06:04:02.597341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1873 06:04:02.598105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1875 06:04:02.692804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1876 06:04:02.693559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1878 06:04:02.778309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1879 06:04:02.779078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1881 06:04:02.867618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1882 06:04:02.868431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1884 06:04:02.961510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1885 06:04:02.962268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1887 06:04:03.050742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1888 06:04:03.051511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1890 06:04:03.140364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1891 06:04:03.141123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1893 06:04:03.235203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1894 06:04:03.235964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1896 06:04:03.329955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1897 06:04:03.330740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1899 06:04:03.434825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1900 06:04:03.435832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1902 06:04:03.533191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1903 06:04:03.534112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1905 06:04:03.628486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1906 06:04:03.629300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1908 06:04:03.718238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1909 06:04:03.719156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1911 06:04:03.812031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1912 06:04:03.812959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1914 06:04:03.900979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1915 06:04:03.901857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1917 06:04:03.992111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1918 06:04:03.992982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1920 06:04:04.087316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1921 06:04:04.088147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1923 06:04:04.181302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1924 06:04:04.182107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1926 06:04:04.276630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1927 06:04:04.277431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1929 06:04:04.370668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1930 06:04:04.371480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1932 06:04:04.464867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1933 06:04:04.465682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1935 06:04:04.554473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1936 06:04:04.555302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1938 06:04:04.644296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1939 06:04:04.645092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1941 06:04:04.739811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1942 06:04:04.740653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1944 06:04:04.833485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1945 06:04:04.834312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1947 06:04:04.922707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1948 06:04:04.923512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1950 06:04:05.011367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1951 06:04:05.012182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1953 06:04:05.106749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1955 06:04:05.109976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1956 06:04:05.201339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1958 06:04:05.204411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1959 06:04:05.290861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1961 06:04:05.293940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1962 06:04:05.386845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1963 06:04:05.387680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1965 06:04:05.479876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1966 06:04:05.480725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1968 06:04:05.573679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1969 06:04:05.574470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1971 06:04:05.667402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1972 06:04:05.668281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1974 06:04:05.761068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1975 06:04:05.761899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1977 06:04:05.850172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1978 06:04:05.851012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1980 06:04:05.938146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1981 06:04:05.938978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1983 06:04:06.032914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1984 06:04:06.033771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1986 06:04:06.120204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1987 06:04:06.121047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1989 06:04:06.209713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1990 06:04:06.210717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1992 06:04:06.303119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1993 06:04:06.303970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1995 06:04:06.396077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1996 06:04:06.396966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1998 06:04:06.485439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1999 06:04:06.486294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2001 06:04:06.574499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2002 06:04:06.575362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2004 06:04:06.664387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2005 06:04:06.665261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2007 06:04:06.761173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2008 06:04:06.762060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2010 06:04:06.855200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2011 06:04:06.856092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2013 06:04:06.949130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2014 06:04:06.949999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2016 06:04:07.039192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2017 06:04:07.040069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2019 06:04:07.133999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2020 06:04:07.134899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2022 06:04:07.226205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2023 06:04:07.227068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2025 06:04:07.311603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2026 06:04:07.312486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2028 06:04:07.406115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2029 06:04:07.406934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2031 06:04:07.493801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2032 06:04:07.494639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2034 06:04:07.584264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2035 06:04:07.585097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2037 06:04:07.679713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2038 06:04:07.680658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2040 06:04:07.768956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2041 06:04:07.769772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2043 06:04:07.858026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2044 06:04:07.858872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2046 06:04:07.952675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2047 06:04:07.953454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2049 06:04:08.042155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2050 06:04:08.042917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2052 06:04:08.137316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2053 06:04:08.138128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2055 06:04:08.226101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2056 06:04:08.226875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2058 06:04:08.319717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2059 06:04:08.320534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2061 06:04:08.417285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2062 06:04:08.418068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2064 06:04:08.511318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2065 06:04:08.512341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2067 06:04:08.648563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2068 06:04:08.649835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2070 06:04:08.748387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2071 06:04:08.749208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2073 06:04:08.838574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2074 06:04:08.839335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2076 06:04:08.931814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2077 06:04:08.932620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2079 06:04:09.027452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2080 06:04:09.028270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2082 06:04:09.121523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2083 06:04:09.122292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2085 06:04:09.210844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2086 06:04:09.211604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2088 06:04:09.299649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2089 06:04:09.300481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2091 06:04:09.394813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2092 06:04:09.395581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2094 06:04:09.483111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2095 06:04:09.483894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2097 06:04:09.578037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2098 06:04:09.578796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2100 06:04:09.665778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2101 06:04:09.666535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2103 06:04:09.760072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2104 06:04:09.760902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2106 06:04:09.848076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2107 06:04:09.848890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2109 06:04:09.938323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2110 06:04:09.939101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2112 06:04:10.032205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2113 06:04:10.033150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2115 06:04:10.127170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2116 06:04:10.128054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2118 06:04:10.219055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2119 06:04:10.219863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2121 06:04:10.309364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2122 06:04:10.310164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2124 06:04:10.398545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2125 06:04:10.399350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2127 06:04:10.496179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2128 06:04:10.496981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2130 06:04:10.590081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2131 06:04:10.590880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2133 06:04:10.683635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2134 06:04:10.684469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2136 06:04:10.773635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2137 06:04:10.774461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2139 06:04:10.860855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2140 06:04:10.861671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2142 06:04:10.957409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2143 06:04:10.958226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2145 06:04:11.048477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2146 06:04:11.049295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2148 06:04:11.142879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2149 06:04:11.143690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2151 06:04:11.227657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2152 06:04:11.228497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2154 06:04:11.315705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2155 06:04:11.316578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2157 06:04:11.404143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2158 06:04:11.404969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2160 06:04:11.492048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2161 06:04:11.492851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2163 06:04:11.580342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2164 06:04:11.581137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2166 06:04:11.675722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2167 06:04:11.676558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2169 06:04:11.768673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2170 06:04:11.769471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2172 06:04:11.858449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2173 06:04:11.859252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2175 06:04:11.947503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2176 06:04:11.948355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2178 06:04:12.044336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2179 06:04:12.045182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2181 06:04:12.137793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2182 06:04:12.138622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2184 06:04:12.227568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2185 06:04:12.228399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2187 06:04:12.320774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2188 06:04:12.321566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2190 06:04:12.416912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2191 06:04:12.417709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2193 06:04:12.512094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2194 06:04:12.512893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2196 06:04:12.599826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2197 06:04:12.600666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2199 06:04:12.694766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2200 06:04:12.695563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2202 06:04:12.783521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2203 06:04:12.784358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2205 06:04:12.871178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2206 06:04:12.872020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2208 06:04:12.958491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2209 06:04:12.959277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2211 06:04:13.046752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2212 06:04:13.047548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2214 06:04:13.140125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2215 06:04:13.140929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2217 06:04:13.229665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2218 06:04:13.230492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2220 06:04:13.315275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2221 06:04:13.316104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2223 06:04:13.412170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2224 06:04:13.412964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2226 06:04:13.508693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2227 06:04:13.509488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2229 06:04:13.605288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2230 06:04:13.606089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2232 06:04:13.694127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2233 06:04:13.694932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2235 06:04:13.783015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2236 06:04:13.783814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2238 06:04:13.877689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2239 06:04:13.878502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2241 06:04:13.984101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2242 06:04:13.984931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2244 06:04:14.081097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2245 06:04:14.081914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2247 06:04:14.170897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2248 06:04:14.171696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2250 06:04:14.259879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2251 06:04:14.260729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2253 06:04:14.355410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2254 06:04:14.356224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2256 06:04:14.440259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2257 06:04:14.441059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2259 06:04:14.535358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2260 06:04:14.536160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2262 06:04:14.623854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2263 06:04:14.624696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2265 06:04:14.716804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2266 06:04:14.717602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2268 06:04:14.806069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2269 06:04:14.806864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2271 06:04:14.898051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2272 06:04:14.898860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2274 06:04:14.989952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2276 06:04:14.992415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2277 06:04:15.078690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2278 06:04:15.079500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2280 06:04:15.175472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2281 06:04:15.176307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2283 06:04:15.263920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2284 06:04:15.264753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2286 06:04:15.351395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2287 06:04:15.352214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2289 06:04:15.439355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2290 06:04:15.440184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2292 06:04:15.533436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2293 06:04:15.534231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2295 06:04:15.622380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2296 06:04:15.623184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2298 06:04:15.711234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2299 06:04:15.712081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2301 06:04:15.806077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2302 06:04:15.806928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2304 06:04:15.893085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2305 06:04:15.893897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2307 06:04:15.982578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2308 06:04:15.983419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2310 06:04:16.074813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2311 06:04:16.075649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2313 06:04:16.164324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2314 06:04:16.165124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2316 06:04:16.252322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2317 06:04:16.253113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2319 06:04:16.345463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2320 06:04:16.346282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2322 06:04:16.432636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2323 06:04:16.433457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2325 06:04:16.520984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2326 06:04:16.521773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2328 06:04:16.610015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2329 06:04:16.610806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2331 06:04:16.702361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2332 06:04:16.703151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2334 06:04:16.797752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2335 06:04:16.798603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2337 06:04:16.890451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2338 06:04:16.891277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2340 06:04:16.984101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2341 06:04:16.984926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2343 06:04:17.072075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2344 06:04:17.072881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2346 06:04:17.161456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2347 06:04:17.162270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2349 06:04:17.254508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2350 06:04:17.255315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2352 06:04:17.341561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2353 06:04:17.342357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2355 06:04:17.430199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2356 06:04:17.430990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2358 06:04:17.525579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2359 06:04:17.526367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2361 06:04:17.616393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2362 06:04:17.617191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2364 06:04:17.706202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2365 06:04:17.706988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2367 06:04:17.799720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2368 06:04:17.800306 + set +x
2369 06:04:17.801027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2371 06:04:17.803455 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 927182_1.6.2.4.5>
2372 06:04:17.804219 Received signal: <ENDRUN> 1_kselftest-dt 927182_1.6.2.4.5
2373 06:04:17.804722 Ending use of test pattern.
2374 06:04:17.805171 Ending test lava.1_kselftest-dt (927182_1.6.2.4.5), duration 83.69
2376 06:04:17.808750 <LAVA_TEST_RUNNER EXIT>
2377 06:04:17.809501 ok: lava_test_shell seems to have completed
2378 06:04:17.823414 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2379 06:04:17.825528 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2380 06:04:17.826162 end: 3 lava-test-retry (duration 00:01:25) [common]
2381 06:04:17.826791 start: 4 finalize (timeout 00:05:32) [common]
2382 06:04:17.827410 start: 4.1 power-off (timeout 00:00:30) [common]
2383 06:04:17.828507 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2384 06:04:17.867670 >> OK - accepted request
2385 06:04:17.869798 Returned 0 in 0 seconds
2386 06:04:17.970756 end: 4.1 power-off (duration 00:00:00) [common]
2388 06:04:17.972834 start: 4.2 read-feedback (timeout 00:05:32) [common]
2389 06:04:17.974063 Listened to connection for namespace 'common' for up to 1s
2390 06:04:17.975019 Listened to connection for namespace 'common' for up to 1s
2391 06:04:18.974804 Finalising connection for namespace 'common'
2392 06:04:18.975538 Disconnecting from shell: Finalise
2393 06:04:18.976161 / #
2394 06:04:19.077220 end: 4.2 read-feedback (duration 00:00:01) [common]
2395 06:04:19.077985 end: 4 finalize (duration 00:00:01) [common]
2396 06:04:19.078722 Cleaning after the job
2397 06:04:19.079395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/ramdisk
2398 06:04:19.089753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/kernel
2399 06:04:19.098450 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/dtb
2400 06:04:19.099820 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/nfsrootfs
2401 06:04:19.251360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927182/tftp-deploy-dbbtyzeq/modules
2402 06:04:19.260981 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927182
2403 06:04:22.249039 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927182
2404 06:04:22.249584 Job finished correctly