Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:57:48.280879 lava-dispatcher, installed at version: 2024.01
2 04:57:48.281713 start: 0 validate
3 04:57:48.282195 Start time: 2024-11-02 04:57:48.282165+00:00 (UTC)
4 04:57:48.282765 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:57:48.283304 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:57:48.323343 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:57:48.323913 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 04:57:48.354330 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:57:48.354997 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 04:57:55.431633 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:57:55.432198 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 04:57:56.477225 validate duration: 8.20
14 04:57:56.478267 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:57:56.478676 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:57:56.479055 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:57:56.479779 Not decompressing ramdisk as can be used compressed.
18 04:57:56.480335 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:57:56.480678 saving as /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/ramdisk/rootfs.cpio.gz
20 04:57:56.481020 total size: 8181887 (7 MB)
21 04:57:56.522840 progress 0 % (0 MB)
22 04:57:56.528908 progress 5 % (0 MB)
23 04:57:56.534748 progress 10 % (0 MB)
24 04:57:56.541270 progress 15 % (1 MB)
25 04:57:56.546893 progress 20 % (1 MB)
26 04:57:56.553007 progress 25 % (1 MB)
27 04:57:56.560698 progress 30 % (2 MB)
28 04:57:56.566756 progress 35 % (2 MB)
29 04:57:56.572435 progress 40 % (3 MB)
30 04:57:56.578380 progress 45 % (3 MB)
31 04:57:56.583930 progress 50 % (3 MB)
32 04:57:56.590193 progress 55 % (4 MB)
33 04:57:56.596281 progress 60 % (4 MB)
34 04:57:56.602330 progress 65 % (5 MB)
35 04:57:56.608430 progress 70 % (5 MB)
36 04:57:56.615193 progress 75 % (5 MB)
37 04:57:56.621151 progress 80 % (6 MB)
38 04:57:56.627063 progress 85 % (6 MB)
39 04:57:56.632761 progress 90 % (7 MB)
40 04:57:56.638662 progress 95 % (7 MB)
41 04:57:56.643775 progress 100 % (7 MB)
42 04:57:56.644517 7 MB downloaded in 0.16 s (47.73 MB/s)
43 04:57:56.645116 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:57:56.646022 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:57:56.646318 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:57:56.646592 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:57:56.647087 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 04:57:56.647349 saving as /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/kernel/Image
50 04:57:56.647558 total size: 66443776 (63 MB)
51 04:57:56.647770 No compression specified
52 04:57:56.681706 progress 0 % (0 MB)
53 04:57:56.724188 progress 5 % (3 MB)
54 04:57:56.765841 progress 10 % (6 MB)
55 04:57:56.805911 progress 15 % (9 MB)
56 04:57:56.845416 progress 20 % (12 MB)
57 04:57:56.885174 progress 25 % (15 MB)
58 04:57:56.925112 progress 30 % (19 MB)
59 04:57:56.964660 progress 35 % (22 MB)
60 04:57:57.004613 progress 40 % (25 MB)
61 04:57:57.044034 progress 45 % (28 MB)
62 04:57:57.083543 progress 50 % (31 MB)
63 04:57:57.123215 progress 55 % (34 MB)
64 04:57:57.162627 progress 60 % (38 MB)
65 04:57:57.202599 progress 65 % (41 MB)
66 04:57:57.242125 progress 70 % (44 MB)
67 04:57:57.281578 progress 75 % (47 MB)
68 04:57:57.321511 progress 80 % (50 MB)
69 04:57:57.362028 progress 85 % (53 MB)
70 04:57:57.402744 progress 90 % (57 MB)
71 04:57:57.444547 progress 95 % (60 MB)
72 04:57:57.485164 progress 100 % (63 MB)
73 04:57:57.485933 63 MB downloaded in 0.84 s (75.58 MB/s)
74 04:57:57.486440 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:57:57.487257 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:57:57.487537 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:57:57.487806 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:57:57.488525 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 04:57:57.488874 saving as /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 04:57:57.489110 total size: 53209 (0 MB)
82 04:57:57.489348 No compression specified
83 04:57:57.529450 progress 61 % (0 MB)
84 04:57:57.530362 progress 100 % (0 MB)
85 04:57:57.530959 0 MB downloaded in 0.04 s (1.21 MB/s)
86 04:57:57.531479 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:57:57.532946 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:57:57.533291 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:57:57.533593 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:57:57.534712 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 04:57:57.535057 saving as /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/modules/modules.tar
93 04:57:57.535330 total size: 16116020 (15 MB)
94 04:57:57.535656 Using unxz to decompress xz
95 04:57:57.588180 progress 0 % (0 MB)
96 04:57:57.700885 progress 5 % (0 MB)
97 04:57:57.822596 progress 10 % (1 MB)
98 04:57:57.941327 progress 15 % (2 MB)
99 04:57:58.074865 progress 20 % (3 MB)
100 04:57:58.209048 progress 25 % (3 MB)
101 04:57:58.321658 progress 30 % (4 MB)
102 04:57:58.436824 progress 35 % (5 MB)
103 04:57:58.545981 progress 40 % (6 MB)
104 04:57:58.655158 progress 45 % (6 MB)
105 04:57:58.774613 progress 50 % (7 MB)
106 04:57:58.892291 progress 55 % (8 MB)
107 04:57:59.015856 progress 60 % (9 MB)
108 04:57:59.130133 progress 65 % (10 MB)
109 04:57:59.244771 progress 70 % (10 MB)
110 04:57:59.363857 progress 75 % (11 MB)
111 04:57:59.486452 progress 80 % (12 MB)
112 04:57:59.603839 progress 85 % (13 MB)
113 04:57:59.715502 progress 90 % (13 MB)
114 04:57:59.834090 progress 95 % (14 MB)
115 04:57:59.949188 progress 100 % (15 MB)
116 04:57:59.963729 15 MB downloaded in 2.43 s (6.33 MB/s)
117 04:57:59.964561 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:57:59.966175 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:57:59.966697 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 04:57:59.967214 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 04:57:59.967704 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:57:59.968244 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 04:57:59.969218 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral
125 04:57:59.970055 makedir: /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin
126 04:57:59.970691 makedir: /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/tests
127 04:57:59.971311 makedir: /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/results
128 04:57:59.971915 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-add-keys
129 04:57:59.972900 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-add-sources
130 04:57:59.973826 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-background-process-start
131 04:57:59.974780 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-background-process-stop
132 04:57:59.975760 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-common-functions
133 04:57:59.976762 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-echo-ipv4
134 04:57:59.977688 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-install-packages
135 04:57:59.978579 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-installed-packages
136 04:57:59.979463 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-os-build
137 04:57:59.980398 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-probe-channel
138 04:57:59.981311 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-probe-ip
139 04:57:59.982197 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-target-ip
140 04:57:59.983084 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-target-mac
141 04:57:59.984017 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-target-storage
142 04:57:59.984987 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-case
143 04:57:59.985888 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-event
144 04:57:59.986806 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-feedback
145 04:57:59.987781 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-raise
146 04:57:59.988788 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-reference
147 04:57:59.989707 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-runner
148 04:57:59.990607 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-set
149 04:57:59.991492 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-test-shell
150 04:57:59.992442 Updating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-install-packages (oe)
151 04:57:59.993529 Updating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/bin/lava-installed-packages (oe)
152 04:57:59.994376 Creating /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/environment
153 04:57:59.995094 LAVA metadata
154 04:57:59.995577 - LAVA_JOB_ID=927109
155 04:57:59.996038 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:57:59.996733 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 04:57:59.998564 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:57:59.999171 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 04:57:59.999586 skipped lava-vland-overlay
160 04:58:00.000117 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:58:00.000635 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 04:58:00.001066 skipped lava-multinode-overlay
163 04:58:00.001548 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:58:00.002047 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 04:58:00.002527 Loading test definitions
166 04:58:00.003079 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 04:58:00.003520 Using /lava-927109 at stage 0
168 04:58:00.005065 uuid=927109_1.5.2.4.1 testdef=None
169 04:58:00.005403 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:58:00.005681 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 04:58:00.007556 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:58:00.008424 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 04:58:00.010759 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:58:00.011610 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 04:58:00.013868 runner path: /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/0/tests/0_dmesg test_uuid 927109_1.5.2.4.1
178 04:58:00.014467 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:58:00.015249 Creating lava-test-runner.conf files
181 04:58:00.015455 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927109/lava-overlay-2fapkral/lava-927109/0 for stage 0
182 04:58:00.015802 - 0_dmesg
183 04:58:00.016188 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:58:00.016477 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 04:58:00.040670 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:58:00.041117 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 04:58:00.041383 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:58:00.041654 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:58:00.041921 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 04:58:01.011662 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:58:01.012255 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 04:58:01.012731 extracting modules file /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk
193 04:58:02.578411 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 04:58:02.578934 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 04:58:02.579260 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927109/compress-overlay-5o39od__/overlay-1.5.2.5.tar.gz to ramdisk
196 04:58:02.579521 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927109/compress-overlay-5o39od__/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk
197 04:58:02.616771 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:58:02.617303 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 04:58:02.617677 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 04:58:02.617972 Converting downloaded kernel to a uImage
201 04:58:02.618347 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/kernel/Image /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/kernel/uImage
202 04:58:03.434519 output: Image Name:
203 04:58:03.435033 output: Created: Sat Nov 2 04:58:02 2024
204 04:58:03.435289 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:58:03.435537 output: Data Size: 66443776 Bytes = 64886.50 KiB = 63.37 MiB
206 04:58:03.435782 output: Load Address: 01080000
207 04:58:03.436056 output: Entry Point: 01080000
208 04:58:03.436302 output:
209 04:58:03.436697 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 04:58:03.437024 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 04:58:03.437351 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 04:58:03.437654 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:58:03.437963 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 04:58:03.438275 Building ramdisk /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk
215 04:58:06.966319 >> 254425 blocks
216 04:58:18.062388 Adding RAMdisk u-boot header.
217 04:58:18.062908 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk.cpio.gz.uboot
218 04:58:18.407677 output: Image Name:
219 04:58:18.408127 output: Created: Sat Nov 2 04:58:18 2024
220 04:58:18.408543 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:58:18.408942 output: Data Size: 33576367 Bytes = 32789.42 KiB = 32.02 MiB
222 04:58:18.409338 output: Load Address: 00000000
223 04:58:18.409728 output: Entry Point: 00000000
224 04:58:18.410113 output:
225 04:58:18.410866 rename /var/lib/lava/dispatcher/tmp/927109/extract-overlay-ramdisk-hcyu0g1h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot
226 04:58:18.411535 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 04:58:18.412102 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 04:58:18.412664 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 04:58:18.413111 No LXC device requested
230 04:58:18.413595 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:58:18.414089 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 04:58:18.414571 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:58:18.414974 Checking files for TFTP limit of 4294967296 bytes.
234 04:58:18.417609 end: 1 tftp-deploy (duration 00:00:22) [common]
235 04:58:18.418181 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:58:18.418694 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:58:18.419182 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:58:18.419673 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:58:18.420229 Using kernel file from prepare-kernel: 927109/tftp-deploy-eeow900d/kernel/uImage
240 04:58:18.420825 substitutions:
241 04:58:18.421226 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:58:18.421620 - {DTB_ADDR}: 0x01070000
243 04:58:18.422009 - {DTB}: 927109/tftp-deploy-eeow900d/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 04:58:18.422403 - {INITRD}: 927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot
245 04:58:18.422791 - {KERNEL_ADDR}: 0x01080000
246 04:58:18.423178 - {KERNEL}: 927109/tftp-deploy-eeow900d/kernel/uImage
247 04:58:18.423566 - {LAVA_MAC}: None
248 04:58:18.424022 - {PRESEED_CONFIG}: None
249 04:58:18.424421 - {PRESEED_LOCAL}: None
250 04:58:18.424810 - {RAMDISK_ADDR}: 0x08000000
251 04:58:18.425194 - {RAMDISK}: 927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot
252 04:58:18.425581 - {ROOT_PART}: None
253 04:58:18.425966 - {ROOT}: None
254 04:58:18.426348 - {SERVER_IP}: 192.168.6.2
255 04:58:18.426736 - {TEE_ADDR}: 0x83000000
256 04:58:18.427120 - {TEE}: None
257 04:58:18.427501 Parsed boot commands:
258 04:58:18.427870 - setenv autoload no
259 04:58:18.428282 - setenv initrd_high 0xffffffff
260 04:58:18.428666 - setenv fdt_high 0xffffffff
261 04:58:18.429048 - dhcp
262 04:58:18.429429 - setenv serverip 192.168.6.2
263 04:58:18.429811 - tftpboot 0x01080000 927109/tftp-deploy-eeow900d/kernel/uImage
264 04:58:18.430195 - tftpboot 0x08000000 927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot
265 04:58:18.430578 - tftpboot 0x01070000 927109/tftp-deploy-eeow900d/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 04:58:18.430962 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:58:18.431352 - bootm 0x01080000 0x08000000 0x01070000
268 04:58:18.431842 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:58:18.433334 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:58:18.433771 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 04:58:18.447531 Setting prompt string to ['lava-test: # ']
273 04:58:18.449078 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:58:18.449663 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:58:18.450204 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:58:18.450726 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:58:18.451831 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 04:58:18.484719 >> OK - accepted request
279 04:58:18.486785 Returned 0 in 0 seconds
280 04:58:18.587884 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:58:18.589514 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:58:18.590060 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:58:18.590569 Setting prompt string to ['Hit any key to stop autoboot']
285 04:58:18.591022 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:58:18.592610 Trying 192.168.56.21...
287 04:58:18.593083 Connected to conserv1.
288 04:58:18.593498 Escape character is '^]'.
289 04:58:18.593917
290 04:58:18.594335 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 04:58:18.594767
292 04:58:27.094439 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 04:58:27.095092 bl2_stage_init 0x01
294 04:58:27.095553 bl2_stage_init 0x81
295 04:58:27.099703 hw id: 0x0000 - pwm id 0x01
296 04:58:27.100222 bl2_stage_init 0xc1
297 04:58:27.105376 bl2_stage_init 0x02
298 04:58:27.105848
299 04:58:27.106273 L0:00000000
300 04:58:27.106686 L1:00000703
301 04:58:27.107084 L2:00008067
302 04:58:27.107483 L3:15000000
303 04:58:27.110881 S1:00000000
304 04:58:27.111341 B2:20282000
305 04:58:27.111759 B1:a0f83180
306 04:58:27.112201
307 04:58:27.112609 TE: 69674
308 04:58:27.113010
309 04:58:27.116525 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 04:58:27.117117
311 04:58:27.122224 Board ID = 1
312 04:58:27.122844 Set cpu clk to 24M
313 04:58:27.123302 Set clk81 to 24M
314 04:58:27.125507 Use GP1_pll as DSU clk.
315 04:58:27.125989 DSU clk: 1200 Mhz
316 04:58:27.131107 CPU clk: 1200 MHz
317 04:58:27.131655 Set clk81 to 166.6M
318 04:58:27.136668 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 04:58:27.137161 board id: 1
320 04:58:27.146212 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:58:27.156988 fw parse done
322 04:58:27.162805 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:58:27.205510 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:58:27.216413 PIEI prepare done
325 04:58:27.216856 fastboot data load
326 04:58:27.217258 fastboot data verify
327 04:58:27.221893 verify result: 266
328 04:58:27.227550 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 04:58:27.228022 LPDDR4 probe
330 04:58:27.228443 ddr clk to 1584MHz
331 04:58:27.235564 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:58:27.272815
333 04:58:27.273294 dmc_version 0001
334 04:58:27.279434 Check phy result
335 04:58:27.285295 INFO : End of CA training
336 04:58:27.285726 INFO : End of initialization
337 04:58:27.291057 INFO : Training has run successfully!
338 04:58:27.291487 Check phy result
339 04:58:27.296601 INFO : End of initialization
340 04:58:27.297024 INFO : End of read enable training
341 04:58:27.302170 INFO : End of fine write leveling
342 04:58:27.307757 INFO : End of Write leveling coarse delay
343 04:58:27.308216 INFO : Training has run successfully!
344 04:58:27.308612 Check phy result
345 04:58:27.313368 INFO : End of initialization
346 04:58:27.313805 INFO : End of read dq deskew training
347 04:58:27.318980 INFO : End of MPR read delay center optimization
348 04:58:27.324637 INFO : End of write delay center optimization
349 04:58:27.330231 INFO : End of read delay center optimization
350 04:58:27.330658 INFO : End of max read latency training
351 04:58:27.335708 INFO : Training has run successfully!
352 04:58:27.336164 1D training succeed
353 04:58:27.345055 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:58:27.392678 Check phy result
355 04:58:27.393269 INFO : End of initialization
356 04:58:27.414998 INFO : End of 2D read delay Voltage center optimization
357 04:58:27.434158 INFO : End of 2D read delay Voltage center optimization
358 04:58:27.485967 INFO : End of 2D write delay Voltage center optimization
359 04:58:27.535207 INFO : End of 2D write delay Voltage center optimization
360 04:58:27.540710 INFO : Training has run successfully!
361 04:58:27.541156
362 04:58:27.541555 channel==0
363 04:58:27.546272 RxClkDly_Margin_A0==78 ps 8
364 04:58:27.546712 TxDqDly_Margin_A0==88 ps 9
365 04:58:27.549796 RxClkDly_Margin_A1==88 ps 9
366 04:58:27.550416 TxDqDly_Margin_A1==88 ps 9
367 04:58:27.555287 TrainedVREFDQ_A0==74
368 04:58:27.555875 TrainedVREFDQ_A1==74
369 04:58:27.556376 VrefDac_Margin_A0==23
370 04:58:27.560788 DeviceVref_Margin_A0==40
371 04:58:27.561334 VrefDac_Margin_A1==23
372 04:58:27.566417 DeviceVref_Margin_A1==40
373 04:58:27.566959
374 04:58:27.567416
375 04:58:27.567869 channel==1
376 04:58:27.568357 RxClkDly_Margin_A0==88 ps 9
377 04:58:27.572176 TxDqDly_Margin_A0==88 ps 9
378 04:58:27.572727 RxClkDly_Margin_A1==78 ps 8
379 04:58:27.577679 TxDqDly_Margin_A1==78 ps 8
380 04:58:27.578257 TrainedVREFDQ_A0==77
381 04:58:27.578709 TrainedVREFDQ_A1==75
382 04:58:27.583278 VrefDac_Margin_A0==22
383 04:58:27.583812 DeviceVref_Margin_A0==37
384 04:58:27.584299 VrefDac_Margin_A1==22
385 04:58:27.588888 DeviceVref_Margin_A1==38
386 04:58:27.589421
387 04:58:27.594485 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:58:27.595012
389 04:58:27.622421 soc_vref_reg_value 0x 00000019 00000019 00000018 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000015 00000016 dram_vref_reg_value 0x 00000061
390 04:58:27.628208 2D training succeed
391 04:58:27.633520 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:58:27.634124 auto size-- 65535DDR cs0 size: 2048MB
393 04:58:27.639217 DDR cs1 size: 2048MB
394 04:58:27.639841 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:58:27.644771 cs0 DataBus test pass
396 04:58:27.645368 cs1 DataBus test pass
397 04:58:27.645820 cs0 AddrBus test pass
398 04:58:27.650413 cs1 AddrBus test pass
399 04:58:27.651045
400 04:58:27.651507 100bdlr_step_size ps== 478
401 04:58:27.652037 result report
402 04:58:27.656054 boot times 0Enable ddr reg access
403 04:58:27.662651 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:58:27.677052 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 04:58:28.332202 bl2z: ptr: 05129330, size: 00001e40
406 04:58:28.340136 0.0;M3 CHK:0;cm4_sp_mode 0
407 04:58:28.340778 MVN_1=0x00000000
408 04:58:28.341310 MVN_2=0x00000000
409 04:58:28.351470 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 04:58:28.352137 OPS=0x04
411 04:58:28.352633 ring efuse init
412 04:58:28.357048 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 04:58:28.357608 [0.017319 Inits done]
414 04:58:28.358058 secure task start!
415 04:58:28.364182 high task start!
416 04:58:28.364666 low task start!
417 04:58:28.365110 run into bl31
418 04:58:28.372798 NOTICE: BL31: v1.3(release):4fc40b1
419 04:58:28.380593 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 04:58:28.381088 NOTICE: BL31: G12A normal boot!
421 04:58:28.396108 NOTICE: BL31: BL33 decompress pass
422 04:58:28.401790 ERROR: Error initializing runtime service opteed_fast
423 04:58:31.143608 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 04:58:31.144632 bl2_stage_init 0x01
425 04:58:31.145317 bl2_stage_init 0x81
426 04:58:31.152078 hw id: 0x0000 - pwm id 0x01
427 04:58:31.152710 bl2_stage_init 0xc1
428 04:58:31.154062 bl2_stage_init 0x02
429 04:58:31.154561
430 04:58:31.154981 L0:00000000
431 04:58:31.155384 L1:00000703
432 04:58:31.155858 L2:00008067
433 04:58:31.156427 L3:15000000
434 04:58:31.158631 S1:00000000
435 04:58:31.159172 B2:20282000
436 04:58:31.159674 B1:a0f83180
437 04:58:31.160217
438 04:58:31.160867 TE: 69195
439 04:58:31.161347
440 04:58:31.164329 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 04:58:31.164939
442 04:58:31.169880 Board ID = 1
443 04:58:31.170527 Set cpu clk to 24M
444 04:58:31.171005 Set clk81 to 24M
445 04:58:31.175458 Use GP1_pll as DSU clk.
446 04:58:31.176074 DSU clk: 1200 Mhz
447 04:58:31.176534 CPU clk: 1200 MHz
448 04:58:31.181026 Set clk81 to 166.6M
449 04:58:31.186733 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 04:58:31.187322 board id: 1
451 04:58:31.194179 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 04:58:31.205041 fw parse done
453 04:58:31.210950 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 04:58:31.254159 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 04:58:31.265647 PIEI prepare done
456 04:58:31.266064 fastboot data load
457 04:58:31.266293 fastboot data verify
458 04:58:31.270806 verify result: 266
459 04:58:31.277222 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 04:58:31.277581 LPDDR4 probe
461 04:58:31.277799 ddr clk to 1584MHz
462 04:58:31.283529 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 04:58:31.322181
464 04:58:31.322605 dmc_version 0001
465 04:58:31.328273 Check phy result
466 04:58:31.335167 INFO : End of CA training
467 04:58:31.335601 INFO : End of initialization
468 04:58:31.340775 INFO : Training has run successfully!
469 04:58:31.341225 Check phy result
470 04:58:31.346275 INFO : End of initialization
471 04:58:31.346721 INFO : End of read enable training
472 04:58:31.351890 INFO : End of fine write leveling
473 04:58:31.357482 INFO : End of Write leveling coarse delay
474 04:58:31.357858 INFO : Training has run successfully!
475 04:58:31.358074 Check phy result
476 04:58:31.363365 INFO : End of initialization
477 04:58:31.364870 INFO : End of read dq deskew training
478 04:58:31.368716 INFO : End of MPR read delay center optimization
479 04:58:31.374289 INFO : End of write delay center optimization
480 04:58:31.379869 INFO : End of read delay center optimization
481 04:58:31.380396 INFO : End of max read latency training
482 04:58:31.385504 INFO : Training has run successfully!
483 04:58:31.386110 1D training succeed
484 04:58:31.394661 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 04:58:31.442896 Check phy result
486 04:58:31.443226 INFO : End of initialization
487 04:58:31.469434 INFO : End of 2D read delay Voltage center optimization
488 04:58:31.494569 INFO : End of 2D read delay Voltage center optimization
489 04:58:31.551220 INFO : End of 2D write delay Voltage center optimization
490 04:58:31.605309 INFO : End of 2D write delay Voltage center optimization
491 04:58:31.610770 INFO : Training has run successfully!
492 04:58:31.611271
493 04:58:31.611700 channel==0
494 04:58:31.616466 RxClkDly_Margin_A0==78 ps 8
495 04:58:31.616948 TxDqDly_Margin_A0==88 ps 9
496 04:58:31.621948 RxClkDly_Margin_A1==88 ps 9
497 04:58:31.622421 TxDqDly_Margin_A1==98 ps 10
498 04:58:31.622840 TrainedVREFDQ_A0==77
499 04:58:31.627543 TrainedVREFDQ_A1==74
500 04:58:31.628038 VrefDac_Margin_A0==23
501 04:58:31.628458 DeviceVref_Margin_A0==37
502 04:58:31.633182 VrefDac_Margin_A1==23
503 04:58:31.633679 DeviceVref_Margin_A1==40
504 04:58:31.634107
505 04:58:31.634516
506 04:58:31.634923 channel==1
507 04:58:31.638675 RxClkDly_Margin_A0==88 ps 9
508 04:58:31.639132 TxDqDly_Margin_A0==78 ps 8
509 04:58:31.644364 RxClkDly_Margin_A1==78 ps 8
510 04:58:31.644824 TxDqDly_Margin_A1==88 ps 9
511 04:58:31.649926 TrainedVREFDQ_A0==77
512 04:58:31.650371 TrainedVREFDQ_A1==75
513 04:58:31.650786 VrefDac_Margin_A0==22
514 04:58:31.655518 DeviceVref_Margin_A0==37
515 04:58:31.655958 VrefDac_Margin_A1==22
516 04:58:31.656413 DeviceVref_Margin_A1==38
517 04:58:31.661075
518 04:58:31.661521 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 04:58:31.661932
520 04:58:31.694710 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 04:58:31.695241 2D training succeed
522 04:58:31.700315 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 04:58:31.705915 auto size-- 65535DDR cs0 size: 2048MB
524 04:58:31.706357 DDR cs1 size: 2048MB
525 04:58:31.711460 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 04:58:31.711895 cs0 DataBus test pass
527 04:58:31.717092 cs1 DataBus test pass
528 04:58:31.717539 cs0 AddrBus test pass
529 04:58:31.717947 cs1 AddrBus test pass
530 04:58:31.718377
531 04:58:31.722687 100bdlr_step_size ps== 485
532 04:58:31.723138 result report
533 04:58:31.728430 boot times 0Enable ddr reg access
534 04:58:31.733353 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 04:58:31.747311 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 04:58:32.406968 bl2z: ptr: 05129330, size: 00001e40
537 04:58:32.414700 0.0;M3 CHK:0;cm4_sp_mode 0
538 04:58:32.415217 MVN_1=0x00000000
539 04:58:32.415655 MVN_2=0x00000000
540 04:58:32.425969 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 04:58:32.426266 OPS=0x04
542 04:58:32.426509 ring efuse init
543 04:58:32.431555 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 04:58:32.431860 [0.017354 Inits done]
545 04:58:32.432144 secure task start!
546 04:58:32.438942 high task start!
547 04:58:32.439274 low task start!
548 04:58:32.439509 run into bl31
549 04:58:32.447558 NOTICE: BL31: v1.3(release):4fc40b1
550 04:58:32.455392 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 04:58:32.455686 NOTICE: BL31: G12A normal boot!
552 04:58:32.470966 NOTICE: BL31: BL33 decompress pass
553 04:58:32.476693 ERROR: Error initializing runtime service opteed_fast
554 04:58:33.693817 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 04:58:33.694445 bl2_stage_init 0x01
556 04:58:33.694878 bl2_stage_init 0x81
557 04:58:33.699390 hw id: 0x0000 - pwm id 0x01
558 04:58:33.699903 bl2_stage_init 0xc1
559 04:58:33.704043 bl2_stage_init 0x02
560 04:58:33.704534
561 04:58:33.704963 L0:00000000
562 04:58:33.705378 L1:00000703
563 04:58:33.705785 L2:00008067
564 04:58:33.709675 L3:15000000
565 04:58:33.710169 S1:00000000
566 04:58:33.710590 B2:20282000
567 04:58:33.710993 B1:a0f83180
568 04:58:33.711390
569 04:58:33.711792 TE: 68845
570 04:58:33.712235
571 04:58:33.720889 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 04:58:33.721367
573 04:58:33.721782 Board ID = 1
574 04:58:33.722187 Set cpu clk to 24M
575 04:58:33.722582 Set clk81 to 24M
576 04:58:33.726360 Use GP1_pll as DSU clk.
577 04:58:33.726842 DSU clk: 1200 Mhz
578 04:58:33.727273 CPU clk: 1200 MHz
579 04:58:33.732014 Set clk81 to 166.6M
580 04:58:33.737470 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 04:58:33.737938 board id: 1
582 04:58:33.745570 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 04:58:33.756299 fw parse done
584 04:58:33.761560 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 04:58:33.804562 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 04:58:33.815846 PIEI prepare done
587 04:58:33.816415 fastboot data load
588 04:58:33.816911 fastboot data verify
589 04:58:33.821485 verify result: 266
590 04:58:33.826956 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 04:58:33.827431 LPDDR4 probe
592 04:58:33.827848 ddr clk to 1584MHz
593 04:58:33.834953 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 04:58:33.872249
595 04:58:33.872776 dmc_version 0001
596 04:58:33.878490 Check phy result
597 04:58:33.884886 INFO : End of CA training
598 04:58:33.885394 INFO : End of initialization
599 04:58:33.890483 INFO : Training has run successfully!
600 04:58:33.890802 Check phy result
601 04:58:33.896174 INFO : End of initialization
602 04:58:33.896478 INFO : End of read enable training
603 04:58:33.901641 INFO : End of fine write leveling
604 04:58:33.902289 INFO : End of Write leveling coarse delay
605 04:58:33.907838 INFO : Training has run successfully!
606 04:58:33.908150 Check phy result
607 04:58:33.913447 INFO : End of initialization
608 04:58:33.913743 INFO : End of read dq deskew training
609 04:58:33.919027 INFO : End of MPR read delay center optimization
610 04:58:33.922632 INFO : End of write delay center optimization
611 04:58:33.928009 INFO : End of read delay center optimization
612 04:58:33.933594 INFO : End of max read latency training
613 04:58:33.933891 INFO : Training has run successfully!
614 04:58:33.939183 1D training succeed
615 04:58:33.942965 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 04:58:33.990947 Check phy result
617 04:58:33.991327 INFO : End of initialization
618 04:58:34.013459 INFO : End of 2D read delay Voltage center optimization
619 04:58:34.033350 INFO : End of 2D read delay Voltage center optimization
620 04:58:34.084419 INFO : End of 2D write delay Voltage center optimization
621 04:58:34.134563 INFO : End of 2D write delay Voltage center optimization
622 04:58:34.140137 INFO : Training has run successfully!
623 04:58:34.140797
624 04:58:34.141414 channel==0
625 04:58:34.145648 RxClkDly_Margin_A0==78 ps 8
626 04:58:34.146264 TxDqDly_Margin_A0==98 ps 10
627 04:58:34.151275 RxClkDly_Margin_A1==88 ps 9
628 04:58:34.151925 TxDqDly_Margin_A1==98 ps 10
629 04:58:34.152533 TrainedVREFDQ_A0==74
630 04:58:34.156892 TrainedVREFDQ_A1==75
631 04:58:34.157561 VrefDac_Margin_A0==24
632 04:58:34.158144 DeviceVref_Margin_A0==40
633 04:58:34.162636 VrefDac_Margin_A1==23
634 04:58:34.163708 DeviceVref_Margin_A1==39
635 04:58:34.164135
636 04:58:34.164577
637 04:58:34.168047 channel==1
638 04:58:34.168518 RxClkDly_Margin_A0==78 ps 8
639 04:58:34.168876 TxDqDly_Margin_A0==78 ps 8
640 04:58:34.173616 RxClkDly_Margin_A1==78 ps 8
641 04:58:34.174167 TxDqDly_Margin_A1==88 ps 9
642 04:58:34.179270 TrainedVREFDQ_A0==77
643 04:58:34.179913 TrainedVREFDQ_A1==75
644 04:58:34.180423 VrefDac_Margin_A0==22
645 04:58:34.184939 DeviceVref_Margin_A0==37
646 04:58:34.185496 VrefDac_Margin_A1==22
647 04:58:34.190606 DeviceVref_Margin_A1==39
648 04:58:34.191171
649 04:58:34.191626 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 04:58:34.192114
651 04:58:34.224048 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 04:58:34.224686 2D training succeed
653 04:58:34.229695 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 04:58:34.235194 auto size-- 65535DDR cs0 size: 2048MB
655 04:58:34.235715 DDR cs1 size: 2048MB
656 04:58:34.240838 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 04:58:34.241347 cs0 DataBus test pass
658 04:58:34.246501 cs1 DataBus test pass
659 04:58:34.247016 cs0 AddrBus test pass
660 04:58:34.247465 cs1 AddrBus test pass
661 04:58:34.247901
662 04:58:34.252024 100bdlr_step_size ps== 478
663 04:58:34.252536 result report
664 04:58:34.257654 boot times 0Enable ddr reg access
665 04:58:34.262599 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 04:58:34.275788 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 04:58:34.931166 bl2z: ptr: 05129330, size: 00001e40
668 04:58:34.938347 0.0;M3 CHK:0;cm4_sp_mode 0
669 04:58:34.938744 MVN_1=0x00000000
670 04:58:34.938992 MVN_2=0x00000000
671 04:58:34.950179 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 04:58:34.951242 OPS=0x04
673 04:58:34.952220 ring efuse init
674 04:58:34.955565 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 04:58:34.956177 [0.017318 Inits done]
676 04:58:34.956650 secure task start!
677 04:58:34.963350 high task start!
678 04:58:34.964042 low task start!
679 04:58:34.964584 run into bl31
680 04:58:34.972079 NOTICE: BL31: v1.3(release):4fc40b1
681 04:58:34.979222 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 04:58:34.979920 NOTICE: BL31: G12A normal boot!
683 04:58:34.995391 NOTICE: BL31: BL33 decompress pass
684 04:58:35.000657 ERROR: Error initializing runtime service opteed_fast
685 04:58:35.794999
686 04:58:35.795676
687 04:58:35.801336 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 04:58:35.801904
689 04:58:35.803704 Model: Libre Computer AML-S905D3-CC Solitude
690 04:58:35.950331 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 04:58:35.966178 DRAM: 2 GiB (effective 3.8 GiB)
692 04:58:36.067282 Core: 406 devices, 33 uclasses, devicetree: separate
693 04:58:36.072429 WDT: Not starting watchdog@f0d0
694 04:58:36.098171 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 04:58:36.110329 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 04:58:36.114804 ** Bad device specification mmc 0 **
697 04:58:36.125372 Card did not respond to voltage select! : -110
698 04:58:36.132639 ** Bad device specification mmc 0 **
699 04:58:36.133439 Couldn't find partition mmc 0
700 04:58:36.141358 Card did not respond to voltage select! : -110
701 04:58:36.146901 ** Bad device specification mmc 0 **
702 04:58:36.147501 Couldn't find partition mmc 0
703 04:58:36.151257 Error: could not access storage.
704 04:58:36.447501 Net: eth0: ethernet@ff3f0000
705 04:58:36.448217 starting USB...
706 04:58:36.692956 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 04:58:36.693659 Starting the controller
708 04:58:36.699039 USB XHCI 1.10
709 04:58:38.253765 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 04:58:38.262318 scanning usb for storage devices... 0 Storage Device(s) found
712 04:58:38.315230 Hit any key to stop autoboot: 1
713 04:58:38.316435 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
714 04:58:38.317164 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
715 04:58:38.317749 Setting prompt string to ['=>']
716 04:58:38.318315 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
717 04:58:38.327406 0
718 04:58:38.328256 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 04:58:38.429515 => setenv autoload no
721 04:58:38.430561 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 04:58:38.437004 setenv autoload no
724 04:58:38.539173 => setenv initrd_high 0xffffffff
725 04:58:38.540497 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 04:58:38.544867 setenv initrd_high 0xffffffff
728 04:58:38.646679 => setenv fdt_high 0xffffffff
729 04:58:38.647567 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 04:58:38.651914 setenv fdt_high 0xffffffff
732 04:58:38.754450 => dhcp
733 04:58:38.755292 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 04:58:38.759299 dhcp
735 04:58:39.264091 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 04:58:39.264741 Speed: 1000, full duplex
737 04:58:39.265226 BOOTP broadcast 1
738 04:58:39.512500 BOOTP broadcast 2
739 04:58:39.527963 DHCP client bound to address 192.168.6.21 (262 ms)
741 04:58:39.630891 => setenv serverip 192.168.6.2
742 04:58:39.631920 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 04:58:39.636315 setenv serverip 192.168.6.2
745 04:58:39.738017 => tftpboot 0x01080000 927109/tftp-deploy-eeow900d/kernel/uImage
746 04:58:39.738949 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 04:58:39.745818 tftpboot 0x01080000 927109/tftp-deploy-eeow900d/kernel/uImage
748 04:58:39.746448 Speed: 1000, full duplex
749 04:58:39.747036 Using ethernet@ff3f0000 device
750 04:58:39.751273 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 04:58:39.756852 Filename '927109/tftp-deploy-eeow900d/kernel/uImage'.
752 04:58:39.760224 Load address: 0x1080000
753 04:58:43.973106 Loading: *################################################## 63.4 MiB
754 04:58:43.973700 15 MiB/s
755 04:58:43.974111 done
756 04:58:43.977308 Bytes transferred = 66443840 (3f5da40 hex)
758 04:58:44.078773 => tftpboot 0x08000000 927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot
759 04:58:44.079490 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
760 04:58:44.086244 tftpboot 0x08000000 927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot
761 04:58:44.086700 Speed: 1000, full duplex
762 04:58:44.087105 Using ethernet@ff3f0000 device
763 04:58:44.091642 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 04:58:44.101432 Filename '927109/tftp-deploy-eeow900d/ramdisk/ramdisk.cpio.gz.uboot'.
765 04:58:44.101950 Load address: 0x8000000
766 04:58:51.533632 Loading: *################T ################################# UDP wrong checksum 00000007 00004cd7
767 04:58:53.342362 UDP wrong checksum 000000ff 0000cefe
768 04:58:53.352845 UDP wrong checksum 000000ff 000062f1
769 04:58:53.994466 UDP wrong checksum 000000ff 000036cb
770 04:58:54.053003 UDP wrong checksum 000000ff 0000d2bd
771 04:58:56.534285 T UDP wrong checksum 00000007 00004cd7
772 04:58:58.984217 UDP wrong checksum 000000ff 0000e567
773 04:58:58.996762 UDP wrong checksum 000000ff 00007a5a
774 04:59:05.155343 T UDP wrong checksum 000000ff 0000ee90
775 04:59:05.204999 UDP wrong checksum 000000ff 00008183
776 04:59:06.536310 T UDP wrong checksum 00000007 00004cd7
777 04:59:26.540622 T T T T UDP wrong checksum 00000007 00004cd7
778 04:59:41.544326 T T
779 04:59:41.545144 Retry count exceeded; starting again
781 04:59:41.547075 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
784 04:59:41.549266 end: 2.4 uboot-commands (duration 00:01:23) [common]
786 04:59:41.551047 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
788 04:59:41.552369 end: 2 uboot-action (duration 00:01:23) [common]
790 04:59:41.554065 Cleaning after the job
791 04:59:41.554656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/ramdisk
792 04:59:41.556314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/kernel
793 04:59:41.616950 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/dtb
794 04:59:41.617860 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927109/tftp-deploy-eeow900d/modules
795 04:59:41.647717 start: 4.1 power-off (timeout 00:00:30) [common]
796 04:59:41.648486 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
797 04:59:41.682880 >> OK - accepted request
798 04:59:41.685266 Returned 0 in 0 seconds
799 04:59:41.786949 end: 4.1 power-off (duration 00:00:00) [common]
801 04:59:41.788290 start: 4.2 read-feedback (timeout 00:10:00) [common]
802 04:59:41.789193 Listened to connection for namespace 'common' for up to 1s
803 04:59:42.790177 Finalising connection for namespace 'common'
804 04:59:42.791067 Disconnecting from shell: Finalise
805 04:59:42.791592 =>
806 04:59:42.892660 end: 4.2 read-feedback (duration 00:00:01) [common]
807 04:59:42.893452 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927109
808 04:59:43.246333 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927109
809 04:59:43.247110 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.