Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:00:07.883069 lava-dispatcher, installed at version: 2024.01
2 05:00:07.883940 start: 0 validate
3 05:00:07.884506 Start time: 2024-11-02 05:00:07.884475+00:00 (UTC)
4 05:00:07.885150 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:00:07.885763 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:00:07.929538 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:00:07.930069 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 05:00:07.958610 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:00:07.959222 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:00:07.991707 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:00:07.992256 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:00:08.023810 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:00:08.024409 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 05:00:08.064528 validate duration: 0.18
16 05:00:08.065408 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:00:08.065743 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:00:08.066063 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:00:08.066662 Not decompressing ramdisk as can be used compressed.
20 05:00:08.067124 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 05:00:08.067412 saving as /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/ramdisk/initrd.cpio.gz
22 05:00:08.067681 total size: 5628182 (5 MB)
23 05:00:08.103193 progress 0 % (0 MB)
24 05:00:08.107754 progress 5 % (0 MB)
25 05:00:08.111852 progress 10 % (0 MB)
26 05:00:08.115549 progress 15 % (0 MB)
27 05:00:08.119528 progress 20 % (1 MB)
28 05:00:08.123163 progress 25 % (1 MB)
29 05:00:08.127229 progress 30 % (1 MB)
30 05:00:08.131220 progress 35 % (1 MB)
31 05:00:08.134901 progress 40 % (2 MB)
32 05:00:08.138851 progress 45 % (2 MB)
33 05:00:08.142329 progress 50 % (2 MB)
34 05:00:08.146293 progress 55 % (2 MB)
35 05:00:08.150370 progress 60 % (3 MB)
36 05:00:08.153995 progress 65 % (3 MB)
37 05:00:08.157945 progress 70 % (3 MB)
38 05:00:08.161543 progress 75 % (4 MB)
39 05:00:08.165407 progress 80 % (4 MB)
40 05:00:08.168695 progress 85 % (4 MB)
41 05:00:08.172363 progress 90 % (4 MB)
42 05:00:08.176234 progress 95 % (5 MB)
43 05:00:08.179686 progress 100 % (5 MB)
44 05:00:08.180410 5 MB downloaded in 0.11 s (47.63 MB/s)
45 05:00:08.180998 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:00:08.181882 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:00:08.182174 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:00:08.182442 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:00:08.182903 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 05:00:08.183144 saving as /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/kernel/Image
52 05:00:08.183353 total size: 66443776 (63 MB)
53 05:00:08.183560 No compression specified
54 05:00:08.225436 progress 0 % (0 MB)
55 05:00:08.264653 progress 5 % (3 MB)
56 05:00:08.303836 progress 10 % (6 MB)
57 05:00:08.343163 progress 15 % (9 MB)
58 05:00:08.382331 progress 20 % (12 MB)
59 05:00:08.421021 progress 25 % (15 MB)
60 05:00:08.460755 progress 30 % (19 MB)
61 05:00:08.500368 progress 35 % (22 MB)
62 05:00:08.539505 progress 40 % (25 MB)
63 05:00:08.578378 progress 45 % (28 MB)
64 05:00:08.618246 progress 50 % (31 MB)
65 05:00:08.658191 progress 55 % (34 MB)
66 05:00:08.697686 progress 60 % (38 MB)
67 05:00:08.736714 progress 65 % (41 MB)
68 05:00:08.775604 progress 70 % (44 MB)
69 05:00:08.814412 progress 75 % (47 MB)
70 05:00:08.853573 progress 80 % (50 MB)
71 05:00:08.893823 progress 85 % (53 MB)
72 05:00:08.933121 progress 90 % (57 MB)
73 05:00:08.972859 progress 95 % (60 MB)
74 05:00:09.011005 progress 100 % (63 MB)
75 05:00:09.011737 63 MB downloaded in 0.83 s (76.49 MB/s)
76 05:00:09.012257 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:00:09.013084 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:00:09.013357 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:00:09.013624 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:00:09.014066 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:00:09.014336 saving as /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:00:09.014542 total size: 54703 (0 MB)
84 05:00:09.014750 No compression specified
85 05:00:09.057649 progress 59 % (0 MB)
86 05:00:09.058585 progress 100 % (0 MB)
87 05:00:09.059193 0 MB downloaded in 0.04 s (1.17 MB/s)
88 05:00:09.059697 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:00:09.060618 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:00:09.061009 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:00:09.061333 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:00:09.061817 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 05:00:09.062095 saving as /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/nfsrootfs/full.rootfs.tar
95 05:00:09.062301 total size: 107552908 (102 MB)
96 05:00:09.062518 Using unxz to decompress xz
97 05:00:09.097835 progress 0 % (0 MB)
98 05:00:09.743345 progress 5 % (5 MB)
99 05:00:10.469117 progress 10 % (10 MB)
100 05:00:11.191735 progress 15 % (15 MB)
101 05:00:11.949115 progress 20 % (20 MB)
102 05:00:12.520083 progress 25 % (25 MB)
103 05:00:13.138864 progress 30 % (30 MB)
104 05:00:13.877322 progress 35 % (35 MB)
105 05:00:14.245202 progress 40 % (41 MB)
106 05:00:14.675667 progress 45 % (46 MB)
107 05:00:15.365576 progress 50 % (51 MB)
108 05:00:16.054887 progress 55 % (56 MB)
109 05:00:16.806593 progress 60 % (61 MB)
110 05:00:17.561811 progress 65 % (66 MB)
111 05:00:18.310917 progress 70 % (71 MB)
112 05:00:19.078813 progress 75 % (76 MB)
113 05:00:19.762565 progress 80 % (82 MB)
114 05:00:20.475888 progress 85 % (87 MB)
115 05:00:21.216030 progress 90 % (92 MB)
116 05:00:21.947188 progress 95 % (97 MB)
117 05:00:22.695753 progress 100 % (102 MB)
118 05:00:22.707659 102 MB downloaded in 13.65 s (7.52 MB/s)
119 05:00:22.708433 end: 1.4.1 http-download (duration 00:00:14) [common]
121 05:00:22.710242 end: 1.4 download-retry (duration 00:00:14) [common]
122 05:00:22.710823 start: 1.5 download-retry (timeout 00:09:45) [common]
123 05:00:22.711395 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 05:00:22.712411 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 05:00:22.712937 saving as /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/modules/modules.tar
126 05:00:22.713391 total size: 16116020 (15 MB)
127 05:00:22.713852 Using unxz to decompress xz
128 05:00:22.759887 progress 0 % (0 MB)
129 05:00:22.860263 progress 5 % (0 MB)
130 05:00:22.977547 progress 10 % (1 MB)
131 05:00:23.094832 progress 15 % (2 MB)
132 05:00:23.242843 progress 20 % (3 MB)
133 05:00:23.415265 progress 25 % (3 MB)
134 05:00:23.551357 progress 30 % (4 MB)
135 05:00:23.739445 progress 35 % (5 MB)
136 05:00:23.868864 progress 40 % (6 MB)
137 05:00:23.997820 progress 45 % (6 MB)
138 05:00:24.138313 progress 50 % (7 MB)
139 05:00:24.276346 progress 55 % (8 MB)
140 05:00:24.418009 progress 60 % (9 MB)
141 05:00:24.550412 progress 65 % (10 MB)
142 05:00:24.684247 progress 70 % (10 MB)
143 05:00:24.817773 progress 75 % (11 MB)
144 05:00:24.955714 progress 80 % (12 MB)
145 05:00:25.090706 progress 85 % (13 MB)
146 05:00:25.220449 progress 90 % (13 MB)
147 05:00:25.344551 progress 95 % (14 MB)
148 05:00:25.477757 progress 100 % (15 MB)
149 05:00:25.493967 15 MB downloaded in 2.78 s (5.53 MB/s)
150 05:00:25.494938 end: 1.5.1 http-download (duration 00:00:03) [common]
152 05:00:25.496813 end: 1.5 download-retry (duration 00:00:03) [common]
153 05:00:25.497418 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 05:00:25.498019 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 05:00:35.923575 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927130/extract-nfsrootfs-toftjaxx
156 05:00:35.924204 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 05:00:35.924496 start: 1.6.2 lava-overlay (timeout 00:09:32) [common]
158 05:00:35.925118 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x
159 05:00:35.925591 makedir: /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin
160 05:00:35.925979 makedir: /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/tests
161 05:00:35.926352 makedir: /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/results
162 05:00:35.926722 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-add-keys
163 05:00:35.927315 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-add-sources
164 05:00:35.927828 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-background-process-start
165 05:00:35.928356 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-background-process-stop
166 05:00:35.928876 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-common-functions
167 05:00:35.929366 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-echo-ipv4
168 05:00:35.929841 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-install-packages
169 05:00:35.930325 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-installed-packages
170 05:00:35.930817 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-os-build
171 05:00:35.931327 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-probe-channel
172 05:00:35.931811 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-probe-ip
173 05:00:35.932325 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-target-ip
174 05:00:35.932797 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-target-mac
175 05:00:35.933268 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-target-storage
176 05:00:35.933745 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-case
177 05:00:35.934214 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-event
178 05:00:35.934697 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-feedback
179 05:00:35.935189 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-raise
180 05:00:35.935661 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-reference
181 05:00:35.936169 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-runner
182 05:00:35.936736 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-set
183 05:00:35.937279 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-test-shell
184 05:00:35.937791 Updating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-install-packages (oe)
185 05:00:35.938402 Updating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/bin/lava-installed-packages (oe)
186 05:00:35.938853 Creating /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/environment
187 05:00:35.939221 LAVA metadata
188 05:00:35.939479 - LAVA_JOB_ID=927130
189 05:00:35.939715 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:00:35.940117 start: 1.6.2.1 ssh-authorize (timeout 00:09:32) [common]
191 05:00:35.941106 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:00:35.941414 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:32) [common]
193 05:00:35.941620 skipped lava-vland-overlay
194 05:00:35.941861 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:00:35.942114 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:32) [common]
196 05:00:35.942331 skipped lava-multinode-overlay
197 05:00:35.942570 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:00:35.942822 start: 1.6.2.4 test-definition (timeout 00:09:32) [common]
199 05:00:35.943068 Loading test definitions
200 05:00:35.943341 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:32) [common]
201 05:00:35.943560 Using /lava-927130 at stage 0
202 05:00:35.944780 uuid=927130_1.6.2.4.1 testdef=None
203 05:00:35.945099 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:00:35.945381 start: 1.6.2.4.2 test-overlay (timeout 00:09:32) [common]
205 05:00:35.947208 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:00:35.948011 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:32) [common]
208 05:00:35.950260 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:00:35.951078 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:32) [common]
211 05:00:35.953300 runner path: /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/0/tests/0_dmesg test_uuid 927130_1.6.2.4.1
212 05:00:35.953871 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:00:35.954625 Creating lava-test-runner.conf files
215 05:00:35.954824 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927130/lava-overlay-gi357x9x/lava-927130/0 for stage 0
216 05:00:35.955157 - 0_dmesg
217 05:00:35.955492 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:00:35.955765 start: 1.6.2.5 compress-overlay (timeout 00:09:32) [common]
219 05:00:35.977629 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:00:35.978026 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:32) [common]
221 05:00:35.978287 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:00:35.978555 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:00:35.978816 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
224 05:00:36.601486 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:00:36.601940 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
226 05:00:36.602184 extracting modules file /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927130/extract-nfsrootfs-toftjaxx
227 05:00:38.154517 extracting modules file /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927130/extract-overlay-ramdisk-qssuzumb/ramdisk
228 05:00:39.734061 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:00:39.734537 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
230 05:00:39.734816 [common] Applying overlay to NFS
231 05:00:39.735027 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927130/compress-overlay-tyvzg62z/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927130/extract-nfsrootfs-toftjaxx
232 05:00:39.763825 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:00:39.764228 start: 1.6.6 prepare-kernel (timeout 00:09:28) [common]
234 05:00:39.764502 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:28) [common]
235 05:00:39.764729 Converting downloaded kernel to a uImage
236 05:00:39.765026 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/kernel/Image /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/kernel/uImage
237 05:00:40.533394 output: Image Name:
238 05:00:40.533812 output: Created: Sat Nov 2 05:00:39 2024
239 05:00:40.534020 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:00:40.534224 output: Data Size: 66443776 Bytes = 64886.50 KiB = 63.37 MiB
241 05:00:40.534425 output: Load Address: 01080000
242 05:00:40.534624 output: Entry Point: 01080000
243 05:00:40.534822 output:
244 05:00:40.535154 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 05:00:40.535418 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 05:00:40.535687 start: 1.6.7 configure-preseed-file (timeout 00:09:28) [common]
247 05:00:40.535938 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:00:40.536240 start: 1.6.8 compress-ramdisk (timeout 00:09:28) [common]
249 05:00:40.536501 Building ramdisk /var/lib/lava/dispatcher/tmp/927130/extract-overlay-ramdisk-qssuzumb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927130/extract-overlay-ramdisk-qssuzumb/ramdisk
250 05:00:43.690343 >> 239643 blocks
251 05:00:53.971081 Adding RAMdisk u-boot header.
252 05:00:53.971676 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927130/extract-overlay-ramdisk-qssuzumb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927130/extract-overlay-ramdisk-qssuzumb/ramdisk.cpio.gz.uboot
253 05:00:54.302430 output: Image Name:
254 05:00:54.302941 output: Created: Sat Nov 2 05:00:53 2024
255 05:00:54.303257 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:00:54.303524 output: Data Size: 30952399 Bytes = 30226.95 KiB = 29.52 MiB
257 05:00:54.303787 output: Load Address: 00000000
258 05:00:54.304313 output: Entry Point: 00000000
259 05:00:54.305118 output:
260 05:00:54.307022 rename /var/lib/lava/dispatcher/tmp/927130/extract-overlay-ramdisk-qssuzumb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot
261 05:00:54.308389 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 05:00:54.309537 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 05:00:54.310537 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
264 05:00:54.311442 No LXC device requested
265 05:00:54.312447 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:00:54.313502 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
267 05:00:54.314498 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:00:54.315259 Checking files for TFTP limit of 4294967296 bytes.
269 05:00:54.320530 end: 1 tftp-deploy (duration 00:00:46) [common]
270 05:00:54.321655 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:00:54.322645 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:00:54.323639 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:00:54.324783 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:00:54.325736 Using kernel file from prepare-kernel: 927130/tftp-deploy-nl6bwosl/kernel/uImage
275 05:00:54.326946 substitutions:
276 05:00:54.327703 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:00:54.328748 - {DTB_ADDR}: 0x01070000
278 05:00:54.329512 - {DTB}: 927130/tftp-deploy-nl6bwosl/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:00:54.330349 - {INITRD}: 927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot
280 05:00:54.331094 - {KERNEL_ADDR}: 0x01080000
281 05:00:54.331862 - {KERNEL}: 927130/tftp-deploy-nl6bwosl/kernel/uImage
282 05:00:54.332669 - {LAVA_MAC}: None
283 05:00:54.333488 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927130/extract-nfsrootfs-toftjaxx
284 05:00:54.334292 - {NFS_SERVER_IP}: 192.168.6.2
285 05:00:54.334965 - {PRESEED_CONFIG}: None
286 05:00:54.335797 - {PRESEED_LOCAL}: None
287 05:00:54.336566 - {RAMDISK_ADDR}: 0x08000000
288 05:00:54.337378 - {RAMDISK}: 927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot
289 05:00:54.338120 - {ROOT_PART}: None
290 05:00:54.338893 - {ROOT}: None
291 05:00:54.339636 - {SERVER_IP}: 192.168.6.2
292 05:00:54.340535 - {TEE_ADDR}: 0x83000000
293 05:00:54.341241 - {TEE}: None
294 05:00:54.342047 Parsed boot commands:
295 05:00:54.342774 - setenv autoload no
296 05:00:54.343510 - setenv initrd_high 0xffffffff
297 05:00:54.344381 - setenv fdt_high 0xffffffff
298 05:00:54.345056 - dhcp
299 05:00:54.345877 - setenv serverip 192.168.6.2
300 05:00:54.346604 - tftpboot 0x01080000 927130/tftp-deploy-nl6bwosl/kernel/uImage
301 05:00:54.347359 - tftpboot 0x08000000 927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot
302 05:00:54.348127 - tftpboot 0x01070000 927130/tftp-deploy-nl6bwosl/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:00:54.348840 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927130/extract-nfsrootfs-toftjaxx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:00:54.349467 - bootm 0x01080000 0x08000000 0x01070000
305 05:00:54.350314 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:00:54.353497 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:00:54.354232 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:00:54.368427 Setting prompt string to ['lava-test: # ']
310 05:00:54.369658 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:00:54.370123 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:00:54.370503 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:00:54.371013 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:00:54.371917 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:00:54.407028 >> OK - accepted request
316 05:00:54.409083 Returned 0 in 0 seconds
317 05:00:54.510394 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:00:54.513605 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:00:54.514794 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:00:54.515773 Setting prompt string to ['Hit any key to stop autoboot']
322 05:00:54.516784 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:00:54.519752 Trying 192.168.56.21...
324 05:00:54.520717 Connected to conserv1.
325 05:00:54.521567 Escape character is '^]'.
326 05:00:54.522332
327 05:00:54.523194 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:00:54.524049
329 05:01:06.167401 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 05:01:06.168241 bl2_stage_init 0x81
331 05:01:06.173014 hw id: 0x0000 - pwm id 0x01
332 05:01:06.173587 bl2_stage_init 0xc1
333 05:01:06.174100 bl2_stage_init 0x02
334 05:01:06.174638
335 05:01:06.178565 L0:00000000
336 05:01:06.179144 L1:20000703
337 05:01:06.179695 L2:00008067
338 05:01:06.180214 L3:14000000
339 05:01:06.180718 B2:00402000
340 05:01:06.184315 B1:e0f83180
341 05:01:06.184893
342 05:01:06.185393 TE: 58150
343 05:01:06.185894
344 05:01:06.189883 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 05:01:06.190457
346 05:01:06.190965 Board ID = 1
347 05:01:06.195437 Set A53 clk to 24M
348 05:01:06.196039 Set A73 clk to 24M
349 05:01:06.196588 Set clk81 to 24M
350 05:01:06.201059 A53 clk: 1200 MHz
351 05:01:06.201684 A73 clk: 1200 MHz
352 05:01:06.202183 CLK81: 166.6M
353 05:01:06.202678 smccc: 00012aab
354 05:01:06.206481 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 05:01:06.212204 board id: 1
356 05:01:06.217989 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 05:01:06.228605 fw parse done
358 05:01:06.234666 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 05:01:06.277100 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 05:01:06.288044 PIEI prepare done
361 05:01:06.288658 fastboot data load
362 05:01:06.289232 fastboot data verify
363 05:01:06.293706 verify result: 266
364 05:01:06.299260 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 05:01:06.299901 LPDDR4 probe
366 05:01:06.300452 ddr clk to 1584MHz
367 05:01:06.307222 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 05:01:06.344651
369 05:01:06.345278 dmc_version 0001
370 05:01:06.351177 Check phy result
371 05:01:06.357006 INFO : End of CA training
372 05:01:06.357548 INFO : End of initialization
373 05:01:06.362617 INFO : Training has run successfully!
374 05:01:06.363158 Check phy result
375 05:01:06.368249 INFO : End of initialization
376 05:01:06.368796 INFO : End of read enable training
377 05:01:06.371543 INFO : End of fine write leveling
378 05:01:06.377122 INFO : End of Write leveling coarse delay
379 05:01:06.382709 INFO : Training has run successfully!
380 05:01:06.383251 Check phy result
381 05:01:06.383744 INFO : End of initialization
382 05:01:06.388302 INFO : End of read dq deskew training
383 05:01:06.393886 INFO : End of MPR read delay center optimization
384 05:01:06.394420 INFO : End of write delay center optimization
385 05:01:06.399470 INFO : End of read delay center optimization
386 05:01:06.405089 INFO : End of max read latency training
387 05:01:06.405688 INFO : Training has run successfully!
388 05:01:06.410688 1D training succeed
389 05:01:06.416679 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 05:01:06.464314 Check phy result
391 05:01:06.464943 INFO : End of initialization
392 05:01:06.486790 INFO : End of 2D read delay Voltage center optimization
393 05:01:06.507011 INFO : End of 2D read delay Voltage center optimization
394 05:01:06.558778 INFO : End of 2D write delay Voltage center optimization
395 05:01:06.608054 INFO : End of 2D write delay Voltage center optimization
396 05:01:06.613584 INFO : Training has run successfully!
397 05:01:06.614169
398 05:01:06.614671 channel==0
399 05:01:06.619174 RxClkDly_Margin_A0==88 ps 9
400 05:01:06.619713 TxDqDly_Margin_A0==98 ps 10
401 05:01:06.624685 RxClkDly_Margin_A1==88 ps 9
402 05:01:06.625232 TxDqDly_Margin_A1==98 ps 10
403 05:01:06.625739 TrainedVREFDQ_A0==74
404 05:01:06.630326 TrainedVREFDQ_A1==74
405 05:01:06.630867 VrefDac_Margin_A0==25
406 05:01:06.631430 DeviceVref_Margin_A0==40
407 05:01:06.635934 VrefDac_Margin_A1==25
408 05:01:06.636560 DeviceVref_Margin_A1==40
409 05:01:06.637045
410 05:01:06.637541
411 05:01:06.641600 channel==1
412 05:01:06.642099 RxClkDly_Margin_A0==98 ps 10
413 05:01:06.642550 TxDqDly_Margin_A0==88 ps 9
414 05:01:06.647176 RxClkDly_Margin_A1==98 ps 10
415 05:01:06.647673 TxDqDly_Margin_A1==98 ps 10
416 05:01:06.652767 TrainedVREFDQ_A0==76
417 05:01:06.653256 TrainedVREFDQ_A1==77
418 05:01:06.653702 VrefDac_Margin_A0==22
419 05:01:06.658296 DeviceVref_Margin_A0==38
420 05:01:06.658774 VrefDac_Margin_A1==22
421 05:01:06.663962 DeviceVref_Margin_A1==37
422 05:01:06.664517
423 05:01:06.664963 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 05:01:06.669567
425 05:01:06.697570 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
426 05:01:06.698166 2D training succeed
427 05:01:06.703124 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 05:01:06.708622 auto size-- 65535DDR cs0 size: 2048MB
429 05:01:06.709107 DDR cs1 size: 2048MB
430 05:01:06.714276 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 05:01:06.714760 cs0 DataBus test pass
432 05:01:06.719865 cs1 DataBus test pass
433 05:01:06.720622 cs0 AddrBus test pass
434 05:01:06.721187 cs1 AddrBus test pass
435 05:01:06.721733
436 05:01:06.725466 100bdlr_step_size ps== 420
437 05:01:06.726063 result report
438 05:01:06.731018 boot times 0Enable ddr reg access
439 05:01:06.736495 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 05:01:06.749962 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 05:01:07.322275 0.0;M3 CHK:0;cm4_sp_mode 0
442 05:01:07.323368 MVN_1=0x00000000
443 05:01:07.327466 MVN_2=0x00000000
444 05:01:07.333241 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 05:01:07.334189 OPS=0x10
446 05:01:07.334950 ring efuse init
447 05:01:07.335740 chipver efuse init
448 05:01:07.341480 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 05:01:07.342342 [0.018961 Inits done]
450 05:01:07.349333 secure task start!
451 05:01:07.350332 high task start!
452 05:01:07.351102 low task start!
453 05:01:07.351927 run into bl31
454 05:01:07.355761 NOTICE: BL31: v1.3(release):4fc40b1
455 05:01:07.363494 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 05:01:07.364472 NOTICE: BL31: G12A normal boot!
457 05:01:07.388873 NOTICE: BL31: BL33 decompress pass
458 05:01:07.394563 ERROR: Error initializing runtime service opteed_fast
459 05:01:08.627341
460 05:01:08.627761
461 05:01:08.635657 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 05:01:08.635967
463 05:01:08.636209 Model: Libre Computer AML-A311D-CC Alta
464 05:01:08.844200 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 05:01:08.867546 DRAM: 2 GiB (effective 3.8 GiB)
466 05:01:09.010518 Core: 408 devices, 31 uclasses, devicetree: separate
467 05:01:09.016293 WDT: Not starting watchdog@f0d0
468 05:01:09.048698 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 05:01:09.061039 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 05:01:09.066028 ** Bad device specification mmc 0 **
471 05:01:09.076361 Card did not respond to voltage select! : -110
472 05:01:09.084053 ** Bad device specification mmc 0 **
473 05:01:09.084342 Couldn't find partition mmc 0
474 05:01:09.092403 Card did not respond to voltage select! : -110
475 05:01:09.098000 ** Bad device specification mmc 0 **
476 05:01:09.098304 Couldn't find partition mmc 0
477 05:01:09.103122 Error: could not access storage.
478 05:01:10.367806 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
479 05:01:10.368251 bl2_stage_init 0x81
480 05:01:10.373284 hw id: 0x0000 - pwm id 0x01
481 05:01:10.373553 bl2_stage_init 0xc1
482 05:01:10.373761 bl2_stage_init 0x02
483 05:01:10.373963
484 05:01:10.378882 L0:00000000
485 05:01:10.379140 L1:20000703
486 05:01:10.379343 L2:00008067
487 05:01:10.379544 L3:14000000
488 05:01:10.379740 B2:00402000
489 05:01:10.384502 B1:e0f83180
490 05:01:10.384764
491 05:01:10.384972 TE: 58150
492 05:01:10.385171
493 05:01:10.390140 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
494 05:01:10.390409
495 05:01:10.390612 Board ID = 1
496 05:01:10.395685 Set A53 clk to 24M
497 05:01:10.395964 Set A73 clk to 24M
498 05:01:10.396204 Set clk81 to 24M
499 05:01:10.401275 A53 clk: 1200 MHz
500 05:01:10.401545 A73 clk: 1200 MHz
501 05:01:10.401752 CLK81: 166.6M
502 05:01:10.401957 smccc: 00012aac
503 05:01:10.406883 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
504 05:01:10.412480 board id: 1
505 05:01:10.418300 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
506 05:01:10.428987 fw parse done
507 05:01:10.434915 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
508 05:01:10.477558 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
509 05:01:10.488447 PIEI prepare done
510 05:01:10.488757 fastboot data load
511 05:01:10.488965 fastboot data verify
512 05:01:10.494228 verify result: 266
513 05:01:10.499708 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
514 05:01:10.499970 LPDDR4 probe
515 05:01:10.500231 ddr clk to 1584MHz
516 05:01:10.507663 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
517 05:01:10.545004
518 05:01:10.545346 dmc_version 0001
519 05:01:10.550762 Check phy result
520 05:01:10.557481 INFO : End of CA training
521 05:01:10.557798 INFO : End of initialization
522 05:01:10.563062 INFO : Training has run successfully!
523 05:01:10.563358 Check phy result
524 05:01:10.568658 INFO : End of initialization
525 05:01:10.568945 INFO : End of read enable training
526 05:01:10.574257 INFO : End of fine write leveling
527 05:01:10.579864 INFO : End of Write leveling coarse delay
528 05:01:10.580302 INFO : Training has run successfully!
529 05:01:10.580757 Check phy result
530 05:01:10.585511 INFO : End of initialization
531 05:01:10.586015 INFO : End of read dq deskew training
532 05:01:10.591090 INFO : End of MPR read delay center optimization
533 05:01:10.596697 INFO : End of write delay center optimization
534 05:01:10.602311 INFO : End of read delay center optimization
535 05:01:10.602828 INFO : End of max read latency training
536 05:01:10.607943 INFO : Training has run successfully!
537 05:01:10.608578 1D training succeed
538 05:01:10.617112 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 05:01:10.664816 Check phy result
540 05:01:10.665464 INFO : End of initialization
541 05:01:10.687474 INFO : End of 2D read delay Voltage center optimization
542 05:01:10.707613 INFO : End of 2D read delay Voltage center optimization
543 05:01:10.759650 INFO : End of 2D write delay Voltage center optimization
544 05:01:10.809055 INFO : End of 2D write delay Voltage center optimization
545 05:01:10.814518 INFO : Training has run successfully!
546 05:01:10.815028
547 05:01:10.815480 channel==0
548 05:01:10.820114 RxClkDly_Margin_A0==88 ps 9
549 05:01:10.820636 TxDqDly_Margin_A0==98 ps 10
550 05:01:10.825708 RxClkDly_Margin_A1==88 ps 9
551 05:01:10.826225 TxDqDly_Margin_A1==98 ps 10
552 05:01:10.826683 TrainedVREFDQ_A0==74
553 05:01:10.831301 TrainedVREFDQ_A1==74
554 05:01:10.831811 VrefDac_Margin_A0==25
555 05:01:10.832323 DeviceVref_Margin_A0==40
556 05:01:10.836908 VrefDac_Margin_A1==24
557 05:01:10.837411 DeviceVref_Margin_A1==40
558 05:01:10.837856
559 05:01:10.838298
560 05:01:10.842521 channel==1
561 05:01:10.843011 RxClkDly_Margin_A0==98 ps 10
562 05:01:10.843454 TxDqDly_Margin_A0==98 ps 10
563 05:01:10.848142 RxClkDly_Margin_A1==98 ps 10
564 05:01:10.848707 TxDqDly_Margin_A1==88 ps 9
565 05:01:10.853748 TrainedVREFDQ_A0==77
566 05:01:10.854292 TrainedVREFDQ_A1==77
567 05:01:10.854740 VrefDac_Margin_A0==22
568 05:01:10.859310 DeviceVref_Margin_A0==37
569 05:01:10.859817 VrefDac_Margin_A1==22
570 05:01:10.864917 DeviceVref_Margin_A1==37
571 05:01:10.865420
572 05:01:10.865866 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
573 05:01:10.870491
574 05:01:10.898523 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
575 05:01:10.899156 2D training succeed
576 05:01:10.904101 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
577 05:01:10.909769 auto size-- 65535DDR cs0 size: 2048MB
578 05:01:10.910286 DDR cs1 size: 2048MB
579 05:01:10.915307 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
580 05:01:10.915816 cs0 DataBus test pass
581 05:01:10.920928 cs1 DataBus test pass
582 05:01:10.921439 cs0 AddrBus test pass
583 05:01:10.921884 cs1 AddrBus test pass
584 05:01:10.922318
585 05:01:10.926492 100bdlr_step_size ps== 420
586 05:01:10.927005 result report
587 05:01:10.932105 boot times 0Enable ddr reg access
588 05:01:10.937587 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
589 05:01:10.951032 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
590 05:01:11.524741 0.0;M3 CHK:0;cm4_sp_mode 0
591 05:01:11.525474 MVN_1=0x00000000
592 05:01:11.530164 MVN_2=0x00000000
593 05:01:11.535915 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
594 05:01:11.536541 OPS=0x10
595 05:01:11.536988 ring efuse init
596 05:01:11.537424 chipver efuse init
597 05:01:11.542143 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
598 05:01:11.547201 [0.018961 Inits done]
599 05:01:11.547799 secure task start!
600 05:01:11.548287 high task start!
601 05:01:11.551727 low task start!
602 05:01:11.552245 run into bl31
603 05:01:11.558423 NOTICE: BL31: v1.3(release):4fc40b1
604 05:01:11.566196 NOTICE: BL31: Built : 15:58:17, May 22 2019
605 05:01:11.566818 NOTICE: BL31: G12A normal boot!
606 05:01:11.591747 NOTICE: BL31: BL33 decompress pass
607 05:01:11.597314 ERROR: Error initializing runtime service opteed_fast
608 05:01:12.830331
609 05:01:12.831074
610 05:01:12.839016 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
611 05:01:12.839565
612 05:01:12.840148 Model: Libre Computer AML-A311D-CC Alta
613 05:01:13.047366 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
614 05:01:13.070668 DRAM: 2 GiB (effective 3.8 GiB)
615 05:01:13.213633 Core: 408 devices, 31 uclasses, devicetree: separate
616 05:01:13.219483 WDT: Not starting watchdog@f0d0
617 05:01:13.251874 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
618 05:01:13.264239 Loading Environment from FAT... Card did not respond to voltage select! : -110
619 05:01:13.269180 ** Bad device specification mmc 0 **
620 05:01:13.279534 Card did not respond to voltage select! : -110
621 05:01:13.287181 ** Bad device specification mmc 0 **
622 05:01:13.287781 Couldn't find partition mmc 0
623 05:01:13.295461 Card did not respond to voltage select! : -110
624 05:01:13.300959 ** Bad device specification mmc 0 **
625 05:01:13.301546 Couldn't find partition mmc 0
626 05:01:13.306066 Error: could not access storage.
627 05:01:13.648790 Net: eth0: ethernet@ff3f0000
628 05:01:13.649208 starting USB...
629 05:01:13.901407 Bus usb@ff500000: Register 3000140 NbrPorts 3
630 05:01:13.902078 Starting the controller
631 05:01:13.908290 USB XHCI 1.10
632 05:01:15.618223 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
633 05:01:15.618668 bl2_stage_init 0x81
634 05:01:15.623663 hw id: 0x0000 - pwm id 0x01
635 05:01:15.623965 bl2_stage_init 0xc1
636 05:01:15.624204 bl2_stage_init 0x02
637 05:01:15.624421
638 05:01:15.629294 L0:00000000
639 05:01:15.629866 L1:20000703
640 05:01:15.630309 L2:00008067
641 05:01:15.630743 L3:14000000
642 05:01:15.631174 B2:00402000
643 05:01:15.632255 B1:e0f83180
644 05:01:15.632734
645 05:01:15.633172 TE: 58150
646 05:01:15.633606
647 05:01:15.643424 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
648 05:01:15.644344
649 05:01:15.645182 Board ID = 1
650 05:01:15.645930 Set A53 clk to 24M
651 05:01:15.646763 Set A73 clk to 24M
652 05:01:15.649083 Set clk81 to 24M
653 05:01:15.649975 A53 clk: 1200 MHz
654 05:01:15.650718 A73 clk: 1200 MHz
655 05:01:15.652574 CLK81: 166.6M
656 05:01:15.653455 smccc: 00012aac
657 05:01:15.658212 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
658 05:01:15.663744 board id: 1
659 05:01:15.668820 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
660 05:01:15.679392 fw parse done
661 05:01:15.685385 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
662 05:01:15.727806 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
663 05:01:15.738689 PIEI prepare done
664 05:01:15.739187 fastboot data load
665 05:01:15.739632 fastboot data verify
666 05:01:15.744312 verify result: 266
667 05:01:15.749888 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
668 05:01:15.750374 LPDDR4 probe
669 05:01:15.750815 ddr clk to 1584MHz
670 05:01:15.757886 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
671 05:01:15.795213
672 05:01:15.796293 dmc_version 0001
673 05:01:15.802352 Check phy result
674 05:01:15.807842 INFO : End of CA training
675 05:01:15.808817 INFO : End of initialization
676 05:01:15.813378 INFO : Training has run successfully!
677 05:01:15.814322 Check phy result
678 05:01:15.818904 INFO : End of initialization
679 05:01:15.819459 INFO : End of read enable training
680 05:01:15.824550 INFO : End of fine write leveling
681 05:01:15.830151 INFO : End of Write leveling coarse delay
682 05:01:15.830684 INFO : Training has run successfully!
683 05:01:15.831165 Check phy result
684 05:01:15.835731 INFO : End of initialization
685 05:01:15.836287 INFO : End of read dq deskew training
686 05:01:15.841355 INFO : End of MPR read delay center optimization
687 05:01:15.846911 INFO : End of write delay center optimization
688 05:01:15.852494 INFO : End of read delay center optimization
689 05:01:15.853022 INFO : End of max read latency training
690 05:01:15.858120 INFO : Training has run successfully!
691 05:01:15.858640 1D training succeed
692 05:01:15.867285 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
693 05:01:15.914897 Check phy result
694 05:01:15.915508 INFO : End of initialization
695 05:01:15.936566 INFO : End of 2D read delay Voltage center optimization
696 05:01:15.956834 INFO : End of 2D read delay Voltage center optimization
697 05:01:16.008885 INFO : End of 2D write delay Voltage center optimization
698 05:01:16.058207 INFO : End of 2D write delay Voltage center optimization
699 05:01:16.063777 INFO : Training has run successfully!
700 05:01:16.064351
701 05:01:16.064811 channel==0
702 05:01:16.069374 RxClkDly_Margin_A0==88 ps 9
703 05:01:16.069859 TxDqDly_Margin_A0==98 ps 10
704 05:01:16.075091 RxClkDly_Margin_A1==88 ps 9
705 05:01:16.075578 TxDqDly_Margin_A1==98 ps 10
706 05:01:16.076065 TrainedVREFDQ_A0==74
707 05:01:16.080551 TrainedVREFDQ_A1==74
708 05:01:16.081050 VrefDac_Margin_A0==25
709 05:01:16.081502 DeviceVref_Margin_A0==40
710 05:01:16.086160 VrefDac_Margin_A1==25
711 05:01:16.086650 DeviceVref_Margin_A1==40
712 05:01:16.087098
713 05:01:16.087567
714 05:01:16.091768 channel==1
715 05:01:16.092302 RxClkDly_Margin_A0==98 ps 10
716 05:01:16.092754 TxDqDly_Margin_A0==98 ps 10
717 05:01:16.097412 RxClkDly_Margin_A1==88 ps 9
718 05:01:16.097903 TxDqDly_Margin_A1==88 ps 9
719 05:01:16.103090 TrainedVREFDQ_A0==77
720 05:01:16.103571 TrainedVREFDQ_A1==77
721 05:01:16.104052 VrefDac_Margin_A0==22
722 05:01:16.108541 DeviceVref_Margin_A0==37
723 05:01:16.109036 VrefDac_Margin_A1==24
724 05:01:16.114176 DeviceVref_Margin_A1==37
725 05:01:16.114693
726 05:01:16.115160 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
727 05:01:16.115620
728 05:01:16.147754 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
729 05:01:16.148334 2D training succeed
730 05:01:16.153411 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
731 05:01:16.159075 auto size-- 65535DDR cs0 size: 2048MB
732 05:01:16.159738 DDR cs1 size: 2048MB
733 05:01:16.164549 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
734 05:01:16.164840 cs0 DataBus test pass
735 05:01:16.170132 cs1 DataBus test pass
736 05:01:16.170557 cs0 AddrBus test pass
737 05:01:16.170891 cs1 AddrBus test pass
738 05:01:16.171214
739 05:01:16.175769 100bdlr_step_size ps== 420
740 05:01:16.176200 result report
741 05:01:16.181392 boot times 0Enable ddr reg access
742 05:01:16.187087 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
743 05:01:16.200877 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
744 05:01:16.774004 0.0;M3 CHK:0;cm4_sp_mode 0
745 05:01:16.774699 MVN_1=0x00000000
746 05:01:16.779606 MVN_2=0x00000000
747 05:01:16.785154 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
748 05:01:16.785509 OPS=0x10
749 05:01:16.785757 ring efuse init
750 05:01:16.785972 chipver efuse init
751 05:01:16.790775 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
752 05:01:16.796516 [0.018961 Inits done]
753 05:01:16.796863 secure task start!
754 05:01:16.797103 high task start!
755 05:01:16.801137 low task start!
756 05:01:16.801472 run into bl31
757 05:01:16.807665 NOTICE: BL31: v1.3(release):4fc40b1
758 05:01:16.815426 NOTICE: BL31: Built : 15:58:17, May 22 2019
759 05:01:16.815777 NOTICE: BL31: G12A normal boot!
760 05:01:16.840962 NOTICE: BL31: BL33 decompress pass
761 05:01:16.846593 ERROR: Error initializing runtime service opteed_fast
762 05:01:18.079511
763 05:01:18.079947
764 05:01:18.087695 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
765 05:01:18.088044
766 05:01:18.088273 Model: Libre Computer AML-A311D-CC Alta
767 05:01:18.296121 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
768 05:01:18.319526 DRAM: 2 GiB (effective 3.8 GiB)
769 05:01:18.462541 Core: 408 devices, 31 uclasses, devicetree: separate
770 05:01:18.468494 WDT: Not starting watchdog@f0d0
771 05:01:18.500864 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
772 05:01:18.513130 Loading Environment from FAT... Card did not respond to voltage select! : -110
773 05:01:18.518076 ** Bad device specification mmc 0 **
774 05:01:18.528460 Card did not respond to voltage select! : -110
775 05:01:18.536108 ** Bad device specification mmc 0 **
776 05:01:18.536476 Couldn't find partition mmc 0
777 05:01:18.544482 Card did not respond to voltage select! : -110
778 05:01:18.549980 ** Bad device specification mmc 0 **
779 05:01:18.550481 Couldn't find partition mmc 0
780 05:01:18.555049 Error: could not access storage.
781 05:01:18.897581 Net: eth0: ethernet@ff3f0000
782 05:01:18.898000 starting USB...
783 05:01:19.149228 Bus usb@ff500000: Register 3000140 NbrPorts 3
784 05:01:19.149640 Starting the controller
785 05:01:19.156291 USB XHCI 1.10
786 05:01:21.319512 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
787 05:01:21.320271 bl2_stage_init 0x01
788 05:01:21.320754 bl2_stage_init 0x81
789 05:01:21.325196 hw id: 0x0000 - pwm id 0x01
790 05:01:21.325758 bl2_stage_init 0xc1
791 05:01:21.326224 bl2_stage_init 0x02
792 05:01:21.326675
793 05:01:21.330784 L0:00000000
794 05:01:21.331319 L1:20000703
795 05:01:21.331775 L2:00008067
796 05:01:21.332256 L3:14000000
797 05:01:21.333695 B2:00402000
798 05:01:21.334216 B1:e0f83180
799 05:01:21.334665
800 05:01:21.335114 TE: 58124
801 05:01:21.335558
802 05:01:21.344768 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
803 05:01:21.345326
804 05:01:21.345786 Board ID = 1
805 05:01:21.346231 Set A53 clk to 24M
806 05:01:21.346670 Set A73 clk to 24M
807 05:01:21.350424 Set clk81 to 24M
808 05:01:21.350953 A53 clk: 1200 MHz
809 05:01:21.351401 A73 clk: 1200 MHz
810 05:01:21.356044 CLK81: 166.6M
811 05:01:21.356572 smccc: 00012a92
812 05:01:21.361669 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
813 05:01:21.362268 board id: 1
814 05:01:21.370410 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
815 05:01:21.380912 fw parse done
816 05:01:21.386734 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
817 05:01:21.429363 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
818 05:01:21.440274 PIEI prepare done
819 05:01:21.440870 fastboot data load
820 05:01:21.441354 fastboot data verify
821 05:01:21.445967 verify result: 266
822 05:01:21.451506 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
823 05:01:21.452128 LPDDR4 probe
824 05:01:21.452620 ddr clk to 1584MHz
825 05:01:21.459510 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
826 05:01:21.496842
827 05:01:21.497497 dmc_version 0001
828 05:01:21.503563 Check phy result
829 05:01:21.509394 INFO : End of CA training
830 05:01:21.509975 INFO : End of initialization
831 05:01:21.515000 INFO : Training has run successfully!
832 05:01:21.515457 Check phy result
833 05:01:21.520516 INFO : End of initialization
834 05:01:21.520834 INFO : End of read enable training
835 05:01:21.526122 INFO : End of fine write leveling
836 05:01:21.531695 INFO : End of Write leveling coarse delay
837 05:01:21.532194 INFO : Training has run successfully!
838 05:01:21.532482 Check phy result
839 05:01:21.537348 INFO : End of initialization
840 05:01:21.537998 INFO : End of read dq deskew training
841 05:01:21.543024 INFO : End of MPR read delay center optimization
842 05:01:21.548552 INFO : End of write delay center optimization
843 05:01:21.554202 INFO : End of read delay center optimization
844 05:01:21.554832 INFO : End of max read latency training
845 05:01:21.559805 INFO : Training has run successfully!
846 05:01:21.560442 1D training succeed
847 05:01:21.568970 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
848 05:01:21.616579 Check phy result
849 05:01:21.617231 INFO : End of initialization
850 05:01:21.639170 INFO : End of 2D read delay Voltage center optimization
851 05:01:21.659442 INFO : End of 2D read delay Voltage center optimization
852 05:01:21.711501 INFO : End of 2D write delay Voltage center optimization
853 05:01:21.760832 INFO : End of 2D write delay Voltage center optimization
854 05:01:21.766405 INFO : Training has run successfully!
855 05:01:21.767007
856 05:01:21.767493 channel==0
857 05:01:21.772120 RxClkDly_Margin_A0==88 ps 9
858 05:01:21.772693 TxDqDly_Margin_A0==98 ps 10
859 05:01:21.775283 RxClkDly_Margin_A1==88 ps 9
860 05:01:21.775846 TxDqDly_Margin_A1==98 ps 10
861 05:01:21.780895 TrainedVREFDQ_A0==74
862 05:01:21.781499 TrainedVREFDQ_A1==74
863 05:01:21.786449 VrefDac_Margin_A0==25
864 05:01:21.787053 DeviceVref_Margin_A0==40
865 05:01:21.787496 VrefDac_Margin_A1==25
866 05:01:21.792104 DeviceVref_Margin_A1==40
867 05:01:21.792657
868 05:01:21.793103
869 05:01:21.793533 channel==1
870 05:01:21.793959 RxClkDly_Margin_A0==98 ps 10
871 05:01:21.797625 TxDqDly_Margin_A0==98 ps 10
872 05:01:21.798188 RxClkDly_Margin_A1==98 ps 10
873 05:01:21.803208 TxDqDly_Margin_A1==98 ps 10
874 05:01:21.803754 TrainedVREFDQ_A0==77
875 05:01:21.804240 TrainedVREFDQ_A1==77
876 05:01:21.808829 VrefDac_Margin_A0==22
877 05:01:21.809384 DeviceVref_Margin_A0==37
878 05:01:21.814378 VrefDac_Margin_A1==22
879 05:01:21.814925 DeviceVref_Margin_A1==37
880 05:01:21.815363
881 05:01:21.820056 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
882 05:01:21.820602
883 05:01:21.848031 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
884 05:01:21.853545 2D training succeed
885 05:01:21.859211 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
886 05:01:21.859764 auto size-- 65535DDR cs0 size: 2048MB
887 05:01:21.864771 DDR cs1 size: 2048MB
888 05:01:21.865316 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
889 05:01:21.870353 cs0 DataBus test pass
890 05:01:21.870893 cs1 DataBus test pass
891 05:01:21.871325 cs0 AddrBus test pass
892 05:01:21.876064 cs1 AddrBus test pass
893 05:01:21.876610
894 05:01:21.877050 100bdlr_step_size ps== 420
895 05:01:21.877488 result report
896 05:01:21.881564 boot times 0Enable ddr reg access
897 05:01:21.889478 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
898 05:01:21.902929 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
899 05:01:22.476553 0.0;M3 CHK:0;cm4_sp_mode 0
900 05:01:22.477216 MVN_1=0x00000000
901 05:01:22.482142 MVN_2=0x00000000
902 05:01:22.487953 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
903 05:01:22.488564 OPS=0x10
904 05:01:22.489036 ring efuse init
905 05:01:22.489493 chipver efuse init
906 05:01:22.493476 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
907 05:01:22.499110 [0.018961 Inits done]
908 05:01:22.499669 secure task start!
909 05:01:22.500196 high task start!
910 05:01:22.503813 low task start!
911 05:01:22.504400 run into bl31
912 05:01:22.510379 NOTICE: BL31: v1.3(release):4fc40b1
913 05:01:22.518276 NOTICE: BL31: Built : 15:58:17, May 22 2019
914 05:01:22.518840 NOTICE: BL31: G12A normal boot!
915 05:01:22.543458 NOTICE: BL31: BL33 decompress pass
916 05:01:22.549298 ERROR: Error initializing runtime service opteed_fast
917 05:01:23.782203
918 05:01:23.782881
919 05:01:23.790533 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
920 05:01:23.791104
921 05:01:23.791579 Model: Libre Computer AML-A311D-CC Alta
922 05:01:23.998822 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
923 05:01:24.022176 DRAM: 2 GiB (effective 3.8 GiB)
924 05:01:24.165142 Core: 408 devices, 31 uclasses, devicetree: separate
925 05:01:24.171004 WDT: Not starting watchdog@f0d0
926 05:01:24.203259 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
927 05:01:24.215756 Loading Environment from FAT... Card did not respond to voltage select! : -110
928 05:01:24.220713 ** Bad device specification mmc 0 **
929 05:01:24.231100 Card did not respond to voltage select! : -110
930 05:01:24.238786 ** Bad device specification mmc 0 **
931 05:01:24.239119 Couldn't find partition mmc 0
932 05:01:24.247074 Card did not respond to voltage select! : -110
933 05:01:24.252480 ** Bad device specification mmc 0 **
934 05:01:24.252912 Couldn't find partition mmc 0
935 05:01:24.257681 Error: could not access storage.
936 05:01:24.600300 Net: eth0: ethernet@ff3f0000
937 05:01:24.600723 starting USB...
938 05:01:24.852070 Bus usb@ff500000: Register 3000140 NbrPorts 3
939 05:01:24.852739 Starting the controller
940 05:01:24.859028 USB XHCI 1.10
941 05:01:26.413097 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
942 05:01:26.421559 scanning usb for storage devices... 0 Storage Device(s) found
944 05:01:26.473460 Hit any key to stop autoboot: 1
945 05:01:26.474820 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
946 05:01:26.475508 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
947 05:01:26.476094 Setting prompt string to ['=>']
948 05:01:26.476642 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
949 05:01:26.488939 0
950 05:01:26.489958 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
951 05:01:26.490567 Sending with 10 millisecond of delay
953 05:01:27.626256 => setenv autoload no
954 05:01:27.637553 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
955 05:01:27.640273 setenv autoload no
956 05:01:27.640803 Sending with 10 millisecond of delay
958 05:01:29.440805 => setenv initrd_high 0xffffffff
959 05:01:29.452218 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
960 05:01:29.453315 setenv initrd_high 0xffffffff
961 05:01:29.454257 Sending with 10 millisecond of delay
963 05:01:31.072673 => setenv fdt_high 0xffffffff
964 05:01:31.083301 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
965 05:01:31.084024 setenv fdt_high 0xffffffff
966 05:01:31.084551 Sending with 10 millisecond of delay
968 05:01:31.376405 => dhcp
969 05:01:31.386984 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
970 05:01:31.387554 dhcp
971 05:01:31.387800 Speed: 1000, full duplex
972 05:01:31.388050 BOOTP broadcast 1
973 05:01:31.395520 DHCP client bound to address 192.168.6.27 (9 ms)
974 05:01:31.396121 Sending with 10 millisecond of delay
976 05:01:33.074427 => setenv serverip 192.168.6.2
977 05:01:33.085273 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
978 05:01:33.086238 setenv serverip 192.168.6.2
979 05:01:33.086983 Sending with 10 millisecond of delay
981 05:01:36.816789 => tftpboot 0x01080000 927130/tftp-deploy-nl6bwosl/kernel/uImage
982 05:01:36.827848 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
983 05:01:36.829049 tftpboot 0x01080000 927130/tftp-deploy-nl6bwosl/kernel/uImage
984 05:01:36.829671 Speed: 1000, full duplex
985 05:01:36.830230 Using ethernet@ff3f0000 device
986 05:01:36.830900 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
987 05:01:36.836103 Filename '927130/tftp-deploy-nl6bwosl/kernel/uImage'.
988 05:01:36.839973 Load address: 0x1080000
989 05:01:41.053485 Loading: *################################################## 63.4 MiB
990 05:01:41.054170 15 MiB/s
991 05:01:41.054670 done
992 05:01:41.057869 Bytes transferred = 66443840 (3f5da40 hex)
993 05:01:41.058733 Sending with 10 millisecond of delay
995 05:01:45.747080 => tftpboot 0x08000000 927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot
996 05:01:45.757929 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
997 05:01:45.758850 tftpboot 0x08000000 927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot
998 05:01:45.759339 Speed: 1000, full duplex
999 05:01:45.759801 Using ethernet@ff3f0000 device
1000 05:01:45.760890 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1001 05:01:45.769442 Filename '927130/tftp-deploy-nl6bwosl/ramdisk/ramdisk.cpio.gz.uboot'.
1002 05:01:45.770005 Load address: 0x8000000
1003 05:01:47.795390 Loading: *################################################# UDP wrong checksum 00000007 0000a8af
1004 05:01:52.795798 T UDP wrong checksum 00000007 0000a8af
1005 05:02:02.798878 T T UDP wrong checksum 00000007 0000a8af
1006 05:02:22.800279 T T T UDP wrong checksum 00000007 0000a8af
1007 05:02:38.202666 T T T T UDP wrong checksum 000000ff 00008fbf
1008 05:02:38.252708 UDP wrong checksum 000000ff 000014b2
1009 05:02:39.129605 UDP wrong checksum 000000ff 00000f4b
1010 05:02:39.140498 UDP wrong checksum 000000ff 0000a33d
1011 05:02:42.808022
1012 05:02:42.808682 Retry count exceeded; starting again
1014 05:02:42.810267 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1017 05:02:42.812339 end: 2.4 uboot-commands (duration 00:01:48) [common]
1019 05:02:42.813844 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1021 05:02:42.814985 end: 2 uboot-action (duration 00:01:48) [common]
1023 05:02:42.816731 Cleaning after the job
1024 05:02:42.817358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/ramdisk
1025 05:02:42.818916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/kernel
1026 05:02:42.829990 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/dtb
1027 05:02:42.831307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/nfsrootfs
1028 05:02:42.892369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927130/tftp-deploy-nl6bwosl/modules
1029 05:02:42.900868 start: 4.1 power-off (timeout 00:00:30) [common]
1030 05:02:42.901478 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1031 05:02:42.935350 >> OK - accepted request
1032 05:02:42.937343 Returned 0 in 0 seconds
1033 05:02:43.038060 end: 4.1 power-off (duration 00:00:00) [common]
1035 05:02:43.039028 start: 4.2 read-feedback (timeout 00:10:00) [common]
1036 05:02:43.039683 Listened to connection for namespace 'common' for up to 1s
1037 05:02:44.040326 Finalising connection for namespace 'common'
1038 05:02:44.041082 Disconnecting from shell: Finalise
1039 05:02:44.041650 =>
1040 05:02:44.142730 end: 4.2 read-feedback (duration 00:00:01) [common]
1041 05:02:44.143457 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927130
1042 05:02:45.832867 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927130
1043 05:02:45.833486 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.