Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:02:27.710282 lava-dispatcher, installed at version: 2024.01
2 05:02:27.711129 start: 0 validate
3 05:02:27.711635 Start time: 2024-11-02 05:02:27.711602+00:00 (UTC)
4 05:02:27.712351 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:02:27.713063 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:02:27.767095 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:02:27.768121 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 05:02:27.812355 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:02:27.813174 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:02:27.845668 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:02:27.846186 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:02:27.883746 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:02:27.884312 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 05:02:27.930674 validate duration: 0.22
16 05:02:27.931643 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:02:27.932012 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:02:27.932320 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:02:27.933222 Not decompressing ramdisk as can be used compressed.
20 05:02:27.934236 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 05:02:27.934849 saving as /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/ramdisk/initrd.cpio.gz
22 05:02:27.935482 total size: 5628182 (5 MB)
23 05:02:27.976953 progress 0 % (0 MB)
24 05:02:27.981365 progress 5 % (0 MB)
25 05:02:27.985944 progress 10 % (0 MB)
26 05:02:27.990189 progress 15 % (0 MB)
27 05:02:27.994759 progress 20 % (1 MB)
28 05:02:27.998764 progress 25 % (1 MB)
29 05:02:28.003056 progress 30 % (1 MB)
30 05:02:28.007375 progress 35 % (1 MB)
31 05:02:28.011211 progress 40 % (2 MB)
32 05:02:28.015407 progress 45 % (2 MB)
33 05:02:28.019258 progress 50 % (2 MB)
34 05:02:28.023474 progress 55 % (2 MB)
35 05:02:28.027740 progress 60 % (3 MB)
36 05:02:28.031604 progress 65 % (3 MB)
37 05:02:28.035914 progress 70 % (3 MB)
38 05:02:28.039769 progress 75 % (4 MB)
39 05:02:28.044135 progress 80 % (4 MB)
40 05:02:28.047891 progress 85 % (4 MB)
41 05:02:28.051931 progress 90 % (4 MB)
42 05:02:28.055870 progress 95 % (5 MB)
43 05:02:28.059320 progress 100 % (5 MB)
44 05:02:28.060071 5 MB downloaded in 0.12 s (43.08 MB/s)
45 05:02:28.060656 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:02:28.061560 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:02:28.061859 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:02:28.062135 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:02:28.062753 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 05:02:28.063065 saving as /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/kernel/Image
52 05:02:28.063292 total size: 66443776 (63 MB)
53 05:02:28.063523 No compression specified
54 05:02:28.100500 progress 0 % (0 MB)
55 05:02:28.143822 progress 5 % (3 MB)
56 05:02:28.184060 progress 10 % (6 MB)
57 05:02:28.223909 progress 15 % (9 MB)
58 05:02:28.263552 progress 20 % (12 MB)
59 05:02:28.302732 progress 25 % (15 MB)
60 05:02:28.342948 progress 30 % (19 MB)
61 05:02:28.382541 progress 35 % (22 MB)
62 05:02:28.422239 progress 40 % (25 MB)
63 05:02:28.461189 progress 45 % (28 MB)
64 05:02:28.500716 progress 50 % (31 MB)
65 05:02:28.541148 progress 55 % (34 MB)
66 05:02:28.580745 progress 60 % (38 MB)
67 05:02:28.619906 progress 65 % (41 MB)
68 05:02:28.659075 progress 70 % (44 MB)
69 05:02:28.698257 progress 75 % (47 MB)
70 05:02:28.738002 progress 80 % (50 MB)
71 05:02:28.777290 progress 85 % (53 MB)
72 05:02:28.816939 progress 90 % (57 MB)
73 05:02:28.856664 progress 95 % (60 MB)
74 05:02:28.895267 progress 100 % (63 MB)
75 05:02:28.896033 63 MB downloaded in 0.83 s (76.09 MB/s)
76 05:02:28.896534 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:02:28.897354 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:02:28.897629 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:02:28.897892 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:02:28.898462 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 05:02:28.898752 saving as /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 05:02:28.898960 total size: 53209 (0 MB)
84 05:02:28.899169 No compression specified
85 05:02:28.938526 progress 61 % (0 MB)
86 05:02:28.939381 progress 100 % (0 MB)
87 05:02:28.939918 0 MB downloaded in 0.04 s (1.24 MB/s)
88 05:02:28.940409 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:02:28.941219 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:02:28.941481 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:02:28.941742 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:02:28.942212 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 05:02:28.942462 saving as /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/nfsrootfs/full.rootfs.tar
95 05:02:28.942667 total size: 107552908 (102 MB)
96 05:02:28.942878 Using unxz to decompress xz
97 05:02:28.975646 progress 0 % (0 MB)
98 05:02:29.623747 progress 5 % (5 MB)
99 05:02:30.349604 progress 10 % (10 MB)
100 05:02:31.073081 progress 15 % (15 MB)
101 05:02:31.832493 progress 20 % (20 MB)
102 05:02:32.405924 progress 25 % (25 MB)
103 05:02:33.029315 progress 30 % (30 MB)
104 05:02:33.766051 progress 35 % (35 MB)
105 05:02:34.125598 progress 40 % (41 MB)
106 05:02:34.556045 progress 45 % (46 MB)
107 05:02:35.246609 progress 50 % (51 MB)
108 05:02:35.942057 progress 55 % (56 MB)
109 05:02:36.700330 progress 60 % (61 MB)
110 05:02:37.475624 progress 65 % (66 MB)
111 05:02:38.213032 progress 70 % (71 MB)
112 05:02:38.976492 progress 75 % (76 MB)
113 05:02:39.651181 progress 80 % (82 MB)
114 05:02:40.356018 progress 85 % (87 MB)
115 05:02:41.089961 progress 90 % (92 MB)
116 05:02:41.808844 progress 95 % (97 MB)
117 05:02:42.545407 progress 100 % (102 MB)
118 05:02:42.558012 102 MB downloaded in 13.62 s (7.53 MB/s)
119 05:02:42.558826 end: 1.4.1 http-download (duration 00:00:14) [common]
121 05:02:42.560055 end: 1.4 download-retry (duration 00:00:14) [common]
122 05:02:42.560759 start: 1.5 download-retry (timeout 00:09:45) [common]
123 05:02:42.561673 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 05:02:42.562855 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 05:02:42.563456 saving as /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/modules/modules.tar
126 05:02:42.564013 total size: 16116020 (15 MB)
127 05:02:42.564564 Using unxz to decompress xz
128 05:02:42.613434 progress 0 % (0 MB)
129 05:02:42.715405 progress 5 % (0 MB)
130 05:02:42.837026 progress 10 % (1 MB)
131 05:02:42.953704 progress 15 % (2 MB)
132 05:02:43.084295 progress 20 % (3 MB)
133 05:02:43.215339 progress 25 % (3 MB)
134 05:02:43.326279 progress 30 % (4 MB)
135 05:02:43.438819 progress 35 % (5 MB)
136 05:02:43.547301 progress 40 % (6 MB)
137 05:02:43.655254 progress 45 % (6 MB)
138 05:02:43.768657 progress 50 % (7 MB)
139 05:02:43.882146 progress 55 % (8 MB)
140 05:02:44.002516 progress 60 % (9 MB)
141 05:02:44.114826 progress 65 % (10 MB)
142 05:02:44.227605 progress 70 % (10 MB)
143 05:02:44.355181 progress 75 % (11 MB)
144 05:02:44.494753 progress 80 % (12 MB)
145 05:02:44.631954 progress 85 % (13 MB)
146 05:02:44.752630 progress 90 % (13 MB)
147 05:02:44.857601 progress 95 % (14 MB)
148 05:02:44.971193 progress 100 % (15 MB)
149 05:02:44.985739 15 MB downloaded in 2.42 s (6.35 MB/s)
150 05:02:44.986454 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:02:44.987467 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:02:44.987800 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 05:02:44.988372 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 05:02:56.288229 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927127/extract-nfsrootfs-yfk97z4r
156 05:02:56.288842 end: 1.6.1 extract-nfsrootfs (duration 00:00:11) [common]
157 05:02:56.289129 start: 1.6.2 lava-overlay (timeout 00:09:32) [common]
158 05:02:56.289741 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve
159 05:02:56.290181 makedir: /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin
160 05:02:56.290516 makedir: /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/tests
161 05:02:56.290880 makedir: /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/results
162 05:02:56.291225 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-add-keys
163 05:02:56.291768 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-add-sources
164 05:02:56.292349 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-background-process-start
165 05:02:56.292875 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-background-process-stop
166 05:02:56.293420 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-common-functions
167 05:02:56.294016 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-echo-ipv4
168 05:02:56.294532 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-install-packages
169 05:02:56.295026 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-installed-packages
170 05:02:56.295523 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-os-build
171 05:02:56.296107 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-probe-channel
172 05:02:56.296628 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-probe-ip
173 05:02:56.297111 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-target-ip
174 05:02:56.297676 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-target-mac
175 05:02:56.298176 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-target-storage
176 05:02:56.298668 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-case
177 05:02:56.299154 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-event
178 05:02:56.299631 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-feedback
179 05:02:56.300134 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-raise
180 05:02:56.300620 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-reference
181 05:02:56.301099 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-runner
182 05:02:56.301582 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-set
183 05:02:56.302058 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-test-shell
184 05:02:56.302545 Updating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-install-packages (oe)
185 05:02:56.303080 Updating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/bin/lava-installed-packages (oe)
186 05:02:56.303572 Creating /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/environment
187 05:02:56.304022 LAVA metadata
188 05:02:56.304293 - LAVA_JOB_ID=927127
189 05:02:56.304510 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:02:56.304878 start: 1.6.2.1 ssh-authorize (timeout 00:09:32) [common]
191 05:02:56.305850 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:02:56.306166 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:32) [common]
193 05:02:56.306376 skipped lava-vland-overlay
194 05:02:56.306620 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:02:56.306874 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:32) [common]
196 05:02:56.307092 skipped lava-multinode-overlay
197 05:02:56.307334 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:02:56.307583 start: 1.6.2.4 test-definition (timeout 00:09:32) [common]
199 05:02:56.307829 Loading test definitions
200 05:02:56.308142 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:32) [common]
201 05:02:56.308367 Using /lava-927127 at stage 0
202 05:02:56.309623 uuid=927127_1.6.2.4.1 testdef=None
203 05:02:56.309939 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:02:56.310202 start: 1.6.2.4.2 test-overlay (timeout 00:09:32) [common]
205 05:02:56.312022 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:02:56.312815 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:32) [common]
208 05:02:56.315120 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:02:56.315939 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:32) [common]
211 05:02:56.318164 runner path: /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/0/tests/0_dmesg test_uuid 927127_1.6.2.4.1
212 05:02:56.318724 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:02:56.319475 Creating lava-test-runner.conf files
215 05:02:56.319674 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927127/lava-overlay-78pzmmve/lava-927127/0 for stage 0
216 05:02:56.320082 - 0_dmesg
217 05:02:56.320445 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:02:56.320718 start: 1.6.2.5 compress-overlay (timeout 00:09:32) [common]
219 05:02:56.342775 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:02:56.343178 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:32) [common]
221 05:02:56.343440 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:02:56.343708 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:02:56.343966 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
224 05:02:56.996225 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:02:56.996698 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
226 05:02:56.996946 extracting modules file /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927127/extract-nfsrootfs-yfk97z4r
227 05:02:58.577972 extracting modules file /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927127/extract-overlay-ramdisk-n3nlv1t3/ramdisk
228 05:03:00.299805 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:03:00.300332 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
230 05:03:00.300617 [common] Applying overlay to NFS
231 05:03:00.300832 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927127/compress-overlay-77i7owlj/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927127/extract-nfsrootfs-yfk97z4r
232 05:03:00.332076 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:03:00.332579 start: 1.6.6 prepare-kernel (timeout 00:09:28) [common]
234 05:03:00.332867 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:28) [common]
235 05:03:00.333109 Converting downloaded kernel to a uImage
236 05:03:00.333592 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/kernel/Image /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/kernel/uImage
237 05:03:01.911741 output: Image Name:
238 05:03:01.912194 output: Created: Sat Nov 2 05:03:00 2024
239 05:03:01.912414 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:03:01.912620 output: Data Size: 66443776 Bytes = 64886.50 KiB = 63.37 MiB
241 05:03:01.912823 output: Load Address: 01080000
242 05:03:01.913026 output: Entry Point: 01080000
243 05:03:01.913226 output:
244 05:03:01.913557 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
245 05:03:01.913821 end: 1.6.6 prepare-kernel (duration 00:00:02) [common]
246 05:03:01.914090 start: 1.6.7 configure-preseed-file (timeout 00:09:26) [common]
247 05:03:01.914343 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:03:01.914598 start: 1.6.8 compress-ramdisk (timeout 00:09:26) [common]
249 05:03:01.914852 Building ramdisk /var/lib/lava/dispatcher/tmp/927127/extract-overlay-ramdisk-n3nlv1t3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927127/extract-overlay-ramdisk-n3nlv1t3/ramdisk
250 05:03:05.026689 >> 239643 blocks
251 05:03:15.247319 Adding RAMdisk u-boot header.
252 05:03:15.248113 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927127/extract-overlay-ramdisk-n3nlv1t3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927127/extract-overlay-ramdisk-n3nlv1t3/ramdisk.cpio.gz.uboot
253 05:03:15.579495 output: Image Name:
254 05:03:15.579884 output: Created: Sat Nov 2 05:03:15 2024
255 05:03:15.580293 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:03:15.580708 output: Data Size: 30948989 Bytes = 30223.62 KiB = 29.52 MiB
257 05:03:15.581129 output: Load Address: 00000000
258 05:03:15.581527 output: Entry Point: 00000000
259 05:03:15.581921 output:
260 05:03:15.582996 rename /var/lib/lava/dispatcher/tmp/927127/extract-overlay-ramdisk-n3nlv1t3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot
261 05:03:15.583711 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 05:03:15.584287 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 05:03:15.584814 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:12) [common]
264 05:03:15.585271 No LXC device requested
265 05:03:15.585766 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:03:15.586270 start: 1.8 deploy-device-env (timeout 00:09:12) [common]
267 05:03:15.586758 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:03:15.587166 Checking files for TFTP limit of 4294967296 bytes.
269 05:03:15.589833 end: 1 tftp-deploy (duration 00:00:48) [common]
270 05:03:15.590404 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:03:15.590919 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:03:15.591411 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:03:15.591907 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:03:15.592471 Using kernel file from prepare-kernel: 927127/tftp-deploy-k5u6njaf/kernel/uImage
275 05:03:15.593094 substitutions:
276 05:03:15.593501 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:03:15.593902 - {DTB_ADDR}: 0x01070000
278 05:03:15.594301 - {DTB}: 927127/tftp-deploy-k5u6njaf/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 05:03:15.594697 - {INITRD}: 927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot
280 05:03:15.595091 - {KERNEL_ADDR}: 0x01080000
281 05:03:15.595486 - {KERNEL}: 927127/tftp-deploy-k5u6njaf/kernel/uImage
282 05:03:15.595877 - {LAVA_MAC}: None
283 05:03:15.596339 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927127/extract-nfsrootfs-yfk97z4r
284 05:03:15.596737 - {NFS_SERVER_IP}: 192.168.6.2
285 05:03:15.597128 - {PRESEED_CONFIG}: None
286 05:03:15.597516 - {PRESEED_LOCAL}: None
287 05:03:15.597903 - {RAMDISK_ADDR}: 0x08000000
288 05:03:15.598287 - {RAMDISK}: 927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot
289 05:03:15.598671 - {ROOT_PART}: None
290 05:03:15.599057 - {ROOT}: None
291 05:03:15.599445 - {SERVER_IP}: 192.168.6.2
292 05:03:15.599827 - {TEE_ADDR}: 0x83000000
293 05:03:15.600269 - {TEE}: None
294 05:03:15.600662 Parsed boot commands:
295 05:03:15.601037 - setenv autoload no
296 05:03:15.601421 - setenv initrd_high 0xffffffff
297 05:03:15.601804 - setenv fdt_high 0xffffffff
298 05:03:15.602186 - dhcp
299 05:03:15.602568 - setenv serverip 192.168.6.2
300 05:03:15.602951 - tftpboot 0x01080000 927127/tftp-deploy-k5u6njaf/kernel/uImage
301 05:03:15.603335 - tftpboot 0x08000000 927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot
302 05:03:15.603718 - tftpboot 0x01070000 927127/tftp-deploy-k5u6njaf/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 05:03:15.604141 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927127/extract-nfsrootfs-yfk97z4r,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:03:15.604543 - bootm 0x01080000 0x08000000 0x01070000
305 05:03:15.605033 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:03:15.606488 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:03:15.606901 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 05:03:15.620875 Setting prompt string to ['lava-test: # ']
310 05:03:15.622370 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:03:15.622949 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:03:15.623484 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:03:15.624037 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:03:15.625170 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 05:03:15.660926 >> OK - accepted request
316 05:03:15.663054 Returned 0 in 0 seconds
317 05:03:15.764185 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:03:15.765736 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:03:15.766286 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:03:15.766794 Setting prompt string to ['Hit any key to stop autoboot']
322 05:03:15.767244 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:03:15.768786 Trying 192.168.56.21...
324 05:03:15.769263 Connected to conserv1.
325 05:03:15.769688 Escape character is '^]'.
326 05:03:15.770113
327 05:03:15.770544 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:03:15.770977
329 05:03:22.887719 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 05:03:22.888338 bl2_stage_init 0x01
331 05:03:22.888758 bl2_stage_init 0x81
332 05:03:22.893289 hw id: 0x0000 - pwm id 0x01
333 05:03:22.893723 bl2_stage_init 0xc1
334 05:03:22.894133 bl2_stage_init 0x02
335 05:03:22.894531
336 05:03:22.898785 L0:00000000
337 05:03:22.899218 L1:00000703
338 05:03:22.899625 L2:00008067
339 05:03:22.900049 L3:15000000
340 05:03:22.900447 S1:00000000
341 05:03:22.904378 B2:20282000
342 05:03:22.904847 B1:a0f83180
343 05:03:22.905245
344 05:03:22.905644 TE: 71611
345 05:03:22.906038
346 05:03:22.910050 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 05:03:22.910482
348 05:03:22.915725 Board ID = 1
349 05:03:22.916166 Set cpu clk to 24M
350 05:03:22.916565 Set clk81 to 24M
351 05:03:22.921251 Use GP1_pll as DSU clk.
352 05:03:22.921668 DSU clk: 1200 Mhz
353 05:03:22.922062 CPU clk: 1200 MHz
354 05:03:22.922453 Set clk81 to 166.6M
355 05:03:22.932490 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 05:03:22.932963 board id: 1
357 05:03:22.938795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:03:22.949676 fw parse done
359 05:03:22.955633 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:03:22.998788 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:03:23.009882 PIEI prepare done
362 05:03:23.010320 fastboot data load
363 05:03:23.010724 fastboot data verify
364 05:03:23.015727 verify result: 266
365 05:03:23.021235 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 05:03:23.021689 LPDDR4 probe
367 05:03:23.022084 ddr clk to 1584MHz
368 05:03:23.029169 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:03:23.066147
370 05:03:23.066607 dmc_version 0001
371 05:03:23.072997 Check phy result
372 05:03:23.080202 INFO : End of CA training
373 05:03:23.080621 INFO : End of initialization
374 05:03:23.085677 INFO : Training has run successfully!
375 05:03:23.086143 Check phy result
376 05:03:23.091184 INFO : End of initialization
377 05:03:23.091607 INFO : End of read enable training
378 05:03:23.096891 INFO : End of fine write leveling
379 05:03:23.102413 INFO : End of Write leveling coarse delay
380 05:03:23.102879 INFO : Training has run successfully!
381 05:03:23.103278 Check phy result
382 05:03:23.107920 INFO : End of initialization
383 05:03:23.108380 INFO : End of read dq deskew training
384 05:03:23.113540 INFO : End of MPR read delay center optimization
385 05:03:23.119481 INFO : End of write delay center optimization
386 05:03:23.124703 INFO : End of read delay center optimization
387 05:03:23.125120 INFO : End of max read latency training
388 05:03:23.130282 INFO : Training has run successfully!
389 05:03:23.130727 1D training succeed
390 05:03:23.139520 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:03:23.187738 Check phy result
392 05:03:23.188261 INFO : End of initialization
393 05:03:23.214983 INFO : End of 2D read delay Voltage center optimization
394 05:03:23.239085 INFO : End of 2D read delay Voltage center optimization
395 05:03:23.295820 INFO : End of 2D write delay Voltage center optimization
396 05:03:23.349810 INFO : End of 2D write delay Voltage center optimization
397 05:03:23.355303 INFO : Training has run successfully!
398 05:03:23.355733
399 05:03:23.356167 channel==0
400 05:03:23.360887 RxClkDly_Margin_A0==88 ps 9
401 05:03:23.361321 TxDqDly_Margin_A0==98 ps 10
402 05:03:23.364213 RxClkDly_Margin_A1==88 ps 9
403 05:03:23.364628 TxDqDly_Margin_A1==98 ps 10
404 05:03:23.369876 TrainedVREFDQ_A0==74
405 05:03:23.370295 TrainedVREFDQ_A1==74
406 05:03:23.370692 VrefDac_Margin_A0==24
407 05:03:23.375412 DeviceVref_Margin_A0==40
408 05:03:23.375823 VrefDac_Margin_A1==23
409 05:03:23.381004 DeviceVref_Margin_A1==40
410 05:03:23.381422
411 05:03:23.381820
412 05:03:23.382224 channel==1
413 05:03:23.382650 RxClkDly_Margin_A0==78 ps 8
414 05:03:23.386638 TxDqDly_Margin_A0==98 ps 10
415 05:03:23.387090 RxClkDly_Margin_A1==78 ps 8
416 05:03:23.392213 TxDqDly_Margin_A1==78 ps 8
417 05:03:23.392648 TrainedVREFDQ_A0==78
418 05:03:23.393046 TrainedVREFDQ_A1==75
419 05:03:23.397904 VrefDac_Margin_A0==22
420 05:03:23.398325 DeviceVref_Margin_A0==36
421 05:03:23.403408 VrefDac_Margin_A1==22
422 05:03:23.403820 DeviceVref_Margin_A1==39
423 05:03:23.404256
424 05:03:23.409040 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:03:23.409455
426 05:03:23.437055 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
427 05:03:23.442638 2D training succeed
428 05:03:23.448219 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:03:23.448678 auto size-- 65535DDR cs0 size: 2048MB
430 05:03:23.453825 DDR cs1 size: 2048MB
431 05:03:23.454249 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:03:23.459505 cs0 DataBus test pass
433 05:03:23.459923 cs1 DataBus test pass
434 05:03:23.460353 cs0 AddrBus test pass
435 05:03:23.465027 cs1 AddrBus test pass
436 05:03:23.465444
437 05:03:23.465838 100bdlr_step_size ps== 471
438 05:03:23.466236 result report
439 05:03:23.470659 boot times 0Enable ddr reg access
440 05:03:23.478183 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:03:23.492046 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 05:03:24.150336 bl2z: ptr: 05129330, size: 00001e40
443 05:03:24.158976 0.0;M3 CHK:0;cm4_sp_mode 0
444 05:03:24.159449 MVN_1=0x00000000
445 05:03:24.159852 MVN_2=0x00000000
446 05:03:24.170520 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 05:03:24.171045 OPS=0x04
448 05:03:24.171462 ring efuse init
449 05:03:24.174107 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 05:03:24.177745 [0.017355 Inits done]
451 05:03:24.178180 secure task start!
452 05:03:24.178581 high task start!
453 05:03:24.183481 low task start!
454 05:03:24.183910 run into bl31
455 05:03:24.192097 NOTICE: BL31: v1.3(release):4fc40b1
456 05:03:24.199857 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 05:03:24.200330 NOTICE: BL31: G12A normal boot!
458 05:03:24.215416 NOTICE: BL31: BL33 decompress pass
459 05:03:24.224089 ERROR: Error initializing runtime service opteed_fast
460 05:03:25.567620 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 05:03:25.568274 bl2_stage_init 0x01
462 05:03:25.568713 bl2_stage_init 0x81
463 05:03:25.569114 hw id: 0x0000 - pwm id 0x01
464 05:03:25.569749 bl2_stage_init 0xc1
465 05:03:25.570214 bl2_stage_init 0x02
466 05:03:25.570633
467 05:03:25.571039 L0:00000000
468 05:03:25.571464 L1:00000703
469 05:03:25.571878 L2:00008067
470 05:03:25.572309 L3:15000000
471 05:03:25.572711 S1:00000000
472 05:03:25.573107 B2:20282000
473 05:03:25.573502 B1:a0f83180
474 05:03:25.573897
475 05:03:25.574295 TE: 69013
476 05:03:25.574688
477 05:03:25.575439 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 05:03:25.575862
479 05:03:25.576301 Board ID = 1
480 05:03:25.576705 Set cpu clk to 24M
481 05:03:25.577103 Set clk81 to 24M
482 05:03:25.577496 Use GP1_pll as DSU clk.
483 05:03:25.577891 DSU clk: 1200 Mhz
484 05:03:25.578283 CPU clk: 1200 MHz
485 05:03:25.578670 Set clk81 to 166.6M
486 05:03:25.579057 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 05:03:25.579451 board id: 1
488 05:03:25.579840 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 05:03:25.580272 fw parse done
490 05:03:25.580669 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 05:03:25.581062 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 05:03:25.581451 PIEI prepare done
493 05:03:25.581839 fastboot data load
494 05:03:25.582225 fastboot data verify
495 05:03:25.582613 verify result: 266
496 05:03:25.583000 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 05:03:25.583390 LPDDR4 probe
498 05:03:25.583778 ddr clk to 1584MHz
499 05:03:26.935764 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, s SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 05:03:26.936378 bl2_stage_init 0x01
501 05:03:26.936806 bl2_stage_init 0x81
502 05:03:26.941339 hw id: 0x0000 - pwm id 0x01
503 05:03:26.941847 bl2_stage_init 0xc1
504 05:03:26.946609 bl2_stage_init 0x02
505 05:03:26.947117
506 05:03:26.947516 L0:00000000
507 05:03:26.947905 L1:00000703
508 05:03:26.948336 L2:00008067
509 05:03:26.948726 L3:15000000
510 05:03:26.952251 S1:00000000
511 05:03:26.952723 B2:20282000
512 05:03:26.953117 B1:a0f83180
513 05:03:26.953509
514 05:03:26.953900 TE: 69190
515 05:03:26.954289
516 05:03:26.957787 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 05:03:26.958277
518 05:03:26.963434 Board ID = 1
519 05:03:26.963938 Set cpu clk to 24M
520 05:03:26.964374 Set clk81 to 24M
521 05:03:26.966726 Use GP1_pll as DSU clk.
522 05:03:26.967222 DSU clk: 1200 Mhz
523 05:03:26.972271 CPU clk: 1200 MHz
524 05:03:26.972790 Set clk81 to 166.6M
525 05:03:26.977947 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 05:03:26.978444 board id: 1
527 05:03:26.987683 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 05:03:26.998366 fw parse done
529 05:03:27.004306 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 05:03:27.047313 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 05:03:27.057868 PIEI prepare done
532 05:03:27.058355 fastboot data load
533 05:03:27.058785 fastboot data verify
534 05:03:27.063420 verify result: 266
535 05:03:27.069023 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 05:03:27.069503 LPDDR4 probe
537 05:03:27.069914 ddr clk to 1584MHz
538 05:03:27.077071 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 05:03:27.114288
540 05:03:27.114841 dmc_version 0001
541 05:03:27.121071 Check phy result
542 05:03:27.127018 INFO : End of CA training
543 05:03:27.127498 INFO : End of initialization
544 05:03:27.132467 INFO : Training has run successfully!
545 05:03:27.132983 Check phy result
546 05:03:27.138058 INFO : End of initialization
547 05:03:27.138535 INFO : End of read enable training
548 05:03:27.143744 INFO : End of fine write leveling
549 05:03:27.149276 INFO : End of Write leveling coarse delay
550 05:03:27.149747 INFO : Training has run successfully!
551 05:03:27.150164 Check phy result
552 05:03:27.155031 INFO : End of initialization
553 05:03:27.155578 INFO : End of read dq deskew training
554 05:03:27.160482 INFO : End of MPR read delay center optimization
555 05:03:27.166075 INFO : End of write delay center optimization
556 05:03:27.171652 INFO : End of read delay center optimization
557 05:03:27.172163 INFO : End of max read latency training
558 05:03:27.177253 INFO : Training has run successfully!
559 05:03:27.177738 1D training succeed
560 05:03:27.186451 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 05:03:27.234125 Check phy result
562 05:03:27.234686 INFO : End of initialization
563 05:03:27.256395 INFO : End of 2D read delay Voltage center optimization
564 05:03:27.275547 INFO : End of 2D read delay Voltage center optimization
565 05:03:27.327448 INFO : End of 2D write delay Voltage center optimization
566 05:03:27.376661 INFO : End of 2D write delay Voltage center optimization
567 05:03:27.382188 INFO : Training has run successfully!
568 05:03:27.382687
569 05:03:27.383304 channel==0
570 05:03:27.387794 RxClkDly_Margin_A0==78 ps 8
571 05:03:27.388322 TxDqDly_Margin_A0==98 ps 10
572 05:03:27.393411 RxClkDly_Margin_A1==88 ps 9
573 05:03:27.393908 TxDqDly_Margin_A1==98 ps 10
574 05:03:27.394366 TrainedVREFDQ_A0==76
575 05:03:27.399055 TrainedVREFDQ_A1==75
576 05:03:27.399560 VrefDac_Margin_A0==23
577 05:03:27.400057 DeviceVref_Margin_A0==38
578 05:03:27.404601 VrefDac_Margin_A1==23
579 05:03:27.405087 DeviceVref_Margin_A1==39
580 05:03:27.405540
581 05:03:27.406047
582 05:03:27.410189 channel==1
583 05:03:27.410668 RxClkDly_Margin_A0==78 ps 8
584 05:03:27.411122 TxDqDly_Margin_A0==98 ps 10
585 05:03:27.415787 RxClkDly_Margin_A1==78 ps 8
586 05:03:27.416296 TxDqDly_Margin_A1==88 ps 9
587 05:03:27.421385 TrainedVREFDQ_A0==78
588 05:03:27.421874 TrainedVREFDQ_A1==75
589 05:03:27.422321 VrefDac_Margin_A0==22
590 05:03:27.427081 DeviceVref_Margin_A0==36
591 05:03:27.427575 VrefDac_Margin_A1==22
592 05:03:27.432589 DeviceVref_Margin_A1==39
593 05:03:27.433075
594 05:03:27.433493 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 05:03:27.433899
596 05:03:27.466198 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
597 05:03:27.466766 2D training succeed
598 05:03:27.471790 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 05:03:27.477369 auto size-- 65535DDR cs0 size: 2048MB
600 05:03:27.477820 DDR cs1 size: 2048MB
601 05:03:27.483108 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 05:03:27.483620 cs0 DataBus test pass
603 05:03:27.488609 cs1 DataBus test pass
604 05:03:27.489096 cs0 AddrBus test pass
605 05:03:27.489511 cs1 AddrBus test pass
606 05:03:27.489916
607 05:03:27.494259 100bdlr_step_size ps== 478
608 05:03:27.494787 result report
609 05:03:27.499805 boot times 0Enable ddr reg access
610 05:03:27.505118 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 05:03:27.518861 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 05:03:28.174099 bl2z: ptr: 05129330, size: 00001e40
613 05:03:28.181468 0.0;M3 CHK:0;cm4_sp_mode 0
614 05:03:28.182063 MVN_1=0x00000000
615 05:03:28.182540 MVN_2=0x00000000
616 05:03:28.192853 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 05:03:28.193479 OPS=0x04
618 05:03:28.193919 ring efuse init
619 05:03:28.198541 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 05:03:28.199144 [0.017319 Inits done]
621 05:03:28.199600 secure task start!
622 05:03:28.206327 high task start!
623 05:03:28.206897 low task start!
624 05:03:28.207342 run into bl31
625 05:03:28.214788 NOTICE: BL31: v1.3(release):4fc40b1
626 05:03:28.222730 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 05:03:28.223357 NOTICE: BL31: G12A normal boot!
628 05:03:28.238175 NOTICE: BL31: BL33 decompress pass
629 05:03:28.243883 ERROR: Error initializing runtime service opteed_fast
630 05:03:29.636407 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 05:03:29.637040 bl2_stage_init 0x01
632 05:03:29.637474 bl2_stage_init 0x81
633 05:03:29.641953 hw id: 0x0000 - pwm id 0x01
634 05:03:29.642455 bl2_stage_init 0xc1
635 05:03:29.647600 bl2_stage_init 0x02
636 05:03:29.648130
637 05:03:29.648564 L0:00000000
638 05:03:29.648976 L1:00000703
639 05:03:29.649379 L2:00008067
640 05:03:29.649778 L3:15000000
641 05:03:29.653288 S1:00000000
642 05:03:29.653769 B2:20282000
643 05:03:29.654182 B1:a0f83180
644 05:03:29.654585
645 05:03:29.654987 TE: 70618
646 05:03:29.655388
647 05:03:29.658733 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 05:03:29.659209
649 05:03:29.664355 Board ID = 1
650 05:03:29.664831 Set cpu clk to 24M
651 05:03:29.665246 Set clk81 to 24M
652 05:03:29.670119 Use GP1_pll as DSU clk.
653 05:03:29.670599 DSU clk: 1200 Mhz
654 05:03:29.671008 CPU clk: 1200 MHz
655 05:03:29.675455 Set clk81 to 166.6M
656 05:03:29.680999 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 05:03:29.681479 board id: 1
658 05:03:29.688243 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 05:03:29.699128 fw parse done
660 05:03:29.705092 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 05:03:29.747325 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 05:03:29.759299 PIEI prepare done
663 05:03:29.759802 fastboot data load
664 05:03:29.760273 fastboot data verify
665 05:03:29.764897 verify result: 266
666 05:03:29.770583 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 05:03:29.771053 LPDDR4 probe
668 05:03:29.771467 ddr clk to 1584MHz
669 05:03:29.778638 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 05:03:29.816274
671 05:03:29.816784 dmc_version 0001
672 05:03:29.822550 Check phy result
673 05:03:29.829310 INFO : End of CA training
674 05:03:29.829788 INFO : End of initialization
675 05:03:29.834858 INFO : Training has run successfully!
676 05:03:29.835328 Check phy result
677 05:03:29.840514 INFO : End of initialization
678 05:03:29.841002 INFO : End of read enable training
679 05:03:29.846047 INFO : End of fine write leveling
680 05:03:29.851693 INFO : End of Write leveling coarse delay
681 05:03:29.852198 INFO : Training has run successfully!
682 05:03:29.852613 Check phy result
683 05:03:29.857299 INFO : End of initialization
684 05:03:29.857780 INFO : End of read dq deskew training
685 05:03:29.862866 INFO : End of MPR read delay center optimization
686 05:03:29.868508 INFO : End of write delay center optimization
687 05:03:29.874043 INFO : End of read delay center optimization
688 05:03:29.874513 INFO : End of max read latency training
689 05:03:29.879639 INFO : Training has run successfully!
690 05:03:29.880154 1D training succeed
691 05:03:29.888832 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 05:03:29.937163 Check phy result
693 05:03:29.937674 INFO : End of initialization
694 05:03:29.963798 INFO : End of 2D read delay Voltage center optimization
695 05:03:29.988783 INFO : End of 2D read delay Voltage center optimization
696 05:03:30.045513 INFO : End of 2D write delay Voltage center optimization
697 05:03:30.099367 INFO : End of 2D write delay Voltage center optimization
698 05:03:30.105057 INFO : Training has run successfully!
699 05:03:30.105533
700 05:03:30.105950 channel==0
701 05:03:30.110615 RxClkDly_Margin_A0==69 ps 7
702 05:03:30.111080 TxDqDly_Margin_A0==88 ps 9
703 05:03:30.116339 RxClkDly_Margin_A1==88 ps 9
704 05:03:30.116802 TxDqDly_Margin_A1==98 ps 10
705 05:03:30.117216 TrainedVREFDQ_A0==74
706 05:03:30.121829 TrainedVREFDQ_A1==75
707 05:03:30.122297 VrefDac_Margin_A0==24
708 05:03:30.122707 DeviceVref_Margin_A0==40
709 05:03:30.127379 VrefDac_Margin_A1==23
710 05:03:30.127842 DeviceVref_Margin_A1==39
711 05:03:30.128299
712 05:03:30.128704
713 05:03:30.129104 channel==1
714 05:03:30.133012 RxClkDly_Margin_A0==78 ps 8
715 05:03:30.133479 TxDqDly_Margin_A0==98 ps 10
716 05:03:30.138622 RxClkDly_Margin_A1==78 ps 8
717 05:03:30.139093 TxDqDly_Margin_A1==88 ps 9
718 05:03:30.144296 TrainedVREFDQ_A0==78
719 05:03:30.144776 TrainedVREFDQ_A1==75
720 05:03:30.145190 VrefDac_Margin_A0==22
721 05:03:30.149853 DeviceVref_Margin_A0==36
722 05:03:30.150324 VrefDac_Margin_A1==22
723 05:03:30.155404 DeviceVref_Margin_A1==39
724 05:03:30.155871
725 05:03:30.156315 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 05:03:30.156716
727 05:03:30.189006 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
728 05:03:30.189595 2D training succeed
729 05:03:30.194550 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 05:03:30.200149 auto size-- 65535DDR cs0 size: 2048MB
731 05:03:30.200641 DDR cs1 size: 2048MB
732 05:03:30.205729 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 05:03:30.206214 cs0 DataBus test pass
734 05:03:30.211331 cs1 DataBus test pass
735 05:03:30.211810 cs0 AddrBus test pass
736 05:03:30.212257 cs1 AddrBus test pass
737 05:03:30.212660
738 05:03:30.216916 100bdlr_step_size ps== 478
739 05:03:30.217404 result report
740 05:03:30.222517 boot times 0Enable ddr reg access
741 05:03:30.227690 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 05:03:30.241563 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 05:03:30.900940 bl2z: ptr: 05129330, size: 00001e40
744 05:03:30.909218 0.0;M3 CHK:0;cm4_sp_mode 0
745 05:03:30.909734 MVN_1=0x00000000
746 05:03:30.910157 MVN_2=0x00000000
747 05:03:30.920649 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 05:03:30.921169 OPS=0x04
749 05:03:30.921589 ring efuse init
750 05:03:30.926360 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 05:03:30.926854 [0.017355 Inits done]
752 05:03:30.927271 secure task start!
753 05:03:30.934200 high task start!
754 05:03:30.934687 low task start!
755 05:03:30.935101 run into bl31
756 05:03:30.942811 NOTICE: BL31: v1.3(release):4fc40b1
757 05:03:30.950765 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 05:03:30.951271 NOTICE: BL31: G12A normal boot!
759 05:03:30.966169 NOTICE: BL31: BL33 decompress pass
760 05:03:30.971882 ERROR: Error initializing runtime service opteed_fast
761 05:03:31.767180
762 05:03:31.767798
763 05:03:31.772743 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 05:03:31.773368
765 05:03:31.776163 Model: Libre Computer AML-S905D3-CC Solitude
766 05:03:31.923049 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 05:03:31.938452 DRAM: 2 GiB (effective 3.8 GiB)
768 05:03:32.039392 Core: 406 devices, 33 uclasses, devicetree: separate
769 05:03:32.045256 WDT: Not starting watchdog@f0d0
770 05:03:32.070420 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 05:03:32.082629 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 05:03:32.087670 ** Bad device specification mmc 0 **
773 05:03:32.097666 Card did not respond to voltage select! : -110
774 05:03:32.105317 ** Bad device specification mmc 0 **
775 05:03:32.105662 Couldn't find partition mmc 0
776 05:03:32.113615 Card did not respond to voltage select! : -110
777 05:03:32.119119 ** Bad device specification mmc 0 **
778 05:03:32.119582 Couldn't find partition mmc 0
779 05:03:32.124199 Error: could not access storage.
780 05:03:32.421846 Net: eth0: ethernet@ff3f0000
781 05:03:32.422291 starting USB...
782 05:03:32.666394 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 05:03:32.667055 Starting the controller
784 05:03:32.673335 USB XHCI 1.10
785 05:03:34.227453 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 05:03:34.234809 scanning usb for storage devices... 0 Storage Device(s) found
788 05:03:34.286425 Hit any key to stop autoboot: 1
789 05:03:34.287255 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
790 05:03:34.287894 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
791 05:03:34.288463 Setting prompt string to ['=>']
792 05:03:34.289005 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
793 05:03:34.301754 0
794 05:03:34.302722 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 05:03:34.404063 => setenv autoload no
797 05:03:34.404765 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
798 05:03:34.410123 setenv autoload no
800 05:03:34.511676 => setenv initrd_high 0xffffffff
801 05:03:34.512652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 05:03:34.517049 setenv initrd_high 0xffffffff
804 05:03:34.618575 => setenv fdt_high 0xffffffff
805 05:03:34.619353 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 05:03:34.624576 setenv fdt_high 0xffffffff
808 05:03:34.726155 => dhcp
809 05:03:34.726870 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 05:03:34.730983 dhcp
811 05:03:35.536782 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
812 05:03:35.537387 Speed: 1000, full duplex
813 05:03:35.537853 BOOTP broadcast 1
814 05:03:35.559318 DHCP client bound to address 192.168.6.21 (22 ms)
816 05:03:35.660931 => setenv serverip 192.168.6.2
817 05:03:35.661771 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
818 05:03:35.666472 setenv serverip 192.168.6.2
820 05:03:35.768096 => tftpboot 0x01080000 927127/tftp-deploy-k5u6njaf/kernel/uImage
821 05:03:35.768931 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
822 05:03:35.775729 tftpboot 0x01080000 927127/tftp-deploy-k5u6njaf/kernel/uImage
823 05:03:35.776342 Speed: 1000, full duplex
824 05:03:35.776802 Using ethernet@ff3f0000 device
825 05:03:35.781290 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
826 05:03:35.786765 Filename '927127/tftp-deploy-k5u6njaf/kernel/uImage'.
827 05:03:35.790579 Load address: 0x1080000
828 05:03:38.710341 Loading: *#################################### UDP wrong checksum 000000ff 00006100
829 05:03:38.727636 UDP wrong checksum 000000ff 0000f5f2
830 05:03:39.877927 ############## 63.4 MiB
831 05:03:39.878601 15.5 MiB/s
832 05:03:39.879079 done
833 05:03:39.882325 Bytes transferred = 66443840 (3f5da40 hex)
835 05:03:39.983938 => tftpboot 0x08000000 927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot
836 05:03:39.984651 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
837 05:03:39.991391 tftpboot 0x08000000 927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot
838 05:03:39.991894 Speed: 1000, full duplex
839 05:03:39.992391 Using ethernet@ff3f0000 device
840 05:03:39.996850 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
841 05:03:40.006727 Filename '927127/tftp-deploy-k5u6njaf/ramdisk/ramdisk.cpio.gz.uboot'.
842 05:03:40.007244 Load address: 0x8000000
843 05:03:47.452221 Loading: *#########################T ######################## UDP wrong checksum 00000007 00000f5c
844 05:03:52.452122 T UDP wrong checksum 00000007 00000f5c
845 05:04:02.454274 T T UDP wrong checksum 00000007 00000f5c
846 05:04:22.456566 T T T UDP wrong checksum 00000007 00000f5c
847 05:04:30.248716 T T UDP wrong checksum 000000ff 0000ca81
848 05:04:30.288981 UDP wrong checksum 000000ff 00005074
849 05:04:37.461848 T
850 05:04:37.462271 Retry count exceeded; starting again
852 05:04:37.463243 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
855 05:04:37.464429 end: 2.4 uboot-commands (duration 00:01:22) [common]
857 05:04:37.465159 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
859 05:04:37.465646 end: 2 uboot-action (duration 00:01:22) [common]
861 05:04:37.466435 Cleaning after the job
862 05:04:37.466722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/ramdisk
863 05:04:37.467950 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/kernel
864 05:04:37.504715 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/dtb
865 05:04:37.505573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/nfsrootfs
866 05:04:37.626620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927127/tftp-deploy-k5u6njaf/modules
867 05:04:37.656838 start: 4.1 power-off (timeout 00:00:30) [common]
868 05:04:37.657509 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
869 05:04:37.689635 >> OK - accepted request
870 05:04:37.691593 Returned 0 in 0 seconds
871 05:04:37.792736 end: 4.1 power-off (duration 00:00:00) [common]
873 05:04:37.794580 start: 4.2 read-feedback (timeout 00:10:00) [common]
874 05:04:37.796058 Listened to connection for namespace 'common' for up to 1s
875 05:04:38.796469 Finalising connection for namespace 'common'
876 05:04:38.796961 Disconnecting from shell: Finalise
877 05:04:38.797236 =>
878 05:04:38.897902 end: 4.2 read-feedback (duration 00:00:01) [common]
879 05:04:38.898437 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927127
880 05:04:41.041160 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927127
881 05:04:41.041849 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.