Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:21:09.220641 lava-dispatcher, installed at version: 2024.01
2 05:21:09.221420 start: 0 validate
3 05:21:09.221907 Start time: 2024-11-02 05:21:09.221876+00:00 (UTC)
4 05:21:09.222502 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:21:09.223078 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:21:09.262252 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:21:09.262813 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:21:09.292706 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:21:09.293345 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:21:14.358961 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:21:14.359448 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 05:21:15.405737 validate duration: 6.18
14 05:21:15.406573 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:21:15.406898 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:21:15.407198 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:21:15.407784 Not decompressing ramdisk as can be used compressed.
18 05:21:15.408204 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:21:15.408497 saving as /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/ramdisk/rootfs.cpio.gz
20 05:21:15.408774 total size: 8181887 (7 MB)
21 05:21:15.445141 progress 0 % (0 MB)
22 05:21:15.456915 progress 5 % (0 MB)
23 05:21:15.468259 progress 10 % (0 MB)
24 05:21:15.480124 progress 15 % (1 MB)
25 05:21:15.485405 progress 20 % (1 MB)
26 05:21:15.491801 progress 25 % (1 MB)
27 05:21:15.496999 progress 30 % (2 MB)
28 05:21:15.502616 progress 35 % (2 MB)
29 05:21:15.508280 progress 40 % (3 MB)
30 05:21:15.513893 progress 45 % (3 MB)
31 05:21:15.519286 progress 50 % (3 MB)
32 05:21:15.524988 progress 55 % (4 MB)
33 05:21:15.530224 progress 60 % (4 MB)
34 05:21:15.536306 progress 65 % (5 MB)
35 05:21:15.541563 progress 70 % (5 MB)
36 05:21:15.547824 progress 75 % (5 MB)
37 05:21:15.553712 progress 80 % (6 MB)
38 05:21:15.559885 progress 85 % (6 MB)
39 05:21:15.565721 progress 90 % (7 MB)
40 05:21:15.571307 progress 95 % (7 MB)
41 05:21:15.576155 progress 100 % (7 MB)
42 05:21:15.576885 7 MB downloaded in 0.17 s (46.42 MB/s)
43 05:21:15.577447 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:21:15.578368 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:21:15.578669 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:21:15.578950 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:21:15.579472 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kernel/Image
49 05:21:15.579772 saving as /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/kernel/Image
50 05:21:15.580016 total size: 45713920 (43 MB)
51 05:21:15.580246 No compression specified
52 05:21:15.619529 progress 0 % (0 MB)
53 05:21:15.648959 progress 5 % (2 MB)
54 05:21:15.678139 progress 10 % (4 MB)
55 05:21:15.706308 progress 15 % (6 MB)
56 05:21:15.737519 progress 20 % (8 MB)
57 05:21:15.766148 progress 25 % (10 MB)
58 05:21:15.795434 progress 30 % (13 MB)
59 05:21:15.824021 progress 35 % (15 MB)
60 05:21:15.852140 progress 40 % (17 MB)
61 05:21:15.880914 progress 45 % (19 MB)
62 05:21:15.909015 progress 50 % (21 MB)
63 05:21:15.937526 progress 55 % (24 MB)
64 05:21:15.966128 progress 60 % (26 MB)
65 05:21:15.994516 progress 65 % (28 MB)
66 05:21:16.023332 progress 70 % (30 MB)
67 05:21:16.051386 progress 75 % (32 MB)
68 05:21:16.080091 progress 80 % (34 MB)
69 05:21:16.107742 progress 85 % (37 MB)
70 05:21:16.135582 progress 90 % (39 MB)
71 05:21:16.164189 progress 95 % (41 MB)
72 05:21:16.192295 progress 100 % (43 MB)
73 05:21:16.192863 43 MB downloaded in 0.61 s (71.14 MB/s)
74 05:21:16.193353 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:21:16.194169 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:21:16.194441 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:21:16.194705 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:21:16.195168 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 05:21:16.195445 saving as /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 05:21:16.195653 total size: 53209 (0 MB)
82 05:21:16.195863 No compression specified
83 05:21:16.232070 progress 61 % (0 MB)
84 05:21:16.232980 progress 100 % (0 MB)
85 05:21:16.233541 0 MB downloaded in 0.04 s (1.34 MB/s)
86 05:21:16.234027 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:21:16.234837 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:21:16.235098 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:21:16.235359 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:21:16.235825 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/modules.tar.xz
92 05:21:16.236097 saving as /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/modules/modules.tar
93 05:21:16.236305 total size: 11611500 (11 MB)
94 05:21:16.236515 Using unxz to decompress xz
95 05:21:16.270809 progress 0 % (0 MB)
96 05:21:16.348770 progress 5 % (0 MB)
97 05:21:16.429707 progress 10 % (1 MB)
98 05:21:16.514592 progress 15 % (1 MB)
99 05:21:17.345497 progress 20 % (2 MB)
100 05:21:17.430310 progress 25 % (2 MB)
101 05:21:17.510234 progress 30 % (3 MB)
102 05:21:17.587968 progress 35 % (3 MB)
103 05:21:17.664888 progress 40 % (4 MB)
104 05:21:17.751235 progress 45 % (5 MB)
105 05:21:17.833846 progress 50 % (5 MB)
106 05:21:17.913347 progress 55 % (6 MB)
107 05:21:17.997639 progress 60 % (6 MB)
108 05:21:18.084251 progress 65 % (7 MB)
109 05:21:18.167380 progress 70 % (7 MB)
110 05:21:18.244053 progress 75 % (8 MB)
111 05:21:18.328139 progress 80 % (8 MB)
112 05:21:18.409235 progress 85 % (9 MB)
113 05:21:18.478309 progress 90 % (9 MB)
114 05:21:18.577471 progress 95 % (10 MB)
115 05:21:18.676247 progress 100 % (11 MB)
116 05:21:18.689505 11 MB downloaded in 2.45 s (4.51 MB/s)
117 05:21:18.690280 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:21:18.691279 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:21:18.691612 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:21:18.691939 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:21:18.692655 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:21:18.693351 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:21:18.694599 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn
125 05:21:18.695809 makedir: /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin
126 05:21:18.696703 makedir: /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/tests
127 05:21:18.697501 makedir: /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/results
128 05:21:18.698293 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-add-keys
129 05:21:18.699525 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-add-sources
130 05:21:18.700795 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-background-process-start
131 05:21:18.702025 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-background-process-stop
132 05:21:18.703309 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-common-functions
133 05:21:18.704576 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-echo-ipv4
134 05:21:18.705767 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-install-packages
135 05:21:18.706980 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-installed-packages
136 05:21:18.708220 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-os-build
137 05:21:18.709426 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-probe-channel
138 05:21:18.710597 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-probe-ip
139 05:21:18.711758 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-target-ip
140 05:21:18.712998 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-target-mac
141 05:21:18.714175 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-target-storage
142 05:21:18.715362 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-case
143 05:21:18.716617 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-event
144 05:21:18.717791 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-feedback
145 05:21:18.718987 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-raise
146 05:21:18.720234 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-reference
147 05:21:18.721497 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-runner
148 05:21:18.722822 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-set
149 05:21:18.724043 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-test-shell
150 05:21:18.725296 Updating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-install-packages (oe)
151 05:21:18.726598 Updating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/bin/lava-installed-packages (oe)
152 05:21:18.727738 Creating /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/environment
153 05:21:18.728510 LAVA metadata
154 05:21:18.728878 - LAVA_JOB_ID=927245
155 05:21:18.729168 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:21:18.729650 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:21:18.730918 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:21:18.731330 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:21:18.731589 skipped lava-vland-overlay
160 05:21:18.731894 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:21:18.732254 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:21:18.732536 skipped lava-multinode-overlay
163 05:21:18.732839 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:21:18.733155 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:21:18.733465 Loading test definitions
166 05:21:18.733823 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:21:18.734105 Using /lava-927245 at stage 0
168 05:21:18.735741 uuid=927245_1.5.2.4.1 testdef=None
169 05:21:18.736202 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:21:18.736546 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:21:18.738832 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:21:18.739817 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:21:18.742714 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:21:18.743743 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:21:18.746558 runner path: /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/0/tests/0_dmesg test_uuid 927245_1.5.2.4.1
178 05:21:18.747302 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:21:18.748396 Creating lava-test-runner.conf files
181 05:21:18.748655 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927245/lava-overlay-uospx7xn/lava-927245/0 for stage 0
182 05:21:18.749112 - 0_dmesg
183 05:21:18.749564 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:21:18.749907 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:21:18.779635 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:21:18.780203 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:21:18.780536 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:21:18.780870 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:21:18.781194 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:21:19.902879 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:21:19.903463 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:21:19.903805 extracting modules file /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk
193 05:21:21.598647 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 05:21:21.599169 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 05:21:21.599461 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927245/compress-overlay-y4ilpj__/overlay-1.5.2.5.tar.gz to ramdisk
196 05:21:21.599680 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927245/compress-overlay-y4ilpj__/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk
197 05:21:21.631534 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:21:21.632041 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 05:21:21.632363 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 05:21:21.632614 Converting downloaded kernel to a uImage
201 05:21:21.632961 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/kernel/Image /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/kernel/uImage
202 05:21:22.154988 output: Image Name:
203 05:21:22.155414 output: Created: Sat Nov 2 05:21:21 2024
204 05:21:22.155657 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:21:22.155948 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 05:21:22.156245 output: Load Address: 01080000
207 05:21:22.156543 output: Entry Point: 01080000
208 05:21:22.156784 output:
209 05:21:22.157142 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:21:22.157570 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:21:22.157860 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 05:21:22.158126 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:21:22.158392 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 05:21:22.158651 Building ramdisk /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk
215 05:21:24.673379 >> 181606 blocks
216 05:21:33.164203 Adding RAMdisk u-boot header.
217 05:21:33.164727 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk.cpio.gz.uboot
218 05:21:33.428973 output: Image Name:
219 05:21:33.429795 output: Created: Sat Nov 2 05:21:33 2024
220 05:21:33.430407 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:21:33.430957 output: Data Size: 26062269 Bytes = 25451.43 KiB = 24.85 MiB
222 05:21:33.431479 output: Load Address: 00000000
223 05:21:33.432057 output: Entry Point: 00000000
224 05:21:33.432585 output:
225 05:21:33.435222 rename /var/lib/lava/dispatcher/tmp/927245/extract-overlay-ramdisk-nar4dycs/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot
226 05:21:33.436286 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:21:33.438145 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 05:21:33.439745 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 05:21:33.440178 No LXC device requested
230 05:21:33.440536 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:21:33.440959 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 05:21:33.441480 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:21:33.442514 Checking files for TFTP limit of 4294967296 bytes.
234 05:21:33.446264 end: 1 tftp-deploy (duration 00:00:18) [common]
235 05:21:33.447121 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:21:33.447821 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:21:33.448589 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:21:33.449297 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:21:33.450002 Using kernel file from prepare-kernel: 927245/tftp-deploy-5jwpanrh/kernel/uImage
240 05:21:33.450788 substitutions:
241 05:21:33.451323 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:21:33.451841 - {DTB_ADDR}: 0x01070000
243 05:21:33.452474 - {DTB}: 927245/tftp-deploy-5jwpanrh/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 05:21:33.453083 - {INITRD}: 927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot
245 05:21:33.453625 - {KERNEL_ADDR}: 0x01080000
246 05:21:33.454141 - {KERNEL}: 927245/tftp-deploy-5jwpanrh/kernel/uImage
247 05:21:33.454656 - {LAVA_MAC}: None
248 05:21:33.455226 - {PRESEED_CONFIG}: None
249 05:21:33.455740 - {PRESEED_LOCAL}: None
250 05:21:33.456302 - {RAMDISK_ADDR}: 0x08000000
251 05:21:33.456834 - {RAMDISK}: 927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot
252 05:21:33.457361 - {ROOT_PART}: None
253 05:21:33.457881 - {ROOT}: None
254 05:21:33.458389 - {SERVER_IP}: 192.168.6.2
255 05:21:33.458909 - {TEE_ADDR}: 0x83000000
256 05:21:33.459416 - {TEE}: None
257 05:21:33.459921 Parsed boot commands:
258 05:21:33.460458 - setenv autoload no
259 05:21:33.460967 - setenv initrd_high 0xffffffff
260 05:21:33.461479 - setenv fdt_high 0xffffffff
261 05:21:33.461981 - dhcp
262 05:21:33.462487 - setenv serverip 192.168.6.2
263 05:21:33.462991 - tftpboot 0x01080000 927245/tftp-deploy-5jwpanrh/kernel/uImage
264 05:21:33.463495 - tftpboot 0x08000000 927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot
265 05:21:33.464015 - tftpboot 0x01070000 927245/tftp-deploy-5jwpanrh/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 05:21:33.464535 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:21:33.465080 - bootm 0x01080000 0x08000000 0x01070000
268 05:21:33.465784 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:21:33.467766 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:21:33.468412 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 05:21:33.484062 Setting prompt string to ['lava-test: # ']
273 05:21:33.485342 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:21:33.485881 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:21:33.486303 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:21:33.486718 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:21:33.487675 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 05:21:33.523890 >> OK - accepted request
279 05:21:33.526069 Returned 0 in 0 seconds
280 05:21:33.627363 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:21:33.628417 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:21:33.628751 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:21:33.629053 Setting prompt string to ['Hit any key to stop autoboot']
285 05:21:33.629293 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:21:33.630233 Trying 192.168.56.21...
287 05:21:33.630517 Connected to conserv1.
288 05:21:33.630727 Escape character is '^]'.
289 05:21:33.630943
290 05:21:33.631162 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:21:33.631385
292 05:21:41.151872 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 05:21:41.152383 bl2_stage_init 0x01
294 05:21:41.152665 bl2_stage_init 0x81
295 05:21:41.157320 hw id: 0x0000 - pwm id 0x01
296 05:21:41.157756 bl2_stage_init 0xc1
297 05:21:41.162925 bl2_stage_init 0x02
298 05:21:41.163354
299 05:21:41.163602 L0:00000000
300 05:21:41.163828 L1:00000703
301 05:21:41.164097 L2:00008067
302 05:21:41.164339 L3:15000000
303 05:21:41.168653 S1:00000000
304 05:21:41.169090 B2:20282000
305 05:21:41.169341 B1:a0f83180
306 05:21:41.169567
307 05:21:41.169789 TE: 69451
308 05:21:41.170012
309 05:21:41.174168 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 05:21:41.174587
311 05:21:41.179766 Board ID = 1
312 05:21:41.180193 Set cpu clk to 24M
313 05:21:41.180472 Set clk81 to 24M
314 05:21:41.185292 Use GP1_pll as DSU clk.
315 05:21:41.185706 DSU clk: 1200 Mhz
316 05:21:41.186015 CPU clk: 1200 MHz
317 05:21:41.190821 Set clk81 to 166.6M
318 05:21:41.196570 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 05:21:41.196901 board id: 1
320 05:21:41.203565 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:21:41.214660 fw parse done
322 05:21:41.220634 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:21:41.263488 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:21:41.274726 PIEI prepare done
325 05:21:41.275199 fastboot data load
326 05:21:41.275597 fastboot data verify
327 05:21:41.280193 verify result: 266
328 05:21:41.285802 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 05:21:41.286228 LPDDR4 probe
330 05:21:41.286619 ddr clk to 1584MHz
331 05:21:41.293838 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:21:41.331566
333 05:21:41.332092 dmc_version 0001
334 05:21:41.338560 Check phy result
335 05:21:41.344561 INFO : End of CA training
336 05:21:41.344994 INFO : End of initialization
337 05:21:41.350148 INFO : Training has run successfully!
338 05:21:41.350568 Check phy result
339 05:21:41.355702 INFO : End of initialization
340 05:21:41.356155 INFO : End of read enable training
341 05:21:41.361448 INFO : End of fine write leveling
342 05:21:41.366917 INFO : End of Write leveling coarse delay
343 05:21:41.367337 INFO : Training has run successfully!
344 05:21:41.367728 Check phy result
345 05:21:41.372542 INFO : End of initialization
346 05:21:41.372960 INFO : End of read dq deskew training
347 05:21:41.378080 INFO : End of MPR read delay center optimization
348 05:21:41.383687 INFO : End of write delay center optimization
349 05:21:41.389413 INFO : End of read delay center optimization
350 05:21:41.389852 INFO : End of max read latency training
351 05:21:41.394945 INFO : Training has run successfully!
352 05:21:41.395425 1D training succeed
353 05:21:41.404154 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:21:41.452433 Check phy result
355 05:21:41.452868 INFO : End of initialization
356 05:21:41.479788 INFO : End of 2D read delay Voltage center optimization
357 05:21:41.504093 INFO : End of 2D read delay Voltage center optimization
358 05:21:41.560640 INFO : End of 2D write delay Voltage center optimization
359 05:21:41.614726 INFO : End of 2D write delay Voltage center optimization
360 05:21:41.620231 INFO : Training has run successfully!
361 05:21:41.620661
362 05:21:41.621059 channel==0
363 05:21:41.625811 RxClkDly_Margin_A0==78 ps 8
364 05:21:41.626233 TxDqDly_Margin_A0==98 ps 10
365 05:21:41.631476 RxClkDly_Margin_A1==88 ps 9
366 05:21:41.631894 TxDqDly_Margin_A1==98 ps 10
367 05:21:41.632340 TrainedVREFDQ_A0==78
368 05:21:41.637035 TrainedVREFDQ_A1==74
369 05:21:41.637457 VrefDac_Margin_A0==24
370 05:21:41.637846 DeviceVref_Margin_A0==36
371 05:21:41.642622 VrefDac_Margin_A1==23
372 05:21:41.643036 DeviceVref_Margin_A1==40
373 05:21:41.643427
374 05:21:41.643812
375 05:21:41.648221 channel==1
376 05:21:41.648657 RxClkDly_Margin_A0==78 ps 8
377 05:21:41.649047 TxDqDly_Margin_A0==88 ps 9
378 05:21:41.653812 RxClkDly_Margin_A1==78 ps 8
379 05:21:41.654235 TxDqDly_Margin_A1==88 ps 9
380 05:21:41.659459 TrainedVREFDQ_A0==75
381 05:21:41.659879 TrainedVREFDQ_A1==77
382 05:21:41.660306 VrefDac_Margin_A0==22
383 05:21:41.665007 DeviceVref_Margin_A0==39
384 05:21:41.665434 VrefDac_Margin_A1==22
385 05:21:41.670589 DeviceVref_Margin_A1==37
386 05:21:41.670995
387 05:21:41.671391 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:21:41.671781
389 05:21:41.704238 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
390 05:21:41.704799 2D training succeed
391 05:21:41.709856 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:21:41.715492 auto size-- 65535DDR cs0 size: 2048MB
393 05:21:41.715917 DDR cs1 size: 2048MB
394 05:21:41.721000 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:21:41.721437 cs0 DataBus test pass
396 05:21:41.726642 cs1 DataBus test pass
397 05:21:41.727060 cs0 AddrBus test pass
398 05:21:41.727447 cs1 AddrBus test pass
399 05:21:41.727831
400 05:21:41.732316 100bdlr_step_size ps== 478
401 05:21:41.732778 result report
402 05:21:41.737808 boot times 0Enable ddr reg access
403 05:21:41.742992 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:21:41.758427 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 05:21:42.417406 bl2z: ptr: 05129330, size: 00001e40
406 05:21:42.425557 0.0;M3 CHK:0;cm4_sp_mode 0
407 05:21:42.425943 MVN_1=0x00000000
408 05:21:42.426177 MVN_2=0x00000000
409 05:21:42.436892 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 05:21:42.437278 OPS=0x04
411 05:21:42.437507 ring efuse init
412 05:21:42.442607 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 05:21:42.443023 [0.017355 Inits done]
414 05:21:42.443234 secure task start!
415 05:21:42.450836 high task start!
416 05:21:42.451179 low task start!
417 05:21:42.451397 run into bl31
418 05:21:42.459102 NOTICE: BL31: v1.3(release):4fc40b1
419 05:21:42.466925 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 05:21:42.467260 NOTICE: BL31: G12A normal boot!
421 05:21:42.483487 NOTICE: BL31: BL33 decompress pass
422 05:21:42.488298 ERROR: Error initializing runtime service opteed_fast
423 05:21:43.701707 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 05:21:43.702387 bl2_stage_init 0x01
425 05:21:43.702879 bl2_stage_init 0x81
426 05:21:43.707237 hw id: 0x0000 - pwm id 0x01
427 05:21:43.707783 bl2_stage_init 0xc1
428 05:21:43.712837 bl2_stage_init 0x02
429 05:21:43.713370
430 05:21:43.713842 L0:00000000
431 05:21:43.714307 L1:00000703
432 05:21:43.714764 L2:00008067
433 05:21:43.715230 L3:15000000
434 05:21:43.718411 S1:00000000
435 05:21:43.718922 B2:20282000
436 05:21:43.719366 B1:a0f83180
437 05:21:43.719804
438 05:21:43.720292 TE: 68055
439 05:21:43.720729
440 05:21:43.724020 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 05:21:43.724514
442 05:21:43.729610 Board ID = 1
443 05:21:43.730112 Set cpu clk to 24M
444 05:21:43.730554 Set clk81 to 24M
445 05:21:43.735187 Use GP1_pll as DSU clk.
446 05:21:43.735702 DSU clk: 1200 Mhz
447 05:21:43.736189 CPU clk: 1200 MHz
448 05:21:43.740900 Set clk81 to 166.6M
449 05:21:43.746390 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 05:21:43.746886 board id: 1
451 05:21:43.753595 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 05:21:43.764505 fw parse done
453 05:21:43.770439 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 05:21:43.813592 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 05:21:43.824791 PIEI prepare done
456 05:21:43.825317 fastboot data load
457 05:21:43.825768 fastboot data verify
458 05:21:43.830403 verify result: 266
459 05:21:43.836010 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 05:21:43.836549 LPDDR4 probe
461 05:21:43.836983 ddr clk to 1584MHz
462 05:21:45.201025 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 05:21:45.201464 bl2_stage_init 0x01
464 05:21:45.201690 bl2_stage_init 0x81
465 05:21:45.206584 hw id: 0x0000 - pwm id 0x01
466 05:21:45.206968 bl2_stage_init 0xc1
467 05:21:45.212148 bl2_stage_init 0x02
468 05:21:45.212514
469 05:21:45.212849 L0:00000000
470 05:21:45.213178 L1:00000703
471 05:21:45.213418 L2:00008067
472 05:21:45.213628 L3:15000000
473 05:21:45.217797 S1:00000000
474 05:21:45.218153 B2:20282000
475 05:21:45.218478 B1:a0f83180
476 05:21:45.218792
477 05:21:45.219104 TE: 69189
478 05:21:45.219420
479 05:21:45.223359 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 05:21:45.223624
481 05:21:45.228958 Board ID = 1
482 05:21:45.229233 Set cpu clk to 24M
483 05:21:45.229447 Set clk81 to 24M
484 05:21:45.234546 Use GP1_pll as DSU clk.
485 05:21:45.234902 DSU clk: 1200 Mhz
486 05:21:45.235228 CPU clk: 1200 MHz
487 05:21:45.240137 Set clk81 to 166.6M
488 05:21:45.245791 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 05:21:45.246164 board id: 1
490 05:21:45.253033 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 05:21:45.263932 fw parse done
492 05:21:45.269873 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 05:21:45.313009 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 05:21:45.324137 PIEI prepare done
495 05:21:45.324479 fastboot data load
496 05:21:45.324698 fastboot data verify
497 05:21:45.329697 verify result: 266
498 05:21:45.335328 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 05:21:45.335757 LPDDR4 probe
500 05:21:45.336121 ddr clk to 1584MHz
501 05:21:45.343351 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 05:21:45.381171
503 05:21:45.381776 dmc_version 0001
504 05:21:45.388142 Check phy result
505 05:21:45.394106 INFO : End of CA training
506 05:21:45.394654 INFO : End of initialization
507 05:21:45.399691 INFO : Training has run successfully!
508 05:21:45.400298 Check phy result
509 05:21:45.405313 INFO : End of initialization
510 05:21:45.405837 INFO : End of read enable training
511 05:21:45.410919 INFO : End of fine write leveling
512 05:21:45.416495 INFO : End of Write leveling coarse delay
513 05:21:45.417019 INFO : Training has run successfully!
514 05:21:45.417481 Check phy result
515 05:21:45.422113 INFO : End of initialization
516 05:21:45.422660 INFO : End of read dq deskew training
517 05:21:45.427699 INFO : End of MPR read delay center optimization
518 05:21:45.433324 INFO : End of write delay center optimization
519 05:21:45.438934 INFO : End of read delay center optimization
520 05:21:45.439487 INFO : End of max read latency training
521 05:21:45.444499 INFO : Training has run successfully!
522 05:21:45.445069 1D training succeed
523 05:21:45.453709 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 05:21:45.502042 Check phy result
525 05:21:45.502665 INFO : End of initialization
526 05:21:45.529478 INFO : End of 2D read delay Voltage center optimization
527 05:21:45.553590 INFO : End of 2D read delay Voltage center optimization
528 05:21:45.610360 INFO : End of 2D write delay Voltage center optimization
529 05:21:45.664437 INFO : End of 2D write delay Voltage center optimization
530 05:21:45.669853 INFO : Training has run successfully!
531 05:21:45.670371
532 05:21:45.670843 channel==0
533 05:21:45.675443 RxClkDly_Margin_A0==88 ps 9
534 05:21:45.675944 TxDqDly_Margin_A0==98 ps 10
535 05:21:45.681185 RxClkDly_Margin_A1==88 ps 9
536 05:21:45.681717 TxDqDly_Margin_A1==98 ps 10
537 05:21:45.682178 TrainedVREFDQ_A0==74
538 05:21:45.686774 TrainedVREFDQ_A1==74
539 05:21:45.687301 VrefDac_Margin_A0==24
540 05:21:45.687740 DeviceVref_Margin_A0==40
541 05:21:45.692329 VrefDac_Margin_A1==22
542 05:21:45.692841 DeviceVref_Margin_A1==40
543 05:21:45.693272
544 05:21:45.693685
545 05:21:45.697911 channel==1
546 05:21:45.698421 RxClkDly_Margin_A0==78 ps 8
547 05:21:45.698849 TxDqDly_Margin_A0==78 ps 8
548 05:21:45.703505 RxClkDly_Margin_A1==78 ps 8
549 05:21:45.704041 TxDqDly_Margin_A1==88 ps 9
550 05:21:45.709174 TrainedVREFDQ_A0==75
551 05:21:45.709683 TrainedVREFDQ_A1==75
552 05:21:45.710110 VrefDac_Margin_A0==22
553 05:21:45.714744 DeviceVref_Margin_A0==39
554 05:21:45.715282 VrefDac_Margin_A1==22
555 05:21:45.720350 DeviceVref_Margin_A1==39
556 05:21:45.720871
557 05:21:45.721296 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 05:21:45.721709
559 05:21:45.753891 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
560 05:21:45.754459 2D training succeed
561 05:21:45.759523 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 05:21:45.765190 auto size-- 65535DDR cs0 size: 2048MB
563 05:21:45.765699 DDR cs1 size: 2048MB
564 05:21:45.770719 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 05:21:45.771225 cs0 DataBus test pass
566 05:21:45.776324 cs1 DataBus test pass
567 05:21:45.776834 cs0 AddrBus test pass
568 05:21:45.777259 cs1 AddrBus test pass
569 05:21:45.777669
570 05:21:45.781936 100bdlr_step_size ps== 471
571 05:21:45.782457 result report
572 05:21:45.787590 boot times 0Enable ddr reg access
573 05:21:45.792716 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 05:21:45.806529 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 05:21:46.466084 bl2z: ptr: 05129330, size: 00001e40
576 05:21:46.474071 0.0;M3 CHK:0;cm4_sp_mode 0
577 05:21:46.474568 MVN_1=0x00000000
578 05:21:46.474991 MVN_2=0x00000000
579 05:21:46.485476 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 05:21:46.485972 OPS=0x04
581 05:21:46.486390 ring efuse init
582 05:21:46.490994 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 05:21:46.491487 [0.017354 Inits done]
584 05:21:46.491900 secure task start!
585 05:21:46.498339 high task start!
586 05:21:46.498804 low task start!
587 05:21:46.499218 run into bl31
588 05:21:46.506745 NOTICE: BL31: v1.3(release):4fc40b1
589 05:21:46.514629 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 05:21:46.515097 NOTICE: BL31: G12A normal boot!
591 05:21:46.530322 NOTICE: BL31: BL33 decompress pass
592 05:21:46.535916 ERROR: Error initializing runtime service opteed_fast
593 05:21:47.905013 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 05:21:47.905448 bl2_stage_init 0x01
595 05:21:47.906001 bl2_stage_init 0x81
596 05:21:47.909850 hw id: 0x0000 - pwm id 0x01
597 05:21:47.910444 bl2_stage_init 0xc1
598 05:21:47.915254 bl2_stage_init 0x02
599 05:21:47.915815
600 05:21:47.916523 L0:00000000
601 05:21:47.916939 L1:00000703
602 05:21:47.917336 L2:00008067
603 05:21:47.917729 L3:15000000
604 05:21:47.920927 S1:00000000
605 05:21:47.921422 B2:20282000
606 05:21:47.921822 B1:a0f83180
607 05:21:47.922209
608 05:21:47.922599 TE: 70441
609 05:21:47.922986
610 05:21:47.926633 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 05:21:47.927108
612 05:21:47.932161 Board ID = 1
613 05:21:47.932692 Set cpu clk to 24M
614 05:21:47.933092 Set clk81 to 24M
615 05:21:47.937721 Use GP1_pll as DSU clk.
616 05:21:47.938179 DSU clk: 1200 Mhz
617 05:21:47.938573 CPU clk: 1200 MHz
618 05:21:47.943316 Set clk81 to 166.6M
619 05:21:47.948918 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 05:21:47.949452 board id: 1
621 05:21:47.955750 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 05:21:47.966938 fw parse done
623 05:21:47.972865 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 05:21:48.015962 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 05:21:48.027191 PIEI prepare done
626 05:21:48.027689 fastboot data load
627 05:21:48.028129 fastboot data verify
628 05:21:48.032807 verify result: 266
629 05:21:48.038444 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 05:21:48.038944 LPDDR4 probe
631 05:21:48.039337 ddr clk to 1584MHz
632 05:21:48.045822 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 05:21:48.084318
634 05:21:48.084944 dmc_version 0001
635 05:21:48.090982 Check phy result
636 05:21:48.097245 INFO : End of CA training
637 05:21:48.097791 INFO : End of initialization
638 05:21:48.102826 INFO : Training has run successfully!
639 05:21:48.103323 Check phy result
640 05:21:48.108385 INFO : End of initialization
641 05:21:48.108870 INFO : End of read enable training
642 05:21:48.111677 INFO : End of fine write leveling
643 05:21:48.117276 INFO : End of Write leveling coarse delay
644 05:21:48.122826 INFO : Training has run successfully!
645 05:21:48.123307 Check phy result
646 05:21:48.123704 INFO : End of initialization
647 05:21:48.128387 INFO : End of read dq deskew training
648 05:21:48.132425 INFO : End of MPR read delay center optimization
649 05:21:48.137474 INFO : End of write delay center optimization
650 05:21:48.143132 INFO : End of read delay center optimization
651 05:21:48.143699 INFO : End of max read latency training
652 05:21:48.148639 INFO : Training has run successfully!
653 05:21:48.149193 1D training succeed
654 05:21:48.155977 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 05:21:48.205044 Check phy result
656 05:21:48.205445 INFO : End of initialization
657 05:21:48.232467 INFO : End of 2D read delay Voltage center optimization
658 05:21:48.256721 INFO : End of 2D read delay Voltage center optimization
659 05:21:48.313210 INFO : End of 2D write delay Voltage center optimization
660 05:21:48.367431 INFO : End of 2D write delay Voltage center optimization
661 05:21:48.372983 INFO : Training has run successfully!
662 05:21:48.373556
663 05:21:48.373993 channel==0
664 05:21:48.378691 RxClkDly_Margin_A0==78 ps 8
665 05:21:48.379238 TxDqDly_Margin_A0==98 ps 10
666 05:21:48.384161 RxClkDly_Margin_A1==88 ps 9
667 05:21:48.384726 TxDqDly_Margin_A1==98 ps 10
668 05:21:48.385176 TrainedVREFDQ_A0==74
669 05:21:48.389775 TrainedVREFDQ_A1==75
670 05:21:48.390352 VrefDac_Margin_A0==24
671 05:21:48.390754 DeviceVref_Margin_A0==40
672 05:21:48.395318 VrefDac_Margin_A1==23
673 05:21:48.395858 DeviceVref_Margin_A1==39
674 05:21:48.396362
675 05:21:48.396760
676 05:21:48.400943 channel==1
677 05:21:48.401481 RxClkDly_Margin_A0==88 ps 9
678 05:21:48.401901 TxDqDly_Margin_A0==88 ps 9
679 05:21:48.406486 RxClkDly_Margin_A1==88 ps 9
680 05:21:48.406981 TxDqDly_Margin_A1==88 ps 9
681 05:21:48.412136 TrainedVREFDQ_A0==75
682 05:21:48.412658 TrainedVREFDQ_A1==75
683 05:21:48.413059 VrefDac_Margin_A0==22
684 05:21:48.417719 DeviceVref_Margin_A0==38
685 05:21:48.418232 VrefDac_Margin_A1==22
686 05:21:48.423350 DeviceVref_Margin_A1==39
687 05:21:48.423844
688 05:21:48.424279 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 05:21:48.424691
690 05:21:48.457210 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000015 00000018 00000016 00000018 00000018 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
691 05:21:48.457857 2D training succeed
692 05:21:48.462682 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 05:21:48.468217 auto size-- 65535DDR cs0 size: 2048MB
694 05:21:48.468761 DDR cs1 size: 2048MB
695 05:21:48.473809 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 05:21:48.474347 cs0 DataBus test pass
697 05:21:48.479389 cs1 DataBus test pass
698 05:21:48.479918 cs0 AddrBus test pass
699 05:21:48.480389 cs1 AddrBus test pass
700 05:21:48.480795
701 05:21:48.484868 100bdlr_step_size ps== 485
702 05:21:48.485430 result report
703 05:21:48.490463 boot times 0Enable ddr reg access
704 05:21:48.495696 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 05:21:48.509484 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 05:21:49.169442 bl2z: ptr: 05129330, size: 00001e40
707 05:21:49.177832 0.0;M3 CHK:0;cm4_sp_mode 0
708 05:21:49.178652 MVN_1=0x00000000
709 05:21:49.179187 MVN_2=0x00000000
710 05:21:49.189370 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 05:21:49.190041 OPS=0x04
712 05:21:49.190580 ring efuse init
713 05:21:49.192181 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 05:21:49.198692 [0.017354 Inits done]
715 05:21:49.199294 secure task start!
716 05:21:49.199811 high task start!
717 05:21:49.200358 low task start!
718 05:21:49.202971 run into bl31
719 05:21:49.211606 NOTICE: BL31: v1.3(release):4fc40b1
720 05:21:49.219416 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 05:21:49.220096 NOTICE: BL31: G12A normal boot!
722 05:21:49.235018 NOTICE: BL31: BL33 decompress pass
723 05:21:49.240701 ERROR: Error initializing runtime service opteed_fast
724 05:21:50.036169
725 05:21:50.037006
726 05:21:50.041582 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 05:21:50.042305
728 05:21:50.044952 Model: Libre Computer AML-S905D3-CC Solitude
729 05:21:50.192072 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 05:21:50.207470 DRAM: 2 GiB (effective 3.8 GiB)
731 05:21:50.308350 Core: 406 devices, 33 uclasses, devicetree: separate
732 05:21:50.314217 WDT: Not starting watchdog@f0d0
733 05:21:50.339271 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 05:21:50.351600 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 05:21:50.356490 ** Bad device specification mmc 0 **
736 05:21:50.366713 Card did not respond to voltage select! : -110
737 05:21:50.374223 ** Bad device specification mmc 0 **
738 05:21:50.374708 Couldn't find partition mmc 0
739 05:21:50.382575 Card did not respond to voltage select! : -110
740 05:21:50.388120 ** Bad device specification mmc 0 **
741 05:21:50.388595 Couldn't find partition mmc 0
742 05:21:50.393104 Error: could not access storage.
743 05:21:50.689602 Net: eth0: ethernet@ff3f0000
744 05:21:50.690235 starting USB...
745 05:21:50.934190 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 05:21:50.934793 Starting the controller
747 05:21:50.941144 USB XHCI 1.10
748 05:21:52.495234 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 05:21:52.504340 scanning usb for storage devices... 0 Storage Device(s) found
751 05:21:52.556088 Hit any key to stop autoboot: 1
752 05:21:52.556954 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 05:21:52.557469 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 05:21:52.558015 Setting prompt string to ['=>']
755 05:21:52.558548 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 05:21:52.570536 0
757 05:21:52.571376 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 05:21:52.672996 => setenv autoload no
760 05:21:52.674085 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 05:21:52.678094 setenv autoload no
763 05:21:52.779803 => setenv initrd_high 0xffffffff
764 05:21:52.780413 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 05:21:52.786335 setenv initrd_high 0xffffffff
767 05:21:52.888193 => setenv fdt_high 0xffffffff
768 05:21:52.888786 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 05:21:52.894386 setenv fdt_high 0xffffffff
771 05:21:52.995662 => dhcp
772 05:21:52.996799 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 05:21:53.000426 dhcp
774 05:21:53.706021 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 05:21:53.706493 Speed: 1000, full duplex
776 05:21:53.706740 BOOTP broadcast 1
777 05:21:53.954819 BOOTP broadcast 2
778 05:21:53.966452 DHCP client bound to address 192.168.6.21 (260 ms)
780 05:21:54.067700 => setenv serverip 192.168.6.2
781 05:21:54.068298 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 05:21:54.072813 setenv serverip 192.168.6.2
784 05:21:54.174003 => tftpboot 0x01080000 927245/tftp-deploy-5jwpanrh/kernel/uImage
785 05:21:54.174552 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 05:21:54.181477 tftpboot 0x01080000 927245/tftp-deploy-5jwpanrh/kernel/uImage
787 05:21:54.181868 Speed: 1000, full duplex
788 05:21:54.182096 Using ethernet@ff3f0000 device
789 05:21:54.187009 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 05:21:54.195478 Filename '927245/tftp-deploy-5jwpanrh/kernel/uImage'.
791 05:21:54.197013 Load address: 0x1080000
792 05:21:57.339563 Loading: *################################################## 43.6 MiB
793 05:21:57.340224 13.9 MiB/s
794 05:21:57.340635 done
795 05:21:57.343941 Bytes transferred = 45713984 (2b98a40 hex)
797 05:21:57.445420 => tftpboot 0x08000000 927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot
798 05:21:57.446074 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 05:21:57.452840 tftpboot 0x08000000 927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot
800 05:21:57.453324 Speed: 1000, full duplex
801 05:21:57.453722 Using ethernet@ff3f0000 device
802 05:21:57.458396 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 05:21:57.468201 Filename '927245/tftp-deploy-5jwpanrh/ramdisk/ramdisk.cpio.gz.uboot'.
804 05:21:57.468552 Load address: 0x8000000
805 05:21:59.051244 Loading: *################################################# UDP wrong checksum 00000005 00008f0c
806 05:22:04.051912 T UDP wrong checksum 00000005 00008f0c
807 05:22:14.053657 T T UDP wrong checksum 00000005 00008f0c
808 05:22:34.057625 T T T T UDP wrong checksum 00000005 00008f0c
809 05:22:44.479707 T T UDP wrong checksum 000000ff 00009ca4
810 05:22:44.488377 UDP wrong checksum 000000ff 00003097
811 05:22:54.061480 T
812 05:22:54.061892 Retry count exceeded; starting again
814 05:22:54.062777 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
817 05:22:54.063779 end: 2.4 uboot-commands (duration 00:01:21) [common]
819 05:22:54.064576 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
821 05:22:54.065155 end: 2 uboot-action (duration 00:01:21) [common]
823 05:22:54.066151 Cleaning after the job
824 05:22:54.066480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/ramdisk
825 05:22:54.067339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/kernel
826 05:22:54.072995 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/dtb
827 05:22:54.073793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927245/tftp-deploy-5jwpanrh/modules
828 05:22:54.079593 start: 4.1 power-off (timeout 00:00:30) [common]
829 05:22:54.080447 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
830 05:22:54.111285 >> OK - accepted request
831 05:22:54.113369 Returned 0 in 0 seconds
832 05:22:54.214282 end: 4.1 power-off (duration 00:00:00) [common]
834 05:22:54.215308 start: 4.2 read-feedback (timeout 00:10:00) [common]
835 05:22:54.216071 Listened to connection for namespace 'common' for up to 1s
836 05:22:55.216996 Finalising connection for namespace 'common'
837 05:22:55.217699 Disconnecting from shell: Finalise
838 05:22:55.218066 =>
839 05:22:55.318902 end: 4.2 read-feedback (duration 00:00:01) [common]
840 05:22:55.319505 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927245
841 05:22:55.615712 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927245
842 05:22:55.616382 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.