Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 4
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:29:08.720456 lava-dispatcher, installed at version: 2024.01
2 05:29:08.721266 start: 0 validate
3 05:29:08.721753 Start time: 2024-11-02 05:29:08.721723+00:00 (UTC)
4 05:29:08.722308 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:29:08.722839 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 05:29:08.760915 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:29:08.761476 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:29:08.797774 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:29:08.798417 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:29:08.831503 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:29:08.832053 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 05:29:08.872974 validate duration: 0.15
14 05:29:08.873837 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:29:08.874172 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:29:08.874483 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:29:08.875097 Not decompressing ramdisk as can be used compressed.
18 05:29:08.875549 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 05:29:08.875829 saving as /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/ramdisk/rootfs.cpio.gz
20 05:29:08.876137 total size: 47897469 (45 MB)
21 05:29:08.917343 progress 0 % (0 MB)
22 05:29:08.948025 progress 5 % (2 MB)
23 05:29:08.977813 progress 10 % (4 MB)
24 05:29:09.010758 progress 15 % (6 MB)
25 05:29:09.040670 progress 20 % (9 MB)
26 05:29:09.070422 progress 25 % (11 MB)
27 05:29:09.100094 progress 30 % (13 MB)
28 05:29:09.134529 progress 35 % (16 MB)
29 05:29:09.171119 progress 40 % (18 MB)
30 05:29:09.203545 progress 45 % (20 MB)
31 05:29:09.233739 progress 50 % (22 MB)
32 05:29:09.263723 progress 55 % (25 MB)
33 05:29:09.294199 progress 60 % (27 MB)
34 05:29:09.324695 progress 65 % (29 MB)
35 05:29:09.355330 progress 70 % (32 MB)
36 05:29:09.385276 progress 75 % (34 MB)
37 05:29:09.416473 progress 80 % (36 MB)
38 05:29:09.445710 progress 85 % (38 MB)
39 05:29:09.475192 progress 90 % (41 MB)
40 05:29:09.504313 progress 95 % (43 MB)
41 05:29:09.533247 progress 100 % (45 MB)
42 05:29:09.533981 45 MB downloaded in 0.66 s (69.44 MB/s)
43 05:29:09.534553 end: 1.1.1 http-download (duration 00:00:01) [common]
45 05:29:09.535480 end: 1.1 download-retry (duration 00:00:01) [common]
46 05:29:09.535790 start: 1.2 download-retry (timeout 00:09:59) [common]
47 05:29:09.536105 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 05:29:09.536623 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kernel/Image
49 05:29:09.536880 saving as /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/kernel/Image
50 05:29:09.537099 total size: 45713920 (43 MB)
51 05:29:09.537316 No compression specified
52 05:29:09.578057 progress 0 % (0 MB)
53 05:29:09.606220 progress 5 % (2 MB)
54 05:29:09.637182 progress 10 % (4 MB)
55 05:29:09.666992 progress 15 % (6 MB)
56 05:29:09.695275 progress 20 % (8 MB)
57 05:29:09.725686 progress 25 % (10 MB)
58 05:29:09.757520 progress 30 % (13 MB)
59 05:29:09.786197 progress 35 % (15 MB)
60 05:29:09.815073 progress 40 % (17 MB)
61 05:29:09.843471 progress 45 % (19 MB)
62 05:29:09.872148 progress 50 % (21 MB)
63 05:29:09.900198 progress 55 % (24 MB)
64 05:29:09.930417 progress 60 % (26 MB)
65 05:29:09.960311 progress 65 % (28 MB)
66 05:29:09.989990 progress 70 % (30 MB)
67 05:29:10.020483 progress 75 % (32 MB)
68 05:29:10.049086 progress 80 % (34 MB)
69 05:29:10.078244 progress 85 % (37 MB)
70 05:29:10.106659 progress 90 % (39 MB)
71 05:29:10.135155 progress 95 % (41 MB)
72 05:29:10.162829 progress 100 % (43 MB)
73 05:29:10.163356 43 MB downloaded in 0.63 s (69.62 MB/s)
74 05:29:10.163853 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:29:10.164732 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:29:10.165033 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:29:10.165398 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:29:10.165971 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 05:29:10.166309 saving as /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 05:29:10.166535 total size: 53209 (0 MB)
82 05:29:10.166826 No compression specified
83 05:29:10.208374 progress 61 % (0 MB)
84 05:29:10.209224 progress 100 % (0 MB)
85 05:29:10.209772 0 MB downloaded in 0.04 s (1.17 MB/s)
86 05:29:10.210248 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:29:10.211079 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:29:10.211351 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:29:10.211626 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:29:10.212113 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/modules.tar.xz
92 05:29:10.212368 saving as /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/modules/modules.tar
93 05:29:10.212582 total size: 11611500 (11 MB)
94 05:29:10.212799 Using unxz to decompress xz
95 05:29:10.252228 progress 0 % (0 MB)
96 05:29:10.333315 progress 5 % (0 MB)
97 05:29:10.423360 progress 10 % (1 MB)
98 05:29:10.511788 progress 15 % (1 MB)
99 05:29:10.587757 progress 20 % (2 MB)
100 05:29:10.663666 progress 25 % (2 MB)
101 05:29:10.742286 progress 30 % (3 MB)
102 05:29:10.827451 progress 35 % (3 MB)
103 05:29:10.903639 progress 40 % (4 MB)
104 05:29:10.988712 progress 45 % (5 MB)
105 05:29:11.070067 progress 50 % (5 MB)
106 05:29:11.148466 progress 55 % (6 MB)
107 05:29:11.229086 progress 60 % (6 MB)
108 05:29:11.313079 progress 65 % (7 MB)
109 05:29:11.394825 progress 70 % (7 MB)
110 05:29:11.478703 progress 75 % (8 MB)
111 05:29:11.563027 progress 80 % (8 MB)
112 05:29:11.643133 progress 85 % (9 MB)
113 05:29:11.712381 progress 90 % (9 MB)
114 05:29:11.810402 progress 95 % (10 MB)
115 05:29:11.907663 progress 100 % (11 MB)
116 05:29:11.920494 11 MB downloaded in 1.71 s (6.48 MB/s)
117 05:29:11.921101 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:29:11.922014 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:29:11.922326 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:29:11.922597 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:29:11.922891 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:29:11.923148 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:29:11.923816 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr
125 05:29:11.924718 makedir: /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin
126 05:29:11.925580 makedir: /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/tests
127 05:29:11.926335 makedir: /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/results
128 05:29:11.927078 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-add-keys
129 05:29:11.928374 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-add-sources
130 05:29:11.929543 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-background-process-start
131 05:29:11.930748 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-background-process-stop
132 05:29:11.931951 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-common-functions
133 05:29:11.933149 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-echo-ipv4
134 05:29:11.934269 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-install-packages
135 05:29:11.935389 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-installed-packages
136 05:29:11.936581 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-os-build
137 05:29:11.937784 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-probe-channel
138 05:29:11.939001 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-probe-ip
139 05:29:11.940146 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-target-ip
140 05:29:11.941279 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-target-mac
141 05:29:11.942374 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-target-storage
142 05:29:11.943443 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-case
143 05:29:11.944661 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-event
144 05:29:11.945775 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-feedback
145 05:29:11.946917 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-raise
146 05:29:11.948158 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-reference
147 05:29:11.949285 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-runner
148 05:29:11.950404 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-set
149 05:29:11.951561 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-test-shell
150 05:29:11.952736 Updating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-install-packages (oe)
151 05:29:11.953914 Updating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/bin/lava-installed-packages (oe)
152 05:29:11.954927 Creating /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/environment
153 05:29:11.955772 LAVA metadata
154 05:29:11.956480 - LAVA_JOB_ID=927237
155 05:29:11.956961 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:29:11.957680 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:29:11.959668 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:29:11.960350 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:29:11.960828 skipped lava-vland-overlay
160 05:29:11.961366 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:29:11.961936 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:29:11.962420 skipped lava-multinode-overlay
163 05:29:11.962962 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:29:11.963511 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:29:11.964091 Loading test definitions
166 05:29:11.964439 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:29:11.964711 Using /lava-927237 at stage 0
168 05:29:11.966036 uuid=927237_1.5.2.4.1 testdef=None
169 05:29:11.966387 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:29:11.966699 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:29:11.968634 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:29:11.969511 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:29:11.971856 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:29:11.972810 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:29:11.975087 runner path: /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/0/tests/0_igt-gpu-panfrost test_uuid 927237_1.5.2.4.1
178 05:29:11.975664 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:29:11.976591 Creating lava-test-runner.conf files
181 05:29:11.976804 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927237/lava-overlay-_zj8g2nr/lava-927237/0 for stage 0
182 05:29:11.977192 - 0_igt-gpu-panfrost
183 05:29:11.977592 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:29:11.977877 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:29:12.004127 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:29:12.004551 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:29:12.004824 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:29:12.005128 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:29:12.005398 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:29:19.302027 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 05:29:19.302567 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 05:29:19.302872 extracting modules file /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk
193 05:29:20.937205 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 05:29:20.937686 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 05:29:20.937964 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927237/compress-overlay-8ivlvslq/overlay-1.5.2.5.tar.gz to ramdisk
196 05:29:20.938179 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927237/compress-overlay-8ivlvslq/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk
197 05:29:20.968012 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:29:20.968385 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 05:29:20.968654 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 05:29:20.968880 Converting downloaded kernel to a uImage
201 05:29:20.969179 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/kernel/Image /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/kernel/uImage
202 05:29:21.480297 output: Image Name:
203 05:29:21.480720 output: Created: Sat Nov 2 05:29:20 2024
204 05:29:21.480930 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:29:21.481136 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 05:29:21.481338 output: Load Address: 01080000
207 05:29:21.481538 output: Entry Point: 01080000
208 05:29:21.481736 output:
209 05:29:21.482067 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:29:21.482334 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:29:21.482607 start: 1.5.7 configure-preseed-file (timeout 00:09:47) [common]
212 05:29:21.482860 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:29:21.483116 start: 1.5.8 compress-ramdisk (timeout 00:09:47) [common]
214 05:29:21.483367 Building ramdisk /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk
215 05:29:28.150001 >> 502411 blocks
216 05:29:48.873048 Adding RAMdisk u-boot header.
217 05:29:48.873631 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk.cpio.gz.uboot
218 05:29:49.566875 output: Image Name:
219 05:29:49.567539 output: Created: Sat Nov 2 05:29:48 2024
220 05:29:49.568065 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:29:49.568537 output: Data Size: 65719470 Bytes = 64179.17 KiB = 62.67 MiB
222 05:29:49.568992 output: Load Address: 00000000
223 05:29:49.569444 output: Entry Point: 00000000
224 05:29:49.569886 output:
225 05:29:49.571032 rename /var/lib/lava/dispatcher/tmp/927237/extract-overlay-ramdisk-oc4vbewa/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/ramdisk/ramdisk.cpio.gz.uboot
226 05:29:49.571832 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 05:29:49.572502 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 05:29:49.573079 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 05:29:49.573573 No LXC device requested
230 05:29:49.574142 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:29:49.574716 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 05:29:49.575271 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:29:49.575723 Checking files for TFTP limit of 4294967296 bytes.
234 05:29:49.578681 end: 1 tftp-deploy (duration 00:00:41) [common]
235 05:29:49.579320 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:29:49.580122 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:29:49.580712 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:29:49.581276 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:29:49.581861 Using kernel file from prepare-kernel: 927237/tftp-deploy-078udmg7/kernel/uImage
240 05:29:49.582561 substitutions:
241 05:29:49.583026 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:29:49.583657 - {DTB_ADDR}: 0x01070000
243 05:29:49.584172 - {DTB}: 927237/tftp-deploy-078udmg7/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 05:29:49.584634 - {INITRD}: 927237/tftp-deploy-078udmg7/ramdisk/ramdisk.cpio.gz.uboot
245 05:29:49.585080 - {KERNEL_ADDR}: 0x01080000
246 05:29:49.585524 - {KERNEL}: 927237/tftp-deploy-078udmg7/kernel/uImage
247 05:29:49.585995 - {LAVA_MAC}: None
248 05:29:49.586533 - {PRESEED_CONFIG}: None
249 05:29:49.587216 - {PRESEED_LOCAL}: None
250 05:29:49.587718 - {RAMDISK_ADDR}: 0x08000000
251 05:29:49.588247 - {RAMDISK}: 927237/tftp-deploy-078udmg7/ramdisk/ramdisk.cpio.gz.uboot
252 05:29:49.588738 - {ROOT_PART}: None
253 05:29:49.589185 - {ROOT}: None
254 05:29:49.589628 - {SERVER_IP}: 192.168.6.2
255 05:29:49.590097 - {TEE_ADDR}: 0x83000000
256 05:29:49.590579 - {TEE}: None
257 05:29:49.591265 Parsed boot commands:
258 05:29:49.591791 - setenv autoload no
259 05:29:49.592293 - setenv initrd_high 0xffffffff
260 05:29:49.592763 - setenv fdt_high 0xffffffff
261 05:29:49.593232 - dhcp
262 05:29:49.593675 - setenv serverip 192.168.6.2
263 05:29:49.594110 - tftpboot 0x01080000 927237/tftp-deploy-078udmg7/kernel/uImage
264 05:29:49.594547 - tftpboot 0x08000000 927237/tftp-deploy-078udmg7/ramdisk/ramdisk.cpio.gz.uboot
265 05:29:49.594984 - tftpboot 0x01070000 927237/tftp-deploy-078udmg7/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 05:29:49.595422 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:29:49.596091 - bootm 0x01080000 0x08000000 0x01070000
268 05:29:49.596745 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:29:49.598513 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:29:49.599041 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 05:29:49.616017 Setting prompt string to ['lava-test: # ']
273 05:29:49.617642 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:29:49.618316 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:29:49.618949 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:29:49.619888 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:29:49.621253 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 05:29:49.668019 >> OK - accepted request
279 05:29:49.670223 Returned 0 in 0 seconds
280 05:29:49.771507 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:29:49.773421 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:29:49.774072 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:29:49.774628 Setting prompt string to ['Hit any key to stop autoboot']
285 05:29:49.775126 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:29:49.776952 Trying 192.168.56.21...
287 05:29:49.777484 Connected to conserv1.
288 05:29:49.777957 Escape character is '^]'.
289 05:29:49.778418
290 05:29:49.778895 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:29:49.779378
292 05:29:56.674760 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 05:29:56.675380 bl2_stage_init 0x01
294 05:29:56.675801 bl2_stage_init 0x81
295 05:29:56.680187 hw id: 0x0000 - pwm id 0x01
296 05:29:56.680646 bl2_stage_init 0xc1
297 05:29:56.685777 bl2_stage_init 0x02
298 05:29:56.686209
299 05:29:56.686617 L0:00000000
300 05:29:56.687007 L1:00000703
301 05:29:56.687392 L2:00008067
302 05:29:56.687778 L3:15000000
303 05:29:56.691338 S1:00000000
304 05:29:56.691759 B2:20282000
305 05:29:56.692196 B1:a0f83180
306 05:29:56.692588
307 05:29:56.692976 TE: 68977
308 05:29:56.693363
309 05:29:56.696974 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 05:29:56.697398
311 05:29:56.702623 Board ID = 1
312 05:29:56.703044 Set cpu clk to 24M
313 05:29:56.703434 Set clk81 to 24M
314 05:29:56.708146 Use GP1_pll as DSU clk.
315 05:29:56.708568 DSU clk: 1200 Mhz
316 05:29:56.708957 CPU clk: 1200 MHz
317 05:29:56.713812 Set clk81 to 166.6M
318 05:29:56.719340 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 05:29:56.719763 board id: 1
320 05:29:56.725604 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:29:56.737488 fw parse done
322 05:29:56.743426 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:29:56.786530 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:29:56.797675 PIEI prepare done
325 05:29:56.798094 fastboot data load
326 05:29:56.798493 fastboot data verify
327 05:29:56.803246 verify result: 266
328 05:29:56.808845 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 05:29:56.809278 LPDDR4 probe
330 05:29:56.809668 ddr clk to 1584MHz
331 05:29:56.816971 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:29:56.854584
333 05:29:56.855038 dmc_version 0001
334 05:29:56.860743 Check phy result
335 05:29:56.867614 INFO : End of CA training
336 05:29:56.868090 INFO : End of initialization
337 05:29:56.873258 INFO : Training has run successfully!
338 05:29:56.873681 Check phy result
339 05:29:56.878835 INFO : End of initialization
340 05:29:56.879254 INFO : End of read enable training
341 05:29:56.884455 INFO : End of fine write leveling
342 05:29:56.890061 INFO : End of Write leveling coarse delay
343 05:29:56.890477 INFO : Training has run successfully!
344 05:29:56.890869 Check phy result
345 05:29:56.895545 INFO : End of initialization
346 05:29:56.895956 INFO : End of read dq deskew training
347 05:29:56.901183 INFO : End of MPR read delay center optimization
348 05:29:56.906845 INFO : End of write delay center optimization
349 05:29:56.912373 INFO : End of read delay center optimization
350 05:29:56.912812 INFO : End of max read latency training
351 05:29:56.917998 INFO : Training has run successfully!
352 05:29:56.918414 1D training succeed
353 05:29:56.927176 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:29:56.975898 Check phy result
355 05:29:56.976393 INFO : End of initialization
356 05:29:57.002897 INFO : End of 2D read delay Voltage center optimization
357 05:29:57.026979 INFO : End of 2D read delay Voltage center optimization
358 05:29:57.083691 INFO : End of 2D write delay Voltage center optimization
359 05:29:57.138063 INFO : End of 2D write delay Voltage center optimization
360 05:29:57.143331 INFO : Training has run successfully!
361 05:29:57.143756
362 05:29:57.144190 channel==0
363 05:29:57.149268 RxClkDly_Margin_A0==69 ps 7
364 05:29:57.149700 TxDqDly_Margin_A0==98 ps 10
365 05:29:57.154515 RxClkDly_Margin_A1==78 ps 8
366 05:29:57.154933 TxDqDly_Margin_A1==88 ps 9
367 05:29:57.155319 TrainedVREFDQ_A0==75
368 05:29:57.160112 TrainedVREFDQ_A1==74
369 05:29:57.160539 VrefDac_Margin_A0==24
370 05:29:57.160926 DeviceVref_Margin_A0==39
371 05:29:57.165732 VrefDac_Margin_A1==22
372 05:29:57.166155 DeviceVref_Margin_A1==40
373 05:29:57.166540
374 05:29:57.166935
375 05:29:57.167323 channel==1
376 05:29:57.171249 RxClkDly_Margin_A0==78 ps 8
377 05:29:57.171674 TxDqDly_Margin_A0==98 ps 10
378 05:29:57.176887 RxClkDly_Margin_A1==88 ps 9
379 05:29:57.177319 TxDqDly_Margin_A1==78 ps 8
380 05:29:57.182490 TrainedVREFDQ_A0==78
381 05:29:57.182933 TrainedVREFDQ_A1==75
382 05:29:57.183324 VrefDac_Margin_A0==22
383 05:29:57.188110 DeviceVref_Margin_A0==36
384 05:29:57.188561 VrefDac_Margin_A1==20
385 05:29:57.193724 DeviceVref_Margin_A1==39
386 05:29:57.194161
387 05:29:57.194553 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:29:57.194940
389 05:29:57.227259 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
390 05:29:57.227789 2D training succeed
391 05:29:57.232833 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:29:57.238425 auto size-- 65535DDR cs0 size: 2048MB
393 05:29:57.238842 DDR cs1 size: 2048MB
394 05:29:57.244085 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:29:57.244506 cs0 DataBus test pass
396 05:29:57.249840 cs1 DataBus test pass
397 05:29:57.250256 cs0 AddrBus test pass
398 05:29:57.250642 cs1 AddrBus test pass
399 05:29:57.251023
400 05:29:57.255276 100bdlr_step_size ps== 485
401 05:29:57.255699 result report
402 05:29:57.260876 boot times 0Enable ddr reg access
403 05:29:57.266028 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:29:57.279932 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 05:29:57.939564 bl2z: ptr: 05129330, size: 00001e40
406 05:29:57.948080 0.0;M3 CHK:0;cm4_sp_mode 0
407 05:29:57.948591 MVN_1=0x00000000
408 05:29:57.948999 MVN_2=0x00000000
409 05:29:57.959576 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 05:29:57.960047 OPS=0x04
411 05:29:57.960455 ring efuse init
412 05:29:57.965177 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 05:29:57.965608 [0.017354 Inits done]
414 05:29:57.966004 secure task start!
415 05:29:57.972094 high task start!
416 05:29:57.972578 low task start!
417 05:29:57.972984 run into bl31
418 05:29:57.981090 NOTICE: BL31: v1.3(release):4fc40b1
419 05:29:57.988992 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 05:29:57.989430 NOTICE: BL31: G12A normal boot!
421 05:29:58.004396 NOTICE: BL31: BL33 decompress pass
422 05:29:58.010118 ERROR: Error initializing runtime service opteed_fast
423 05:29:59.228509 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 05:29:59.229117 bl2_stage_init 0x01
425 05:29:59.229533 bl2_stage_init 0x81
426 05:29:59.233951 hw id: 0x0000 - pwm id 0x01
427 05:29:59.234384 bl2_stage_init 0xc1
428 05:29:59.238146 bl2_stage_init 0x02
429 05:29:59.238577
430 05:29:59.238981 L0:00000000
431 05:29:59.239376 L1:00000703
432 05:29:59.243520 L2:00008067
433 05:29:59.243957 L3:15000000
434 05:29:59.244394 S1:00000000
435 05:29:59.244792 B2:20282000
436 05:29:59.245186 B1:a0f83180
437 05:29:59.245579
438 05:29:59.249226 TE: 71137
439 05:29:59.249674
440 05:29:59.254791 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 05:29:59.255227
442 05:29:59.255642 Board ID = 1
443 05:29:59.256067 Set cpu clk to 24M
444 05:29:59.258416 Set clk81 to 24M
445 05:29:59.258836 Use GP1_pll as DSU clk.
446 05:29:59.263961 DSU clk: 1200 Mhz
447 05:29:59.264416 CPU clk: 1200 MHz
448 05:29:59.264813 Set clk81 to 166.6M
449 05:29:59.269528 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 05:29:59.275114 board id: 1
451 05:29:59.279299 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 05:29:59.291260 fw parse done
453 05:29:59.296649 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 05:29:59.340402 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 05:29:59.351540 PIEI prepare done
456 05:29:59.352056 fastboot data load
457 05:29:59.352478 fastboot data verify
458 05:29:59.357082 verify result: 266
459 05:29:59.365308 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 05:29:59.365778 LPDDR4 probe
461 05:29:59.366180 ddr clk to 1584MHz
462 05:30:00.727337 Load ddrfw from SPI, src SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 05:30:00.728195 bl2_stage_init 0x01
464 05:30:00.728782 bl2_stage_init 0x81
465 05:30:00.732948 hw id: 0x0000 - pwm id 0x01
466 05:30:00.733578 bl2_stage_init 0xc1
467 05:30:00.737486 bl2_stage_init 0x02
468 05:30:00.738108
469 05:30:00.738676 L0:00000000
470 05:30:00.739186 L1:00000703
471 05:30:00.739688 L2:00008067
472 05:30:00.743029 L3:15000000
473 05:30:00.743566 S1:00000000
474 05:30:00.744096 B2:20282000
475 05:30:00.744613 B1:a0f83180
476 05:30:00.745116
477 05:30:00.745621 TE: 71592
478 05:30:00.746129
479 05:30:00.754098 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 05:30:00.754662
481 05:30:00.755173 Board ID = 1
482 05:30:00.755677 Set cpu clk to 24M
483 05:30:00.756228 Set clk81 to 24M
484 05:30:00.759797 Use GP1_pll as DSU clk.
485 05:30:00.760382 DSU clk: 1200 Mhz
486 05:30:00.760894 CPU clk: 1200 MHz
487 05:30:00.765381 Set clk81 to 166.6M
488 05:30:00.771009 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 05:30:00.771605 board id: 1
490 05:30:00.779455 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 05:30:00.790007 fw parse done
492 05:30:00.795925 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 05:30:00.838563 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 05:30:00.849643 PIEI prepare done
495 05:30:00.850270 fastboot data load
496 05:30:00.850784 fastboot data verify
497 05:30:00.855021 verify result: 266
498 05:30:00.860848 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 05:30:00.861617 LPDDR4 probe
500 05:30:00.862139 ddr clk to 1584MHz
501 05:30:00.867867 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 05:30:00.907688
503 05:30:00.908537 dmc_version 0001
504 05:30:00.912623 Check phy result
505 05:30:00.918537 INFO : End of CA training
506 05:30:00.919191 INFO : End of initialization
507 05:30:00.924048 INFO : Training has run successfully!
508 05:30:00.924618 Check phy result
509 05:30:00.929583 INFO : End of initialization
510 05:30:00.930136 INFO : End of read enable training
511 05:30:00.935264 INFO : End of fine write leveling
512 05:30:00.940796 INFO : End of Write leveling coarse delay
513 05:30:00.941380 INFO : Training has run successfully!
514 05:30:00.941911 Check phy result
515 05:30:00.946420 INFO : End of initialization
516 05:30:00.946981 INFO : End of read dq deskew training
517 05:30:00.952060 INFO : End of MPR read delay center optimization
518 05:30:00.957581 INFO : End of write delay center optimization
519 05:30:00.963227 INFO : End of read delay center optimization
520 05:30:00.963784 INFO : End of max read latency training
521 05:30:00.968818 INFO : Training has run successfully!
522 05:30:00.969374 1D training succeed
523 05:30:00.978050 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 05:30:01.025664 Check phy result
525 05:30:01.026352 INFO : End of initialization
526 05:30:01.047805 INFO : End of 2D read delay Voltage center optimization
527 05:30:01.067175 INFO : End of 2D read delay Voltage center optimization
528 05:30:01.119035 INFO : End of 2D write delay Voltage center optimization
529 05:30:01.168312 INFO : End of 2D write delay Voltage center optimization
530 05:30:01.173700 INFO : Training has run successfully!
531 05:30:01.174294
532 05:30:01.174849 channel==0
533 05:30:01.180183 RxClkDly_Margin_A0==78 ps 8
534 05:30:01.180746 TxDqDly_Margin_A0==98 ps 10
535 05:30:01.181308 RxClkDly_Margin_A1==88 ps 9
536 05:30:01.185917 TxDqDly_Margin_A1==98 ps 10
537 05:30:01.186529 TrainedVREFDQ_A0==74
538 05:30:01.191544 TrainedVREFDQ_A1==75
539 05:30:01.192141 VrefDac_Margin_A0==24
540 05:30:01.192679 DeviceVref_Margin_A0==40
541 05:30:01.197633 VrefDac_Margin_A1==23
542 05:30:01.198211 DeviceVref_Margin_A1==39
543 05:30:01.198731
544 05:30:01.199254
545 05:30:01.199767 channel==1
546 05:30:01.202671 RxClkDly_Margin_A0==78 ps 8
547 05:30:01.203219 TxDqDly_Margin_A0==98 ps 10
548 05:30:01.208196 RxClkDly_Margin_A1==78 ps 8
549 05:30:01.208783 TxDqDly_Margin_A1==88 ps 9
550 05:30:01.209317 TrainedVREFDQ_A0==78
551 05:30:01.213832 TrainedVREFDQ_A1==78
552 05:30:01.214393 VrefDac_Margin_A0==22
553 05:30:01.219545 DeviceVref_Margin_A0==36
554 05:30:01.220142 VrefDac_Margin_A1==22
555 05:30:01.220662 DeviceVref_Margin_A1==36
556 05:30:01.221170
557 05:30:01.225065 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 05:30:01.225619
559 05:30:01.258487 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
560 05:30:01.259131 2D training succeed
561 05:30:01.264086 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 05:30:01.269662 auto size-- 65535DDR cs0 size: 2048MB
563 05:30:01.270229 DDR cs1 size: 2048MB
564 05:30:01.275405 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 05:30:01.275976 cs0 DataBus test pass
566 05:30:01.276543 cs1 DataBus test pass
567 05:30:01.280892 cs0 AddrBus test pass
568 05:30:01.281443 cs1 AddrBus test pass
569 05:30:01.281953
570 05:30:01.286488 100bdlr_step_size ps== 478
571 05:30:01.287075 result report
572 05:30:01.287590 boot times 0Enable ddr reg access
573 05:30:01.296549 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 05:30:01.310314 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 05:30:01.965638 bl2z: ptr: 05129330, size: 00001e40
576 05:30:01.971360 0.0;M3 CHK:0;cm4_sp_mode 0
577 05:30:01.971964 MVN_1=0x00000000
578 05:30:01.972534 MVN_2=0x00000000
579 05:30:01.982798 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 05:30:01.983387 OPS=0x04
581 05:30:01.983905 ring efuse init
582 05:30:01.985753 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 05:30:01.991429 [0.017319 Inits done]
584 05:30:01.992032 secure task start!
585 05:30:01.992571 high task start!
586 05:30:01.993087 low task start!
587 05:30:01.995650 run into bl31
588 05:30:02.004270 NOTICE: BL31: v1.3(release):4fc40b1
589 05:30:02.011195 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 05:30:02.011825 NOTICE: BL31: G12A normal boot!
591 05:30:02.027614 NOTICE: BL31: BL33 decompress pass
592 05:30:02.033205 ERROR: Error initializing runtime service opteed_fast
593 05:30:03.277356 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 05:30:03.277783 bl2_stage_init 0x01
595 05:30:03.278007 bl2_stage_init 0x81
596 05:30:03.282848 hw id: 0x0000 - pwm id 0x01
597 05:30:03.283255 bl2_stage_init 0xc1
598 05:30:03.288451 bl2_stage_init 0x02
599 05:30:03.288857
600 05:30:03.289205 L0:00000000
601 05:30:03.289437 L1:00000703
602 05:30:03.289645 L2:00008067
603 05:30:03.289845 L3:15000000
604 05:30:03.294043 S1:00000000
605 05:30:03.294432 B2:20282000
606 05:30:03.294757 B1:a0f83180
607 05:30:03.295151
608 05:30:03.295599 TE: 71447
609 05:30:03.296072
610 05:30:03.299738 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 05:30:03.300038
612 05:30:03.305257 Board ID = 1
613 05:30:03.305655 Set cpu clk to 24M
614 05:30:03.305990 Set clk81 to 24M
615 05:30:03.310949 Use GP1_pll as DSU clk.
616 05:30:03.311283 DSU clk: 1200 Mhz
617 05:30:03.311494 CPU clk: 1200 MHz
618 05:30:03.316431 Set clk81 to 166.6M
619 05:30:03.322098 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 05:30:03.322454 board id: 1
621 05:30:03.329283 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 05:30:03.339912 fw parse done
623 05:30:03.345939 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 05:30:03.388648 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 05:30:03.399388 PIEI prepare done
626 05:30:03.399835 fastboot data load
627 05:30:03.400289 fastboot data verify
628 05:30:03.405034 verify result: 266
629 05:30:03.410882 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 05:30:03.411329 LPDDR4 probe
631 05:30:03.411729 ddr clk to 1584MHz
632 05:30:03.418616 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 05:30:03.455944
634 05:30:03.456457 dmc_version 0001
635 05:30:03.462787 Check phy result
636 05:30:03.468544 INFO : End of CA training
637 05:30:03.469018 INFO : End of initialization
638 05:30:03.474264 INFO : Training has run successfully!
639 05:30:03.474972 Check phy result
640 05:30:03.479919 INFO : End of initialization
641 05:30:03.480570 INFO : End of read enable training
642 05:30:03.485413 INFO : End of fine write leveling
643 05:30:03.491014 INFO : End of Write leveling coarse delay
644 05:30:03.491638 INFO : Training has run successfully!
645 05:30:03.492213 Check phy result
646 05:30:03.496584 INFO : End of initialization
647 05:30:03.497197 INFO : End of read dq deskew training
648 05:30:03.502153 INFO : End of MPR read delay center optimization
649 05:30:03.507918 INFO : End of write delay center optimization
650 05:30:03.513360 INFO : End of read delay center optimization
651 05:30:03.513972 INFO : End of max read latency training
652 05:30:03.519090 INFO : Training has run successfully!
653 05:30:03.519689 1D training succeed
654 05:30:03.528315 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 05:30:03.575787 Check phy result
656 05:30:03.576491 INFO : End of initialization
657 05:30:03.598222 INFO : End of 2D read delay Voltage center optimization
658 05:30:03.617265 INFO : End of 2D read delay Voltage center optimization
659 05:30:03.669067 INFO : End of 2D write delay Voltage center optimization
660 05:30:03.718276 INFO : End of 2D write delay Voltage center optimization
661 05:30:03.723826 INFO : Training has run successfully!
662 05:30:03.724441
663 05:30:03.724981 channel==0
664 05:30:03.729401 RxClkDly_Margin_A0==78 ps 8
665 05:30:03.729965 TxDqDly_Margin_A0==98 ps 10
666 05:30:03.732827 RxClkDly_Margin_A1==88 ps 9
667 05:30:03.733382 TxDqDly_Margin_A1==98 ps 10
668 05:30:03.738315 TrainedVREFDQ_A0==74
669 05:30:03.738867 TrainedVREFDQ_A1==74
670 05:30:03.739399 VrefDac_Margin_A0==24
671 05:30:03.743888 DeviceVref_Margin_A0==40
672 05:30:03.744478 VrefDac_Margin_A1==23
673 05:30:03.749456 DeviceVref_Margin_A1==40
674 05:30:03.750005
675 05:30:03.750535
676 05:30:03.751052 channel==1
677 05:30:03.751563 RxClkDly_Margin_A0==78 ps 8
678 05:30:03.755059 TxDqDly_Margin_A0==98 ps 10
679 05:30:03.755597 RxClkDly_Margin_A1==78 ps 8
680 05:30:03.760757 TxDqDly_Margin_A1==78 ps 8
681 05:30:03.761347 TrainedVREFDQ_A0==75
682 05:30:03.761880 TrainedVREFDQ_A1==75
683 05:30:03.766269 VrefDac_Margin_A0==22
684 05:30:03.766829 DeviceVref_Margin_A0==39
685 05:30:03.771890 VrefDac_Margin_A1==22
686 05:30:03.772454 DeviceVref_Margin_A1==39
687 05:30:03.772979
688 05:30:03.777463 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 05:30:03.778014
690 05:30:03.805495 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
691 05:30:03.811167 2D training succeed
692 05:30:03.816777 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 05:30:03.817340 auto size-- 65535DDR cs0 size: 2048MB
694 05:30:03.822274 DDR cs1 size: 2048MB
695 05:30:03.822818 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 05:30:03.827892 cs0 DataBus test pass
697 05:30:03.828496 cs1 DataBus test pass
698 05:30:03.829015 cs0 AddrBus test pass
699 05:30:03.833491 cs1 AddrBus test pass
700 05:30:03.834039
701 05:30:03.834561 100bdlr_step_size ps== 478
702 05:30:03.835096 result report
703 05:30:03.839146 boot times 0Enable ddr reg access
704 05:30:03.846655 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 05:30:03.860437 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 05:30:04.514296 bl2z: ptr: 05129330, size: 00001e40
707 05:30:04.521967 0.0;M3 CHK:0;cm4_sp_mode 0
708 05:30:04.522564 MVN_1=0x00000000
709 05:30:04.523090 MVN_2=0x00000000
710 05:30:04.533445 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 05:30:04.534027 OPS=0x04
712 05:30:04.534562 ring efuse init
713 05:30:04.539047 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 05:30:04.539631 [0.017319 Inits done]
715 05:30:04.540195 secure task start!
716 05:30:04.546293 high task start!
717 05:30:04.546854 low task start!
718 05:30:04.547389 run into bl31
719 05:30:04.554927 NOTICE: BL31: v1.3(release):4fc40b1
720 05:30:04.562864 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 05:30:04.563423 NOTICE: BL31: G12A normal boot!
722 05:30:04.578286 NOTICE: BL31: BL33 decompress pass
723 05:30:04.584094 ERROR: Error initializing runtime service opteed_fast
724 05:30:05.379364
725 05:30:05.380031
726 05:30:05.384775 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 05:30:05.385268
728 05:30:05.388249 Model: Libre Computer AML-S905D3-CC Solitude
729 05:30:05.535516 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 05:30:05.550972 DRAM: 2 GiB (effective 3.8 GiB)
731 05:30:05.651747 Core: 406 devices, 33 uclasses, devicetree: separate
732 05:30:05.657616 WDT: Not starting watchdog@f0d0
733 05:30:05.682602 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 05:30:05.694835 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 05:30:05.699855 ** Bad device specification mmc 0 **
736 05:30:05.709878 Card did not respond to voltage select! : -110
737 05:30:05.717633 ** Bad device specification mmc 0 **
738 05:30:05.718150 Couldn't find partition mmc 0
739 05:30:05.725836 Card did not respond to voltage select! : -110
740 05:30:05.731416 ** Bad device specification mmc 0 **
741 05:30:05.731923 Couldn't find partition mmc 0
742 05:30:05.736477 Error: could not access storage.
743 05:30:06.033882 Net: eth0: ethernet@ff3f0000
744 05:30:06.034493 starting USB...
745 05:30:06.495358 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 05:30:06.495779 Starting the controller
747 05:30:06.497734 USB XHCI 1.10
748 05:30:07.841880 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 05:30:07.850110 scanning usb for storage devices... 0 Storage Device(s) found
751 05:30:07.901969 Hit any key to stop autoboot: 1
752 05:30:07.902999 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
753 05:30:07.903777 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
754 05:30:07.904452 Setting prompt string to ['=>']
755 05:30:07.905064 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
756 05:30:07.916166 0
757 05:30:07.917251 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 05:30:08.018838 => setenv autoload no
760 05:30:08.019854 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
761 05:30:08.026110 setenv autoload no
763 05:30:08.127925 => setenv initrd_high 0xffffffff
764 05:30:08.128929 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 05:30:08.133316 setenv initrd_high 0xffffffff
767 05:30:08.235176 => setenv fdt_high 0xffffffff
768 05:30:08.235804 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 05:30:08.239965 setenv fdt_high 0xffffffff
771 05:30:08.341146 => dhcp
772 05:30:08.342028 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 05:30:08.345146 dhcp
774 05:30:09.222181 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. Connection closed by foreign host.
776 05:30:09.224897 end: 2.4.3 bootloader-commands (duration 00:00:01) [common]
779 05:30:09.227236 end: 2.4 uboot-commands (duration 00:00:20) [common]
781 05:30:09.229006 uboot-action failed: 1 of 1 attempts. 'Connection closed'
783 05:30:09.230339 end: 2 uboot-action (duration 00:00:20) [common]
785 05:30:09.232422 Cleaning after the job
786 05:30:09.233183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/ramdisk
787 05:30:09.275333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/kernel
788 05:30:09.305847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/dtb
789 05:30:09.306870 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927237/tftp-deploy-078udmg7/modules
790 05:30:09.331255 start: 4.1 power-off (timeout 00:00:30) [common]
791 05:30:09.332141 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
792 05:30:09.362221 >> curl: (7) Failed to connect to conserv1.mayfield.sirena.org.uk port 16421 after 2 ms: Couldn't connect to server
793 05:30:09.364298 Returned 7 in 0 seconds
794 05:30:09.364821 Unable to run '['curl', 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01']'
796 05:30:09.365443 end: 4.1 power-off (duration 00:00:00) [common]
798 05:30:09.366172 Failed to run 'finalize': Unable to power-off: 'curl http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix\&port=solitude-01' failed
800 05:30:09.476902 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927237
801 05:30:10.087839 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927237
802 05:30:10.088447 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.