Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:34:09.088592 lava-dispatcher, installed at version: 2024.01
2 05:34:09.089392 start: 0 validate
3 05:34:09.089876 Start time: 2024-11-02 05:34:09.089846+00:00 (UTC)
4 05:34:09.090408 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:34:09.090950 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:34:09.133435 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:34:09.133966 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:34:09.167501 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:34:09.168140 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:34:09.200505 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:34:09.201010 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:34:09.234985 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:34:09.235501 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:34:09.283255 validate duration: 0.19
16 05:34:09.284773 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:34:09.285378 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:34:09.285973 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:34:09.286937 Not decompressing ramdisk as can be used compressed.
20 05:34:09.287697 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 05:34:09.288253 saving as /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/ramdisk/initrd.cpio.gz
22 05:34:09.288770 total size: 5628169 (5 MB)
23 05:34:09.334943 progress 0 % (0 MB)
24 05:34:09.343418 progress 5 % (0 MB)
25 05:34:09.352399 progress 10 % (0 MB)
26 05:34:09.360033 progress 15 % (0 MB)
27 05:34:09.368550 progress 20 % (1 MB)
28 05:34:09.375433 progress 25 % (1 MB)
29 05:34:09.379768 progress 30 % (1 MB)
30 05:34:09.383845 progress 35 % (1 MB)
31 05:34:09.387431 progress 40 % (2 MB)
32 05:34:09.391452 progress 45 % (2 MB)
33 05:34:09.395126 progress 50 % (2 MB)
34 05:34:09.399122 progress 55 % (2 MB)
35 05:34:09.403175 progress 60 % (3 MB)
36 05:34:09.406834 progress 65 % (3 MB)
37 05:34:09.410824 progress 70 % (3 MB)
38 05:34:09.414478 progress 75 % (4 MB)
39 05:34:09.418482 progress 80 % (4 MB)
40 05:34:09.422137 progress 85 % (4 MB)
41 05:34:09.426185 progress 90 % (4 MB)
42 05:34:09.430087 progress 95 % (5 MB)
43 05:34:09.433358 progress 100 % (5 MB)
44 05:34:09.434003 5 MB downloaded in 0.15 s (36.96 MB/s)
45 05:34:09.434544 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:34:09.435457 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:34:09.435767 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:34:09.436156 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:34:09.436678 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kernel/Image
51 05:34:09.436932 saving as /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/kernel/Image
52 05:34:09.437156 total size: 45713920 (43 MB)
53 05:34:09.437374 No compression specified
54 05:34:09.479068 progress 0 % (0 MB)
55 05:34:09.506485 progress 5 % (2 MB)
56 05:34:09.534202 progress 10 % (4 MB)
57 05:34:09.561924 progress 15 % (6 MB)
58 05:34:09.589496 progress 20 % (8 MB)
59 05:34:09.616823 progress 25 % (10 MB)
60 05:34:09.644377 progress 30 % (13 MB)
61 05:34:09.671888 progress 35 % (15 MB)
62 05:34:09.699349 progress 40 % (17 MB)
63 05:34:09.726355 progress 45 % (19 MB)
64 05:34:09.754259 progress 50 % (21 MB)
65 05:34:09.781537 progress 55 % (24 MB)
66 05:34:09.809065 progress 60 % (26 MB)
67 05:34:09.836021 progress 65 % (28 MB)
68 05:34:09.863596 progress 70 % (30 MB)
69 05:34:09.891117 progress 75 % (32 MB)
70 05:34:09.918708 progress 80 % (34 MB)
71 05:34:09.946257 progress 85 % (37 MB)
72 05:34:09.973688 progress 90 % (39 MB)
73 05:34:10.001225 progress 95 % (41 MB)
74 05:34:10.028232 progress 100 % (43 MB)
75 05:34:10.028747 43 MB downloaded in 0.59 s (73.69 MB/s)
76 05:34:10.029214 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:34:10.030023 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:34:10.030295 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:34:10.030558 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:34:10.031018 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:34:10.031280 saving as /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:34:10.031488 total size: 54703 (0 MB)
84 05:34:10.031695 No compression specified
85 05:34:10.073714 progress 59 % (0 MB)
86 05:34:10.074565 progress 100 % (0 MB)
87 05:34:10.075109 0 MB downloaded in 0.04 s (1.20 MB/s)
88 05:34:10.075596 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:34:10.076473 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:34:10.076743 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:34:10.077009 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:34:10.077471 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 05:34:10.077712 saving as /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/nfsrootfs/full.rootfs.tar
95 05:34:10.077917 total size: 120894716 (115 MB)
96 05:34:10.078127 Using unxz to decompress xz
97 05:34:10.111237 progress 0 % (0 MB)
98 05:34:10.942067 progress 5 % (5 MB)
99 05:34:11.781556 progress 10 % (11 MB)
100 05:34:12.575351 progress 15 % (17 MB)
101 05:34:13.313453 progress 20 % (23 MB)
102 05:34:13.909362 progress 25 % (28 MB)
103 05:34:14.738075 progress 30 % (34 MB)
104 05:34:15.531929 progress 35 % (40 MB)
105 05:34:15.881478 progress 40 % (46 MB)
106 05:34:16.269259 progress 45 % (51 MB)
107 05:34:16.989193 progress 50 % (57 MB)
108 05:34:17.870308 progress 55 % (63 MB)
109 05:34:18.651614 progress 60 % (69 MB)
110 05:34:19.407107 progress 65 % (74 MB)
111 05:34:20.179410 progress 70 % (80 MB)
112 05:34:20.999834 progress 75 % (86 MB)
113 05:34:21.794044 progress 80 % (92 MB)
114 05:34:22.563820 progress 85 % (98 MB)
115 05:34:23.507619 progress 90 % (103 MB)
116 05:34:24.311477 progress 95 % (109 MB)
117 05:34:25.144172 progress 100 % (115 MB)
118 05:34:25.156663 115 MB downloaded in 15.08 s (7.65 MB/s)
119 05:34:25.157241 end: 1.4.1 http-download (duration 00:00:15) [common]
121 05:34:25.158057 end: 1.4 download-retry (duration 00:00:15) [common]
122 05:34:25.158320 start: 1.5 download-retry (timeout 00:09:44) [common]
123 05:34:25.158580 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 05:34:25.159078 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/modules.tar.xz
125 05:34:25.159319 saving as /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/modules/modules.tar
126 05:34:25.159523 total size: 11611500 (11 MB)
127 05:34:25.159733 Using unxz to decompress xz
128 05:34:25.203894 progress 0 % (0 MB)
129 05:34:25.283472 progress 5 % (0 MB)
130 05:34:25.376206 progress 10 % (1 MB)
131 05:34:25.471667 progress 15 % (1 MB)
132 05:34:25.561603 progress 20 % (2 MB)
133 05:34:25.650780 progress 25 % (2 MB)
134 05:34:25.744681 progress 30 % (3 MB)
135 05:34:25.835342 progress 35 % (3 MB)
136 05:34:25.925771 progress 40 % (4 MB)
137 05:34:26.024228 progress 45 % (5 MB)
138 05:34:26.105559 progress 50 % (5 MB)
139 05:34:26.184442 progress 55 % (6 MB)
140 05:34:26.267047 progress 60 % (6 MB)
141 05:34:26.350589 progress 65 % (7 MB)
142 05:34:26.432190 progress 70 % (7 MB)
143 05:34:26.508817 progress 75 % (8 MB)
144 05:34:26.590427 progress 80 % (8 MB)
145 05:34:26.669876 progress 85 % (9 MB)
146 05:34:26.737778 progress 90 % (9 MB)
147 05:34:26.836381 progress 95 % (10 MB)
148 05:34:26.933364 progress 100 % (11 MB)
149 05:34:26.945148 11 MB downloaded in 1.79 s (6.20 MB/s)
150 05:34:26.945858 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:34:26.947485 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:34:26.948056 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 05:34:26.948599 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 05:34:43.224688 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927296/extract-nfsrootfs-104cqahr
156 05:34:43.225303 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 05:34:43.225623 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 05:34:43.226284 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j
159 05:34:43.226756 makedir: /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin
160 05:34:43.227139 makedir: /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/tests
161 05:34:43.227508 makedir: /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/results
162 05:34:43.227878 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-add-keys
163 05:34:43.228452 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-add-sources
164 05:34:43.228993 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-background-process-start
165 05:34:43.229576 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-background-process-stop
166 05:34:43.230107 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-common-functions
167 05:34:43.230587 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-echo-ipv4
168 05:34:43.231053 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-install-packages
169 05:34:43.231512 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-installed-packages
170 05:34:43.231967 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-os-build
171 05:34:43.232469 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-probe-channel
172 05:34:43.232933 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-probe-ip
173 05:34:43.233414 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-target-ip
174 05:34:43.233888 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-target-mac
175 05:34:43.234357 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-target-storage
176 05:34:43.234820 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-case
177 05:34:43.235280 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-event
178 05:34:43.235814 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-feedback
179 05:34:43.236316 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-raise
180 05:34:43.236777 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-reference
181 05:34:43.237254 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-runner
182 05:34:43.237732 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-set
183 05:34:43.238192 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-test-shell
184 05:34:43.238662 Updating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-add-keys (debian)
185 05:34:43.239171 Updating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-add-sources (debian)
186 05:34:43.239654 Updating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-install-packages (debian)
187 05:34:43.240171 Updating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-installed-packages (debian)
188 05:34:43.240667 Updating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/bin/lava-os-build (debian)
189 05:34:43.241090 Creating /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/environment
190 05:34:43.241444 LAVA metadata
191 05:34:43.241696 - LAVA_JOB_ID=927296
192 05:34:43.241910 - LAVA_DISPATCHER_IP=192.168.6.2
193 05:34:43.242261 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 05:34:43.243185 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 05:34:43.243487 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 05:34:43.243692 skipped lava-vland-overlay
197 05:34:43.243931 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 05:34:43.244213 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 05:34:43.244429 skipped lava-multinode-overlay
200 05:34:43.244672 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 05:34:43.244921 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 05:34:43.245163 Loading test definitions
203 05:34:43.245434 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 05:34:43.245652 Using /lava-927296 at stage 0
205 05:34:43.246710 uuid=927296_1.6.2.4.1 testdef=None
206 05:34:43.247007 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 05:34:43.247267 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 05:34:43.248804 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 05:34:43.249581 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 05:34:43.251447 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 05:34:43.252330 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 05:34:43.254128 runner path: /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/0/tests/0_timesync-off test_uuid 927296_1.6.2.4.1
215 05:34:43.254674 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 05:34:43.255479 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 05:34:43.255700 Using /lava-927296 at stage 0
219 05:34:43.256275 Fetching tests from https://github.com/kernelci/test-definitions.git
220 05:34:43.256580 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/0/tests/1_kselftest-rtc'
221 05:34:46.777971 Running '/usr/bin/git checkout kernelci.org
222 05:34:47.227947 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 05:34:47.229374 uuid=927296_1.6.2.4.5 testdef=None
224 05:34:47.229714 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 05:34:47.230457 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 05:34:47.233326 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 05:34:47.234140 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 05:34:47.237854 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 05:34:47.238702 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 05:34:47.242267 runner path: /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/0/tests/1_kselftest-rtc test_uuid 927296_1.6.2.4.5
234 05:34:47.242547 BOARD='meson-g12b-a311d-libretech-cc'
235 05:34:47.242752 BRANCH='mainline'
236 05:34:47.242950 SKIPFILE='/dev/null'
237 05:34:47.243147 SKIP_INSTALL='True'
238 05:34:47.243341 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 05:34:47.243540 TST_CASENAME=''
240 05:34:47.243735 TST_CMDFILES='rtc'
241 05:34:47.244275 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 05:34:47.245058 Creating lava-test-runner.conf files
244 05:34:47.245260 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927296/lava-overlay-y_bx3t1j/lava-927296/0 for stage 0
245 05:34:47.245597 - 0_timesync-off
246 05:34:47.245828 - 1_kselftest-rtc
247 05:34:47.246147 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 05:34:47.246421 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 05:35:10.445316 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 05:35:10.445947 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 05:35:10.446396 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 05:35:10.446777 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 05:35:10.447253 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 05:35:11.059227 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 05:35:11.059697 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 05:35:11.059972 extracting modules file /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927296/extract-nfsrootfs-104cqahr
257 05:35:12.511849 extracting modules file /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927296/extract-overlay-ramdisk-un694mjl/ramdisk
258 05:35:13.912329 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 05:35:13.912805 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 05:35:13.913109 [common] Applying overlay to NFS
261 05:35:13.913339 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927296/compress-overlay-o2jew35n/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927296/extract-nfsrootfs-104cqahr
262 05:35:16.656099 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 05:35:16.656569 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 05:35:16.656881 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 05:35:16.657146 Converting downloaded kernel to a uImage
266 05:35:16.657477 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/kernel/Image /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/kernel/uImage
267 05:35:17.134934 output: Image Name:
268 05:35:17.135368 output: Created: Sat Nov 2 05:35:16 2024
269 05:35:17.135599 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 05:35:17.135815 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 05:35:17.136060 output: Load Address: 01080000
272 05:35:17.136275 output: Entry Point: 01080000
273 05:35:17.136481 output:
274 05:35:17.136822 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 05:35:17.137104 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 05:35:17.137386 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 05:35:17.137654 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 05:35:17.137924 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 05:35:17.138191 Building ramdisk /var/lib/lava/dispatcher/tmp/927296/extract-overlay-ramdisk-un694mjl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927296/extract-overlay-ramdisk-un694mjl/ramdisk
280 05:35:19.285222 >> 166823 blocks
281 05:35:27.014007 Adding RAMdisk u-boot header.
282 05:35:27.014720 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927296/extract-overlay-ramdisk-un694mjl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927296/extract-overlay-ramdisk-un694mjl/ramdisk.cpio.gz.uboot
283 05:35:27.287371 output: Image Name:
284 05:35:27.287800 output: Created: Sat Nov 2 05:35:27 2024
285 05:35:27.288072 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 05:35:27.288494 output: Data Size: 23435807 Bytes = 22886.53 KiB = 22.35 MiB
287 05:35:27.288895 output: Load Address: 00000000
288 05:35:27.289288 output: Entry Point: 00000000
289 05:35:27.289683 output:
290 05:35:27.290643 rename /var/lib/lava/dispatcher/tmp/927296/extract-overlay-ramdisk-un694mjl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot
291 05:35:27.291357 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 05:35:27.291896 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 05:35:27.292458 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 05:35:27.292915 No LXC device requested
295 05:35:27.293412 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 05:35:27.293917 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 05:35:27.294409 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 05:35:27.294815 Checking files for TFTP limit of 4294967296 bytes.
299 05:35:27.297503 end: 1 tftp-deploy (duration 00:01:18) [common]
300 05:35:27.298074 start: 2 uboot-action (timeout 00:05:00) [common]
301 05:35:27.298597 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 05:35:27.299091 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 05:35:27.299593 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 05:35:27.300149 Using kernel file from prepare-kernel: 927296/tftp-deploy-nm2stz6z/kernel/uImage
305 05:35:27.300780 substitutions:
306 05:35:27.301187 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 05:35:27.301588 - {DTB_ADDR}: 0x01070000
308 05:35:27.301985 - {DTB}: 927296/tftp-deploy-nm2stz6z/dtb/meson-g12b-a311d-libretech-cc.dtb
309 05:35:27.302386 - {INITRD}: 927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot
310 05:35:27.302784 - {KERNEL_ADDR}: 0x01080000
311 05:35:27.303176 - {KERNEL}: 927296/tftp-deploy-nm2stz6z/kernel/uImage
312 05:35:27.303567 - {LAVA_MAC}: None
313 05:35:27.304016 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927296/extract-nfsrootfs-104cqahr
314 05:35:27.304432 - {NFS_SERVER_IP}: 192.168.6.2
315 05:35:27.304827 - {PRESEED_CONFIG}: None
316 05:35:27.305219 - {PRESEED_LOCAL}: None
317 05:35:27.305612 - {RAMDISK_ADDR}: 0x08000000
318 05:35:27.305998 - {RAMDISK}: 927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot
319 05:35:27.306388 - {ROOT_PART}: None
320 05:35:27.306775 - {ROOT}: None
321 05:35:27.307159 - {SERVER_IP}: 192.168.6.2
322 05:35:27.307542 - {TEE_ADDR}: 0x83000000
323 05:35:27.307928 - {TEE}: None
324 05:35:27.308342 Parsed boot commands:
325 05:35:27.308720 - setenv autoload no
326 05:35:27.309107 - setenv initrd_high 0xffffffff
327 05:35:27.309488 - setenv fdt_high 0xffffffff
328 05:35:27.309870 - dhcp
329 05:35:27.310251 - setenv serverip 192.168.6.2
330 05:35:27.310637 - tftpboot 0x01080000 927296/tftp-deploy-nm2stz6z/kernel/uImage
331 05:35:27.311025 - tftpboot 0x08000000 927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot
332 05:35:27.311412 - tftpboot 0x01070000 927296/tftp-deploy-nm2stz6z/dtb/meson-g12b-a311d-libretech-cc.dtb
333 05:35:27.311797 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927296/extract-nfsrootfs-104cqahr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 05:35:27.312222 - bootm 0x01080000 0x08000000 0x01070000
335 05:35:27.312724 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 05:35:27.314196 start: 2.3 connect-device (timeout 00:05:00) [common]
338 05:35:27.314609 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 05:35:27.330971 Setting prompt string to ['lava-test: # ']
340 05:35:27.332545 end: 2.3 connect-device (duration 00:00:00) [common]
341 05:35:27.333160 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 05:35:27.333716 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 05:35:27.334230 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 05:35:27.335376 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 05:35:27.372443 >> OK - accepted request
346 05:35:27.374557 Returned 0 in 0 seconds
347 05:35:27.475603 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 05:35:27.477193 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 05:35:27.477748 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 05:35:27.478243 Setting prompt string to ['Hit any key to stop autoboot']
352 05:35:27.478681 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 05:35:27.480235 Trying 192.168.56.21...
354 05:35:27.480714 Connected to conserv1.
355 05:35:27.481121 Escape character is '^]'.
356 05:35:27.481528
357 05:35:27.481944 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 05:35:27.482356
359 05:35:39.125047 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 05:35:39.125676 bl2_stage_init 0x81
361 05:35:39.130488 hw id: 0x0000 - pwm id 0x01
362 05:35:39.130945 bl2_stage_init 0xc1
363 05:35:39.131354 bl2_stage_init 0x02
364 05:35:39.131757
365 05:35:39.136076 L0:00000000
366 05:35:39.136530 L1:20000703
367 05:35:39.136944 L2:00008067
368 05:35:39.137347 L3:14000000
369 05:35:39.137753 B2:00402000
370 05:35:39.138861 B1:e0f83180
371 05:35:39.139294
372 05:35:39.139706 TE: 58150
373 05:35:39.140133
374 05:35:39.149988 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 05:35:39.150424
376 05:35:39.150816 Board ID = 1
377 05:35:39.151202 Set A53 clk to 24M
378 05:35:39.151585 Set A73 clk to 24M
379 05:35:39.155611 Set clk81 to 24M
380 05:35:39.156062 A53 clk: 1200 MHz
381 05:35:39.156455 A73 clk: 1200 MHz
382 05:35:39.161165 CLK81: 166.6M
383 05:35:39.161580 smccc: 00012aac
384 05:35:39.166933 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 05:35:39.167352 board id: 1
386 05:35:39.175427 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 05:35:39.186242 fw parse done
388 05:35:39.192076 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 05:35:39.234691 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 05:35:39.245488 PIEI prepare done
391 05:35:39.245931 fastboot data load
392 05:35:39.246338 fastboot data verify
393 05:35:39.251108 verify result: 266
394 05:35:39.256789 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 05:35:39.257214 LPDDR4 probe
396 05:35:39.257607 ddr clk to 1584MHz
397 05:35:39.264801 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 05:35:39.302076
399 05:35:39.302559 dmc_version 0001
400 05:35:39.308584 Check phy result
401 05:35:39.314426 INFO : End of CA training
402 05:35:39.314847 INFO : End of initialization
403 05:35:39.320175 INFO : Training has run successfully!
404 05:35:39.320594 Check phy result
405 05:35:39.325657 INFO : End of initialization
406 05:35:39.326072 INFO : End of read enable training
407 05:35:39.331251 INFO : End of fine write leveling
408 05:35:39.336857 INFO : End of Write leveling coarse delay
409 05:35:39.337274 INFO : Training has run successfully!
410 05:35:39.337664 Check phy result
411 05:35:39.342450 INFO : End of initialization
412 05:35:39.342875 INFO : End of read dq deskew training
413 05:35:39.348168 INFO : End of MPR read delay center optimization
414 05:35:39.353654 INFO : End of write delay center optimization
415 05:35:39.359221 INFO : End of read delay center optimization
416 05:35:39.359635 INFO : End of max read latency training
417 05:35:39.364848 INFO : Training has run successfully!
418 05:35:39.365266 1D training succeed
419 05:35:39.374055 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 05:35:39.421738 Check phy result
421 05:35:39.422170 INFO : End of initialization
422 05:35:39.444249 INFO : End of 2D read delay Voltage center optimization
423 05:35:39.464493 INFO : End of 2D read delay Voltage center optimization
424 05:35:39.516630 INFO : End of 2D write delay Voltage center optimization
425 05:35:39.566019 INFO : End of 2D write delay Voltage center optimization
426 05:35:39.571480 INFO : Training has run successfully!
427 05:35:39.571928
428 05:35:39.572377 channel==0
429 05:35:39.577259 RxClkDly_Margin_A0==88 ps 9
430 05:35:39.577685 TxDqDly_Margin_A0==98 ps 10
431 05:35:39.582645 RxClkDly_Margin_A1==88 ps 9
432 05:35:39.583062 TxDqDly_Margin_A1==98 ps 10
433 05:35:39.583455 TrainedVREFDQ_A0==74
434 05:35:39.588237 TrainedVREFDQ_A1==76
435 05:35:39.588663 VrefDac_Margin_A0==24
436 05:35:39.589054 DeviceVref_Margin_A0==40
437 05:35:39.593948 VrefDac_Margin_A1==25
438 05:35:39.594368 DeviceVref_Margin_A1==38
439 05:35:39.594757
440 05:35:39.595150
441 05:35:39.599413 channel==1
442 05:35:39.599834 RxClkDly_Margin_A0==98 ps 10
443 05:35:39.600258 TxDqDly_Margin_A0==88 ps 9
444 05:35:39.605144 RxClkDly_Margin_A1==88 ps 9
445 05:35:39.605559 TxDqDly_Margin_A1==88 ps 9
446 05:35:39.610651 TrainedVREFDQ_A0==76
447 05:35:39.611068 TrainedVREFDQ_A1==77
448 05:35:39.611460 VrefDac_Margin_A0==22
449 05:35:39.616216 DeviceVref_Margin_A0==38
450 05:35:39.616630 VrefDac_Margin_A1==24
451 05:35:39.621906 DeviceVref_Margin_A1==37
452 05:35:39.622336
453 05:35:39.622727 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 05:35:39.623116
455 05:35:39.655437 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000019 00000017 00000018 00000017 00000018 00000016 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
456 05:35:39.655964 2D training succeed
457 05:35:39.661169 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 05:35:39.666611 auto size-- 65535DDR cs0 size: 2048MB
459 05:35:39.667036 DDR cs1 size: 2048MB
460 05:35:39.672223 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 05:35:39.672636 cs0 DataBus test pass
462 05:35:39.677811 cs1 DataBus test pass
463 05:35:39.678227 cs0 AddrBus test pass
464 05:35:39.678612 cs1 AddrBus test pass
465 05:35:39.678997
466 05:35:39.683502 100bdlr_step_size ps== 420
467 05:35:39.683925 result report
468 05:35:39.689170 boot times 0Enable ddr reg access
469 05:35:39.694385 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 05:35:39.707778 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 05:35:40.281532 0.0;M3 CHK:0;cm4_sp_mode 0
472 05:35:40.282149 MVN_1=0x00000000
473 05:35:40.287015 MVN_2=0x00000000
474 05:35:40.292713 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 05:35:40.293139 OPS=0x10
476 05:35:40.293538 ring efuse init
477 05:35:40.293928 chipver efuse init
478 05:35:40.298352 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 05:35:40.303940 [0.018961 Inits done]
480 05:35:40.304422 secure task start!
481 05:35:40.304818 high task start!
482 05:35:40.308497 low task start!
483 05:35:40.308929 run into bl31
484 05:35:40.315192 NOTICE: BL31: v1.3(release):4fc40b1
485 05:35:40.322089 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 05:35:40.322520 NOTICE: BL31: G12A normal boot!
487 05:35:40.348448 NOTICE: BL31: BL33 decompress pass
488 05:35:40.354149 ERROR: Error initializing runtime service opteed_fast
489 05:35:41.587085
490 05:35:41.587758
491 05:35:41.595367 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 05:35:41.595875
493 05:35:41.596331 Model: Libre Computer AML-A311D-CC Alta
494 05:35:41.803897 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 05:35:41.827155 DRAM: 2 GiB (effective 3.8 GiB)
496 05:35:41.970225 Core: 408 devices, 31 uclasses, devicetree: separate
497 05:35:41.976021 WDT: Not starting watchdog@f0d0
498 05:35:42.008369 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 05:35:42.020714 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 05:35:42.025696 ** Bad device specification mmc 0 **
501 05:35:42.036068 Card did not respond to voltage select! : -110
502 05:35:42.043677 ** Bad device specification mmc 0 **
503 05:35:42.044145 Couldn't find partition mmc 0
504 05:35:42.052151 Card did not respond to voltage select! : -110
505 05:35:42.057547 ** Bad device specification mmc 0 **
506 05:35:42.057981 Couldn't find partition mmc 0
507 05:35:42.062598 Error: could not access storage.
508 05:35:43.325024 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 05:35:43.325468 bl2_stage_init 0x01
510 05:35:43.325707 bl2_stage_init 0x81
511 05:35:43.330464 hw id: 0x0000 - pwm id 0x01
512 05:35:43.330813 bl2_stage_init 0xc1
513 05:35:43.331051 bl2_stage_init 0x02
514 05:35:43.331268
515 05:35:43.336114 L0:00000000
516 05:35:43.336490 L1:20000703
517 05:35:43.336864 L2:00008067
518 05:35:43.337283 L3:14000000
519 05:35:43.341739 B2:00402000
520 05:35:43.342148 B1:e0f83180
521 05:35:43.342372
522 05:35:43.342588 TE: 58167
523 05:35:43.342797
524 05:35:43.347352 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 05:35:43.347685
526 05:35:43.348223 Board ID = 1
527 05:35:43.352995 Set A53 clk to 24M
528 05:35:43.353662 Set A73 clk to 24M
529 05:35:43.354155 Set clk81 to 24M
530 05:35:43.358598 A53 clk: 1200 MHz
531 05:35:43.359189 A73 clk: 1200 MHz
532 05:35:43.359627 CLK81: 166.6M
533 05:35:43.359879 smccc: 00012abe
534 05:35:43.364253 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 05:35:43.369947 board id: 1
536 05:35:43.376972 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 05:35:43.386797 fw parse done
538 05:35:43.392607 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 05:35:43.434852 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 05:35:43.445890 PIEI prepare done
541 05:35:43.446526 fastboot data load
542 05:35:43.447017 fastboot data verify
543 05:35:43.451592 verify result: 266
544 05:35:43.457134 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 05:35:43.457745 LPDDR4 probe
546 05:35:43.458223 ddr clk to 1584MHz
547 05:35:43.465145 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 05:35:43.502295
549 05:35:43.502940 dmc_version 0001
550 05:35:43.509093 Check phy result
551 05:35:43.514917 INFO : End of CA training
552 05:35:43.515546 INFO : End of initialization
553 05:35:43.520615 INFO : Training has run successfully!
554 05:35:43.521253 Check phy result
555 05:35:43.526385 INFO : End of initialization
556 05:35:43.527244 INFO : End of read enable training
557 05:35:43.532409 INFO : End of fine write leveling
558 05:35:43.537839 INFO : End of Write leveling coarse delay
559 05:35:43.538502 INFO : Training has run successfully!
560 05:35:43.538982 Check phy result
561 05:35:43.543590 INFO : End of initialization
562 05:35:43.544153 INFO : End of read dq deskew training
563 05:35:43.551406 INFO : End of MPR read delay center optimization
564 05:35:43.554038 INFO : End of write delay center optimization
565 05:35:43.560284 INFO : End of read delay center optimization
566 05:35:43.561736 INFO : End of max read latency training
567 05:35:43.565319 INFO : Training has run successfully!
568 05:35:43.565684 1D training succeed
569 05:35:43.574455 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 05:35:43.622193 Check phy result
571 05:35:43.622840 INFO : End of initialization
572 05:35:43.643714 INFO : End of 2D read delay Voltage center optimization
573 05:35:43.663928 INFO : End of 2D read delay Voltage center optimization
574 05:35:43.715748 INFO : End of 2D write delay Voltage center optimization
575 05:35:43.764872 INFO : End of 2D write delay Voltage center optimization
576 05:35:43.770457 INFO : Training has run successfully!
577 05:35:43.771010
578 05:35:43.771480 channel==0
579 05:35:43.776062 RxClkDly_Margin_A0==88 ps 9
580 05:35:43.776608 TxDqDly_Margin_A0==98 ps 10
581 05:35:43.781692 RxClkDly_Margin_A1==88 ps 9
582 05:35:43.782244 TxDqDly_Margin_A1==98 ps 10
583 05:35:43.782710 TrainedVREFDQ_A0==74
584 05:35:43.787261 TrainedVREFDQ_A1==74
585 05:35:43.787800 VrefDac_Margin_A0==25
586 05:35:43.788306 DeviceVref_Margin_A0==40
587 05:35:43.792868 VrefDac_Margin_A1==25
588 05:35:43.793401 DeviceVref_Margin_A1==40
589 05:35:43.793863
590 05:35:43.794313
591 05:35:43.798448 channel==1
592 05:35:43.798983 RxClkDly_Margin_A0==98 ps 10
593 05:35:43.799443 TxDqDly_Margin_A0==98 ps 10
594 05:35:43.804032 RxClkDly_Margin_A1==98 ps 10
595 05:35:43.804566 TxDqDly_Margin_A1==88 ps 9
596 05:35:43.809751 TrainedVREFDQ_A0==77
597 05:35:43.810291 TrainedVREFDQ_A1==77
598 05:35:43.810752 VrefDac_Margin_A0==22
599 05:35:43.815238 DeviceVref_Margin_A0==37
600 05:35:43.815776 VrefDac_Margin_A1==22
601 05:35:43.820853 DeviceVref_Margin_A1==37
602 05:35:43.821406
603 05:35:43.821868 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 05:35:43.826431
605 05:35:43.854398 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
606 05:35:43.855005 2D training succeed
607 05:35:43.860073 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 05:35:43.865715 auto size-- 65535DDR cs0 size: 2048MB
609 05:35:43.866254 DDR cs1 size: 2048MB
610 05:35:43.871233 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 05:35:43.871772 cs0 DataBus test pass
612 05:35:43.876851 cs1 DataBus test pass
613 05:35:43.877390 cs0 AddrBus test pass
614 05:35:43.877856 cs1 AddrBus test pass
615 05:35:43.878308
616 05:35:43.882444 100bdlr_step_size ps== 420
617 05:35:43.882999 result report
618 05:35:43.888062 boot times 0Enable ddr reg access
619 05:35:43.893449 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 05:35:43.906884 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 05:35:44.479140 0.0;M3 CHK:0;cm4_sp_mode 0
622 05:35:44.479823 MVN_1=0x00000000
623 05:35:44.484580 MVN_2=0x00000000
624 05:35:44.490239 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 05:35:44.490808 OPS=0x10
626 05:35:44.491281 ring efuse init
627 05:35:44.491754 chipver efuse init
628 05:35:44.498727 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 05:35:44.499312 [0.018961 Inits done]
630 05:35:44.499749 secure task start!
631 05:35:44.506032 high task start!
632 05:35:44.506547 low task start!
633 05:35:44.506982 run into bl31
634 05:35:44.512723 NOTICE: BL31: v1.3(release):4fc40b1
635 05:35:44.520598 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 05:35:44.521163 NOTICE: BL31: G12A normal boot!
637 05:35:44.545886 NOTICE: BL31: BL33 decompress pass
638 05:35:44.551600 ERROR: Error initializing runtime service opteed_fast
639 05:35:45.784384
640 05:35:45.785041
641 05:35:45.792825 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 05:35:45.793379
643 05:35:45.793844 Model: Libre Computer AML-A311D-CC Alta
644 05:35:46.001194 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 05:35:46.024526 DRAM: 2 GiB (effective 3.8 GiB)
646 05:35:46.167702 Core: 408 devices, 31 uclasses, devicetree: separate
647 05:35:46.173490 WDT: Not starting watchdog@f0d0
648 05:35:46.205825 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 05:35:46.218229 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 05:35:46.223254 ** Bad device specification mmc 0 **
651 05:35:46.233543 Card did not respond to voltage select! : -110
652 05:35:46.241219 ** Bad device specification mmc 0 **
653 05:35:46.241745 Couldn't find partition mmc 0
654 05:35:46.249530 Card did not respond to voltage select! : -110
655 05:35:46.255074 ** Bad device specification mmc 0 **
656 05:35:46.255596 Couldn't find partition mmc 0
657 05:35:46.260217 Error: could not access storage.
658 05:35:46.602613 Net: eth0: ethernet@ff3f0000
659 05:35:46.603269 starting USB...
660 05:35:46.854416 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 05:35:46.855069 Starting the controller
662 05:35:46.861352 USB XHCI 1.10
663 05:35:48.575654 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 05:35:48.576380 bl2_stage_init 0x01
665 05:35:48.576847 bl2_stage_init 0x81
666 05:35:48.581038 hw id: 0x0000 - pwm id 0x01
667 05:35:48.581558 bl2_stage_init 0xc1
668 05:35:48.582017 bl2_stage_init 0x02
669 05:35:48.582463
670 05:35:48.586770 L0:00000000
671 05:35:48.587279 L1:20000703
672 05:35:48.587728 L2:00008067
673 05:35:48.588224 L3:14000000
674 05:35:48.592209 B2:00402000
675 05:35:48.592719 B1:e0f83180
676 05:35:48.593170
677 05:35:48.593618 TE: 58159
678 05:35:48.594063
679 05:35:48.597791 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 05:35:48.598308
681 05:35:48.598760 Board ID = 1
682 05:35:48.603447 Set A53 clk to 24M
683 05:35:48.603951 Set A73 clk to 24M
684 05:35:48.604451 Set clk81 to 24M
685 05:35:48.609004 A53 clk: 1200 MHz
686 05:35:48.609508 A73 clk: 1200 MHz
687 05:35:48.609958 CLK81: 166.6M
688 05:35:48.610397 smccc: 00012ab5
689 05:35:48.614605 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 05:35:48.620202 board id: 1
691 05:35:48.626244 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 05:35:48.636586 fw parse done
693 05:35:48.642526 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 05:35:48.685218 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 05:35:48.696102 PIEI prepare done
696 05:35:48.696609 fastboot data load
697 05:35:48.697066 fastboot data verify
698 05:35:48.701772 verify result: 266
699 05:35:48.707380 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 05:35:48.707884 LPDDR4 probe
701 05:35:48.708379 ddr clk to 1584MHz
702 05:35:48.715332 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 05:35:48.752623
704 05:35:48.753171 dmc_version 0001
705 05:35:48.759251 Check phy result
706 05:35:48.765136 INFO : End of CA training
707 05:35:48.765649 INFO : End of initialization
708 05:35:48.770734 INFO : Training has run successfully!
709 05:35:48.771243 Check phy result
710 05:35:48.776420 INFO : End of initialization
711 05:35:48.776929 INFO : End of read enable training
712 05:35:48.781920 INFO : End of fine write leveling
713 05:35:48.787508 INFO : End of Write leveling coarse delay
714 05:35:48.788044 INFO : Training has run successfully!
715 05:35:48.788501 Check phy result
716 05:35:48.793134 INFO : End of initialization
717 05:35:48.793639 INFO : End of read dq deskew training
718 05:35:48.798721 INFO : End of MPR read delay center optimization
719 05:35:48.804406 INFO : End of write delay center optimization
720 05:35:48.809917 INFO : End of read delay center optimization
721 05:35:48.810422 INFO : End of max read latency training
722 05:35:48.815514 INFO : Training has run successfully!
723 05:35:48.816055 1D training succeed
724 05:35:48.824651 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 05:35:48.872343 Check phy result
726 05:35:48.872886 INFO : End of initialization
727 05:35:48.894051 INFO : End of 2D read delay Voltage center optimization
728 05:35:48.914291 INFO : End of 2D read delay Voltage center optimization
729 05:35:48.966325 INFO : End of 2D write delay Voltage center optimization
730 05:35:49.015752 INFO : End of 2D write delay Voltage center optimization
731 05:35:49.021317 INFO : Training has run successfully!
732 05:35:49.021837
733 05:35:49.022291 channel==0
734 05:35:49.026858 RxClkDly_Margin_A0==88 ps 9
735 05:35:49.027368 TxDqDly_Margin_A0==98 ps 10
736 05:35:49.032476 RxClkDly_Margin_A1==88 ps 9
737 05:35:49.032978 TxDqDly_Margin_A1==98 ps 10
738 05:35:49.033431 TrainedVREFDQ_A0==74
739 05:35:49.038114 TrainedVREFDQ_A1==74
740 05:35:49.038657 VrefDac_Margin_A0==25
741 05:35:49.039113 DeviceVref_Margin_A0==40
742 05:35:49.043684 VrefDac_Margin_A1==25
743 05:35:49.044218 DeviceVref_Margin_A1==40
744 05:35:49.044668
745 05:35:49.045113
746 05:35:49.049325 channel==1
747 05:35:49.049826 RxClkDly_Margin_A0==98 ps 10
748 05:35:49.050277 TxDqDly_Margin_A0==98 ps 10
749 05:35:49.054869 RxClkDly_Margin_A1==98 ps 10
750 05:35:49.055375 TxDqDly_Margin_A1==98 ps 10
751 05:35:49.060493 TrainedVREFDQ_A0==77
752 05:35:49.060999 TrainedVREFDQ_A1==78
753 05:35:49.061456 VrefDac_Margin_A0==22
754 05:35:49.066070 DeviceVref_Margin_A0==37
755 05:35:49.066567 VrefDac_Margin_A1==22
756 05:35:49.071670 DeviceVref_Margin_A1==36
757 05:35:49.072208
758 05:35:49.072664 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 05:35:49.077296
760 05:35:49.105282 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 05:35:49.105824 2D training succeed
762 05:35:49.110891 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 05:35:49.116507 auto size-- 65535DDR cs0 size: 2048MB
764 05:35:49.117041 DDR cs1 size: 2048MB
765 05:35:49.122082 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 05:35:49.122614 cs0 DataBus test pass
767 05:35:49.127664 cs1 DataBus test pass
768 05:35:49.128243 cs0 AddrBus test pass
769 05:35:49.128703 cs1 AddrBus test pass
770 05:35:49.129152
771 05:35:49.133344 100bdlr_step_size ps== 420
772 05:35:49.133879 result report
773 05:35:49.138955 boot times 0Enable ddr reg access
774 05:35:49.144381 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 05:35:49.157856 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 05:35:49.731485 0.0;M3 CHK:0;cm4_sp_mode 0
777 05:35:49.732214 MVN_1=0x00000000
778 05:35:49.736955 MVN_2=0x00000000
779 05:35:49.742757 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 05:35:49.743339 OPS=0x10
781 05:35:49.743780 ring efuse init
782 05:35:49.744255 chipver efuse init
783 05:35:49.748338 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 05:35:49.753844 [0.018961 Inits done]
785 05:35:49.754343 secure task start!
786 05:35:49.754773 high task start!
787 05:35:49.758482 low task start!
788 05:35:49.758980 run into bl31
789 05:35:49.765113 NOTICE: BL31: v1.3(release):4fc40b1
790 05:35:49.772904 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 05:35:49.773426 NOTICE: BL31: G12A normal boot!
792 05:35:49.798351 NOTICE: BL31: BL33 decompress pass
793 05:35:49.803938 ERROR: Error initializing runtime service opteed_fast
794 05:35:51.036893
795 05:35:51.037531
796 05:35:51.044541 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 05:35:51.045107
798 05:35:51.045585 Model: Libre Computer AML-A311D-CC Alta
799 05:35:51.253898 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 05:35:51.277178 DRAM: 2 GiB (effective 3.8 GiB)
801 05:35:51.420140 Core: 408 devices, 31 uclasses, devicetree: separate
802 05:35:51.426048 WDT: Not starting watchdog@f0d0
803 05:35:51.458633 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 05:35:51.470710 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 05:35:51.475840 ** Bad device specification mmc 0 **
806 05:35:51.486061 Card did not respond to voltage select! : -110
807 05:35:51.493715 ** Bad device specification mmc 0 **
808 05:35:51.494225 Couldn't find partition mmc 0
809 05:35:51.502047 Card did not respond to voltage select! : -110
810 05:35:51.507621 ** Bad device specification mmc 0 **
811 05:35:51.508157 Couldn't find partition mmc 0
812 05:35:51.512629 Error: could not access storage.
813 05:35:51.856220 Net: eth0: ethernet@ff3f0000
814 05:35:51.856839 starting USB...
815 05:35:52.107971 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 05:35:52.108576 Starting the controller
817 05:35:52.114947 USB XHCI 1.10
818 05:35:54.277302 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 05:35:54.277991 bl2_stage_init 0x01
820 05:35:54.278492 bl2_stage_init 0x81
821 05:35:54.282805 hw id: 0x0000 - pwm id 0x01
822 05:35:54.283368 bl2_stage_init 0xc1
823 05:35:54.283836 bl2_stage_init 0x02
824 05:35:54.284379
825 05:35:54.288355 L0:00000000
826 05:35:54.288906 L1:20000703
827 05:35:54.289368 L2:00008067
828 05:35:54.289840 L3:14000000
829 05:35:54.291379 B2:00402000
830 05:35:54.291905 B1:e0f83180
831 05:35:54.292405
832 05:35:54.292851 TE: 58167
833 05:35:54.293294
834 05:35:54.302308 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 05:35:54.302878
836 05:35:54.303332 Board ID = 1
837 05:35:54.303774 Set A53 clk to 24M
838 05:35:54.304259 Set A73 clk to 24M
839 05:35:54.307976 Set clk81 to 24M
840 05:35:54.308546 A53 clk: 1200 MHz
841 05:35:54.308995 A73 clk: 1200 MHz
842 05:35:54.311562 CLK81: 166.6M
843 05:35:54.312125 smccc: 00012abd
844 05:35:54.317242 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 05:35:54.322662 board id: 1
846 05:35:54.328032 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 05:35:54.338371 fw parse done
848 05:35:54.344316 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 05:35:54.386912 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 05:35:54.397913 PIEI prepare done
851 05:35:54.398462 fastboot data load
852 05:35:54.398921 fastboot data verify
853 05:35:54.403484 verify result: 266
854 05:35:54.409096 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 05:35:54.409638 LPDDR4 probe
856 05:35:54.410089 ddr clk to 1584MHz
857 05:35:54.417058 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 05:35:54.454337
859 05:35:54.454906 dmc_version 0001
860 05:35:54.461068 Check phy result
861 05:35:54.466889 INFO : End of CA training
862 05:35:54.467483 INFO : End of initialization
863 05:35:54.472471 INFO : Training has run successfully!
864 05:35:54.473016 Check phy result
865 05:35:54.478164 INFO : End of initialization
866 05:35:54.478740 INFO : End of read enable training
867 05:35:54.483718 INFO : End of fine write leveling
868 05:35:54.489291 INFO : End of Write leveling coarse delay
869 05:35:54.489855 INFO : Training has run successfully!
870 05:35:54.490312 Check phy result
871 05:35:54.494851 INFO : End of initialization
872 05:35:54.495382 INFO : End of read dq deskew training
873 05:35:54.500487 INFO : End of MPR read delay center optimization
874 05:35:54.506108 INFO : End of write delay center optimization
875 05:35:54.511659 INFO : End of read delay center optimization
876 05:35:54.512243 INFO : End of max read latency training
877 05:35:54.517284 INFO : Training has run successfully!
878 05:35:54.517813 1D training succeed
879 05:35:54.526342 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 05:35:54.574118 Check phy result
881 05:35:54.574740 INFO : End of initialization
882 05:35:54.595780 INFO : End of 2D read delay Voltage center optimization
883 05:35:54.616049 INFO : End of 2D read delay Voltage center optimization
884 05:35:54.668074 INFO : End of 2D write delay Voltage center optimization
885 05:35:54.717365 INFO : End of 2D write delay Voltage center optimization
886 05:35:54.722934 INFO : Training has run successfully!
887 05:35:54.723468
888 05:35:54.723925 channel==0
889 05:35:54.728536 RxClkDly_Margin_A0==88 ps 9
890 05:35:54.729067 TxDqDly_Margin_A0==98 ps 10
891 05:35:54.734144 RxClkDly_Margin_A1==88 ps 9
892 05:35:54.734677 TxDqDly_Margin_A1==88 ps 9
893 05:35:54.735151 TrainedVREFDQ_A0==74
894 05:35:54.739765 TrainedVREFDQ_A1==74
895 05:35:54.740376 VrefDac_Margin_A0==25
896 05:35:54.740834 DeviceVref_Margin_A0==40
897 05:35:54.745296 VrefDac_Margin_A1==25
898 05:35:54.745851 DeviceVref_Margin_A1==40
899 05:35:54.746283
900 05:35:54.746711
901 05:35:54.747137 channel==1
902 05:35:54.750902 RxClkDly_Margin_A0==98 ps 10
903 05:35:54.751421 TxDqDly_Margin_A0==98 ps 10
904 05:35:54.756512 RxClkDly_Margin_A1==88 ps 9
905 05:35:54.757038 TxDqDly_Margin_A1==88 ps 9
906 05:35:54.762183 TrainedVREFDQ_A0==77
907 05:35:54.762757 TrainedVREFDQ_A1==77
908 05:35:54.763192 VrefDac_Margin_A0==22
909 05:35:54.767725 DeviceVref_Margin_A0==37
910 05:35:54.768279 VrefDac_Margin_A1==24
911 05:35:54.773329 DeviceVref_Margin_A1==37
912 05:35:54.773840
913 05:35:54.774275 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 05:35:54.774703
915 05:35:54.806869 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
916 05:35:54.807483 2D training succeed
917 05:35:54.812522 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 05:35:54.818140 auto size-- 65535DDR cs0 size: 2048MB
919 05:35:54.818662 DDR cs1 size: 2048MB
920 05:35:54.823698 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 05:35:54.824263 cs0 DataBus test pass
922 05:35:54.829318 cs1 DataBus test pass
923 05:35:54.829833 cs0 AddrBus test pass
924 05:35:54.830260 cs1 AddrBus test pass
925 05:35:54.830687
926 05:35:54.834901 100bdlr_step_size ps== 420
927 05:35:54.835423 result report
928 05:35:54.840513 boot times 0Enable ddr reg access
929 05:35:54.845740 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 05:35:54.859269 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 05:35:55.432900 0.0;M3 CHK:0;cm4_sp_mode 0
932 05:35:55.433548 MVN_1=0x00000000
933 05:35:55.438402 MVN_2=0x00000000
934 05:35:55.444232 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 05:35:55.444741 OPS=0x10
936 05:35:55.445197 ring efuse init
937 05:35:55.445641 chipver efuse init
938 05:35:55.449725 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 05:35:55.455336 [0.018960 Inits done]
940 05:35:55.455844 secure task start!
941 05:35:55.456346 high task start!
942 05:35:55.459904 low task start!
943 05:35:55.460441 run into bl31
944 05:35:55.466644 NOTICE: BL31: v1.3(release):4fc40b1
945 05:35:55.474426 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 05:35:55.474961 NOTICE: BL31: G12A normal boot!
947 05:35:55.499773 NOTICE: BL31: BL33 decompress pass
948 05:35:55.505430 ERROR: Error initializing runtime service opteed_fast
949 05:35:56.738279
950 05:35:56.738917
951 05:35:56.745738 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 05:35:56.746266
953 05:35:56.746741 Model: Libre Computer AML-A311D-CC Alta
954 05:35:56.955155 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 05:35:56.978580 DRAM: 2 GiB (effective 3.8 GiB)
956 05:35:57.121552 Core: 408 devices, 31 uclasses, devicetree: separate
957 05:35:57.127436 WDT: Not starting watchdog@f0d0
958 05:35:57.159621 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 05:35:57.172104 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 05:35:57.177066 ** Bad device specification mmc 0 **
961 05:35:57.187468 Card did not respond to voltage select! : -110
962 05:35:57.195030 ** Bad device specification mmc 0 **
963 05:35:57.195541 Couldn't find partition mmc 0
964 05:35:57.203506 Card did not respond to voltage select! : -110
965 05:35:57.208907 ** Bad device specification mmc 0 **
966 05:35:57.209413 Couldn't find partition mmc 0
967 05:35:57.213975 Error: could not access storage.
968 05:35:57.556436 Net: eth0: ethernet@ff3f0000
969 05:35:57.557094 starting USB...
970 05:35:57.808445 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 05:35:57.809079 Starting the controller
972 05:35:57.814280 USB XHCI 1.10
973 05:35:59.369344 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 05:35:59.376688 scanning usb for storage devices... 0 Storage Device(s) found
976 05:35:59.428515 Hit any key to stop autoboot: 1
977 05:35:59.429797 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 05:35:59.430488 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 05:35:59.431017 Setting prompt string to ['=>']
980 05:35:59.431566 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 05:35:59.445192 0
982 05:35:59.446177 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 05:35:59.446729 Sending with 10 millisecond of delay
985 05:36:00.582461 => setenv autoload no
986 05:36:00.593370 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 05:36:00.596003 setenv autoload no
988 05:36:00.596468 Sending with 10 millisecond of delay
990 05:36:02.394066 => setenv initrd_high 0xffffffff
991 05:36:02.404899 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 05:36:02.405887 setenv initrd_high 0xffffffff
993 05:36:02.406648 Sending with 10 millisecond of delay
995 05:36:04.024166 => setenv fdt_high 0xffffffff
996 05:36:04.034971 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
997 05:36:04.035870 setenv fdt_high 0xffffffff
998 05:36:04.036687 Sending with 10 millisecond of delay
1000 05:36:04.328797 => dhcp
1001 05:36:04.339658 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 05:36:04.341116 dhcp
1003 05:36:04.341597 Speed: 1000, full duplex
1004 05:36:04.342079 BOOTP broadcast 1
1005 05:36:04.508366 DHCP client bound to address 192.168.6.27 (168 ms)
1006 05:36:04.509275 Sending with 10 millisecond of delay
1008 05:36:06.186207 => setenv serverip 192.168.6.2
1009 05:36:06.197056 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1010 05:36:06.198035 setenv serverip 192.168.6.2
1011 05:36:06.198778 Sending with 10 millisecond of delay
1013 05:36:09.923624 => tftpboot 0x01080000 927296/tftp-deploy-nm2stz6z/kernel/uImage
1014 05:36:09.934510 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1015 05:36:09.935455 tftpboot 0x01080000 927296/tftp-deploy-nm2stz6z/kernel/uImage
1016 05:36:09.935961 Speed: 1000, full duplex
1017 05:36:09.936486 Using ethernet@ff3f0000 device
1018 05:36:09.937485 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 05:36:09.943009 Filename '927296/tftp-deploy-nm2stz6z/kernel/uImage'.
1020 05:36:09.946871 Load address: 0x1080000
1021 05:36:12.730026 Loading: *################################################## 43.6 MiB
1022 05:36:12.730750 15.6 MiB/s
1023 05:36:12.731245 done
1024 05:36:12.734661 Bytes transferred = 45713984 (2b98a40 hex)
1025 05:36:12.735685 Sending with 10 millisecond of delay
1027 05:36:17.426738 => tftpboot 0x08000000 927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot
1028 05:36:17.437585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1029 05:36:17.438564 tftpboot 0x08000000 927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot
1030 05:36:17.439062 Speed: 1000, full duplex
1031 05:36:17.439524 Using ethernet@ff3f0000 device
1032 05:36:17.440584 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 05:36:17.452305 Filename '927296/tftp-deploy-nm2stz6z/ramdisk/ramdisk.cpio.gz.uboot'.
1034 05:36:17.452871 Load address: 0x8000000
1035 05:36:24.071470 Loading: *#####################T ############################ UDP wrong checksum 00000005 0000fb5c
1036 05:36:29.072274 T UDP wrong checksum 00000005 0000fb5c
1037 05:36:29.179855 UDP wrong checksum 000000ff 0000265b
1038 05:36:29.221209 UDP wrong checksum 000000ff 0000b94d
1039 05:36:39.075364 T T UDP wrong checksum 00000005 0000fb5c
1040 05:36:44.600550 T UDP wrong checksum 000000ff 00005d43
1041 05:36:44.660272 UDP wrong checksum 000000ff 0000f635
1042 05:36:59.076972 T T UDP wrong checksum 00000005 0000fb5c
1043 05:37:10.489774 T T T UDP wrong checksum 000000ff 0000aa8a
1044 05:37:10.569787 UDP wrong checksum 000000ff 0000447d
1045 05:37:14.083544
1046 05:37:14.084217 Retry count exceeded; starting again
1048 05:37:14.085650 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1051 05:37:14.087456 end: 2.4 uboot-commands (duration 00:01:47) [common]
1053 05:37:14.088854 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1055 05:37:14.089876 end: 2 uboot-action (duration 00:01:47) [common]
1057 05:37:14.091403 Cleaning after the job
1058 05:37:14.091968 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/ramdisk
1059 05:37:14.093316 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/kernel
1060 05:37:14.137151 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/dtb
1061 05:37:14.137929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/nfsrootfs
1062 05:37:14.212317 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927296/tftp-deploy-nm2stz6z/modules
1063 05:37:14.219453 start: 4.1 power-off (timeout 00:00:30) [common]
1064 05:37:14.220080 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1065 05:37:14.255303 >> OK - accepted request
1066 05:37:14.256838 Returned 0 in 0 seconds
1067 05:37:14.358017 end: 4.1 power-off (duration 00:00:00) [common]
1069 05:37:14.359255 start: 4.2 read-feedback (timeout 00:10:00) [common]
1070 05:37:14.360087 Listened to connection for namespace 'common' for up to 1s
1071 05:37:15.360250 Finalising connection for namespace 'common'
1072 05:37:15.360824 Disconnecting from shell: Finalise
1073 05:37:15.361193 =>
1074 05:37:15.462113 end: 4.2 read-feedback (duration 00:00:01) [common]
1075 05:37:15.462953 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927296
1076 05:37:18.694137 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927296
1077 05:37:18.694745 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.