Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:30:49.057074 lava-dispatcher, installed at version: 2024.01
2 05:30:49.057868 start: 0 validate
3 05:30:49.058349 Start time: 2024-11-02 05:30:49.058317+00:00 (UTC)
4 05:30:49.058920 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:30:49.059664 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:30:49.093730 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:30:49.094258 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:30:49.127462 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:30:49.128119 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:30:49.161928 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:30:49.162535 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:30:49.201446 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:30:49.201935 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:30:49.238210 validate duration: 0.18
16 05:30:49.239103 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:30:49.239430 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:30:49.239749 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:30:49.240344 Not decompressing ramdisk as can be used compressed.
20 05:30:49.240800 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 05:30:49.241081 saving as /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/ramdisk/initrd.cpio.gz
22 05:30:49.241361 total size: 5628140 (5 MB)
23 05:30:49.276036 progress 0 % (0 MB)
24 05:30:49.281240 progress 5 % (0 MB)
25 05:30:49.289488 progress 10 % (0 MB)
26 05:30:49.296309 progress 15 % (0 MB)
27 05:30:49.300578 progress 20 % (1 MB)
28 05:30:49.304346 progress 25 % (1 MB)
29 05:30:49.308446 progress 30 % (1 MB)
30 05:30:49.312603 progress 35 % (1 MB)
31 05:30:49.316330 progress 40 % (2 MB)
32 05:30:49.320417 progress 45 % (2 MB)
33 05:30:49.324060 progress 50 % (2 MB)
34 05:30:49.328111 progress 55 % (2 MB)
35 05:30:49.332153 progress 60 % (3 MB)
36 05:30:49.335786 progress 65 % (3 MB)
37 05:30:49.339813 progress 70 % (3 MB)
38 05:30:49.343546 progress 75 % (4 MB)
39 05:30:49.347605 progress 80 % (4 MB)
40 05:30:49.351199 progress 85 % (4 MB)
41 05:30:49.355197 progress 90 % (4 MB)
42 05:30:49.359000 progress 95 % (5 MB)
43 05:30:49.362289 progress 100 % (5 MB)
44 05:30:49.362952 5 MB downloaded in 0.12 s (44.15 MB/s)
45 05:30:49.363497 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:30:49.364404 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:30:49.364700 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:30:49.364969 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:30:49.365444 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kernel/Image
51 05:30:49.365689 saving as /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/kernel/Image
52 05:30:49.365898 total size: 45713920 (43 MB)
53 05:30:49.366107 No compression specified
54 05:30:49.407121 progress 0 % (0 MB)
55 05:30:49.435956 progress 5 % (2 MB)
56 05:30:49.465087 progress 10 % (4 MB)
57 05:30:49.493967 progress 15 % (6 MB)
58 05:30:49.523314 progress 20 % (8 MB)
59 05:30:49.552641 progress 25 % (10 MB)
60 05:30:49.581449 progress 30 % (13 MB)
61 05:30:49.610224 progress 35 % (15 MB)
62 05:30:49.638675 progress 40 % (17 MB)
63 05:30:49.667342 progress 45 % (19 MB)
64 05:30:49.696328 progress 50 % (21 MB)
65 05:30:49.724892 progress 55 % (24 MB)
66 05:30:49.753736 progress 60 % (26 MB)
67 05:30:49.781960 progress 65 % (28 MB)
68 05:30:49.810317 progress 70 % (30 MB)
69 05:30:49.838856 progress 75 % (32 MB)
70 05:30:49.867307 progress 80 % (34 MB)
71 05:30:49.895589 progress 85 % (37 MB)
72 05:30:49.924008 progress 90 % (39 MB)
73 05:30:49.952947 progress 95 % (41 MB)
74 05:30:49.981312 progress 100 % (43 MB)
75 05:30:49.981882 43 MB downloaded in 0.62 s (70.78 MB/s)
76 05:30:49.982360 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:30:49.983184 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:30:49.983461 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:30:49.983726 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:30:49.984426 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:30:49.984724 saving as /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:30:49.984933 total size: 54703 (0 MB)
84 05:30:49.985144 No compression specified
85 05:30:50.031907 progress 59 % (0 MB)
86 05:30:50.032836 progress 100 % (0 MB)
87 05:30:50.033461 0 MB downloaded in 0.05 s (1.08 MB/s)
88 05:30:50.033999 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:30:50.034931 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:30:50.035248 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:30:50.035578 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:30:50.036179 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 05:30:50.036503 saving as /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/nfsrootfs/full.rootfs.tar
95 05:30:50.036734 total size: 474398908 (452 MB)
96 05:30:50.036982 Using unxz to decompress xz
97 05:30:50.080086 progress 0 % (0 MB)
98 05:30:51.259332 progress 5 % (22 MB)
99 05:30:52.704691 progress 10 % (45 MB)
100 05:30:53.147576 progress 15 % (67 MB)
101 05:30:53.945932 progress 20 % (90 MB)
102 05:30:54.465815 progress 25 % (113 MB)
103 05:30:54.872567 progress 30 % (135 MB)
104 05:30:55.556722 progress 35 % (158 MB)
105 05:30:56.574465 progress 40 % (181 MB)
106 05:30:57.369192 progress 45 % (203 MB)
107 05:30:57.922922 progress 50 % (226 MB)
108 05:30:58.561145 progress 55 % (248 MB)
109 05:30:59.762336 progress 60 % (271 MB)
110 05:31:01.187867 progress 65 % (294 MB)
111 05:31:02.779868 progress 70 % (316 MB)
112 05:31:05.939100 progress 75 % (339 MB)
113 05:31:08.562924 progress 80 % (361 MB)
114 05:31:11.487556 progress 85 % (384 MB)
115 05:31:14.646913 progress 90 % (407 MB)
116 05:31:17.901406 progress 95 % (429 MB)
117 05:31:21.104513 progress 100 % (452 MB)
118 05:31:21.117523 452 MB downloaded in 31.08 s (14.56 MB/s)
119 05:31:21.118276 end: 1.4.1 http-download (duration 00:00:31) [common]
121 05:31:21.120222 end: 1.4 download-retry (duration 00:00:31) [common]
122 05:31:21.121108 start: 1.5 download-retry (timeout 00:09:28) [common]
123 05:31:21.121834 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 05:31:21.123007 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/modules.tar.xz
125 05:31:21.123685 saving as /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/modules/modules.tar
126 05:31:21.124227 total size: 11611500 (11 MB)
127 05:31:21.124806 Using unxz to decompress xz
128 05:31:21.173490 progress 0 % (0 MB)
129 05:31:21.240599 progress 5 % (0 MB)
130 05:31:21.316420 progress 10 % (1 MB)
131 05:31:21.396720 progress 15 % (1 MB)
132 05:31:21.472833 progress 20 % (2 MB)
133 05:31:21.549541 progress 25 % (2 MB)
134 05:31:21.628140 progress 30 % (3 MB)
135 05:31:21.704225 progress 35 % (3 MB)
136 05:31:21.779551 progress 40 % (4 MB)
137 05:31:21.864207 progress 45 % (5 MB)
138 05:31:21.944713 progress 50 % (5 MB)
139 05:31:22.022490 progress 55 % (6 MB)
140 05:31:22.102842 progress 60 % (6 MB)
141 05:31:22.186627 progress 65 % (7 MB)
142 05:31:22.270430 progress 70 % (7 MB)
143 05:31:22.346433 progress 75 % (8 MB)
144 05:31:22.428417 progress 80 % (8 MB)
145 05:31:22.508222 progress 85 % (9 MB)
146 05:31:22.577302 progress 90 % (9 MB)
147 05:31:22.675211 progress 95 % (10 MB)
148 05:31:22.772141 progress 100 % (11 MB)
149 05:31:22.783889 11 MB downloaded in 1.66 s (6.67 MB/s)
150 05:31:22.784897 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:31:22.786646 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:31:22.787214 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 05:31:22.787776 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 05:31:38.975073 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927272/extract-nfsrootfs-zy7oxm0d
156 05:31:38.975807 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 05:31:38.976192 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 05:31:38.976950 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi
159 05:31:38.977506 makedir: /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin
160 05:31:38.977941 makedir: /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/tests
161 05:31:38.978340 makedir: /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/results
162 05:31:38.978756 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-add-keys
163 05:31:38.979424 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-add-sources
164 05:31:38.980146 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-background-process-start
165 05:31:38.980807 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-background-process-stop
166 05:31:38.981584 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-common-functions
167 05:31:38.982221 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-echo-ipv4
168 05:31:38.982813 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-install-packages
169 05:31:38.983417 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-installed-packages
170 05:31:38.984026 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-os-build
171 05:31:38.984637 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-probe-channel
172 05:31:38.985219 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-probe-ip
173 05:31:38.985801 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-target-ip
174 05:31:38.986378 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-target-mac
175 05:31:38.986961 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-target-storage
176 05:31:38.987547 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-case
177 05:31:38.988166 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-event
178 05:31:38.988759 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-feedback
179 05:31:38.989338 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-raise
180 05:31:38.989931 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-reference
181 05:31:38.990540 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-runner
182 05:31:38.991152 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-set
183 05:31:38.991733 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-test-shell
184 05:31:38.992379 Updating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-install-packages (oe)
185 05:31:38.993053 Updating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/bin/lava-installed-packages (oe)
186 05:31:38.993595 Creating /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/environment
187 05:31:38.994050 LAVA metadata
188 05:31:38.994360 - LAVA_JOB_ID=927272
189 05:31:38.994618 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:31:38.995065 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 05:31:38.996288 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:31:38.996688 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 05:31:38.996943 skipped lava-vland-overlay
194 05:31:38.997236 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:31:38.997550 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 05:31:38.997812 skipped lava-multinode-overlay
197 05:31:38.998106 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:31:38.998407 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 05:31:38.998712 Loading test definitions
200 05:31:38.999045 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 05:31:38.999310 Using /lava-927272 at stage 0
202 05:31:39.000752 uuid=927272_1.6.2.4.1 testdef=None
203 05:31:39.001115 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:31:39.001437 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 05:31:39.003501 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:31:39.004479 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 05:31:39.007111 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:31:39.008149 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 05:31:39.010649 runner path: /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 927272_1.6.2.4.1
212 05:31:39.011338 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:31:39.012312 Creating lava-test-runner.conf files
215 05:31:39.012561 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927272/lava-overlay-woro6psi/lava-927272/0 for stage 0
216 05:31:39.012971 - 0_v4l2-decoder-conformance-h265
217 05:31:39.013385 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:31:39.013715 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 05:31:39.040522 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:31:39.041000 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 05:31:39.041310 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:31:39.041635 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:31:39.041948 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 05:31:39.681798 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:31:39.682261 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 05:31:39.682511 extracting modules file /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927272/extract-nfsrootfs-zy7oxm0d
227 05:31:41.054744 extracting modules file /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927272/extract-overlay-ramdisk-hqmn05vc/ramdisk
228 05:31:42.450625 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:31:42.451127 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 05:31:42.451410 [common] Applying overlay to NFS
231 05:31:42.451624 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927272/compress-overlay-9rk_13cf/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927272/extract-nfsrootfs-zy7oxm0d
232 05:31:42.482039 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:31:42.482525 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 05:31:42.482803 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 05:31:42.483040 Converting downloaded kernel to a uImage
236 05:31:42.483365 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/kernel/Image /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/kernel/uImage
237 05:31:42.978317 output: Image Name:
238 05:31:42.978735 output: Created: Sat Nov 2 05:31:42 2024
239 05:31:42.978942 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:31:42.979146 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 05:31:42.979346 output: Load Address: 01080000
242 05:31:42.979545 output: Entry Point: 01080000
243 05:31:42.979741 output:
244 05:31:42.980101 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 05:31:42.980381 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 05:31:42.980653 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 05:31:42.980905 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:31:42.981163 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 05:31:42.981417 Building ramdisk /var/lib/lava/dispatcher/tmp/927272/extract-overlay-ramdisk-hqmn05vc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927272/extract-overlay-ramdisk-hqmn05vc/ramdisk
250 05:31:45.190292 >> 166823 blocks
251 05:31:53.122014 Adding RAMdisk u-boot header.
252 05:31:53.122728 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927272/extract-overlay-ramdisk-hqmn05vc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927272/extract-overlay-ramdisk-hqmn05vc/ramdisk.cpio.gz.uboot
253 05:31:53.361719 output: Image Name:
254 05:31:53.362191 output: Created: Sat Nov 2 05:31:53 2024
255 05:31:53.362410 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:31:53.362657 output: Data Size: 23435701 Bytes = 22886.43 KiB = 22.35 MiB
257 05:31:53.362864 output: Load Address: 00000000
258 05:31:53.363062 output: Entry Point: 00000000
259 05:31:53.363289 output:
260 05:31:53.364119 rename /var/lib/lava/dispatcher/tmp/927272/extract-overlay-ramdisk-hqmn05vc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot
261 05:31:53.364969 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:31:53.365575 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 05:31:53.366159 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 05:31:53.366667 No LXC device requested
265 05:31:53.367224 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:31:53.367789 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 05:31:53.368390 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:31:53.368851 Checking files for TFTP limit of 4294967296 bytes.
269 05:31:53.371760 end: 1 tftp-deploy (duration 00:01:04) [common]
270 05:31:53.372428 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:31:53.373005 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:31:53.373552 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:31:53.374100 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:31:53.374677 Using kernel file from prepare-kernel: 927272/tftp-deploy-6h7mw4w9/kernel/uImage
275 05:31:53.375369 substitutions:
276 05:31:53.375814 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:31:53.376282 - {DTB_ADDR}: 0x01070000
278 05:31:53.376722 - {DTB}: 927272/tftp-deploy-6h7mw4w9/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:31:53.377159 - {INITRD}: 927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot
280 05:31:53.377596 - {KERNEL_ADDR}: 0x01080000
281 05:31:53.378025 - {KERNEL}: 927272/tftp-deploy-6h7mw4w9/kernel/uImage
282 05:31:53.378459 - {LAVA_MAC}: None
283 05:31:53.378930 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927272/extract-nfsrootfs-zy7oxm0d
284 05:31:53.379367 - {NFS_SERVER_IP}: 192.168.6.2
285 05:31:53.379798 - {PRESEED_CONFIG}: None
286 05:31:53.380255 - {PRESEED_LOCAL}: None
287 05:31:53.380685 - {RAMDISK_ADDR}: 0x08000000
288 05:31:53.381108 - {RAMDISK}: 927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot
289 05:31:53.381535 - {ROOT_PART}: None
290 05:31:53.381962 - {ROOT}: None
291 05:31:53.382385 - {SERVER_IP}: 192.168.6.2
292 05:31:53.382810 - {TEE_ADDR}: 0x83000000
293 05:31:53.383233 - {TEE}: None
294 05:31:53.383655 Parsed boot commands:
295 05:31:53.384092 - setenv autoload no
296 05:31:53.384522 - setenv initrd_high 0xffffffff
297 05:31:53.384946 - setenv fdt_high 0xffffffff
298 05:31:53.385370 - dhcp
299 05:31:53.385790 - setenv serverip 192.168.6.2
300 05:31:53.386211 - tftpboot 0x01080000 927272/tftp-deploy-6h7mw4w9/kernel/uImage
301 05:31:53.386637 - tftpboot 0x08000000 927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot
302 05:31:53.387059 - tftpboot 0x01070000 927272/tftp-deploy-6h7mw4w9/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:31:53.387484 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927272/extract-nfsrootfs-zy7oxm0d,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:31:53.387920 - bootm 0x01080000 0x08000000 0x01070000
305 05:31:53.388490 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:31:53.390108 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:31:53.390569 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:31:53.405339 Setting prompt string to ['lava-test: # ']
310 05:31:53.406937 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:31:53.407595 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:31:53.408236 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:31:53.408818 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:31:53.410023 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:31:53.447489 >> OK - accepted request
316 05:31:53.449646 Returned 0 in 0 seconds
317 05:31:53.550826 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:31:53.552616 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:31:53.553241 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:31:53.553805 Setting prompt string to ['Hit any key to stop autoboot']
322 05:31:53.554315 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:31:53.556047 Trying 192.168.56.21...
324 05:31:53.556598 Connected to conserv1.
325 05:31:53.557062 Escape character is '^]'.
326 05:31:53.557516
327 05:31:53.557979 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:31:53.558446
329 05:32:05.174163 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 05:32:05.174599 bl2_stage_init 0x01
331 05:32:05.174843 bl2_stage_init 0x81
332 05:32:05.179759 hw id: 0x0000 - pwm id 0x01
333 05:32:05.180168 bl2_stage_init 0xc1
334 05:32:05.180389 bl2_stage_init 0x02
335 05:32:05.180616
336 05:32:05.185269 L0:00000000
337 05:32:05.185614 L1:20000703
338 05:32:05.185828 L2:00008067
339 05:32:05.186042 L3:14000000
340 05:32:05.190858 B2:00402000
341 05:32:05.191202 B1:e0f83180
342 05:32:05.191523
343 05:32:05.191751 TE: 58167
344 05:32:05.191962
345 05:32:05.196444 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 05:32:05.196749
347 05:32:05.196961 Board ID = 1
348 05:32:05.202064 Set A53 clk to 24M
349 05:32:05.202500 Set A73 clk to 24M
350 05:32:05.202716 Set clk81 to 24M
351 05:32:05.207662 A53 clk: 1200 MHz
352 05:32:05.208001 A73 clk: 1200 MHz
353 05:32:05.208241 CLK81: 166.6M
354 05:32:05.208454 smccc: 00012abd
355 05:32:05.213354 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 05:32:05.218863 board id: 1
357 05:32:05.224750 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:32:05.235475 fw parse done
359 05:32:05.241397 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:32:05.284098 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:32:05.294924 PIEI prepare done
362 05:32:05.295315 fastboot data load
363 05:32:05.295539 fastboot data verify
364 05:32:05.300565 verify result: 266
365 05:32:05.306197 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 05:32:05.306506 LPDDR4 probe
367 05:32:05.306726 ddr clk to 1584MHz
368 05:32:05.314162 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:32:05.351476
370 05:32:05.351884 dmc_version 0001
371 05:32:05.358152 Check phy result
372 05:32:05.363991 INFO : End of CA training
373 05:32:05.364362 INFO : End of initialization
374 05:32:05.369546 INFO : Training has run successfully!
375 05:32:05.369839 Check phy result
376 05:32:05.375222 INFO : End of initialization
377 05:32:05.375604 INFO : End of read enable training
378 05:32:05.380822 INFO : End of fine write leveling
379 05:32:05.386492 INFO : End of Write leveling coarse delay
380 05:32:05.386807 INFO : Training has run successfully!
381 05:32:05.387024 Check phy result
382 05:32:05.392070 INFO : End of initialization
383 05:32:05.392414 INFO : End of read dq deskew training
384 05:32:05.397556 INFO : End of MPR read delay center optimization
385 05:32:05.403176 INFO : End of write delay center optimization
386 05:32:05.408793 INFO : End of read delay center optimization
387 05:32:05.409155 INFO : End of max read latency training
388 05:32:05.414369 INFO : Training has run successfully!
389 05:32:05.414666 1D training succeed
390 05:32:05.423516 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:32:05.471284 Check phy result
392 05:32:05.471721 INFO : End of initialization
393 05:32:05.492904 INFO : End of 2D read delay Voltage center optimization
394 05:32:05.512260 INFO : End of 2D read delay Voltage center optimization
395 05:32:05.564354 INFO : End of 2D write delay Voltage center optimization
396 05:32:05.613773 INFO : End of 2D write delay Voltage center optimization
397 05:32:05.619307 INFO : Training has run successfully!
398 05:32:05.620034
399 05:32:05.620613 channel==0
400 05:32:05.624980 RxClkDly_Margin_A0==88 ps 9
401 05:32:05.625898 TxDqDly_Margin_A0==98 ps 10
402 05:32:05.630529 RxClkDly_Margin_A1==88 ps 9
403 05:32:05.631151 TxDqDly_Margin_A1==98 ps 10
404 05:32:05.631653 TrainedVREFDQ_A0==74
405 05:32:05.636156 TrainedVREFDQ_A1==74
406 05:32:05.636744 VrefDac_Margin_A0==25
407 05:32:05.637183 DeviceVref_Margin_A0==40
408 05:32:05.641816 VrefDac_Margin_A1==25
409 05:32:05.642481 DeviceVref_Margin_A1==40
410 05:32:05.642906
411 05:32:05.643404
412 05:32:05.647469 channel==1
413 05:32:05.648129 RxClkDly_Margin_A0==98 ps 10
414 05:32:05.648623 TxDqDly_Margin_A0==98 ps 10
415 05:32:05.652965 RxClkDly_Margin_A1==88 ps 9
416 05:32:05.653672 TxDqDly_Margin_A1==88 ps 9
417 05:32:05.658618 TrainedVREFDQ_A0==77
418 05:32:05.659909 TrainedVREFDQ_A1==77
419 05:32:05.660402 VrefDac_Margin_A0==23
420 05:32:05.664119 DeviceVref_Margin_A0==37
421 05:32:05.664639 VrefDac_Margin_A1==24
422 05:32:05.669755 DeviceVref_Margin_A1==37
423 05:32:05.670264
424 05:32:05.670703 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:32:05.671116
426 05:32:05.703290 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
427 05:32:05.704081 2D training succeed
428 05:32:05.708872 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:32:05.714687 auto size-- 65535DDR cs0 size: 2048MB
430 05:32:05.715182 DDR cs1 size: 2048MB
431 05:32:05.720193 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:32:05.720557 cs0 DataBus test pass
433 05:32:05.725675 cs1 DataBus test pass
434 05:32:05.726189 cs0 AddrBus test pass
435 05:32:05.726616 cs1 AddrBus test pass
436 05:32:05.727051
437 05:32:05.731300 100bdlr_step_size ps== 420
438 05:32:05.731825 result report
439 05:32:05.736870 boot times 0Enable ddr reg access
440 05:32:05.742225 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:32:05.755835 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 05:32:06.328684 0.0;M3 CHK:0;cm4_sp_mode 0
443 05:32:06.329301 MVN_1=0x00000000
444 05:32:06.334175 MVN_2=0x00000000
445 05:32:06.339915 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 05:32:06.340479 OPS=0x10
447 05:32:06.340900 ring efuse init
448 05:32:06.341307 chipver efuse init
449 05:32:06.348157 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 05:32:06.348631 [0.018961 Inits done]
451 05:32:06.354807 secure task start!
452 05:32:06.355237 high task start!
453 05:32:06.355642 low task start!
454 05:32:06.356073 run into bl31
455 05:32:06.362365 NOTICE: BL31: v1.3(release):4fc40b1
456 05:32:06.370170 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 05:32:06.370603 NOTICE: BL31: G12A normal boot!
458 05:32:06.396228 NOTICE: BL31: BL33 decompress pass
459 05:32:06.400322 ERROR: Error initializing runtime service opteed_fast
460 05:32:07.634270
461 05:32:07.634875
462 05:32:07.642590 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 05:32:07.643049
464 05:32:07.643458 Model: Libre Computer AML-A311D-CC Alta
465 05:32:07.851256 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 05:32:07.874642 DRAM: 2 GiB (effective 3.8 GiB)
467 05:32:08.017655 Core: 408 devices, 31 uclasses, devicetree: separate
468 05:32:08.023374 WDT: Not starting watchdog@f0d0
469 05:32:08.055786 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 05:32:08.068338 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 05:32:08.073199 ** Bad device specification mmc 0 **
472 05:32:08.083498 Card did not respond to voltage select! : -110
473 05:32:08.091136 ** Bad device specification mmc 0 **
474 05:32:08.091453 Couldn't find partition mmc 0
475 05:32:08.099437 Card did not respond to voltage select! : -110
476 05:32:08.104970 ** Bad device specification mmc 0 **
477 05:32:08.105366 Couldn't find partition mmc 0
478 05:32:08.110080 Error: could not access storage.
479 05:32:09.374777 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 05:32:09.375355 bl2_stage_init 0x01
481 05:32:09.375781 bl2_stage_init 0x81
482 05:32:09.380162 hw id: 0x0000 - pwm id 0x01
483 05:32:09.380608 bl2_stage_init 0xc1
484 05:32:09.381018 bl2_stage_init 0x02
485 05:32:09.381415
486 05:32:09.385761 L0:00000000
487 05:32:09.386227 L1:20000703
488 05:32:09.386661 L2:00008067
489 05:32:09.387080 L3:14000000
490 05:32:09.388514 B2:00402000
491 05:32:09.388952 B1:e0f83180
492 05:32:09.389351
493 05:32:09.389745 TE: 58167
494 05:32:09.390141
495 05:32:09.399873 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 05:32:09.400389
497 05:32:09.400801 Board ID = 1
498 05:32:09.401195 Set A53 clk to 24M
499 05:32:09.401589 Set A73 clk to 24M
500 05:32:09.405349 Set clk81 to 24M
501 05:32:09.405781 A53 clk: 1200 MHz
502 05:32:09.406178 A73 clk: 1200 MHz
503 05:32:09.411034 CLK81: 166.6M
504 05:32:09.411464 smccc: 00012abd
505 05:32:09.416393 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 05:32:09.416827 board id: 1
507 05:32:09.424226 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 05:32:09.435739 fw parse done
509 05:32:09.440693 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 05:32:09.484232 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 05:32:09.495063 PIEI prepare done
512 05:32:09.495356 fastboot data load
513 05:32:09.495576 fastboot data verify
514 05:32:09.500773 verify result: 266
515 05:32:09.506350 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 05:32:09.506819 LPDDR4 probe
517 05:32:09.507233 ddr clk to 1584MHz
518 05:32:09.514413 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 05:32:09.551723
520 05:32:09.552290 dmc_version 0001
521 05:32:09.558320 Check phy result
522 05:32:09.564192 INFO : End of CA training
523 05:32:09.564641 INFO : End of initialization
524 05:32:09.569772 INFO : Training has run successfully!
525 05:32:09.570244 Check phy result
526 05:32:09.575410 INFO : End of initialization
527 05:32:09.575882 INFO : End of read enable training
528 05:32:09.580979 INFO : End of fine write leveling
529 05:32:09.586577 INFO : End of Write leveling coarse delay
530 05:32:09.587093 INFO : Training has run successfully!
531 05:32:09.587514 Check phy result
532 05:32:09.592222 INFO : End of initialization
533 05:32:09.592674 INFO : End of read dq deskew training
534 05:32:09.597787 INFO : End of MPR read delay center optimization
535 05:32:09.603413 INFO : End of write delay center optimization
536 05:32:09.608988 INFO : End of read delay center optimization
537 05:32:09.609448 INFO : End of max read latency training
538 05:32:09.614559 INFO : Training has run successfully!
539 05:32:09.615056 1D training succeed
540 05:32:09.623726 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 05:32:09.671455 Check phy result
542 05:32:09.672036 INFO : End of initialization
543 05:32:09.693044 INFO : End of 2D read delay Voltage center optimization
544 05:32:09.712253 INFO : End of 2D read delay Voltage center optimization
545 05:32:09.764283 INFO : End of 2D write delay Voltage center optimization
546 05:32:09.813538 INFO : End of 2D write delay Voltage center optimization
547 05:32:09.818971 INFO : Training has run successfully!
548 05:32:09.819415
549 05:32:09.819824 channel==0
550 05:32:09.824509 RxClkDly_Margin_A0==88 ps 9
551 05:32:09.824956 TxDqDly_Margin_A0==98 ps 10
552 05:32:09.830149 RxClkDly_Margin_A1==88 ps 9
553 05:32:09.830642 TxDqDly_Margin_A1==98 ps 10
554 05:32:09.831064 TrainedVREFDQ_A0==74
555 05:32:09.835745 TrainedVREFDQ_A1==74
556 05:32:09.836288 VrefDac_Margin_A0==25
557 05:32:09.836709 DeviceVref_Margin_A0==40
558 05:32:09.841442 VrefDac_Margin_A1==25
559 05:32:09.841930 DeviceVref_Margin_A1==40
560 05:32:09.842374
561 05:32:09.842803
562 05:32:09.846820 channel==1
563 05:32:09.847311 RxClkDly_Margin_A0==88 ps 9
564 05:32:09.847775 TxDqDly_Margin_A0==98 ps 10
565 05:32:09.852556 RxClkDly_Margin_A1==88 ps 9
566 05:32:09.852894 TxDqDly_Margin_A1==88 ps 9
567 05:32:09.858129 TrainedVREFDQ_A0==77
568 05:32:09.858664 TrainedVREFDQ_A1==77
569 05:32:09.859129 VrefDac_Margin_A0==23
570 05:32:09.863754 DeviceVref_Margin_A0==37
571 05:32:09.864272 VrefDac_Margin_A1==24
572 05:32:09.869504 DeviceVref_Margin_A1==37
573 05:32:09.870017
574 05:32:09.870434 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 05:32:09.870868
576 05:32:09.902955 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 05:32:09.903659 2D training succeed
578 05:32:09.908496 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 05:32:09.914063 auto size-- 65535DDR cs0 size: 2048MB
580 05:32:09.915048 DDR cs1 size: 2048MB
581 05:32:09.919758 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 05:32:09.920710 cs0 DataBus test pass
583 05:32:09.925596 cs1 DataBus test pass
584 05:32:09.926531 cs0 AddrBus test pass
585 05:32:09.927346 cs1 AddrBus test pass
586 05:32:09.928339
587 05:32:09.930952 100bdlr_step_size ps== 420
588 05:32:09.931940 result report
589 05:32:09.936472 boot times 0Enable ddr reg access
590 05:32:09.941801 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 05:32:09.955286 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 05:32:10.527240 0.0;M3 CHK:0;cm4_sp_mode 0
593 05:32:10.528115 MVN_1=0x00000000
594 05:32:10.532660 MVN_2=0x00000000
595 05:32:10.538478 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 05:32:10.539074 OPS=0x10
597 05:32:10.539638 ring efuse init
598 05:32:10.540237 chipver efuse init
599 05:32:10.546699 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 05:32:10.547598 [0.018961 Inits done]
601 05:32:10.554234 secure task start!
602 05:32:10.555080 high task start!
603 05:32:10.555902 low task start!
604 05:32:10.556689 run into bl31
605 05:32:10.560949 NOTICE: BL31: v1.3(release):4fc40b1
606 05:32:10.568696 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 05:32:10.569213 NOTICE: BL31: G12A normal boot!
608 05:32:10.594595 NOTICE: BL31: BL33 decompress pass
609 05:32:10.600295 ERROR: Error initializing runtime service opteed_fast
610 05:32:11.833318
611 05:32:11.834458
612 05:32:11.841566 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 05:32:11.842453
614 05:32:11.843304 Model: Libre Computer AML-A311D-CC Alta
615 05:32:12.050000 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 05:32:12.073346 DRAM: 2 GiB (effective 3.8 GiB)
617 05:32:12.216400 Core: 408 devices, 31 uclasses, devicetree: separate
618 05:32:12.222232 WDT: Not starting watchdog@f0d0
619 05:32:12.254533 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 05:32:12.266868 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 05:32:12.271886 ** Bad device specification mmc 0 **
622 05:32:12.282263 Card did not respond to voltage select! : -110
623 05:32:12.289920 ** Bad device specification mmc 0 **
624 05:32:12.290865 Couldn't find partition mmc 0
625 05:32:12.298227 Card did not respond to voltage select! : -110
626 05:32:12.303699 ** Bad device specification mmc 0 **
627 05:32:12.304307 Couldn't find partition mmc 0
628 05:32:12.308734 Error: could not access storage.
629 05:32:12.651298 Net: eth0: ethernet@ff3f0000
630 05:32:12.652039 starting USB...
631 05:32:12.903096 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 05:32:12.903758 Starting the controller
633 05:32:12.909968 USB XHCI 1.10
634 05:32:14.624336 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 05:32:14.625038 bl2_stage_init 0x01
636 05:32:14.625554 bl2_stage_init 0x81
637 05:32:14.629932 hw id: 0x0000 - pwm id 0x01
638 05:32:14.630430 bl2_stage_init 0xc1
639 05:32:14.630880 bl2_stage_init 0x02
640 05:32:14.631320
641 05:32:14.635567 L0:00000000
642 05:32:14.636084 L1:20000703
643 05:32:14.636543 L2:00008067
644 05:32:14.636990 L3:14000000
645 05:32:14.638406 B2:00402000
646 05:32:14.638885 B1:e0f83180
647 05:32:14.639335
648 05:32:14.639786 TE: 58124
649 05:32:14.640270
650 05:32:14.649593 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 05:32:14.650097
652 05:32:14.650555 Board ID = 1
653 05:32:14.650997 Set A53 clk to 24M
654 05:32:14.651433 Set A73 clk to 24M
655 05:32:14.655159 Set clk81 to 24M
656 05:32:14.655653 A53 clk: 1200 MHz
657 05:32:14.656149 A73 clk: 1200 MHz
658 05:32:14.660688 CLK81: 166.6M
659 05:32:14.661183 smccc: 00012a91
660 05:32:14.666383 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 05:32:14.666883 board id: 1
662 05:32:14.674973 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 05:32:14.685641 fw parse done
664 05:32:14.691605 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 05:32:14.734273 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 05:32:14.745032 PIEI prepare done
667 05:32:14.745550 fastboot data load
668 05:32:14.746015 fastboot data verify
669 05:32:14.750760 verify result: 266
670 05:32:14.756680 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 05:32:14.757271 LPDDR4 probe
672 05:32:14.757764 ddr clk to 1584MHz
673 05:32:14.763488 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 05:32:14.801546
675 05:32:14.802142 dmc_version 0001
676 05:32:14.808210 Check phy result
677 05:32:14.814099 INFO : End of CA training
678 05:32:14.814670 INFO : End of initialization
679 05:32:14.819687 INFO : Training has run successfully!
680 05:32:14.820237 Check phy result
681 05:32:14.825213 INFO : End of initialization
682 05:32:14.825763 INFO : End of read enable training
683 05:32:14.830895 INFO : End of fine write leveling
684 05:32:14.836498 INFO : End of Write leveling coarse delay
685 05:32:14.836998 INFO : Training has run successfully!
686 05:32:14.837517 Check phy result
687 05:32:14.842117 INFO : End of initialization
688 05:32:14.842695 INFO : End of read dq deskew training
689 05:32:14.847761 INFO : End of MPR read delay center optimization
690 05:32:14.853270 INFO : End of write delay center optimization
691 05:32:14.858843 INFO : End of read delay center optimization
692 05:32:14.859562 INFO : End of max read latency training
693 05:32:14.864551 INFO : Training has run successfully!
694 05:32:14.865452 1D training succeed
695 05:32:14.873706 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 05:32:14.921278 Check phy result
697 05:32:14.921918 INFO : End of initialization
698 05:32:14.943049 INFO : End of 2D read delay Voltage center optimization
699 05:32:14.962607 INFO : End of 2D read delay Voltage center optimization
700 05:32:15.014693 INFO : End of 2D write delay Voltage center optimization
701 05:32:15.063939 INFO : End of 2D write delay Voltage center optimization
702 05:32:15.069662 INFO : Training has run successfully!
703 05:32:15.070507
704 05:32:15.071390 channel==0
705 05:32:15.075004 RxClkDly_Margin_A0==88 ps 9
706 05:32:15.075849 TxDqDly_Margin_A0==98 ps 10
707 05:32:15.080751 RxClkDly_Margin_A1==88 ps 9
708 05:32:15.081622 TxDqDly_Margin_A1==98 ps 10
709 05:32:15.082393 TrainedVREFDQ_A0==74
710 05:32:15.086333 TrainedVREFDQ_A1==75
711 05:32:15.087098 VrefDac_Margin_A0==24
712 05:32:15.087558 DeviceVref_Margin_A0==40
713 05:32:15.091853 VrefDac_Margin_A1==25
714 05:32:15.092445 DeviceVref_Margin_A1==39
715 05:32:15.092961
716 05:32:15.093472
717 05:32:15.097522 channel==1
718 05:32:15.098066 RxClkDly_Margin_A0==88 ps 9
719 05:32:15.098578 TxDqDly_Margin_A0==98 ps 10
720 05:32:15.103145 RxClkDly_Margin_A1==88 ps 9
721 05:32:15.103693 TxDqDly_Margin_A1==108 ps 11
722 05:32:15.108692 TrainedVREFDQ_A0==77
723 05:32:15.109247 TrainedVREFDQ_A1==77
724 05:32:15.109770 VrefDac_Margin_A0==23
725 05:32:15.114305 DeviceVref_Margin_A0==37
726 05:32:15.114793 VrefDac_Margin_A1==24
727 05:32:15.119923 DeviceVref_Margin_A1==37
728 05:32:15.120489
729 05:32:15.120949 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 05:32:15.125538
731 05:32:15.153426 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000019 0000001a 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 05:32:15.154067 2D training succeed
733 05:32:15.159064 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 05:32:15.164529 auto size-- 65535DDR cs0 size: 2048MB
735 05:32:15.165094 DDR cs1 size: 2048MB
736 05:32:15.170275 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 05:32:15.171213 cs0 DataBus test pass
738 05:32:15.175882 cs1 DataBus test pass
739 05:32:15.176769 cs0 AddrBus test pass
740 05:32:15.177612 cs1 AddrBus test pass
741 05:32:15.178380
742 05:32:15.181438 100bdlr_step_size ps== 420
743 05:32:15.182283 result report
744 05:32:15.186984 boot times 0Enable ddr reg access
745 05:32:15.192330 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 05:32:15.205911 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 05:32:15.778933 0.0;M3 CHK:0;cm4_sp_mode 0
748 05:32:15.779681 MVN_1=0x00000000
749 05:32:15.784413 MVN_2=0x00000000
750 05:32:15.790211 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 05:32:15.790827 OPS=0x10
752 05:32:15.791324 ring efuse init
753 05:32:15.791811 chipver efuse init
754 05:32:15.795919 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 05:32:15.801423 [0.018961 Inits done]
756 05:32:15.801961 secure task start!
757 05:32:15.802400 high task start!
758 05:32:15.806003 low task start!
759 05:32:15.806482 run into bl31
760 05:32:15.812681 NOTICE: BL31: v1.3(release):4fc40b1
761 05:32:15.820505 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 05:32:15.821057 NOTICE: BL31: G12A normal boot!
763 05:32:15.845945 NOTICE: BL31: BL33 decompress pass
764 05:32:15.851331 ERROR: Error initializing runtime service opteed_fast
765 05:32:17.084442
766 05:32:17.085151
767 05:32:17.092888 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 05:32:17.093451
769 05:32:17.093985 Model: Libre Computer AML-A311D-CC Alta
770 05:32:17.301297 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 05:32:17.323716 DRAM: 2 GiB (effective 3.8 GiB)
772 05:32:17.467838 Core: 408 devices, 31 uclasses, devicetree: separate
773 05:32:17.473586 WDT: Not starting watchdog@f0d0
774 05:32:17.505828 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 05:32:17.518282 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 05:32:17.523196 ** Bad device specification mmc 0 **
777 05:32:17.533609 Card did not respond to voltage select! : -110
778 05:32:17.541239 ** Bad device specification mmc 0 **
779 05:32:17.541822 Couldn't find partition mmc 0
780 05:32:17.549670 Card did not respond to voltage select! : -110
781 05:32:17.555148 ** Bad device specification mmc 0 **
782 05:32:17.555736 Couldn't find partition mmc 0
783 05:32:17.559419 Error: could not access storage.
784 05:32:17.901699 Net: eth0: ethernet@ff3f0000
785 05:32:17.902355 starting USB...
786 05:32:18.154346 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 05:32:18.155007 Starting the controller
788 05:32:18.161286 USB XHCI 1.10
789 05:32:20.324612 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 05:32:20.325269 bl2_stage_init 0x01
791 05:32:20.325760 bl2_stage_init 0x81
792 05:32:20.330066 hw id: 0x0000 - pwm id 0x01
793 05:32:20.330605 bl2_stage_init 0xc1
794 05:32:20.331095 bl2_stage_init 0x02
795 05:32:20.331543
796 05:32:20.335723 L0:00000000
797 05:32:20.336320 L1:20000703
798 05:32:20.336774 L2:00008067
799 05:32:20.337206 L3:14000000
800 05:32:20.341280 B2:00402000
801 05:32:20.341764 B1:e0f83180
802 05:32:20.342198
803 05:32:20.342644 TE: 58159
804 05:32:20.343092
805 05:32:20.346811 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 05:32:20.347305
807 05:32:20.347760 Board ID = 1
808 05:32:20.352480 Set A53 clk to 24M
809 05:32:20.352974 Set A73 clk to 24M
810 05:32:20.353408 Set clk81 to 24M
811 05:32:20.358056 A53 clk: 1200 MHz
812 05:32:20.358574 A73 clk: 1200 MHz
813 05:32:20.359007 CLK81: 166.6M
814 05:32:20.359432 smccc: 00012ab5
815 05:32:20.363672 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 05:32:20.369245 board id: 1
817 05:32:20.375107 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 05:32:20.385880 fw parse done
819 05:32:20.390840 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 05:32:20.433464 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 05:32:20.445252 PIEI prepare done
822 05:32:20.445769 fastboot data load
823 05:32:20.446257 fastboot data verify
824 05:32:20.450841 verify result: 266
825 05:32:20.456647 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 05:32:20.457280 LPDDR4 probe
827 05:32:20.457837 ddr clk to 1584MHz
828 05:32:20.463529 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 05:32:20.500824
830 05:32:20.501362 dmc_version 0001
831 05:32:20.507580 Check phy result
832 05:32:20.514252 INFO : End of CA training
833 05:32:20.514749 INFO : End of initialization
834 05:32:20.519910 INFO : Training has run successfully!
835 05:32:20.520471 Check phy result
836 05:32:20.525505 INFO : End of initialization
837 05:32:20.526023 INFO : End of read enable training
838 05:32:20.528956 INFO : End of fine write leveling
839 05:32:20.534446 INFO : End of Write leveling coarse delay
840 05:32:20.540052 INFO : Training has run successfully!
841 05:32:20.540557 Check phy result
842 05:32:20.541007 INFO : End of initialization
843 05:32:20.545640 INFO : End of read dq deskew training
844 05:32:20.549001 INFO : End of MPR read delay center optimization
845 05:32:20.554581 INFO : End of write delay center optimization
846 05:32:20.560184 INFO : End of read delay center optimization
847 05:32:20.560693 INFO : End of max read latency training
848 05:32:20.565737 INFO : Training has run successfully!
849 05:32:20.566255 1D training succeed
850 05:32:20.572991 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 05:32:20.620449 Check phy result
852 05:32:20.620973 INFO : End of initialization
853 05:32:20.643152 INFO : End of 2D read delay Voltage center optimization
854 05:32:20.662593 INFO : End of 2D read delay Voltage center optimization
855 05:32:20.714695 INFO : End of 2D write delay Voltage center optimization
856 05:32:20.764953 INFO : End of 2D write delay Voltage center optimization
857 05:32:20.770339 INFO : Training has run successfully!
858 05:32:20.770844
859 05:32:20.771291 channel==0
860 05:32:20.775941 RxClkDly_Margin_A0==88 ps 9
861 05:32:20.776489 TxDqDly_Margin_A0==98 ps 10
862 05:32:20.781553 RxClkDly_Margin_A1==88 ps 9
863 05:32:20.782043 TxDqDly_Margin_A1==98 ps 10
864 05:32:20.782481 TrainedVREFDQ_A0==74
865 05:32:20.787163 TrainedVREFDQ_A1==75
866 05:32:20.787698 VrefDac_Margin_A0==25
867 05:32:20.788195 DeviceVref_Margin_A0==40
868 05:32:20.792796 VrefDac_Margin_A1==24
869 05:32:20.793373 DeviceVref_Margin_A1==39
870 05:32:20.793907
871 05:32:20.794397
872 05:32:20.798434 channel==1
873 05:32:20.798991 RxClkDly_Margin_A0==88 ps 9
874 05:32:20.799505 TxDqDly_Margin_A0==98 ps 10
875 05:32:20.804017 RxClkDly_Margin_A1==88 ps 9
876 05:32:20.804598 TxDqDly_Margin_A1==88 ps 9
877 05:32:20.809630 TrainedVREFDQ_A0==77
878 05:32:20.810177 TrainedVREFDQ_A1==77
879 05:32:20.810698 VrefDac_Margin_A0==23
880 05:32:20.815223 DeviceVref_Margin_A0==37
881 05:32:20.815780 VrefDac_Margin_A1==24
882 05:32:20.820717 DeviceVref_Margin_A1==37
883 05:32:20.821212
884 05:32:20.821641 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 05:32:20.822065
886 05:32:20.854385 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 05:32:20.855032 2D training succeed
888 05:32:20.860124 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 05:32:20.865696 auto size-- 65535DDR cs0 size: 2048MB
890 05:32:20.866561 DDR cs1 size: 2048MB
891 05:32:20.871216 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 05:32:20.872141 cs0 DataBus test pass
893 05:32:20.876763 cs1 DataBus test pass
894 05:32:20.877610 cs0 AddrBus test pass
895 05:32:20.878354 cs1 AddrBus test pass
896 05:32:20.879124
897 05:32:20.882334 100bdlr_step_size ps== 420
898 05:32:20.883191 result report
899 05:32:20.888001 boot times 0Enable ddr reg access
900 05:32:20.892262 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 05:32:20.905801 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 05:32:21.480383 0.0;M3 CHK:0;cm4_sp_mode 0
903 05:32:21.481091 MVN_1=0x00000000
904 05:32:21.486084 MVN_2=0x00000000
905 05:32:21.491742 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 05:32:21.492673 OPS=0x10
907 05:32:21.493474 ring efuse init
908 05:32:21.494212 chipver efuse init
909 05:32:21.497274 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 05:32:21.503028 [0.018960 Inits done]
911 05:32:21.503693 secure task start!
912 05:32:21.504180 high task start!
913 05:32:21.507433 low task start!
914 05:32:21.507973 run into bl31
915 05:32:21.514100 NOTICE: BL31: v1.3(release):4fc40b1
916 05:32:21.521938 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 05:32:21.522521 NOTICE: BL31: G12A normal boot!
918 05:32:21.547216 NOTICE: BL31: BL33 decompress pass
919 05:32:21.552173 ERROR: Error initializing runtime service opteed_fast
920 05:32:22.785745
921 05:32:22.786339
922 05:32:22.794245 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 05:32:22.794732
924 05:32:22.795139 Model: Libre Computer AML-A311D-CC Alta
925 05:32:23.002583 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 05:32:23.025967 DRAM: 2 GiB (effective 3.8 GiB)
927 05:32:23.168997 Core: 408 devices, 31 uclasses, devicetree: separate
928 05:32:23.174929 WDT: Not starting watchdog@f0d0
929 05:32:23.207247 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 05:32:23.219675 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 05:32:23.224553 ** Bad device specification mmc 0 **
932 05:32:23.234909 Card did not respond to voltage select! : -110
933 05:32:23.242557 ** Bad device specification mmc 0 **
934 05:32:23.243042 Couldn't find partition mmc 0
935 05:32:23.250938 Card did not respond to voltage select! : -110
936 05:32:23.256435 ** Bad device specification mmc 0 **
937 05:32:23.256929 Couldn't find partition mmc 0
938 05:32:23.261463 Error: could not access storage.
939 05:32:23.605027 Net: eth0: ethernet@ff3f0000
940 05:32:23.605604 starting USB...
941 05:32:23.856853 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 05:32:23.857439 Starting the controller
943 05:32:23.863797 USB XHCI 1.10
944 05:32:25.420996 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 05:32:25.429305 scanning usb for storage devices... 0 Storage Device(s) found
947 05:32:25.480839 Hit any key to stop autoboot: 1
948 05:32:25.481763 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 05:32:25.482386 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 05:32:25.482932 Setting prompt string to ['=>']
951 05:32:25.483451 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 05:32:25.496881 0
953 05:32:25.497811 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 05:32:25.498320 Sending with 10 millisecond of delay
956 05:32:26.633609 => setenv autoload no
957 05:32:26.644412 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 05:32:26.648602 setenv autoload no
959 05:32:26.649403 Sending with 10 millisecond of delay
961 05:32:28.446404 => setenv initrd_high 0xffffffff
962 05:32:28.457173 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 05:32:28.458045 setenv initrd_high 0xffffffff
964 05:32:28.458752 Sending with 10 millisecond of delay
966 05:32:30.074972 => setenv fdt_high 0xffffffff
967 05:32:30.085765 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 05:32:30.086583 setenv fdt_high 0xffffffff
969 05:32:30.087289 Sending with 10 millisecond of delay
971 05:32:30.379097 => dhcp
972 05:32:30.389792 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 05:32:30.390591 dhcp
974 05:32:30.391019 Speed: 1000, full duplex
975 05:32:30.391426 BOOTP broadcast 1
976 05:32:30.589133 DHCP client bound to address 192.168.6.27 (199 ms)
977 05:32:30.589896 Sending with 10 millisecond of delay
979 05:32:32.266653 => setenv serverip 192.168.6.2
980 05:32:32.277460 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 05:32:32.278341 setenv serverip 192.168.6.2
982 05:32:32.279050 Sending with 10 millisecond of delay
984 05:32:36.002439 => tftpboot 0x01080000 927272/tftp-deploy-6h7mw4w9/kernel/uImage
985 05:32:36.013226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 05:32:36.014096 tftpboot 0x01080000 927272/tftp-deploy-6h7mw4w9/kernel/uImage
987 05:32:36.014556 Speed: 1000, full duplex
988 05:32:36.015000 Using ethernet@ff3f0000 device
989 05:32:36.015853 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 05:32:36.021349 Filename '927272/tftp-deploy-6h7mw4w9/kernel/uImage'.
991 05:32:36.025322 Load address: 0x1080000
992 05:32:38.908891 Loading: *################################################## 43.6 MiB
993 05:32:38.909484 15.1 MiB/s
994 05:32:38.909932 done
995 05:32:38.913402 Bytes transferred = 45713984 (2b98a40 hex)
996 05:32:38.914262 Sending with 10 millisecond of delay
998 05:32:43.602512 => tftpboot 0x08000000 927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot
999 05:32:43.613290 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 05:32:43.614119 tftpboot 0x08000000 927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot
1001 05:32:43.614564 Speed: 1000, full duplex
1002 05:32:43.614975 Using ethernet@ff3f0000 device
1003 05:32:43.616011 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 05:32:43.627080 Filename '927272/tftp-deploy-6h7mw4w9/ramdisk/ramdisk.cpio.gz.uboot'.
1005 05:32:43.627599 Load address: 0x8000000
1006 05:32:50.340903 Loading: *#######################T ########################## UDP wrong checksum 00000005 0000c4eb
1007 05:32:55.341808 T UDP wrong checksum 00000005 0000c4eb
1008 05:33:01.199114 T UDP wrong checksum 000000ff 00001e57
1009 05:33:01.248443 UDP wrong checksum 000000ff 0000b749
1010 05:33:05.344773 T UDP wrong checksum 00000005 0000c4eb
1011 05:33:25.345857 T T T UDP wrong checksum 00000005 0000c4eb
1012 05:33:27.159350 T UDP wrong checksum 000000ff 0000915a
1013 05:33:27.210745 UDP wrong checksum 000000ff 00002b4d
1014 05:33:40.353168 T T
1015 05:33:40.353840 Retry count exceeded; starting again
1017 05:33:40.355399 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1020 05:33:40.357581 end: 2.4 uboot-commands (duration 00:01:47) [common]
1022 05:33:40.359304 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1024 05:33:40.360517 end: 2 uboot-action (duration 00:01:47) [common]
1026 05:33:40.362172 Cleaning after the job
1027 05:33:40.362759 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/ramdisk
1028 05:33:40.364235 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/kernel
1029 05:33:40.411280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/dtb
1030 05:33:40.412115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/nfsrootfs
1031 05:33:40.658101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927272/tftp-deploy-6h7mw4w9/modules
1032 05:33:40.679061 start: 4.1 power-off (timeout 00:00:30) [common]
1033 05:33:40.679719 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1034 05:33:40.712869 >> OK - accepted request
1035 05:33:40.714907 Returned 0 in 0 seconds
1036 05:33:40.815704 end: 4.1 power-off (duration 00:00:00) [common]
1038 05:33:40.816775 start: 4.2 read-feedback (timeout 00:10:00) [common]
1039 05:33:40.817442 Listened to connection for namespace 'common' for up to 1s
1040 05:33:41.817937 Finalising connection for namespace 'common'
1041 05:33:41.818447 Disconnecting from shell: Finalise
1042 05:33:41.818746 =>
1043 05:33:41.919519 end: 4.2 read-feedback (duration 00:00:01) [common]
1044 05:33:41.920192 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927272
1045 05:33:44.569832 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927272
1046 05:33:44.570448 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.