Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:44:29.498339 lava-dispatcher, installed at version: 2024.01
2 05:44:29.499152 start: 0 validate
3 05:44:29.499636 Start time: 2024-11-02 05:44:29.499606+00:00 (UTC)
4 05:44:29.500201 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:44:29.500772 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:44:29.535236 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:44:29.535779 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:44:29.571255 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:44:29.571873 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:44:29.605884 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:44:29.606386 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:44:29.642161 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:44:29.642691 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:44:29.689700 validate duration: 0.19
16 05:44:29.691324 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:44:29.691962 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:44:29.692631 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:44:29.693871 Not decompressing ramdisk as can be used compressed.
20 05:44:29.694858 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 05:44:29.695497 saving as /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/ramdisk/initrd.cpio.gz
22 05:44:29.696087 total size: 5628140 (5 MB)
23 05:44:29.743173 progress 0 % (0 MB)
24 05:44:29.752288 progress 5 % (0 MB)
25 05:44:29.761141 progress 10 % (0 MB)
26 05:44:29.769043 progress 15 % (0 MB)
27 05:44:29.777708 progress 20 % (1 MB)
28 05:44:29.784461 progress 25 % (1 MB)
29 05:44:29.788621 progress 30 % (1 MB)
30 05:44:29.792682 progress 35 % (1 MB)
31 05:44:29.796405 progress 40 % (2 MB)
32 05:44:29.800537 progress 45 % (2 MB)
33 05:44:29.804217 progress 50 % (2 MB)
34 05:44:29.808307 progress 55 % (2 MB)
35 05:44:29.812361 progress 60 % (3 MB)
36 05:44:29.815968 progress 65 % (3 MB)
37 05:44:29.820105 progress 70 % (3 MB)
38 05:44:29.823845 progress 75 % (4 MB)
39 05:44:29.827927 progress 80 % (4 MB)
40 05:44:29.831518 progress 85 % (4 MB)
41 05:44:29.835471 progress 90 % (4 MB)
42 05:44:29.839163 progress 95 % (5 MB)
43 05:44:29.842472 progress 100 % (5 MB)
44 05:44:29.843129 5 MB downloaded in 0.15 s (36.50 MB/s)
45 05:44:29.843681 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:44:29.844605 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:44:29.844897 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:44:29.845168 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:44:29.845827 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kernel/Image
51 05:44:29.846110 saving as /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/kernel/Image
52 05:44:29.846337 total size: 45713920 (43 MB)
53 05:44:29.846564 No compression specified
54 05:44:29.888198 progress 0 % (0 MB)
55 05:44:29.916089 progress 5 % (2 MB)
56 05:44:29.944126 progress 10 % (4 MB)
57 05:44:29.973831 progress 15 % (6 MB)
58 05:44:30.002206 progress 20 % (8 MB)
59 05:44:30.032250 progress 25 % (10 MB)
60 05:44:30.060049 progress 30 % (13 MB)
61 05:44:30.090231 progress 35 % (15 MB)
62 05:44:30.118816 progress 40 % (17 MB)
63 05:44:30.146625 progress 45 % (19 MB)
64 05:44:30.174392 progress 50 % (21 MB)
65 05:44:30.202528 progress 55 % (24 MB)
66 05:44:30.230588 progress 60 % (26 MB)
67 05:44:30.258033 progress 65 % (28 MB)
68 05:44:30.285792 progress 70 % (30 MB)
69 05:44:30.313880 progress 75 % (32 MB)
70 05:44:30.341929 progress 80 % (34 MB)
71 05:44:30.369540 progress 85 % (37 MB)
72 05:44:30.397503 progress 90 % (39 MB)
73 05:44:30.425596 progress 95 % (41 MB)
74 05:44:30.452722 progress 100 % (43 MB)
75 05:44:30.453312 43 MB downloaded in 0.61 s (71.83 MB/s)
76 05:44:30.453837 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:44:30.454744 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:44:30.455028 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:44:30.455296 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:44:30.455776 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:44:30.456066 saving as /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:44:30.456279 total size: 54703 (0 MB)
84 05:44:30.456489 No compression specified
85 05:44:30.500456 progress 59 % (0 MB)
86 05:44:30.501300 progress 100 % (0 MB)
87 05:44:30.501855 0 MB downloaded in 0.05 s (1.14 MB/s)
88 05:44:30.502344 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:44:30.503156 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:44:30.503418 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:44:30.503680 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:44:30.504177 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 05:44:30.504439 saving as /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/nfsrootfs/full.rootfs.tar
95 05:44:30.504643 total size: 474398908 (452 MB)
96 05:44:30.504854 Using unxz to decompress xz
97 05:44:30.545706 progress 0 % (0 MB)
98 05:44:31.637109 progress 5 % (22 MB)
99 05:44:33.084656 progress 10 % (45 MB)
100 05:44:33.531373 progress 15 % (67 MB)
101 05:44:34.359731 progress 20 % (90 MB)
102 05:44:34.890694 progress 25 % (113 MB)
103 05:44:35.245593 progress 30 % (135 MB)
104 05:44:35.855942 progress 35 % (158 MB)
105 05:44:36.761333 progress 40 % (181 MB)
106 05:44:37.601361 progress 45 % (203 MB)
107 05:44:38.371591 progress 50 % (226 MB)
108 05:44:39.189716 progress 55 % (248 MB)
109 05:44:40.393822 progress 60 % (271 MB)
110 05:44:41.896956 progress 65 % (294 MB)
111 05:44:43.547243 progress 70 % (316 MB)
112 05:44:46.639548 progress 75 % (339 MB)
113 05:44:49.069616 progress 80 % (361 MB)
114 05:44:51.953033 progress 85 % (384 MB)
115 05:44:55.074799 progress 90 % (407 MB)
116 05:44:58.258448 progress 95 % (429 MB)
117 05:45:01.395705 progress 100 % (452 MB)
118 05:45:01.408683 452 MB downloaded in 30.90 s (14.64 MB/s)
119 05:45:01.409915 end: 1.4.1 http-download (duration 00:00:31) [common]
121 05:45:01.412054 end: 1.4 download-retry (duration 00:00:31) [common]
122 05:45:01.412740 start: 1.5 download-retry (timeout 00:09:28) [common]
123 05:45:01.413395 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 05:45:01.414446 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/modules.tar.xz
125 05:45:01.415031 saving as /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/modules/modules.tar
126 05:45:01.415551 total size: 11611500 (11 MB)
127 05:45:01.416142 Using unxz to decompress xz
128 05:45:01.458134 progress 0 % (0 MB)
129 05:45:01.525180 progress 5 % (0 MB)
130 05:45:01.599258 progress 10 % (1 MB)
131 05:45:01.678489 progress 15 % (1 MB)
132 05:45:01.753273 progress 20 % (2 MB)
133 05:45:01.828209 progress 25 % (2 MB)
134 05:45:01.906407 progress 30 % (3 MB)
135 05:45:01.981502 progress 35 % (3 MB)
136 05:45:02.056803 progress 40 % (4 MB)
137 05:45:02.140788 progress 45 % (5 MB)
138 05:45:02.220533 progress 50 % (5 MB)
139 05:45:02.301162 progress 55 % (6 MB)
140 05:45:02.380939 progress 60 % (6 MB)
141 05:45:02.464059 progress 65 % (7 MB)
142 05:45:02.545434 progress 70 % (7 MB)
143 05:45:02.620320 progress 75 % (8 MB)
144 05:45:02.701713 progress 80 % (8 MB)
145 05:45:02.780854 progress 85 % (9 MB)
146 05:45:02.848263 progress 90 % (9 MB)
147 05:45:02.947114 progress 95 % (10 MB)
148 05:45:03.043800 progress 100 % (11 MB)
149 05:45:03.055495 11 MB downloaded in 1.64 s (6.75 MB/s)
150 05:45:03.056144 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:45:03.057800 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:45:03.058323 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 05:45:03.058835 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 05:45:18.779532 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927312/extract-nfsrootfs-4st7rylq
156 05:45:18.780175 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 05:45:18.780467 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 05:45:18.781169 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt
159 05:45:18.781616 makedir: /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin
160 05:45:18.781942 makedir: /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/tests
161 05:45:18.782249 makedir: /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/results
162 05:45:18.782579 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-add-keys
163 05:45:18.783105 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-add-sources
164 05:45:18.783610 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-background-process-start
165 05:45:18.784146 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-background-process-stop
166 05:45:18.784694 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-common-functions
167 05:45:18.785192 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-echo-ipv4
168 05:45:18.785703 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-install-packages
169 05:45:18.786231 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-installed-packages
170 05:45:18.786707 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-os-build
171 05:45:18.787178 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-probe-channel
172 05:45:18.787653 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-probe-ip
173 05:45:18.788152 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-target-ip
174 05:45:18.788628 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-target-mac
175 05:45:18.789108 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-target-storage
176 05:45:18.789609 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-case
177 05:45:18.790114 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-event
178 05:45:18.790589 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-feedback
179 05:45:18.791060 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-raise
180 05:45:18.791526 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-reference
181 05:45:18.792104 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-runner
182 05:45:18.792610 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-set
183 05:45:18.793077 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-test-shell
184 05:45:18.793573 Updating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-install-packages (oe)
185 05:45:18.794119 Updating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/bin/lava-installed-packages (oe)
186 05:45:18.794557 Creating /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/environment
187 05:45:18.794922 LAVA metadata
188 05:45:18.795176 - LAVA_JOB_ID=927312
189 05:45:18.795391 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:45:18.795739 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 05:45:18.796724 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:45:18.797040 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 05:45:18.797249 skipped lava-vland-overlay
194 05:45:18.797491 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:45:18.797745 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 05:45:18.797964 skipped lava-multinode-overlay
197 05:45:18.798206 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:45:18.798455 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 05:45:18.798702 Loading test definitions
200 05:45:18.798979 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 05:45:18.799198 Using /lava-927312 at stage 0
202 05:45:18.800354 uuid=927312_1.6.2.4.1 testdef=None
203 05:45:18.800658 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:45:18.800922 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 05:45:18.802667 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:45:18.803463 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 05:45:18.805630 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:45:18.806460 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 05:45:18.808538 runner path: /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 927312_1.6.2.4.1
212 05:45:18.809099 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:45:18.809857 Creating lava-test-runner.conf files
215 05:45:18.810060 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927312/lava-overlay-2kwf2szt/lava-927312/0 for stage 0
216 05:45:18.810391 - 0_v4l2-decoder-conformance-vp9
217 05:45:18.810730 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:45:18.811000 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 05:45:18.832353 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:45:18.832708 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 05:45:18.832967 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:45:18.833230 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:45:18.833489 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 05:45:19.445198 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:45:19.445680 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 05:45:19.445953 extracting modules file /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927312/extract-nfsrootfs-4st7rylq
227 05:45:20.809434 extracting modules file /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927312/extract-overlay-ramdisk-sg7s40n_/ramdisk
228 05:45:22.221687 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:45:22.222172 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 05:45:22.222471 [common] Applying overlay to NFS
231 05:45:22.222704 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927312/compress-overlay-hnw5n5xv/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927312/extract-nfsrootfs-4st7rylq
232 05:45:22.251900 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:45:22.252289 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 05:45:22.252586 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 05:45:22.252826 Converting downloaded kernel to a uImage
236 05:45:22.253156 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/kernel/Image /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/kernel/uImage
237 05:45:22.743167 output: Image Name:
238 05:45:22.743561 output: Created: Sat Nov 2 05:45:22 2024
239 05:45:22.743790 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:45:22.744057 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 05:45:22.744280 output: Load Address: 01080000
242 05:45:22.744488 output: Entry Point: 01080000
243 05:45:22.744693 output:
244 05:45:22.745030 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 05:45:22.745311 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 05:45:22.745591 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 05:45:22.745863 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:45:22.746134 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 05:45:22.746402 Building ramdisk /var/lib/lava/dispatcher/tmp/927312/extract-overlay-ramdisk-sg7s40n_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927312/extract-overlay-ramdisk-sg7s40n_/ramdisk
250 05:45:24.885564 >> 166823 blocks
251 05:45:32.726205 Adding RAMdisk u-boot header.
252 05:45:32.726927 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927312/extract-overlay-ramdisk-sg7s40n_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927312/extract-overlay-ramdisk-sg7s40n_/ramdisk.cpio.gz.uboot
253 05:45:32.979238 output: Image Name:
254 05:45:32.979667 output: Created: Sat Nov 2 05:45:32 2024
255 05:45:32.979882 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:45:32.980244 output: Data Size: 23436097 Bytes = 22886.81 KiB = 22.35 MiB
257 05:45:32.980810 output: Load Address: 00000000
258 05:45:32.981221 output: Entry Point: 00000000
259 05:45:32.981617 output:
260 05:45:32.982572 rename /var/lib/lava/dispatcher/tmp/927312/extract-overlay-ramdisk-sg7s40n_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot
261 05:45:32.983274 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:45:32.983820 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 05:45:32.984389 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 05:45:32.984863 No LXC device requested
265 05:45:32.985363 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:45:32.985870 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 05:45:32.986361 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:45:32.986773 Checking files for TFTP limit of 4294967296 bytes.
269 05:45:32.989460 end: 1 tftp-deploy (duration 00:01:03) [common]
270 05:45:32.990033 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:45:32.990556 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:45:32.991051 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:45:32.991547 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:45:32.992090 Using kernel file from prepare-kernel: 927312/tftp-deploy-ww2rwd7h/kernel/uImage
275 05:45:32.992718 substitutions:
276 05:45:32.993123 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:45:32.993521 - {DTB_ADDR}: 0x01070000
278 05:45:32.993919 - {DTB}: 927312/tftp-deploy-ww2rwd7h/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:45:32.994312 - {INITRD}: 927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot
280 05:45:32.994704 - {KERNEL_ADDR}: 0x01080000
281 05:45:32.995093 - {KERNEL}: 927312/tftp-deploy-ww2rwd7h/kernel/uImage
282 05:45:32.995481 - {LAVA_MAC}: None
283 05:45:32.995904 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927312/extract-nfsrootfs-4st7rylq
284 05:45:32.996338 - {NFS_SERVER_IP}: 192.168.6.2
285 05:45:32.996728 - {PRESEED_CONFIG}: None
286 05:45:32.997115 - {PRESEED_LOCAL}: None
287 05:45:32.997500 - {RAMDISK_ADDR}: 0x08000000
288 05:45:32.997882 - {RAMDISK}: 927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot
289 05:45:32.998265 - {ROOT_PART}: None
290 05:45:32.998648 - {ROOT}: None
291 05:45:32.999028 - {SERVER_IP}: 192.168.6.2
292 05:45:32.999411 - {TEE_ADDR}: 0x83000000
293 05:45:32.999793 - {TEE}: None
294 05:45:33.000203 Parsed boot commands:
295 05:45:33.000576 - setenv autoload no
296 05:45:33.000958 - setenv initrd_high 0xffffffff
297 05:45:33.001339 - setenv fdt_high 0xffffffff
298 05:45:33.001720 - dhcp
299 05:45:33.002099 - setenv serverip 192.168.6.2
300 05:45:33.002478 - tftpboot 0x01080000 927312/tftp-deploy-ww2rwd7h/kernel/uImage
301 05:45:33.002859 - tftpboot 0x08000000 927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot
302 05:45:33.003239 - tftpboot 0x01070000 927312/tftp-deploy-ww2rwd7h/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:45:33.003619 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927312/extract-nfsrootfs-4st7rylq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:45:33.004030 - bootm 0x01080000 0x08000000 0x01070000
305 05:45:33.004526 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:45:33.006001 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:45:33.006412 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:45:33.021051 Setting prompt string to ['lava-test: # ']
310 05:45:33.022522 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:45:33.023113 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:45:33.023654 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:45:33.024254 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:45:33.025092 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:45:33.057229 >> OK - accepted request
316 05:45:33.059301 Returned 0 in 0 seconds
317 05:45:33.160411 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:45:33.162088 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:45:33.162676 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:45:33.163213 Setting prompt string to ['Hit any key to stop autoboot']
322 05:45:33.163672 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:45:33.165374 Trying 192.168.56.21...
324 05:45:33.165877 Connected to conserv1.
325 05:45:33.166295 Escape character is '^]'.
326 05:45:33.166710
327 05:45:33.167125 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:45:33.167542
329 05:45:45.320406 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 05:45:45.321016 bl2_stage_init 0x01
331 05:45:45.321425 bl2_stage_init 0x81
332 05:45:45.325926 hw id: 0x0000 - pwm id 0x01
333 05:45:45.326377 bl2_stage_init 0xc1
334 05:45:45.326783 bl2_stage_init 0x02
335 05:45:45.327176
336 05:45:45.331486 L0:00000000
337 05:45:45.331916 L1:20000703
338 05:45:45.332354 L2:00008067
339 05:45:45.332751 L3:14000000
340 05:45:45.337050 B2:00402000
341 05:45:45.337476 B1:e0f83180
342 05:45:45.337863
343 05:45:45.338253 TE: 58124
344 05:45:45.338639
345 05:45:45.342642 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 05:45:45.343058
347 05:45:45.343452 Board ID = 1
348 05:45:45.348239 Set A53 clk to 24M
349 05:45:45.348651 Set A73 clk to 24M
350 05:45:45.349039 Set clk81 to 24M
351 05:45:45.353865 A53 clk: 1200 MHz
352 05:45:45.354273 A73 clk: 1200 MHz
353 05:45:45.354660 CLK81: 166.6M
354 05:45:45.355039 smccc: 00012a91
355 05:45:45.359722 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 05:45:45.365037 board id: 1
357 05:45:45.370916 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:45:45.381621 fw parse done
359 05:45:45.387688 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:45:45.430240 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:45:45.441144 PIEI prepare done
362 05:45:45.441564 fastboot data load
363 05:45:45.441956 fastboot data verify
364 05:45:45.446677 verify result: 266
365 05:45:45.452291 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 05:45:45.452709 LPDDR4 probe
367 05:45:45.453098 ddr clk to 1584MHz
368 05:45:45.460242 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:45:45.497519
370 05:45:45.497949 dmc_version 0001
371 05:45:45.504270 Check phy result
372 05:45:45.510077 INFO : End of CA training
373 05:45:45.510502 INFO : End of initialization
374 05:45:45.515743 INFO : Training has run successfully!
375 05:45:45.516211 Check phy result
376 05:45:45.521273 INFO : End of initialization
377 05:45:45.521696 INFO : End of read enable training
378 05:45:45.524683 INFO : End of fine write leveling
379 05:45:45.530294 INFO : End of Write leveling coarse delay
380 05:45:45.535875 INFO : Training has run successfully!
381 05:45:45.536336 Check phy result
382 05:45:45.536729 INFO : End of initialization
383 05:45:45.541966 INFO : End of read dq deskew training
384 05:45:45.547236 INFO : End of MPR read delay center optimization
385 05:45:45.547813 INFO : End of write delay center optimization
386 05:45:45.552831 INFO : End of read delay center optimization
387 05:45:45.558446 INFO : End of max read latency training
388 05:45:45.558950 INFO : Training has run successfully!
389 05:45:45.564055 1D training succeed
390 05:45:45.569993 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:45:45.617395 Check phy result
392 05:45:45.617920 INFO : End of initialization
393 05:45:45.639284 INFO : End of 2D read delay Voltage center optimization
394 05:45:45.658462 INFO : End of 2D read delay Voltage center optimization
395 05:45:45.710408 INFO : End of 2D write delay Voltage center optimization
396 05:45:45.760788 INFO : End of 2D write delay Voltage center optimization
397 05:45:45.766375 INFO : Training has run successfully!
398 05:45:45.766814
399 05:45:45.767244 channel==0
400 05:45:45.771821 RxClkDly_Margin_A0==88 ps 9
401 05:45:45.772301 TxDqDly_Margin_A0==98 ps 10
402 05:45:45.777485 RxClkDly_Margin_A1==88 ps 9
403 05:45:45.777918 TxDqDly_Margin_A1==98 ps 10
404 05:45:45.778328 TrainedVREFDQ_A0==74
405 05:45:45.783101 TrainedVREFDQ_A1==74
406 05:45:45.783533 VrefDac_Margin_A0==25
407 05:45:45.783939 DeviceVref_Margin_A0==40
408 05:45:45.788716 VrefDac_Margin_A1==25
409 05:45:45.789149 DeviceVref_Margin_A1==40
410 05:45:45.789555
411 05:45:45.789963
412 05:45:45.794451 channel==1
413 05:45:45.794891 RxClkDly_Margin_A0==98 ps 10
414 05:45:45.795297 TxDqDly_Margin_A0==88 ps 9
415 05:45:45.799844 RxClkDly_Margin_A1==88 ps 9
416 05:45:45.800294 TxDqDly_Margin_A1==108 ps 11
417 05:45:45.805513 TrainedVREFDQ_A0==76
418 05:45:45.805946 TrainedVREFDQ_A1==78
419 05:45:45.806352 VrefDac_Margin_A0==22
420 05:45:45.811028 DeviceVref_Margin_A0==38
421 05:45:45.811455 VrefDac_Margin_A1==24
422 05:45:45.816740 DeviceVref_Margin_A1==36
423 05:45:45.817165
424 05:45:45.817570 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:45:45.822289
426 05:45:45.850386 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 05:45:45.850935 2D training succeed
428 05:45:45.855852 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:45:45.861503 auto size-- 65535DDR cs0 size: 2048MB
430 05:45:45.861936 DDR cs1 size: 2048MB
431 05:45:45.867105 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:45:45.867536 cs0 DataBus test pass
433 05:45:45.872735 cs1 DataBus test pass
434 05:45:45.873163 cs0 AddrBus test pass
435 05:45:45.873572 cs1 AddrBus test pass
436 05:45:45.873969
437 05:45:45.878264 100bdlr_step_size ps== 420
438 05:45:45.878696 result report
439 05:45:45.883866 boot times 0Enable ddr reg access
440 05:45:45.889377 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:45:45.902832 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 05:45:46.476569 0.0;M3 CHK:0;cm4_sp_mode 0
443 05:45:46.477177 MVN_1=0x00000000
444 05:45:46.481999 MVN_2=0x00000000
445 05:45:46.487795 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 05:45:46.488271 OPS=0x10
447 05:45:46.488680 ring efuse init
448 05:45:46.489078 chipver efuse init
449 05:45:46.493308 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 05:45:46.498906 [0.018961 Inits done]
451 05:45:46.499329 secure task start!
452 05:45:46.499735 high task start!
453 05:45:46.503509 low task start!
454 05:45:46.503928 run into bl31
455 05:45:46.510186 NOTICE: BL31: v1.3(release):4fc40b1
456 05:45:46.517956 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 05:45:46.518392 NOTICE: BL31: G12A normal boot!
458 05:45:46.543436 NOTICE: BL31: BL33 decompress pass
459 05:45:46.549038 ERROR: Error initializing runtime service opteed_fast
460 05:45:47.782143
461 05:45:47.782750
462 05:45:47.790597 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 05:45:47.791097
464 05:45:47.791528 Model: Libre Computer AML-A311D-CC Alta
465 05:45:47.999085 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 05:45:48.022329 DRAM: 2 GiB (effective 3.8 GiB)
467 05:45:48.165225 Core: 408 devices, 31 uclasses, devicetree: separate
468 05:45:48.171350 WDT: Not starting watchdog@f0d0
469 05:45:48.203408 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 05:45:48.215913 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 05:45:48.220996 ** Bad device specification mmc 0 **
472 05:45:48.231250 Card did not respond to voltage select! : -110
473 05:45:48.238991 ** Bad device specification mmc 0 **
474 05:45:48.239420 Couldn't find partition mmc 0
475 05:45:48.247204 Card did not respond to voltage select! : -110
476 05:45:48.252761 ** Bad device specification mmc 0 **
477 05:45:48.253198 Couldn't find partition mmc 0
478 05:45:48.257888 Error: could not access storage.
479 05:45:49.521192 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 05:45:49.521812 bl2_stage_init 0x81
481 05:45:49.526642 hw id: 0x0000 - pwm id 0x01
482 05:45:49.527098 bl2_stage_init 0xc1
483 05:45:49.527517 bl2_stage_init 0x02
484 05:45:49.527921
485 05:45:49.532378 L0:00000000
486 05:45:49.532835 L1:20000703
487 05:45:49.533244 L2:00008067
488 05:45:49.533648 L3:14000000
489 05:45:49.534044 B2:00402000
490 05:45:49.535132 B1:e0f83180
491 05:45:49.535562
492 05:45:49.535967 TE: 58150
493 05:45:49.536407
494 05:45:49.546369 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 05:45:49.546822
496 05:45:49.547232 Board ID = 1
497 05:45:49.547633 Set A53 clk to 24M
498 05:45:49.548056 Set A73 clk to 24M
499 05:45:49.551940 Set clk81 to 24M
500 05:45:49.552394 A53 clk: 1200 MHz
501 05:45:49.552798 A73 clk: 1200 MHz
502 05:45:49.557581 CLK81: 166.6M
503 05:45:49.558008 smccc: 00012aac
504 05:45:49.563061 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 05:45:49.563493 board id: 1
506 05:45:49.571905 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 05:45:49.582281 fw parse done
508 05:45:49.588209 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 05:45:49.630872 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 05:45:49.641720 PIEI prepare done
511 05:45:49.642151 fastboot data load
512 05:45:49.642560 fastboot data verify
513 05:45:49.647354 verify result: 266
514 05:45:49.652922 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 05:45:49.653356 LPDDR4 probe
516 05:45:49.653763 ddr clk to 1584MHz
517 05:45:49.660904 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 05:45:49.698268
519 05:45:49.698711 dmc_version 0001
520 05:45:49.703922 Check phy result
521 05:45:49.710900 INFO : End of CA training
522 05:45:49.711325 INFO : End of initialization
523 05:45:49.716455 INFO : Training has run successfully!
524 05:45:49.716886 Check phy result
525 05:45:49.722085 INFO : End of initialization
526 05:45:49.722537 INFO : End of read enable training
527 05:45:49.727571 INFO : End of fine write leveling
528 05:45:49.733195 INFO : End of Write leveling coarse delay
529 05:45:49.733625 INFO : Training has run successfully!
530 05:45:49.734034 Check phy result
531 05:45:49.738790 INFO : End of initialization
532 05:45:49.739215 INFO : End of read dq deskew training
533 05:45:49.744428 INFO : End of MPR read delay center optimization
534 05:45:49.750022 INFO : End of write delay center optimization
535 05:45:49.755605 INFO : End of read delay center optimization
536 05:45:49.756064 INFO : End of max read latency training
537 05:45:49.761237 INFO : Training has run successfully!
538 05:45:49.761662 1D training succeed
539 05:45:49.769570 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 05:45:49.817893 Check phy result
541 05:45:49.818352 INFO : End of initialization
542 05:45:49.839625 INFO : End of 2D read delay Voltage center optimization
543 05:45:49.859920 INFO : End of 2D read delay Voltage center optimization
544 05:45:49.911911 INFO : End of 2D write delay Voltage center optimization
545 05:45:49.961332 INFO : End of 2D write delay Voltage center optimization
546 05:45:49.966855 INFO : Training has run successfully!
547 05:45:49.967282
548 05:45:49.967688 channel==0
549 05:45:49.972448 RxClkDly_Margin_A0==88 ps 9
550 05:45:49.972885 TxDqDly_Margin_A0==98 ps 10
551 05:45:49.978065 RxClkDly_Margin_A1==88 ps 9
552 05:45:49.978497 TxDqDly_Margin_A1==98 ps 10
553 05:45:49.978909 TrainedVREFDQ_A0==74
554 05:45:49.983644 TrainedVREFDQ_A1==74
555 05:45:49.984118 VrefDac_Margin_A0==25
556 05:45:49.984523 DeviceVref_Margin_A0==40
557 05:45:49.989316 VrefDac_Margin_A1==25
558 05:45:49.989741 DeviceVref_Margin_A1==40
559 05:45:49.990142
560 05:45:49.990538
561 05:45:49.994830 channel==1
562 05:45:49.995255 RxClkDly_Margin_A0==98 ps 10
563 05:45:49.995658 TxDqDly_Margin_A0==98 ps 10
564 05:45:50.000442 RxClkDly_Margin_A1==98 ps 10
565 05:45:50.000873 TxDqDly_Margin_A1==88 ps 9
566 05:45:50.006067 TrainedVREFDQ_A0==77
567 05:45:50.006497 TrainedVREFDQ_A1==77
568 05:45:50.006902 VrefDac_Margin_A0==22
569 05:45:50.011636 DeviceVref_Margin_A0==37
570 05:45:50.012081 VrefDac_Margin_A1==24
571 05:45:50.017332 DeviceVref_Margin_A1==37
572 05:45:50.017755
573 05:45:50.018155 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 05:45:50.022824
575 05:45:50.050844 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
576 05:45:50.051302 2D training succeed
577 05:45:50.056459 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 05:45:50.062039 auto size-- 65535DDR cs0 size: 2048MB
579 05:45:50.062466 DDR cs1 size: 2048MB
580 05:45:50.067639 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 05:45:50.068101 cs0 DataBus test pass
582 05:45:50.073344 cs1 DataBus test pass
583 05:45:50.073769 cs0 AddrBus test pass
584 05:45:50.074170 cs1 AddrBus test pass
585 05:45:50.074565
586 05:45:50.078855 100bdlr_step_size ps== 420
587 05:45:50.079298 result report
588 05:45:50.084434 boot times 0Enable ddr reg access
589 05:45:50.089842 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 05:45:50.103406 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 05:45:50.676485 0.0;M3 CHK:0;cm4_sp_mode 0
592 05:45:50.677062 MVN_1=0x00000000
593 05:45:50.681873 MVN_2=0x00000000
594 05:45:50.687668 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 05:45:50.688206 OPS=0x10
596 05:45:50.688639 ring efuse init
597 05:45:50.689044 chipver efuse init
598 05:45:50.693425 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 05:45:50.698888 [0.018961 Inits done]
600 05:45:50.699310 secure task start!
601 05:45:50.699701 high task start!
602 05:45:50.703445 low task start!
603 05:45:50.703862 run into bl31
604 05:45:50.710100 NOTICE: BL31: v1.3(release):4fc40b1
605 05:45:50.717881 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 05:45:50.718309 NOTICE: BL31: G12A normal boot!
607 05:45:50.743392 NOTICE: BL31: BL33 decompress pass
608 05:45:50.748062 ERROR: Error initializing runtime service opteed_fast
609 05:45:51.981924
610 05:45:51.982493
611 05:45:51.990317 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 05:45:51.990760
613 05:45:51.991170 Model: Libre Computer AML-A311D-CC Alta
614 05:45:52.198705 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 05:45:52.222004 DRAM: 2 GiB (effective 3.8 GiB)
616 05:45:52.365162 Core: 408 devices, 31 uclasses, devicetree: separate
617 05:45:52.370905 WDT: Not starting watchdog@f0d0
618 05:45:52.403134 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 05:45:52.415602 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 05:45:52.420667 ** Bad device specification mmc 0 **
621 05:45:52.430915 Card did not respond to voltage select! : -110
622 05:45:52.438681 ** Bad device specification mmc 0 **
623 05:45:52.439119 Couldn't find partition mmc 0
624 05:45:52.446892 Card did not respond to voltage select! : -110
625 05:45:52.452423 ** Bad device specification mmc 0 **
626 05:45:52.452860 Couldn't find partition mmc 0
627 05:45:52.457465 Error: could not access storage.
628 05:45:52.799092 Net: eth0: ethernet@ff3f0000
629 05:45:52.799569 starting USB...
630 05:45:53.052011 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 05:45:53.052640 Starting the controller
632 05:45:53.058846 USB XHCI 1.10
633 05:45:54.729476 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 05:45:54.730084 bl2_stage_init 0x01
635 05:45:54.730509 bl2_stage_init 0x81
636 05:45:54.735062 hw id: 0x0000 - pwm id 0x01
637 05:45:54.735512 bl2_stage_init 0xc1
638 05:45:54.735922 bl2_stage_init 0x02
639 05:45:54.736382
640 05:45:54.740665 L0:00000000
641 05:45:54.741101 L1:20000703
642 05:45:54.741508 L2:00008067
643 05:45:54.741908 L3:14000000
644 05:45:54.746229 B2:00402000
645 05:45:54.746659 B1:e0f83180
646 05:45:54.747060
647 05:45:54.747461 TE: 58124
648 05:45:54.747860
649 05:45:54.751927 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 05:45:54.752393
651 05:45:54.752803 Board ID = 1
652 05:45:54.757453 Set A53 clk to 24M
653 05:45:54.757889 Set A73 clk to 24M
654 05:45:54.758293 Set clk81 to 24M
655 05:45:54.763062 A53 clk: 1200 MHz
656 05:45:54.763492 A73 clk: 1200 MHz
657 05:45:54.763895 CLK81: 166.6M
658 05:45:54.764329 smccc: 00012a92
659 05:45:54.768653 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 05:45:54.774227 board id: 1
661 05:45:54.780150 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 05:45:54.790809 fw parse done
663 05:45:54.796967 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 05:45:54.840036 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 05:45:54.850425 PIEI prepare done
666 05:45:54.850881 fastboot data load
667 05:45:54.851298 fastboot data verify
668 05:45:54.856220 verify result: 266
669 05:45:54.861705 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 05:45:54.862138 LPDDR4 probe
671 05:45:54.862545 ddr clk to 1584MHz
672 05:45:54.869720 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 05:45:54.906957
674 05:45:54.907408 dmc_version 0001
675 05:45:54.913561 Check phy result
676 05:45:54.919409 INFO : End of CA training
677 05:45:54.919836 INFO : End of initialization
678 05:45:54.925059 INFO : Training has run successfully!
679 05:45:54.925494 Check phy result
680 05:45:54.930605 INFO : End of initialization
681 05:45:54.931034 INFO : End of read enable training
682 05:45:54.936214 INFO : End of fine write leveling
683 05:45:54.941827 INFO : End of Write leveling coarse delay
684 05:45:54.942250 INFO : Training has run successfully!
685 05:45:54.942657 Check phy result
686 05:45:54.947391 INFO : End of initialization
687 05:45:54.947819 INFO : End of read dq deskew training
688 05:45:54.953073 INFO : End of MPR read delay center optimization
689 05:45:54.958527 INFO : End of write delay center optimization
690 05:45:54.964213 INFO : End of read delay center optimization
691 05:45:54.964638 INFO : End of max read latency training
692 05:45:54.969823 INFO : Training has run successfully!
693 05:45:54.970252 1D training succeed
694 05:45:54.978976 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 05:45:55.026519 Check phy result
696 05:45:55.026949 INFO : End of initialization
697 05:45:55.048189 INFO : End of 2D read delay Voltage center optimization
698 05:45:55.068235 INFO : End of 2D read delay Voltage center optimization
699 05:45:55.120254 INFO : End of 2D write delay Voltage center optimization
700 05:45:55.169413 INFO : End of 2D write delay Voltage center optimization
701 05:45:55.175158 INFO : Training has run successfully!
702 05:45:55.175586
703 05:45:55.176052 channel==0
704 05:45:55.180659 RxClkDly_Margin_A0==88 ps 9
705 05:45:55.181087 TxDqDly_Margin_A0==98 ps 10
706 05:45:55.186259 RxClkDly_Margin_A1==88 ps 9
707 05:45:55.186688 TxDqDly_Margin_A1==98 ps 10
708 05:45:55.187096 TrainedVREFDQ_A0==74
709 05:45:55.191784 TrainedVREFDQ_A1==74
710 05:45:55.192245 VrefDac_Margin_A0==25
711 05:45:55.192652 DeviceVref_Margin_A0==40
712 05:45:55.197436 VrefDac_Margin_A1==25
713 05:45:55.197863 DeviceVref_Margin_A1==40
714 05:45:55.198265
715 05:45:55.198664
716 05:45:55.203150 channel==1
717 05:45:55.203574 RxClkDly_Margin_A0==98 ps 10
718 05:45:55.203974 TxDqDly_Margin_A0==98 ps 10
719 05:45:55.208591 RxClkDly_Margin_A1==88 ps 9
720 05:45:55.209020 TxDqDly_Margin_A1==88 ps 9
721 05:45:55.214151 TrainedVREFDQ_A0==77
722 05:45:55.214581 TrainedVREFDQ_A1==77
723 05:45:55.214988 VrefDac_Margin_A0==22
724 05:45:55.219770 DeviceVref_Margin_A0==37
725 05:45:55.220224 VrefDac_Margin_A1==24
726 05:45:55.225349 DeviceVref_Margin_A1==37
727 05:45:55.225777
728 05:45:55.226183 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 05:45:55.226582
730 05:45:55.258971 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
731 05:45:55.259427 2D training succeed
732 05:45:55.264564 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 05:45:55.270178 auto size-- 65535DDR cs0 size: 2048MB
734 05:45:55.270627 DDR cs1 size: 2048MB
735 05:45:55.275767 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 05:45:55.276255 cs0 DataBus test pass
737 05:45:55.281355 cs1 DataBus test pass
738 05:45:55.281784 cs0 AddrBus test pass
739 05:45:55.282186 cs1 AddrBus test pass
740 05:45:55.282583
741 05:45:55.286971 100bdlr_step_size ps== 420
742 05:45:55.287413 result report
743 05:45:55.292534 boot times 0Enable ddr reg access
744 05:45:55.297950 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 05:45:55.311394 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 05:45:55.883365 0.0;M3 CHK:0;cm4_sp_mode 0
747 05:45:55.883909 MVN_1=0x00000000
748 05:45:55.888797 MVN_2=0x00000000
749 05:45:55.894613 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 05:45:55.895103 OPS=0x10
751 05:45:55.895498 ring efuse init
752 05:45:55.895883 chipver efuse init
753 05:45:55.900162 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 05:45:55.905749 [0.018961 Inits done]
755 05:45:55.906163 secure task start!
756 05:45:55.906551 high task start!
757 05:45:55.910327 low task start!
758 05:45:55.910738 run into bl31
759 05:45:55.917073 NOTICE: BL31: v1.3(release):4fc40b1
760 05:45:55.924818 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 05:45:55.925239 NOTICE: BL31: G12A normal boot!
762 05:45:55.950221 NOTICE: BL31: BL33 decompress pass
763 05:45:55.955916 ERROR: Error initializing runtime service opteed_fast
764 05:45:57.188827
765 05:45:57.189433
766 05:45:57.197225 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 05:45:57.197674
768 05:45:57.198091 Model: Libre Computer AML-A311D-CC Alta
769 05:45:57.405670 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 05:45:57.429004 DRAM: 2 GiB (effective 3.8 GiB)
771 05:45:57.572033 Core: 408 devices, 31 uclasses, devicetree: separate
772 05:45:57.577892 WDT: Not starting watchdog@f0d0
773 05:45:57.610127 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 05:45:57.622592 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 05:45:57.627567 ** Bad device specification mmc 0 **
776 05:45:57.637943 Card did not respond to voltage select! : -110
777 05:45:57.645537 ** Bad device specification mmc 0 **
778 05:45:57.645965 Couldn't find partition mmc 0
779 05:45:57.653957 Card did not respond to voltage select! : -110
780 05:45:57.659443 ** Bad device specification mmc 0 **
781 05:45:57.659872 Couldn't find partition mmc 0
782 05:45:57.664497 Error: could not access storage.
783 05:45:58.008078 Net: eth0: ethernet@ff3f0000
784 05:45:58.008560 starting USB...
785 05:45:58.259890 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 05:45:58.260446 Starting the controller
787 05:45:58.266812 USB XHCI 1.10
788 05:46:00.429625 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 05:46:00.430214 bl2_stage_init 0x01
790 05:46:00.430635 bl2_stage_init 0x81
791 05:46:00.435292 hw id: 0x0000 - pwm id 0x01
792 05:46:00.435733 bl2_stage_init 0xc1
793 05:46:00.436196 bl2_stage_init 0x02
794 05:46:00.436604
795 05:46:00.440822 L0:00000000
796 05:46:00.441253 L1:20000703
797 05:46:00.441658 L2:00008067
798 05:46:00.442058 L3:14000000
799 05:46:00.443844 B2:00402000
800 05:46:00.444301 B1:e0f83180
801 05:46:00.444705
802 05:46:00.445102 TE: 58124
803 05:46:00.445502
804 05:46:00.454917 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 05:46:00.455363
806 05:46:00.455773 Board ID = 1
807 05:46:00.456205 Set A53 clk to 24M
808 05:46:00.456609 Set A73 clk to 24M
809 05:46:00.460553 Set clk81 to 24M
810 05:46:00.460981 A53 clk: 1200 MHz
811 05:46:00.461383 A73 clk: 1200 MHz
812 05:46:00.466140 CLK81: 166.6M
813 05:46:00.466565 smccc: 00012a92
814 05:46:00.471797 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 05:46:00.472257 board id: 1
816 05:46:00.480328 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 05:46:00.490950 fw parse done
818 05:46:00.496952 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 05:46:00.539547 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 05:46:00.550397 PIEI prepare done
821 05:46:00.550838 fastboot data load
822 05:46:00.551244 fastboot data verify
823 05:46:00.556024 verify result: 266
824 05:46:00.561589 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 05:46:00.562025 LPDDR4 probe
826 05:46:00.562431 ddr clk to 1584MHz
827 05:46:00.569647 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 05:46:00.606901
829 05:46:00.607334 dmc_version 0001
830 05:46:00.613565 Check phy result
831 05:46:00.619439 INFO : End of CA training
832 05:46:00.619860 INFO : End of initialization
833 05:46:00.625009 INFO : Training has run successfully!
834 05:46:00.625437 Check phy result
835 05:46:00.630620 INFO : End of initialization
836 05:46:00.631051 INFO : End of read enable training
837 05:46:00.636213 INFO : End of fine write leveling
838 05:46:00.641806 INFO : End of Write leveling coarse delay
839 05:46:00.642238 INFO : Training has run successfully!
840 05:46:00.642646 Check phy result
841 05:46:00.647410 INFO : End of initialization
842 05:46:00.647835 INFO : End of read dq deskew training
843 05:46:00.653017 INFO : End of MPR read delay center optimization
844 05:46:00.658661 INFO : End of write delay center optimization
845 05:46:00.664263 INFO : End of read delay center optimization
846 05:46:00.664691 INFO : End of max read latency training
847 05:46:00.669820 INFO : Training has run successfully!
848 05:46:00.670248 1D training succeed
849 05:46:00.679050 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 05:46:00.726601 Check phy result
851 05:46:00.727035 INFO : End of initialization
852 05:46:00.749166 INFO : End of 2D read delay Voltage center optimization
853 05:46:00.769415 INFO : End of 2D read delay Voltage center optimization
854 05:46:00.821443 INFO : End of 2D write delay Voltage center optimization
855 05:46:00.871043 INFO : End of 2D write delay Voltage center optimization
856 05:46:00.876432 INFO : Training has run successfully!
857 05:46:00.876857
858 05:46:00.877264 channel==0
859 05:46:00.882046 RxClkDly_Margin_A0==88 ps 9
860 05:46:00.882483 TxDqDly_Margin_A0==98 ps 10
861 05:46:00.885392 RxClkDly_Margin_A1==88 ps 9
862 05:46:00.885815 TxDqDly_Margin_A1==98 ps 10
863 05:46:00.890975 TrainedVREFDQ_A0==74
864 05:46:00.891448 TrainedVREFDQ_A1==75
865 05:46:00.891860 VrefDac_Margin_A0==24
866 05:46:00.896557 DeviceVref_Margin_A0==40
867 05:46:00.897006 VrefDac_Margin_A1==24
868 05:46:00.902165 DeviceVref_Margin_A1==39
869 05:46:00.902581
870 05:46:00.902967
871 05:46:00.903349 channel==1
872 05:46:00.903732 RxClkDly_Margin_A0==98 ps 10
873 05:46:00.907699 TxDqDly_Margin_A0==88 ps 9
874 05:46:00.908144 RxClkDly_Margin_A1==88 ps 9
875 05:46:00.913363 TxDqDly_Margin_A1==88 ps 9
876 05:46:00.913779 TrainedVREFDQ_A0==75
877 05:46:00.914169 TrainedVREFDQ_A1==77
878 05:46:00.918972 VrefDac_Margin_A0==22
879 05:46:00.919383 DeviceVref_Margin_A0==38
880 05:46:00.924555 VrefDac_Margin_A1==24
881 05:46:00.924967 DeviceVref_Margin_A1==37
882 05:46:00.925350
883 05:46:00.930174 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 05:46:00.930585
885 05:46:00.958025 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
886 05:46:00.963598 2D training succeed
887 05:46:00.969210 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 05:46:00.969623 auto size-- 65535DDR cs0 size: 2048MB
889 05:46:00.974813 DDR cs1 size: 2048MB
890 05:46:00.975224 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 05:46:00.980441 cs0 DataBus test pass
892 05:46:00.980849 cs1 DataBus test pass
893 05:46:00.981234 cs0 AddrBus test pass
894 05:46:00.986003 cs1 AddrBus test pass
895 05:46:00.986411
896 05:46:00.986799 100bdlr_step_size ps== 420
897 05:46:00.987197 result report
898 05:46:00.991630 boot times 0Enable ddr reg access
899 05:46:00.999191 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 05:46:01.012679 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 05:46:01.586423 0.0;M3 CHK:0;cm4_sp_mode 0
902 05:46:01.586989 MVN_1=0x00000000
903 05:46:01.591940 MVN_2=0x00000000
904 05:46:01.597613 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 05:46:01.598049 OPS=0x10
906 05:46:01.598456 ring efuse init
907 05:46:01.598851 chipver efuse init
908 05:46:01.603212 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 05:46:01.608905 [0.018961 Inits done]
910 05:46:01.609327 secure task start!
911 05:46:01.609729 high task start!
912 05:46:01.613414 low task start!
913 05:46:01.613837 run into bl31
914 05:46:01.620065 NOTICE: BL31: v1.3(release):4fc40b1
915 05:46:01.628019 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 05:46:01.628448 NOTICE: BL31: G12A normal boot!
917 05:46:01.653206 NOTICE: BL31: BL33 decompress pass
918 05:46:01.659023 ERROR: Error initializing runtime service opteed_fast
919 05:46:02.891881
920 05:46:02.892440
921 05:46:02.900188 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 05:46:02.900622
923 05:46:02.901030 Model: Libre Computer AML-A311D-CC Alta
924 05:46:03.108623 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 05:46:03.132019 DRAM: 2 GiB (effective 3.8 GiB)
926 05:46:03.275058 Core: 408 devices, 31 uclasses, devicetree: separate
927 05:46:03.280893 WDT: Not starting watchdog@f0d0
928 05:46:03.313164 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 05:46:03.325647 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 05:46:03.330609 ** Bad device specification mmc 0 **
931 05:46:03.341117 Card did not respond to voltage select! : -110
932 05:46:03.348568 ** Bad device specification mmc 0 **
933 05:46:03.349106 Couldn't find partition mmc 0
934 05:46:03.356887 Card did not respond to voltage select! : -110
935 05:46:03.362441 ** Bad device specification mmc 0 **
936 05:46:03.362939 Couldn't find partition mmc 0
937 05:46:03.367464 Error: could not access storage.
938 05:46:03.709965 Net: eth0: ethernet@ff3f0000
939 05:46:03.710538 starting USB...
940 05:46:03.961715 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 05:46:03.962221 Starting the controller
942 05:46:03.967858 USB XHCI 1.10
943 05:46:05.522648 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 05:46:05.530934 scanning usb for storage devices... 0 Storage Device(s) found
946 05:46:05.582491 Hit any key to stop autoboot: 1
947 05:46:05.583262 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
948 05:46:05.583847 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
949 05:46:05.584359 Setting prompt string to ['=>']
950 05:46:05.584851 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
951 05:46:05.598494 0
952 05:46:05.599345 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 05:46:05.599841 Sending with 10 millisecond of delay
955 05:46:06.734438 => setenv autoload no
956 05:46:06.745201 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
957 05:46:06.750188 setenv autoload no
958 05:46:06.750924 Sending with 10 millisecond of delay
960 05:46:08.547418 => setenv initrd_high 0xffffffff
961 05:46:08.558208 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
962 05:46:08.559042 setenv initrd_high 0xffffffff
963 05:46:08.559754 Sending with 10 millisecond of delay
965 05:46:10.176031 => setenv fdt_high 0xffffffff
966 05:46:10.186831 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
967 05:46:10.187627 setenv fdt_high 0xffffffff
968 05:46:10.188364 Sending with 10 millisecond of delay
970 05:46:10.480156 => dhcp
971 05:46:10.490731 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
972 05:46:10.491265 dhcp
973 05:46:10.491523 Speed: 1000, full duplex
974 05:46:10.491752 BOOTP broadcast 1
975 05:46:10.500210 DHCP client bound to address 192.168.6.27 (10 ms)
976 05:46:10.500741 Sending with 10 millisecond of delay
978 05:46:12.176654 => setenv serverip 192.168.6.2
979 05:46:12.187387 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
980 05:46:12.188266 setenv serverip 192.168.6.2
981 05:46:12.188957 Sending with 10 millisecond of delay
983 05:46:15.911588 => tftpboot 0x01080000 927312/tftp-deploy-ww2rwd7h/kernel/uImage
984 05:46:15.922393 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
985 05:46:15.923219 tftpboot 0x01080000 927312/tftp-deploy-ww2rwd7h/kernel/uImage
986 05:46:15.923682 Speed: 1000, full duplex
987 05:46:15.924146 Using ethernet@ff3f0000 device
988 05:46:15.925004 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
989 05:46:15.930523 Filename '927312/tftp-deploy-ww2rwd7h/kernel/uImage'.
990 05:46:15.934345 Load address: 0x1080000
991 05:46:18.730412 Loading: *################################################## 43.6 MiB
992 05:46:18.731010 15.6 MiB/s
993 05:46:18.731447 done
994 05:46:18.734841 Bytes transferred = 45713984 (2b98a40 hex)
995 05:46:18.735640 Sending with 10 millisecond of delay
997 05:46:23.422451 => tftpboot 0x08000000 927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot
998 05:46:23.433194 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
999 05:46:23.433980 tftpboot 0x08000000 927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot
1000 05:46:23.434424 Speed: 1000, full duplex
1001 05:46:23.434842 Using ethernet@ff3f0000 device
1002 05:46:23.435853 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1003 05:46:23.444509 Filename '927312/tftp-deploy-ww2rwd7h/ramdisk/ramdisk.cpio.gz.uboot'.
1004 05:46:23.444966 Load address: 0x8000000
1005 05:46:30.408629 Loading: *#####################T ############################ UDP wrong checksum 00000005 0000817d
1006 05:46:35.409511 T UDP wrong checksum 00000005 0000817d
1007 05:46:45.412793 T T UDP wrong checksum 00000005 0000817d
1008 05:47:05.416940 T T T T UDP wrong checksum 00000005 0000817d
1009 05:47:20.421085 T T
1010 05:47:20.421761 Retry count exceeded; starting again
1012 05:47:20.423313 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1015 05:47:20.425486 end: 2.4 uboot-commands (duration 00:01:47) [common]
1017 05:47:20.426970 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1019 05:47:20.428111 end: 2 uboot-action (duration 00:01:47) [common]
1021 05:47:20.429772 Cleaning after the job
1022 05:47:20.430369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/ramdisk
1023 05:47:20.431970 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/kernel
1024 05:47:20.478173 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/dtb
1025 05:47:20.478941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/nfsrootfs
1026 05:47:20.803278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927312/tftp-deploy-ww2rwd7h/modules
1027 05:47:20.827386 start: 4.1 power-off (timeout 00:00:30) [common]
1028 05:47:20.828091 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1029 05:47:20.864260 >> OK - accepted request
1030 05:47:20.866447 Returned 0 in 0 seconds
1031 05:47:20.967179 end: 4.1 power-off (duration 00:00:00) [common]
1033 05:47:20.968140 start: 4.2 read-feedback (timeout 00:10:00) [common]
1034 05:47:20.968780 Listened to connection for namespace 'common' for up to 1s
1035 05:47:21.969309 Finalising connection for namespace 'common'
1036 05:47:21.969783 Disconnecting from shell: Finalise
1037 05:47:21.970067 =>
1038 05:47:22.070773 end: 4.2 read-feedback (duration 00:00:01) [common]
1039 05:47:22.071406 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927312
1040 05:47:24.627035 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927312
1041 05:47:24.627665 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.