Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:26:09.060788 lava-dispatcher, installed at version: 2024.01
2 05:26:09.061631 start: 0 validate
3 05:26:09.062108 Start time: 2024-11-02 05:26:09.062076+00:00 (UTC)
4 05:26:09.062672 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:26:09.063224 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:26:09.104757 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:26:09.105352 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:26:09.136808 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:26:09.137476 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:26:09.171868 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:26:09.172437 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:26:09.208155 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:26:09.208662 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-299-g11066801dd4b7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:26:09.243487 validate duration: 0.18
16 05:26:09.244407 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:26:09.244782 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:26:09.245160 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:26:09.245837 Not decompressing ramdisk as can be used compressed.
20 05:26:09.246322 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 05:26:09.246608 saving as /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/ramdisk/initrd.cpio.gz
22 05:26:09.246900 total size: 5628140 (5 MB)
23 05:26:09.287755 progress 0 % (0 MB)
24 05:26:09.291869 progress 5 % (0 MB)
25 05:26:09.296373 progress 10 % (0 MB)
26 05:26:09.300138 progress 15 % (0 MB)
27 05:26:09.304325 progress 20 % (1 MB)
28 05:26:09.308084 progress 25 % (1 MB)
29 05:26:09.312254 progress 30 % (1 MB)
30 05:26:09.316406 progress 35 % (1 MB)
31 05:26:09.320144 progress 40 % (2 MB)
32 05:26:09.324209 progress 45 % (2 MB)
33 05:26:09.327949 progress 50 % (2 MB)
34 05:26:09.332165 progress 55 % (2 MB)
35 05:26:09.336479 progress 60 % (3 MB)
36 05:26:09.340178 progress 65 % (3 MB)
37 05:26:09.344154 progress 70 % (3 MB)
38 05:26:09.347776 progress 75 % (4 MB)
39 05:26:09.352149 progress 80 % (4 MB)
40 05:26:09.356373 progress 85 % (4 MB)
41 05:26:09.360698 progress 90 % (4 MB)
42 05:26:09.364541 progress 95 % (5 MB)
43 05:26:09.367853 progress 100 % (5 MB)
44 05:26:09.368559 5 MB downloaded in 0.12 s (44.13 MB/s)
45 05:26:09.369099 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:26:09.369971 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:26:09.370257 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:26:09.370524 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:26:09.370973 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/kernel/Image
51 05:26:09.371210 saving as /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/kernel/Image
52 05:26:09.371417 total size: 45713920 (43 MB)
53 05:26:09.371625 No compression specified
54 05:26:09.405448 progress 0 % (0 MB)
55 05:26:09.434123 progress 5 % (2 MB)
56 05:26:09.462874 progress 10 % (4 MB)
57 05:26:09.491675 progress 15 % (6 MB)
58 05:26:09.520043 progress 20 % (8 MB)
59 05:26:09.548370 progress 25 % (10 MB)
60 05:26:09.577110 progress 30 % (13 MB)
61 05:26:09.606601 progress 35 % (15 MB)
62 05:26:09.635462 progress 40 % (17 MB)
63 05:26:09.664483 progress 45 % (19 MB)
64 05:26:09.693640 progress 50 % (21 MB)
65 05:26:09.722634 progress 55 % (24 MB)
66 05:26:09.751766 progress 60 % (26 MB)
67 05:26:09.780675 progress 65 % (28 MB)
68 05:26:09.809438 progress 70 % (30 MB)
69 05:26:09.838217 progress 75 % (32 MB)
70 05:26:09.867341 progress 80 % (34 MB)
71 05:26:09.896263 progress 85 % (37 MB)
72 05:26:09.925314 progress 90 % (39 MB)
73 05:26:09.954607 progress 95 % (41 MB)
74 05:26:09.983501 progress 100 % (43 MB)
75 05:26:09.984104 43 MB downloaded in 0.61 s (71.16 MB/s)
76 05:26:09.984595 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:26:09.985412 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:26:09.985685 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:26:09.985949 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:26:09.986431 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 05:26:09.986708 saving as /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 05:26:09.986915 total size: 53209 (0 MB)
84 05:26:09.987122 No compression specified
85 05:26:10.030439 progress 61 % (0 MB)
86 05:26:10.031606 progress 100 % (0 MB)
87 05:26:10.032339 0 MB downloaded in 0.05 s (1.12 MB/s)
88 05:26:10.032959 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:26:10.033980 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:26:10.034320 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:26:10.034679 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:26:10.035280 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 05:26:10.035610 saving as /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/nfsrootfs/full.rootfs.tar
95 05:26:10.035860 total size: 474398908 (452 MB)
96 05:26:10.036181 Using unxz to decompress xz
97 05:26:10.075804 progress 0 % (0 MB)
98 05:26:11.315788 progress 5 % (22 MB)
99 05:26:12.810171 progress 10 % (45 MB)
100 05:26:13.262886 progress 15 % (67 MB)
101 05:26:14.080338 progress 20 % (90 MB)
102 05:26:14.594713 progress 25 % (113 MB)
103 05:26:14.956753 progress 30 % (135 MB)
104 05:26:15.582978 progress 35 % (158 MB)
105 05:26:16.422336 progress 40 % (181 MB)
106 05:26:17.179571 progress 45 % (203 MB)
107 05:26:17.745190 progress 50 % (226 MB)
108 05:26:18.371866 progress 55 % (248 MB)
109 05:26:19.575232 progress 60 % (271 MB)
110 05:26:21.089235 progress 65 % (294 MB)
111 05:26:22.738219 progress 70 % (316 MB)
112 05:26:25.841853 progress 75 % (339 MB)
113 05:26:28.286327 progress 80 % (361 MB)
114 05:26:31.361032 progress 85 % (384 MB)
115 05:26:34.593763 progress 90 % (407 MB)
116 05:26:37.870171 progress 95 % (429 MB)
117 05:26:41.060970 progress 100 % (452 MB)
118 05:26:41.073856 452 MB downloaded in 31.04 s (14.58 MB/s)
119 05:26:41.074815 end: 1.4.1 http-download (duration 00:00:31) [common]
121 05:26:41.076659 end: 1.4 download-retry (duration 00:00:31) [common]
122 05:26:41.077253 start: 1.5 download-retry (timeout 00:09:28) [common]
123 05:26:41.077835 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 05:26:41.078773 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-299-g11066801dd4b7/arm64/defconfig/gcc-12/modules.tar.xz
125 05:26:41.079287 saving as /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/modules/modules.tar
126 05:26:41.079744 total size: 11611500 (11 MB)
127 05:26:41.080249 Using unxz to decompress xz
128 05:26:41.123837 progress 0 % (0 MB)
129 05:26:41.192090 progress 5 % (0 MB)
130 05:26:41.267591 progress 10 % (1 MB)
131 05:26:41.348116 progress 15 % (1 MB)
132 05:26:41.424163 progress 20 % (2 MB)
133 05:26:41.500391 progress 25 % (2 MB)
134 05:26:41.579043 progress 30 % (3 MB)
135 05:26:41.655125 progress 35 % (3 MB)
136 05:26:41.730336 progress 40 % (4 MB)
137 05:26:41.814787 progress 45 % (5 MB)
138 05:26:41.895375 progress 50 % (5 MB)
139 05:26:41.973267 progress 55 % (6 MB)
140 05:26:42.053544 progress 60 % (6 MB)
141 05:26:42.137486 progress 65 % (7 MB)
142 05:26:42.219108 progress 70 % (7 MB)
143 05:26:42.295090 progress 75 % (8 MB)
144 05:26:42.376672 progress 80 % (8 MB)
145 05:26:42.456293 progress 85 % (9 MB)
146 05:26:42.523811 progress 90 % (9 MB)
147 05:26:42.622194 progress 95 % (10 MB)
148 05:26:42.720012 progress 100 % (11 MB)
149 05:26:42.731643 11 MB downloaded in 1.65 s (6.70 MB/s)
150 05:26:42.732797 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:26:42.734927 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:26:42.735626 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 05:26:42.736351 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 05:27:00.205232 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927230/extract-nfsrootfs-qlc3d6gs
156 05:27:00.205868 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 05:27:00.206203 start: 1.6.2 lava-overlay (timeout 00:09:09) [common]
158 05:27:00.206944 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr
159 05:27:00.207445 makedir: /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin
160 05:27:00.207857 makedir: /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/tests
161 05:27:00.208365 makedir: /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/results
162 05:27:00.208723 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-add-keys
163 05:27:00.209259 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-add-sources
164 05:27:00.209774 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-background-process-start
165 05:27:00.210278 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-background-process-stop
166 05:27:00.210803 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-common-functions
167 05:27:00.211293 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-echo-ipv4
168 05:27:00.211772 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-install-packages
169 05:27:00.212296 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-installed-packages
170 05:27:00.212777 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-os-build
171 05:27:00.213273 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-probe-channel
172 05:27:00.213802 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-probe-ip
173 05:27:00.214289 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-target-ip
174 05:27:00.214832 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-target-mac
175 05:27:00.215318 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-target-storage
176 05:27:00.215799 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-case
177 05:27:00.216331 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-event
178 05:27:00.216809 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-feedback
179 05:27:00.217301 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-raise
180 05:27:00.217835 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-reference
181 05:27:00.218319 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-runner
182 05:27:00.218794 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-set
183 05:27:00.219265 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-test-shell
184 05:27:00.219746 Updating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-install-packages (oe)
185 05:27:00.220307 Updating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/bin/lava-installed-packages (oe)
186 05:27:00.220745 Creating /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/environment
187 05:27:00.221110 LAVA metadata
188 05:27:00.221365 - LAVA_JOB_ID=927230
189 05:27:00.221577 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:27:00.221928 start: 1.6.2.1 ssh-authorize (timeout 00:09:09) [common]
191 05:27:00.222873 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:27:00.223177 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:09) [common]
193 05:27:00.223384 skipped lava-vland-overlay
194 05:27:00.223624 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:27:00.223877 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:09) [common]
196 05:27:00.224130 skipped lava-multinode-overlay
197 05:27:00.224377 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:27:00.224628 start: 1.6.2.4 test-definition (timeout 00:09:09) [common]
199 05:27:00.224873 Loading test definitions
200 05:27:00.225146 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:09) [common]
201 05:27:00.225366 Using /lava-927230 at stage 0
202 05:27:00.226534 uuid=927230_1.6.2.4.1 testdef=None
203 05:27:00.226841 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:27:00.227105 start: 1.6.2.4.2 test-overlay (timeout 00:09:09) [common]
205 05:27:00.228836 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:27:00.229617 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:09) [common]
208 05:27:00.231713 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:27:00.232561 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:09) [common]
211 05:27:00.234589 runner path: /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 927230_1.6.2.4.1
212 05:27:00.235148 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:27:00.235895 Creating lava-test-runner.conf files
215 05:27:00.236119 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927230/lava-overlay-z8lfnfdr/lava-927230/0 for stage 0
216 05:27:00.236452 - 0_v4l2-decoder-conformance-vp9
217 05:27:00.236788 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:27:00.237055 start: 1.6.2.5 compress-overlay (timeout 00:09:09) [common]
219 05:27:00.258399 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:27:00.258748 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:09) [common]
221 05:27:00.259004 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:27:00.259266 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:27:00.259523 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
224 05:27:00.951109 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:27:00.951591 start: 1.6.4 extract-modules (timeout 00:09:08) [common]
226 05:27:00.951861 extracting modules file /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927230/extract-nfsrootfs-qlc3d6gs
227 05:27:02.312247 extracting modules file /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927230/extract-overlay-ramdisk-27ifm43k/ramdisk
228 05:27:03.705890 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:27:03.706347 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 05:27:03.706639 [common] Applying overlay to NFS
231 05:27:03.706865 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927230/compress-overlay-7e_h4pzw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927230/extract-nfsrootfs-qlc3d6gs
232 05:27:03.735894 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:27:03.736299 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 05:27:03.736592 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 05:27:03.736830 Converting downloaded kernel to a uImage
236 05:27:03.737146 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/kernel/Image /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/kernel/uImage
237 05:27:04.201661 output: Image Name:
238 05:27:04.202066 output: Created: Sat Nov 2 05:27:03 2024
239 05:27:04.202292 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:27:04.202506 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 05:27:04.202713 output: Load Address: 01080000
242 05:27:04.202916 output: Entry Point: 01080000
243 05:27:04.203119 output:
244 05:27:04.203453 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 05:27:04.203731 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 05:27:04.204040 start: 1.6.7 configure-preseed-file (timeout 00:09:05) [common]
247 05:27:04.204319 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:27:04.204592 start: 1.6.8 compress-ramdisk (timeout 00:09:05) [common]
249 05:27:04.204857 Building ramdisk /var/lib/lava/dispatcher/tmp/927230/extract-overlay-ramdisk-27ifm43k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927230/extract-overlay-ramdisk-27ifm43k/ramdisk
250 05:27:06.346841 >> 166823 blocks
251 05:27:14.297120 Adding RAMdisk u-boot header.
252 05:27:14.297750 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927230/extract-overlay-ramdisk-27ifm43k/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927230/extract-overlay-ramdisk-27ifm43k/ramdisk.cpio.gz.uboot
253 05:27:14.560914 output: Image Name:
254 05:27:14.561328 output: Created: Sat Nov 2 05:27:14 2024
255 05:27:14.561538 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:27:14.561743 output: Data Size: 23435801 Bytes = 22886.52 KiB = 22.35 MiB
257 05:27:14.561942 output: Load Address: 00000000
258 05:27:14.562138 output: Entry Point: 00000000
259 05:27:14.562334 output:
260 05:27:14.562928 rename /var/lib/lava/dispatcher/tmp/927230/extract-overlay-ramdisk-27ifm43k/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot
261 05:27:14.563345 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:27:14.563632 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
263 05:27:14.563905 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 05:27:14.564336 No LXC device requested
265 05:27:14.564845 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:27:14.565382 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 05:27:14.565877 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:27:14.566290 Checking files for TFTP limit of 4294967296 bytes.
269 05:27:14.568960 end: 1 tftp-deploy (duration 00:01:05) [common]
270 05:27:14.569534 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:27:14.570048 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:27:14.570537 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:27:14.571033 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:27:14.571544 Using kernel file from prepare-kernel: 927230/tftp-deploy-sxt3bra_/kernel/uImage
275 05:27:14.572192 substitutions:
276 05:27:14.572602 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:27:14.573002 - {DTB_ADDR}: 0x01070000
278 05:27:14.573396 - {DTB}: 927230/tftp-deploy-sxt3bra_/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 05:27:14.573791 - {INITRD}: 927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot
280 05:27:14.574182 - {KERNEL_ADDR}: 0x01080000
281 05:27:14.574571 - {KERNEL}: 927230/tftp-deploy-sxt3bra_/kernel/uImage
282 05:27:14.574956 - {LAVA_MAC}: None
283 05:27:14.575378 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927230/extract-nfsrootfs-qlc3d6gs
284 05:27:14.575770 - {NFS_SERVER_IP}: 192.168.6.2
285 05:27:14.576183 - {PRESEED_CONFIG}: None
286 05:27:14.576573 - {PRESEED_LOCAL}: None
287 05:27:14.576959 - {RAMDISK_ADDR}: 0x08000000
288 05:27:14.577342 - {RAMDISK}: 927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot
289 05:27:14.577725 - {ROOT_PART}: None
290 05:27:14.578109 - {ROOT}: None
291 05:27:14.578491 - {SERVER_IP}: 192.168.6.2
292 05:27:14.578871 - {TEE_ADDR}: 0x83000000
293 05:27:14.579253 - {TEE}: None
294 05:27:14.579636 Parsed boot commands:
295 05:27:14.580027 - setenv autoload no
296 05:27:14.580418 - setenv initrd_high 0xffffffff
297 05:27:14.580800 - setenv fdt_high 0xffffffff
298 05:27:14.581181 - dhcp
299 05:27:14.581562 - setenv serverip 192.168.6.2
300 05:27:14.581940 - tftpboot 0x01080000 927230/tftp-deploy-sxt3bra_/kernel/uImage
301 05:27:14.582320 - tftpboot 0x08000000 927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot
302 05:27:14.582698 - tftpboot 0x01070000 927230/tftp-deploy-sxt3bra_/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 05:27:14.583078 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/927230/extract-nfsrootfs-qlc3d6gs,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:27:14.583471 - bootm 0x01080000 0x08000000 0x01070000
305 05:27:14.583962 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:27:14.585446 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:27:14.585859 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 05:27:14.602194 Setting prompt string to ['lava-test: # ']
310 05:27:14.603659 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:27:14.604288 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:27:14.604824 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:27:14.605347 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:27:14.606505 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 05:27:14.644123 >> OK - accepted request
316 05:27:14.646487 Returned 0 in 0 seconds
317 05:27:14.747608 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:27:14.749227 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:27:14.749791 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:27:14.750297 Setting prompt string to ['Hit any key to stop autoboot']
322 05:27:14.750748 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:27:14.752332 Trying 192.168.56.21...
324 05:27:14.752797 Connected to conserv1.
325 05:27:14.753213 Escape character is '^]'.
326 05:27:14.753619
327 05:27:14.754027 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 05:27:14.754430
329 05:27:21.976370 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 05:27:21.977058 bl2_stage_init 0x01
331 05:27:21.977563 bl2_stage_init 0x81
332 05:27:21.981206 hw id: 0x0000 - pwm id 0x01
333 05:27:21.981880 bl2_stage_init 0xc1
334 05:27:21.986877 bl2_stage_init 0x02
335 05:27:21.987611
336 05:27:21.988150 L0:00000000
337 05:27:21.988628 L1:00000703
338 05:27:21.989075 L2:00008067
339 05:27:21.989523 L3:15000000
340 05:27:21.992807 S1:00000000
341 05:27:21.993448 B2:20282000
342 05:27:21.993955 B1:a0f83180
343 05:27:21.994430
344 05:27:21.994904 TE: 70679
345 05:27:21.995367
346 05:27:21.998862 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 05:27:21.999251
348 05:27:22.003301 Board ID = 1
349 05:27:22.003637 Set cpu clk to 24M
350 05:27:22.003846 Set clk81 to 24M
351 05:27:22.008792 Use GP1_pll as DSU clk.
352 05:27:22.009064 DSU clk: 1200 Mhz
353 05:27:22.009270 CPU clk: 1200 MHz
354 05:27:22.014671 Set clk81 to 166.6M
355 05:27:22.020296 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 05:27:22.020878 board id: 1
357 05:27:22.027333 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:27:22.038265 fw parse done
359 05:27:22.044222 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:27:22.087173 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:27:22.098418 PIEI prepare done
362 05:27:22.099001 fastboot data load
363 05:27:22.099443 fastboot data verify
364 05:27:22.104011 verify result: 266
365 05:27:22.109578 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 05:27:22.110102 LPDDR4 probe
367 05:27:22.110521 ddr clk to 1584MHz
368 05:27:22.117673 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:27:22.155350
370 05:27:22.155899 dmc_version 0001
371 05:27:22.162372 Check phy result
372 05:27:22.168324 INFO : End of CA training
373 05:27:22.168812 INFO : End of initialization
374 05:27:22.173933 INFO : Training has run successfully!
375 05:27:22.174415 Check phy result
376 05:27:22.179579 INFO : End of initialization
377 05:27:22.180083 INFO : End of read enable training
378 05:27:22.185111 INFO : End of fine write leveling
379 05:27:22.190720 INFO : End of Write leveling coarse delay
380 05:27:22.191204 INFO : Training has run successfully!
381 05:27:22.191615 Check phy result
382 05:27:22.196345 INFO : End of initialization
383 05:27:22.196830 INFO : End of read dq deskew training
384 05:27:22.201898 INFO : End of MPR read delay center optimization
385 05:27:22.207580 INFO : End of write delay center optimization
386 05:27:22.213128 INFO : End of read delay center optimization
387 05:27:22.213612 INFO : End of max read latency training
388 05:27:22.218727 INFO : Training has run successfully!
389 05:27:22.219209 1D training succeed
390 05:27:22.227842 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:27:22.276225 Check phy result
392 05:27:22.276768 INFO : End of initialization
393 05:27:22.303684 INFO : End of 2D read delay Voltage center optimization
394 05:27:22.327793 INFO : End of 2D read delay Voltage center optimization
395 05:27:22.384471 INFO : End of 2D write delay Voltage center optimization
396 05:27:22.438509 INFO : End of 2D write delay Voltage center optimization
397 05:27:22.444065 INFO : Training has run successfully!
398 05:27:22.444559
399 05:27:22.444972 channel==0
400 05:27:22.449670 RxClkDly_Margin_A0==88 ps 9
401 05:27:22.450119 TxDqDly_Margin_A0==98 ps 10
402 05:27:22.455206 RxClkDly_Margin_A1==88 ps 9
403 05:27:22.455656 TxDqDly_Margin_A1==98 ps 10
404 05:27:22.456095 TrainedVREFDQ_A0==74
405 05:27:22.460798 TrainedVREFDQ_A1==74
406 05:27:22.461248 VrefDac_Margin_A0==22
407 05:27:22.461650 DeviceVref_Margin_A0==40
408 05:27:22.466457 VrefDac_Margin_A1==23
409 05:27:22.466910 DeviceVref_Margin_A1==40
410 05:27:22.467312
411 05:27:22.467707
412 05:27:22.471953 channel==1
413 05:27:22.472404 RxClkDly_Margin_A0==78 ps 8
414 05:27:22.472803 TxDqDly_Margin_A0==98 ps 10
415 05:27:22.477600 RxClkDly_Margin_A1==78 ps 8
416 05:27:22.478030 TxDqDly_Margin_A1==78 ps 8
417 05:27:22.483161 TrainedVREFDQ_A0==78
418 05:27:22.483591 TrainedVREFDQ_A1==75
419 05:27:22.484018 VrefDac_Margin_A0==22
420 05:27:22.488777 DeviceVref_Margin_A0==36
421 05:27:22.489224 VrefDac_Margin_A1==22
422 05:27:22.494489 DeviceVref_Margin_A1==39
423 05:27:22.494921
424 05:27:22.495329 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:27:22.495727
426 05:27:22.528027 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
427 05:27:22.528601 2D training succeed
428 05:27:22.533579 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:27:22.539171 auto size-- 65535DDR cs0 size: 2048MB
430 05:27:22.539608 DDR cs1 size: 2048MB
431 05:27:22.544765 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:27:22.545209 cs0 DataBus test pass
433 05:27:22.550442 cs1 DataBus test pass
434 05:27:22.550879 cs0 AddrBus test pass
435 05:27:22.551283 cs1 AddrBus test pass
436 05:27:22.551677
437 05:27:22.556041 100bdlr_step_size ps== 471
438 05:27:22.556502 result report
439 05:27:22.561598 boot times 0Enable ddr reg access
440 05:27:22.566858 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:27:22.580740 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 05:27:23.240154 bl2z: ptr: 05129330, size: 00001e40
443 05:27:23.248870 0.0;M3 CHK:0;cm4_sp_mode 0
444 05:27:23.249427 MVN_1=0x00000000
445 05:27:23.249995 MVN_2=0x00000000
446 05:27:23.260341 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 05:27:23.260687 OPS=0x04
448 05:27:23.261114 ring efuse init
449 05:27:23.263152 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 05:27:23.268969 [0.017354 Inits done]
451 05:27:23.269462 secure task start!
452 05:27:23.269859 high task start!
453 05:27:23.270249 low task start!
454 05:27:23.273252 run into bl31
455 05:27:23.281910 NOTICE: BL31: v1.3(release):4fc40b1
456 05:27:23.289724 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 05:27:23.290226 NOTICE: BL31: G12A normal boot!
458 05:27:23.305266 NOTICE: BL31: BL33 decompress pass
459 05:27:23.313423 ERROR: Error initializing runtime service opteed_fast
460 05:27:24.525315 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 05:27:24.525991 bl2_stage_init 0x01
462 05:27:24.526485 bl2_stage_init 0x81
463 05:27:24.530930 hw id: 0x0000 - pwm id 0x01
464 05:27:24.531458 bl2_stage_init 0xc1
465 05:27:24.536495 bl2_stage_init 0x02
466 05:27:24.537012
467 05:27:24.537472 L0:00000000
468 05:27:24.537916 L1:00000703
469 05:27:24.538359 L2:00008067
470 05:27:24.538795 L3:15000000
471 05:27:24.542077 S1:00000000
472 05:27:24.542611 B2:20282000
473 05:27:24.543062 B1:a0f83180
474 05:27:24.543501
475 05:27:24.543939 TE: 70515
476 05:27:24.544435
477 05:27:24.547716 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 05:27:24.548262
479 05:27:24.553301 Board ID = 1
480 05:27:24.553813 Set cpu clk to 24M
481 05:27:24.554262 Set clk81 to 24M
482 05:27:24.558919 Use GP1_pll as DSU clk.
483 05:27:24.559435 DSU clk: 1200 Mhz
484 05:27:24.559885 CPU clk: 1200 MHz
485 05:27:24.564515 Set clk81 to 166.6M
486 05:27:24.570097 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 05:27:24.570613 board id: 1
488 05:27:24.577297 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 05:27:24.588207 fw parse done
490 05:27:24.594171 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 05:27:24.637264 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 05:27:24.648480 PIEI prepare done
493 05:27:24.649012 fastboot data load
494 05:27:24.649467 fastboot data verify
495 05:27:24.654063 verify result: 266
496 05:27:24.659654 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 05:27:24.660218 LPDDR4 probe
498 05:27:24.660676 ddr clk to 1584MHz
499 05:27:26.026677 Load ddrfw from SPI, src: 0x00018000, SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 05:27:26.027398 bl2_stage_init 0x01
501 05:27:26.027889 bl2_stage_init 0x81
502 05:27:26.032073 hw id: 0x0000 - pwm id 0x01
503 05:27:26.032658 bl2_stage_init 0xc1
504 05:27:26.036488 bl2_stage_init 0x02
505 05:27:26.037098
506 05:27:26.037539 L0:00000000
507 05:27:26.037966 L1:00000703
508 05:27:26.038392 L2:00008067
509 05:27:26.042194 L3:15000000
510 05:27:26.042759 S1:00000000
511 05:27:26.043203 B2:20282000
512 05:27:26.043632 B1:a0f83180
513 05:27:26.044095
514 05:27:26.044532 TE: 70568
515 05:27:26.044962
516 05:27:26.053271 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 05:27:26.053965
518 05:27:26.054627 Board ID = 1
519 05:27:26.055272 Set cpu clk to 24M
520 05:27:26.055848 Set clk81 to 24M
521 05:27:26.058964 Use GP1_pll as DSU clk.
522 05:27:26.059532 DSU clk: 1200 Mhz
523 05:27:26.059962 CPU clk: 1200 MHz
524 05:27:26.064562 Set clk81 to 166.6M
525 05:27:26.070214 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 05:27:26.070800 board id: 1
527 05:27:26.078492 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 05:27:26.089514 fw parse done
529 05:27:26.095390 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 05:27:26.138500 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 05:27:26.149624 PIEI prepare done
532 05:27:26.150284 fastboot data load
533 05:27:26.150775 fastboot data verify
534 05:27:26.155248 verify result: 266
535 05:27:26.160769 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 05:27:26.161491 LPDDR4 probe
537 05:27:26.161957 ddr clk to 1584MHz
538 05:27:26.168937 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 05:27:26.215907
540 05:27:26.216626 dmc_version 0001
541 05:27:26.217077 Check phy result
542 05:27:26.219481 INFO : End of CA training
543 05:27:26.220110 INFO : End of initialization
544 05:27:26.225194 INFO : Training has run successfully!
545 05:27:26.225852 Check phy result
546 05:27:26.230625 INFO : End of initialization
547 05:27:26.231233 INFO : End of read enable training
548 05:27:26.236330 INFO : End of fine write leveling
549 05:27:26.241868 INFO : End of Write leveling coarse delay
550 05:27:26.242460 INFO : Training has run successfully!
551 05:27:26.242904 Check phy result
552 05:27:26.247484 INFO : End of initialization
553 05:27:26.248130 INFO : End of read dq deskew training
554 05:27:26.253075 INFO : End of MPR read delay center optimization
555 05:27:26.258602 INFO : End of write delay center optimization
556 05:27:26.264288 INFO : End of read delay center optimization
557 05:27:26.264886 INFO : End of max read latency training
558 05:27:26.269809 INFO : Training has run successfully!
559 05:27:26.270348 1D training succeed
560 05:27:26.278880 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 05:27:26.327387 Check phy result
562 05:27:26.328094 INFO : End of initialization
563 05:27:26.354771 INFO : End of 2D read delay Voltage center optimization
564 05:27:26.379056 INFO : End of 2D read delay Voltage center optimization
565 05:27:26.435613 INFO : End of 2D write delay Voltage center optimization
566 05:27:26.489569 INFO : End of 2D write delay Voltage center optimization
567 05:27:26.495334 INFO : Training has run successfully!
568 05:27:26.495871
569 05:27:26.496422 channel==0
570 05:27:26.500688 RxClkDly_Margin_A0==78 ps 8
571 05:27:26.501234 TxDqDly_Margin_A0==98 ps 10
572 05:27:26.506302 RxClkDly_Margin_A1==69 ps 7
573 05:27:26.506836 TxDqDly_Margin_A1==98 ps 10
574 05:27:26.507323 TrainedVREFDQ_A0==74
575 05:27:26.511854 TrainedVREFDQ_A1==74
576 05:27:26.512394 VrefDac_Margin_A0==24
577 05:27:26.512823 DeviceVref_Margin_A0==40
578 05:27:26.517451 VrefDac_Margin_A1==23
579 05:27:26.517946 DeviceVref_Margin_A1==40
580 05:27:26.518354
581 05:27:26.518756
582 05:27:26.523156 channel==1
583 05:27:26.523662 RxClkDly_Margin_A0==78 ps 8
584 05:27:26.524176 TxDqDly_Margin_A0==98 ps 10
585 05:27:26.528649 RxClkDly_Margin_A1==78 ps 8
586 05:27:26.529145 TxDqDly_Margin_A1==88 ps 9
587 05:27:26.534231 TrainedVREFDQ_A0==75
588 05:27:26.534743 TrainedVREFDQ_A1==78
589 05:27:26.535172 VrefDac_Margin_A0==22
590 05:27:26.539890 DeviceVref_Margin_A0==39
591 05:27:26.540447 VrefDac_Margin_A1==22
592 05:27:26.545460 DeviceVref_Margin_A1==36
593 05:27:26.545967
594 05:27:26.546384 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 05:27:26.546793
596 05:27:26.579214 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
597 05:27:26.579812 2D training succeed
598 05:27:26.584837 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 05:27:26.590269 auto size-- 65535DDR cs0 size: 2048MB
600 05:27:26.590785 DDR cs1 size: 2048MB
601 05:27:26.595897 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 05:27:26.596454 cs0 DataBus test pass
603 05:27:26.601470 cs1 DataBus test pass
604 05:27:26.601997 cs0 AddrBus test pass
605 05:27:26.602424 cs1 AddrBus test pass
606 05:27:26.602826
607 05:27:26.607321 100bdlr_step_size ps== 471
608 05:27:26.607874 result report
609 05:27:26.612655 boot times 0Enable ddr reg access
610 05:27:26.617900 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 05:27:26.631749 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 05:27:27.291807 bl2z: ptr: 05129330, size: 00001e40
613 05:27:27.301083 0.0;M3 CHK:0;cm4_sp_mode 0
614 05:27:27.301615 MVN_1=0x00000000
615 05:27:27.302040 MVN_2=0x00000000
616 05:27:27.312599 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 05:27:27.313111 OPS=0x04
618 05:27:27.313536 ring efuse init
619 05:27:27.318433 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 05:27:27.318981 [0.017354 Inits done]
621 05:27:27.319461 secure task start!
622 05:27:27.325508 high task start!
623 05:27:27.326060 low task start!
624 05:27:27.326502 run into bl31
625 05:27:27.334224 NOTICE: BL31: v1.3(release):4fc40b1
626 05:27:27.341933 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 05:27:27.342431 NOTICE: BL31: G12A normal boot!
628 05:27:27.357487 NOTICE: BL31: BL33 decompress pass
629 05:27:27.364337 ERROR: Error initializing runtime service opteed_fast
630 05:27:28.577746 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 05:27:28.578383 bl2_stage_init 0x01
632 05:27:28.578831 bl2_stage_init 0x81
633 05:27:28.583325 hw id: 0x0000 - pwm id 0x01
634 05:27:28.583807 bl2_stage_init 0xc1
635 05:27:28.588853 bl2_stage_init 0x02
636 05:27:28.589314
637 05:27:28.589728 L0:00000000
638 05:27:28.590126 L1:00000703
639 05:27:28.590519 L2:00008067
640 05:27:28.590912 L3:15000000
641 05:27:28.594443 S1:00000000
642 05:27:28.594893 B2:20282000
643 05:27:28.595298 B1:a0f83180
644 05:27:28.595692
645 05:27:28.596170 TE: 72025
646 05:27:28.596573
647 05:27:28.600097 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 05:27:28.600551
649 05:27:28.605676 Board ID = 1
650 05:27:28.606128 Set cpu clk to 24M
651 05:27:28.606533 Set clk81 to 24M
652 05:27:28.611290 Use GP1_pll as DSU clk.
653 05:27:28.611741 DSU clk: 1200 Mhz
654 05:27:28.612178 CPU clk: 1200 MHz
655 05:27:28.616863 Set clk81 to 166.6M
656 05:27:28.622548 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 05:27:28.623036 board id: 1
658 05:27:28.629737 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 05:27:28.640356 fw parse done
660 05:27:28.646389 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 05:27:28.688813 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 05:27:28.699877 PIEI prepare done
663 05:27:28.700409 fastboot data load
664 05:27:28.700828 fastboot data verify
665 05:27:28.705471 verify result: 266
666 05:27:28.711009 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 05:27:28.711477 LPDDR4 probe
668 05:27:28.711884 ddr clk to 1584MHz
669 05:27:28.718957 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 05:27:28.756273
671 05:27:28.756721 dmc_version 0001
672 05:27:28.763023 Check phy result
673 05:27:28.768877 INFO : End of CA training
674 05:27:28.769230 INFO : End of initialization
675 05:27:28.774360 INFO : Training has run successfully!
676 05:27:28.774688 Check phy result
677 05:27:28.779915 INFO : End of initialization
678 05:27:28.780232 INFO : End of read enable training
679 05:27:28.783215 INFO : End of fine write leveling
680 05:27:28.788786 INFO : End of Write leveling coarse delay
681 05:27:28.794465 INFO : Training has run successfully!
682 05:27:28.794789 Check phy result
683 05:27:28.795095 INFO : End of initialization
684 05:27:28.800157 INFO : End of read dq deskew training
685 05:27:28.803474 INFO : End of MPR read delay center optimization
686 05:27:28.809118 INFO : End of write delay center optimization
687 05:27:28.814539 INFO : End of read delay center optimization
688 05:27:28.814886 INFO : End of max read latency training
689 05:27:28.820250 INFO : Training has run successfully!
690 05:27:28.820598 1D training succeed
691 05:27:28.828556 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 05:27:28.876141 Check phy result
693 05:27:28.876750 INFO : End of initialization
694 05:27:28.898588 INFO : End of 2D read delay Voltage center optimization
695 05:27:28.917836 INFO : End of 2D read delay Voltage center optimization
696 05:27:28.969523 INFO : End of 2D write delay Voltage center optimization
697 05:27:29.018738 INFO : End of 2D write delay Voltage center optimization
698 05:27:29.024218 INFO : Training has run successfully!
699 05:27:29.024990
700 05:27:29.025611 channel==0
701 05:27:29.029918 RxClkDly_Margin_A0==69 ps 7
702 05:27:29.030698 TxDqDly_Margin_A0==98 ps 10
703 05:27:29.035570 RxClkDly_Margin_A1==69 ps 7
704 05:27:29.036446 TxDqDly_Margin_A1==98 ps 10
705 05:27:29.037069 TrainedVREFDQ_A0==76
706 05:27:29.041023 TrainedVREFDQ_A1==74
707 05:27:29.041643 VrefDac_Margin_A0==23
708 05:27:29.042123 DeviceVref_Margin_A0==38
709 05:27:29.046610 VrefDac_Margin_A1==22
710 05:27:29.047173 DeviceVref_Margin_A1==40
711 05:27:29.047585
712 05:27:29.048053
713 05:27:29.052166 channel==1
714 05:27:29.052661 RxClkDly_Margin_A0==88 ps 9
715 05:27:29.053064 TxDqDly_Margin_A0==98 ps 10
716 05:27:29.057708 RxClkDly_Margin_A1==78 ps 8
717 05:27:29.058193 TxDqDly_Margin_A1==88 ps 9
718 05:27:29.063398 TrainedVREFDQ_A0==75
719 05:27:29.063894 TrainedVREFDQ_A1==77
720 05:27:29.064366 VrefDac_Margin_A0==22
721 05:27:29.068963 DeviceVref_Margin_A0==39
722 05:27:29.069468 VrefDac_Margin_A1==22
723 05:27:29.074550 DeviceVref_Margin_A1==37
724 05:27:29.075058
725 05:27:29.075475 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 05:27:29.075882
727 05:27:29.108117 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
728 05:27:29.108687 2D training succeed
729 05:27:29.113745 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 05:27:29.119299 auto size-- 65535DDR cs0 size: 2048MB
731 05:27:29.119793 DDR cs1 size: 2048MB
732 05:27:29.124941 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 05:27:29.125422 cs0 DataBus test pass
734 05:27:29.130560 cs1 DataBus test pass
735 05:27:29.131042 cs0 AddrBus test pass
736 05:27:29.131453 cs1 AddrBus test pass
737 05:27:29.131850
738 05:27:29.136141 100bdlr_step_size ps== 478
739 05:27:29.136626 result report
740 05:27:29.141699 boot times 0Enable ddr reg access
741 05:27:29.147007 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 05:27:29.160791 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 05:27:29.815745 bl2z: ptr: 05129330, size: 00001e40
744 05:27:29.821698 0.0;M3 CHK:0;cm4_sp_mode 0
745 05:27:29.822058 MVN_1=0x00000000
746 05:27:29.822287 MVN_2=0x00000000
747 05:27:29.833125 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 05:27:29.833729 OPS=0x04
749 05:27:29.834179 ring efuse init
750 05:27:29.838783 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 05:27:29.839375 [0.017319 Inits done]
752 05:27:29.839839 secure task start!
753 05:27:29.845966 high task start!
754 05:27:29.846537 low task start!
755 05:27:29.846965 run into bl31
756 05:27:29.854548 NOTICE: BL31: v1.3(release):4fc40b1
757 05:27:29.862396 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 05:27:29.863101 NOTICE: BL31: G12A normal boot!
759 05:27:29.877935 NOTICE: BL31: BL33 decompress pass
760 05:27:29.883667 ERROR: Error initializing runtime service opteed_fast
761 05:27:30.678965
762 05:27:30.679617
763 05:27:30.684321 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 05:27:30.684839
765 05:27:30.687836 Model: Libre Computer AML-S905D3-CC Solitude
766 05:27:30.834881 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 05:27:30.850224 DRAM: 2 GiB (effective 3.8 GiB)
768 05:27:30.951240 Core: 406 devices, 33 uclasses, devicetree: separate
769 05:27:30.957025 WDT: Not starting watchdog@f0d0
770 05:27:30.982139 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 05:27:30.994320 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 05:27:30.999304 ** Bad device specification mmc 0 **
773 05:27:31.009358 Card did not respond to voltage select! : -110
774 05:27:31.017010 ** Bad device specification mmc 0 **
775 05:27:31.017464 Couldn't find partition mmc 0
776 05:27:31.025332 Card did not respond to voltage select! : -110
777 05:27:31.031012 ** Bad device specification mmc 0 **
778 05:27:31.031644 Couldn't find partition mmc 0
779 05:27:31.036029 Error: could not access storage.
780 05:27:31.332526 Net: eth0: ethernet@ff3f0000
781 05:27:31.333199 starting USB...
782 05:27:31.577136 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 05:27:31.577827 Starting the controller
784 05:27:31.584083 USB XHCI 1.10
785 05:27:33.138855 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 05:27:33.146869 scanning usb for storage devices... 0 Storage Device(s) found
788 05:27:33.198039 Hit any key to stop autoboot: 1
789 05:27:33.198697 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
790 05:27:33.199076 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
791 05:27:33.199370 Setting prompt string to ['=>']
792 05:27:33.199649 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
793 05:27:33.212581 0
794 05:27:33.213255 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 05:27:33.314161 => setenv autoload no
797 05:27:33.314755 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
798 05:27:33.318979 setenv autoload no
800 05:27:33.420065 => setenv initrd_high 0xffffffff
801 05:27:33.420654 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 05:27:33.425016 setenv initrd_high 0xffffffff
804 05:27:33.526328 => setenv fdt_high 0xffffffff
805 05:27:33.526889 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 05:27:33.531252 setenv fdt_high 0xffffffff
808 05:27:33.632555 => dhcp
809 05:27:33.633237 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 05:27:33.637279 dhcp
811 05:27:34.192922 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
812 05:27:34.193430 Speed: 1000, full duplex
813 05:27:34.193725 BOOTP broadcast 1
814 05:27:34.441046 BOOTP broadcast 2
815 05:27:34.460733 DHCP client bound to address 192.168.6.21 (267 ms)
817 05:27:34.562759 => setenv serverip 192.168.6.2
818 05:27:34.564047 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
819 05:27:34.568474 setenv serverip 192.168.6.2
821 05:27:34.670342 => tftpboot 0x01080000 927230/tftp-deploy-sxt3bra_/kernel/uImage
822 05:27:34.671326 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
823 05:27:34.678182 tftpboot 0x01080000 927230/tftp-deploy-sxt3bra_/kernel/uImage
824 05:27:34.678711 Speed: 1000, full duplex
825 05:27:34.679135 Using ethernet@ff3f0000 device
826 05:27:34.683550 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
827 05:27:34.689372 Filename '927230/tftp-deploy-sxt3bra_/kernel/uImage'.
828 05:27:34.693180 Load address: 0x1080000
829 05:27:37.553266 Loading: *################################################## 43.6 MiB
830 05:27:37.554237 15.2 MiB/s
831 05:27:37.554789 done
832 05:27:37.556761 Bytes transferred = 45713984 (2b98a40 hex)
834 05:27:37.658770 => tftpboot 0x08000000 927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot
835 05:27:37.659958 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
836 05:27:37.666842 tftpboot 0x08000000 927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot
837 05:27:37.667517 Speed: 1000, full duplex
838 05:27:37.668115 Using ethernet@ff3f0000 device
839 05:27:37.672334 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
840 05:27:37.682171 Filename '927230/tftp-deploy-sxt3bra_/ramdisk/ramdisk.cpio.gz.uboot'.
841 05:27:37.682817 Load address: 0x8000000
842 05:27:39.207834 Loading: *################################################# UDP wrong checksum 00000005 00003fef
843 05:27:42.632734 UDP wrong checksum 000000ff 00005086
844 05:27:42.642137 UDP wrong checksum 000000ff 0000e578
845 05:27:44.208960 T UDP wrong checksum 00000005 00003fef
846 05:27:54.210981 T T UDP wrong checksum 00000005 00003fef
847 05:28:14.212366 T T T UDP wrong checksum 00000005 00003fef
848 05:28:26.906689 T T T UDP wrong checksum 000000ff 0000dbc5
849 05:28:26.952400 UDP wrong checksum 000000ff 00006cb8
850 05:28:34.218556 T
851 05:28:34.219228 Retry count exceeded; starting again
853 05:28:34.220782 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
856 05:28:34.222850 end: 2.4 uboot-commands (duration 00:01:20) [common]
858 05:28:34.224462 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
860 05:28:34.225610 end: 2 uboot-action (duration 00:01:20) [common]
862 05:28:34.227307 Cleaning after the job
863 05:28:34.227922 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/ramdisk
864 05:28:34.229474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/kernel
865 05:28:34.258933 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/dtb
866 05:28:34.260340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/nfsrootfs
867 05:28:34.335374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927230/tftp-deploy-sxt3bra_/modules
868 05:28:34.343443 start: 4.1 power-off (timeout 00:00:30) [common]
869 05:28:34.344102 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
870 05:28:34.379515 >> OK - accepted request
871 05:28:34.381602 Returned 0 in 0 seconds
872 05:28:34.482313 end: 4.1 power-off (duration 00:00:00) [common]
874 05:28:34.483223 start: 4.2 read-feedback (timeout 00:10:00) [common]
875 05:28:34.483861 Listened to connection for namespace 'common' for up to 1s
876 05:28:35.484830 Finalising connection for namespace 'common'
877 05:28:35.485324 Disconnecting from shell: Finalise
878 05:28:35.485611 =>
879 05:28:35.586232 end: 4.2 read-feedback (duration 00:00:01) [common]
880 05:28:35.586614 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927230
881 05:28:38.049429 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927230
882 05:28:38.050047 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.