Boot log: beaglebone-black

    1 21:23:28.593273  lava-dispatcher, installed at version: 2023.08
    2 21:23:28.593650  start: 0 validate
    3 21:23:28.593878  Start time: 2024-11-03 21:23:28.593863+00:00 (UTC)
    4 21:23:28.594147  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 21:23:28.949891  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
    6 21:23:29.112422  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 21:23:29.275488  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 21:23:29.437958  Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
    9 21:23:29.608343  validate duration: 1.01
   11 21:23:29.609464  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 21:23:29.609944  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 21:23:29.610388  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 21:23:29.611164  Not decompressing ramdisk as can be used compressed.
   15 21:23:29.611596  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 21:23:29.611932  saving as /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/ramdisk/initrd.cpio.gz
   17 21:23:29.612279  total size: 4775763 (4 MB)
   18 21:23:29.936746  progress   0 % (0 MB)
   19 21:23:30.418758  progress   5 % (0 MB)
   20 21:23:30.579479  progress  10 % (0 MB)
   21 21:23:30.771517  progress  15 % (0 MB)
   22 21:23:30.941981  progress  20 % (0 MB)
   23 21:23:30.948004  progress  25 % (1 MB)
   24 21:23:30.953971  progress  30 % (1 MB)
   25 21:23:30.960724  progress  35 % (1 MB)
   26 21:23:31.065856  progress  40 % (1 MB)
   27 21:23:31.091198  progress  45 % (2 MB)
   28 21:23:31.232628  progress  50 % (2 MB)
   29 21:23:31.381010  progress  55 % (2 MB)
   30 21:23:31.417924  progress  60 % (2 MB)
   31 21:23:31.562464  progress  65 % (2 MB)
   32 21:23:31.708435  progress  70 % (3 MB)
   33 21:23:31.742278  progress  75 % (3 MB)
   34 21:23:31.886029  progress  80 % (3 MB)
   35 21:23:32.026635  progress  85 % (3 MB)
   36 21:23:32.064246  progress  90 % (4 MB)
   37 21:23:32.207394  progress  95 % (4 MB)
   38 21:23:32.344692  progress 100 % (4 MB)
   39 21:23:32.345748  4 MB downloaded in 2.73 s (1.67 MB/s)
   40 21:23:32.346443  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 21:23:32.347573  end: 1.1 download-retry (duration 00:00:03) [common]
   43 21:23:32.347984  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 21:23:32.348381  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 21:23:32.348989  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/kernel/zImage
   46 21:23:32.349310  saving as /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/kernel/zImage
   47 21:23:32.349610  total size: 11444736 (10 MB)
   48 21:23:32.349910  No compression specified
   49 21:23:32.515254  progress   0 % (0 MB)
   50 21:23:32.706179  progress   5 % (0 MB)
   51 21:23:33.021722  progress  10 % (1 MB)
   52 21:23:33.473446  progress  15 % (1 MB)
   53 21:23:33.706346  progress  20 % (2 MB)
   54 21:23:34.114733  progress  25 % (2 MB)
   55 21:23:34.309441  progress  30 % (3 MB)
   56 21:23:34.630042  progress  35 % (3 MB)
   57 21:23:34.945880  progress  40 % (4 MB)
   58 21:23:35.263385  progress  45 % (4 MB)
   59 21:23:35.574769  progress  50 % (5 MB)
   60 21:23:35.891161  progress  55 % (6 MB)
   61 21:23:36.198556  progress  60 % (6 MB)
   62 21:23:36.464373  progress  65 % (7 MB)
   63 21:23:36.710614  progress  70 % (7 MB)
   64 21:23:37.022253  progress  75 % (8 MB)
   65 21:23:37.338475  progress  80 % (8 MB)
   66 21:23:37.648756  progress  85 % (9 MB)
   67 21:23:37.960399  progress  90 % (9 MB)
   68 21:23:38.157599  progress  95 % (10 MB)
   69 21:23:38.473326  progress 100 % (10 MB)
   70 21:23:38.474092  10 MB downloaded in 6.12 s (1.78 MB/s)
   71 21:23:38.474926  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 21:23:38.476123  end: 1.2 download-retry (duration 00:00:06) [common]
   74 21:23:38.476541  start: 1.3 download-retry (timeout 00:09:51) [common]
   75 21:23:38.477001  start: 1.3.1 http-download (timeout 00:09:51) [common]
   76 21:23:38.477628  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
   77 21:23:38.477978  saving as /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/dtb/am335x-boneblack.dtb
   78 21:23:38.478308  total size: 70568 (0 MB)
   79 21:23:38.478607  No compression specified
   80 21:23:38.644673  progress  46 % (0 MB)
   81 21:23:38.691224  progress  92 % (0 MB)
   82 21:23:38.692581  progress 100 % (0 MB)
   83 21:23:38.693144  0 MB downloaded in 0.21 s (0.31 MB/s)
   84 21:23:38.693700  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 21:23:38.694750  end: 1.3 download-retry (duration 00:00:00) [common]
   87 21:23:38.695137  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 21:23:38.695570  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 21:23:38.696108  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 21:23:38.696416  saving as /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/nfsrootfs/full.rootfs.tar
   91 21:23:38.696707  total size: 117747780 (112 MB)
   92 21:23:38.697040  Using unxz to decompress xz
   93 21:23:38.863050  progress   0 % (0 MB)
   94 21:23:42.256431  progress   5 % (5 MB)
   95 21:23:45.328136  progress  10 % (11 MB)
   96 21:23:48.273833  progress  15 % (16 MB)
   97 21:23:50.768107  progress  20 % (22 MB)
   98 21:23:52.609780  progress  25 % (28 MB)
   99 21:23:54.030078  progress  30 % (33 MB)
  100 21:23:55.103938  progress  35 % (39 MB)
  101 21:23:56.017381  progress  40 % (44 MB)
  102 21:23:56.961575  progress  45 % (50 MB)
  103 21:23:57.942942  progress  50 % (56 MB)
  104 21:23:58.851676  progress  55 % (61 MB)
  105 21:24:00.022159  progress  60 % (67 MB)
  106 21:24:01.109446  progress  65 % (73 MB)
  107 21:24:02.174981  progress  70 % (78 MB)
  108 21:24:03.245744  progress  75 % (84 MB)
  109 21:24:04.470329  progress  80 % (89 MB)
  110 21:24:06.253369  progress  85 % (95 MB)
  111 21:24:07.986494  progress  90 % (101 MB)
  112 21:24:09.926231  progress  95 % (106 MB)
  113 21:24:11.859838  progress 100 % (112 MB)
  114 21:24:11.868294  112 MB downloaded in 33.17 s (3.39 MB/s)
  115 21:24:11.868887  end: 1.4.1 http-download (duration 00:00:33) [common]
  117 21:24:11.869837  end: 1.4 download-retry (duration 00:00:33) [common]
  118 21:24:11.870237  start: 1.5 download-retry (timeout 00:09:18) [common]
  119 21:24:11.870629  start: 1.5.1 http-download (timeout 00:09:18) [common]
  120 21:24:11.871254  downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
  121 21:24:11.871567  saving as /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/modules/modules.tar
  122 21:24:11.871859  total size: 6606656 (6 MB)
  123 21:24:11.872158  Using unxz to decompress xz
  124 21:24:12.038035  progress   0 % (0 MB)
  125 21:24:12.225520  progress   5 % (0 MB)
  126 21:24:12.267280  progress  10 % (0 MB)
  127 21:24:12.371986  progress  15 % (0 MB)
  128 21:24:12.528321  progress  20 % (1 MB)
  129 21:24:12.681656  progress  25 % (1 MB)
  130 21:24:12.721418  progress  30 % (1 MB)
  131 21:24:12.877313  progress  35 % (2 MB)
  132 21:24:13.026797  progress  40 % (2 MB)
  133 21:24:13.178647  progress  45 % (2 MB)
  134 21:24:13.332072  progress  50 % (3 MB)
  135 21:24:13.479743  progress  55 % (3 MB)
  136 21:24:13.528927  progress  60 % (3 MB)
  137 21:24:13.681172  progress  65 % (4 MB)
  138 21:24:13.825764  progress  70 % (4 MB)
  139 21:24:13.975677  progress  75 % (4 MB)
  140 21:24:14.122158  progress  80 % (5 MB)
  141 21:24:14.172155  progress  85 % (5 MB)
  142 21:24:14.316767  progress  90 % (5 MB)
  143 21:24:14.460565  progress  95 % (6 MB)
  144 21:24:14.605959  progress 100 % (6 MB)
  145 21:24:14.609612  6 MB downloaded in 2.74 s (2.30 MB/s)
  146 21:24:14.610246  end: 1.5.1 http-download (duration 00:00:03) [common]
  148 21:24:14.611343  end: 1.5 download-retry (duration 00:00:03) [common]
  149 21:24:14.611750  start: 1.6 prepare-tftp-overlay (timeout 00:09:15) [common]
  150 21:24:14.612151  start: 1.6.1 extract-nfsrootfs (timeout 00:09:15) [common]
  151 21:24:21.854074  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a
  152 21:24:21.854402  end: 1.6.1 extract-nfsrootfs (duration 00:00:07) [common]
  153 21:24:21.854554  start: 1.6.2 lava-overlay (timeout 00:09:08) [common]
  154 21:24:21.854842  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw
  155 21:24:21.855090  makedir: /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin
  156 21:24:21.855261  makedir: /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/tests
  157 21:24:21.855427  makedir: /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/results
  158 21:24:21.855588  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-add-keys
  159 21:24:21.855829  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-add-sources
  160 21:24:21.856050  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-background-process-start
  161 21:24:21.856273  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-background-process-stop
  162 21:24:21.856511  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-common-functions
  163 21:24:21.856735  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-echo-ipv4
  164 21:24:21.857094  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-install-packages
  165 21:24:21.857340  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-installed-packages
  166 21:24:21.857555  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-os-build
  167 21:24:21.857769  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-probe-channel
  168 21:24:21.857980  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-probe-ip
  169 21:24:21.858197  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-target-ip
  170 21:24:21.858411  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-target-mac
  171 21:24:21.858624  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-target-storage
  172 21:24:21.858844  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-case
  173 21:24:21.859060  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-event
  174 21:24:21.859273  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-feedback
  175 21:24:21.859485  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-raise
  176 21:24:21.859700  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-reference
  177 21:24:21.859917  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-runner
  178 21:24:21.860127  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-set
  179 21:24:21.860337  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-test-shell
  180 21:24:21.860562  Updating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-add-keys (debian)
  181 21:24:21.894965  Updating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-add-sources (debian)
  182 21:24:21.895268  Updating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-install-packages (debian)
  183 21:24:21.895554  Updating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-installed-packages (debian)
  184 21:24:21.895820  Updating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/bin/lava-os-build (debian)
  185 21:24:21.896033  Creating /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/environment
  186 21:24:21.896201  LAVA metadata
  187 21:24:21.896318  - LAVA_JOB_ID=1215758
  188 21:24:21.896430  - LAVA_DISPATCHER_IP=172.16.3.3
  189 21:24:21.896601  start: 1.6.2.1 ssh-authorize (timeout 00:09:08) [common]
  190 21:24:21.897092  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 21:24:21.897259  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:08) [common]
  192 21:24:21.897366  skipped lava-vland-overlay
  193 21:24:21.897495  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 21:24:21.897629  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:08) [common]
  195 21:24:21.897740  skipped lava-multinode-overlay
  196 21:24:21.897868  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 21:24:21.897998  start: 1.6.2.4 test-definition (timeout 00:09:08) [common]
  198 21:24:21.898114  Loading test definitions
  199 21:24:21.898255  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:08) [common]
  200 21:24:21.898369  Using /lava-1215758 at stage 0
  201 21:24:21.898917  uuid=1215758_1.6.2.4.1 testdef=None
  202 21:24:21.899083  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 21:24:21.899221  start: 1.6.2.4.2 test-overlay (timeout 00:09:08) [common]
  204 21:24:21.899996  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 21:24:21.900355  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:08) [common]
  207 21:24:21.901340  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 21:24:21.901744  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:08) [common]
  210 21:24:21.920336  runner path: /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/0/tests/0_timesync-off test_uuid 1215758_1.6.2.4.1
  211 21:24:21.920622  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 21:24:21.921035  start: 1.6.2.4.5 git-repo-action (timeout 00:09:08) [common]
  214 21:24:21.921167  Using /lava-1215758 at stage 0
  215 21:24:21.921334  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 21:24:21.921453  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/0/tests/1_kselftest-dt'
  217 21:24:27.330210  Running '/usr/bin/git checkout kernelci.org
  218 21:24:27.630626  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 21:24:27.631927  uuid=1215758_1.6.2.4.5 testdef=None
  220 21:24:27.632269  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 21:24:27.632953  start: 1.6.2.4.6 test-overlay (timeout 00:09:02) [common]
  223 21:24:27.635313  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 21:24:27.636076  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:02) [common]
  226 21:24:27.639305  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 21:24:27.639928  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:02) [common]
  229 21:24:27.642971  runner path: /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/0/tests/1_kselftest-dt test_uuid 1215758_1.6.2.4.5
  230 21:24:27.643243  BOARD='beaglebone-black'
  231 21:24:27.643465  BRANCH='mainline'
  232 21:24:27.643674  SKIPFILE='/dev/null'
  233 21:24:27.643882  SKIP_INSTALL='True'
  234 21:24:27.644082  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
  235 21:24:27.644289  TST_CASENAME=''
  236 21:24:27.644490  TST_CMDFILES='dt'
  237 21:24:27.644932  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 21:24:27.645539  Creating lava-test-runner.conf files
  240 21:24:27.645747  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1215758/lava-overlay-8swjkncw/lava-1215758/0 for stage 0
  241 21:24:27.646067  - 0_timesync-off
  242 21:24:27.646287  - 1_kselftest-dt
  243 21:24:27.646615  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 21:24:27.646894  start: 1.6.2.5 compress-overlay (timeout 00:09:02) [common]
  245 21:24:37.108529  end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
  246 21:24:37.108771  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:53) [common]
  247 21:24:37.108956  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 21:24:37.109118  end: 1.6.2 lava-overlay (duration 00:00:15) [common]
  249 21:24:37.109261  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:53) [common]
  250 21:24:37.248724  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 21:24:37.248986  start: 1.6.4 extract-modules (timeout 00:08:52) [common]
  252 21:24:37.249130  extracting modules file /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a
  253 21:24:37.632135  extracting modules file /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1215758/extract-overlay-ramdisk-o19t26u2/ramdisk
  254 21:24:38.017583  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 21:24:38.017848  start: 1.6.5 apply-overlay-tftp (timeout 00:08:52) [common]
  256 21:24:38.017976  [common] Applying overlay to NFS
  257 21:24:38.018082  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1215758/compress-overlay-q38vtabs/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a
  258 21:24:39.345598  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  259 21:24:39.345856  start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
  260 21:24:39.345999  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
  261 21:24:39.346143  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 21:24:39.346275  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 21:24:39.346411  start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
  264 21:24:39.346541  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 21:24:39.346673  start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
  266 21:24:39.346786  Building ramdisk /var/lib/lava/dispatcher/tmp/1215758/extract-overlay-ramdisk-o19t26u2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1215758/extract-overlay-ramdisk-o19t26u2/ramdisk
  267 21:24:39.635580  >> 74900 blocks

  268 21:24:41.703161  Adding RAMdisk u-boot header.
  269 21:24:41.703568  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1215758/extract-overlay-ramdisk-o19t26u2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1215758/extract-overlay-ramdisk-o19t26u2/ramdisk.cpio.gz.uboot
  270 21:24:42.038065  output: Image Name:   
  271 21:24:42.038496  output: Created:      Sun Nov  3 21:24:41 2024
  272 21:24:42.038820  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 21:24:42.039125  output: Data Size:    14796057 Bytes = 14449.27 KiB = 14.11 MiB
  274 21:24:42.039421  output: Load Address: 00000000
  275 21:24:42.039709  output: Entry Point:  00000000
  276 21:24:42.039995  output: 
  277 21:24:42.040480  rename /var/lib/lava/dispatcher/tmp/1215758/extract-overlay-ramdisk-o19t26u2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot
  278 21:24:42.040951  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 21:24:42.041187  end: 1.6 prepare-tftp-overlay (duration 00:00:27) [common]
  280 21:24:42.041592  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
  281 21:24:42.041904  No LXC device requested
  282 21:24:42.042276  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 21:24:42.042665  start: 1.8 deploy-device-env (timeout 00:08:48) [common]
  284 21:24:42.043043  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 21:24:42.043343  Checking files for TFTP limit of 4294967296 bytes.
  286 21:24:42.045075  end: 1 tftp-deploy (duration 00:01:12) [common]
  287 21:24:42.045493  start: 2 uboot-action (timeout 00:05:00) [common]
  288 21:24:42.045893  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 21:24:42.046271  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 21:24:42.046658  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 21:24:42.047212  substitutions:
  292 21:24:42.047523  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 21:24:42.047821  - {DTB_ADDR}: 0x88000000
  294 21:24:42.048111  - {DTB}: 1215758/tftp-deploy-2udq1ia5/dtb/am335x-boneblack.dtb
  295 21:24:42.048400  - {INITRD}: 1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot
  296 21:24:42.048689  - {KERNEL_ADDR}: 0x82000000
  297 21:24:42.048931  - {KERNEL}: 1215758/tftp-deploy-2udq1ia5/kernel/zImage
  298 21:24:42.049104  - {LAVA_MAC}: None
  299 21:24:42.049402  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a
  300 21:24:42.049687  - {NFS_SERVER_IP}: 172.16.3.3
  301 21:24:42.049968  - {PRESEED_CONFIG}: None
  302 21:24:42.050244  - {PRESEED_LOCAL}: None
  303 21:24:42.050522  - {RAMDISK_ADDR}: 0x83000000
  304 21:24:42.050798  - {RAMDISK}: 1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot
  305 21:24:42.051076  - {ROOT_PART}: None
  306 21:24:42.051349  - {ROOT}: None
  307 21:24:42.051621  - {SERVER_IP}: 172.16.3.3
  308 21:24:42.051892  - {TEE_ADDR}: 0x83000000
  309 21:24:42.052164  - {TEE}: None
  310 21:24:42.052435  Parsed boot commands:
  311 21:24:42.052701  - setenv autoload no
  312 21:24:42.052907  - setenv initrd_high 0xffffffff
  313 21:24:42.053024  - setenv fdt_high 0xffffffff
  314 21:24:42.053296  - dhcp
  315 21:24:42.053567  - setenv serverip 172.16.3.3
  316 21:24:42.053838  - tftp 0x82000000 1215758/tftp-deploy-2udq1ia5/kernel/zImage
  317 21:24:42.054112  - tftp 0x83000000 1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot
  318 21:24:42.054389  - setenv initrd_size ${filesize}
  319 21:24:42.054660  - tftp 0x88000000 1215758/tftp-deploy-2udq1ia5/dtb/am335x-boneblack.dtb
  320 21:24:42.054935  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 21:24:42.055220  - bootz 0x82000000 0x83000000 0x88000000
  322 21:24:42.055579  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 21:24:42.056579  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 21:24:42.056880  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 21:24:42.064016  Setting prompt string to ['lava-test: # ']
  327 21:24:42.064492  end: 2.3 connect-device (duration 00:00:00) [common]
  328 21:24:42.064699  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 21:24:42.064899  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 21:24:42.065079  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 21:24:42.065371  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 21:24:42.377990  >> OFF

  333 21:24:57.666767  >> ON

  334 21:24:57.667720  Returned 0 in 15 seconds
  335 21:24:57.768685  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 21:24:57.769861  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 21:24:57.770303  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 21:24:57.770699  Setting prompt string to ['Hit any key to stop autoboot']
  340 21:24:57.771047  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 21:24:57.771995  Trying 192.168.1.205...
  342 21:24:57.772309  Connected to ts5.
  343 21:24:57.772597  Escape character is '^]'.
  344 21:24:57.772906  
  345 21:24:57.773191  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [] (Debian GNU/Linux)
  346 21:24:57.773483  
  347 21:24:58.261940  
  348 21:24:58.269812  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 21:24:58.270201  Trying to boot from MMC2
  350 21:24:58.783947  
  351 21:24:58.784348  
  352 21:24:58.790074  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 21:24:58.790471  
  354 21:24:58.790800  CPU  : AM335X-GP rev 2.1
  355 21:24:58.796752  Model: TI AM335x BeagleBone Black
  356 21:24:58.797172  DRAM:  512 MiB
  357 21:24:58.877686  WDT:   Started with servicing (60s timeout)
  358 21:24:59.282536  NAND:  0 MiB
  359 21:24:59.293289  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 21:24:59.325681  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 21:24:59.355931  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 21:24:59.413548  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 21:24:59.414047  start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
  364 21:24:59.414429  Setting prompt string to ['=> ']
  365 21:24:59.414793  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:43)
  366 21:24:59.424402  Hit any key to stop autoboot:  2   0 
  367 21:24:59.425225  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 21:24:59.425610  Sending with 10 millisecond of delay
  370 21:25:00.562231  => setenv autoload no
  371 21:25:00.572769  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 21:25:00.574697  setenv autoload no
  373 21:25:00.575117  Sending with 10 millisecond of delay
  375 21:25:02.374507  => setenv initrd_high 0xffffffff
  376 21:25:02.385243  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:40)
  377 21:25:02.385915  setenv initrd_high 0xffffffff
  378 21:25:02.386490  Sending with 10 millisecond of delay
  380 21:25:04.005655  => setenv fdt_high 0xffffffff
  381 21:25:04.016262  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 21:25:04.016909  setenv fdt_high 0xffffffff
  383 21:25:04.017477  Sending with 10 millisecond of delay
  385 21:25:04.309538  => dhcp
  386 21:25:04.320089  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 21:25:04.321001  dhcp
  388 21:25:04.321339  link up on port 0, speed 100, full duplex
  389 21:25:04.321650  BOOTP broadcast 1
  390 21:25:04.367018  DHCP client bound to address 172.16.3.190 (39 ms)
  391 21:25:04.367638  Sending with 10 millisecond of delay
  393 21:25:05.987198  => setenv serverip 172.16.3.3
  394 21:25:05.997747  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 21:25:05.998376  setenv serverip 172.16.3.3
  396 21:25:05.998946  Sending with 10 millisecond of delay
  398 21:25:09.548539  => tftp 0x82000000 1215758/tftp-deploy-2udq1ia5/kernel/zImage
  399 21:25:09.559174  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 21:25:09.560093  tftp 0x82000000 1215758/tftp-deploy-2udq1ia5/kernel/zImage
  401 21:25:09.560429  link up on port 0, speed 100, full duplex
  402 21:25:09.566312  Using ethernet@4a100000 device
  403 21:25:09.571201  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  404 21:25:09.577814  Filename '1215758/tftp-deploy-2udq1ia5/kernel/zImage'.
  405 21:25:09.578024  Load address: 0x82000000
  406 21:25:12.433441  Loading: *##################################################  10.9 MiB
  407 21:25:12.433944  	 3.8 MiB/s
  408 21:25:12.434254  done
  409 21:25:12.438938  Bytes transferred = 11444736 (aea200 hex)
  410 21:25:12.439580  Sending with 10 millisecond of delay
  412 21:25:16.954009  => tftp 0x83000000 1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot
  413 21:25:16.964609  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 21:25:16.966400  tftp 0x83000000 1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot
  415 21:25:16.966786  link up on port 0, speed 100, full duplex
  416 21:25:16.970297  Using ethernet@4a100000 device
  417 21:25:16.976412  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  418 21:25:16.984458  Filename '1215758/tftp-deploy-2udq1ia5/ramdisk/ramdisk.cpio.gz.uboot'.
  419 21:25:16.984757  Load address: 0x83000000
  420 21:25:20.739817  Loading: *##################################################  14.1 MiB
  421 21:25:20.740273  	 3.8 MiB/s
  422 21:25:20.740588  done
  423 21:25:20.744093  Bytes transferred = 14796121 (e1c559 hex)
  424 21:25:20.744752  Sending with 10 millisecond of delay
  426 21:25:22.605368  => setenv initrd_size ${filesize}
  427 21:25:22.616049  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:19)
  428 21:25:22.616682  setenv initrd_size ${filesize}
  429 21:25:22.617284  Sending with 10 millisecond of delay
  431 21:25:26.830515  => tftp 0x88000000 1215758/tftp-deploy-2udq1ia5/dtb/am335x-boneblack.dtb
  432 21:25:26.841064  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
  433 21:25:26.842191  tftp 0x88000000 1215758/tftp-deploy-2udq1ia5/dtb/am335x-boneblack.dtb
  434 21:25:26.842527  link up on port 0, speed 100, full duplex
  435 21:25:26.847436  Using ethernet@4a100000 device
  436 21:25:26.852301  TFTP from server 172.16.3.3; our IP address is 172.16.3.190
  437 21:25:26.865601  Filename '1215758/tftp-deploy-2udq1ia5/dtb/am335x-boneblack.dtb'.
  438 21:25:26.865867  Load address: 0x88000000
  439 21:25:26.881919  Loading: *##################################################  68.9 KiB
  440 21:25:26.882311  	 3.2 MiB/s
  441 21:25:26.890176  done
  442 21:25:26.890559  Bytes transferred = 70568 (113a8 hex)
  443 21:25:26.891128  Sending with 10 millisecond of delay
  445 21:25:40.270089  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 21:25:40.280776  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:02)
  447 21:25:40.281431  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 21:25:40.282017  Sending with 10 millisecond of delay
  450 21:25:42.624962  => bootz 0x82000000 0x83000000 0x88000000
  451 21:25:42.635587  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 21:25:42.636034  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:03:59)
  453 21:25:42.636771  bootz 0x82000000 0x83000000 0x88000000
  454 21:25:42.637137  Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
  455 21:25:42.639866  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 21:25:42.644744     Image Name:   
  457 21:25:42.645155     Created:      2024-11-03  21:24:41 UTC
  458 21:25:42.653616     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 21:25:42.654007     Data Size:    14796057 Bytes = 14.1 MiB
  460 21:25:42.661751     Load Address: 00000000
  461 21:25:42.662140     Entry Point:  00000000
  462 21:25:42.830996     Verifying Checksum ... OK
  463 21:25:42.831383  ## Flattened Device Tree blob at 88000000
  464 21:25:42.837114     Booting using the fdt blob at 0x88000000
  465 21:25:42.841442     Using Device Tree in place at 88000000, end 880143a7
  466 21:25:42.854658  
  467 21:25:42.855044  Starting kernel ...
  468 21:25:42.855353  
  469 21:25:42.856052  end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
  470 21:25:42.856478  start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
  471 21:25:42.856851  Setting prompt string to ['Linux version [0-9]']
  472 21:25:42.857193  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 21:25:42.857542  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 21:25:43.697218  [    0.000000] Booting Linux on physical CPU 0x0
  475 21:25:43.703639  start: 2.4.4.1 login-action (timeout 00:03:58) [common]
  476 21:25:43.704051  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 21:25:43.704396  Setting prompt string to []
  478 21:25:43.704742  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 21:25:43.705110  Using line separator: #'\n'#
  480 21:25:43.705406  No login prompt set.
  481 21:25:43.705709  Parsing kernel messages
  482 21:25:43.705987  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 21:25:43.706511  [login-action] Waiting for messages, (timeout 00:03:58)
  484 21:25:43.716852  [    0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j360873-arm-gcc-12-multi-v7-defconfig-8gfmt) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sun Nov  3 20:41:51 UTC 2024
  485 21:25:43.729068  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 21:25:43.732677  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 21:25:43.737607  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 21:25:43.743867  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 21:25:43.749946  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 21:25:43.759962  [    0.000000] Memory policy: Data cache writeback
  491 21:25:43.760343  [    0.000000] efi: UEFI not found.
  492 21:25:43.765436  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 21:25:43.771822  [    0.000000] Zone ranges:
  494 21:25:43.777990  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 21:25:43.784140  [    0.000000]   Normal   empty
  496 21:25:43.784519  [    0.000000]   HighMem  empty
  497 21:25:43.786607  [    0.000000] Movable zone start for each node
  498 21:25:43.791647  [    0.000000] Early memory node ranges
  499 21:25:43.797890  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 21:25:43.805851  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 21:25:43.831393  [    0.000000] CPU: All CPU(s) started in SVC mode.
  502 21:25:43.841040  [    0.000000] AM335X ES2.1 (sgx neon)
  503 21:25:43.844630  [    0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
  504 21:25:43.871647  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  505 21:25:43.877754  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  506 21:25:43.882985  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  507 21:25:43.891504  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  508 21:25:43.899466  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  509 21:25:43.929058  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  510 21:25:43.935025  <6>[    0.000000] trace event string verifier disabled
  511 21:25:43.935417  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  512 21:25:43.942381  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  513 21:25:43.948652  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  514 21:25:43.958505  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  515 21:25:43.964188  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  516 21:25:43.980127  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  517 21:25:43.997881  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  518 21:25:44.003396  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  519 21:25:44.097390  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  520 21:25:44.105752  <6>[    0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  521 21:25:44.118141  <6>[    0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  522 21:25:44.126489  <6>[    0.019163] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  523 21:25:44.136134  <6>[    0.034065] Console: colour dummy device 80x30
  524 21:25:44.142627  Matched prompt #6: WARNING:
  525 21:25:44.143036  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  526 21:25:44.147259  <3>[    0.038962] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  527 21:25:44.150768  <3>[    0.046028] This ensures that you still see kernel messages. Please
  528 21:25:44.156542  <3>[    0.052750] update your kernel commandline.
  529 21:25:44.196508  <6>[    0.057362] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  530 21:25:44.200239  <6>[    0.096168] CPU: Testing write buffer coherency: ok
  531 21:25:44.203881  <6>[    0.101531] CPU0: Spectre v2: using BPIALL workaround
  532 21:25:44.209954  <6>[    0.106997] pid_max: default: 32768 minimum: 301
  533 21:25:44.220851  <6>[    0.112190] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  534 21:25:44.227095  <6>[    0.120011] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  535 21:25:44.233803  <6>[    0.129350] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  536 21:25:44.309877  <6>[    0.199542] Setting up static identity map for 0x80300000 - 0x803000ac
  537 21:25:44.315755  <6>[    0.209126] rcu: Hierarchical SRCU implementation.
  538 21:25:44.320246  <6>[    0.214407] rcu: 	Max phase no-delay instances is 1000.
  539 21:25:44.327884  <6>[    0.225480] EFI services will not be available.
  540 21:25:44.334125  <6>[    0.230845] smp: Bringing up secondary CPUs ...
  541 21:25:44.340141  <6>[    0.235814] smp: Brought up 1 node, 1 CPU
  542 21:25:44.347632  <6>[    0.240287] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  543 21:25:44.353749  <6>[    0.247007] CPU: All CPU(s) started in SVC mode.
  544 21:25:44.371419  <6>[    0.252208] Memory: 405992K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49056K reserved, 65536K cma-reserved, 0K highmem)
  545 21:25:44.371818  <6>[    0.268475] devtmpfs: initialized
  546 21:25:44.393638  <6>[    0.285528] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  547 21:25:44.404814  <6>[    0.294112] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  548 21:25:44.410591  <6>[    0.304553] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  549 21:25:44.422132  <6>[    0.316824] pinctrl core: initialized pinctrl subsystem
  550 21:25:44.430624  <6>[    0.327510] DMI not present or invalid.
  551 21:25:44.439156  <6>[    0.333351] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  552 21:25:44.448423  <6>[    0.342290] DMA: preallocated 256 KiB pool for atomic coherent allocations
  553 21:25:44.463845  <6>[    0.353719] thermal_sys: Registered thermal governor 'step_wise'
  554 21:25:44.464231  <6>[    0.353889] cpuidle: using governor menu
  555 21:25:44.491378  <6>[    0.389543] No ATAGs?
  556 21:25:44.497058  <6>[    0.392181] hw-breakpoint: debug architecture 0x4 unsupported.
  557 21:25:44.507389  <6>[    0.404089] Serial: AMBA PL011 UART driver
  558 21:25:44.537036  <6>[    0.434911] iommu: Default domain type: Translated
  559 21:25:44.546370  <6>[    0.440248] iommu: DMA domain TLB invalidation policy: strict mode
  560 21:25:44.574124  <5>[    0.470824] SCSI subsystem initialized
  561 21:25:44.579248  <6>[    0.475711] usbcore: registered new interface driver usbfs
  562 21:25:44.584133  <6>[    0.481735] usbcore: registered new interface driver hub
  563 21:25:44.594007  <6>[    0.487519] usbcore: registered new device driver usb
  564 21:25:44.600137  <6>[    0.494020] pps_core: LinuxPPS API ver. 1 registered
  565 21:25:44.606262  <6>[    0.499407] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  566 21:25:44.616743  <6>[    0.509133] PTP clock support registered
  567 21:25:44.617159  <6>[    0.513607] EDAC MC: Ver: 3.0.0
  568 21:25:44.666266  <6>[    0.562563] scmi_core: SCMI protocol bus registered
  569 21:25:44.691889  <6>[    0.588969] vgaarb: loaded
  570 21:25:44.697415  <6>[    0.592799] clocksource: Switched to clocksource dmtimer
  571 21:25:44.721746  <6>[    0.619757] NET: Registered PF_INET protocol family
  572 21:25:44.734169  <6>[    0.625459] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  573 21:25:44.741615  <6>[    0.634300] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  574 21:25:44.747886  <6>[    0.643224] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  575 21:25:44.757416  <6>[    0.651467] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  576 21:25:44.768898  <6>[    0.659755] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  577 21:25:44.773997  <6>[    0.667473] TCP: Hash tables configured (established 4096 bind 4096)
  578 21:25:44.777686  <6>[    0.674400] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  579 21:25:44.789875  <6>[    0.681410] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  580 21:25:44.794149  <6>[    0.689016] NET: Registered PF_UNIX/PF_LOCAL protocol family
  581 21:25:44.880516  <6>[    0.772575] RPC: Registered named UNIX socket transport module.
  582 21:25:44.880929  <6>[    0.779007] RPC: Registered udp transport module.
  583 21:25:44.885628  <6>[    0.784135] RPC: Registered tcp transport module.
  584 21:25:44.894260  <6>[    0.789238] RPC: Registered tcp-with-tls transport module.
  585 21:25:44.900386  <6>[    0.795162] RPC: Registered tcp NFSv4.1 backchannel transport module.
  586 21:25:44.908002  <6>[    0.802070] PCI: CLS 0 bytes, default 64
  587 21:25:44.910233  <5>[    0.807846] Initialise system trusted keyrings
  588 21:25:44.932368  <6>[    0.827902] Trying to unpack rootfs image as initramfs...
  589 21:25:45.011117  <6>[    0.903116] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  590 21:25:45.015411  <6>[    0.910616] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  591 21:25:45.055612  <5>[    0.953548] NFS: Registering the id_resolver key type
  592 21:25:45.062003  <5>[    0.959140] Key type id_resolver registered
  593 21:25:45.067989  <5>[    0.963833] Key type id_legacy registered
  594 21:25:45.075368  <6>[    0.968276] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  595 21:25:45.082161  <6>[    0.975478] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  596 21:25:45.152240  <5>[    1.050398] Key type asymmetric registered
  597 21:25:45.158368  <5>[    1.054969] Asymmetric key parser 'x509' registered
  598 21:25:45.166730  <6>[    1.060397] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  599 21:25:45.171877  <6>[    1.068316] io scheduler mq-deadline registered
  600 21:25:45.177999  <6>[    1.073276] io scheduler kyber registered
  601 21:25:45.181206  <6>[    1.077732] io scheduler bfq registered
  602 21:25:45.304655  <6>[    1.198837] ledtrig-cpu: registered to indicate activity on CPUs
  603 21:25:45.573079  <6>[    1.467239] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  604 21:25:45.610048  <6>[    1.507728] msm_serial: driver initialized
  605 21:25:45.616219  <6>[    1.512504] SuperH (H)SCI(F) driver initialized
  606 21:25:45.621187  <6>[    1.517878] STMicroelectronics ASC driver initialized
  607 21:25:45.624710  <6>[    1.523559] STM32 USART driver initialized
  608 21:25:45.749754  <6>[    1.647419] brd: module loaded
  609 21:25:45.787425  <6>[    1.684881] loop: module loaded
  610 21:25:45.826914  <6>[    1.723953] CAN device driver interface
  611 21:25:45.833101  <6>[    1.728939] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  612 21:25:45.838172  <6>[    1.736063] e1000e: Intel(R) PRO/1000 Network Driver
  613 21:25:45.844247  <6>[    1.741451] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  614 21:25:45.850562  <6>[    1.747917] igb: Intel(R) Gigabit Ethernet Network Driver
  615 21:25:45.858648  <6>[    1.753763] igb: Copyright (c) 2007-2014 Intel Corporation.
  616 21:25:45.870072  <6>[    1.763127] pegasus: Pegasus/Pegasus II USB Ethernet driver
  617 21:25:45.876367  <6>[    1.769202] usbcore: registered new interface driver pegasus
  618 21:25:45.879881  <6>[    1.775378] usbcore: registered new interface driver asix
  619 21:25:45.885027  <6>[    1.781234] usbcore: registered new interface driver ax88179_178a
  620 21:25:45.891106  <6>[    1.787836] usbcore: registered new interface driver cdc_ether
  621 21:25:45.896229  <6>[    1.794158] usbcore: registered new interface driver smsc75xx
  622 21:25:45.905987  <6>[    1.800375] usbcore: registered new interface driver smsc95xx
  623 21:25:45.912248  <6>[    1.806609] usbcore: registered new interface driver net1080
  624 21:25:45.917247  <6>[    1.812729] usbcore: registered new interface driver cdc_subset
  625 21:25:45.926982  <6>[    1.819138] usbcore: registered new interface driver zaurus
  626 21:25:45.936616  <6>[    1.825205] usbcore: registered new interface driver cdc_ncm
  627 21:25:45.941010  <6>[    1.834782] usbcore: registered new interface driver usb-storage
  628 21:25:45.949178  <6>[    1.845886] i2c_dev: i2c /dev entries driver
  629 21:25:45.973501  <5>[    1.864198] cpuidle: enable-method property 'ti,am3352' found operations
  630 21:25:45.979624  <6>[    1.873692] sdhci: Secure Digital Host Controller Interface driver
  631 21:25:45.988118  <6>[    1.880348] sdhci: Copyright(c) Pierre Ossman
  632 21:25:45.994273  <6>[    1.886759] Synopsys Designware Multimedia Card Interface Driver
  633 21:25:45.999852  <6>[    1.894712] sdhci-pltfm: SDHCI platform and OF driver helper
  634 21:25:46.013228  <6>[    1.904582] usbcore: registered new interface driver usbhid
  635 21:25:46.013613  <6>[    1.910606] usbhid: USB HID core driver
  636 21:25:46.026918  <6>[    1.921992] NET: Registered PF_INET6 protocol family
  637 21:25:46.466096  <6>[    2.364675] Segment Routing with IPv6
  638 21:25:46.472420  <6>[    2.368824] In-situ OAM (IOAM) with IPv6
  639 21:25:46.479685  <6>[    2.373358] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  640 21:25:46.486085  <6>[    2.380595] NET: Registered PF_PACKET protocol family
  641 21:25:46.491072  <6>[    2.386174] can: controller area network core
  642 21:25:46.497335  <6>[    2.391007] NET: Registered PF_CAN protocol family
  643 21:25:46.497718  <6>[    2.396240] can: raw protocol
  644 21:25:46.507064  <6>[    2.399567] can: broadcast manager protocol
  645 21:25:46.507447  <6>[    2.404165] can: netlink gateway - max_hops=1
  646 21:25:46.512105  <5>[    2.409639] Key type dns_resolver registered
  647 21:25:46.518338  <6>[    2.414712] ThumbEE CPU extension supported.
  648 21:25:46.521995  <5>[    2.419400] Registering SWP/SWPB emulation handler
  649 21:25:46.530288  <3>[    2.425099] omap_voltage_late_init: Voltage driver support not added
  650 21:25:46.718062  <5>[    2.613215] Loading compiled-in X.509 certificates
  651 21:25:46.868884  <6>[    2.753764] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  652 21:25:46.875596  <6>[    2.770372] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  653 21:25:46.902637  <3>[    2.794292] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  654 21:25:47.100310  <3>[    2.992630] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  655 21:25:47.296296  <6>[    3.193548] OMAP GPIO hardware version 0.1
  656 21:25:47.317494  <6>[    3.212140] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  657 21:25:47.410512  <4>[    3.304393] at24 2-0054: supply vcc not found, using dummy regulator
  658 21:25:47.451237  <4>[    3.344342] at24 2-0055: supply vcc not found, using dummy regulator
  659 21:25:47.489384  <4>[    3.383878] at24 2-0056: supply vcc not found, using dummy regulator
  660 21:25:47.525493  <4>[    3.419796] at24 2-0057: supply vcc not found, using dummy regulator
  661 21:25:47.564579  <6>[    3.459889] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  662 21:25:47.645246  <3>[    3.535361] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  663 21:25:47.668606  <6>[    3.556339] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  664 21:25:47.690202  <4>[    3.582389] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  665 21:25:47.721241  <4>[    3.613133] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  666 21:25:47.844934  <6>[    3.738937] omap_rng 48310000.rng: Random Number Generator ver. 20
  667 21:25:47.869027  <5>[    3.765626] random: crng init done
  668 21:25:47.921033  <6>[    3.813435] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  669 21:25:47.957712  <6>[    3.854255] Freeing initrd memory: 14452K
  670 21:25:48.013470  <6>[    3.905233] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  671 21:25:48.019600  <6>[    3.915557] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  672 21:25:48.028099  <6>[    3.922898] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  673 21:25:48.038073  <6>[    3.930367] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  674 21:25:48.047966  <6>[    3.938504] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  675 21:25:48.055345  <6>[    3.950147] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  676 21:25:48.068150  <5>[    3.959179] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  677 21:25:48.096501  <3>[    3.988912] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  678 21:25:48.103286  <6>[    3.997499] edma 49000000.dma: TI EDMA DMA engine driver
  679 21:25:48.173368  <3>[    4.065206] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  680 21:25:48.187585  <6>[    4.079534] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  681 21:25:48.201204  <3>[    4.096587] l3-aon-clkctrl:0000:0: failed to disable
  682 21:25:48.255089  <6>[    4.146690] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  683 21:25:48.258959  <6>[    4.156207] printk: legacy console [ttyS0] enabled
  684 21:25:48.265083  <6>[    4.156207] printk: legacy console [ttyS0] enabled
  685 21:25:48.271187  <6>[    4.166529] printk: legacy bootconsole [omap8250] disabled
  686 21:25:48.277872  <6>[    4.166529] printk: legacy bootconsole [omap8250] disabled
  687 21:25:48.312866  <4>[    4.203544] tps65217-pmic: Failed to locate of_node [id: -1]
  688 21:25:48.315954  <4>[    4.210937] tps65217-bl: Failed to locate of_node [id: -1]
  689 21:25:48.331722  <6>[    4.230490] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  690 21:25:48.350357  <6>[    4.237441] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  691 21:25:48.360106  <6>[    4.251139] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  692 21:25:48.368205  <6>[    4.263042] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  693 21:25:48.390095  <6>[    4.282924] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  694 21:25:48.396218  <6>[    4.291982] sdhci-omap 48060000.mmc: Got CD GPIO
  695 21:25:48.404148  <4>[    4.297166] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  696 21:25:48.418954  <4>[    4.310610] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  697 21:25:48.425089  <4>[    4.319307] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  698 21:25:48.434494  <4>[    4.327911] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  699 21:25:48.533819  <6>[    4.427444] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  700 21:25:48.577565  <6>[    4.470155] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  701 21:25:48.625212  <6>[    4.516654] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  702 21:25:48.631841  <6>[    4.526217] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  703 21:25:48.703393  <6>[    4.591488] mmc1: new high speed MMC card at address 0001
  704 21:25:48.703780  <6>[    4.599614] mmcblk1: mmc1:0001 M62704 3.56 GiB
  705 21:25:48.714078  <6>[    4.611303]  mmcblk1: p1
  706 21:25:48.727373  <6>[    4.615820] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  707 21:25:48.732028  <6>[    4.628476] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  708 21:25:48.743673  <6>[    4.639351] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  709 21:25:48.758685  <6>[    4.652997] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  710 21:25:50.861906  <6>[    6.753851] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  711 21:25:51.004378  <5>[    6.782821] Sending DHCP requests ., OK
  712 21:25:51.016590  <6>[    6.907278] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.190
  713 21:25:51.017000  <6>[    6.915408] IP-Config: Complete:
  714 21:25:51.029049  <6>[    6.918949]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.190, mask=255.255.255.0, gw=172.16.3.3
  715 21:25:51.035115  <6>[    6.929380]      host=172.16.3.190, domain=denx.de, nis-domain=(none)
  716 21:25:51.044898  <6>[    6.936202]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  717 21:25:51.045289  <6>[    6.936235]      nameserver0=172.16.3.3
  718 21:25:51.051160  <6>[    6.947538]      ntpserver0=172.16.3.3
  719 21:25:51.057255  <6>[    6.952982] clk: Disabling unused clocks
  720 21:25:51.060564  <6>[    6.957587] PM: genpd: Disabling unused power domains
  721 21:25:51.080518  <6>[    6.975630] Freeing unused kernel image (initmem) memory: 2048K
  722 21:25:51.088819  <6>[    6.985372] Run /init as init process
  723 21:25:51.111445  Loading, please wait...
  724 21:25:51.187222  Starting systemd-udevd version 252.22-1~deb12u1
  725 21:25:54.193725  <4>[   10.084661] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  726 21:25:54.394900  <4>[   10.285705] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  727 21:25:54.524760  <6>[   10.423690] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  728 21:25:54.535161  <6>[   10.429362] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  729 21:25:54.785057  <6>[   10.682367] hub 1-0:1.0: USB hub found
  730 21:25:54.797978  <6>[   10.695945] tda998x 0-0070: found TDA19988
  731 21:25:54.804710  <6>[   10.701331] hub 1-0:1.0: 1 port detected
  732 21:25:57.678975  Begin: Loading essential drivers ... done.
  733 21:25:57.685088  Begin: Running /scripts/init-premount ... done.
  734 21:25:57.690076  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  735 21:25:57.698624  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  736 21:25:57.704325  Device /sys/class/net/eth0 found
  737 21:25:57.704704  done.
  738 21:25:57.765846  Begin: Waiting up to 180 secs for any network device to become available ... done.
  739 21:25:57.837630  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  740 21:25:57.885049  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  741 21:25:57.897191   address: 172.16.3.190     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  742 21:25:57.900766   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  743 21:25:57.910963   domain : denx.de                                                         
  744 21:25:57.911347   rootserver: 172.16.3.33 rootpath: 
  745 21:25:57.916507   filename  : this-host-is-not-configured.kpxe
  746 21:25:57.966476  done.
  747 21:25:57.983478  Begin: Running /scripts/nfs-bottom ... done.
  748 21:25:58.048366  Begin: Running /scripts/init-bottom ... done.
  749 21:25:59.339359  <30>[   15.233990] systemd[1]: System time before build time, advancing clock.
  750 21:25:59.550570  <30>[   15.418731] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  751 21:25:59.562064  <30>[   15.458287] systemd[1]: Detected architecture arm.
  752 21:25:59.575837  
  753 21:25:59.576235  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  754 21:25:59.576546  
  755 21:25:59.597098  <30>[   15.492608] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  756 21:26:01.946000  <30>[   17.839272] systemd[1]: Queued start job for default target graphical.target.
  757 21:26:01.964060  <30>[   17.856778] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  758 21:26:01.971942  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  759 21:26:01.992934  <30>[   17.885611] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  760 21:26:02.001101  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  761 21:26:02.023192  <30>[   17.916225] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  762 21:26:02.031549  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  763 21:26:02.052513  <30>[   17.944815] systemd[1]: Created slice user.slice - User and Session Slice.
  764 21:26:02.058225  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  765 21:26:02.087493  <30>[   17.974199] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  766 21:26:02.093208  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  767 21:26:02.111082  <30>[   18.003930] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  768 21:26:02.122789  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  769 21:26:02.149087  <30>[   18.033850] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  770 21:26:02.161480  <30>[   18.054362] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  771 21:26:02.167094           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  772 21:26:02.190171  <30>[   18.083332] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  773 21:26:02.198206  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  774 21:26:02.221597  <30>[   18.113694] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  775 21:26:02.231049  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  776 21:26:02.251066  <30>[   18.143862] systemd[1]: Reached target paths.target - Path Units.
  777 21:26:02.256555  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  778 21:26:02.280950  <30>[   18.173447] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  779 21:26:02.287577  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  780 21:26:02.312003  <30>[   18.204222] systemd[1]: Reached target slices.target - Slice Units.
  781 21:26:02.317569  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  782 21:26:02.340620  <30>[   18.233628] systemd[1]: Reached target swap.target - Swaps.
  783 21:26:02.344063  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  784 21:26:02.371460  <30>[   18.263470] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  785 21:26:02.378657  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  786 21:26:02.402815  <30>[   18.294459] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  787 21:26:02.410157  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  788 21:26:02.500904  <30>[   18.389768] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  789 21:26:02.514806  <30>[   18.407422] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  790 21:26:02.523183  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  791 21:26:02.552893  <30>[   18.447183] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  792 21:26:02.565946  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  793 21:26:02.594542  <30>[   18.486009] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  794 21:26:02.601906  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  795 21:26:02.638036  <30>[   18.530995] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  796 21:26:02.651208  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  797 21:26:02.672091  <30>[   18.564807] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  798 21:26:02.680328  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  799 21:26:02.708704  <30>[   18.594558] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  800 21:26:02.722274  <30>[   18.611177] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  801 21:26:02.773998  <30>[   18.668462] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  802 21:26:02.800667           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  803 21:26:02.850523  <30>[   18.743937] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  804 21:26:02.879257           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  805 21:26:02.981074  <30>[   18.873685] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  806 21:26:02.995013           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  807 21:26:03.043584  <30>[   18.934066] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  808 21:26:03.049798           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  809 21:26:03.092052  <30>[   18.985806] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  810 21:26:03.120762           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  811 21:26:03.171435  <30>[   19.063907] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  812 21:26:03.176973           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  813 21:26:03.210950  <30>[   19.104380] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  814 21:26:03.239104           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  815 21:26:03.292839  <30>[   19.186340] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  816 21:26:03.313212           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  817 21:26:03.370745  <30>[   19.263939] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  818 21:26:03.391047           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  819 21:26:03.409075  <28>[   19.297263] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  820 21:26:03.429436  <28>[   19.322567] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  821 21:26:03.479161  <30>[   19.374205] systemd[1]: Starting systemd-journald.service - Journal Service...
  822 21:26:03.498187           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  823 21:26:03.570366  <30>[   19.464234] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  824 21:26:03.589447           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  825 21:26:03.613602  <30>[   19.506889] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  826 21:26:03.699183           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  827 21:26:03.784021  <30>[   19.676214] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  828 21:26:03.830638           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  829 21:26:03.883787  <30>[   19.776180] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  830 21:26:03.923010           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  831 21:26:03.999944  <30>[   19.893290] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  832 21:26:04.007933  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  833 21:26:04.040933  <30>[   19.935103] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  834 21:26:04.080233  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  835 21:26:04.104930  <30>[   19.997306] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  836 21:26:04.134843  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  837 21:26:04.281868  <30>[   20.175442] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  838 21:26:04.311843  <30>[   20.204467] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  839 21:26:04.340732  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  840 21:26:04.362039  <30>[   20.255613] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  841 21:26:04.388667  <30>[   20.282386] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  842 21:26:04.420771  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  843 21:26:04.441652  <30>[   20.334623] systemd[1]: Started systemd-journald.service - Journal Service.
  844 21:26:04.448431  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  845 21:26:04.471909  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  846 21:26:04.496449  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  847 21:26:04.532626  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  848 21:26:04.556033  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  849 21:26:04.583718  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  850 21:26:04.603106  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  851 21:26:04.623405  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  852 21:26:04.654209  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  853 21:26:04.722987           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  854 21:26:04.774788           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  855 21:26:04.841627           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  856 21:26:04.934623           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  857 21:26:04.992858           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  858 21:26:05.131505  <46>[   21.025695] systemd-journald[162]: Received client request to flush runtime journal.
  859 21:26:05.142375  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  860 21:26:05.347135  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  861 21:26:05.392875  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  862 21:26:05.452127           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  863 21:26:05.510421  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  864 21:26:06.453044  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  865 21:26:06.471289  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  866 21:26:06.502056  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  867 21:26:06.759967           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  868 21:26:07.335427  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  869 21:26:07.392530           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  870 21:26:07.883638  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  871 21:26:07.931402           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  872 21:26:09.841898  <5>[   25.736377] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  873 21:26:09.928713  [[0m[0;31m*     [0m] (1 of 4) Job systemd-tmpfiles-setup…vice/start running (7s / no limit)
  874 21:26:10.418825  M[K[[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  875 21:26:10.810589  [K[[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  876 21:26:11.479798  <5>[   27.375925] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  877 21:26:11.564384  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  878 21:26:11.585364  <5>[   27.478125] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  879 21:26:11.591586  <4>[   27.487410] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  880 21:26:11.599487  <6>[   27.496543] cfg80211: failed to load regulatory.db
  881 21:26:12.544240  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  882 21:26:20.225129  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  883 21:26:20.252007  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  884 21:26:20.272531  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  885 21:26:20.339252           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  886 21:26:20.383890           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  887 21:26:20.418872           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  888 21:26:20.461151           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  889 21:26:20.732513           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  890 21:26:20.771820           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  891 21:26:20.814524  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  892 21:26:20.851873  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  893 21:26:20.894100  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  894 21:26:20.927470  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  895 21:26:21.077615  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  896 21:26:21.580535  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  897 21:26:21.614632  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  898 21:26:21.640228  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  899 21:26:21.660430  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  900 21:26:21.793798  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  901 21:26:21.883763  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  902 21:26:21.912761  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  903 21:26:22.001565  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  904 21:26:22.184860  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  905 21:26:22.214721  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  906 21:26:22.246912  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  907 21:26:22.268138  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  908 21:26:22.292596  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  909 21:26:22.369801           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  910 21:26:22.409984           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  911 21:26:22.655892           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  912 21:26:22.841900           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  913 21:26:22.879014           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  914 21:26:22.902812  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  915 21:26:23.010922  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  916 21:26:23.039538  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  917 21:26:23.339405           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  918 21:26:23.358726  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  919 21:26:23.423168  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  920 21:26:23.532311  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  921 21:26:23.569383  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  922 21:26:23.609730  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  923 21:26:23.933980  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  924 21:26:24.185799  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  925 21:26:24.236763  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  926 21:26:24.265749  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  927 21:26:24.354729           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  928 21:26:24.584048  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  929 21:26:24.823598  
  930 21:26:24.823979  Debian GNU/Linux 12 debian-bookworm-armhf ttyS0
  931 21:26:24.824290  
  932 21:26:24.831317  debian-bookworm-armhf lo
  933 21:26:24.831701  
  934 21:26:25.208924  Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sun Nov  3 20:41:51 UTC 2024 armv7l
  935 21:26:25.209309  
  936 21:26:25.215014  The programs included with the Debian GNU/Linux system are free software;
  937 21:26:25.218823  the exact distribution terms for each program are described in the
  938 21:26:25.223936  individual files in /usr/share/doc/*/copyright.
  939 21:26:25.224316  
  940 21:26:25.230144  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  941 21:26:25.234529  permitted by applicable law.
  942 21:26:30.127595  Unable to match end of the kernel message
  944 21:26:30.128616  Setting prompt string to ['/ #']
  945 21:26:30.129097  end: 2.4.4.1 login-action (duration 00:00:46) [common]
  947 21:26:30.130030  end: 2.4.4 auto-login-action (duration 00:00:47) [common]
  948 21:26:30.130451  start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
  949 21:26:30.130795  Setting prompt string to ['/ #']
  950 21:26:30.131092  Forcing a shell prompt, looking for ['/ #']
  952 21:26:30.181855  / # 
  953 21:26:30.182376  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  954 21:26:30.182763  Waiting using forced prompt support (timeout 00:02:30)
  955 21:26:30.189433  
  956 21:26:30.197500  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  957 21:26:30.197970  start: 2.4.6 export-device-env (timeout 00:03:12) [common]
  958 21:26:30.198330  Sending with 10 millisecond of delay
  960 21:26:35.255788  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a'
  961 21:26:35.266518  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1215758/extract-nfsrootfs-nejgol4a'
  962 21:26:35.269303  Sending with 10 millisecond of delay
  964 21:26:37.310760  / # export NFS_SERVER_IP='172.16.3.3'
  965 21:26:37.321471  export NFS_SERVER_IP='172.16.3.3'
  966 21:26:37.323734  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  967 21:26:37.324204  end: 2.4 uboot-commands (duration 00:01:55) [common]
  968 21:26:37.324645  end: 2 uboot-action (duration 00:01:55) [common]
  969 21:26:37.325135  start: 3 lava-test-retry (timeout 00:06:52) [common]
  970 21:26:37.325583  start: 3.1 lava-test-shell (timeout 00:06:52) [common]
  971 21:26:37.325927  Using namespace: common
  973 21:26:37.426914  / # #
  974 21:26:37.427421  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  975 21:26:37.434788  #
  976 21:26:37.440726  Using /lava-1215758
  978 21:26:37.541847  / # export SHELL=/bin/bash
  979 21:26:37.549014  export SHELL=/bin/bash
  981 21:26:37.654494  / # . /lava-1215758/environment
  982 21:26:37.661992  . /lava-1215758/environment
  984 21:26:37.774982  / # /lava-1215758/bin/lava-test-runner /lava-1215758/0
  985 21:26:37.775498  Test shell timeout: 10s (minimum of the action and connection timeout)
  986 21:26:37.782826  /lava-1215758/bin/lava-test-runner /lava-1215758/0
  987 21:26:38.390953  + export TESTRUN_ID=0_timesync-off
  988 21:26:38.398831  + TESTRUN_ID=0_timesync-off
  989 21:26:38.399220  + cd /lava-1215758/0/tests/0_timesync-off
  990 21:26:38.399533  ++ cat uuid
  991 21:26:38.424199  + UUID=1215758_1.6.2.4.1
  992 21:26:38.424586  + set +x
  993 21:26:38.430504  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1215758_1.6.2.4.1>
  994 21:26:38.431148  Received signal: <STARTRUN> 0_timesync-off 1215758_1.6.2.4.1
  995 21:26:38.431482  Starting test lava.0_timesync-off (1215758_1.6.2.4.1)
  996 21:26:38.431867  Skipping test definition patterns.
  997 21:26:38.433737  + systemctl stop systemd-timesyncd
  998 21:26:38.768312  + set +x
  999 21:26:38.768933  Received signal: <ENDRUN> 0_timesync-off 1215758_1.6.2.4.1
 1000 21:26:38.769307  Ending use of test pattern.
 1001 21:26:38.769610  Ending test lava.0_timesync-off (1215758_1.6.2.4.1), duration 0.34
 1003 21:26:38.771452  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1215758_1.6.2.4.1>
 1004 21:26:39.043551  + export TESTRUN_ID=1_kselftest-dt
 1005 21:26:39.052747  + TESTRUN_ID=1_kselftest-dt
 1006 21:26:39.053160  + cd /lava-1215758/0/tests/1_kselftest-dt
 1007 21:26:39.053475  ++ cat uuid
 1008 21:26:39.092853  + UUID=1215758_1.6.2.4.5
 1009 21:26:39.093240  + set +x
 1010 21:26:39.097800  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1215758_1.6.2.4.5>
 1011 21:26:39.098192  + cd ./automated/linux/kselftest/
 1012 21:26:39.098742  Received signal: <STARTRUN> 1_kselftest-dt 1215758_1.6.2.4.5
 1013 21:26:39.099057  Starting test lava.1_kselftest-dt (1215758_1.6.2.4.5)
 1014 21:26:39.099409  Skipping test definition patterns.
 1015 21:26:39.126924  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1016 21:26:39.275190  INFO: install_deps skipped
 1017 21:26:39.936571  --2024-01-26 21:49:16--  http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
 1018 21:26:39.975637  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1019 21:26:40.136293  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1020 21:26:40.292484  HTTP request sent, awaiting response... 200 OK
 1021 21:26:40.292933  Length: 4106072 (3.9M) [application/octet-stream]
 1022 21:26:40.297417  Saving to: 'kselftest_armhf.tar.gz'
 1023 21:26:40.297738  
 1024 21:26:42.511645  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  46.14K   148KB/s               kselftest_armhf.tar   5%[>                   ] 218.67K   348KB/s               kselftest_armhf.tar  16%[==>                 ] 651.79K   668KB/s               kselftest_armhf.tar  46%[========>           ]   1.81M  1.39MB/s               kselftest_armhf.tar  64%[===========>        ]   2.52M  1.61MB/s               kselftest_armhf.tar  78%[==============>     ]   3.07M  1.73MB/s               kselftest_armhf.tar  89%[================>   ]   3.50M  1.77MB/s               kselftest_armhf.tar  98%[==================> ]   3.84M  1.75MB/s               kselftest_armhf.tar 100%[===================>]   3.92M  1.77MB/s    in 2.2s    
 1025 21:26:42.512071  
 1026 21:26:43.205126  2024-01-26 21:49:19 (1.77 MB/s) - 'kselftest_armhf.tar.gz' saved [4106072/4106072]
 1027 21:26:43.205581  
 1028 21:26:43.494643  tar: ./nsfs/pidns: time stamp 2024-11-03 20:51:22 is 24361321.845778579 s in the future
 1029 21:26:43.635290  tar: ./nsfs/config: time stamp 2024-10-27 19:28:30 is 23751549.702962787 s in the future
 1030 21:26:43.782237  tar: ./nsfs/owner: time stamp 2024-11-03 20:51:22 is 24361321.555914245 s in the future
 1031 21:26:43.831944  tar: ./nsfs: time stamp 2024-11-03 20:52:07 is 24361366.505790245 s in the future
 1032 21:26:43.988732  tar: ./cachestat/test_cachestat: time stamp 2024-11-03 20:50:10 is 24361249.351251454 s in the future
 1033 21:26:44.046835  tar: ./cachestat: time stamp 2024-11-03 20:51:58 is 24361357.290551412 s in the future
 1034 21:26:44.186507  tar: ./kselftest/prefix.pl: time stamp 2024-11-03 20:51:58 is 24361357.152351203 s in the future
 1035 21:26:44.316625  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-27 19:28:30 is 23751549.022124037 s in the future
 1036 21:26:44.450125  tar: ./kselftest/runner.sh: time stamp 2024-11-03 20:51:58 is 24361356.888553203 s in the future
 1037 21:26:44.577119  tar: ./kselftest/ksft.py: time stamp 2024-11-03 20:51:58 is 24361356.761455787 s in the future
 1038 21:26:44.703099  tar: ./kselftest/module.sh: time stamp 2024-11-03 20:51:57 is 24361355.635287703 s in the future
 1039 21:26:44.765645  tar: ./kselftest: time stamp 2024-10-27 19:28:30 is 23751548.57300212 s in the future
 1040 21:26:44.928649  tar: ./cpufreq/governor.sh: time stamp 2024-10-27 19:28:30 is 23751548.410788495 s in the future
 1041 21:26:45.056546  tar: ./cpufreq/config: time stamp 2024-10-27 19:28:30 is 23751548.281370495 s in the future
 1042 21:26:45.194005  tar: ./cpufreq/cpufreq.sh: time stamp 2024-10-27 19:28:30 is 23751548.144185328 s in the future
 1043 21:26:45.329097  tar: ./cpufreq/special-tests.sh: time stamp 2024-10-27 19:28:30 is 23751548.009676245 s in the future
 1044 21:26:45.463934  tar: ./cpufreq/module.sh: time stamp 2024-10-27 19:28:30 is 23751547.874691328 s in the future
 1045 21:26:45.590908  tar: ./cpufreq/cpu.sh: time stamp 2024-10-27 19:28:30 is 23751547.747709912 s in the future
 1046 21:26:45.722009  tar: ./cpufreq/main.sh: time stamp 2024-10-27 19:28:30 is 23751547.616108953 s in the future
 1047 21:26:45.772838  tar: ./cpufreq: time stamp 2024-11-03 20:51:59 is 24361356.56402712 s in the future
 1048 21:26:45.940876  tar: ./kvm/config: time stamp 2024-10-27 19:28:30 is 23751547.397303703 s in the future
 1049 21:26:46.091062  tar: ./kvm/settings: time stamp 2024-10-27 19:28:30 is 23751547.24727562 s in the future
 1050 21:26:46.144050  tar: ./kvm: time stamp 2024-11-03 20:52:03 is 24361360.193363162 s in the future
 1051 21:26:46.279438  tar: ./size/get_size: time stamp 2024-11-03 20:51:38 is 24361335.058941828 s in the future
 1052 21:26:46.340851  tar: ./size: time stamp 2024-11-03 20:52:08 is 24361364.99644362 s in the future
 1053 21:26:46.501587  tar: ./amd-pstate/gitsource.sh: time stamp 2024-10-27 19:28:30 is 23751546.836730495 s in the future
 1054 21:26:46.646588  tar: ./amd-pstate/run.sh: time stamp 2024-10-27 19:28:30 is 23751546.69280187 s in the future
 1055 21:26:46.773506  tar: ./amd-pstate/basic.sh: time stamp 2024-10-27 19:28:30 is 23751546.564973328 s in the future
 1056 21:26:46.901640  tar: ./amd-pstate/config: time stamp 2024-10-27 19:28:30 is 23751546.436548661 s in the future
 1057 21:26:47.043543  tar: ./amd-pstate/tbench.sh: time stamp 2024-10-27 19:28:30 is 23751546.294768995 s in the future
 1058 21:26:47.108231  tar: ./amd-pstate: time stamp 2024-11-03 20:51:58 is 24361354.229698203 s in the future
 1059 21:26:47.272055  tar: ./pidfd/pidfd_poll_test: time stamp 2024-11-03 20:51:23 is 24361319.066350911 s in the future
 1060 21:26:47.429495  tar: ./pidfd/pidfd_test: time stamp 2024-11-03 20:51:23 is 24361318.90798262 s in the future
 1061 21:26:47.569058  tar: ./pidfd/config: time stamp 2024-10-27 19:28:30 is 23751545.76919062 s in the future
 1062 21:26:47.744737  tar: ./pidfd/pidfd_setns_test: time stamp 2024-11-03 20:51:24 is 24361319.59402337 s in the future
 1063 21:26:47.913089  tar: ./pidfd/pidfd_getfd_test: time stamp 2024-11-03 20:51:24 is 24361319.425273995 s in the future
 1064 21:26:48.067577  tar: ./pidfd/pidfd_wait: time stamp 2024-11-03 20:51:24 is 24361319.270370245 s in the future
 1065 21:26:48.230537  tar: ./pidfd/pidfd_fdinfo_test: time stamp 2024-11-03 20:51:23 is 24361318.108099953 s in the future
 1066 21:26:48.387180  tar: ./pidfd/pidfd_open_test: time stamp 2024-11-03 20:51:23 is 24361317.951930495 s in the future
 1067 21:26:48.433911  tar: ./pidfd: time stamp 2024-11-03 20:52:07 is 24361361.903699786 s in the future
 1068 21:26:48.625540  tar: ./alsa/utimer-test: time stamp 2024-11-03 20:50:10 is 24361244.713592745 s in the future
 1069 21:26:48.765307  tar: ./alsa/pcm-test.conf: time stamp 2024-10-27 19:28:30 is 23751544.573663161 s in the future
 1070 21:26:48.909306  tar: ./alsa/global-timer: time stamp 2024-11-03 20:50:09 is 24361243.429784078 s in the future
 1071 21:26:49.043630  tar: ./alsa/mixer-test: time stamp 2024-11-03 20:50:09 is 24361243.294841578 s in the future
 1072 21:26:49.182469  tar: ./alsa/libatest.so: time stamp 2024-11-03 20:50:09 is 24361243.154552536 s in the future
 1073 21:26:49.332894  tar: ./alsa/test-pcmtest-driver: time stamp 2024-11-03 20:50:10 is 24361244.006463703 s in the future
 1074 21:26:49.484327  tar: ./alsa/pcm-test: time stamp 2024-11-03 20:50:10 is 24361243.854285411 s in the future
 1075 21:26:49.640117  tar: ./alsa/conf.d/Lenovo_ThinkPad_P1_Gen2.conf: time stamp 2024-10-27 19:28:30 is 23751543.700676286 s in the future
 1076 21:26:49.709929  tar: ./alsa/conf.d: time stamp 2024-10-27 19:28:30 is 23751543.627585661 s in the future
 1077 21:26:49.770493  tar: ./alsa: time stamp 2024-11-03 20:51:58 is 24361351.567561119 s in the future
 1078 21:26:49.971508  tar: ./rust/test_probe_samples.sh: time stamp 2024-10-27 19:28:30 is 23751543.367355578 s in the future
 1079 21:26:50.086785  tar: ./rust/config: time stamp 2024-10-27 19:28:30 is 23751543.250504411 s in the future
 1080 21:26:50.141970  tar: ./rust: time stamp 2024-11-03 20:52:08 is 24361361.195473911 s in the future
 1081 21:26:50.305024  tar: ./capabilities/test_execve: time stamp 2024-11-03 20:50:10 is 24361243.033534703 s in the future
 1082 21:26:50.442656  tar: ./capabilities/validate_cap: time stamp 2024-11-03 20:50:10 is 24361242.896887328 s in the future
 1083 21:26:50.504344  tar: ./capabilities: time stamp 2024-11-03 20:51:58 is 24361350.833621744 s in the future
 1084 21:26:50.635554  tar: ./net/net_helper.sh: time stamp 2024-10-27 19:28:30 is 23751542.701902453 s in the future
 1085 21:26:50.768645  tar: ./net/lib.sh: time stamp 2024-10-27 19:28:30 is 23751542.568404369 s in the future
 1086 21:26:50.934702  tar: ./net/netfilter/nft_tproxy_tcp.sh: time stamp 2024-10-27 19:28:30 is 23751542.404893536 s in the future
 1087 21:26:51.090501  tar: ./net/netfilter/nf_nat_edemux.sh: time stamp 2024-10-27 19:28:30 is 23751542.249549703 s in the future
 1088 21:26:51.206041  tar: ./net/netfilter/conntrack_sctp_collision.sh: time stamp 2024-10-27 19:28:30 is 23751542.134743578 s in the future
 1089 21:26:51.345280  tar: ./net/netfilter/audit_logread: time stamp 2024-11-03 20:51:11 is 24361302.994524119 s in the future
 1090 21:26:51.481467  tar: ./net/netfilter/br_netfilter.sh: time stamp 2024-10-27 19:28:30 is 23751541.857462286 s in the future
 1091 21:26:51.620562  tar: ./net/netfilter/conntrack_icmp_related.sh: time stamp 2024-10-27 19:28:30 is 23751541.719053494 s in the future
 1092 21:26:51.746569  tar: ./net/netfilter/lib.sh: time stamp 2024-10-27 19:28:30 is 23751541.592658828 s in the future
 1093 21:26:51.863420  tar: ./net/netfilter/ipvs.sh: time stamp 2024-10-27 19:28:30 is 23751541.475773453 s in the future
 1094 21:26:52.005575  tar: ./net/netfilter/nft_concat_range.sh: time stamp 2024-10-27 19:28:30 is 23751541.334758953 s in the future
 1095 21:26:52.153664  tar: ./net/netfilter/nf_queue: time stamp 2024-11-03 20:51:11 is 24361302.184602828 s in the future
 1096 21:26:52.293578  tar: ./net/netfilter/nft_queue.sh: time stamp 2024-10-27 19:28:30 is 23751541.045316161 s in the future
 1097 21:26:52.421985  tar: ./net/netfilter/vxlan_mtu_frag.sh: time stamp 2024-10-27 19:28:30 is 23751540.917282661 s in the future
 1098 21:26:52.555491  tar: ./net/netfilter/conntrack_reverse_clash.sh: time stamp 2024-10-27 19:28:30 is 23751540.783830369 s in the future
 1099 21:26:52.691316  tar: ./net/netfilter/nft_synproxy.sh: time stamp 2024-10-27 19:28:30 is 23751540.647940494 s in the future
 1100 21:26:52.832484  tar: ./net/netfilter/conntrack_reverse_clash: time stamp 2024-11-03 20:51:11 is 24361301.508156827 s in the future
 1101 21:26:52.960774  tar: ./net/netfilter/nft_nat_zones.sh: time stamp 2024-10-27 19:28:30 is 23751540.378088911 s in the future
 1102 21:26:53.090020  tar: ./net/netfilter/nft_tproxy_udp.sh: time stamp 2024-10-27 19:28:30 is 23751540.249627077 s in the future
 1103 21:26:53.216400  tar: ./net/netfilter/nft_audit.sh: time stamp 2024-10-27 19:28:30 is 23751540.122499452 s in the future
 1104 21:26:53.356221  tar: ./net/netfilter/sctp_collision: time stamp 2024-11-03 20:51:11 is 24361300.982882702 s in the future
 1105 21:26:53.495096  tar: ./net/netfilter/nft_meta.sh: time stamp 2024-10-27 19:28:30 is 23751539.844289577 s in the future
 1106 21:26:53.613553  tar: ./net/netfilter/config: time stamp 2024-10-27 19:28:30 is 23751539.724268577 s in the future
 1107 21:26:53.783629  tar: ./net/netfilter/packetdrill/conntrack_syn_challenge_ack.pkt: time stamp 2024-10-27 19:28:30 is 23751539.558842036 s in the future
 1108 21:26:53.909028  tar: ./net/netfilter/packetdrill/conntrack_rst_invalid.pkt: time stamp 2024-10-27 19:28:30 is 23751539.432306452 s in the future
 1109 21:26:54.050279  tar: ./net/netfilter/packetdrill/conntrack_synack_old.pkt: time stamp 2024-10-27 19:28:30 is 23751539.291563286 s in the future
 1110 21:26:54.287608  tar: ./net/netfilter/packetdrill/conntrack_synack_reuse.pkt: time stamp 2024-10-27 19:28:30 is 23751539.053620244 s in the future
 1111 21:26:54.505414  tar: ./net/netfilter/packetdrill/common.sh: time stamp 2024-10-27 19:28:30 is 23751538.833274202 s in the future
 1112 21:26:54.632923  tar: ./net/netfilter/packetdrill/conntrack_ack_loss_stall.pkt: time stamp 2024-10-27 19:28:30 is 23751538.707998911 s in the future
 1113 21:26:54.760646  tar: ./net/netfilter/packetdrill/conntrack_inexact_rst.pkt: time stamp 2024-10-27 19:28:30 is 23751538.579549577 s in the future
 1114 21:26:54.823161  tar: ./net/netfilter/packetdrill: time stamp 2024-10-27 19:28:30 is 23751538.516038827 s in the future
 1115 21:26:54.948271  tar: ./net/netfilter/rpath.sh: time stamp 2024-10-27 19:28:30 is 23751538.390708952 s in the future
 1116 21:26:55.091286  tar: ./net/netfilter/xt_string.sh: time stamp 2024-10-27 19:28:30 is 23751538.247792869 s in the future
 1117 21:26:55.223711  tar: ./net/netfilter/bridge_brouter.sh: time stamp 2024-10-27 19:28:30 is 23751538.115735494 s in the future
 1118 21:26:55.373040  tar: ./net/netfilter/nft_nat.sh: time stamp 2024-10-27 19:28:30 is 23751537.965552744 s in the future
 1119 21:26:55.505508  tar: ./net/netfilter/nf_conntrack_packetdrill.sh: time stamp 2024-10-27 19:28:30 is 23751537.834224494 s in the future
 1120 21:26:55.666462  tar: ./net/netfilter/nft_fib.sh: time stamp 2024-10-27 19:28:30 is 23751537.672378035 s in the future
 1121 21:26:55.798997  tar: ./net/netfilter/conntrack_ipip_mtu.sh: time stamp 2024-10-27 19:28:30 is 23751537.54018641 s in the future
 1122 21:26:55.925141  tar: ./net/netfilter/conntrack_tcp_unreplied.sh: time stamp 2024-10-27 19:28:30 is 23751537.415195202 s in the future
 1123 21:26:56.074606  tar: ./net/netfilter/conntrack_dump_flush: time stamp 2024-11-03 20:51:11 is 24361298.264988202 s in the future
 1124 21:26:56.192420  tar: ./net/netfilter/nft_concat_range_perf.sh: time stamp 2024-10-27 19:28:30 is 23751537.14707941 s in the future
 1125 21:26:56.307972  tar: ./net/netfilter/br_netfilter_queue.sh: time stamp 2024-10-27 19:28:30 is 23751537.031407702 s in the future
 1126 21:26:56.460345  tar: ./net/netfilter/settings: time stamp 2024-10-27 19:28:30 is 23751536.877843994 s in the future
 1127 21:26:56.592716  tar: ./net/netfilter/nft_flowtable.sh: time stamp 2024-11-01 00:06:48 is 24113834.746564035 s in the future
 1128 21:26:56.717720  tar: ./net/netfilter/nft_conntrack_helper.sh: time stamp 2024-10-27 19:28:30 is 23751536.621540869 s in the future
 1129 21:26:56.899768  tar: ./net/netfilter/conntrack_vrf.sh: time stamp 2024-10-27 19:28:30 is 23751536.439281119 s in the future
 1130 21:26:57.050165  tar: ./net/netfilter/nft_zones_many.sh: time stamp 2024-10-27 19:28:30 is 23751536.289085994 s in the future
 1131 21:26:57.193130  tar: ./net/netfilter/connect_close: time stamp 2024-11-03 20:51:11 is 24361297.146164202 s in the future
 1132 21:26:57.242103  tar: ./net/netfilter: time stamp 2024-11-03 20:52:06 is 24361352.096049119 s in the future
 1133 21:26:57.466420  tar: ./net/tcp_ao/self-connect_ipv4: time stamp 2024-11-03 20:51:16 is 24361301.873110994 s in the future
 1134 21:26:57.670524  tar: ./net/tcp_ao/restore_ipv4: time stamp 2024-11-03 20:51:15 is 24361300.668553494 s in the future
 1135 21:26:57.894607  tar: ./net/tcp_ao/icmps-discard_ipv6: time stamp 2024-11-03 20:51:19 is 24361304.443647952 s in the future
 1136 21:26:58.085048  tar: ./net/tcp_ao/connect-deny_ipv6: time stamp 2024-11-03 20:51:18 is 24361303.253812118 s in the future
 1137 21:26:58.266024  tar: ./net/tcp_ao/bench-lookups_ipv4: time stamp 2024-11-03 20:51:13 is 24361298.072342452 s in the future
 1138 21:26:58.476406  tar: ./net/tcp_ao/bench-lookups_ipv6: time stamp 2024-11-03 20:51:18 is 24361302.862003285 s in the future
 1139 21:26:58.654211  tar: ./net/tcp_ao/icmps-discard_ipv4: time stamp 2024-11-03 20:51:14 is 24361298.684552535 s in the future
 1140 21:26:58.901698  tar: ./net/tcp_ao/self-connect_ipv6: time stamp 2024-11-03 20:51:21 is 24361305.436940118 s in the future
 1141 21:26:59.040503  tar: ./net/tcp_ao/config: time stamp 2024-10-27 19:28:30 is 23751534.296895327 s in the future
 1142 21:26:59.245869  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-11-03 20:51:16 is 24361300.092613452 s in the future
 1143 21:26:59.471196  tar: ./net/tcp_ao/connect_ipv4: time stamp 2024-11-03 20:51:13 is 24361296.867429118 s in the future
 1144 21:26:59.676719  tar: ./net/tcp_ao/unsigned-md5_ipv6: time stamp 2024-11-03 20:51:22 is 24361305.66168641 s in the future
 1145 21:26:59.868433  tar: ./net/tcp_ao/connect-deny_ipv4: time stamp 2024-11-03 20:51:14 is 24361297.471503702 s in the future
 1146 21:27:00.091736  tar: ./net/tcp_ao/key-management_ipv4: time stamp 2024-11-03 20:51:15 is 24361298.250448368 s in the future
 1147 21:27:00.287385  tar: ./net/tcp_ao/restore_ipv6: time stamp 2024-11-03 20:51:20 is 24361303.050626868 s in the future
 1148 21:27:00.483117  tar: ./net/tcp_ao/seq-ext_ipv6: time stamp 2024-11-03 20:51:21 is 24361303.854911327 s in the future
 1149 21:27:00.675672  tar: ./net/tcp_ao/setsockopt-closed_ipv4: time stamp 2024-11-03 20:51:17 is 24361299.66307866 s in the future
 1150 21:27:00.859706  tar: ./net/tcp_ao/connect_ipv6: time stamp 2024-11-03 20:51:18 is 24361300.477686618 s in the future
 1151 21:27:01.062934  tar: ./net/tcp_ao/rst_ipv6: time stamp 2024-11-03 20:51:21 is 24361303.275151201 s in the future
 1152 21:27:01.266966  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-11-03 20:51:16 is 24361298.070783576 s in the future
 1153 21:27:01.475437  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-11-03 20:51:14 is 24361295.862462993 s in the future
 1154 21:27:01.678564  tar: ./net/tcp_ao/setsockopt-closed_ipv6: time stamp 2024-11-03 20:51:22 is 24361303.660057951 s in the future
 1155 21:27:01.827866  tar: ./net/tcp_ao/settings: time stamp 2024-10-27 19:28:30 is 23751531.510177576 s in the future
 1156 21:27:02.045575  tar: ./net/tcp_ao/icmps-accept_ipv6: time stamp 2024-11-03 20:51:19 is 24361300.293406118 s in the future
 1157 21:27:02.252029  tar: ./net/tcp_ao/unsigned-md5_ipv4: time stamp 2024-11-03 20:51:18 is 24361299.08712666 s in the future
 1158 21:27:02.454287  tar: ./net/tcp_ao/key-management_ipv6: time stamp 2024-11-03 20:51:20 is 24361300.885150701 s in the future
 1159 21:27:02.524267  tar: ./net/tcp_ao: time stamp 2024-11-03 20:52:06 is 24361346.811747743 s in the future
 1160 21:27:02.688476  tar: ./net/packetdrill/tcp_inq_server.pkt: time stamp 2024-10-27 19:28:30 is 23751530.651285785 s in the future
 1161 21:27:02.821539  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-5pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751530.520355785 s in the future
 1162 21:27:02.936240  tar: ./net/packetdrill/tcp_zerocopy_client.pkt: time stamp 2024-10-27 19:28:30 is 23751530.403549785 s in the future
 1163 21:27:03.055366  tar: ./net/packetdrill/tcp_zerocopy_fastopen-client.pkt: time stamp 2024-10-27 19:28:30 is 23751530.285354368 s in the future
 1164 21:27:03.202536  tar: ./net/packetdrill/defaults.sh: time stamp 2024-10-27 19:28:30 is 23751530.135172076 s in the future
 1165 21:27:03.331308  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt-send-6pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751530.01029366 s in the future
 1166 21:27:03.462924  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-4pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751529.878208493 s in the future
 1167 21:27:03.591484  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-10-27 19:28:30 is 23751529.747855868 s in the future
 1168 21:27:03.729715  tar: ./net/packetdrill/tcp_md5_md5-only-on-client-ack.pkt: time stamp 2024-10-27 19:28:30 is 23751529.611565909 s in the future
 1169 21:27:03.865873  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited-9-packets-out.pkt: time stamp 2024-10-27 19:28:30 is 23751529.476309159 s in the future
 1170 21:27:03.988373  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751529.352949576 s in the future
 1171 21:27:04.121935  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-10-27 19:28:30 is 23751529.217706951 s in the future
 1172 21:27:04.259497  tar: ./net/packetdrill/config: time stamp 2024-10-27 19:28:30 is 23751529.077748826 s in the future
 1173 21:27:04.391175  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-1pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751528.950644951 s in the future
 1174 21:27:04.513346  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-10-27 19:28:30 is 23751528.827558993 s in the future
 1175 21:27:04.641043  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-win-update.pkt: time stamp 2024-10-27 19:28:30 is 23751528.700561743 s in the future
 1176 21:27:04.766606  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-2pkt.pkt: time stamp 2024-10-27 19:28:30 is 23751528.574289493 s in the future
 1177 21:27:04.881108  tar: ./net/packetdrill/tcp_zerocopy_closed.pkt: time stamp 2024-10-27 19:28:30 is 23751528.458669451 s in the future
 1178 21:27:04.994764  tar: ./net/packetdrill/set_sysctls.py: time stamp 2024-10-27 19:28:30 is 23751528.343927409 s in the future
 1179 21:27:05.139192  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-idle.pkt: time stamp 2024-10-27 19:28:30 is 23751528.202131951 s in the future
 1180 21:27:05.264471  tar: ./net/packetdrill/ksft_runner.sh: time stamp 2024-10-27 19:28:30 is 23751528.073981534 s in the future
 1181 21:27:05.392192  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited.pkt: time stamp 2024-10-27 19:28:30 is 23751527.949608909 s in the future
 1182 21:27:05.510043  tar: ./net/packetdrill/tcp_zerocopy_small.pkt: time stamp 2024-10-27 19:28:30 is 23751527.829428118 s in the future
 1183 21:27:05.654197  tar: ./net/packetdrill/tcp_zerocopy_batch.pkt: time stamp 2024-10-27 19:28:30 is 23751527.685034909 s in the future
 1184 21:27:05.774286  tar: ./net/packetdrill/tcp_inq_client.pkt: time stamp 2024-10-27 19:28:30 is 23751527.565148909 s in the future
 1185 21:27:05.890943  tar: ./net/packetdrill/tcp_zerocopy_epoll_edge.pkt: time stamp 2024-10-27 19:28:30 is 23751527.449084201 s in the future
 1186 21:27:06.014502  tar: ./net/packetdrill/tcp_zerocopy_epoll_exclusive.pkt: time stamp 2024-10-27 19:28:30 is 23751527.326420993 s in the future
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 1276 21:27:18.122325  tar: ./net/forwarding/router_nh.sh: time stamp 2024-10-27 19:28:30 is 23751515.215393074 s in the future
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 1283 21:27:19.087945  tar: ./net/forwarding/bridge_locked_port.sh: time stamp 2024-10-27 19:28:30 is 23751514.250558741 s in the future
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 2020 21:28:55.502611  tar: ./filesystems/devpts_pts: time stamp 2024-11-03 20:50:33 is 24361140.829223479 s in the future
 2021 21:28:55.663561  tar: ./filesystems/overlayfs/dev_in_maps: time stamp 2024-11-03 20:50:35 is 24361142.669352813 s in the future
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 2023 21:28:55.887611  tar: ./filesystems/statmount/statmount_test: time stamp 2024-11-03 20:50:35 is 24361142.445591229 s in the future
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 2055 21:29:00.762388  tar: ./openat2: time stamp 2024-11-03 20:52:07 is 24361229.567167521 s in the future
 2056 21:29:00.914598  tar: ./pstore/pstore_tests: time stamp 2024-10-27 19:28:30 is 23751412.416608979 s in the future
 2057 21:29:01.022471  tar: ./pstore/config: time stamp 2024-10-27 19:28:30 is 23751412.308583104 s in the future
 2058 21:29:01.131869  tar: ./pstore/pstore_crash_test: time stamp 2024-10-27 19:28:30 is 23751412.200037979 s in the future
 2059 21:29:01.240057  tar: ./pstore/pstore_post_reboot_tests: time stamp 2024-10-27 19:28:30 is 23751412.091633104 s in the future
 2060 21:29:01.373586  tar: ./pstore/common_tests: time stamp 2024-10-27 19:28:30 is 23751411.958092312 s in the future
 2061 21:29:01.421186  tar: ./pstore: time stamp 2024-11-03 20:52:07 is 24361228.907984395 s in the future
 2062 21:29:01.583317  tar: ./vDSO/vdso_test_gettimeofday: time stamp 2024-11-03 20:51:45 is 24361206.749630229 s in the future
 2063 21:29:01.690338  tar: ./vDSO/vdso_test_getcpu: time stamp 2024-11-03 20:51:45 is 24361206.641200479 s in the future
 2064 21:29:01.824822  tar: ./vDSO/vdso_test_clock_getres: time stamp 2024-11-03 20:51:45 is 24361206.507609312 s in the future
 2065 21:29:01.965391  tar: ./vDSO/vdso_test_correctness: time stamp 2024-11-03 20:51:45 is 24361206.365884979 s in the future
 2066 21:29:02.081775  tar: ./vDSO/vdso_test_abi: time stamp 2024-11-03 20:51:45 is 24361206.249095354 s in the future
 2067 21:29:02.233133  tar: ./vDSO/vdso_test_getrandom: time stamp 2024-11-03 20:51:45 is 24361206.098924062 s in the future
 2068 21:29:02.373622  tar: ./vDSO/vdso_test_chacha: time stamp 2024-11-03 20:51:46 is 24361206.957300062 s in the future
 2069 21:29:02.422437  tar: ./vDSO: time stamp 2024-11-03 20:52:10 is 24361230.90722152 s in the future
 2070 21:29:02.573650  tar: ./mqueue/mq_open_tests: time stamp 2024-11-03 20:50:59 is 24361159.757206229 s in the future
 2071 21:29:02.716442  tar: ./mqueue/mq_perf_tests: time stamp 2024-11-03 20:50:59 is 24361159.615108979 s in the future
 2072 21:29:02.781097  tar: ./mqueue: time stamp 2024-11-03 20:52:05 is 24361225.549040187 s in the future
 2073 21:29:02.923820  tar: ./sync/sync_test: time stamp 2024-11-03 20:51:39 is 24361199.406946645 s in the future
 2074 21:29:03.041210  tar: ./sync/config: time stamp 2024-10-27 19:28:30 is 23751410.289508145 s in the future
 2075 21:29:03.090010  tar: ./sync: time stamp 2024-11-03 20:52:09 is 24361229.239833104 s in the future
 2076 21:29:03.257204  tar: ./ipc/msgque: time stamp 2024-11-03 20:50:42 is 24361142.07309602 s in the future
 2077 21:29:03.390637  tar: ./ipc/config: time stamp 2024-10-27 19:28:30 is 23751409.93998352 s in the future
 2078 21:29:03.440290  tar: ./ipc: time stamp 2024-11-03 20:52:02 is 24361221.88954802 s in the future
 2079 21:29:03.783917  tar: ./tdx/tdx_guest_test: time stamp 2024-11-03 20:51:40 is 24361199.547761854 s in the future
 2080 21:29:03.891735  tar: ./tdx/config: time stamp 2024-10-27 19:28:30 is 23751409.439204145 s in the future
 2081 21:29:03.940353  tar: ./tdx: time stamp 2024-11-03 20:52:09 is 24361228.389125478 s in the future
 2082 21:29:04.075863  tar: ./tpm2/test_async.sh: time stamp 2024-10-27 19:28:30 is 23751409.25572627 s in the future
 2083 21:29:04.224946  tar: ./tpm2/tpm2.py: time stamp 2024-10-27 19:28:30 is 23751409.105474812 s in the future
 2084 21:29:04.350946  tar: ./tpm2/tpm2_tests.py: time stamp 2024-10-27 19:28:30 is 23751408.980069562 s in the future
 2085 21:29:04.475818  tar: ./tpm2/test_smoke.sh: time stamp 2024-10-27 19:28:30 is 23751408.85501327 s in the future
 2086 21:29:04.583665  tar: ./tpm2/settings: time stamp 2024-10-27 19:28:30 is 23751408.747182562 s in the future
 2087 21:29:04.717174  tar: ./tpm2/test_space.sh: time stamp 2024-10-27 19:28:30 is 23751408.613476437 s in the future
 2088 21:29:04.767059  tar: ./tpm2: time stamp 2024-11-03 20:52:10 is 24361228.563018145 s in the future
 2089 21:29:04.918306  tar: ./ptrace/vmaccess: time stamp 2024-11-03 20:51:27 is 24361185.412745062 s in the future
 2090 21:29:05.101210  tar: ./ptrace/get_set_sud: time stamp 2024-11-03 20:51:27 is 24361185.229278145 s in the future
 2091 21:29:05.234645  tar: ./ptrace/peeksiginfo: time stamp 2024-11-03 20:51:27 is 24361185.096335228 s in the future
 2092 21:29:05.376335  tar: ./ptrace/get_syscall_info: time stamp 2024-11-03 20:51:26 is 24361183.954585228 s in the future
 2093 21:29:05.433553  tar: ./ptrace: time stamp 2024-11-03 20:52:07 is 24361224.896421728 s in the future
 2094 21:29:05.587216  tar: ./syscall_user_dispatch/sud_benchmark: time stamp 2024-11-03 20:51:39 is 24361196.745612353 s in the future
 2095 21:29:05.702763  tar: ./syscall_user_dispatch/config: time stamp 2024-10-27 19:28:30 is 23751407.629001478 s in the future
 2096 21:29:05.854277  tar: ./syscall_user_dispatch/sud_test: time stamp 2024-11-03 20:51:39 is 24361196.478673645 s in the future
 2097 21:29:05.903191  tar: ./syscall_user_dispatch: time stamp 2024-11-03 20:52:09 is 24361226.42875927 s in the future
 2098 21:29:06.119931  tar: ./resctrl/resctrl_tests: time stamp 2024-11-03 20:51:32 is 24361189.211714853 s in the future
 2099 21:29:06.252263  tar: ./resctrl/config: time stamp 2024-10-27 19:28:30 is 23751407.079465978 s in the future
 2100 21:29:06.377126  tar: ./resctrl/settings: time stamp 2024-10-27 19:28:30 is 23751406.953398603 s in the future
 2101 21:29:06.434175  tar: ./resctrl: time stamp 2024-11-03 20:52:07 is 24361223.894893478 s in the future
 2102 21:29:06.562262  tar: ./proc/setns-sysvipc: time stamp 2024-11-03 20:51:26 is 24361182.769629728 s in the future
 2103 21:29:06.743031  tar: ./proc/read: time stamp 2024-11-03 20:51:26 is 24361182.586365853 s in the future
 2104 21:29:06.911239  tar: ./proc/proc-subset-pid: time stamp 2024-11-03 20:51:25 is 24361181.41947302 s in the future
 2105 21:29:07.036233  tar: ./proc/proc-loadavg-001: time stamp 2024-11-03 20:51:25 is 24361181.29451152 s in the future
 2106 21:29:07.162261  tar: ./proc/proc-self-map-files-002: time stamp 2024-11-03 20:51:25 is 24361181.16926102 s in the future
 2107 21:29:07.287223  tar: ./proc/proc-empty-vm: time stamp 2024-11-03 20:51:25 is 24361181.044020061 s in the future
 2108 21:29:07.412114  tar: ./proc/proc-tid0: time stamp 2024-11-03 20:51:25 is 24361180.919142145 s in the future
 2109 21:29:07.553885  tar: ./proc/proc-pid-vm: time stamp 2024-11-03 20:51:25 is 24361180.777142936 s in the future
 2110 21:29:07.671443  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-11-03 20:51:25 is 24361180.66029802 s in the future
 2111 21:29:07.804890  tar: ./proc/proc-2-is-kthread: time stamp 2024-11-03 20:51:25 is 24361180.52681352 s in the future
 2112 21:29:07.929842  tar: ./proc/proc-uptime-001: time stamp 2024-11-03 20:51:26 is 24361181.401938645 s in the future
 2113 21:29:08.063257  tar: ./proc/proc-uptime-002: time stamp 2024-11-03 20:51:26 is 24361181.268739478 s in the future
 2114 21:29:08.179632  tar: ./proc/proc-self-syscall: time stamp 2024-11-03 20:51:25 is 24361180.151397728 s in the future
 2115 21:29:08.305584  tar: ./proc/proc-multiple-procfs: time stamp 2024-11-03 20:51:26 is 24361181.026282228 s in the future
 2116 21:29:08.421036  tar: ./proc/config: time stamp 2024-10-27 19:28:30 is 23751404.90993752 s in the future
 2117 21:29:08.554185  tar: ./proc/thread-self: time stamp 2024-11-03 20:51:26 is 24361180.77634452 s in the future
 2118 21:29:08.680025  tar: ./proc/setns-dcache: time stamp 2024-11-03 20:51:26 is 24361180.650875561 s in the future
 2119 21:29:08.797545  tar: ./proc/proc-self-map-files-001: time stamp 2024-11-03 20:51:25 is 24361179.53407827 s in the future
 2120 21:29:08.930992  tar: ./proc/proc-self-wchan: time stamp 2024-11-03 20:51:25 is 24361179.400863478 s in the future
 2121 21:29:09.063368  tar: ./proc/proc-fsconfig-hidepid: time stamp 2024-11-03 20:51:26 is 24361180.267714811 s in the future
 2122 21:29:09.180955  tar: ./proc/fd-002-posix-eq: time stamp 2024-11-03 20:51:24 is 24361178.150396728 s in the future
 2123 21:29:09.307159  tar: ./proc/fd-001-lookup: time stamp 2024-11-03 20:51:24 is 24361178.025231895 s in the future
 2124 21:29:09.430997  tar: ./proc/fd-003-kthread: time stamp 2024-11-03 20:51:25 is 24361178.900391561 s in the future
 2125 21:29:09.554754  tar: ./proc/self: time stamp 2024-11-03 20:51:26 is 24361179.775324061 s in the future
 2126 21:29:09.603422  tar: ./proc: time stamp 2024-11-03 20:52:07 is 24361220.725570394 s in the future
 2127 21:29:09.781136  tar: ./core/close_range_test: time stamp 2024-11-03 20:50:13 is 24361106.549823978 s in the future
 2128 21:29:09.912455  tar: ./core/unshare_test: time stamp 2024-11-03 20:50:14 is 24361107.417960728 s in the future
 2129 21:29:09.970613  tar: ./core: time stamp 2024-11-03 20:51:58 is 24361211.358557603 s in the future
 2130 21:29:10.092194  tar: ./run_kselftest.sh: time stamp 2024-11-03 20:51:58 is 24361211.240205019 s in the future
 2131 21:29:10.331137  tar: ./futex/functional/futex_wait: time stamp 2024-11-03 20:50:37 is 24361130.000431478 s in the future
 2132 21:29:10.439266  tar: ./futex/functional/run.sh: time stamp 2024-10-27 19:28:30 is 23751402.892529769 s in the future
 2133 21:29:10.566653  tar: ./futex/functional/futex_wait_private_mapped_file: time stamp 2024-11-03 20:50:37 is 24361129.766334644 s in the future
 2134 21:29:10.699077  tar: ./futex/functional/futex_wait_wouldblock: time stamp 2024-11-03 20:50:36 is 24361128.633409103 s in the future
 2135 21:29:10.832483  tar: ./futex/functional/futex_wait_timeout: time stamp 2024-11-03 20:50:36 is 24361128.499075436 s in the future
 2136 21:29:10.966077  tar: ./futex/functional/futex_wait_uninitialized_heap: time stamp 2024-11-03 20:50:37 is 24361129.366592269 s in the future
 2137 21:29:11.091041  tar: ./futex/functional/futex_requeue: time stamp 2024-11-03 20:50:37 is 24361129.240458019 s in the future
 2138 21:29:11.234178  tar: ./futex/functional/futex_requeue_pi_signal_restart: time stamp 2024-11-03 20:50:36 is 24361128.098981144 s in the future
 2139 21:29:11.366527  tar: ./futex/functional/futex_waitv: time stamp 2024-11-03 20:50:37 is 24361128.965241186 s in the future
 2140 21:29:11.501119  tar: ./futex/functional/futex_requeue_pi_mismatched_ops: time stamp 2024-11-03 20:50:36 is 24361127.831506936 s in the future
 2141 21:29:11.633012  tar: ./futex/functional/futex_requeue_pi: time stamp 2024-11-03 20:50:36 is 24361127.698098561 s in the future
 2142 21:29:11.712872  tar: ./futex/functional: time stamp 2024-11-03 20:52:02 is 24361213.617483769 s in the future
 2143 21:29:11.830218  tar: ./futex/run.sh: time stamp 2024-11-03 20:52:02 is 24361213.499262519 s in the future
 2144 21:29:11.899070  tar: ./futex: time stamp 2024-11-03 20:52:02 is 24361213.431228478 s in the future
 2145 21:29:11.947801  tar: .: time stamp 2024-11-03 20:52:12 is 24361223.381240478 s in the future
 2146 21:29:12.220051  skiplist:
 2147 21:29:12.220428  ========================================
 2148 21:29:12.225521  ========================================
 2149 21:29:12.534420  dt:test_unprobed_devices.sh
 2150 21:29:12.662892  ============== Tests to run ===============
 2151 21:29:12.679966  dt:test_unprobed_devices.sh
 2152 21:29:12.683101  ===========End Tests to run ===============
 2153 21:29:12.726711  shardfile-dt pass
 2154 21:29:13.049504  <12>[  208.956904] kselftest: Running tests in dt
 2155 21:29:13.080438  TAP version 13
 2156 21:29:13.103016  1..1
 2157 21:29:13.155907  # timeout set to 45
 2158 21:29:13.156288  # selftests: dt: test_unprobed_devices.sh
 2159 21:29:14.062768  # TAP version 13
 2160 21:29:39.321803  # 1..257
 2161 21:29:39.524663  # ok 1 / # SKIP
 2162 21:29:39.546255  # ok 2 /clk_mcasp0
 2163 21:29:39.620770  # ok 3 /clk_mcasp0_fixed # SKIP
 2164 21:29:39.694269  # ok 4 /cpus/cpu@0 # SKIP
 2165 21:29:39.769117  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2166 21:29:39.789776  # ok 6 /fixedregulator0
 2167 21:29:39.810387  # ok 7 /leds
 2168 21:29:39.837378  # ok 8 /ocp
 2169 21:29:39.855882  # ok 9 /ocp/interconnect@44c00000
 2170 21:29:39.880831  # ok 10 /ocp/interconnect@44c00000/segment@0
 2171 21:29:39.909431  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2172 21:29:39.930606  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2173 21:29:40.006025  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2174 21:29:40.025944  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2175 21:29:40.050699  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2176 21:29:40.160703  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2177 21:29:40.237217  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2178 21:29:40.310470  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2179 21:29:40.384012  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2180 21:29:40.458648  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2181 21:29:40.531869  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2182 21:29:40.607572  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2183 21:29:40.681015  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2184 21:29:40.755702  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2185 21:29:40.829766  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2186 21:29:40.903043  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2187 21:29:40.979797  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2188 21:29:41.054424  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2189 21:29:41.130435  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2190 21:29:41.202785  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2191 21:29:41.283021  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2192 21:29:41.353164  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2193 21:29:41.434507  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2194 21:29:41.503643  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2195 21:29:41.582673  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2196 21:29:41.657288  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2197 21:29:41.734516  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2198 21:29:41.807799  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2199 21:29:41.884721  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2200 21:29:41.958471  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2201 21:29:42.033884  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2202 21:29:42.108688  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2203 21:29:42.185521  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2204 21:29:42.259316  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2205 21:29:42.334861  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2206 21:29:42.408480  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2207 21:29:42.485152  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2208 21:29:42.558681  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2209 21:29:42.635353  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2210 21:29:42.708922  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2211 21:29:42.781507  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2212 21:29:42.856058  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2213 21:29:42.931522  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2214 21:29:43.006078  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2215 21:29:43.081423  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2216 21:29:43.156205  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2217 21:29:43.230977  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2218 21:29:43.304824  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2219 21:29:43.379857  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2220 21:29:43.461641  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2221 21:29:43.529920  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2222 21:29:43.605771  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2223 21:29:43.683805  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2224 21:29:43.758456  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2225 21:29:43.830640  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2226 21:29:43.905405  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2227 21:29:43.985553  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2228 21:29:44.058058  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2229 21:29:44.130127  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2230 21:29:44.205797  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2231 21:29:44.285861  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2232 21:29:44.358439  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2233 21:29:44.430700  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2234 21:29:44.505285  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2235 21:29:44.580700  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2236 21:29:44.657819  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2237 21:29:44.732659  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2238 21:29:44.806229  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2239 21:29:44.881769  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2240 21:29:44.955565  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2241 21:29:45.029951  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2242 21:29:45.105635  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2243 21:29:45.179932  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2244 21:29:45.254413  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2245 21:29:45.334105  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2246 21:29:45.407511  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2247 21:29:45.479660  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2248 21:29:45.555384  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2249 21:29:45.632082  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2250 21:29:45.707045  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2251 21:29:45.780712  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2252 21:29:45.856748  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2253 21:29:45.935705  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2254 21:29:46.009448  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2255 21:29:46.028514  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2256 21:29:46.052099  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2257 21:29:46.081001  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2258 21:29:46.101461  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2259 21:29:46.127401  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2260 21:29:46.150942  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2261 21:29:46.174773  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2262 21:29:46.198246  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2263 21:29:46.307248  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2264 21:29:46.334159  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2265 21:29:46.363323  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2266 21:29:46.385906  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2267 21:29:46.494070  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2268 21:29:46.571214  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2269 21:29:46.645946  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2270 21:29:46.722543  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2271 21:29:46.797488  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2272 21:29:46.871948  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2273 21:29:46.946800  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2274 21:29:47.022672  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2275 21:29:47.196868  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2276 21:29:47.209705  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2277 21:29:47.258633  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2278 21:29:47.329159  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2279 21:29:47.402712  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2280 21:29:47.478933  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2281 21:29:47.553947  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2282 21:29:47.628978  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2283 21:29:47.655167  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2284 21:29:47.724361  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2285 21:29:47.796692  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2286 21:29:47.870971  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2287 21:29:47.893567  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2288 21:29:47.967686  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2289 21:29:47.990147  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2290 21:29:48.066684  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2291 21:29:48.086833  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2292 21:29:48.115765  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2293 21:29:48.138522  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2294 21:29:48.159830  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2295 21:29:48.183524  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2296 21:29:48.208081  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2297 21:29:48.233783  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 2298 21:29:48.313934  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 2299 21:29:48.332473  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2300 21:29:48.359574  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2301 21:29:48.431036  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2302 21:29:48.504647  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2303 21:29:48.525998  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2304 21:29:48.629353  # not ok 144 /ocp/interconnect@47c00000
 2305 21:29:48.704407  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2306 21:29:48.729637  # ok 146 /ocp/interconnect@48000000
 2307 21:29:48.752994  # ok 147 /ocp/interconnect@48000000/segment@0
 2308 21:29:48.776819  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2309 21:29:48.797926  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2310 21:29:48.822709  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2311 21:29:48.850398  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2312 21:29:48.873903  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2313 21:29:48.899514  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2314 21:29:48.922061  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2315 21:29:48.995047  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2316 21:29:49.070653  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2317 21:29:49.089949  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2318 21:29:49.114535  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2319 21:29:49.136721  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2320 21:29:49.161237  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2321 21:29:49.184760  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2322 21:29:49.209394  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2323 21:29:49.232831  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2324 21:29:49.260849  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2325 21:29:49.285417  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2326 21:29:49.307175  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2327 21:29:49.329600  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2328 21:29:49.353236  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2329 21:29:49.380982  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2330 21:29:49.405678  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2331 21:29:49.429284  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2332 21:29:49.453962  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2333 21:29:49.474706  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2334 21:29:49.497959  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2335 21:29:49.517787  # ok 175 /ocp/interconnect@48000000/segment@100000
 2336 21:29:49.545611  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2337 21:29:49.569251  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2338 21:29:49.643822  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 2339 21:29:49.721120  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 2340 21:29:49.791975  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 2341 21:29:49.867807  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 2342 21:29:49.946647  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 2343 21:29:50.019308  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 2344 21:29:50.096038  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 2345 21:29:50.173813  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 2346 21:29:50.194471  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2347 21:29:50.214829  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2348 21:29:50.238210  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2349 21:29:50.264940  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2350 21:29:50.291677  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2351 21:29:50.316392  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2352 21:29:50.335831  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2353 21:29:50.361601  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2354 21:29:50.384059  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2355 21:29:50.408575  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2356 21:29:50.432084  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2357 21:29:50.460961  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2358 21:29:50.482004  # ok 198 /ocp/interconnect@48000000/segment@200000
 2359 21:29:50.503188  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2360 21:29:50.578009  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2361 21:29:50.603450  # ok 201 /ocp/interconnect@48000000/segment@300000
 2362 21:29:50.627245  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2363 21:29:50.648473  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2364 21:29:50.674142  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2365 21:29:50.697676  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2366 21:29:50.720600  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2367 21:29:50.746941  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2368 21:29:50.825360  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2369 21:29:50.842214  # ok 209 /ocp/interconnect@4a000000
 2370 21:29:50.869676  # ok 210 /ocp/interconnect@4a000000/segment@0
 2371 21:29:50.895516  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2372 21:29:50.919177  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2373 21:29:50.941596  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2374 21:29:50.962938  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2375 21:29:51.039178  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2376 21:29:51.152721  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2377 21:29:51.228380  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2378 21:29:51.333482  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2379 21:29:51.405725  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2380 21:29:51.484410  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2381 21:29:51.588527  # not ok 221 /ocp/interconnect@4b140000
 2382 21:29:51.663542  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2383 21:29:51.737671  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2384 21:29:51.755387  # ok 224 /ocp/target-module@40300000
 2385 21:29:51.778610  # ok 225 /ocp/target-module@40300000/sram@0
 2386 21:29:51.860325  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2387 21:29:51.935509  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2388 21:29:51.951063  # ok 228 /ocp/target-module@47400000
 2389 21:29:51.977686  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2390 21:29:51.998773  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2391 21:29:52.026504  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2392 21:29:52.050871  # ok 232 /ocp/target-module@47400000/usb@1400
 2393 21:29:52.073254  # ok 233 /ocp/target-module@47400000/usb@1800
 2394 21:29:52.097741  # ok 234 /ocp/target-module@47810000
 2395 21:29:52.116682  # ok 235 /ocp/target-module@49000000
 2396 21:29:52.215190  # ok 236 /ocp/target-module@49000000/dma@0
 2397 21:29:52.220120  # ok 237 /ocp/target-module@49800000
 2398 21:29:52.220498  # ok 238 /ocp/target-module@49800000/dma@0
 2399 21:29:52.228621  # ok 239 /ocp/target-module@49900000
 2400 21:29:52.239613  # ok 240 /ocp/target-module@49900000/dma@0
 2401 21:29:52.257104  # ok 241 /ocp/target-module@49a00000
 2402 21:29:52.286767  # ok 242 /ocp/target-module@49a00000/dma@0
 2403 21:29:52.309113  # ok 243 /ocp/target-module@4c000000
 2404 21:29:52.381467  # not ok 244 /ocp/target-module@4c000000/emif@0
 2405 21:29:52.407783  # ok 245 /ocp/target-module@50000000
 2406 21:29:52.429717  # ok 246 /ocp/target-module@53100000
 2407 21:29:52.501444  # not ok 247 /ocp/target-module@53100000/sham@0
 2408 21:29:52.523569  # ok 248 /ocp/target-module@53500000
 2409 21:29:52.602854  # not ok 249 /ocp/target-module@53500000/aes@0
 2410 21:29:52.620456  # ok 250 /ocp/target-module@56000000
 2411 21:29:52.733507  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2412 21:29:52.801803  # ok 252 /opp-table # SKIP
 2413 21:29:52.878572  # ok 253 /soc # SKIP
 2414 21:29:52.894763  # ok 254 /sound
 2415 21:29:52.920698  # ok 255 /target-module@4b000000
 2416 21:29:52.951601  # ok 256 /target-module@4b000000/target-module@140000
 2417 21:29:52.967677  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2418 21:29:52.975743  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2419 21:29:52.983895  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2420 21:29:55.535721  dt_test_unprobed_devices_sh_ skip
 2421 21:29:55.540409  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2422 21:29:55.546592  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2423 21:29:55.546964  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2424 21:29:55.555205  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2425 21:29:55.555577  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2426 21:29:55.561279  dt_test_unprobed_devices_sh_leds pass
 2427 21:29:55.566147  dt_test_unprobed_devices_sh_ocp pass
 2428 21:29:55.570935  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2429 21:29:55.575954  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2430 21:29:55.582015  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2431 21:29:55.591702  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2432 21:29:55.596708  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2433 21:29:55.607697  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2434 21:29:55.612494  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2435 21:29:55.623648  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2436 21:29:55.633258  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2437 21:29:55.644515  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2438 21:29:55.649282  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2439 21:29:55.659101  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2440 21:29:55.670097  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2441 21:29:55.680130  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2442 21:29:55.691199  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2443 21:29:55.701040  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2444 21:29:55.712006  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2445 21:29:55.721716  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2446 21:29:55.732761  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2447 21:29:55.742652  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2448 21:29:55.752441  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2449 21:29:55.763412  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2450 21:29:55.774643  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2451 21:29:55.779327  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2452 21:29:55.790511  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2453 21:29:55.800118  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2454 21:29:55.811279  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2455 21:29:55.820854  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2456 21:29:55.832097  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2457 21:29:55.841718  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2458 21:29:55.852893  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2459 21:29:55.862550  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2460 21:29:55.873616  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2461 21:29:55.883447  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2462 21:29:55.894644  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2463 21:29:55.909225  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2464 21:29:55.920522  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2465 21:29:55.930156  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2466 21:29:55.941168  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2467 21:29:55.950992  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2468 21:29:55.961965  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2469 21:29:55.971764  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2470 21:29:55.982754  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2471 21:29:55.998646  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2472 21:29:56.008306  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2473 21:29:56.019546  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2474 21:29:56.029167  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2475 21:29:56.040349  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2476 21:29:56.054994  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2477 21:29:56.061158  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2478 21:29:56.070838  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2479 21:29:56.081961  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2480 21:29:56.096635  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2481 21:29:56.102760  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2482 21:29:56.117357  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2483 21:29:56.128635  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2484 21:29:56.138275  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2485 21:29:56.149508  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2486 21:29:56.159183  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2487 21:29:56.170210  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2488 21:29:56.179930  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2489 21:29:56.190935  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2490 21:29:56.200763  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2491 21:29:56.211766  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2492 21:29:56.227642  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2493 21:29:56.232570  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2494 21:29:56.248649  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2495 21:29:56.258177  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2496 21:29:56.269501  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2497 21:29:56.279077  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2498 21:29:56.290197  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2499 21:29:56.299831  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2500 21:29:56.310958  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2501 21:29:56.320641  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2502 21:29:56.331766  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2503 21:29:56.341622  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2504 21:29:56.352761  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2505 21:29:56.362434  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2506 21:29:56.372442  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2507 21:29:56.383309  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2508 21:29:56.394422  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2509 21:29:56.409197  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2510 21:29:56.415357  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2511 21:29:56.429954  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2512 21:29:56.441011  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2513 21:29:56.450761  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2514 21:29:56.461731  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2515 21:29:56.471637  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2516 21:29:56.481440  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2517 21:29:56.492422  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2518 21:29:56.498515  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2519 21:29:56.508146  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2520 21:29:56.519233  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2521 21:29:56.524348  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2522 21:29:56.534134  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2523 21:29:56.545186  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2524 21:29:56.554972  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2525 21:29:56.565956  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2526 21:29:56.575761  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2527 21:29:56.586882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2528 21:29:56.596642  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2529 21:29:56.607638  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2530 21:29:56.622429  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2531 21:29:56.633256  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2532 21:29:56.644520  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2533 21:29:56.659200  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2534 21:29:56.670193  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2535 21:29:56.680015  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2536 21:29:56.691072  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2537 21:29:56.707016  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2538 21:29:56.716566  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2539 21:29:56.727744  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2540 21:29:56.742418  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2541 21:29:56.758503  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2542 21:29:56.769521  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2543 21:29:56.779196  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2544 21:29:56.785398  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2545 21:29:56.794964  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2546 21:29:56.806133  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2547 21:29:56.811086  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2548 21:29:56.820876  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2549 21:29:56.831877  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2550 21:29:56.836652  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2551 21:29:56.847755  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2552 21:29:56.852607  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2553 21:29:56.862500  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2554 21:29:56.873470  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2555 21:29:56.883194  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2556 21:29:56.889342  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 2557 21:29:56.904018  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 2558 21:29:56.915060  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2559 21:29:56.919838  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2560 21:29:56.931001  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2561 21:29:56.940753  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2562 21:29:56.951852  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2563 21:29:56.956755  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2564 21:29:56.961528  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2565 21:29:56.966545  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2566 21:29:56.972632  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2567 21:29:56.982305  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2568 21:29:56.987334  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2569 21:29:56.998271  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2570 21:29:57.003205  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2571 21:29:57.014329  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2572 21:29:57.019207  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2573 21:29:57.028938  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2574 21:29:57.035147  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2575 21:29:57.044736  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2576 21:29:57.055964  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2577 21:29:57.060871  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2578 21:29:57.070601  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2579 21:29:57.076720  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2580 21:29:57.086382  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2581 21:29:57.097505  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2582 21:29:57.102384  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2583 21:29:57.112389  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2584 21:29:57.118514  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2585 21:29:57.128058  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2586 21:29:57.133031  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2587 21:29:57.144047  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2588 21:29:57.153831  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2589 21:29:57.160009  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2590 21:29:57.169728  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2591 21:29:57.174764  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2592 21:29:57.185742  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2593 21:29:57.195628  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2594 21:29:57.201610  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2595 21:29:57.206566  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2596 21:29:57.216331  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2597 21:29:57.227349  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 2598 21:29:57.237076  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 2599 21:29:57.248091  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 2600 21:29:57.264015  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 2601 21:29:57.268878  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 2602 21:29:57.284878  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 2603 21:29:57.289729  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 2604 21:29:57.305607  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 2605 21:29:57.310636  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2606 21:29:57.320339  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2607 21:29:57.331355  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2608 21:29:57.336046  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2609 21:29:57.347350  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2610 21:29:57.352152  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2611 21:29:57.361961  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2612 21:29:57.372944  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2613 21:29:57.377719  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2614 21:29:57.388893  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2615 21:29:57.393724  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2616 21:29:57.403622  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2617 21:29:57.413423  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2618 21:29:57.419413  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2619 21:29:57.430529  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2620 21:29:57.435507  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2621 21:29:57.445188  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2622 21:29:57.451369  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2623 21:29:57.460946  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2624 21:29:57.465958  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2625 21:29:57.476942  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2626 21:29:57.486753  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2627 21:29:57.492899  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2628 21:29:57.497729  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2629 21:29:57.507632  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2630 21:29:57.513607  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2631 21:29:57.523411  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2632 21:29:57.533435  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2633 21:29:57.539516  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2634 21:29:57.549288  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2635 21:29:57.560263  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2636 21:29:57.570198  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2637 21:29:57.576325  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2638 21:29:57.585930  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2639 21:29:57.597096  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2640 21:29:57.601955  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2641 21:29:57.606716  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2642 21:29:57.611762  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2643 21:29:57.617803  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2644 21:29:57.622865  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2645 21:29:57.632599  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2646 21:29:57.638760  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2647 21:29:57.643616  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2648 21:29:57.653494  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2649 21:29:57.659543  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2650 21:29:57.664515  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2651 21:29:57.674188  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2652 21:29:57.680295  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2653 21:29:57.685131  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2654 21:29:57.689906  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2655 21:29:57.694972  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2656 21:29:57.701123  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2657 21:29:57.705944  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2658 21:29:57.710748  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2659 21:29:57.715757  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2660 21:29:57.721805  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2661 21:29:57.726818  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2662 21:29:57.731565  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2663 21:29:57.737820  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2664 21:29:57.743891  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2665 21:29:57.748879  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2666 21:29:57.754959  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2667 21:29:57.759894  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2668 21:29:57.766064  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2669 21:29:57.770910  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2670 21:29:57.780711  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2671 21:29:57.781122  dt_test_unprobed_devices_sh_opp-table skip
 2672 21:29:57.786881  dt_test_unprobed_devices_sh_soc skip
 2673 21:29:57.791740  dt_test_unprobed_devices_sh_sound pass
 2674 21:29:57.792115  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2675 21:29:57.801488  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2676 21:29:57.807565  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2677 21:29:57.812540  dt_test_unprobed_devices_sh fail
 2678 21:29:57.816886  + ../../utils/send-to-lava.sh ./output/result.txt
 2679 21:29:57.936095  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2680 21:29:57.937264  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2682 21:29:58.120826  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2683 21:29:58.121445  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2685 21:29:58.328941  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2686 21:29:58.329551  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2688 21:29:58.547708  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2689 21:29:58.548323  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2691 21:29:58.729486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2692 21:29:58.730097  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2694 21:29:58.905108  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2695 21:29:58.905719  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2697 21:29:59.103773  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2698 21:29:59.104383  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2700 21:29:59.286586  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2701 21:29:59.287199  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2703 21:29:59.460968  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2704 21:29:59.461580  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2706 21:29:59.646012  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2707 21:29:59.646624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2709 21:29:59.839600  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2710 21:29:59.840226  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2712 21:30:00.031289  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2713 21:30:00.031905  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2715 21:30:00.231821  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2716 21:30:00.232437  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2718 21:30:00.421619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2719 21:30:00.422237  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2721 21:30:00.614344  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2722 21:30:00.614957  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2724 21:30:00.801064  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2725 21:30:00.801677  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2727 21:30:00.975919  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2728 21:30:00.976536  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2730 21:30:01.162721  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2731 21:30:01.163335  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2733 21:30:01.345156  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2734 21:30:01.345777  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2736 21:30:01.535125  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2737 21:30:01.535745  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2739 21:30:01.721175  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2740 21:30:01.721793  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2742 21:30:01.921713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2743 21:30:01.922331  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2745 21:30:02.129621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2746 21:30:02.130239  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2748 21:30:02.328080  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2749 21:30:02.328699  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2751 21:30:02.513893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2752 21:30:02.514516  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2754 21:30:02.730448  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2755 21:30:02.731061  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2757 21:30:02.951798  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2758 21:30:02.952412  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2760 21:30:03.130401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2761 21:30:03.131018  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2763 21:30:03.320334  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2764 21:30:03.320949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2766 21:30:03.514601  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2767 21:30:03.515224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2769 21:30:03.708503  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2770 21:30:03.709142  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2772 21:30:03.915612  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2773 21:30:03.916227  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2775 21:30:04.104139  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2776 21:30:04.104760  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2778 21:30:04.297303  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2779 21:30:04.297923  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2781 21:30:04.478642  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2782 21:30:04.479256  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2784 21:30:04.656089  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2785 21:30:04.656709  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2787 21:30:04.870278  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2788 21:30:04.870896  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2790 21:30:05.054055  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2791 21:30:05.054675  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2793 21:30:05.236827  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2794 21:30:05.237444  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2796 21:30:05.444757  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2797 21:30:05.445397  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2799 21:30:05.640017  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2800 21:30:05.640643  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2802 21:30:05.831140  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2803 21:30:05.831757  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2805 21:30:06.024520  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2806 21:30:06.025171  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2808 21:30:06.208387  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2809 21:30:06.209004  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2811 21:30:06.405756  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2812 21:30:06.406372  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2814 21:30:06.626635  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2815 21:30:06.627252  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2817 21:30:06.807275  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2818 21:30:06.807895  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2820 21:30:07.019511  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2821 21:30:07.020128  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2823 21:30:07.212854  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2824 21:30:07.213478  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2826 21:30:07.397889  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2827 21:30:07.398504  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2829 21:30:07.587904  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2830 21:30:07.588528  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2832 21:30:07.781250  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2833 21:30:07.781868  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2835 21:30:07.966349  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2836 21:30:07.966968  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2838 21:30:08.164770  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2839 21:30:08.165426  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2841 21:30:08.349841  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2842 21:30:08.350461  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2844 21:30:08.585310  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2845 21:30:08.585928  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2847 21:30:08.790417  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2848 21:30:08.791034  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2850 21:30:08.981538  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2851 21:30:08.982157  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2853 21:30:09.165461  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2854 21:30:09.166076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2856 21:30:09.358681  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2857 21:30:09.359298  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2859 21:30:09.549840  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2860 21:30:09.550459  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2862 21:30:09.731295  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2863 21:30:09.731911  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2865 21:30:09.929741  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2866 21:30:09.930361  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2868 21:30:10.116499  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2869 21:30:10.117145  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2871 21:30:10.303500  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2872 21:30:10.304114  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2874 21:30:10.494570  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2875 21:30:10.495185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2877 21:30:10.691991  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2878 21:30:10.692607  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2880 21:30:10.897877  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2881 21:30:10.898490  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2883 21:30:11.101609  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2884 21:30:11.102222  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2886 21:30:11.285270  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2887 21:30:11.285890  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2889 21:30:11.458619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2890 21:30:11.459233  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2892 21:30:11.632862  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2893 21:30:11.633475  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2895 21:30:11.850512  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2896 21:30:11.851132  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2898 21:30:12.066954  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2899 21:30:12.067571  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2901 21:30:12.257004  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2902 21:30:12.257621  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2904 21:30:12.438856  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2905 21:30:12.439479  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2907 21:30:12.615340  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2908 21:30:12.615958  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2910 21:30:12.827661  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2911 21:30:12.828279  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2913 21:30:13.048338  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2914 21:30:13.048954  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2916 21:30:13.234514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2917 21:30:13.235131  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2919 21:30:13.435297  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2920 21:30:13.435914  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2922 21:30:13.659090  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2923 21:30:13.659705  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2925 21:30:13.849140  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2926 21:30:13.849757  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2928 21:30:14.041408  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2929 21:30:14.042022  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2931 21:30:14.266411  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2932 21:30:14.267028  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2934 21:30:14.484933  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2935 21:30:14.485555  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2937 21:30:14.693747  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2938 21:30:14.694364  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2940 21:30:14.907007  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2941 21:30:14.907626  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2943 21:30:15.092737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2944 21:30:15.093384  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2946 21:30:15.296887  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2947 21:30:15.297515  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2949 21:30:15.486345  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2950 21:30:15.486962  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2952 21:30:15.648723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2953 21:30:15.649380  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2955 21:30:15.834660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2956 21:30:15.835280  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2958 21:30:16.043780  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2959 21:30:16.044395  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2961 21:30:16.225548  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2962 21:30:16.226167  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2964 21:30:16.390167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2965 21:30:16.390789  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2967 21:30:16.559962  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2968 21:30:16.560579  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2970 21:30:16.744547  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2971 21:30:16.745197  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2973 21:30:16.943699  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2974 21:30:16.944315  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2976 21:30:17.126488  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2977 21:30:17.127103  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2979 21:30:17.327051  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2980 21:30:17.327681  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2982 21:30:17.528490  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2983 21:30:17.529141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2985 21:30:17.725631  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2986 21:30:17.726246  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2988 21:30:17.914269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2989 21:30:17.914883  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2991 21:30:18.102130  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2992 21:30:18.102745  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 2994 21:30:18.288138  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 2995 21:30:18.288754  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 2997 21:30:18.486570  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 2998 21:30:18.487185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 3000 21:30:18.694314  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 3001 21:30:18.694927  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 3003 21:30:18.880188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 3004 21:30:18.880828  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 3006 21:30:19.078771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 3007 21:30:19.079388  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 3009 21:30:19.286907  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 3010 21:30:19.287524  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 3012 21:30:19.480454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 3013 21:30:19.481093  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 3015 21:30:19.681358  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 3016 21:30:19.681980  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 3018 21:30:19.876771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 3019 21:30:19.877420  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 3021 21:30:20.069306  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3022 21:30:20.069924  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3024 21:30:20.263871  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3025 21:30:20.264489  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3027 21:30:20.440559  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3028 21:30:20.441207  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3030 21:30:20.630621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3031 21:30:20.631238  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3033 21:30:20.836977  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3034 21:30:20.837594  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3036 21:30:21.035504  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3037 21:30:21.036117  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3039 21:30:21.231651  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3041 21:30:21.233665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3042 21:30:21.428276  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3044 21:30:21.431281  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3045 21:30:21.622966  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3047 21:30:21.626010  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3048 21:30:21.834121  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3049 21:30:21.834738  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3051 21:30:22.044198  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3052 21:30:22.044830  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3054 21:30:22.278380  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3055 21:30:22.278993  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3057 21:30:22.471371  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3058 21:30:22.471984  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3060 21:30:22.670680  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3061 21:30:22.671297  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3063 21:30:22.896431  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3064 21:30:22.897070  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3066 21:30:23.083922  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3067 21:30:23.084536  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3069 21:30:23.262320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3070 21:30:23.262933  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3072 21:30:23.477563  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3073 21:30:23.478185  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3075 21:30:23.663238  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3076 21:30:23.663849  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3078 21:30:23.885654  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3079 21:30:23.886268  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3081 21:30:24.071211  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3082 21:30:24.071824  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3084 21:30:24.271670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3085 21:30:24.272282  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3087 21:30:24.463573  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3088 21:30:24.464186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3090 21:30:24.664377  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 3091 21:30:24.664991  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 3093 21:30:24.848269  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 3094 21:30:24.848873  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 3096 21:30:25.044622  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3097 21:30:25.045268  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3099 21:30:25.238726  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3100 21:30:25.239343  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3102 21:30:25.432076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3103 21:30:25.432697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3105 21:30:25.671425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3106 21:30:25.672039  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3108 21:30:25.852577  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3109 21:30:25.853224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3111 21:30:26.082123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3112 21:30:26.082746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3114 21:30:26.294813  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3115 21:30:26.295428  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3117 21:30:26.488439  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3118 21:30:26.489078  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3120 21:30:26.694982  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3121 21:30:26.695594  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3123 21:30:26.873432  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3124 21:30:26.874049  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3126 21:30:27.070506  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3127 21:30:27.071118  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3129 21:30:27.253702  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3130 21:30:27.254318  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3132 21:30:27.452969  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3133 21:30:27.453581  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3135 21:30:27.671220  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3136 21:30:27.671836  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3138 21:30:27.873494  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3139 21:30:27.874106  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3141 21:30:28.073892  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3142 21:30:28.074507  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3144 21:30:28.263628  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3145 21:30:28.264246  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3147 21:30:28.455609  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3148 21:30:28.456224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3150 21:30:28.645413  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3151 21:30:28.646027  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3153 21:30:28.853185  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3154 21:30:28.853802  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3156 21:30:29.047214  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3157 21:30:29.047833  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3159 21:30:29.255889  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3160 21:30:29.256507  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3162 21:30:29.460549  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3163 21:30:29.461193  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3165 21:30:29.652589  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3166 21:30:29.653240  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3168 21:30:29.843032  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3169 21:30:29.843649  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3171 21:30:30.040067  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3172 21:30:30.040681  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3174 21:30:30.252906  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3175 21:30:30.253516  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3177 21:30:30.471423  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3178 21:30:30.472037  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3180 21:30:30.674966  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3181 21:30:30.675579  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3183 21:30:30.857384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3184 21:30:30.857993  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3186 21:30:31.041956  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3187 21:30:31.042578  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3189 21:30:31.246439  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3190 21:30:31.247048  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3192 21:30:31.436292  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3193 21:30:31.436875  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3195 21:30:31.617635  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3196 21:30:31.618249  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3198 21:30:31.801201  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3199 21:30:31.801814  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3201 21:30:31.990041  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3202 21:30:31.990656  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3204 21:30:32.177398  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3205 21:30:32.178011  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3207 21:30:32.372536  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3208 21:30:32.373181  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3210 21:30:32.575262  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3211 21:30:32.575876  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3213 21:30:32.753613  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 3214 21:30:32.754234  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 3216 21:30:32.978457  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 3217 21:30:32.979076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 3219 21:30:33.164278  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 3220 21:30:33.164876  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 3222 21:30:33.375567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 3223 21:30:33.376186  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 3225 21:30:33.572151  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 3226 21:30:33.572768  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 3228 21:30:33.748561  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 3229 21:30:33.749210  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 3231 21:30:33.947335  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 3232 21:30:33.947948  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 3234 21:30:34.195558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 3235 21:30:34.196179  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 3237 21:30:34.371562  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3238 21:30:34.372183  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3240 21:30:34.559346  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3241 21:30:34.559961  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3243 21:30:34.733438  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3244 21:30:34.734061  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3246 21:30:34.933532  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3247 21:30:34.934145  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3249 21:30:35.113770  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3250 21:30:35.114384  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3252 21:30:35.298294  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3253 21:30:35.298908  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3255 21:30:35.480765  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3256 21:30:35.481404  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3258 21:30:35.672587  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3259 21:30:35.673231  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3261 21:30:35.853186  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3262 21:30:35.853800  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3264 21:30:36.048211  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3265 21:30:36.048850  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3267 21:30:36.254993  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3268 21:30:36.255604  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3270 21:30:36.456316  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3271 21:30:36.456930  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3273 21:30:36.656385  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3274 21:30:36.657000  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3276 21:30:36.883208  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3277 21:30:36.883823  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3279 21:30:37.089503  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3280 21:30:37.090124  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3282 21:30:37.309614  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3283 21:30:37.310233  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3285 21:30:37.492097  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3286 21:30:37.492712  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3288 21:30:37.671323  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3289 21:30:37.671938  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3291 21:30:37.873850  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3292 21:30:37.874465  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3294 21:30:38.061537  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3295 21:30:38.062152  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3297 21:30:38.236704  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3298 21:30:38.237351  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3300 21:30:38.421251  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3301 21:30:38.421871  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3303 21:30:38.613197  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3304 21:30:38.613811  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3306 21:30:38.807913  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3307 21:30:38.808525  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3309 21:30:39.008129  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3310 21:30:39.008741  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3312 21:30:39.266421  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3313 21:30:39.267037  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3315 21:30:39.476198  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3316 21:30:39.476833  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3318 21:30:39.670340  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3319 21:30:39.670956  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3321 21:30:39.870794  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3322 21:30:39.871411  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3324 21:30:40.080552  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3325 21:30:40.081196  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3327 21:30:40.275583  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3328 21:30:40.276200  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3330 21:30:40.486597  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3331 21:30:40.487214  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3333 21:30:40.668231  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3334 21:30:40.668863  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3336 21:30:40.853078  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3337 21:30:40.853696  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3339 21:30:41.060971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3340 21:30:41.061587  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3342 21:30:41.248241  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3343 21:30:41.248868  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3345 21:30:41.450266  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3346 21:30:41.450877  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3348 21:30:41.670136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3349 21:30:41.670748  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3351 21:30:41.843729  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3352 21:30:41.844343  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3354 21:30:42.033227  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3355 21:30:42.033842  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3357 21:30:42.217734  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3358 21:30:42.218348  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3360 21:30:42.407507  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3362 21:30:42.411596  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3363 21:30:42.596640  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3364 21:30:42.597283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3366 21:30:42.783262  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3367 21:30:42.783878  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3369 21:30:42.961184  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3370 21:30:42.961798  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3372 21:30:43.151654  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3373 21:30:43.152267  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3375 21:30:43.344213  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3376 21:30:43.344853  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3378 21:30:43.528320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3379 21:30:43.528929  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3381 21:30:43.703994  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3382 21:30:43.704612  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3384 21:30:43.880443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3385 21:30:43.881081  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3387 21:30:44.064650  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3388 21:30:44.065301  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3390 21:30:44.262360  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3391 21:30:44.262974  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3393 21:30:44.438198  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3394 21:30:44.438814  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3396 21:30:44.617007  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3397 21:30:44.617623  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3399 21:30:44.820256  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3400 21:30:44.820876  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3402 21:30:45.041136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3403 21:30:45.041750  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3405 21:30:45.215663  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3406 21:30:45.216276  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3408 21:30:45.386133  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3409 21:30:45.386746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3411 21:30:45.569162  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3412 21:30:45.569783  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3414 21:30:45.743805  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3415 21:30:45.744416  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3417 21:30:45.934130  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3418 21:30:45.934746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3420 21:30:46.132949  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3421 21:30:46.133562  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3423 21:30:46.318148  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3424 21:30:46.318758  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3426 21:30:46.529832  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3427 21:30:46.530442  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3429 21:30:46.727619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3430 21:30:46.728234  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3432 21:30:46.920290  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3433 21:30:46.920875  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3435 21:30:47.116871  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3436 21:30:47.117482  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3438 21:30:47.298460  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3439 21:30:47.299083  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3441 21:30:47.499136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3442 21:30:47.499747  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3444 21:30:47.687368  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3445 21:30:47.687985  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3447 21:30:47.879884  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3448 21:30:47.880498  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3450 21:30:48.101170  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3451 21:30:48.101784  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3453 21:30:48.296038  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3454 21:30:48.296423  + set +x
 3455 21:30:48.296959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3457 21:30:48.300339  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1215758_1.6.2.4.5>
 3458 21:30:48.300945  Received signal: <ENDRUN> 1_kselftest-dt 1215758_1.6.2.4.5
 3459 21:30:48.301290  Ending use of test pattern.
 3460 21:30:48.301593  Ending test lava.1_kselftest-dt (1215758_1.6.2.4.5), duration 249.20
 3462 21:30:48.355683  <LAVA_TEST_RUNNER EXIT>
 3463 21:30:48.356290  ok: lava_test_shell seems to have completed
 3464 21:30:48.363415  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3465 21:30:48.364863  end: 3.1 lava-test-shell (duration 00:04:11) [common]
 3466 21:30:48.365272  end: 3 lava-test-retry (duration 00:04:11) [common]
 3467 21:30:48.365691  start: 4 finalize (timeout 00:02:41) [common]
 3468 21:30:48.366084  start: 4.1 power-off (timeout 00:00:30) [common]
 3469 21:30:48.366558  Calling: 'drpm' 'lf-bbb-02' 'off'
 3470 21:30:48.697616  >> OFF

 3471 21:30:48.699159  Returned 0 in 0 seconds
 3472 21:30:48.800267  end: 4.1 power-off (duration 00:00:00) [common]
 3474 21:30:48.801366  start: 4.2 read-feedback (timeout 00:02:41) [common]
 3475 21:30:48.802379  Listened to connection for namespace 'common' for up to 1s
 3476 21:30:48.803092  Listened to connection for namespace 'common' for up to 1s
 3477 21:30:49.802467  Finalising connection for namespace 'common'
 3478 21:30:49.802973  Disconnecting from shell: Finalise
 3479 21:30:49.803358  / # 
 3480 21:30:49.904118  end: 4.2 read-feedback (duration 00:00:01) [common]
 3481 21:30:49.904628  end: 4 finalize (duration 00:00:02) [common]
 3482 21:30:49.905153  Cleaning after the job
 3483 21:30:49.905603  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/ramdisk
 3484 21:30:49.911695  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/kernel
 3485 21:30:49.916256  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/dtb
 3486 21:30:49.916986  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/nfsrootfs
 3487 21:30:50.028420  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215758/tftp-deploy-2udq1ia5/modules
 3488 21:30:50.033915  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1215758
 3489 21:30:51.162237  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1215758
 3490 21:30:51.162541  Job finished correctly