Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:23:23.388221 lava-dispatcher, installed at version: 2024.01
2 20:23:23.389110 start: 0 validate
3 20:23:23.389646 Start time: 2024-11-03 20:23:23.389612+00:00 (UTC)
4 20:23:23.390271 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:23:23.390875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:23:23.431778 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:23:23.432531 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 20:23:23.466739 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:23:23.467409 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:23:24.517191 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:23:24.517747 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 20:23:24.561712 validate duration: 1.17
14 20:23:24.563178 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:23:24.563781 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:23:24.564282 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:23:24.564874 Not decompressing ramdisk as can be used compressed.
18 20:23:24.565326 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:23:24.565564 saving as /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/ramdisk/rootfs.cpio.gz
20 20:23:24.565816 total size: 8181887 (7 MB)
21 20:23:24.606000 progress 0 % (0 MB)
22 20:23:24.618511 progress 5 % (0 MB)
23 20:23:24.625229 progress 10 % (0 MB)
24 20:23:24.634493 progress 15 % (1 MB)
25 20:23:24.639921 progress 20 % (1 MB)
26 20:23:24.645796 progress 25 % (1 MB)
27 20:23:24.651152 progress 30 % (2 MB)
28 20:23:24.656970 progress 35 % (2 MB)
29 20:23:24.662407 progress 40 % (3 MB)
30 20:23:24.668288 progress 45 % (3 MB)
31 20:23:24.673747 progress 50 % (3 MB)
32 20:23:24.679838 progress 55 % (4 MB)
33 20:23:24.685367 progress 60 % (4 MB)
34 20:23:24.691383 progress 65 % (5 MB)
35 20:23:24.696944 progress 70 % (5 MB)
36 20:23:24.702928 progress 75 % (5 MB)
37 20:23:24.708498 progress 80 % (6 MB)
38 20:23:24.714259 progress 85 % (6 MB)
39 20:23:24.719564 progress 90 % (7 MB)
40 20:23:24.725402 progress 95 % (7 MB)
41 20:23:24.730382 progress 100 % (7 MB)
42 20:23:24.731049 7 MB downloaded in 0.17 s (47.23 MB/s)
43 20:23:24.731627 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:23:24.732609 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:23:24.732926 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:23:24.733213 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:23:24.733730 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/kernel/Image
49 20:23:24.734017 saving as /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/kernel/Image
50 20:23:24.734236 total size: 169943552 (162 MB)
51 20:23:24.734455 No compression specified
52 20:23:24.774533 progress 0 % (0 MB)
53 20:23:24.881822 progress 5 % (8 MB)
54 20:23:24.988107 progress 10 % (16 MB)
55 20:23:25.094587 progress 15 % (24 MB)
56 20:23:25.201632 progress 20 % (32 MB)
57 20:23:25.306860 progress 25 % (40 MB)
58 20:23:25.414331 progress 30 % (48 MB)
59 20:23:25.518961 progress 35 % (56 MB)
60 20:23:25.623175 progress 40 % (64 MB)
61 20:23:25.727221 progress 45 % (72 MB)
62 20:23:25.831673 progress 50 % (81 MB)
63 20:23:25.937028 progress 55 % (89 MB)
64 20:23:26.042070 progress 60 % (97 MB)
65 20:23:26.146797 progress 65 % (105 MB)
66 20:23:26.251476 progress 70 % (113 MB)
67 20:23:26.357154 progress 75 % (121 MB)
68 20:23:26.462340 progress 80 % (129 MB)
69 20:23:26.567758 progress 85 % (137 MB)
70 20:23:26.673275 progress 90 % (145 MB)
71 20:23:26.777939 progress 95 % (153 MB)
72 20:23:26.883137 progress 100 % (162 MB)
73 20:23:26.883754 162 MB downloaded in 2.15 s (75.40 MB/s)
74 20:23:26.884277 end: 1.2.1 http-download (duration 00:00:02) [common]
76 20:23:26.885105 end: 1.2 download-retry (duration 00:00:02) [common]
77 20:23:26.885380 start: 1.3 download-retry (timeout 00:09:58) [common]
78 20:23:26.885645 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 20:23:26.886133 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 20:23:26.886426 saving as /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/dtb/meson-g12b-a311d-libretech-cc.dtb
81 20:23:26.886639 total size: 54703 (0 MB)
82 20:23:26.886851 No compression specified
83 20:23:26.929719 progress 59 % (0 MB)
84 20:23:26.930552 progress 100 % (0 MB)
85 20:23:26.931101 0 MB downloaded in 0.04 s (1.17 MB/s)
86 20:23:26.931562 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:23:26.932419 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:23:26.932685 start: 1.4 download-retry (timeout 00:09:58) [common]
90 20:23:26.932947 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 20:23:26.933425 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 20:23:26.933685 saving as /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/modules/modules.tar
93 20:23:26.933890 total size: 27642748 (26 MB)
94 20:23:26.934103 Using unxz to decompress xz
95 20:23:26.970276 progress 0 % (0 MB)
96 20:23:27.163179 progress 5 % (1 MB)
97 20:23:27.363202 progress 10 % (2 MB)
98 20:23:27.593514 progress 15 % (3 MB)
99 20:23:27.829481 progress 20 % (5 MB)
100 20:23:28.030952 progress 25 % (6 MB)
101 20:23:28.238022 progress 30 % (7 MB)
102 20:23:28.441703 progress 35 % (9 MB)
103 20:23:28.640215 progress 40 % (10 MB)
104 20:23:28.840218 progress 45 % (11 MB)
105 20:23:29.057122 progress 50 % (13 MB)
106 20:23:29.256425 progress 55 % (14 MB)
107 20:23:29.476218 progress 60 % (15 MB)
108 20:23:29.683068 progress 65 % (17 MB)
109 20:23:29.885814 progress 70 % (18 MB)
110 20:23:30.095075 progress 75 % (19 MB)
111 20:23:30.296361 progress 80 % (21 MB)
112 20:23:30.508876 progress 85 % (22 MB)
113 20:23:30.715686 progress 90 % (23 MB)
114 20:23:30.915298 progress 95 % (25 MB)
115 20:23:31.119243 progress 100 % (26 MB)
116 20:23:31.132736 26 MB downloaded in 4.20 s (6.28 MB/s)
117 20:23:31.133340 end: 1.4.1 http-download (duration 00:00:04) [common]
119 20:23:31.134172 end: 1.4 download-retry (duration 00:00:04) [common]
120 20:23:31.134441 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 20:23:31.134708 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 20:23:31.134957 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:23:31.135210 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 20:23:31.135776 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9
125 20:23:31.136545 makedir: /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin
126 20:23:31.137217 makedir: /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/tests
127 20:23:31.137834 makedir: /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/results
128 20:23:31.138435 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-add-keys
129 20:23:31.139280 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-add-sources
130 20:23:31.139817 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-background-process-start
131 20:23:31.140712 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-background-process-stop
132 20:23:31.141730 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-common-functions
133 20:23:31.142719 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-echo-ipv4
134 20:23:31.143627 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-install-packages
135 20:23:31.144564 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-installed-packages
136 20:23:31.145470 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-os-build
137 20:23:31.146454 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-probe-channel
138 20:23:31.147355 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-probe-ip
139 20:23:31.148282 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-target-ip
140 20:23:31.149178 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-target-mac
141 20:23:31.150062 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-target-storage
142 20:23:31.150968 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-case
143 20:23:31.151851 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-event
144 20:23:31.152821 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-feedback
145 20:23:31.153733 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-raise
146 20:23:31.154712 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-reference
147 20:23:31.155613 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-runner
148 20:23:31.156573 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-set
149 20:23:31.157461 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-test-shell
150 20:23:31.158366 Updating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-install-packages (oe)
151 20:23:31.159350 Updating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/bin/lava-installed-packages (oe)
152 20:23:31.160226 Creating /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/environment
153 20:23:31.160950 LAVA metadata
154 20:23:31.161426 - LAVA_JOB_ID=930651
155 20:23:31.161848 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:23:31.162502 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 20:23:31.164305 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:23:31.164896 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 20:23:31.165301 skipped lava-vland-overlay
160 20:23:31.165778 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:23:31.166278 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 20:23:31.166700 skipped lava-multinode-overlay
163 20:23:31.167176 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:23:31.167669 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 20:23:31.168183 Loading test definitions
166 20:23:31.168739 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 20:23:31.169172 Using /lava-930651 at stage 0
168 20:23:31.171459 uuid=930651_1.5.2.4.1 testdef=None
169 20:23:31.172051 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:23:31.172567 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 20:23:31.175682 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:23:31.176528 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 20:23:31.178868 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:23:31.179703 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 20:23:31.181948 runner path: /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/0/tests/0_dmesg test_uuid 930651_1.5.2.4.1
178 20:23:31.182515 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:23:31.183283 Creating lava-test-runner.conf files
181 20:23:31.183485 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/930651/lava-overlay-dwc5l2a9/lava-930651/0 for stage 0
182 20:23:31.183825 - 0_dmesg
183 20:23:31.184222 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:23:31.184506 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 20:23:31.208316 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:23:31.208731 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 20:23:31.208996 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:23:31.209264 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:23:31.209529 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 20:23:32.193334 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:23:32.193908 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 20:23:32.194410 extracting modules file /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk
193 20:23:33.929597 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 20:23:33.930137 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 20:23:33.930422 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930651/compress-overlay-iz71whby/overlay-1.5.2.5.tar.gz to ramdisk
196 20:23:33.930639 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930651/compress-overlay-iz71whby/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk
197 20:23:33.961582 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:23:33.962049 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 20:23:33.962324 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 20:23:33.962554 Converting downloaded kernel to a uImage
201 20:23:33.962870 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/kernel/Image /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/kernel/uImage
202 20:23:35.845839 output: Image Name:
203 20:23:35.846259 output: Created: Sun Nov 3 20:23:33 2024
204 20:23:35.846472 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:23:35.846681 output: Data Size: 169943552 Bytes = 165960.50 KiB = 162.07 MiB
206 20:23:35.846886 output: Load Address: 01080000
207 20:23:35.847085 output: Entry Point: 01080000
208 20:23:35.847285 output:
209 20:23:35.847617 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 20:23:35.847883 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 20:23:35.848197 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 20:23:35.848454 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:23:35.848710 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 20:23:35.848965 Building ramdisk /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk
215 20:23:41.881489 >> 441542 blocks
216 20:24:00.451517 Adding RAMdisk u-boot header.
217 20:24:00.452286 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk.cpio.gz.uboot
218 20:24:00.997361 output: Image Name:
219 20:24:00.998041 output: Created: Sun Nov 3 20:24:00 2024
220 20:24:00.998496 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:24:00.998939 output: Data Size: 53580095 Bytes = 52324.31 KiB = 51.10 MiB
222 20:24:00.999379 output: Load Address: 00000000
223 20:24:00.999817 output: Entry Point: 00000000
224 20:24:01.000306 output:
225 20:24:01.001369 rename /var/lib/lava/dispatcher/tmp/930651/extract-overlay-ramdisk-m7byou1q/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/ramdisk/ramdisk.cpio.gz.uboot
226 20:24:01.002136 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 20:24:01.002727 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 20:24:01.003299 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 20:24:01.003794 No LXC device requested
230 20:24:01.004388 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:24:01.004943 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 20:24:01.005479 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:24:01.005931 Checking files for TFTP limit of 4294967296 bytes.
234 20:24:01.008961 end: 1 tftp-deploy (duration 00:00:36) [common]
235 20:24:01.009590 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:24:01.010164 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:24:01.010706 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:24:01.011251 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:24:01.011827 Using kernel file from prepare-kernel: 930651/tftp-deploy-zl4v3yje/kernel/uImage
240 20:24:01.012564 substitutions:
241 20:24:01.013020 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:24:01.013464 - {DTB_ADDR}: 0x01070000
243 20:24:01.013902 - {DTB}: 930651/tftp-deploy-zl4v3yje/dtb/meson-g12b-a311d-libretech-cc.dtb
244 20:24:01.014340 - {INITRD}: 930651/tftp-deploy-zl4v3yje/ramdisk/ramdisk.cpio.gz.uboot
245 20:24:01.014778 - {KERNEL_ADDR}: 0x01080000
246 20:24:01.015211 - {KERNEL}: 930651/tftp-deploy-zl4v3yje/kernel/uImage
247 20:24:01.015649 - {LAVA_MAC}: None
248 20:24:01.016149 - {PRESEED_CONFIG}: None
249 20:24:01.016587 - {PRESEED_LOCAL}: None
250 20:24:01.017019 - {RAMDISK_ADDR}: 0x08000000
251 20:24:01.017450 - {RAMDISK}: 930651/tftp-deploy-zl4v3yje/ramdisk/ramdisk.cpio.gz.uboot
252 20:24:01.017888 - {ROOT_PART}: None
253 20:24:01.018323 - {ROOT}: None
254 20:24:01.018755 - {SERVER_IP}: 192.168.6.2
255 20:24:01.019188 - {TEE_ADDR}: 0x83000000
256 20:24:01.019620 - {TEE}: None
257 20:24:01.020074 Parsed boot commands:
258 20:24:01.020497 - setenv autoload no
259 20:24:01.020927 - setenv initrd_high 0xffffffff
260 20:24:01.021353 - setenv fdt_high 0xffffffff
261 20:24:01.021779 - dhcp
262 20:24:01.022206 - setenv serverip 192.168.6.2
263 20:24:01.022634 - tftpboot 0x01080000 930651/tftp-deploy-zl4v3yje/kernel/uImage
264 20:24:01.023064 - tftpboot 0x08000000 930651/tftp-deploy-zl4v3yje/ramdisk/ramdisk.cpio.gz.uboot
265 20:24:01.023493 - tftpboot 0x01070000 930651/tftp-deploy-zl4v3yje/dtb/meson-g12b-a311d-libretech-cc.dtb
266 20:24:01.023922 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:24:01.024372 - bootm 0x01080000 0x08000000 0x01070000
268 20:24:01.024635 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:24:01.025388 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:24:01.025626 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 20:24:01.037937 Setting prompt string to ['lava-test: # ']
273 20:24:01.039502 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:24:01.040178 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:24:01.040809 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:24:01.041427 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:24:01.042313 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 20:24:01.077063 >> OK - accepted request
279 20:24:01.079071 Returned 0 in 0 seconds
280 20:24:01.180314 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:24:01.182193 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:24:01.182805 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:24:01.183352 Setting prompt string to ['Hit any key to stop autoboot']
285 20:24:01.183843 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:24:01.185593 Trying 192.168.56.21...
287 20:24:01.186097 Connected to conserv1.
288 20:24:01.186541 Escape character is '^]'.
289 20:24:01.187005
290 20:24:01.187469 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:24:01.187937
292 20:24:12.694793 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 20:24:12.695207 bl2_stage_init 0x01
294 20:24:12.695458 bl2_stage_init 0x81
295 20:24:12.700487 hw id: 0x0000 - pwm id 0x01
296 20:24:12.700828 bl2_stage_init 0xc1
297 20:24:12.701052 bl2_stage_init 0x02
298 20:24:12.701270
299 20:24:12.705969 L0:00000000
300 20:24:12.706282 L1:20000703
301 20:24:12.706484 L2:00008067
302 20:24:12.706677 L3:14000000
303 20:24:12.711514 B2:00402000
304 20:24:12.712027 B1:e0f83180
305 20:24:12.712464
306 20:24:12.712896 TE: 58159
307 20:24:12.713326
308 20:24:12.717165 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 20:24:12.717636
310 20:24:12.718069 Board ID = 1
311 20:24:12.722593 Set A53 clk to 24M
312 20:24:12.723058 Set A73 clk to 24M
313 20:24:12.723485 Set clk81 to 24M
314 20:24:12.728291 A53 clk: 1200 MHz
315 20:24:12.728772 A73 clk: 1200 MHz
316 20:24:12.729203 CLK81: 166.6M
317 20:24:12.729632 smccc: 00012ab5
318 20:24:12.733882 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 20:24:12.739399 board id: 1
320 20:24:12.745435 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:24:12.756025 fw parse done
322 20:24:12.761957 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:24:12.803680 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:24:12.815474 PIEI prepare done
325 20:24:12.816007 fastboot data load
326 20:24:12.816464 fastboot data verify
327 20:24:12.821099 verify result: 266
328 20:24:12.826824 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 20:24:12.827297 LPDDR4 probe
330 20:24:12.827734 ddr clk to 1584MHz
331 20:24:12.835564 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:24:12.871954
333 20:24:12.872506 dmc_version 0001
334 20:24:12.878586 Check phy result
335 20:24:12.884458 INFO : End of CA training
336 20:24:12.884939 INFO : End of initialization
337 20:24:12.890187 INFO : Training has run successfully!
338 20:24:12.890660 Check phy result
339 20:24:12.895648 INFO : End of initialization
340 20:24:12.896147 INFO : End of read enable training
341 20:24:12.901226 INFO : End of fine write leveling
342 20:24:12.906840 INFO : End of Write leveling coarse delay
343 20:24:12.907320 INFO : Training has run successfully!
344 20:24:12.907769 Check phy result
345 20:24:12.912433 INFO : End of initialization
346 20:24:12.912916 INFO : End of read dq deskew training
347 20:24:12.918156 INFO : End of MPR read delay center optimization
348 20:24:12.923640 INFO : End of write delay center optimization
349 20:24:12.929297 INFO : End of read delay center optimization
350 20:24:12.929780 INFO : End of max read latency training
351 20:24:12.934847 INFO : Training has run successfully!
352 20:24:12.935321 1D training succeed
353 20:24:12.943253 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:24:12.991245 Check phy result
355 20:24:12.991908 INFO : End of initialization
356 20:24:13.012611 INFO : End of 2D read delay Voltage center optimization
357 20:24:13.032449 INFO : End of 2D read delay Voltage center optimization
358 20:24:13.084357 INFO : End of 2D write delay Voltage center optimization
359 20:24:13.134443 INFO : End of 2D write delay Voltage center optimization
360 20:24:13.140100 INFO : Training has run successfully!
361 20:24:13.140545
362 20:24:13.140945 channel==0
363 20:24:13.145593 RxClkDly_Margin_A0==88 ps 9
364 20:24:13.146076 TxDqDly_Margin_A0==98 ps 10
365 20:24:13.151188 RxClkDly_Margin_A1==88 ps 9
366 20:24:13.151642 TxDqDly_Margin_A1==88 ps 9
367 20:24:13.152086 TrainedVREFDQ_A0==74
368 20:24:13.156823 TrainedVREFDQ_A1==74
369 20:24:13.157266 VrefDac_Margin_A0==25
370 20:24:13.157664 DeviceVref_Margin_A0==40
371 20:24:13.162372 VrefDac_Margin_A1==25
372 20:24:13.162800 DeviceVref_Margin_A1==40
373 20:24:13.163195
374 20:24:13.163584
375 20:24:13.163975 channel==1
376 20:24:13.167956 RxClkDly_Margin_A0==98 ps 10
377 20:24:13.168435 TxDqDly_Margin_A0==98 ps 10
378 20:24:13.173560 RxClkDly_Margin_A1==98 ps 10
379 20:24:13.173985 TxDqDly_Margin_A1==88 ps 9
380 20:24:13.179122 TrainedVREFDQ_A0==77
381 20:24:13.179554 TrainedVREFDQ_A1==77
382 20:24:13.179950 VrefDac_Margin_A0==22
383 20:24:13.184809 DeviceVref_Margin_A0==37
384 20:24:13.185229 VrefDac_Margin_A1==22
385 20:24:13.190403 DeviceVref_Margin_A1==37
386 20:24:13.190840
387 20:24:13.191241 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:24:13.191632
389 20:24:13.223997 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 20:24:13.224562 2D training succeed
391 20:24:13.229578 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:24:13.235184 auto size-- 65535DDR cs0 size: 2048MB
393 20:24:13.235637 DDR cs1 size: 2048MB
394 20:24:13.240758 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:24:13.241203 cs0 DataBus test pass
396 20:24:13.246374 cs1 DataBus test pass
397 20:24:13.246794 cs0 AddrBus test pass
398 20:24:13.247182 cs1 AddrBus test pass
399 20:24:13.247568
400 20:24:13.251947 100bdlr_step_size ps== 420
401 20:24:13.252420 result report
402 20:24:13.257604 boot times 0Enable ddr reg access
403 20:24:13.262018 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:24:13.275959 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 20:24:13.848399 0.0;M3 CHK:0;cm4_sp_mode 0
406 20:24:13.848998 MVN_1=0x00000000
407 20:24:13.853861 MVN_2=0x00000000
408 20:24:13.859654 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 20:24:13.860159 OPS=0x10
410 20:24:13.860580 ring efuse init
411 20:24:13.860978 chipver efuse init
412 20:24:13.865234 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 20:24:13.870809 [0.018960 Inits done]
414 20:24:13.871237 secure task start!
415 20:24:13.871643 high task start!
416 20:24:13.875109 low task start!
417 20:24:13.875545 run into bl31
418 20:24:13.882167 NOTICE: BL31: v1.3(release):4fc40b1
419 20:24:13.888971 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 20:24:13.889421 NOTICE: BL31: G12A normal boot!
421 20:24:13.915313 NOTICE: BL31: BL33 decompress pass
422 20:24:13.920077 ERROR: Error initializing runtime service opteed_fast
423 20:24:15.153731
424 20:24:15.154117
425 20:24:15.162135 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 20:24:15.162430
427 20:24:15.162645 Model: Libre Computer AML-A311D-CC Alta
428 20:24:15.369855 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 20:24:15.393253 DRAM: 2 GiB (effective 3.8 GiB)
430 20:24:15.537001 Core: 408 devices, 31 uclasses, devicetree: separate
431 20:24:15.542483 WDT: Not starting watchdog@f0d0
432 20:24:15.575132 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 20:24:15.587583 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 20:24:15.592529 ** Bad device specification mmc 0 **
435 20:24:15.602885 Card did not respond to voltage select! : -110
436 20:24:15.609647 ** Bad device specification mmc 0 **
437 20:24:15.609941 Couldn't find partition mmc 0
438 20:24:15.618917 Card did not respond to voltage select! : -110
439 20:24:15.624407 ** Bad device specification mmc 0 **
440 20:24:15.625165 Couldn't find partition mmc 0
441 20:24:15.629147 Error: could not access storage.
442 20:24:16.894900 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 20:24:16.895562 bl2_stage_init 0x01
444 20:24:16.896077 bl2_stage_init 0x81
445 20:24:16.900526 hw id: 0x0000 - pwm id 0x01
446 20:24:16.901052 bl2_stage_init 0xc1
447 20:24:16.901513 bl2_stage_init 0x02
448 20:24:16.901961
449 20:24:16.906069 L0:00000000
450 20:24:16.906581 L1:20000703
451 20:24:16.907034 L2:00008067
452 20:24:16.907473 L3:14000000
453 20:24:16.911686 B2:00402000
454 20:24:16.912242 B1:e0f83180
455 20:24:16.912699
456 20:24:16.913149 TE: 58124
457 20:24:16.913593
458 20:24:16.917271 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 20:24:16.917796
460 20:24:16.918251 Board ID = 1
461 20:24:16.922880 Set A53 clk to 24M
462 20:24:16.923416 Set A73 clk to 24M
463 20:24:16.923873 Set clk81 to 24M
464 20:24:16.928483 A53 clk: 1200 MHz
465 20:24:16.928998 A73 clk: 1200 MHz
466 20:24:16.929451 CLK81: 166.6M
467 20:24:16.929889 smccc: 00012a92
468 20:24:16.934011 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 20:24:16.939646 board id: 1
470 20:24:16.944644 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 20:24:16.956225 fw parse done
472 20:24:16.961780 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 20:24:17.004563 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 20:24:17.015721 PIEI prepare done
475 20:24:17.016298 fastboot data load
476 20:24:17.016765 fastboot data verify
477 20:24:17.021399 verify result: 266
478 20:24:17.026999 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 20:24:17.027528 LPDDR4 probe
480 20:24:17.028023 ddr clk to 1584MHz
481 20:24:17.034298 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 20:24:17.071922
483 20:24:17.072510 dmc_version 0001
484 20:24:17.078853 Check phy result
485 20:24:17.084790 INFO : End of CA training
486 20:24:17.085310 INFO : End of initialization
487 20:24:17.090397 INFO : Training has run successfully!
488 20:24:17.090934 Check phy result
489 20:24:17.096010 INFO : End of initialization
490 20:24:17.096563 INFO : End of read enable training
491 20:24:17.099301 INFO : End of fine write leveling
492 20:24:17.104817 INFO : End of Write leveling coarse delay
493 20:24:17.110478 INFO : Training has run successfully!
494 20:24:17.111029 Check phy result
495 20:24:17.111495 INFO : End of initialization
496 20:24:17.116049 INFO : End of read dq deskew training
497 20:24:17.121644 INFO : End of MPR read delay center optimization
498 20:24:17.122178 INFO : End of write delay center optimization
499 20:24:17.127229 INFO : End of read delay center optimization
500 20:24:17.132827 INFO : End of max read latency training
501 20:24:17.133354 INFO : Training has run successfully!
502 20:24:17.138424 1D training succeed
503 20:24:17.143513 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 20:24:17.191824 Check phy result
505 20:24:17.192461 INFO : End of initialization
506 20:24:17.213149 INFO : End of 2D read delay Voltage center optimization
507 20:24:17.233388 INFO : End of 2D read delay Voltage center optimization
508 20:24:17.285278 INFO : End of 2D write delay Voltage center optimization
509 20:24:17.335321 INFO : End of 2D write delay Voltage center optimization
510 20:24:17.340803 INFO : Training has run successfully!
511 20:24:17.341184
512 20:24:17.341520 channel==0
513 20:24:17.346401 RxClkDly_Margin_A0==88 ps 9
514 20:24:17.346762 TxDqDly_Margin_A0==98 ps 10
515 20:24:17.351974 RxClkDly_Margin_A1==88 ps 9
516 20:24:17.352290 TxDqDly_Margin_A1==98 ps 10
517 20:24:17.352698 TrainedVREFDQ_A0==74
518 20:24:17.357601 TrainedVREFDQ_A1==74
519 20:24:17.358006 VrefDac_Margin_A0==25
520 20:24:17.358301 DeviceVref_Margin_A0==40
521 20:24:17.363161 VrefDac_Margin_A1==25
522 20:24:17.363520 DeviceVref_Margin_A1==40
523 20:24:17.363851
524 20:24:17.364198
525 20:24:17.369012 channel==1
526 20:24:17.369716 RxClkDly_Margin_A0==98 ps 10
527 20:24:17.370331 TxDqDly_Margin_A0==98 ps 10
528 20:24:17.374532 RxClkDly_Margin_A1==98 ps 10
529 20:24:17.375235 TxDqDly_Margin_A1==98 ps 10
530 20:24:17.380148 TrainedVREFDQ_A0==77
531 20:24:17.380840 TrainedVREFDQ_A1==78
532 20:24:17.381451 VrefDac_Margin_A0==22
533 20:24:17.385724 DeviceVref_Margin_A0==37
534 20:24:17.386424 VrefDac_Margin_A1==22
535 20:24:17.391364 DeviceVref_Margin_A1==36
536 20:24:17.392122
537 20:24:17.392789 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 20:24:17.396903
539 20:24:17.424835 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 20:24:17.425436 2D training succeed
541 20:24:17.430462 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 20:24:17.436087 auto size-- 65535DDR cs0 size: 2048MB
543 20:24:17.436614 DDR cs1 size: 2048MB
544 20:24:17.441692 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 20:24:17.442217 cs0 DataBus test pass
546 20:24:17.447301 cs1 DataBus test pass
547 20:24:17.447817 cs0 AddrBus test pass
548 20:24:17.448324 cs1 AddrBus test pass
549 20:24:17.448766
550 20:24:17.452872 100bdlr_step_size ps== 420
551 20:24:17.453396 result report
552 20:24:17.458497 boot times 0Enable ddr reg access
553 20:24:17.463574 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 20:24:17.477491 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 20:24:18.051251 0.0;M3 CHK:0;cm4_sp_mode 0
556 20:24:18.052150 MVN_1=0x00000000
557 20:24:18.056838 MVN_2=0x00000000
558 20:24:18.062535 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 20:24:18.063256 OPS=0x10
560 20:24:18.063871 ring efuse init
561 20:24:18.064610 chipver efuse init
562 20:24:18.068074 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 20:24:18.073648 [0.018961 Inits done]
564 20:24:18.074132 secure task start!
565 20:24:18.074568 high task start!
566 20:24:18.077807 low task start!
567 20:24:18.078288 run into bl31
568 20:24:18.085091 NOTICE: BL31: v1.3(release):4fc40b1
569 20:24:18.092425 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 20:24:18.092913 NOTICE: BL31: G12A normal boot!
571 20:24:18.118149 NOTICE: BL31: BL33 decompress pass
572 20:24:18.123133 ERROR: Error initializing runtime service opteed_fast
573 20:24:19.356434
574 20:24:19.356840
575 20:24:19.364126 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 20:24:19.364449
577 20:24:19.364690 Model: Libre Computer AML-A311D-CC Alta
578 20:24:19.572813 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 20:24:19.596388 DRAM: 2 GiB (effective 3.8 GiB)
580 20:24:19.739804 Core: 408 devices, 31 uclasses, devicetree: separate
581 20:24:19.745383 WDT: Not starting watchdog@f0d0
582 20:24:19.777989 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 20:24:19.790271 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 20:24:19.794937 ** Bad device specification mmc 0 **
585 20:24:19.805832 Card did not respond to voltage select! : -110
586 20:24:19.812807 ** Bad device specification mmc 0 **
587 20:24:19.813123 Couldn't find partition mmc 0
588 20:24:19.821686 Card did not respond to voltage select! : -110
589 20:24:19.827246 ** Bad device specification mmc 0 **
590 20:24:19.827548 Couldn't find partition mmc 0
591 20:24:19.831493 Error: could not access storage.
592 20:24:20.175225 Net: eth0: ethernet@ff3f0000
593 20:24:20.175852 starting USB...
594 20:24:20.427844 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 20:24:20.428519 Starting the controller
596 20:24:20.434600 USB XHCI 1.10
597 20:24:22.146952 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 20:24:22.147604 bl2_stage_init 0x01
599 20:24:22.148119 bl2_stage_init 0x81
600 20:24:22.152536 hw id: 0x0000 - pwm id 0x01
601 20:24:22.153041 bl2_stage_init 0xc1
602 20:24:22.153497 bl2_stage_init 0x02
603 20:24:22.153943
604 20:24:22.157921 L0:00000000
605 20:24:22.158419 L1:20000703
606 20:24:22.158869 L2:00008067
607 20:24:22.159312 L3:14000000
608 20:24:22.160951 B2:00402000
609 20:24:22.161449 B1:e0f83180
610 20:24:22.161899
611 20:24:22.162348 TE: 58167
612 20:24:22.162792
613 20:24:22.172070 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 20:24:22.172606
615 20:24:22.173064 Board ID = 1
616 20:24:22.173513 Set A53 clk to 24M
617 20:24:22.173955 Set A73 clk to 24M
618 20:24:22.177747 Set clk81 to 24M
619 20:24:22.178364 A53 clk: 1200 MHz
620 20:24:22.178861 A73 clk: 1200 MHz
621 20:24:22.183266 CLK81: 166.6M
622 20:24:22.183772 smccc: 00012abe
623 20:24:22.188849 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 20:24:22.189358 board id: 1
625 20:24:22.197474 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 20:24:22.208102 fw parse done
627 20:24:22.213124 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 20:24:22.256741 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 20:24:22.267630 PIEI prepare done
630 20:24:22.268176 fastboot data load
631 20:24:22.268641 fastboot data verify
632 20:24:22.273311 verify result: 266
633 20:24:22.278924 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 20:24:22.279476 LPDDR4 probe
635 20:24:22.279935 ddr clk to 1584MHz
636 20:24:22.286860 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 20:24:22.324193
638 20:24:22.324744 dmc_version 0001
639 20:24:22.330819 Check phy result
640 20:24:22.336688 INFO : End of CA training
641 20:24:22.337214 INFO : End of initialization
642 20:24:22.342289 INFO : Training has run successfully!
643 20:24:22.342828 Check phy result
644 20:24:22.347902 INFO : End of initialization
645 20:24:22.348467 INFO : End of read enable training
646 20:24:22.353499 INFO : End of fine write leveling
647 20:24:22.359041 INFO : End of Write leveling coarse delay
648 20:24:22.359571 INFO : Training has run successfully!
649 20:24:22.360071 Check phy result
650 20:24:22.364700 INFO : End of initialization
651 20:24:22.365232 INFO : End of read dq deskew training
652 20:24:22.370247 INFO : End of MPR read delay center optimization
653 20:24:22.375962 INFO : End of write delay center optimization
654 20:24:22.381543 INFO : End of read delay center optimization
655 20:24:22.382085 INFO : End of max read latency training
656 20:24:22.387078 INFO : Training has run successfully!
657 20:24:22.387607 1D training succeed
658 20:24:22.396257 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 20:24:22.443882 Check phy result
660 20:24:22.444462 INFO : End of initialization
661 20:24:22.465700 INFO : End of 2D read delay Voltage center optimization
662 20:24:22.485955 INFO : End of 2D read delay Voltage center optimization
663 20:24:22.537982 INFO : End of 2D write delay Voltage center optimization
664 20:24:22.587362 INFO : End of 2D write delay Voltage center optimization
665 20:24:22.592871 INFO : Training has run successfully!
666 20:24:22.593395
667 20:24:22.593871 channel==0
668 20:24:22.598670 RxClkDly_Margin_A0==88 ps 9
669 20:24:22.599208 TxDqDly_Margin_A0==98 ps 10
670 20:24:22.604171 RxClkDly_Margin_A1==88 ps 9
671 20:24:22.604695 TxDqDly_Margin_A1==98 ps 10
672 20:24:22.605159 TrainedVREFDQ_A0==74
673 20:24:22.609820 TrainedVREFDQ_A1==74
674 20:24:22.610344 VrefDac_Margin_A0==25
675 20:24:22.610794 DeviceVref_Margin_A0==40
676 20:24:22.615256 VrefDac_Margin_A1==25
677 20:24:22.615769 DeviceVref_Margin_A1==40
678 20:24:22.616260
679 20:24:22.616709
680 20:24:22.620864 channel==1
681 20:24:22.621387 RxClkDly_Margin_A0==98 ps 10
682 20:24:22.621835 TxDqDly_Margin_A0==88 ps 9
683 20:24:22.626613 RxClkDly_Margin_A1==98 ps 10
684 20:24:22.627130 TxDqDly_Margin_A1==88 ps 9
685 20:24:22.632126 TrainedVREFDQ_A0==76
686 20:24:22.632644 TrainedVREFDQ_A1==77
687 20:24:22.633095 VrefDac_Margin_A0==22
688 20:24:22.637614 DeviceVref_Margin_A0==38
689 20:24:22.638126 VrefDac_Margin_A1==22
690 20:24:22.643309 DeviceVref_Margin_A1==37
691 20:24:22.643824
692 20:24:22.644311 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 20:24:22.644755
694 20:24:22.676845 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 20:24:22.677528 2D training succeed
696 20:24:22.682485 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 20:24:22.687972 auto size-- 65535DDR cs0 size: 2048MB
698 20:24:22.688531 DDR cs1 size: 2048MB
699 20:24:22.693601 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 20:24:22.694120 cs0 DataBus test pass
701 20:24:22.699181 cs1 DataBus test pass
702 20:24:22.699693 cs0 AddrBus test pass
703 20:24:22.700196 cs1 AddrBus test pass
704 20:24:22.700643
705 20:24:22.704810 100bdlr_step_size ps== 420
706 20:24:22.705336 result report
707 20:24:22.710414 boot times 0Enable ddr reg access
708 20:24:22.715755 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 20:24:22.729196 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 20:24:23.302635 0.0;M3 CHK:0;cm4_sp_mode 0
711 20:24:23.303054 MVN_1=0x00000000
712 20:24:23.308202 MVN_2=0x00000000
713 20:24:23.313955 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 20:24:23.314493 OPS=0x10
715 20:24:23.314961 ring efuse init
716 20:24:23.315393 chipver efuse init
717 20:24:23.319528 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 20:24:23.325176 [0.018961 Inits done]
719 20:24:23.325705 secure task start!
720 20:24:23.326103 high task start!
721 20:24:23.329758 low task start!
722 20:24:23.330198 run into bl31
723 20:24:23.336402 NOTICE: BL31: v1.3(release):4fc40b1
724 20:24:23.344200 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 20:24:23.344655 NOTICE: BL31: G12A normal boot!
726 20:24:23.369636 NOTICE: BL31: BL33 decompress pass
727 20:24:23.375309 ERROR: Error initializing runtime service opteed_fast
728 20:24:24.608248
729 20:24:24.608644
730 20:24:24.616708 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 20:24:24.617035
732 20:24:24.617260 Model: Libre Computer AML-A311D-CC Alta
733 20:24:24.825054 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 20:24:24.848450 DRAM: 2 GiB (effective 3.8 GiB)
735 20:24:24.991468 Core: 408 devices, 31 uclasses, devicetree: separate
736 20:24:24.997282 WDT: Not starting watchdog@f0d0
737 20:24:25.029554 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 20:24:25.042013 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 20:24:25.046966 ** Bad device specification mmc 0 **
740 20:24:25.057297 Card did not respond to voltage select! : -110
741 20:24:25.064969 ** Bad device specification mmc 0 **
742 20:24:25.065296 Couldn't find partition mmc 0
743 20:24:25.073292 Card did not respond to voltage select! : -110
744 20:24:25.078785 ** Bad device specification mmc 0 **
745 20:24:25.079252 Couldn't find partition mmc 0
746 20:24:25.083860 Error: could not access storage.
747 20:24:25.427429 Net: eth0: ethernet@ff3f0000
748 20:24:25.427829 starting USB...
749 20:24:25.679307 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 20:24:25.679747 Starting the controller
751 20:24:25.686175 USB XHCI 1.10
752 20:24:27.845462 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
753 20:24:27.846146 bl2_stage_init 0x81
754 20:24:27.851131 hw id: 0x0000 - pwm id 0x01
755 20:24:27.851883 bl2_stage_init 0xc1
756 20:24:27.852619 bl2_stage_init 0x02
757 20:24:27.853262
758 20:24:27.856592 L0:00000000
759 20:24:27.857116 L1:20000703
760 20:24:27.857584 L2:00008067
761 20:24:27.858026 L3:14000000
762 20:24:27.858472 B2:00402000
763 20:24:27.862342 B1:e0f83180
764 20:24:27.862850
765 20:24:27.863330 TE: 58150
766 20:24:27.863793
767 20:24:27.867685 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 20:24:27.868241
769 20:24:27.868720 Board ID = 1
770 20:24:27.873307 Set A53 clk to 24M
771 20:24:27.873843 Set A73 clk to 24M
772 20:24:27.874335 Set clk81 to 24M
773 20:24:27.878959 A53 clk: 1200 MHz
774 20:24:27.879493 A73 clk: 1200 MHz
775 20:24:27.879951 CLK81: 166.6M
776 20:24:27.880424 smccc: 00012aab
777 20:24:27.884490 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 20:24:27.890154 board id: 1
779 20:24:27.896098 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 20:24:27.906591 fw parse done
781 20:24:27.912531 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 20:24:27.955344 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 20:24:27.966279 PIEI prepare done
784 20:24:27.966832 fastboot data load
785 20:24:27.967310 fastboot data verify
786 20:24:27.971800 verify result: 266
787 20:24:27.977373 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 20:24:27.978129 LPDDR4 probe
789 20:24:27.978794 ddr clk to 1584MHz
790 20:24:27.985319 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 20:24:28.022515
792 20:24:28.023337 dmc_version 0001
793 20:24:28.029165 Check phy result
794 20:24:28.035026 INFO : End of CA training
795 20:24:28.035368 INFO : End of initialization
796 20:24:28.040755 INFO : Training has run successfully!
797 20:24:28.041097 Check phy result
798 20:24:28.046267 INFO : End of initialization
799 20:24:28.046609 INFO : End of read enable training
800 20:24:28.051803 INFO : End of fine write leveling
801 20:24:28.057612 INFO : End of Write leveling coarse delay
802 20:24:28.058175 INFO : Training has run successfully!
803 20:24:28.058622 Check phy result
804 20:24:28.063189 INFO : End of initialization
805 20:24:28.063735 INFO : End of read dq deskew training
806 20:24:28.068746 INFO : End of MPR read delay center optimization
807 20:24:28.074350 INFO : End of write delay center optimization
808 20:24:28.079937 INFO : End of read delay center optimization
809 20:24:28.080526 INFO : End of max read latency training
810 20:24:28.085538 INFO : Training has run successfully!
811 20:24:28.086085 1D training succeed
812 20:24:28.094672 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 20:24:28.142330 Check phy result
814 20:24:28.142916 INFO : End of initialization
815 20:24:28.164074 INFO : End of 2D read delay Voltage center optimization
816 20:24:28.184341 INFO : End of 2D read delay Voltage center optimization
817 20:24:28.236361 INFO : End of 2D write delay Voltage center optimization
818 20:24:28.285778 INFO : End of 2D write delay Voltage center optimization
819 20:24:28.291451 INFO : Training has run successfully!
820 20:24:28.292052
821 20:24:28.292517 channel==0
822 20:24:28.296945 RxClkDly_Margin_A0==88 ps 9
823 20:24:28.297485 TxDqDly_Margin_A0==98 ps 10
824 20:24:28.300396 RxClkDly_Margin_A1==88 ps 9
825 20:24:28.300949 TxDqDly_Margin_A1==98 ps 10
826 20:24:28.305799 TrainedVREFDQ_A0==74
827 20:24:28.306337 TrainedVREFDQ_A1==74
828 20:24:28.306782 VrefDac_Margin_A0==25
829 20:24:28.311371 DeviceVref_Margin_A0==40
830 20:24:28.311902 VrefDac_Margin_A1==25
831 20:24:28.317058 DeviceVref_Margin_A1==40
832 20:24:28.317599
833 20:24:28.318041
834 20:24:28.318474 channel==1
835 20:24:28.318907 RxClkDly_Margin_A0==98 ps 10
836 20:24:28.320554 TxDqDly_Margin_A0==88 ps 9
837 20:24:28.326200 RxClkDly_Margin_A1==88 ps 9
838 20:24:28.326730 TxDqDly_Margin_A1==88 ps 9
839 20:24:28.327171 TrainedVREFDQ_A0==76
840 20:24:28.331698 TrainedVREFDQ_A1==77
841 20:24:28.332268 VrefDac_Margin_A0==22
842 20:24:28.337411 DeviceVref_Margin_A0==38
843 20:24:28.337934 VrefDac_Margin_A1==24
844 20:24:28.338366 DeviceVref_Margin_A1==37
845 20:24:28.338795
846 20:24:28.342940 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 20:24:28.343479
848 20:24:28.376580 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 20:24:28.377203 2D training succeed
850 20:24:28.382218 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 20:24:28.387644 auto size-- 65535DDR cs0 size: 2048MB
852 20:24:28.388237 DDR cs1 size: 2048MB
853 20:24:28.393317 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 20:24:28.393880 cs0 DataBus test pass
855 20:24:28.394330 cs1 DataBus test pass
856 20:24:28.398884 cs0 AddrBus test pass
857 20:24:28.399438 cs1 AddrBus test pass
858 20:24:28.399875
859 20:24:28.404453 100bdlr_step_size ps== 420
860 20:24:28.405010 result report
861 20:24:28.405445 boot times 0Enable ddr reg access
862 20:24:28.414069 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 20:24:28.427539 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 20:24:29.001179 0.0;M3 CHK:0;cm4_sp_mode 0
865 20:24:29.001876 MVN_1=0x00000000
866 20:24:29.006685 MVN_2=0x00000000
867 20:24:29.012432 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 20:24:29.012997 OPS=0x10
869 20:24:29.013485 ring efuse init
870 20:24:29.013946 chipver efuse init
871 20:24:29.018049 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 20:24:29.023582 [0.018961 Inits done]
873 20:24:29.024165 secure task start!
874 20:24:29.024616 high task start!
875 20:24:29.028234 low task start!
876 20:24:29.028786 run into bl31
877 20:24:29.034879 NOTICE: BL31: v1.3(release):4fc40b1
878 20:24:29.042719 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 20:24:29.043332 NOTICE: BL31: G12A normal boot!
880 20:24:29.068623 NOTICE: BL31: BL33 decompress pass
881 20:24:29.074384 ERROR: Error initializing runtime service opteed_fast
882 20:24:30.307109
883 20:24:30.307794
884 20:24:30.315547 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 20:24:30.316153
886 20:24:30.316633 Model: Libre Computer AML-A311D-CC Alta
887 20:24:30.523832 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 20:24:30.547252 DRAM: 2 GiB (effective 3.8 GiB)
889 20:24:30.690466 Core: 408 devices, 31 uclasses, devicetree: separate
890 20:24:30.696298 WDT: Not starting watchdog@f0d0
891 20:24:30.728645 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 20:24:30.741004 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 20:24:30.745980 ** Bad device specification mmc 0 **
894 20:24:30.756384 Card did not respond to voltage select! : -110
895 20:24:30.764033 ** Bad device specification mmc 0 **
896 20:24:30.764666 Couldn't find partition mmc 0
897 20:24:30.772354 Card did not respond to voltage select! : -110
898 20:24:30.777815 ** Bad device specification mmc 0 **
899 20:24:30.778385 Couldn't find partition mmc 0
900 20:24:30.782935 Error: could not access storage.
901 20:24:31.126381 Net: eth0: ethernet@ff3f0000
902 20:24:31.126798 starting USB...
903 20:24:31.378113 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 20:24:31.378514 Starting the controller
905 20:24:31.384998 USB XHCI 1.10
906 20:24:32.938972 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 20:24:32.947273 scanning usb for storage devices... 0 Storage Device(s) found
909 20:24:32.998377 Hit any key to stop autoboot: 1
910 20:24:32.999031 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 20:24:32.999471 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 20:24:32.999730 Setting prompt string to ['=>']
913 20:24:33.000008 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 20:24:33.004821 0
915 20:24:33.005412 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 20:24:33.005691 Sending with 10 millisecond of delay
918 20:24:34.140714 => setenv autoload no
919 20:24:34.151560 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 20:24:34.156915 setenv autoload no
921 20:24:34.157701 Sending with 10 millisecond of delay
923 20:24:35.957810 => setenv initrd_high 0xffffffff
924 20:24:35.968606 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 20:24:35.969246 setenv initrd_high 0xffffffff
926 20:24:35.969771 Sending with 10 millisecond of delay
928 20:24:37.586129 => setenv fdt_high 0xffffffff
929 20:24:37.596950 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 20:24:37.597875 setenv fdt_high 0xffffffff
931 20:24:37.598642 Sending with 10 millisecond of delay
933 20:24:37.890704 => dhcp
934 20:24:37.901537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 20:24:37.902495 dhcp
936 20:24:37.902977 Speed: 1000, full duplex
937 20:24:37.903435 BOOTP broadcast 1
938 20:24:38.121033 DHCP client bound to address 192.168.6.27 (220 ms)
939 20:24:38.121715 Sending with 10 millisecond of delay
941 20:24:39.799540 => setenv serverip 192.168.6.2
942 20:24:39.810161 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
943 20:24:39.810769 setenv serverip 192.168.6.2
944 20:24:39.811433 Sending with 10 millisecond of delay
946 20:24:43.539747 => tftpboot 0x01080000 930651/tftp-deploy-zl4v3yje/kernel/uImage
947 20:24:43.550488 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
948 20:24:43.551136 tftpboot 0x01080000 930651/tftp-deploy-zl4v3yje/kernel/uImage
949 20:24:43.551499 Speed: 1000, full duplex
950 20:24:43.551789 Using ethernet@ff3f0000 device
951 20:24:43.553076 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
952 20:24:43.558601 Filename '930651/tftp-deploy-zl4v3yje/kernel/uImage'.
953 20:24:43.562556 Load address: 0x1080000
954 20:24:47.380255 Loading: *################# UDP wrong checksum 000000ff 0000dabc
955 20:24:47.420152 # UDP wrong checksum 000000ff 00005faf
956 20:24:47.778277 #
957 20:24:47.778688 TFTP error: trying to overwrite reserved memory...
959 20:24:47.779511 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
962 20:24:47.780462 end: 2.4 uboot-commands (duration 00:00:47) [common]
964 20:24:47.781140 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
966 20:24:47.781675 end: 2 uboot-action (duration 00:00:47) [common]
968 20:24:47.782454 Cleaning after the job
969 20:24:47.782758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/ramdisk
970 20:24:47.812406 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/kernel
971 20:24:47.825479 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/dtb
972 20:24:47.826609 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930651/tftp-deploy-zl4v3yje/modules
973 20:24:47.835352 start: 4.1 power-off (timeout 00:00:30) [common]
974 20:24:47.835938 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
975 20:24:47.872979 >> OK - accepted request
976 20:24:47.875250 Returned 0 in 0 seconds
977 20:24:47.976138 end: 4.1 power-off (duration 00:00:00) [common]
979 20:24:47.977869 start: 4.2 read-feedback (timeout 00:10:00) [common]
980 20:24:47.979054 Listened to connection for namespace 'common' for up to 1s
981 20:24:48.979212 Finalising connection for namespace 'common'
982 20:24:48.980057 Disconnecting from shell: Finalise
983 20:24:48.980607 =>
984 20:24:49.081642 end: 4.2 read-feedback (duration 00:00:01) [common]
985 20:24:49.082378 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/930651
986 20:24:49.395537 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/930651
987 20:24:49.396170 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.