Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:22:42.884242 lava-dispatcher, installed at version: 2024.01
2 20:22:42.885011 start: 0 validate
3 20:22:42.885465 Start time: 2024-11-03 20:22:42.885435+00:00 (UTC)
4 20:22:42.886020 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:22:42.886539 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:22:42.926106 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:22:42.926674 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 20:22:42.958828 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:22:42.959479 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:22:44.006677 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:22:44.007171 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 20:22:44.049671 validate duration: 1.16
14 20:22:44.050558 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:22:44.050892 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:22:44.051208 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:22:44.051790 Not decompressing ramdisk as can be used compressed.
18 20:22:44.052245 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:22:44.052522 saving as /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/ramdisk/rootfs.cpio.gz
20 20:22:44.052801 total size: 8181887 (7 MB)
21 20:22:44.093939 progress 0 % (0 MB)
22 20:22:44.104136 progress 5 % (0 MB)
23 20:22:44.114250 progress 10 % (0 MB)
24 20:22:44.124600 progress 15 % (1 MB)
25 20:22:44.129821 progress 20 % (1 MB)
26 20:22:44.135505 progress 25 % (1 MB)
27 20:22:44.140638 progress 30 % (2 MB)
28 20:22:44.146231 progress 35 % (2 MB)
29 20:22:44.151369 progress 40 % (3 MB)
30 20:22:44.157041 progress 45 % (3 MB)
31 20:22:44.162140 progress 50 % (3 MB)
32 20:22:44.167729 progress 55 % (4 MB)
33 20:22:44.172899 progress 60 % (4 MB)
34 20:22:44.178524 progress 65 % (5 MB)
35 20:22:44.183720 progress 70 % (5 MB)
36 20:22:44.189275 progress 75 % (5 MB)
37 20:22:44.194341 progress 80 % (6 MB)
38 20:22:44.199950 progress 85 % (6 MB)
39 20:22:44.205230 progress 90 % (7 MB)
40 20:22:44.210818 progress 95 % (7 MB)
41 20:22:44.215615 progress 100 % (7 MB)
42 20:22:44.216318 7 MB downloaded in 0.16 s (47.73 MB/s)
43 20:22:44.216934 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:22:44.217905 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:22:44.218244 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:22:44.218554 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:22:44.219057 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/kernel/Image
49 20:22:44.219329 saving as /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/kernel/Image
50 20:22:44.219557 total size: 169943552 (162 MB)
51 20:22:44.219787 No compression specified
52 20:22:44.253680 progress 0 % (0 MB)
53 20:22:44.355719 progress 5 % (8 MB)
54 20:22:44.457349 progress 10 % (16 MB)
55 20:22:44.558704 progress 15 % (24 MB)
56 20:22:44.660559 progress 20 % (32 MB)
57 20:22:44.761603 progress 25 % (40 MB)
58 20:22:44.862883 progress 30 % (48 MB)
59 20:22:44.963881 progress 35 % (56 MB)
60 20:22:45.065099 progress 40 % (64 MB)
61 20:22:45.166019 progress 45 % (72 MB)
62 20:22:45.267942 progress 50 % (81 MB)
63 20:22:45.369609 progress 55 % (89 MB)
64 20:22:45.471716 progress 60 % (97 MB)
65 20:22:45.573035 progress 65 % (105 MB)
66 20:22:45.676821 progress 70 % (113 MB)
67 20:22:45.779159 progress 75 % (121 MB)
68 20:22:45.880999 progress 80 % (129 MB)
69 20:22:45.982281 progress 85 % (137 MB)
70 20:22:46.084080 progress 90 % (145 MB)
71 20:22:46.185434 progress 95 % (153 MB)
72 20:22:46.287538 progress 100 % (162 MB)
73 20:22:46.288190 162 MB downloaded in 2.07 s (78.35 MB/s)
74 20:22:46.288710 end: 1.2.1 http-download (duration 00:00:02) [common]
76 20:22:46.289567 end: 1.2 download-retry (duration 00:00:02) [common]
77 20:22:46.289869 start: 1.3 download-retry (timeout 00:09:58) [common]
78 20:22:46.290152 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 20:22:46.290644 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:22:46.290926 saving as /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:22:46.291147 total size: 53209 (0 MB)
82 20:22:46.291370 No compression specified
83 20:22:46.329860 progress 61 % (0 MB)
84 20:22:46.330709 progress 100 % (0 MB)
85 20:22:46.331268 0 MB downloaded in 0.04 s (1.27 MB/s)
86 20:22:46.331742 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:22:46.332627 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:22:46.332910 start: 1.4 download-retry (timeout 00:09:58) [common]
90 20:22:46.333188 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 20:22:46.333653 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 20:22:46.333907 saving as /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/modules/modules.tar
93 20:22:46.334126 total size: 27642748 (26 MB)
94 20:22:46.334346 Using unxz to decompress xz
95 20:22:46.368298 progress 0 % (0 MB)
96 20:22:46.553248 progress 5 % (1 MB)
97 20:22:46.749754 progress 10 % (2 MB)
98 20:22:46.975964 progress 15 % (3 MB)
99 20:22:47.207188 progress 20 % (5 MB)
100 20:22:47.404879 progress 25 % (6 MB)
101 20:22:47.608854 progress 30 % (7 MB)
102 20:22:47.809032 progress 35 % (9 MB)
103 20:22:48.001217 progress 40 % (10 MB)
104 20:22:48.192874 progress 45 % (11 MB)
105 20:22:48.403471 progress 50 % (13 MB)
106 20:22:48.605558 progress 55 % (14 MB)
107 20:22:48.828055 progress 60 % (15 MB)
108 20:22:49.034439 progress 65 % (17 MB)
109 20:22:49.237655 progress 70 % (18 MB)
110 20:22:49.444686 progress 75 % (19 MB)
111 20:22:49.645029 progress 80 % (21 MB)
112 20:22:49.856364 progress 85 % (22 MB)
113 20:22:50.059809 progress 90 % (23 MB)
114 20:22:50.256371 progress 95 % (25 MB)
115 20:22:50.455655 progress 100 % (26 MB)
116 20:22:50.468280 26 MB downloaded in 4.13 s (6.38 MB/s)
117 20:22:50.468961 end: 1.4.1 http-download (duration 00:00:04) [common]
119 20:22:50.469907 end: 1.4 download-retry (duration 00:00:04) [common]
120 20:22:50.470223 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 20:22:50.470523 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 20:22:50.470807 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:22:50.471101 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 20:22:50.471883 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5
125 20:22:50.472748 makedir: /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin
126 20:22:50.473398 makedir: /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/tests
127 20:22:50.474012 makedir: /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/results
128 20:22:50.474612 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-add-keys
129 20:22:50.475537 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-add-sources
130 20:22:50.476494 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-background-process-start
131 20:22:50.477546 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-background-process-stop
132 20:22:50.478541 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-common-functions
133 20:22:50.479457 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-echo-ipv4
134 20:22:50.480392 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-install-packages
135 20:22:50.481286 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-installed-packages
136 20:22:50.482187 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-os-build
137 20:22:50.483108 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-probe-channel
138 20:22:50.484069 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-probe-ip
139 20:22:50.484982 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-target-ip
140 20:22:50.485894 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-target-mac
141 20:22:50.486771 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-target-storage
142 20:22:50.487685 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-case
143 20:22:50.488631 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-event
144 20:22:50.489530 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-feedback
145 20:22:50.490432 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-raise
146 20:22:50.491309 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-reference
147 20:22:50.492234 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-runner
148 20:22:50.493130 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-set
149 20:22:50.494002 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-test-shell
150 20:22:50.494903 Updating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-install-packages (oe)
151 20:22:50.495876 Updating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/bin/lava-installed-packages (oe)
152 20:22:50.496814 Creating /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/environment
153 20:22:50.497519 LAVA metadata
154 20:22:50.497995 - LAVA_JOB_ID=930622
155 20:22:50.498437 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:22:50.499121 start: 1.5.2.1 ssh-authorize (timeout 00:09:54) [common]
157 20:22:50.500938 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:22:50.501528 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:54) [common]
159 20:22:50.501936 skipped lava-vland-overlay
160 20:22:50.502423 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:22:50.502927 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:54) [common]
162 20:22:50.503349 skipped lava-multinode-overlay
163 20:22:50.503827 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:22:50.504220 start: 1.5.2.4 test-definition (timeout 00:09:54) [common]
165 20:22:50.504480 Loading test definitions
166 20:22:50.504765 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:54) [common]
167 20:22:50.504991 Using /lava-930622 at stage 0
168 20:22:50.506208 uuid=930622_1.5.2.4.1 testdef=None
169 20:22:50.506522 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:22:50.506791 start: 1.5.2.4.2 test-overlay (timeout 00:09:54) [common]
171 20:22:50.508785 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:22:50.509609 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:54) [common]
174 20:22:50.511929 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:22:50.512790 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:54) [common]
177 20:22:50.515059 runner path: /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/0/tests/0_dmesg test_uuid 930622_1.5.2.4.1
178 20:22:50.515642 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:22:50.516442 Creating lava-test-runner.conf files
181 20:22:50.516649 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/930622/lava-overlay-xk3hs1k5/lava-930622/0 for stage 0
182 20:22:50.517002 - 0_dmesg
183 20:22:50.517351 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:22:50.517632 start: 1.5.2.5 compress-overlay (timeout 00:09:54) [common]
185 20:22:50.541959 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:22:50.542390 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:54) [common]
187 20:22:50.542655 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:22:50.542921 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:22:50.543185 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
190 20:22:51.487266 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:22:51.487738 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
192 20:22:51.488010 extracting modules file /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk
193 20:22:53.161597 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 20:22:53.162070 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 20:22:53.162343 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930622/compress-overlay-15f9a1p1/overlay-1.5.2.5.tar.gz to ramdisk
196 20:22:53.162554 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930622/compress-overlay-15f9a1p1/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk
197 20:22:53.192569 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:22:53.192967 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 20:22:53.193231 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 20:22:53.193452 Converting downloaded kernel to a uImage
201 20:22:53.193753 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/kernel/Image /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/kernel/uImage
202 20:22:54.893245 output: Image Name:
203 20:22:54.893676 output: Created: Sun Nov 3 20:22:53 2024
204 20:22:54.893905 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:22:54.894123 output: Data Size: 169943552 Bytes = 165960.50 KiB = 162.07 MiB
206 20:22:54.894331 output: Load Address: 01080000
207 20:22:54.894536 output: Entry Point: 01080000
208 20:22:54.894737 output:
209 20:22:54.895074 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 20:22:54.895351 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 20:22:54.895634 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 20:22:54.895898 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:22:54.896223 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 20:22:54.896505 Building ramdisk /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk
215 20:23:00.577835 >> 441542 blocks
216 20:23:19.619140 Adding RAMdisk u-boot header.
217 20:23:19.620031 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk.cpio.gz.uboot
218 20:23:20.179547 output: Image Name:
219 20:23:20.180409 output: Created: Sun Nov 3 20:23:19 2024
220 20:23:20.180942 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:23:20.181455 output: Data Size: 53579929 Bytes = 52324.15 KiB = 51.10 MiB
222 20:23:20.181968 output: Load Address: 00000000
223 20:23:20.182473 output: Entry Point: 00000000
224 20:23:20.182973 output:
225 20:23:20.184213 rename /var/lib/lava/dispatcher/tmp/930622/extract-overlay-ramdisk-13dj0r1z/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/ramdisk/ramdisk.cpio.gz.uboot
226 20:23:20.185121 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 20:23:20.185807 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 20:23:20.186478 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 20:23:20.187070 No LXC device requested
230 20:23:20.187703 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:23:20.188395 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 20:23:20.189037 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:23:20.189587 Checking files for TFTP limit of 4294967296 bytes.
234 20:23:20.193038 end: 1 tftp-deploy (duration 00:00:36) [common]
235 20:23:20.193766 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:23:20.194438 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:23:20.195074 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:23:20.195709 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:23:20.196415 Using kernel file from prepare-kernel: 930622/tftp-deploy-0o969f0f/kernel/uImage
240 20:23:20.197194 substitutions:
241 20:23:20.197711 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:23:20.198222 - {DTB_ADDR}: 0x01070000
243 20:23:20.198727 - {DTB}: 930622/tftp-deploy-0o969f0f/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:23:20.199236 - {INITRD}: 930622/tftp-deploy-0o969f0f/ramdisk/ramdisk.cpio.gz.uboot
245 20:23:20.199740 - {KERNEL_ADDR}: 0x01080000
246 20:23:20.200282 - {KERNEL}: 930622/tftp-deploy-0o969f0f/kernel/uImage
247 20:23:20.200789 - {LAVA_MAC}: None
248 20:23:20.201340 - {PRESEED_CONFIG}: None
249 20:23:20.201843 - {PRESEED_LOCAL}: None
250 20:23:20.202341 - {RAMDISK_ADDR}: 0x08000000
251 20:23:20.202863 - {RAMDISK}: 930622/tftp-deploy-0o969f0f/ramdisk/ramdisk.cpio.gz.uboot
252 20:23:20.203379 - {ROOT_PART}: None
253 20:23:20.203879 - {ROOT}: None
254 20:23:20.204417 - {SERVER_IP}: 192.168.6.2
255 20:23:20.204936 - {TEE_ADDR}: 0x83000000
256 20:23:20.205444 - {TEE}: None
257 20:23:20.205958 Parsed boot commands:
258 20:23:20.206450 - setenv autoload no
259 20:23:20.206967 - setenv initrd_high 0xffffffff
260 20:23:20.207482 - setenv fdt_high 0xffffffff
261 20:23:20.208063 - dhcp
262 20:23:20.208583 - setenv serverip 192.168.6.2
263 20:23:20.209091 - tftpboot 0x01080000 930622/tftp-deploy-0o969f0f/kernel/uImage
264 20:23:20.209597 - tftpboot 0x08000000 930622/tftp-deploy-0o969f0f/ramdisk/ramdisk.cpio.gz.uboot
265 20:23:20.210102 - tftpboot 0x01070000 930622/tftp-deploy-0o969f0f/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:23:20.210602 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:23:20.211114 - bootm 0x01080000 0x08000000 0x01070000
268 20:23:20.211813 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:23:20.213820 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:23:20.214417 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:23:20.230228 Setting prompt string to ['lava-test: # ']
273 20:23:20.232155 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:23:20.232983 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:23:20.233714 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:23:20.234404 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:23:20.235875 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:23:20.274522 >> OK - accepted request
279 20:23:20.277303 Returned 0 in 0 seconds
280 20:23:20.378470 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:23:20.380236 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:23:20.380848 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:23:20.381369 Setting prompt string to ['Hit any key to stop autoboot']
285 20:23:20.381845 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:23:20.383442 Trying 192.168.56.21...
287 20:23:20.383954 Connected to conserv1.
288 20:23:20.384429 Escape character is '^]'.
289 20:23:20.384869
290 20:23:20.385315 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:23:20.385747
292 20:23:28.431490 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:23:28.432172 bl2_stage_init 0x01
294 20:23:28.432632 bl2_stage_init 0x81
295 20:23:28.437101 hw id: 0x0000 - pwm id 0x01
296 20:23:28.437801 bl2_stage_init 0xc1
297 20:23:28.438286 bl2_stage_init 0x02
298 20:23:28.438725
299 20:23:28.442563 L0:00000000
300 20:23:28.442886 L1:00000703
301 20:23:28.443107 L2:00008067
302 20:23:28.443332 L3:15000000
303 20:23:28.443558 S1:00000000
304 20:23:28.448321 B2:20282000
305 20:23:28.449031 B1:a0f83180
306 20:23:28.449578
307 20:23:28.449891 TE: 69557
308 20:23:28.450190
309 20:23:28.453908 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:23:28.454558
311 20:23:28.459438 Board ID = 1
312 20:23:28.460061 Set cpu clk to 24M
313 20:23:28.460605 Set clk81 to 24M
314 20:23:28.465012 Use GP1_pll as DSU clk.
315 20:23:28.465613 DSU clk: 1200 Mhz
316 20:23:28.466151 CPU clk: 1200 MHz
317 20:23:28.466685 Set clk81 to 166.6M
318 20:23:28.476181 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:23:28.476781 board id: 1
320 20:23:28.482508 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:23:28.493161 fw parse done
322 20:23:28.499134 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:23:28.541883 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:23:28.552745 PIEI prepare done
325 20:23:28.553381 fastboot data load
326 20:23:28.553954 fastboot data verify
327 20:23:28.558355 verify result: 266
328 20:23:28.563968 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:23:28.564600 LPDDR4 probe
330 20:23:28.565135 ddr clk to 1584MHz
331 20:23:28.571972 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:23:28.609292
333 20:23:28.610057 dmc_version 0001
334 20:23:28.615829 Check phy result
335 20:23:28.621809 INFO : End of CA training
336 20:23:28.622450 INFO : End of initialization
337 20:23:28.627382 INFO : Training has run successfully!
338 20:23:28.627950 Check phy result
339 20:23:28.632994 INFO : End of initialization
340 20:23:28.633570 INFO : End of read enable training
341 20:23:28.636261 INFO : End of fine write leveling
342 20:23:28.641851 INFO : End of Write leveling coarse delay
343 20:23:28.647376 INFO : Training has run successfully!
344 20:23:28.647949 Check phy result
345 20:23:28.648528 INFO : End of initialization
346 20:23:28.653000 INFO : End of read dq deskew training
347 20:23:28.656471 INFO : End of MPR read delay center optimization
348 20:23:28.662027 INFO : End of write delay center optimization
349 20:23:28.667634 INFO : End of read delay center optimization
350 20:23:28.668247 INFO : End of max read latency training
351 20:23:28.673196 INFO : Training has run successfully!
352 20:23:28.673767 1D training succeed
353 20:23:28.681357 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:23:28.729032 Check phy result
355 20:23:28.729843 INFO : End of initialization
356 20:23:28.751420 INFO : End of 2D read delay Voltage center optimization
357 20:23:28.770510 INFO : End of 2D read delay Voltage center optimization
358 20:23:28.822420 INFO : End of 2D write delay Voltage center optimization
359 20:23:28.871666 INFO : End of 2D write delay Voltage center optimization
360 20:23:28.877159 INFO : Training has run successfully!
361 20:23:28.877758
362 20:23:28.878194 channel==0
363 20:23:28.882835 RxClkDly_Margin_A0==78 ps 8
364 20:23:28.884083 TxDqDly_Margin_A0==88 ps 9
365 20:23:28.885926 RxClkDly_Margin_A1==88 ps 9
366 20:23:28.886301 TxDqDly_Margin_A1==88 ps 9
367 20:23:28.891637 TrainedVREFDQ_A0==75
368 20:23:28.892124 TrainedVREFDQ_A1==74
369 20:23:28.892409 VrefDac_Margin_A0==24
370 20:23:28.897121 DeviceVref_Margin_A0==39
371 20:23:28.897552 VrefDac_Margin_A1==23
372 20:23:28.902798 DeviceVref_Margin_A1==40
373 20:23:28.903268
374 20:23:28.903572
375 20:23:28.903851 channel==1
376 20:23:28.904141 RxClkDly_Margin_A0==78 ps 8
377 20:23:28.908413 TxDqDly_Margin_A0==88 ps 9
378 20:23:28.908868 RxClkDly_Margin_A1==78 ps 8
379 20:23:28.914016 TxDqDly_Margin_A1==78 ps 8
380 20:23:28.914640 TrainedVREFDQ_A0==75
381 20:23:28.914982 TrainedVREFDQ_A1==75
382 20:23:28.919867 VrefDac_Margin_A0==22
383 20:23:28.921077 DeviceVref_Margin_A0==39
384 20:23:28.921415 VrefDac_Margin_A1==22
385 20:23:28.925140 DeviceVref_Margin_A1==38
386 20:23:28.925572
387 20:23:28.930686 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:23:28.931121
389 20:23:28.958725 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 20:23:28.964314 2D training succeed
391 20:23:28.969984 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:23:28.970387 auto size-- 65535DDR cs0 size: 2048MB
393 20:23:28.975523 DDR cs1 size: 2048MB
394 20:23:28.975919 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:23:28.981113 cs0 DataBus test pass
396 20:23:28.981506 cs1 DataBus test pass
397 20:23:28.981734 cs0 AddrBus test pass
398 20:23:28.986718 cs1 AddrBus test pass
399 20:23:28.987101
400 20:23:28.987324 100bdlr_step_size ps== 478
401 20:23:28.987540 result report
402 20:23:28.992315 boot times 0Enable ddr reg access
403 20:23:28.999692 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:23:29.013499 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:23:29.667628 bl2z: ptr: 05129330, size: 00001e40
406 20:23:29.674253 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:23:29.674840 MVN_1=0x00000000
408 20:23:29.675271 MVN_2=0x00000000
409 20:23:29.685780 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:23:29.686364 OPS=0x04
411 20:23:29.686798 ring efuse init
412 20:23:29.688801 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:23:29.694573 [0.017320 Inits done]
414 20:23:29.695110 secure task start!
415 20:23:29.695538 high task start!
416 20:23:29.695945 low task start!
417 20:23:29.698772 run into bl31
418 20:23:29.707398 NOTICE: BL31: v1.3(release):4fc40b1
419 20:23:29.715149 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:23:29.715702 NOTICE: BL31: G12A normal boot!
421 20:23:29.730610 NOTICE: BL31: BL33 decompress pass
422 20:23:29.736300 ERROR: Error initializing runtime service opteed_fast
423 20:23:32.483379 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:23:32.484048 bl2_stage_init 0x01
425 20:23:32.484494 bl2_stage_init 0x81
426 20:23:32.488930 hw id: 0x0000 - pwm id 0x01
427 20:23:32.489418 bl2_stage_init 0xc1
428 20:23:32.493299 bl2_stage_init 0x02
429 20:23:32.493830
430 20:23:32.494239 L0:00000000
431 20:23:32.494632 L1:00000703
432 20:23:32.495018 L2:00008067
433 20:23:32.498894 L3:15000000
434 20:23:32.499391 S1:00000000
435 20:23:32.499800 B2:20282000
436 20:23:32.500238 B1:a0f83180
437 20:23:32.500625
438 20:23:32.501016 TE: 71777
439 20:23:32.504465
440 20:23:32.510005 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:23:32.510529
442 20:23:32.510939 Board ID = 1
443 20:23:32.511339 Set cpu clk to 24M
444 20:23:32.511723 Set clk81 to 24M
445 20:23:32.515659 Use GP1_pll as DSU clk.
446 20:23:32.516202 DSU clk: 1200 Mhz
447 20:23:32.516597 CPU clk: 1200 MHz
448 20:23:32.521269 Set clk81 to 166.6M
449 20:23:32.526913 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:23:32.527475 board id: 1
451 20:23:32.535304 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:23:32.546161 fw parse done
453 20:23:32.552210 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:23:32.595252 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:23:32.606455 PIEI prepare done
456 20:23:32.607007 fastboot data load
457 20:23:32.607436 fastboot data verify
458 20:23:32.612058 verify result: 266
459 20:23:32.617701 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:23:32.618245 LPDDR4 probe
461 20:23:32.618657 ddr clk to 1584MHz
462 20:23:32.625680 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 20:23:32.663387
464 20:23:32.663973 dmc_version 0001
465 20:23:32.670399 Check phy result
466 20:23:32.676396 INFO : End of CA training
467 20:23:32.676919 INFO : End of initialization
468 20:23:32.681980 INFO : Training has run successfully!
469 20:23:32.682510 Check phy result
470 20:23:32.687548 INFO : End of initialization
471 20:23:32.688106 INFO : End of read enable training
472 20:23:32.690873 INFO : End of fine write leveling
473 20:23:32.696406 INFO : End of Write leveling coarse delay
474 20:23:32.702083 INFO : Training has run successfully!
475 20:23:32.702624 Check phy result
476 20:23:32.703042 INFO : End of initialization
477 20:23:32.707690 INFO : End of read dq deskew training
478 20:23:32.713317 INFO : End of MPR read delay center optimization
479 20:23:32.713942 INFO : End of write delay center optimization
480 20:23:32.718897 INFO : End of read delay center optimization
481 20:23:32.724441 INFO : End of max read latency training
482 20:23:32.725044 INFO : Training has run successfully!
483 20:23:32.730024 1D training succeed
484 20:23:32.736061 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 20:23:32.784427 Check phy result
486 20:23:32.785063 INFO : End of initialization
487 20:23:32.811733 INFO : End of 2D read delay Voltage center optimization
488 20:23:32.836115 INFO : End of 2D read delay Voltage center optimization
489 20:23:32.892529 INFO : End of 2D write delay Voltage center optimization
490 20:23:32.946562 INFO : End of 2D write delay Voltage center optimization
491 20:23:32.952014 INFO : Training has run successfully!
492 20:23:32.952556
493 20:23:32.952813 channel==0
494 20:23:32.957756 RxClkDly_Margin_A0==69 ps 7
495 20:23:32.958138 TxDqDly_Margin_A0==98 ps 10
496 20:23:32.963254 RxClkDly_Margin_A1==69 ps 7
497 20:23:32.963623 TxDqDly_Margin_A1==98 ps 10
498 20:23:32.963843 TrainedVREFDQ_A0==74
499 20:23:32.968807 TrainedVREFDQ_A1==74
500 20:23:32.969337 VrefDac_Margin_A0==24
501 20:23:32.969703 DeviceVref_Margin_A0==40
502 20:23:32.974558 VrefDac_Margin_A1==23
503 20:23:32.975078 DeviceVref_Margin_A1==40
504 20:23:32.975332
505 20:23:32.975547
506 20:23:32.980088 channel==1
507 20:23:32.980598 RxClkDly_Margin_A0==78 ps 8
508 20:23:32.980932 TxDqDly_Margin_A0==98 ps 10
509 20:23:32.985779 RxClkDly_Margin_A1==69 ps 7
510 20:23:32.986291 TxDqDly_Margin_A1==88 ps 9
511 20:23:32.991247 TrainedVREFDQ_A0==75
512 20:23:32.991605 TrainedVREFDQ_A1==77
513 20:23:32.991821 VrefDac_Margin_A0==22
514 20:23:32.996786 DeviceVref_Margin_A0==39
515 20:23:32.997141 VrefDac_Margin_A1==22
516 20:23:33.002471 DeviceVref_Margin_A1==37
517 20:23:33.002842
518 20:23:33.003054 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 20:23:33.003267
520 20:23:33.035941 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
521 20:23:33.036404 2D training succeed
522 20:23:33.041620 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 20:23:33.047136 auto size-- 65535DDR cs0 size: 2048MB
524 20:23:33.047656 DDR cs1 size: 2048MB
525 20:23:33.052789 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 20:23:33.053157 cs0 DataBus test pass
527 20:23:33.058346 cs1 DataBus test pass
528 20:23:33.058719 cs0 AddrBus test pass
529 20:23:33.058932 cs1 AddrBus test pass
530 20:23:33.059134
531 20:23:33.063928 100bdlr_step_size ps== 471
532 20:23:33.064497 result report
533 20:23:33.069644 boot times 0Enable ddr reg access
534 20:23:33.074804 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 20:23:33.088664 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 20:23:33.748540 bl2z: ptr: 05129330, size: 00001e40
537 20:23:33.755410 0.0;M3 CHK:0;cm4_sp_mode 0
538 20:23:33.755820 MVN_1=0x00000000
539 20:23:33.756074 MVN_2=0x00000000
540 20:23:33.766864 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 20:23:33.767281 OPS=0x04
542 20:23:33.767513 ring efuse init
543 20:23:33.769731 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 20:23:33.775954 [0.017355 Inits done]
545 20:23:33.776339 secure task start!
546 20:23:33.776557 high task start!
547 20:23:33.776765 low task start!
548 20:23:33.780249 run into bl31
549 20:23:33.788842 NOTICE: BL31: v1.3(release):4fc40b1
550 20:23:33.796725 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 20:23:33.797118 NOTICE: BL31: G12A normal boot!
552 20:23:33.812304 NOTICE: BL31: BL33 decompress pass
553 20:23:33.818111 ERROR: Error initializing runtime service opteed_fast
554 20:23:35.180508 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 20:23:35.180968 bl2_stage_init 0x01
556 20:23:35.181208 bl2_stage_init 0x81
557 20:23:35.186098 hw id: 0x0000 - pwm id 0x01
558 20:23:35.186633 bl2_stage_init 0xc1
559 20:23:35.186989 bl2_stage_init 0x02
560 20:23:35.187319
561 20:23:35.191674 L0:00000000
562 20:23:35.192271 L1:00000703
563 20:23:35.192545 L2:00008067
564 20:23:35.192763 L3:15000000
565 20:23:35.193161 S1:00000000
566 20:23:35.193872 B2:20282000
567 20:23:35.198852 B1:a0f83180
568 20:23:35.199338
569 20:23:35.199722 TE: 69207
570 20:23:35.200117
571 20:23:35.204508 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 20:23:35.204938
573 20:23:35.205177 Board ID = 1
574 20:23:35.210062 Set cpu clk to 24M
575 20:23:35.210593 Set clk81 to 24M
576 20:23:35.210949 Use GP1_pll as DSU clk.
577 20:23:35.215634 DSU clk: 1200 Mhz
578 20:23:35.216169 CPU clk: 1200 MHz
579 20:23:35.216432 Set clk81 to 166.6M
580 20:23:35.221251 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 20:23:35.221633 board id: 1
582 20:23:35.231623 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 20:23:35.242719 fw parse done
584 20:23:35.248593 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 20:23:35.291670 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 20:23:35.302886 PIEI prepare done
587 20:23:35.303311 fastboot data load
588 20:23:35.303565 fastboot data verify
589 20:23:35.308454 verify result: 266
590 20:23:35.313997 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 20:23:35.314553 LPDDR4 probe
592 20:23:35.314835 ddr clk to 1584MHz
593 20:23:35.322030 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 20:23:35.359687
595 20:23:35.360143 dmc_version 0001
596 20:23:35.366734 Check phy result
597 20:23:35.372707 INFO : End of CA training
598 20:23:35.373104 INFO : End of initialization
599 20:23:35.378318 INFO : Training has run successfully!
600 20:23:35.378868 Check phy result
601 20:23:35.383945 INFO : End of initialization
602 20:23:35.384378 INFO : End of read enable training
603 20:23:35.389609 INFO : End of fine write leveling
604 20:23:35.395167 INFO : End of Write leveling coarse delay
605 20:23:35.395761 INFO : Training has run successfully!
606 20:23:35.396074 Check phy result
607 20:23:35.400730 INFO : End of initialization
608 20:23:35.401295 INFO : End of read dq deskew training
609 20:23:35.406314 INFO : End of MPR read delay center optimization
610 20:23:35.411872 INFO : End of write delay center optimization
611 20:23:35.417454 INFO : End of read delay center optimization
612 20:23:35.417808 INFO : End of max read latency training
613 20:23:35.423094 INFO : Training has run successfully!
614 20:23:35.423456 1D training succeed
615 20:23:35.432315 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 20:23:35.480658 Check phy result
617 20:23:35.481189 INFO : End of initialization
618 20:23:35.508102 INFO : End of 2D read delay Voltage center optimization
619 20:23:35.532258 INFO : End of 2D read delay Voltage center optimization
620 20:23:35.588885 INFO : End of 2D write delay Voltage center optimization
621 20:23:35.642989 INFO : End of 2D write delay Voltage center optimization
622 20:23:35.648424 INFO : Training has run successfully!
623 20:23:35.648903
624 20:23:35.649307 channel==0
625 20:23:35.654001 RxClkDly_Margin_A0==78 ps 8
626 20:23:35.654475 TxDqDly_Margin_A0==98 ps 10
627 20:23:35.659626 RxClkDly_Margin_A1==88 ps 9
628 20:23:35.660144 TxDqDly_Margin_A1==88 ps 9
629 20:23:35.660549 TrainedVREFDQ_A0==76
630 20:23:35.665252 TrainedVREFDQ_A1==74
631 20:23:35.665741 VrefDac_Margin_A0==23
632 20:23:35.666136 DeviceVref_Margin_A0==38
633 20:23:35.670908 VrefDac_Margin_A1==23
634 20:23:35.671393 DeviceVref_Margin_A1==40
635 20:23:35.671786
636 20:23:35.672219
637 20:23:35.672612 channel==1
638 20:23:35.676424 RxClkDly_Margin_A0==88 ps 9
639 20:23:35.676955 TxDqDly_Margin_A0==98 ps 10
640 20:23:35.682753 RxClkDly_Margin_A1==78 ps 8
641 20:23:35.683372 TxDqDly_Margin_A1==88 ps 9
642 20:23:35.687614 TrainedVREFDQ_A0==78
643 20:23:35.688180 TrainedVREFDQ_A1==78
644 20:23:35.688597 VrefDac_Margin_A0==22
645 20:23:35.693150 DeviceVref_Margin_A0==36
646 20:23:35.693682 VrefDac_Margin_A1==22
647 20:23:35.698730 DeviceVref_Margin_A1==36
648 20:23:35.699261
649 20:23:35.699699 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 20:23:35.700174
651 20:23:35.732318 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
652 20:23:35.732943 2D training succeed
653 20:23:35.737937 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 20:23:35.743550 auto size-- 65535DDR cs0 size: 2048MB
655 20:23:35.744116 DDR cs1 size: 2048MB
656 20:23:35.749128 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 20:23:35.749636 cs0 DataBus test pass
658 20:23:35.754748 cs1 DataBus test pass
659 20:23:35.755276 cs0 AddrBus test pass
660 20:23:35.755679 cs1 AddrBus test pass
661 20:23:35.756138
662 20:23:35.760421 100bdlr_step_size ps== 471
663 20:23:35.760937 result report
664 20:23:35.765961 boot times 0Enable ddr reg access
665 20:23:35.771094 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 20:23:35.785052 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 20:23:36.444674 bl2z: ptr: 05129330, size: 00001e40
668 20:23:36.452669 0.0;M3 CHK:0;cm4_sp_mode 0
669 20:23:36.453207 MVN_1=0x00000000
670 20:23:36.453632 MVN_2=0x00000000
671 20:23:36.464146 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 20:23:36.464622 OPS=0x04
673 20:23:36.465042 ring efuse init
674 20:23:36.469845 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 20:23:36.470321 [0.017354 Inits done]
676 20:23:36.470739 secure task start!
677 20:23:36.477558 high task start!
678 20:23:36.478021 low task start!
679 20:23:36.478434 run into bl31
680 20:23:36.486211 NOTICE: BL31: v1.3(release):4fc40b1
681 20:23:36.494180 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 20:23:36.494636 NOTICE: BL31: G12A normal boot!
683 20:23:36.509590 NOTICE: BL31: BL33 decompress pass
684 20:23:36.515254 ERROR: Error initializing runtime service opteed_fast
685 20:23:37.310743
686 20:23:37.311339
687 20:23:37.316169 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 20:23:37.316706
689 20:23:37.319538 Model: Libre Computer AML-S905D3-CC Solitude
690 20:23:37.466685 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 20:23:37.482050 DRAM: 2 GiB (effective 3.8 GiB)
692 20:23:37.583120 Core: 406 devices, 33 uclasses, devicetree: separate
693 20:23:37.588888 WDT: Not starting watchdog@f0d0
694 20:23:37.613927 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 20:23:37.626224 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 20:23:37.632120 ** Bad device specification mmc 0 **
697 20:23:37.641233 Card did not respond to voltage select! : -110
698 20:23:37.648813 ** Bad device specification mmc 0 **
699 20:23:37.649178 Couldn't find partition mmc 0
700 20:23:37.657138 Card did not respond to voltage select! : -110
701 20:23:37.662651 ** Bad device specification mmc 0 **
702 20:23:37.663001 Couldn't find partition mmc 0
703 20:23:37.667719 Error: could not access storage.
704 20:23:37.964224 Net: eth0: ethernet@ff3f0000
705 20:23:37.964665 starting USB...
706 20:23:38.209081 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 20:23:38.209703 Starting the controller
708 20:23:38.216037 USB XHCI 1.10
709 20:23:39.770070 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 20:23:39.778434 scanning usb for storage devices... 0 Storage Device(s) found
712 20:23:39.829894 Hit any key to stop autoboot: 1
713 20:23:39.830697 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 20:23:39.831298 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
715 20:23:39.831771 Setting prompt string to ['=>']
716 20:23:39.832314 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
717 20:23:39.844357 0
718 20:23:39.845228 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 20:23:39.946449 => setenv autoload no
721 20:23:39.947209 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 20:23:39.954183 setenv autoload no
724 20:23:40.055643 => setenv initrd_high 0xffffffff
725 20:23:40.056351 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 20:23:40.060839 setenv initrd_high 0xffffffff
728 20:23:40.162247 => setenv fdt_high 0xffffffff
729 20:23:40.162914 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 20:23:40.167485 setenv fdt_high 0xffffffff
732 20:23:40.268953 => dhcp
733 20:23:40.269645 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 20:23:40.273993 dhcp
735 20:23:40.829528 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 20:23:40.830141 Speed: 1000, full duplex
737 20:23:40.830558 BOOTP broadcast 1
738 20:23:40.842161 DHCP client bound to address 192.168.6.21 (12 ms)
740 20:23:40.943628 => setenv serverip 192.168.6.2
741 20:23:40.944432 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 20:23:40.948779 setenv serverip 192.168.6.2
744 20:23:41.050204 => tftpboot 0x01080000 930622/tftp-deploy-0o969f0f/kernel/uImage
745 20:23:41.050929 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 20:23:41.058177 tftpboot 0x01080000 930622/tftp-deploy-0o969f0f/kernel/uImage
747 20:23:41.058672 Speed: 1000, full duplex
748 20:23:41.059082 Using ethernet@ff3f0000 device
749 20:23:41.063502 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 20:23:41.069071 Filename '930622/tftp-deploy-0o969f0f/kernel/uImage'.
751 20:23:41.072662 Load address: 0x1080000
752 20:23:41.967726 Loading: *#### UDP wrong checksum 00000005 0000104c
753 20:23:45.383288 ###############
754 20:23:45.383712 TFTP error: trying to overwrite reserved memory...
756 20:23:45.384603 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
759 20:23:45.385553 end: 2.4 uboot-commands (duration 00:00:25) [common]
761 20:23:45.386249 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
763 20:23:45.386830 end: 2 uboot-action (duration 00:00:25) [common]
765 20:23:45.387804 Cleaning after the job
766 20:23:45.388204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/ramdisk
767 20:23:45.394204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/kernel
768 20:23:45.400575 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/dtb
769 20:23:45.401311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930622/tftp-deploy-0o969f0f/modules
770 20:23:45.421987 start: 4.1 power-off (timeout 00:00:30) [common]
771 20:23:45.422666 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 20:23:45.457095 >> OK - accepted request
773 20:23:45.459447 Returned 0 in 0 seconds
774 20:23:45.560334 end: 4.1 power-off (duration 00:00:00) [common]
776 20:23:45.561323 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 20:23:45.561988 Listened to connection for namespace 'common' for up to 1s
778 20:23:46.562936 Finalising connection for namespace 'common'
779 20:23:46.563468 Disconnecting from shell: Finalise
780 20:23:46.564195 =>
781 20:23:46.664990 end: 4.2 read-feedback (duration 00:00:01) [common]
782 20:23:46.665505 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/930622
783 20:23:46.943343 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/930622
784 20:23:46.943938 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.