Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:25:23.178403 lava-dispatcher, installed at version: 2024.01
2 20:25:23.179667 start: 0 validate
3 20:25:23.180212 Start time: 2024-11-03 20:25:23.180182+00:00 (UTC)
4 20:25:23.180740 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:25:23.181305 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:25:23.227112 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:25:23.227659 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 20:25:23.261059 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:25:23.261733 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:25:23.295681 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:25:23.296197 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:25:23.330112 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:25:23.330572 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
14 20:25:23.374626 validate duration: 0.19
16 20:25:23.376130 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:25:23.376737 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:25:23.377337 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:25:23.378286 Not decompressing ramdisk as can be used compressed.
20 20:25:23.378981 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 20:25:23.379487 saving as /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/ramdisk/initrd.cpio.gz
22 20:25:23.380015 total size: 5628182 (5 MB)
23 20:25:23.422655 progress 0 % (0 MB)
24 20:25:23.430994 progress 5 % (0 MB)
25 20:25:23.440190 progress 10 % (0 MB)
26 20:25:23.447843 progress 15 % (0 MB)
27 20:25:23.456379 progress 20 % (1 MB)
28 20:25:23.461713 progress 25 % (1 MB)
29 20:25:23.465775 progress 30 % (1 MB)
30 20:25:23.469744 progress 35 % (1 MB)
31 20:25:23.473369 progress 40 % (2 MB)
32 20:25:23.477414 progress 45 % (2 MB)
33 20:25:23.481196 progress 50 % (2 MB)
34 20:25:23.485293 progress 55 % (2 MB)
35 20:25:23.489419 progress 60 % (3 MB)
36 20:25:23.493028 progress 65 % (3 MB)
37 20:25:23.497000 progress 70 % (3 MB)
38 20:25:23.500645 progress 75 % (4 MB)
39 20:25:23.504706 progress 80 % (4 MB)
40 20:25:23.508364 progress 85 % (4 MB)
41 20:25:23.512447 progress 90 % (4 MB)
42 20:25:23.516444 progress 95 % (5 MB)
43 20:25:23.519699 progress 100 % (5 MB)
44 20:25:23.520364 5 MB downloaded in 0.14 s (38.24 MB/s)
45 20:25:23.520926 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:25:23.521836 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:25:23.522140 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:25:23.522418 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:25:23.522910 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/kernel/Image
51 20:25:23.523158 saving as /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/kernel/Image
52 20:25:23.523373 total size: 169943552 (162 MB)
53 20:25:23.523590 No compression specified
54 20:25:23.561424 progress 0 % (0 MB)
55 20:25:23.669236 progress 5 % (8 MB)
56 20:25:23.774787 progress 10 % (16 MB)
57 20:25:23.880631 progress 15 % (24 MB)
58 20:25:23.987438 progress 20 % (32 MB)
59 20:25:24.093001 progress 25 % (40 MB)
60 20:25:24.201179 progress 30 % (48 MB)
61 20:25:24.308169 progress 35 % (56 MB)
62 20:25:24.414590 progress 40 % (64 MB)
63 20:25:24.521590 progress 45 % (72 MB)
64 20:25:24.629010 progress 50 % (81 MB)
65 20:25:24.736169 progress 55 % (89 MB)
66 20:25:24.843301 progress 60 % (97 MB)
67 20:25:24.950988 progress 65 % (105 MB)
68 20:25:25.057677 progress 70 % (113 MB)
69 20:25:25.164495 progress 75 % (121 MB)
70 20:25:25.271118 progress 80 % (129 MB)
71 20:25:25.377788 progress 85 % (137 MB)
72 20:25:25.484490 progress 90 % (145 MB)
73 20:25:25.591253 progress 95 % (153 MB)
74 20:25:25.697832 progress 100 % (162 MB)
75 20:25:25.698466 162 MB downloaded in 2.18 s (74.51 MB/s)
76 20:25:25.698944 end: 1.2.1 http-download (duration 00:00:02) [common]
78 20:25:25.699766 end: 1.2 download-retry (duration 00:00:02) [common]
79 20:25:25.700068 start: 1.3 download-retry (timeout 00:09:58) [common]
80 20:25:25.700343 start: 1.3.1 http-download (timeout 00:09:58) [common]
81 20:25:25.700822 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:25:25.701094 saving as /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:25:25.701302 total size: 54703 (0 MB)
84 20:25:25.701510 No compression specified
85 20:25:25.741671 progress 59 % (0 MB)
86 20:25:25.742530 progress 100 % (0 MB)
87 20:25:25.743090 0 MB downloaded in 0.04 s (1.25 MB/s)
88 20:25:25.743547 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:25:25.744404 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:25:25.744667 start: 1.4 download-retry (timeout 00:09:58) [common]
92 20:25:25.744930 start: 1.4.1 http-download (timeout 00:09:58) [common]
93 20:25:25.745395 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 20:25:25.745631 saving as /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/nfsrootfs/full.rootfs.tar
95 20:25:25.745836 total size: 107552908 (102 MB)
96 20:25:25.746044 Using unxz to decompress xz
97 20:25:25.784245 progress 0 % (0 MB)
98 20:25:26.437841 progress 5 % (5 MB)
99 20:25:27.182660 progress 10 % (10 MB)
100 20:25:27.907444 progress 15 % (15 MB)
101 20:25:28.672798 progress 20 % (20 MB)
102 20:25:29.257180 progress 25 % (25 MB)
103 20:25:29.880915 progress 30 % (30 MB)
104 20:25:30.626709 progress 35 % (35 MB)
105 20:25:31.000187 progress 40 % (41 MB)
106 20:25:31.428364 progress 45 % (46 MB)
107 20:25:32.133681 progress 50 % (51 MB)
108 20:25:32.844612 progress 55 % (56 MB)
109 20:25:33.622026 progress 60 % (61 MB)
110 20:25:34.383685 progress 65 % (66 MB)
111 20:25:35.116235 progress 70 % (71 MB)
112 20:25:35.882740 progress 75 % (76 MB)
113 20:25:36.562006 progress 80 % (82 MB)
114 20:25:37.270044 progress 85 % (87 MB)
115 20:25:38.004662 progress 90 % (92 MB)
116 20:25:38.717928 progress 95 % (97 MB)
117 20:25:39.463318 progress 100 % (102 MB)
118 20:25:39.476535 102 MB downloaded in 13.73 s (7.47 MB/s)
119 20:25:39.477107 end: 1.4.1 http-download (duration 00:00:14) [common]
121 20:25:39.477921 end: 1.4 download-retry (duration 00:00:14) [common]
122 20:25:39.478185 start: 1.5 download-retry (timeout 00:09:44) [common]
123 20:25:39.478442 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 20:25:39.478900 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig+debug/gcc-12/modules.tar.xz
125 20:25:39.479133 saving as /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/modules/modules.tar
126 20:25:39.479333 total size: 27642748 (26 MB)
127 20:25:39.479540 Using unxz to decompress xz
128 20:25:39.525369 progress 0 % (0 MB)
129 20:25:39.714244 progress 5 % (1 MB)
130 20:25:39.913000 progress 10 % (2 MB)
131 20:25:40.143738 progress 15 % (3 MB)
132 20:25:40.377419 progress 20 % (5 MB)
133 20:25:40.578237 progress 25 % (6 MB)
134 20:25:40.782374 progress 30 % (7 MB)
135 20:25:40.982973 progress 35 % (9 MB)
136 20:25:41.176706 progress 40 % (10 MB)
137 20:25:41.370780 progress 45 % (11 MB)
138 20:25:41.581683 progress 50 % (13 MB)
139 20:25:41.782579 progress 55 % (14 MB)
140 20:25:42.000857 progress 60 % (15 MB)
141 20:25:42.207327 progress 65 % (17 MB)
142 20:25:42.406939 progress 70 % (18 MB)
143 20:25:42.614206 progress 75 % (19 MB)
144 20:25:42.815246 progress 80 % (21 MB)
145 20:25:43.026416 progress 85 % (22 MB)
146 20:25:43.231783 progress 90 % (23 MB)
147 20:25:43.429426 progress 95 % (25 MB)
148 20:25:43.628112 progress 100 % (26 MB)
149 20:25:43.641205 26 MB downloaded in 4.16 s (6.33 MB/s)
150 20:25:43.642090 end: 1.5.1 http-download (duration 00:00:04) [common]
152 20:25:43.643678 end: 1.5 download-retry (duration 00:00:04) [common]
153 20:25:43.644237 start: 1.6 prepare-tftp-overlay (timeout 00:09:40) [common]
154 20:25:43.644755 start: 1.6.1 extract-nfsrootfs (timeout 00:09:40) [common]
155 20:25:54.227157 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/930623/extract-nfsrootfs-qp7jx3db
156 20:25:54.227754 end: 1.6.1 extract-nfsrootfs (duration 00:00:11) [common]
157 20:25:54.228070 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
158 20:25:54.228682 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5
159 20:25:54.229107 makedir: /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin
160 20:25:54.229454 makedir: /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/tests
161 20:25:54.229773 makedir: /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/results
162 20:25:54.230104 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-add-keys
163 20:25:54.230624 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-add-sources
164 20:25:54.231191 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-background-process-start
165 20:25:54.231757 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-background-process-stop
166 20:25:54.232361 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-common-functions
167 20:25:54.232860 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-echo-ipv4
168 20:25:54.233337 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-install-packages
169 20:25:54.233817 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-installed-packages
170 20:25:54.234289 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-os-build
171 20:25:54.234755 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-probe-channel
172 20:25:54.235224 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-probe-ip
173 20:25:54.235714 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-target-ip
174 20:25:54.236222 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-target-mac
175 20:25:54.236701 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-target-storage
176 20:25:54.237175 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-case
177 20:25:54.237656 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-event
178 20:25:54.238129 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-feedback
179 20:25:54.238601 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-raise
180 20:25:54.239068 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-reference
181 20:25:54.239559 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-runner
182 20:25:54.240069 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-set
183 20:25:54.240633 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-test-shell
184 20:25:54.241124 Updating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-install-packages (oe)
185 20:25:54.241653 Updating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/bin/lava-installed-packages (oe)
186 20:25:54.242092 Creating /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/environment
187 20:25:54.242453 LAVA metadata
188 20:25:54.242705 - LAVA_JOB_ID=930623
189 20:25:54.242917 - LAVA_DISPATCHER_IP=192.168.6.2
190 20:25:54.243268 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
191 20:25:54.244251 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 20:25:54.244569 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
193 20:25:54.244776 skipped lava-vland-overlay
194 20:25:54.245018 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 20:25:54.245272 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
196 20:25:54.245488 skipped lava-multinode-overlay
197 20:25:54.245730 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 20:25:54.245982 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
199 20:25:54.246230 Loading test definitions
200 20:25:54.246508 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
201 20:25:54.246726 Using /lava-930623 at stage 0
202 20:25:54.247904 uuid=930623_1.6.2.4.1 testdef=None
203 20:25:54.248235 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 20:25:54.248499 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
205 20:25:54.250291 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 20:25:54.251069 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
208 20:25:54.253318 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 20:25:54.254132 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
211 20:25:54.256325 runner path: /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/0/tests/0_dmesg test_uuid 930623_1.6.2.4.1
212 20:25:54.256882 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 20:25:54.257628 Creating lava-test-runner.conf files
215 20:25:54.257826 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/930623/lava-overlay-4jrs4vj5/lava-930623/0 for stage 0
216 20:25:54.258155 - 0_dmesg
217 20:25:54.258489 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 20:25:54.258758 start: 1.6.2.5 compress-overlay (timeout 00:09:29) [common]
219 20:25:54.280329 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 20:25:54.280709 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:29) [common]
221 20:25:54.280970 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 20:25:54.281234 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 20:25:54.281496 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:29) [common]
224 20:25:54.897671 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 20:25:54.898137 start: 1.6.4 extract-modules (timeout 00:09:28) [common]
226 20:25:54.898386 extracting modules file /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930623/extract-nfsrootfs-qp7jx3db
227 20:25:56.598433 extracting modules file /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930623/extract-overlay-ramdisk-hhkwfdj0/ramdisk
228 20:25:58.326934 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 20:25:58.327416 start: 1.6.5 apply-overlay-tftp (timeout 00:09:25) [common]
230 20:25:58.327708 [common] Applying overlay to NFS
231 20:25:58.327932 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930623/compress-overlay-0gj6ewsd/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/930623/extract-nfsrootfs-qp7jx3db
232 20:25:58.357225 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 20:25:58.357629 start: 1.6.6 prepare-kernel (timeout 00:09:25) [common]
234 20:25:58.357926 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:25) [common]
235 20:25:58.358164 Converting downloaded kernel to a uImage
236 20:25:58.358474 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/kernel/Image /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/kernel/uImage
237 20:26:00.210068 output: Image Name:
238 20:26:00.210494 output: Created: Sun Nov 3 20:25:58 2024
239 20:26:00.210703 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 20:26:00.210904 output: Data Size: 169943552 Bytes = 165960.50 KiB = 162.07 MiB
241 20:26:00.211104 output: Load Address: 01080000
242 20:26:00.211301 output: Entry Point: 01080000
243 20:26:00.211494 output:
244 20:26:00.211820 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
245 20:26:00.212125 end: 1.6.6 prepare-kernel (duration 00:00:02) [common]
246 20:26:00.212401 start: 1.6.7 configure-preseed-file (timeout 00:09:23) [common]
247 20:26:00.212652 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 20:26:00.212905 start: 1.6.8 compress-ramdisk (timeout 00:09:23) [common]
249 20:26:00.213158 Building ramdisk /var/lib/lava/dispatcher/tmp/930623/extract-overlay-ramdisk-hhkwfdj0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/930623/extract-overlay-ramdisk-hhkwfdj0/ramdisk
250 20:26:05.591905 >> 426759 blocks
251 20:26:23.194199 Adding RAMdisk u-boot header.
252 20:26:23.194617 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/930623/extract-overlay-ramdisk-hhkwfdj0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/930623/extract-overlay-ramdisk-hhkwfdj0/ramdisk.cpio.gz.uboot
253 20:26:23.716806 output: Image Name:
254 20:26:23.717203 output: Created: Sun Nov 3 20:26:23 2024
255 20:26:23.717415 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 20:26:23.717619 output: Data Size: 50958209 Bytes = 49763.88 KiB = 48.60 MiB
257 20:26:23.717819 output: Load Address: 00000000
258 20:26:23.718015 output: Entry Point: 00000000
259 20:26:23.718209 output:
260 20:26:23.718809 rename /var/lib/lava/dispatcher/tmp/930623/extract-overlay-ramdisk-hhkwfdj0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/ramdisk/ramdisk.cpio.gz.uboot
261 20:26:23.719223 end: 1.6.8 compress-ramdisk (duration 00:00:24) [common]
262 20:26:23.719507 end: 1.6 prepare-tftp-overlay (duration 00:00:40) [common]
263 20:26:23.719780 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:00) [common]
264 20:26:23.720082 No LXC device requested
265 20:26:23.720661 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 20:26:23.721227 start: 1.8 deploy-device-env (timeout 00:09:00) [common]
267 20:26:23.721772 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 20:26:23.722224 Checking files for TFTP limit of 4294967296 bytes.
269 20:26:23.725266 end: 1 tftp-deploy (duration 00:01:00) [common]
270 20:26:23.725904 start: 2 uboot-action (timeout 00:05:00) [common]
271 20:26:23.726478 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 20:26:23.727023 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 20:26:23.727573 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 20:26:23.728177 Using kernel file from prepare-kernel: 930623/tftp-deploy-y1wqkhrh/kernel/uImage
275 20:26:23.728870 substitutions:
276 20:26:23.729314 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 20:26:23.729756 - {DTB_ADDR}: 0x01070000
278 20:26:23.730192 - {DTB}: 930623/tftp-deploy-y1wqkhrh/dtb/meson-g12b-a311d-libretech-cc.dtb
279 20:26:23.730629 - {INITRD}: 930623/tftp-deploy-y1wqkhrh/ramdisk/ramdisk.cpio.gz.uboot
280 20:26:23.731064 - {KERNEL_ADDR}: 0x01080000
281 20:26:23.731493 - {KERNEL}: 930623/tftp-deploy-y1wqkhrh/kernel/uImage
282 20:26:23.731923 - {LAVA_MAC}: None
283 20:26:23.732431 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/930623/extract-nfsrootfs-qp7jx3db
284 20:26:23.732869 - {NFS_SERVER_IP}: 192.168.6.2
285 20:26:23.733299 - {PRESEED_CONFIG}: None
286 20:26:23.733723 - {PRESEED_LOCAL}: None
287 20:26:23.734147 - {RAMDISK_ADDR}: 0x08000000
288 20:26:23.734567 - {RAMDISK}: 930623/tftp-deploy-y1wqkhrh/ramdisk/ramdisk.cpio.gz.uboot
289 20:26:23.734993 - {ROOT_PART}: None
290 20:26:23.735416 - {ROOT}: None
291 20:26:23.735839 - {SERVER_IP}: 192.168.6.2
292 20:26:23.736293 - {TEE_ADDR}: 0x83000000
293 20:26:23.736719 - {TEE}: None
294 20:26:23.737145 Parsed boot commands:
295 20:26:23.737559 - setenv autoload no
296 20:26:23.737985 - setenv initrd_high 0xffffffff
297 20:26:23.738407 - setenv fdt_high 0xffffffff
298 20:26:23.738828 - dhcp
299 20:26:23.739248 - setenv serverip 192.168.6.2
300 20:26:23.739668 - tftpboot 0x01080000 930623/tftp-deploy-y1wqkhrh/kernel/uImage
301 20:26:23.740117 - tftpboot 0x08000000 930623/tftp-deploy-y1wqkhrh/ramdisk/ramdisk.cpio.gz.uboot
302 20:26:23.740547 - tftpboot 0x01070000 930623/tftp-deploy-y1wqkhrh/dtb/meson-g12b-a311d-libretech-cc.dtb
303 20:26:23.740974 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/930623/extract-nfsrootfs-qp7jx3db,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 20:26:23.741412 - bootm 0x01080000 0x08000000 0x01070000
305 20:26:23.741954 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 20:26:23.743566 start: 2.3 connect-device (timeout 00:05:00) [common]
308 20:26:23.744074 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 20:26:23.759112 Setting prompt string to ['lava-test: # ']
310 20:26:23.760726 end: 2.3 connect-device (duration 00:00:00) [common]
311 20:26:23.761378 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 20:26:23.761985 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 20:26:23.762552 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 20:26:23.763786 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 20:26:23.800907 >> OK - accepted request
316 20:26:23.803516 Returned 0 in 0 seconds
317 20:26:23.904773 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 20:26:23.906533 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 20:26:23.907165 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 20:26:23.907727 Setting prompt string to ['Hit any key to stop autoboot']
322 20:26:23.908310 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 20:26:23.910009 Trying 192.168.56.21...
324 20:26:23.910524 Connected to conserv1.
325 20:26:23.910990 Escape character is '^]'.
326 20:26:23.911445
327 20:26:23.911913 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 20:26:23.912412
329 20:26:35.466675 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 20:26:35.467289 bl2_stage_init 0x01
331 20:26:35.467723 bl2_stage_init 0x81
332 20:26:35.472152 hw id: 0x0000 - pwm id 0x01
333 20:26:35.472701 bl2_stage_init 0xc1
334 20:26:35.473140 bl2_stage_init 0x02
335 20:26:35.473537
336 20:26:35.477736 L0:00000000
337 20:26:35.478189 L1:20000703
338 20:26:35.478598 L2:00008067
339 20:26:35.478985 L3:14000000
340 20:26:35.483253 B2:00402000
341 20:26:35.483707 B1:e0f83180
342 20:26:35.484130
343 20:26:35.484524 TE: 58167
344 20:26:35.484916
345 20:26:35.488866 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 20:26:35.489310
347 20:26:35.489708 Board ID = 1
348 20:26:35.494469 Set A53 clk to 24M
349 20:26:35.494903 Set A73 clk to 24M
350 20:26:35.495292 Set clk81 to 24M
351 20:26:35.500102 A53 clk: 1200 MHz
352 20:26:35.500540 A73 clk: 1200 MHz
353 20:26:35.500926 CLK81: 166.6M
354 20:26:35.501310 smccc: 00012abe
355 20:26:35.505732 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 20:26:35.511314 board id: 1
357 20:26:35.517178 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 20:26:35.527898 fw parse done
359 20:26:35.532911 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 20:26:35.576584 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 20:26:35.587331 PIEI prepare done
362 20:26:35.587841 fastboot data load
363 20:26:35.588301 fastboot data verify
364 20:26:35.593028 verify result: 266
365 20:26:35.598565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 20:26:35.599028 LPDDR4 probe
367 20:26:35.599441 ddr clk to 1584MHz
368 20:26:35.605735 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 20:26:35.643089
370 20:26:35.643597 dmc_version 0001
371 20:26:35.649624 Check phy result
372 20:26:35.656446 INFO : End of CA training
373 20:26:35.656925 INFO : End of initialization
374 20:26:35.662019 INFO : Training has run successfully!
375 20:26:35.662483 Check phy result
376 20:26:35.667624 INFO : End of initialization
377 20:26:35.668135 INFO : End of read enable training
378 20:26:35.673247 INFO : End of fine write leveling
379 20:26:35.678866 INFO : End of Write leveling coarse delay
380 20:26:35.679325 INFO : Training has run successfully!
381 20:26:35.679729 Check phy result
382 20:26:35.684453 INFO : End of initialization
383 20:26:35.684946 INFO : End of read dq deskew training
384 20:26:35.690028 INFO : End of MPR read delay center optimization
385 20:26:35.695597 INFO : End of write delay center optimization
386 20:26:35.701263 INFO : End of read delay center optimization
387 20:26:35.701728 INFO : End of max read latency training
388 20:26:35.706890 INFO : Training has run successfully!
389 20:26:35.707363 1D training succeed
390 20:26:35.715953 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 20:26:35.763642 Check phy result
392 20:26:35.764211 INFO : End of initialization
393 20:26:35.785376 INFO : End of 2D read delay Voltage center optimization
394 20:26:35.805577 INFO : End of 2D read delay Voltage center optimization
395 20:26:35.857690 INFO : End of 2D write delay Voltage center optimization
396 20:26:35.907075 INFO : End of 2D write delay Voltage center optimization
397 20:26:35.912599 INFO : Training has run successfully!
398 20:26:35.913093
399 20:26:35.913518 channel==0
400 20:26:35.918231 RxClkDly_Margin_A0==78 ps 8
401 20:26:35.918756 TxDqDly_Margin_A0==98 ps 10
402 20:26:35.921525 RxClkDly_Margin_A1==88 ps 9
403 20:26:35.922037 TxDqDly_Margin_A1==98 ps 10
404 20:26:35.927095 TrainedVREFDQ_A0==74
405 20:26:35.927634 TrainedVREFDQ_A1==74
406 20:26:35.932695 VrefDac_Margin_A0==25
407 20:26:35.933185 DeviceVref_Margin_A0==40
408 20:26:35.933582 VrefDac_Margin_A1==25
409 20:26:35.938181 DeviceVref_Margin_A1==40
410 20:26:35.938653
411 20:26:35.939051
412 20:26:35.939444 channel==1
413 20:26:35.939830 RxClkDly_Margin_A0==98 ps 10
414 20:26:35.943897 TxDqDly_Margin_A0==98 ps 10
415 20:26:35.944414 RxClkDly_Margin_A1==98 ps 10
416 20:26:35.949329 TxDqDly_Margin_A1==88 ps 9
417 20:26:35.949640 TrainedVREFDQ_A0==77
418 20:26:35.949843 TrainedVREFDQ_A1==77
419 20:26:35.955088 VrefDac_Margin_A0==22
420 20:26:35.955584 DeviceVref_Margin_A0==37
421 20:26:35.960672 VrefDac_Margin_A1==24
422 20:26:35.961131 DeviceVref_Margin_A1==37
423 20:26:35.961537
424 20:26:35.966183 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 20:26:35.966641
426 20:26:35.994167 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 20:26:35.999893 2D training succeed
428 20:26:36.005442 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 20:26:36.005900 auto size-- 65535DDR cs0 size: 2048MB
430 20:26:36.010973 DDR cs1 size: 2048MB
431 20:26:36.011427 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 20:26:36.017003 cs0 DataBus test pass
433 20:26:36.017464 cs1 DataBus test pass
434 20:26:36.017875 cs0 AddrBus test pass
435 20:26:36.022266 cs1 AddrBus test pass
436 20:26:36.022879
437 20:26:36.023312 100bdlr_step_size ps== 420
438 20:26:36.023724 result report
439 20:26:36.028005 boot times 0Enable ddr reg access
440 20:26:36.035709 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 20:26:36.049136 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 20:26:36.622704 0.0;M3 CHK:0;cm4_sp_mode 0
443 20:26:36.623327 MVN_1=0x00000000
444 20:26:36.628145 MVN_2=0x00000000
445 20:26:36.633892 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 20:26:36.634343 OPS=0x10
447 20:26:36.634762 ring efuse init
448 20:26:36.635179 chipver efuse init
449 20:26:36.639481 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 20:26:36.645092 [0.018961 Inits done]
451 20:26:36.645548 secure task start!
452 20:26:36.645960 high task start!
453 20:26:36.649698 low task start!
454 20:26:36.650134 run into bl31
455 20:26:36.656337 NOTICE: BL31: v1.3(release):4fc40b1
456 20:26:36.664140 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 20:26:36.664590 NOTICE: BL31: G12A normal boot!
458 20:26:36.689468 NOTICE: BL31: BL33 decompress pass
459 20:26:36.695143 ERROR: Error initializing runtime service opteed_fast
460 20:26:37.928281
461 20:26:37.928910
462 20:26:37.936482 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 20:26:37.936951
464 20:26:37.937364 Model: Libre Computer AML-A311D-CC Alta
465 20:26:38.145073 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 20:26:38.168404 DRAM: 2 GiB (effective 3.8 GiB)
467 20:26:38.311383 Core: 408 devices, 31 uclasses, devicetree: separate
468 20:26:38.317320 WDT: Not starting watchdog@f0d0
469 20:26:38.349586 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 20:26:38.362002 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 20:26:38.367025 ** Bad device specification mmc 0 **
472 20:26:38.377386 Card did not respond to voltage select! : -110
473 20:26:38.384969 ** Bad device specification mmc 0 **
474 20:26:38.385420 Couldn't find partition mmc 0
475 20:26:38.393391 Card did not respond to voltage select! : -110
476 20:26:38.398814 ** Bad device specification mmc 0 **
477 20:26:38.399261 Couldn't find partition mmc 0
478 20:26:38.403870 Error: could not access storage.
479 20:26:39.667430 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 20:26:39.667961 bl2_stage_init 0x01
481 20:26:39.668343 bl2_stage_init 0x81
482 20:26:39.672859 hw id: 0x0000 - pwm id 0x01
483 20:26:39.673524 bl2_stage_init 0xc1
484 20:26:39.674067 bl2_stage_init 0x02
485 20:26:39.674587
486 20:26:39.678377 L0:00000000
487 20:26:39.678964 L1:20000703
488 20:26:39.679489 L2:00008067
489 20:26:39.680038 L3:14000000
490 20:26:39.681432 B2:00402000
491 20:26:39.681983 B1:e0f83180
492 20:26:39.682503
493 20:26:39.683017 TE: 58124
494 20:26:39.683540
495 20:26:39.692571 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 20:26:39.693164
497 20:26:39.693699 Board ID = 1
498 20:26:39.694215 Set A53 clk to 24M
499 20:26:39.694726 Set A73 clk to 24M
500 20:26:39.698208 Set clk81 to 24M
501 20:26:39.698764 A53 clk: 1200 MHz
502 20:26:39.699287 A73 clk: 1200 MHz
503 20:26:39.703694 CLK81: 166.6M
504 20:26:39.704292 smccc: 00012a92
505 20:26:39.709300 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 20:26:39.709876 board id: 1
507 20:26:39.717759 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 20:26:39.728402 fw parse done
509 20:26:39.734376 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 20:26:39.777063 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 20:26:39.787909 PIEI prepare done
512 20:26:39.788545 fastboot data load
513 20:26:39.789095 fastboot data verify
514 20:26:39.793510 verify result: 266
515 20:26:39.799169 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 20:26:39.799745 LPDDR4 probe
517 20:26:39.800319 ddr clk to 1584MHz
518 20:26:39.807194 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 20:26:39.844444
520 20:26:39.845106 dmc_version 0001
521 20:26:39.851079 Check phy result
522 20:26:39.856949 INFO : End of CA training
523 20:26:39.857522 INFO : End of initialization
524 20:26:39.862538 INFO : Training has run successfully!
525 20:26:39.863098 Check phy result
526 20:26:39.868231 INFO : End of initialization
527 20:26:39.868796 INFO : End of read enable training
528 20:26:39.873747 INFO : End of fine write leveling
529 20:26:39.879499 INFO : End of Write leveling coarse delay
530 20:26:39.880113 INFO : Training has run successfully!
531 20:26:39.880662 Check phy result
532 20:26:39.884988 INFO : End of initialization
533 20:26:39.885572 INFO : End of read dq deskew training
534 20:26:39.890664 INFO : End of MPR read delay center optimization
535 20:26:39.896431 INFO : End of write delay center optimization
536 20:26:39.901820 INFO : End of read delay center optimization
537 20:26:39.902424 INFO : End of max read latency training
538 20:26:39.907443 INFO : Training has run successfully!
539 20:26:39.908103 1D training succeed
540 20:26:39.916500 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 20:26:39.964366 Check phy result
542 20:26:39.965151 INFO : End of initialization
543 20:26:39.985992 INFO : End of 2D read delay Voltage center optimization
544 20:26:40.006193 INFO : End of 2D read delay Voltage center optimization
545 20:26:40.058200 INFO : End of 2D write delay Voltage center optimization
546 20:26:40.107689 INFO : End of 2D write delay Voltage center optimization
547 20:26:40.113139 INFO : Training has run successfully!
548 20:26:40.113726
549 20:26:40.114270 channel==0
550 20:26:40.118693 RxClkDly_Margin_A0==88 ps 9
551 20:26:40.119265 TxDqDly_Margin_A0==98 ps 10
552 20:26:40.124314 RxClkDly_Margin_A1==88 ps 9
553 20:26:40.124882 TxDqDly_Margin_A1==98 ps 10
554 20:26:40.125408 TrainedVREFDQ_A0==74
555 20:26:40.129897 TrainedVREFDQ_A1==74
556 20:26:40.130461 VrefDac_Margin_A0==25
557 20:26:40.130992 DeviceVref_Margin_A0==40
558 20:26:40.135475 VrefDac_Margin_A1==25
559 20:26:40.136062 DeviceVref_Margin_A1==40
560 20:26:40.136603
561 20:26:40.137119
562 20:26:40.141163 channel==1
563 20:26:40.141777 RxClkDly_Margin_A0==98 ps 10
564 20:26:40.142316 TxDqDly_Margin_A0==98 ps 10
565 20:26:40.146670 RxClkDly_Margin_A1==98 ps 10
566 20:26:40.147236 TxDqDly_Margin_A1==88 ps 9
567 20:26:40.152317 TrainedVREFDQ_A0==77
568 20:26:40.152880 TrainedVREFDQ_A1==77
569 20:26:40.153414 VrefDac_Margin_A0==22
570 20:26:40.157899 DeviceVref_Margin_A0==37
571 20:26:40.158452 VrefDac_Margin_A1==22
572 20:26:40.163482 DeviceVref_Margin_A1==37
573 20:26:40.164080
574 20:26:40.164621 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 20:26:40.169143
576 20:26:40.197849 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 20:26:40.198554 2D training succeed
578 20:26:40.202868 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 20:26:40.208438 auto size-- 65535DDR cs0 size: 2048MB
580 20:26:40.209076 DDR cs1 size: 2048MB
581 20:26:40.214381 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 20:26:40.215027 cs0 DataBus test pass
583 20:26:40.220605 cs1 DataBus test pass
584 20:26:40.221220 cs0 AddrBus test pass
585 20:26:40.221762 cs1 AddrBus test pass
586 20:26:40.222293
587 20:26:40.225503 100bdlr_step_size ps== 420
588 20:26:40.226137 result report
589 20:26:40.230691 boot times 0Enable ddr reg access
590 20:26:40.236248 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 20:26:40.249654 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 20:26:40.823289 0.0;M3 CHK:0;cm4_sp_mode 0
593 20:26:40.824129 MVN_1=0x00000000
594 20:26:40.828722 MVN_2=0x00000000
595 20:26:40.834486 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 20:26:40.835121 OPS=0x10
597 20:26:40.835730 ring efuse init
598 20:26:40.836308 chipver efuse init
599 20:26:40.840090 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 20:26:40.845668 [0.018961 Inits done]
601 20:26:40.846268 secure task start!
602 20:26:40.846791 high task start!
603 20:26:40.850253 low task start!
604 20:26:40.850797 run into bl31
605 20:26:40.856883 NOTICE: BL31: v1.3(release):4fc40b1
606 20:26:40.864673 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 20:26:40.865241 NOTICE: BL31: G12A normal boot!
608 20:26:40.890080 NOTICE: BL31: BL33 decompress pass
609 20:26:40.895729 ERROR: Error initializing runtime service opteed_fast
610 20:26:42.128795
611 20:26:42.129624
612 20:26:42.136975 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 20:26:42.137569
614 20:26:42.138111 Model: Libre Computer AML-A311D-CC Alta
615 20:26:42.345531 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 20:26:42.368827 DRAM: 2 GiB (effective 3.8 GiB)
617 20:26:42.511872 Core: 408 devices, 31 uclasses, devicetree: separate
618 20:26:42.517652 WDT: Not starting watchdog@f0d0
619 20:26:42.549987 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 20:26:42.562422 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 20:26:42.567377 ** Bad device specification mmc 0 **
622 20:26:42.577706 Card did not respond to voltage select! : -110
623 20:26:42.585328 ** Bad device specification mmc 0 **
624 20:26:42.585909 Couldn't find partition mmc 0
625 20:26:42.593773 Card did not respond to voltage select! : -110
626 20:26:42.599179 ** Bad device specification mmc 0 **
627 20:26:42.599740 Couldn't find partition mmc 0
628 20:26:42.604239 Error: could not access storage.
629 20:26:42.946797 Net: eth0: ethernet@ff3f0000
630 20:26:42.947535 starting USB...
631 20:26:43.198624 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 20:26:43.199303 Starting the controller
633 20:26:43.205599 USB XHCI 1.10
634 20:26:44.915756 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 20:26:44.916617 bl2_stage_init 0x01
636 20:26:44.917186 bl2_stage_init 0x81
637 20:26:44.921409 hw id: 0x0000 - pwm id 0x01
638 20:26:44.921998 bl2_stage_init 0xc1
639 20:26:44.922538 bl2_stage_init 0x02
640 20:26:44.923080
641 20:26:44.926947 L0:00000000
642 20:26:44.927509 L1:20000703
643 20:26:44.928070 L2:00008067
644 20:26:44.928599 L3:14000000
645 20:26:44.929804 B2:00402000
646 20:26:44.930351 B1:e0f83180
647 20:26:44.930874
648 20:26:44.931400 TE: 58159
649 20:26:44.931917
650 20:26:44.940945 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 20:26:44.941527
652 20:26:44.942052 Board ID = 1
653 20:26:44.942580 Set A53 clk to 24M
654 20:26:44.943093 Set A73 clk to 24M
655 20:26:44.946634 Set clk81 to 24M
656 20:26:44.947201 A53 clk: 1200 MHz
657 20:26:44.947722 A73 clk: 1200 MHz
658 20:26:44.952064 CLK81: 166.6M
659 20:26:44.952614 smccc: 00012ab5
660 20:26:44.957703 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 20:26:44.958260 board id: 1
662 20:26:44.963341 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 20:26:44.977074 fw parse done
664 20:26:44.983181 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 20:26:45.025557 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 20:26:45.036428 PIEI prepare done
667 20:26:45.037010 fastboot data load
668 20:26:45.037545 fastboot data verify
669 20:26:45.042171 verify result: 266
670 20:26:45.047713 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 20:26:45.048351 LPDDR4 probe
672 20:26:45.048894 ddr clk to 1584MHz
673 20:26:45.055723 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 20:26:45.093042
675 20:26:45.093675 dmc_version 0001
676 20:26:45.099623 Check phy result
677 20:26:45.105484 INFO : End of CA training
678 20:26:45.106063 INFO : End of initialization
679 20:26:45.111129 INFO : Training has run successfully!
680 20:26:45.111723 Check phy result
681 20:26:45.116694 INFO : End of initialization
682 20:26:45.117260 INFO : End of read enable training
683 20:26:45.120077 INFO : End of fine write leveling
684 20:26:45.125597 INFO : End of Write leveling coarse delay
685 20:26:45.131201 INFO : Training has run successfully!
686 20:26:45.131779 Check phy result
687 20:26:45.132338 INFO : End of initialization
688 20:26:45.136792 INFO : End of read dq deskew training
689 20:26:45.142363 INFO : End of MPR read delay center optimization
690 20:26:45.142951 INFO : End of write delay center optimization
691 20:26:45.148040 INFO : End of read delay center optimization
692 20:26:45.153601 INFO : End of max read latency training
693 20:26:45.154183 INFO : Training has run successfully!
694 20:26:45.159200 1D training succeed
695 20:26:45.165116 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 20:26:45.212676 Check phy result
697 20:26:45.213310 INFO : End of initialization
698 20:26:45.235145 INFO : End of 2D read delay Voltage center optimization
699 20:26:45.255245 INFO : End of 2D read delay Voltage center optimization
700 20:26:45.307365 INFO : End of 2D write delay Voltage center optimization
701 20:26:45.356511 INFO : End of 2D write delay Voltage center optimization
702 20:26:45.362137 INFO : Training has run successfully!
703 20:26:45.362748
704 20:26:45.363293 channel==0
705 20:26:45.367610 RxClkDly_Margin_A0==88 ps 9
706 20:26:45.368284 TxDqDly_Margin_A0==98 ps 10
707 20:26:45.371134 RxClkDly_Margin_A1==88 ps 9
708 20:26:45.371722 TxDqDly_Margin_A1==98 ps 10
709 20:26:45.376453 TrainedVREFDQ_A0==74
710 20:26:45.377096 TrainedVREFDQ_A1==74
711 20:26:45.381994 VrefDac_Margin_A0==24
712 20:26:45.382593 DeviceVref_Margin_A0==40
713 20:26:45.383132 VrefDac_Margin_A1==25
714 20:26:45.387581 DeviceVref_Margin_A1==40
715 20:26:45.388196
716 20:26:45.388735
717 20:26:45.389250 channel==1
718 20:26:45.389765 RxClkDly_Margin_A0==98 ps 10
719 20:26:45.393347 TxDqDly_Margin_A0==88 ps 9
720 20:26:45.393967 RxClkDly_Margin_A1==98 ps 10
721 20:26:45.399271 TxDqDly_Margin_A1==88 ps 9
722 20:26:45.400055 TrainedVREFDQ_A0==76
723 20:26:45.400627 TrainedVREFDQ_A1==77
724 20:26:45.404409 VrefDac_Margin_A0==22
725 20:26:45.405047 DeviceVref_Margin_A0==38
726 20:26:45.410083 VrefDac_Margin_A1==22
727 20:26:45.410698 DeviceVref_Margin_A1==37
728 20:26:45.411243
729 20:26:45.415597 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 20:26:45.416238
731 20:26:45.443404 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 20:26:45.449117 2D training succeed
733 20:26:45.454675 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 20:26:45.455060 auto size-- 65535DDR cs0 size: 2048MB
735 20:26:45.460333 DDR cs1 size: 2048MB
736 20:26:45.461350 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 20:26:45.465952 cs0 DataBus test pass
738 20:26:45.466344 cs1 DataBus test pass
739 20:26:45.466574 cs0 AddrBus test pass
740 20:26:45.471554 cs1 AddrBus test pass
741 20:26:45.471976
742 20:26:45.472254 100bdlr_step_size ps== 420
743 20:26:45.472493 result report
744 20:26:45.477107 boot times 0Enable ddr reg access
745 20:26:45.484830 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 20:26:45.498335 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 20:26:46.070119 0.0;M3 CHK:0;cm4_sp_mode 0
748 20:26:46.070510 MVN_1=0x00000000
749 20:26:46.075675 MVN_2=0x00000000
750 20:26:46.081461 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 20:26:46.081751 OPS=0x10
752 20:26:46.081970 ring efuse init
753 20:26:46.082177 chipver efuse init
754 20:26:46.087066 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 20:26:46.092639 [0.018961 Inits done]
756 20:26:46.092894 secure task start!
757 20:26:46.093103 high task start!
758 20:26:46.097192 low task start!
759 20:26:46.097440 run into bl31
760 20:26:46.104005 NOTICE: BL31: v1.3(release):4fc40b1
761 20:26:46.111725 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 20:26:46.112000 NOTICE: BL31: G12A normal boot!
763 20:26:46.137062 NOTICE: BL31: BL33 decompress pass
764 20:26:46.142682 ERROR: Error initializing runtime service opteed_fast
765 20:26:47.375697
766 20:26:47.376143
767 20:26:47.384052 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 20:26:47.384464
769 20:26:47.384805 Model: Libre Computer AML-A311D-CC Alta
770 20:26:47.592436 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 20:26:47.615833 DRAM: 2 GiB (effective 3.8 GiB)
772 20:26:47.758855 Core: 408 devices, 31 uclasses, devicetree: separate
773 20:26:47.764727 WDT: Not starting watchdog@f0d0
774 20:26:47.797015 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 20:26:47.809437 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 20:26:47.814434 ** Bad device specification mmc 0 **
777 20:26:47.824747 Card did not respond to voltage select! : -110
778 20:26:47.832415 ** Bad device specification mmc 0 **
779 20:26:47.832708 Couldn't find partition mmc 0
780 20:26:47.840744 Card did not respond to voltage select! : -110
781 20:26:47.846255 ** Bad device specification mmc 0 **
782 20:26:47.846639 Couldn't find partition mmc 0
783 20:26:47.851339 Error: could not access storage.
784 20:26:48.194908 Net: eth0: ethernet@ff3f0000
785 20:26:48.195315 starting USB...
786 20:26:48.446672 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 20:26:48.447226 Starting the controller
788 20:26:48.453605 USB XHCI 1.10
789 20:26:50.615952 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 20:26:50.616610 bl2_stage_init 0x01
791 20:26:50.617040 bl2_stage_init 0x81
792 20:26:50.621501 hw id: 0x0000 - pwm id 0x01
793 20:26:50.621956 bl2_stage_init 0xc1
794 20:26:50.622367 bl2_stage_init 0x02
795 20:26:50.622773
796 20:26:50.627059 L0:00000000
797 20:26:50.627497 L1:20000703
798 20:26:50.627907 L2:00008067
799 20:26:50.628354 L3:14000000
800 20:26:50.632620 B2:00402000
801 20:26:50.633055 B1:e0f83180
802 20:26:50.633459
803 20:26:50.633867 TE: 58167
804 20:26:50.634270
805 20:26:50.638173 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 20:26:50.638620
807 20:26:50.639032 Board ID = 1
808 20:26:50.643861 Set A53 clk to 24M
809 20:26:50.644328 Set A73 clk to 24M
810 20:26:50.644733 Set clk81 to 24M
811 20:26:50.649422 A53 clk: 1200 MHz
812 20:26:50.649862 A73 clk: 1200 MHz
813 20:26:50.650262 CLK81: 166.6M
814 20:26:50.650658 smccc: 00012abe
815 20:26:50.655030 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 20:26:50.660670 board id: 1
817 20:26:50.666734 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 20:26:50.677154 fw parse done
819 20:26:50.683041 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 20:26:50.725975 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 20:26:50.736689 PIEI prepare done
822 20:26:50.737191 fastboot data load
823 20:26:50.737611 fastboot data verify
824 20:26:50.742331 verify result: 266
825 20:26:50.747848 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 20:26:50.748385 LPDDR4 probe
827 20:26:50.748808 ddr clk to 1584MHz
828 20:26:50.755880 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 20:26:50.793226
830 20:26:50.793743 dmc_version 0001
831 20:26:50.799880 Check phy result
832 20:26:50.806602 INFO : End of CA training
833 20:26:50.807077 INFO : End of initialization
834 20:26:50.814221 INFO : Training has run successfully!
835 20:26:50.814707 Check phy result
836 20:26:50.816900 INFO : End of initialization
837 20:26:50.817359 INFO : End of read enable training
838 20:26:50.823063 INFO : End of fine write leveling
839 20:26:50.828671 INFO : End of Write leveling coarse delay
840 20:26:50.829151 INFO : Training has run successfully!
841 20:26:50.829562 Check phy result
842 20:26:50.834657 INFO : End of initialization
843 20:26:50.835136 INFO : End of read dq deskew training
844 20:26:50.840030 INFO : End of MPR read delay center optimization
845 20:26:50.845668 INFO : End of write delay center optimization
846 20:26:50.852249 INFO : End of read delay center optimization
847 20:26:50.852711 INFO : End of max read latency training
848 20:26:50.855961 INFO : Training has run successfully!
849 20:26:50.856454 1D training succeed
850 20:26:50.865168 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 20:26:50.913008 Check phy result
852 20:26:50.913584 INFO : End of initialization
853 20:26:50.935353 INFO : End of 2D read delay Voltage center optimization
854 20:26:50.955386 INFO : End of 2D read delay Voltage center optimization
855 20:26:51.007333 INFO : End of 2D write delay Voltage center optimization
856 20:26:51.056586 INFO : End of 2D write delay Voltage center optimization
857 20:26:51.062056 INFO : Training has run successfully!
858 20:26:51.062498
859 20:26:51.062912 channel==0
860 20:26:51.067642 RxClkDly_Margin_A0==88 ps 9
861 20:26:51.068128 TxDqDly_Margin_A0==98 ps 10
862 20:26:51.073233 RxClkDly_Margin_A1==88 ps 9
863 20:26:51.073671 TxDqDly_Margin_A1==98 ps 10
864 20:26:51.074095 TrainedVREFDQ_A0==74
865 20:26:51.078877 TrainedVREFDQ_A1==74
866 20:26:51.079357 VrefDac_Margin_A0==24
867 20:26:51.079771 DeviceVref_Margin_A0==40
868 20:26:51.084447 VrefDac_Margin_A1==24
869 20:26:51.084905 DeviceVref_Margin_A1==40
870 20:26:51.085295
871 20:26:51.085681
872 20:26:51.090096 channel==1
873 20:26:51.090517 RxClkDly_Margin_A0==98 ps 10
874 20:26:51.090905 TxDqDly_Margin_A0==88 ps 9
875 20:26:51.095660 RxClkDly_Margin_A1==98 ps 10
876 20:26:51.096106 TxDqDly_Margin_A1==88 ps 9
877 20:26:51.101211 TrainedVREFDQ_A0==77
878 20:26:51.101629 TrainedVREFDQ_A1==77
879 20:26:51.102020 VrefDac_Margin_A0==22
880 20:26:51.106831 DeviceVref_Margin_A0==37
881 20:26:51.107245 VrefDac_Margin_A1==22
882 20:26:51.112449 DeviceVref_Margin_A1==37
883 20:26:51.112862
884 20:26:51.113250 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 20:26:51.113634
886 20:26:51.146050 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 20:26:51.146507 2D training succeed
888 20:26:51.151644 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 20:26:51.157230 auto size-- 65535DDR cs0 size: 2048MB
890 20:26:51.157654 DDR cs1 size: 2048MB
891 20:26:51.162833 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 20:26:51.163255 cs0 DataBus test pass
893 20:26:51.168432 cs1 DataBus test pass
894 20:26:51.168848 cs0 AddrBus test pass
895 20:26:51.169233 cs1 AddrBus test pass
896 20:26:51.169616
897 20:26:51.174010 100bdlr_step_size ps== 420
898 20:26:51.174432 result report
899 20:26:51.179610 boot times 0Enable ddr reg access
900 20:26:51.184971 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 20:26:51.198472 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 20:26:51.770530 0.0;M3 CHK:0;cm4_sp_mode 0
903 20:26:51.771119 MVN_1=0x00000000
904 20:26:51.775959 MVN_2=0x00000000
905 20:26:51.781663 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 20:26:51.782105 OPS=0x10
907 20:26:51.782514 ring efuse init
908 20:26:51.782914 chipver efuse init
909 20:26:51.787299 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 20:26:51.792918 [0.018961 Inits done]
911 20:26:51.793346 secure task start!
912 20:26:51.793752 high task start!
913 20:26:51.797457 low task start!
914 20:26:51.797882 run into bl31
915 20:26:51.804062 NOTICE: BL31: v1.3(release):4fc40b1
916 20:26:51.811890 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 20:26:51.812352 NOTICE: BL31: G12A normal boot!
918 20:26:51.837224 NOTICE: BL31: BL33 decompress pass
919 20:26:51.843488 ERROR: Error initializing runtime service opteed_fast
920 20:26:53.075848
921 20:26:53.076443
922 20:26:53.084237 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 20:26:53.084679
924 20:26:53.085093 Model: Libre Computer AML-A311D-CC Alta
925 20:26:53.292670 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 20:26:53.316043 DRAM: 2 GiB (effective 3.8 GiB)
927 20:26:53.459103 Core: 408 devices, 31 uclasses, devicetree: separate
928 20:26:53.464862 WDT: Not starting watchdog@f0d0
929 20:26:53.497110 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 20:26:53.509585 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 20:26:53.514537 ** Bad device specification mmc 0 **
932 20:26:53.524908 Card did not respond to voltage select! : -110
933 20:26:53.532543 ** Bad device specification mmc 0 **
934 20:26:53.532987 Couldn't find partition mmc 0
935 20:26:53.540912 Card did not respond to voltage select! : -110
936 20:26:53.546385 ** Bad device specification mmc 0 **
937 20:26:53.546825 Couldn't find partition mmc 0
938 20:26:53.551451 Error: could not access storage.
939 20:26:53.894951 Net: eth0: ethernet@ff3f0000
940 20:26:53.895469 starting USB...
941 20:26:54.146885 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 20:26:54.147422 Starting the controller
943 20:26:54.153740 USB XHCI 1.10
944 20:26:55.707905 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 20:26:55.716318 scanning usb for storage devices... 0 Storage Device(s) found
947 20:26:55.767480 Hit any key to stop autoboot: 1
948 20:26:55.768284 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 20:26:55.768648 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 20:26:55.768905 Setting prompt string to ['=>']
951 20:26:55.769165 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 20:26:55.783689 0
953 20:26:55.784436 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 20:26:55.784750 Sending with 10 millisecond of delay
956 20:26:56.919173 => setenv autoload no
957 20:26:56.930215 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 20:26:56.935238 setenv autoload no
959 20:26:56.936011 Sending with 10 millisecond of delay
961 20:26:58.733046 => setenv initrd_high 0xffffffff
962 20:26:58.743822 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 20:26:58.744776 setenv initrd_high 0xffffffff
964 20:26:58.745506 Sending with 10 millisecond of delay
966 20:27:00.362247 => setenv fdt_high 0xffffffff
967 20:27:00.373065 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 20:27:00.373653 setenv fdt_high 0xffffffff
969 20:27:00.374433 Sending with 10 millisecond of delay
971 20:27:00.668366 => dhcp
972 20:27:00.679165 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 20:27:00.679846 dhcp
974 20:27:00.680153 Speed: 1000, full duplex
975 20:27:00.680373 BOOTP broadcast 1
976 20:27:00.691495 DHCP client bound to address 192.168.6.27 (12 ms)
977 20:27:00.692439 Sending with 10 millisecond of delay
979 20:27:02.369305 => setenv serverip 192.168.6.2
980 20:27:02.380145 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 20:27:02.381110 setenv serverip 192.168.6.2
982 20:27:02.381853 Sending with 10 millisecond of delay
984 20:27:06.107320 => tftpboot 0x01080000 930623/tftp-deploy-y1wqkhrh/kernel/uImage
985 20:27:06.119104 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 20:27:06.120080 tftpboot 0x01080000 930623/tftp-deploy-y1wqkhrh/kernel/uImage
987 20:27:06.120580 Speed: 1000, full duplex
988 20:27:06.121045 Using ethernet@ff3f0000 device
989 20:27:06.122188 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 20:27:06.127520 Filename '930623/tftp-deploy-y1wqkhrh/kernel/uImage'.
991 20:27:06.131599 Load address: 0x1080000
992 20:27:08.891142 Loading: *############ UDP wrong checksum 000000ff 000000dc
993 20:27:08.903647 UDP wrong checksum 000000ff 000089ce
994 20:27:10.488318 #######
995 20:27:10.488982 TFTP error: trying to overwrite reserved memory...
997 20:27:10.490521 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1000 20:27:10.492621 end: 2.4 uboot-commands (duration 00:00:47) [common]
1002 20:27:10.494132 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1004 20:27:10.495281 end: 2 uboot-action (duration 00:00:47) [common]
1006 20:27:10.497017 Cleaning after the job
1007 20:27:10.497634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/ramdisk
1008 20:27:10.528570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/kernel
1009 20:27:10.578364 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/dtb
1010 20:27:10.579269 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/nfsrootfs
1011 20:27:10.603972 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930623/tftp-deploy-y1wqkhrh/modules
1012 20:27:10.615602 start: 4.1 power-off (timeout 00:00:30) [common]
1013 20:27:10.616247 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1014 20:27:10.653811 >> OK - accepted request
1015 20:27:10.656081 Returned 0 in 0 seconds
1016 20:27:10.756889 end: 4.1 power-off (duration 00:00:00) [common]
1018 20:27:10.757865 start: 4.2 read-feedback (timeout 00:10:00) [common]
1019 20:27:10.758534 Listened to connection for namespace 'common' for up to 1s
1020 20:27:11.758855 Finalising connection for namespace 'common'
1021 20:27:11.759656 Disconnecting from shell: Finalise
1022 20:27:11.760286 =>
1023 20:27:11.861332 end: 4.2 read-feedback (duration 00:00:01) [common]
1024 20:27:11.862011 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/930623
1025 20:27:14.260384 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/930623
1026 20:27:14.261001 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.