Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:17:42.716402 lava-dispatcher, installed at version: 2024.01
2 20:17:42.717178 start: 0 validate
3 20:17:42.717645 Start time: 2024-11-03 20:17:42.717614+00:00 (UTC)
4 20:17:42.718182 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:17:42.718708 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:17:42.763966 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:17:42.764549 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:17:42.798033 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:17:42.798679 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:17:42.834556 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:17:42.835089 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:17:42.876226 validate duration: 0.16
14 20:17:42.877099 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:17:42.877444 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:17:42.877753 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:17:42.878354 Not decompressing ramdisk as can be used compressed.
18 20:17:42.878795 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:17:42.879040 saving as /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/ramdisk/rootfs.cpio.gz
20 20:17:42.879295 total size: 8181887 (7 MB)
21 20:17:42.920845 progress 0 % (0 MB)
22 20:17:42.927025 progress 5 % (0 MB)
23 20:17:42.932686 progress 10 % (0 MB)
24 20:17:42.938618 progress 15 % (1 MB)
25 20:17:42.944155 progress 20 % (1 MB)
26 20:17:42.950090 progress 25 % (1 MB)
27 20:17:42.955502 progress 30 % (2 MB)
28 20:17:42.961308 progress 35 % (2 MB)
29 20:17:42.967019 progress 40 % (3 MB)
30 20:17:42.973172 progress 45 % (3 MB)
31 20:17:42.978917 progress 50 % (3 MB)
32 20:17:42.984831 progress 55 % (4 MB)
33 20:17:42.990173 progress 60 % (4 MB)
34 20:17:42.995886 progress 65 % (5 MB)
35 20:17:43.001120 progress 70 % (5 MB)
36 20:17:43.006931 progress 75 % (5 MB)
37 20:17:43.012360 progress 80 % (6 MB)
38 20:17:43.018004 progress 85 % (6 MB)
39 20:17:43.023160 progress 90 % (7 MB)
40 20:17:43.028772 progress 95 % (7 MB)
41 20:17:43.033784 progress 100 % (7 MB)
42 20:17:43.034424 7 MB downloaded in 0.16 s (50.31 MB/s)
43 20:17:43.034972 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:17:43.035869 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:17:43.036195 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:17:43.036469 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:17:43.036945 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/kernel/Image
49 20:17:43.037215 saving as /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/kernel/Image
50 20:17:43.037441 total size: 45713920 (43 MB)
51 20:17:43.037674 No compression specified
52 20:17:43.076501 progress 0 % (0 MB)
53 20:17:43.104501 progress 5 % (2 MB)
54 20:17:43.132381 progress 10 % (4 MB)
55 20:17:43.159836 progress 15 % (6 MB)
56 20:17:43.187319 progress 20 % (8 MB)
57 20:17:43.214399 progress 25 % (10 MB)
58 20:17:43.241928 progress 30 % (13 MB)
59 20:17:43.269224 progress 35 % (15 MB)
60 20:17:43.296753 progress 40 % (17 MB)
61 20:17:43.323879 progress 45 % (19 MB)
62 20:17:43.351403 progress 50 % (21 MB)
63 20:17:43.379000 progress 55 % (24 MB)
64 20:17:43.406518 progress 60 % (26 MB)
65 20:17:43.433581 progress 65 % (28 MB)
66 20:17:43.461378 progress 70 % (30 MB)
67 20:17:43.489457 progress 75 % (32 MB)
68 20:17:43.517358 progress 80 % (34 MB)
69 20:17:43.545001 progress 85 % (37 MB)
70 20:17:43.573173 progress 90 % (39 MB)
71 20:17:43.601013 progress 95 % (41 MB)
72 20:17:43.628424 progress 100 % (43 MB)
73 20:17:43.628920 43 MB downloaded in 0.59 s (73.71 MB/s)
74 20:17:43.629389 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:17:43.630203 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:17:43.630472 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:17:43.630732 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:17:43.631188 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 20:17:43.631454 saving as /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/dtb/meson-g12b-a311d-libretech-cc.dtb
81 20:17:43.631662 total size: 54703 (0 MB)
82 20:17:43.631871 No compression specified
83 20:17:43.674568 progress 59 % (0 MB)
84 20:17:43.675413 progress 100 % (0 MB)
85 20:17:43.676023 0 MB downloaded in 0.04 s (1.18 MB/s)
86 20:17:43.676530 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:17:43.677346 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:17:43.677608 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:17:43.677869 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:17:43.678332 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/modules.tar.xz
92 20:17:43.678568 saving as /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/modules/modules.tar
93 20:17:43.678772 total size: 11615340 (11 MB)
94 20:17:43.678983 Using unxz to decompress xz
95 20:17:43.713836 progress 0 % (0 MB)
96 20:17:43.779277 progress 5 % (0 MB)
97 20:17:43.854871 progress 10 % (1 MB)
98 20:17:43.953225 progress 15 % (1 MB)
99 20:17:44.044825 progress 20 % (2 MB)
100 20:17:44.124389 progress 25 % (2 MB)
101 20:17:44.199849 progress 30 % (3 MB)
102 20:17:44.278481 progress 35 % (3 MB)
103 20:17:44.350729 progress 40 % (4 MB)
104 20:17:44.432448 progress 45 % (5 MB)
105 20:17:44.517361 progress 50 % (5 MB)
106 20:17:44.594167 progress 55 % (6 MB)
107 20:17:44.678945 progress 60 % (6 MB)
108 20:17:44.759208 progress 65 % (7 MB)
109 20:17:44.839210 progress 70 % (7 MB)
110 20:17:44.917126 progress 75 % (8 MB)
111 20:17:45.001174 progress 80 % (8 MB)
112 20:17:45.081054 progress 85 % (9 MB)
113 20:17:45.164040 progress 90 % (10 MB)
114 20:17:45.237180 progress 95 % (10 MB)
115 20:17:45.313505 progress 100 % (11 MB)
116 20:17:45.326384 11 MB downloaded in 1.65 s (6.72 MB/s)
117 20:17:45.326955 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:17:45.327776 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:17:45.328180 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 20:17:45.328768 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 20:17:45.329337 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:17:45.329890 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 20:17:45.330963 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni
125 20:17:45.331877 makedir: /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin
126 20:17:45.332630 makedir: /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/tests
127 20:17:45.333292 makedir: /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/results
128 20:17:45.333947 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-add-keys
129 20:17:45.334978 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-add-sources
130 20:17:45.335969 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-background-process-start
131 20:17:45.337019 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-background-process-stop
132 20:17:45.338126 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-common-functions
133 20:17:45.339125 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-echo-ipv4
134 20:17:45.340123 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-install-packages
135 20:17:45.341090 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-installed-packages
136 20:17:45.342041 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-os-build
137 20:17:45.342992 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-probe-channel
138 20:17:45.343938 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-probe-ip
139 20:17:45.345050 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-target-ip
140 20:17:45.346015 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-target-mac
141 20:17:45.346960 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-target-storage
142 20:17:45.347938 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-case
143 20:17:45.348949 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-event
144 20:17:45.349919 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-feedback
145 20:17:45.350876 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-raise
146 20:17:45.351818 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-reference
147 20:17:45.352821 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-runner
148 20:17:45.353773 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-set
149 20:17:45.354722 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-test-shell
150 20:17:45.355715 Updating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-install-packages (oe)
151 20:17:45.356799 Updating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/bin/lava-installed-packages (oe)
152 20:17:45.357683 Creating /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/environment
153 20:17:45.358439 LAVA metadata
154 20:17:45.358959 - LAVA_JOB_ID=930530
155 20:17:45.359429 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:17:45.360168 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 20:17:45.362087 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:17:45.362712 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 20:17:45.363160 skipped lava-vland-overlay
160 20:17:45.363696 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:17:45.364323 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 20:17:45.364748 skipped lava-multinode-overlay
163 20:17:45.365243 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:17:45.365737 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 20:17:45.366204 Loading test definitions
166 20:17:45.366740 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 20:17:45.367173 Using /lava-930530 at stage 0
168 20:17:45.369433 uuid=930530_1.5.2.4.1 testdef=None
169 20:17:45.370008 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:17:45.370521 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 20:17:45.373079 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:17:45.373881 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 20:17:45.376124 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:17:45.376972 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 20:17:45.379111 runner path: /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/0/tests/0_dmesg test_uuid 930530_1.5.2.4.1
178 20:17:45.379647 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:17:45.380432 Creating lava-test-runner.conf files
181 20:17:45.380636 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/930530/lava-overlay-bukuw7ni/lava-930530/0 for stage 0
182 20:17:45.380969 - 0_dmesg
183 20:17:45.381312 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:17:45.381589 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:17:45.404908 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:17:45.405275 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:17:45.405535 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:17:45.405796 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:17:45.406057 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:17:46.459232 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:17:46.460118 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 20:17:46.460734 extracting modules file /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk
193 20:17:47.802021 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:17:47.802500 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 20:17:47.802773 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930530/compress-overlay-k72khs76/overlay-1.5.2.5.tar.gz to ramdisk
196 20:17:47.802987 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930530/compress-overlay-k72khs76/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk
197 20:17:47.832752 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:17:47.833143 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 20:17:47.833413 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 20:17:47.833637 Converting downloaded kernel to a uImage
201 20:17:47.833936 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/kernel/Image /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/kernel/uImage
202 20:17:48.318229 output: Image Name:
203 20:17:48.318653 output: Created: Sun Nov 3 20:17:47 2024
204 20:17:48.318868 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:17:48.319078 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:17:48.319280 output: Load Address: 01080000
207 20:17:48.319479 output: Entry Point: 01080000
208 20:17:48.319675 output:
209 20:17:48.320044 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:17:48.320335 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:17:48.320613 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 20:17:48.320871 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:17:48.321131 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 20:17:48.321399 Building ramdisk /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk
215 20:17:50.678173 >> 181607 blocks
216 20:17:59.123705 Adding RAMdisk u-boot header.
217 20:17:59.124397 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk.cpio.gz.uboot
218 20:17:59.396485 output: Image Name:
219 20:17:59.396894 output: Created: Sun Nov 3 20:17:59 2024
220 20:17:59.397103 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:17:59.397307 output: Data Size: 26061973 Bytes = 25451.15 KiB = 24.85 MiB
222 20:17:59.397507 output: Load Address: 00000000
223 20:17:59.397706 output: Entry Point: 00000000
224 20:17:59.397900 output:
225 20:17:59.398479 rename /var/lib/lava/dispatcher/tmp/930530/extract-overlay-ramdisk-fodxdtff/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot
226 20:17:59.398884 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 20:17:59.399162 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 20:17:59.399432 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 20:17:59.399669 No LXC device requested
230 20:17:59.399919 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:17:59.400462 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 20:17:59.401007 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:17:59.401456 Checking files for TFTP limit of 4294967296 bytes.
234 20:17:59.404363 end: 1 tftp-deploy (duration 00:00:17) [common]
235 20:17:59.404981 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:17:59.405552 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:17:59.406090 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:17:59.406632 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:17:59.407202 Using kernel file from prepare-kernel: 930530/tftp-deploy-takk6yrv/kernel/uImage
240 20:17:59.407881 substitutions:
241 20:17:59.408364 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:17:59.408807 - {DTB_ADDR}: 0x01070000
243 20:17:59.409247 - {DTB}: 930530/tftp-deploy-takk6yrv/dtb/meson-g12b-a311d-libretech-cc.dtb
244 20:17:59.409687 - {INITRD}: 930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot
245 20:17:59.410121 - {KERNEL_ADDR}: 0x01080000
246 20:17:59.410554 - {KERNEL}: 930530/tftp-deploy-takk6yrv/kernel/uImage
247 20:17:59.410985 - {LAVA_MAC}: None
248 20:17:59.411459 - {PRESEED_CONFIG}: None
249 20:17:59.411893 - {PRESEED_LOCAL}: None
250 20:17:59.412359 - {RAMDISK_ADDR}: 0x08000000
251 20:17:59.412786 - {RAMDISK}: 930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot
252 20:17:59.413216 - {ROOT_PART}: None
253 20:17:59.413645 - {ROOT}: None
254 20:17:59.414071 - {SERVER_IP}: 192.168.6.2
255 20:17:59.414502 - {TEE_ADDR}: 0x83000000
256 20:17:59.414927 - {TEE}: None
257 20:17:59.415360 Parsed boot commands:
258 20:17:59.415774 - setenv autoload no
259 20:17:59.416235 - setenv initrd_high 0xffffffff
260 20:17:59.416662 - setenv fdt_high 0xffffffff
261 20:17:59.417089 - dhcp
262 20:17:59.417513 - setenv serverip 192.168.6.2
263 20:17:59.417938 - tftpboot 0x01080000 930530/tftp-deploy-takk6yrv/kernel/uImage
264 20:17:59.418362 - tftpboot 0x08000000 930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot
265 20:17:59.418785 - tftpboot 0x01070000 930530/tftp-deploy-takk6yrv/dtb/meson-g12b-a311d-libretech-cc.dtb
266 20:17:59.419209 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:17:59.419640 - bootm 0x01080000 0x08000000 0x01070000
268 20:17:59.420195 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:17:59.421802 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:17:59.422279 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 20:17:59.436527 Setting prompt string to ['lava-test: # ']
273 20:17:59.438096 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:17:59.438745 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:17:59.439420 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:17:59.440110 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:17:59.441400 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 20:17:59.478412 >> OK - accepted request
279 20:17:59.480647 Returned 0 in 0 seconds
280 20:17:59.581819 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:17:59.583556 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:17:59.584219 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:17:59.584783 Setting prompt string to ['Hit any key to stop autoboot']
285 20:17:59.585287 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:17:59.586996 Trying 192.168.56.21...
287 20:17:59.587511 Connected to conserv1.
288 20:17:59.588008 Escape character is '^]'.
289 20:17:59.588479
290 20:17:59.588944 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 20:17:59.589417
292 20:18:11.512331 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 20:18:11.512994 bl2_stage_init 0x01
294 20:18:11.513501 bl2_stage_init 0x81
295 20:18:11.517661 hw id: 0x0000 - pwm id 0x01
296 20:18:11.518306 bl2_stage_init 0xc1
297 20:18:11.518853 bl2_stage_init 0x02
298 20:18:11.519928
299 20:18:11.523447 L0:00000000
300 20:18:11.523951 L1:20000703
301 20:18:11.524424 L2:00008067
302 20:18:11.524861 L3:14000000
303 20:18:11.526276 B2:00402000
304 20:18:11.526739 B1:e0f83180
305 20:18:11.527172
306 20:18:11.527599 TE: 58124
307 20:18:11.528056
308 20:18:11.537946 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 20:18:11.538512
310 20:18:11.538949 Board ID = 1
311 20:18:11.539377 Set A53 clk to 24M
312 20:18:11.539805 Set A73 clk to 24M
313 20:18:11.543222 Set clk81 to 24M
314 20:18:11.543690 A53 clk: 1200 MHz
315 20:18:11.544158 A73 clk: 1200 MHz
316 20:18:11.548517 CLK81: 166.6M
317 20:18:11.549022 smccc: 00012a91
318 20:18:11.554050 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 20:18:11.554527 board id: 1
320 20:18:11.562759 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:18:11.573542 fw parse done
322 20:18:11.580193 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:18:11.621902 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:18:11.632802 PIEI prepare done
325 20:18:11.633289 fastboot data load
326 20:18:11.633724 fastboot data verify
327 20:18:11.638510 verify result: 266
328 20:18:11.643970 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 20:18:11.644508 LPDDR4 probe
330 20:18:11.644969 ddr clk to 1584MHz
331 20:18:11.651959 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:18:11.689304
333 20:18:11.689807 dmc_version 0001
334 20:18:11.696017 Check phy result
335 20:18:11.701887 INFO : End of CA training
336 20:18:11.702400 INFO : End of initialization
337 20:18:11.707398 INFO : Training has run successfully!
338 20:18:11.707872 Check phy result
339 20:18:11.713022 INFO : End of initialization
340 20:18:11.713492 INFO : End of read enable training
341 20:18:11.718589 INFO : End of fine write leveling
342 20:18:11.724212 INFO : End of Write leveling coarse delay
343 20:18:11.724682 INFO : Training has run successfully!
344 20:18:11.725127 Check phy result
345 20:18:11.729923 INFO : End of initialization
346 20:18:11.730395 INFO : End of read dq deskew training
347 20:18:11.735580 INFO : End of MPR read delay center optimization
348 20:18:11.741181 INFO : End of write delay center optimization
349 20:18:11.746529 INFO : End of read delay center optimization
350 20:18:11.747015 INFO : End of max read latency training
351 20:18:11.752132 INFO : Training has run successfully!
352 20:18:11.752601 1D training succeed
353 20:18:11.761462 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:18:11.809014 Check phy result
355 20:18:11.809530 INFO : End of initialization
356 20:18:11.830502 INFO : End of 2D read delay Voltage center optimization
357 20:18:11.850620 INFO : End of 2D read delay Voltage center optimization
358 20:18:11.902780 INFO : End of 2D write delay Voltage center optimization
359 20:18:11.951958 INFO : End of 2D write delay Voltage center optimization
360 20:18:11.957311 INFO : Training has run successfully!
361 20:18:11.957793
362 20:18:11.958240 channel==0
363 20:18:11.962970 RxClkDly_Margin_A0==88 ps 9
364 20:18:11.963442 TxDqDly_Margin_A0==98 ps 10
365 20:18:11.968522 RxClkDly_Margin_A1==88 ps 9
366 20:18:11.968982 TxDqDly_Margin_A1==88 ps 9
367 20:18:11.969428 TrainedVREFDQ_A0==74
368 20:18:11.974252 TrainedVREFDQ_A1==74
369 20:18:11.974714 VrefDac_Margin_A0==25
370 20:18:11.975156 DeviceVref_Margin_A0==40
371 20:18:11.979910 VrefDac_Margin_A1==24
372 20:18:11.980406 DeviceVref_Margin_A1==40
373 20:18:11.980854
374 20:18:11.981294
375 20:18:11.981731 channel==1
376 20:18:11.985359 RxClkDly_Margin_A0==98 ps 10
377 20:18:11.985821 TxDqDly_Margin_A0==98 ps 10
378 20:18:11.991003 RxClkDly_Margin_A1==88 ps 9
379 20:18:11.991462 TxDqDly_Margin_A1==88 ps 9
380 20:18:11.996484 TrainedVREFDQ_A0==77
381 20:18:11.996951 TrainedVREFDQ_A1==77
382 20:18:11.997395 VrefDac_Margin_A0==22
383 20:18:12.002154 DeviceVref_Margin_A0==37
384 20:18:12.002610 VrefDac_Margin_A1==24
385 20:18:12.007813 DeviceVref_Margin_A1==37
386 20:18:12.008295
387 20:18:12.008745 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:18:12.009184
389 20:18:12.041331 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 20:18:12.041900 2D training succeed
391 20:18:12.046901 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:18:12.052535 auto size-- 65535DDR cs0 size: 2048MB
393 20:18:12.053018 DDR cs1 size: 2048MB
394 20:18:12.058148 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:18:12.058625 cs0 DataBus test pass
396 20:18:12.063807 cs1 DataBus test pass
397 20:18:12.064312 cs0 AddrBus test pass
398 20:18:12.064788 cs1 AddrBus test pass
399 20:18:12.065235
400 20:18:12.069358 100bdlr_step_size ps== 420
401 20:18:12.069854 result report
402 20:18:12.075009 boot times 0Enable ddr reg access
403 20:18:12.080233 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:18:12.093640 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 20:18:12.665937 0.0;M3 CHK:0;cm4_sp_mode 0
406 20:18:12.666502 MVN_1=0x00000000
407 20:18:12.671282 MVN_2=0x00000000
408 20:18:12.677133 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 20:18:12.677619 OPS=0x10
410 20:18:12.678068 ring efuse init
411 20:18:12.678508 chipver efuse init
412 20:18:12.682733 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 20:18:12.688186 [0.018961 Inits done]
414 20:18:12.688657 secure task start!
415 20:18:12.689102 high task start!
416 20:18:12.692960 low task start!
417 20:18:12.693429 run into bl31
418 20:18:12.699593 NOTICE: BL31: v1.3(release):4fc40b1
419 20:18:12.707279 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 20:18:12.707759 NOTICE: BL31: G12A normal boot!
421 20:18:12.732795 NOTICE: BL31: BL33 decompress pass
422 20:18:12.738464 ERROR: Error initializing runtime service opteed_fast
423 20:18:13.971397
424 20:18:13.972048
425 20:18:13.979720 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 20:18:13.980245
427 20:18:13.980697 Model: Libre Computer AML-A311D-CC Alta
428 20:18:14.188107 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 20:18:14.211457 DRAM: 2 GiB (effective 3.8 GiB)
430 20:18:14.354436 Core: 408 devices, 31 uclasses, devicetree: separate
431 20:18:14.360391 WDT: Not starting watchdog@f0d0
432 20:18:14.392481 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 20:18:14.404953 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 20:18:14.409997 ** Bad device specification mmc 0 **
435 20:18:14.420314 Card did not respond to voltage select! : -110
436 20:18:14.427883 ** Bad device specification mmc 0 **
437 20:18:14.428393 Couldn't find partition mmc 0
438 20:18:14.436325 Card did not respond to voltage select! : -110
439 20:18:14.441745 ** Bad device specification mmc 0 **
440 20:18:14.442213 Couldn't find partition mmc 0
441 20:18:14.446822 Error: could not access storage.
442 20:18:15.712588 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 20:18:15.713258 bl2_stage_init 0x81
444 20:18:15.718112 hw id: 0x0000 - pwm id 0x01
445 20:18:15.718616 bl2_stage_init 0xc1
446 20:18:15.719066 bl2_stage_init 0x02
447 20:18:15.719507
448 20:18:15.723737 L0:00000000
449 20:18:15.724277 L1:20000703
450 20:18:15.724727 L2:00008067
451 20:18:15.725169 L3:14000000
452 20:18:15.725604 B2:00402000
453 20:18:15.729242 B1:e0f83180
454 20:18:15.729716
455 20:18:15.730163 TE: 58150
456 20:18:15.730605
457 20:18:15.735121 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 20:18:15.735623
459 20:18:15.736110 Board ID = 1
460 20:18:15.740596 Set A53 clk to 24M
461 20:18:15.741066 Set A73 clk to 24M
462 20:18:15.741510 Set clk81 to 24M
463 20:18:15.746065 A53 clk: 1200 MHz
464 20:18:15.746541 A73 clk: 1200 MHz
465 20:18:15.746985 CLK81: 166.6M
466 20:18:15.747421 smccc: 00012aac
467 20:18:15.751744 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 20:18:15.757312 board id: 1
469 20:18:15.763310 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 20:18:15.773593 fw parse done
471 20:18:15.779546 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 20:18:15.822240 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 20:18:15.833162 PIEI prepare done
474 20:18:15.833659 fastboot data load
475 20:18:15.834119 fastboot data verify
476 20:18:15.838781 verify result: 266
477 20:18:15.844378 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 20:18:15.844853 LPDDR4 probe
479 20:18:15.845297 ddr clk to 1584MHz
480 20:18:15.852474 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 20:18:15.889774
482 20:18:15.890320 dmc_version 0001
483 20:18:15.900915 Check phy result
484 20:18:15.901577 INFO : End of CA training
485 20:18:15.906377 INFO : End of initialization
486 20:18:15.906967 INFO : Training has run successfully!
487 20:18:15.912131 Check phy result
488 20:18:15.912704 INFO : End of initialization
489 20:18:15.917621 INFO : End of read enable training
490 20:18:15.918181 INFO : End of fine write leveling
491 20:18:15.923248 INFO : End of Write leveling coarse delay
492 20:18:15.923804 INFO : Training has run successfully!
493 20:18:15.928882 Check phy result
494 20:18:15.929432 INFO : End of initialization
495 20:18:15.934477 INFO : End of read dq deskew training
496 20:18:15.940100 INFO : End of MPR read delay center optimization
497 20:18:15.940668 INFO : End of write delay center optimization
498 20:18:15.945617 INFO : End of read delay center optimization
499 20:18:15.951261 INFO : End of max read latency training
500 20:18:15.951836 INFO : Training has run successfully!
501 20:18:15.956952 1D training succeed
502 20:18:15.961976 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 20:18:16.009569 Check phy result
504 20:18:16.010208 INFO : End of initialization
505 20:18:16.032129 INFO : End of 2D read delay Voltage center optimization
506 20:18:16.052410 INFO : End of 2D read delay Voltage center optimization
507 20:18:16.106015 INFO : End of 2D write delay Voltage center optimization
508 20:18:16.153761 INFO : End of 2D write delay Voltage center optimization
509 20:18:16.159255 INFO : Training has run successfully!
510 20:18:16.159821
511 20:18:16.160352 channel==0
512 20:18:16.164764 RxClkDly_Margin_A0==88 ps 9
513 20:18:16.165293 TxDqDly_Margin_A0==98 ps 10
514 20:18:16.170410 RxClkDly_Margin_A1==88 ps 9
515 20:18:16.171016 TxDqDly_Margin_A1==98 ps 10
516 20:18:16.171451 TrainedVREFDQ_A0==74
517 20:18:16.176350 TrainedVREFDQ_A1==74
518 20:18:16.176956 VrefDac_Margin_A0==24
519 20:18:16.177429 DeviceVref_Margin_A0==40
520 20:18:16.181654 VrefDac_Margin_A1==24
521 20:18:16.182250 DeviceVref_Margin_A1==40
522 20:18:16.182696
523 20:18:16.183135
524 20:18:16.187379 channel==1
525 20:18:16.187939 RxClkDly_Margin_A0==98 ps 10
526 20:18:16.188403 TxDqDly_Margin_A0==88 ps 9
527 20:18:16.192974 RxClkDly_Margin_A1==88 ps 9
528 20:18:16.193569 TxDqDly_Margin_A1==88 ps 9
529 20:18:16.198613 TrainedVREFDQ_A0==76
530 20:18:16.199210 TrainedVREFDQ_A1==77
531 20:18:16.199678 VrefDac_Margin_A0==22
532 20:18:16.204240 DeviceVref_Margin_A0==38
533 20:18:16.204845 VrefDac_Margin_A1==24
534 20:18:16.209591 DeviceVref_Margin_A1==37
535 20:18:16.210119
536 20:18:16.210546 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 20:18:16.210953
538 20:18:16.243304 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
539 20:18:16.243938 2D training succeed
540 20:18:16.249034 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 20:18:16.254362 auto size-- 65535DDR cs0 size: 2048MB
542 20:18:16.254881 DDR cs1 size: 2048MB
543 20:18:16.259922 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 20:18:16.260471 cs0 DataBus test pass
545 20:18:16.265558 cs1 DataBus test pass
546 20:18:16.266041 cs0 AddrBus test pass
547 20:18:16.266453 cs1 AddrBus test pass
548 20:18:16.266851
549 20:18:16.271244 100bdlr_step_size ps== 420
550 20:18:16.271726 result report
551 20:18:16.276752 boot times 0Enable ddr reg access
552 20:18:16.282041 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 20:18:16.295605 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 20:18:16.869216 0.0;M3 CHK:0;cm4_sp_mode 0
555 20:18:16.869809 MVN_1=0x00000000
556 20:18:16.874653 MVN_2=0x00000000
557 20:18:16.880490 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 20:18:16.881017 OPS=0x10
559 20:18:16.881460 ring efuse init
560 20:18:16.881855 chipver efuse init
561 20:18:16.888720 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 20:18:16.889234 [0.018961 Inits done]
563 20:18:16.889627 secure task start!
564 20:18:16.897114 high task start!
565 20:18:16.897664 low task start!
566 20:18:16.898070 run into bl31
567 20:18:16.902786 NOTICE: BL31: v1.3(release):4fc40b1
568 20:18:16.910578 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 20:18:16.911056 NOTICE: BL31: G12A normal boot!
570 20:18:16.936017 NOTICE: BL31: BL33 decompress pass
571 20:18:16.941659 ERROR: Error initializing runtime service opteed_fast
572 20:18:18.174579
573 20:18:18.175200
574 20:18:18.182923 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 20:18:18.183415
576 20:18:18.183831 Model: Libre Computer AML-A311D-CC Alta
577 20:18:18.391342 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 20:18:18.414821 DRAM: 2 GiB (effective 3.8 GiB)
579 20:18:18.557814 Core: 408 devices, 31 uclasses, devicetree: separate
580 20:18:18.563562 WDT: Not starting watchdog@f0d0
581 20:18:18.595917 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 20:18:18.608375 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 20:18:18.613367 ** Bad device specification mmc 0 **
584 20:18:18.623792 Card did not respond to voltage select! : -110
585 20:18:18.631348 ** Bad device specification mmc 0 **
586 20:18:18.631810 Couldn't find partition mmc 0
587 20:18:18.639775 Card did not respond to voltage select! : -110
588 20:18:18.645292 ** Bad device specification mmc 0 **
589 20:18:18.645753 Couldn't find partition mmc 0
590 20:18:18.650243 Error: could not access storage.
591 20:18:18.992710 Net: eth0: ethernet@ff3f0000
592 20:18:18.993257 starting USB...
593 20:18:19.244599 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 20:18:19.245169 Starting the controller
595 20:18:19.251491 USB XHCI 1.10
596 20:18:20.962621 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 20:18:20.963209 bl2_stage_init 0x01
598 20:18:20.963633 bl2_stage_init 0x81
599 20:18:20.968311 hw id: 0x0000 - pwm id 0x01
600 20:18:20.968784 bl2_stage_init 0xc1
601 20:18:20.969194 bl2_stage_init 0x02
602 20:18:20.969597
603 20:18:20.973799 L0:00000000
604 20:18:20.974258 L1:20000703
605 20:18:20.974664 L2:00008067
606 20:18:20.975063 L3:14000000
607 20:18:20.976752 B2:00402000
608 20:18:20.977202 B1:e0f83180
609 20:18:20.977604
610 20:18:20.978002 TE: 58159
611 20:18:20.978403
612 20:18:20.987882 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 20:18:20.988373
614 20:18:20.988782 Board ID = 1
615 20:18:20.989181 Set A53 clk to 24M
616 20:18:20.989577 Set A73 clk to 24M
617 20:18:20.993519 Set clk81 to 24M
618 20:18:20.993980 A53 clk: 1200 MHz
619 20:18:20.994385 A73 clk: 1200 MHz
620 20:18:20.999103 CLK81: 166.6M
621 20:18:20.999558 smccc: 00012ab5
622 20:18:21.004727 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 20:18:21.005182 board id: 1
624 20:18:21.013296 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 20:18:21.023947 fw parse done
626 20:18:21.029934 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 20:18:21.072566 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 20:18:21.083520 PIEI prepare done
629 20:18:21.084114 fastboot data load
630 20:18:21.084560 fastboot data verify
631 20:18:21.089250 verify result: 266
632 20:18:21.094705 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 20:18:21.095225 LPDDR4 probe
634 20:18:21.095635 ddr clk to 1584MHz
635 20:18:21.102680 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 20:18:21.139959
637 20:18:21.140559 dmc_version 0001
638 20:18:21.146669 Check phy result
639 20:18:21.152484 INFO : End of CA training
640 20:18:21.152990 INFO : End of initialization
641 20:18:21.158206 INFO : Training has run successfully!
642 20:18:21.158672 Check phy result
643 20:18:21.163674 INFO : End of initialization
644 20:18:21.164172 INFO : End of read enable training
645 20:18:21.169252 INFO : End of fine write leveling
646 20:18:21.174872 INFO : End of Write leveling coarse delay
647 20:18:21.175344 INFO : Training has run successfully!
648 20:18:21.175749 Check phy result
649 20:18:21.180430 INFO : End of initialization
650 20:18:21.180893 INFO : End of read dq deskew training
651 20:18:21.186189 INFO : End of MPR read delay center optimization
652 20:18:21.191649 INFO : End of write delay center optimization
653 20:18:21.197305 INFO : End of read delay center optimization
654 20:18:21.197786 INFO : End of max read latency training
655 20:18:21.202889 INFO : Training has run successfully!
656 20:18:21.203359 1D training succeed
657 20:18:21.212095 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 20:18:21.259740 Check phy result
659 20:18:21.260361 INFO : End of initialization
660 20:18:21.282293 INFO : End of 2D read delay Voltage center optimization
661 20:18:21.302532 INFO : End of 2D read delay Voltage center optimization
662 20:18:21.354850 INFO : End of 2D write delay Voltage center optimization
663 20:18:21.404133 INFO : End of 2D write delay Voltage center optimization
664 20:18:21.409639 INFO : Training has run successfully!
665 20:18:21.410141
666 20:18:21.410553 channel==0
667 20:18:21.415360 RxClkDly_Margin_A0==88 ps 9
668 20:18:21.415865 TxDqDly_Margin_A0==98 ps 10
669 20:18:21.418805 RxClkDly_Margin_A1==88 ps 9
670 20:18:21.419266 TxDqDly_Margin_A1==98 ps 10
671 20:18:21.424420 TrainedVREFDQ_A0==74
672 20:18:21.424913 TrainedVREFDQ_A1==74
673 20:18:21.425321 VrefDac_Margin_A0==25
674 20:18:21.429795 DeviceVref_Margin_A0==40
675 20:18:21.430250 VrefDac_Margin_A1==25
676 20:18:21.435398 DeviceVref_Margin_A1==40
677 20:18:21.435866
678 20:18:21.436312
679 20:18:21.436718 channel==1
680 20:18:21.437113 RxClkDly_Margin_A0==98 ps 10
681 20:18:21.441031 TxDqDly_Margin_A0==98 ps 10
682 20:18:21.441513 RxClkDly_Margin_A1==98 ps 10
683 20:18:21.446647 TxDqDly_Margin_A1==88 ps 9
684 20:18:21.447117 TrainedVREFDQ_A0==77
685 20:18:21.447524 TrainedVREFDQ_A1==77
686 20:18:21.452318 VrefDac_Margin_A0==22
687 20:18:21.452773 DeviceVref_Margin_A0==37
688 20:18:21.457820 VrefDac_Margin_A1==24
689 20:18:21.458275 DeviceVref_Margin_A1==37
690 20:18:21.458678
691 20:18:21.463376 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 20:18:21.463825
693 20:18:21.491327 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 20:18:21.496907 2D training succeed
695 20:18:21.502558 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 20:18:21.503017 auto size-- 65535DDR cs0 size: 2048MB
697 20:18:21.508309 DDR cs1 size: 2048MB
698 20:18:21.508764 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 20:18:21.513774 cs0 DataBus test pass
700 20:18:21.514229 cs1 DataBus test pass
701 20:18:21.514634 cs0 AddrBus test pass
702 20:18:21.519307 cs1 AddrBus test pass
703 20:18:21.519757
704 20:18:21.520214 100bdlr_step_size ps== 420
705 20:18:21.520624 result report
706 20:18:21.524939 boot times 0Enable ddr reg access
707 20:18:21.532521 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 20:18:21.545973 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 20:18:22.119650 0.0;M3 CHK:0;cm4_sp_mode 0
710 20:18:22.120287 MVN_1=0x00000000
711 20:18:22.125146 MVN_2=0x00000000
712 20:18:22.130933 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 20:18:22.131425 OPS=0x10
714 20:18:22.131819 ring efuse init
715 20:18:22.132249 chipver efuse init
716 20:18:22.136450 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 20:18:22.142043 [0.018961 Inits done]
718 20:18:22.142484 secure task start!
719 20:18:22.142868 high task start!
720 20:18:22.146613 low task start!
721 20:18:22.147049 run into bl31
722 20:18:22.153287 NOTICE: BL31: v1.3(release):4fc40b1
723 20:18:22.161100 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 20:18:22.161545 NOTICE: BL31: G12A normal boot!
725 20:18:22.186401 NOTICE: BL31: BL33 decompress pass
726 20:18:22.192191 ERROR: Error initializing runtime service opteed_fast
727 20:18:23.425061
728 20:18:23.425636
729 20:18:23.433566 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 20:18:23.434044
731 20:18:23.434455 Model: Libre Computer AML-A311D-CC Alta
732 20:18:23.641897 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 20:18:23.665268 DRAM: 2 GiB (effective 3.8 GiB)
734 20:18:23.808298 Core: 408 devices, 31 uclasses, devicetree: separate
735 20:18:23.814134 WDT: Not starting watchdog@f0d0
736 20:18:23.846556 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 20:18:23.858841 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 20:18:23.863869 ** Bad device specification mmc 0 **
739 20:18:23.874168 Card did not respond to voltage select! : -110
740 20:18:23.881828 ** Bad device specification mmc 0 **
741 20:18:23.882278 Couldn't find partition mmc 0
742 20:18:23.890150 Card did not respond to voltage select! : -110
743 20:18:23.895658 ** Bad device specification mmc 0 **
744 20:18:23.896137 Couldn't find partition mmc 0
745 20:18:23.900763 Error: could not access storage.
746 20:18:24.244290 Net: eth0: ethernet@ff3f0000
747 20:18:24.244821 starting USB...
748 20:18:24.496085 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 20:18:24.496599 Starting the controller
750 20:18:24.503010 USB XHCI 1.10
751 20:18:26.664427 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 20:18:26.665015 bl2_stage_init 0x01
753 20:18:26.665428 bl2_stage_init 0x81
754 20:18:26.669890 hw id: 0x0000 - pwm id 0x01
755 20:18:26.670353 bl2_stage_init 0xc1
756 20:18:26.670764 bl2_stage_init 0x02
757 20:18:26.671166
758 20:18:26.675488 L0:00000000
759 20:18:26.675947 L1:20000703
760 20:18:26.676411 L2:00008067
761 20:18:26.676810 L3:14000000
762 20:18:26.681071 B2:00402000
763 20:18:26.681529 B1:e0f83180
764 20:18:26.681927
765 20:18:26.682324 TE: 58167
766 20:18:26.682721
767 20:18:26.686742 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 20:18:26.687206
769 20:18:26.687610 Board ID = 1
770 20:18:26.692178 Set A53 clk to 24M
771 20:18:26.692635 Set A73 clk to 24M
772 20:18:26.693035 Set clk81 to 24M
773 20:18:26.697833 A53 clk: 1200 MHz
774 20:18:26.698287 A73 clk: 1200 MHz
775 20:18:26.698692 CLK81: 166.6M
776 20:18:26.699084 smccc: 00012abd
777 20:18:26.703481 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 20:18:26.709021 board id: 1
779 20:18:26.715030 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 20:18:26.725488 fw parse done
781 20:18:26.731521 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 20:18:26.774036 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 20:18:26.784990 PIEI prepare done
784 20:18:26.785458 fastboot data load
785 20:18:26.785869 fastboot data verify
786 20:18:26.790650 verify result: 266
787 20:18:26.796156 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 20:18:26.796624 LPDDR4 probe
789 20:18:26.797028 ddr clk to 1584MHz
790 20:18:26.804220 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 20:18:26.841448
792 20:18:26.842019 dmc_version 0001
793 20:18:26.848237 Check phy result
794 20:18:26.853990 INFO : End of CA training
795 20:18:26.854473 INFO : End of initialization
796 20:18:26.859604 INFO : Training has run successfully!
797 20:18:26.860141 Check phy result
798 20:18:26.865271 INFO : End of initialization
799 20:18:26.865755 INFO : End of read enable training
800 20:18:26.870796 INFO : End of fine write leveling
801 20:18:26.876487 INFO : End of Write leveling coarse delay
802 20:18:26.876946 INFO : Training has run successfully!
803 20:18:26.877351 Check phy result
804 20:18:26.882047 INFO : End of initialization
805 20:18:26.882503 INFO : End of read dq deskew training
806 20:18:26.887591 INFO : End of MPR read delay center optimization
807 20:18:26.893239 INFO : End of write delay center optimization
808 20:18:26.898770 INFO : End of read delay center optimization
809 20:18:26.899224 INFO : End of max read latency training
810 20:18:26.904520 INFO : Training has run successfully!
811 20:18:26.904986 1D training succeed
812 20:18:26.913557 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 20:18:26.961209 Check phy result
814 20:18:26.961737 INFO : End of initialization
815 20:18:26.982959 INFO : End of 2D read delay Voltage center optimization
816 20:18:27.003178 INFO : End of 2D read delay Voltage center optimization
817 20:18:27.055425 INFO : End of 2D write delay Voltage center optimization
818 20:18:27.104703 INFO : End of 2D write delay Voltage center optimization
819 20:18:27.110180 INFO : Training has run successfully!
820 20:18:27.110633
821 20:18:27.111043 channel==0
822 20:18:27.115768 RxClkDly_Margin_A0==88 ps 9
823 20:18:27.116270 TxDqDly_Margin_A0==98 ps 10
824 20:18:27.119137 RxClkDly_Margin_A1==88 ps 9
825 20:18:27.119591 TxDqDly_Margin_A1==88 ps 9
826 20:18:27.124839 TrainedVREFDQ_A0==74
827 20:18:27.125294 TrainedVREFDQ_A1==74
828 20:18:27.125713 VrefDac_Margin_A0==25
829 20:18:27.130372 DeviceVref_Margin_A0==40
830 20:18:27.130844 VrefDac_Margin_A1==25
831 20:18:27.135920 DeviceVref_Margin_A1==40
832 20:18:27.136410
833 20:18:27.136800
834 20:18:27.137182 channel==1
835 20:18:27.137564 RxClkDly_Margin_A0==98 ps 10
836 20:18:27.141532 TxDqDly_Margin_A0==98 ps 10
837 20:18:27.141985 RxClkDly_Margin_A1==98 ps 10
838 20:18:27.147068 TxDqDly_Margin_A1==88 ps 9
839 20:18:27.147564 TrainedVREFDQ_A0==77
840 20:18:27.148025 TrainedVREFDQ_A1==77
841 20:18:27.152706 VrefDac_Margin_A0==22
842 20:18:27.153178 DeviceVref_Margin_A0==37
843 20:18:27.158332 VrefDac_Margin_A1==22
844 20:18:27.158774 DeviceVref_Margin_A1==37
845 20:18:27.159160
846 20:18:27.163913 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 20:18:27.164386
848 20:18:27.191851 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 20:18:27.197517 2D training succeed
850 20:18:27.203042 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 20:18:27.203492 auto size-- 65535DDR cs0 size: 2048MB
852 20:18:27.208769 DDR cs1 size: 2048MB
853 20:18:27.209213 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 20:18:27.214356 cs0 DataBus test pass
855 20:18:27.214796 cs1 DataBus test pass
856 20:18:27.215182 cs0 AddrBus test pass
857 20:18:27.219913 cs1 AddrBus test pass
858 20:18:27.220398
859 20:18:27.220788 100bdlr_step_size ps== 420
860 20:18:27.221179 result report
861 20:18:27.225596 boot times 0Enable ddr reg access
862 20:18:27.233084 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 20:18:27.246492 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 20:18:27.819628 0.0;M3 CHK:0;cm4_sp_mode 0
865 20:18:27.820305 MVN_1=0x00000000
866 20:18:27.825059 MVN_2=0x00000000
867 20:18:27.830862 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 20:18:27.831326 OPS=0x10
869 20:18:27.831747 ring efuse init
870 20:18:27.832198 chipver efuse init
871 20:18:27.836435 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 20:18:27.842038 [0.018960 Inits done]
873 20:18:27.842500 secure task start!
874 20:18:27.842905 high task start!
875 20:18:27.846601 low task start!
876 20:18:27.847053 run into bl31
877 20:18:27.853232 NOTICE: BL31: v1.3(release):4fc40b1
878 20:18:27.861148 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 20:18:27.861620 NOTICE: BL31: G12A normal boot!
880 20:18:27.886349 NOTICE: BL31: BL33 decompress pass
881 20:18:27.892337 ERROR: Error initializing runtime service opteed_fast
882 20:18:29.124906
883 20:18:29.125511
884 20:18:29.133325 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 20:18:29.133806
886 20:18:29.134215 Model: Libre Computer AML-A311D-CC Alta
887 20:18:29.341749 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 20:18:29.365208 DRAM: 2 GiB (effective 3.8 GiB)
889 20:18:29.508167 Core: 408 devices, 31 uclasses, devicetree: separate
890 20:18:29.514022 WDT: Not starting watchdog@f0d0
891 20:18:29.546317 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 20:18:29.558679 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 20:18:29.562830 ** Bad device specification mmc 0 **
894 20:18:29.574085 Card did not respond to voltage select! : -110
895 20:18:29.581679 ** Bad device specification mmc 0 **
896 20:18:29.582144 Couldn't find partition mmc 0
897 20:18:29.590013 Card did not respond to voltage select! : -110
898 20:18:29.595538 ** Bad device specification mmc 0 **
899 20:18:29.596030 Couldn't find partition mmc 0
900 20:18:29.600554 Error: could not access storage.
901 20:18:29.944183 Net: eth0: ethernet@ff3f0000
902 20:18:29.944753 starting USB...
903 20:18:30.195922 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 20:18:30.196542 Starting the controller
905 20:18:30.202890 USB XHCI 1.10
906 20:18:31.869283 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 20:18:31.872395 scanning usb for storage devices... 0 Storage Device(s) found
909 20:18:31.923923 Hit any key to stop autoboot: 1
910 20:18:31.924763 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 20:18:31.925476 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
912 20:18:31.925955 Setting prompt string to ['=>']
913 20:18:31.926431 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
914 20:18:31.932607 0
915 20:18:31.933505 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 20:18:31.934005 Sending with 10 millisecond of delay
918 20:18:33.068652 => setenv autoload no
919 20:18:33.079455 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
920 20:18:33.084407 setenv autoload no
921 20:18:33.085121 Sending with 10 millisecond of delay
923 20:18:34.881822 => setenv initrd_high 0xffffffff
924 20:18:34.892589 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 20:18:34.893423 setenv initrd_high 0xffffffff
926 20:18:34.894123 Sending with 10 millisecond of delay
928 20:18:36.509969 => setenv fdt_high 0xffffffff
929 20:18:36.520721 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 20:18:36.521558 setenv fdt_high 0xffffffff
931 20:18:36.522262 Sending with 10 millisecond of delay
933 20:18:36.814035 => dhcp
934 20:18:36.824795 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 20:18:36.825632 dhcp
936 20:18:36.826063 Speed: 1000, full duplex
937 20:18:36.826470 BOOTP broadcast 1
938 20:18:36.833947 DHCP client bound to address 192.168.6.27 (9 ms)
939 20:18:36.834674 Sending with 10 millisecond of delay
941 20:18:38.510757 => setenv serverip 192.168.6.2
942 20:18:38.521532 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
943 20:18:38.522440 setenv serverip 192.168.6.2
944 20:18:38.523119 Sending with 10 millisecond of delay
946 20:18:42.245576 => tftpboot 0x01080000 930530/tftp-deploy-takk6yrv/kernel/uImage
947 20:18:42.256379 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
948 20:18:42.257221 tftpboot 0x01080000 930530/tftp-deploy-takk6yrv/kernel/uImage
949 20:18:42.257663 Speed: 1000, full duplex
950 20:18:42.258075 Using ethernet@ff3f0000 device
951 20:18:42.259334 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
952 20:18:42.264835 Filename '930530/tftp-deploy-takk6yrv/kernel/uImage'.
953 20:18:42.268664 Load address: 0x1080000
954 20:18:45.121468 Loading: *################################################## 43.6 MiB
955 20:18:45.122103 15.3 MiB/s
956 20:18:45.122540 done
957 20:18:45.126204 Bytes transferred = 45713984 (2b98a40 hex)
958 20:18:45.127098 Sending with 10 millisecond of delay
960 20:18:49.813050 => tftpboot 0x08000000 930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot
961 20:18:49.823852 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
962 20:18:49.824735 tftpboot 0x08000000 930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot
963 20:18:49.825179 Speed: 1000, full duplex
964 20:18:49.825593 Using ethernet@ff3f0000 device
965 20:18:49.826620 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
966 20:18:49.835155 Filename '930530/tftp-deploy-takk6yrv/ramdisk/ramdisk.cpio.gz.uboot'.
967 20:18:49.835452 Load address: 0x8000000
968 20:18:56.971654 Loading: *################T ################################# UDP wrong checksum 00000005 0000f20d
969 20:19:01.972825 T UDP wrong checksum 00000005 0000f20d
970 20:19:02.285207 UDP wrong checksum 000000ff 0000b88d
971 20:19:02.326775 UDP wrong checksum 000000ff 00005180
972 20:19:11.976082 T T UDP wrong checksum 00000005 0000f20d
973 20:19:31.979832 T T T T UDP wrong checksum 00000005 0000f20d
974 20:19:46.984049 T T
975 20:19:46.984676 Retry count exceeded; starting again
977 20:19:46.986103 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
980 20:19:46.987967 end: 2.4 uboot-commands (duration 00:01:48) [common]
982 20:19:46.989389 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
984 20:19:46.990460 end: 2 uboot-action (duration 00:01:48) [common]
986 20:19:46.991944 Cleaning after the job
987 20:19:46.992515 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/ramdisk
988 20:19:46.993794 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/kernel
989 20:19:47.007915 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/dtb
990 20:19:47.009067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930530/tftp-deploy-takk6yrv/modules
991 20:19:47.014991 start: 4.1 power-off (timeout 00:00:30) [common]
992 20:19:47.015589 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
993 20:19:47.050126 >> OK - accepted request
994 20:19:47.052249 Returned 0 in 0 seconds
995 20:19:47.153367 end: 4.1 power-off (duration 00:00:00) [common]
997 20:19:47.155034 start: 4.2 read-feedback (timeout 00:10:00) [common]
998 20:19:47.156173 Listened to connection for namespace 'common' for up to 1s
999 20:19:48.156925 Finalising connection for namespace 'common'
1000 20:19:48.157407 Disconnecting from shell: Finalise
1001 20:19:48.157678 =>
1002 20:19:48.258338 end: 4.2 read-feedback (duration 00:00:01) [common]
1003 20:19:48.258989 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/930530
1004 20:19:48.561218 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/930530
1005 20:19:48.561809 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.