Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:46:04.186311 lava-dispatcher, installed at version: 2024.01
2 20:46:04.187094 start: 0 validate
3 20:46:04.187596 Start time: 2024-11-03 20:46:04.187566+00:00 (UTC)
4 20:46:04.188167 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:46:04.188718 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:46:04.224047 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:46:04.224619 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:46:04.253926 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:46:04.254557 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:46:04.285808 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:46:04.286319 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:46:04.315706 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:46:04.316244 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-366-g886b7e80ab198%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:46:04.353302 validate duration: 0.17
16 20:46:04.354177 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:46:04.354533 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:46:04.354886 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:46:04.355489 Not decompressing ramdisk as can be used compressed.
20 20:46:04.355957 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 20:46:04.356294 saving as /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/ramdisk/initrd.cpio.gz
22 20:46:04.356598 total size: 5628169 (5 MB)
23 20:46:04.390031 progress 0 % (0 MB)
24 20:46:04.394068 progress 5 % (0 MB)
25 20:46:04.398285 progress 10 % (0 MB)
26 20:46:04.402120 progress 15 % (0 MB)
27 20:46:04.406169 progress 20 % (1 MB)
28 20:46:04.409808 progress 25 % (1 MB)
29 20:46:04.413861 progress 30 % (1 MB)
30 20:46:04.417886 progress 35 % (1 MB)
31 20:46:04.421567 progress 40 % (2 MB)
32 20:46:04.425666 progress 45 % (2 MB)
33 20:46:04.429260 progress 50 % (2 MB)
34 20:46:04.433360 progress 55 % (2 MB)
35 20:46:04.437434 progress 60 % (3 MB)
36 20:46:04.441044 progress 65 % (3 MB)
37 20:46:04.445053 progress 70 % (3 MB)
38 20:46:04.448677 progress 75 % (4 MB)
39 20:46:04.452729 progress 80 % (4 MB)
40 20:46:04.456460 progress 85 % (4 MB)
41 20:46:04.460545 progress 90 % (4 MB)
42 20:46:04.464423 progress 95 % (5 MB)
43 20:46:04.467700 progress 100 % (5 MB)
44 20:46:04.468385 5 MB downloaded in 0.11 s (48.02 MB/s)
45 20:46:04.468917 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:46:04.469831 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:46:04.470129 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:46:04.470401 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:46:04.470883 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/kernel/Image
51 20:46:04.471132 saving as /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/kernel/Image
52 20:46:04.471344 total size: 45713920 (43 MB)
53 20:46:04.471554 No compression specified
54 20:46:04.505882 progress 0 % (0 MB)
55 20:46:04.534386 progress 5 % (2 MB)
56 20:46:04.562871 progress 10 % (4 MB)
57 20:46:04.591335 progress 15 % (6 MB)
58 20:46:04.619213 progress 20 % (8 MB)
59 20:46:04.646895 progress 25 % (10 MB)
60 20:46:04.674776 progress 30 % (13 MB)
61 20:46:04.703215 progress 35 % (15 MB)
62 20:46:04.730928 progress 40 % (17 MB)
63 20:46:04.758631 progress 45 % (19 MB)
64 20:46:04.787012 progress 50 % (21 MB)
65 20:46:04.814877 progress 55 % (24 MB)
66 20:46:04.843220 progress 60 % (26 MB)
67 20:46:04.871024 progress 65 % (28 MB)
68 20:46:04.899555 progress 70 % (30 MB)
69 20:46:04.928061 progress 75 % (32 MB)
70 20:46:04.956365 progress 80 % (34 MB)
71 20:46:04.984372 progress 85 % (37 MB)
72 20:46:05.012857 progress 90 % (39 MB)
73 20:46:05.041125 progress 95 % (41 MB)
74 20:46:05.069184 progress 100 % (43 MB)
75 20:46:05.069750 43 MB downloaded in 0.60 s (72.86 MB/s)
76 20:46:05.070230 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:46:05.071081 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:46:05.071359 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:46:05.071622 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:46:05.072116 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:46:05.072393 saving as /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:46:05.072602 total size: 54703 (0 MB)
84 20:46:05.072809 No compression specified
85 20:46:05.109418 progress 59 % (0 MB)
86 20:46:05.110332 progress 100 % (0 MB)
87 20:46:05.110936 0 MB downloaded in 0.04 s (1.36 MB/s)
88 20:46:05.111472 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:46:05.112425 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:46:05.112718 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:46:05.112991 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:46:05.113498 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 20:46:05.113785 saving as /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/nfsrootfs/full.rootfs.tar
95 20:46:05.114011 total size: 120894716 (115 MB)
96 20:46:05.114253 Using unxz to decompress xz
97 20:46:05.149680 progress 0 % (0 MB)
98 20:46:05.946519 progress 5 % (5 MB)
99 20:46:06.796351 progress 10 % (11 MB)
100 20:46:07.594463 progress 15 % (17 MB)
101 20:46:08.333866 progress 20 % (23 MB)
102 20:46:08.926205 progress 25 % (28 MB)
103 20:46:09.764531 progress 30 % (34 MB)
104 20:46:10.564726 progress 35 % (40 MB)
105 20:46:10.914096 progress 40 % (46 MB)
106 20:46:11.288936 progress 45 % (51 MB)
107 20:46:12.008522 progress 50 % (57 MB)
108 20:46:12.894528 progress 55 % (63 MB)
109 20:46:13.677494 progress 60 % (69 MB)
110 20:46:14.441347 progress 65 % (74 MB)
111 20:46:15.222121 progress 70 % (80 MB)
112 20:46:16.173141 progress 75 % (86 MB)
113 20:46:17.068626 progress 80 % (92 MB)
114 20:46:17.841566 progress 85 % (98 MB)
115 20:46:18.717361 progress 90 % (103 MB)
116 20:46:19.496216 progress 95 % (109 MB)
117 20:46:20.336791 progress 100 % (115 MB)
118 20:46:20.349311 115 MB downloaded in 15.24 s (7.57 MB/s)
119 20:46:20.350221 end: 1.4.1 http-download (duration 00:00:15) [common]
121 20:46:20.351790 end: 1.4 download-retry (duration 00:00:15) [common]
122 20:46:20.352376 start: 1.5 download-retry (timeout 00:09:44) [common]
123 20:46:20.352886 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 20:46:20.354311 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/modules.tar.xz
125 20:46:20.354832 saving as /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/modules/modules.tar
126 20:46:20.355265 total size: 11615340 (11 MB)
127 20:46:20.355692 Using unxz to decompress xz
128 20:46:20.399836 progress 0 % (0 MB)
129 20:46:20.469065 progress 5 % (0 MB)
130 20:46:20.543507 progress 10 % (1 MB)
131 20:46:20.639836 progress 15 % (1 MB)
132 20:46:20.732334 progress 20 % (2 MB)
133 20:46:20.812360 progress 25 % (2 MB)
134 20:46:20.887493 progress 30 % (3 MB)
135 20:46:20.966179 progress 35 % (3 MB)
136 20:46:21.038663 progress 40 % (4 MB)
137 20:46:21.116959 progress 45 % (5 MB)
138 20:46:21.200081 progress 50 % (5 MB)
139 20:46:21.276128 progress 55 % (6 MB)
140 20:46:21.360339 progress 60 % (6 MB)
141 20:46:21.439820 progress 65 % (7 MB)
142 20:46:21.519151 progress 70 % (7 MB)
143 20:46:21.596489 progress 75 % (8 MB)
144 20:46:21.679918 progress 80 % (8 MB)
145 20:46:21.758662 progress 85 % (9 MB)
146 20:46:21.840660 progress 90 % (10 MB)
147 20:46:21.912707 progress 95 % (10 MB)
148 20:46:21.988233 progress 100 % (11 MB)
149 20:46:22.000174 11 MB downloaded in 1.64 s (6.73 MB/s)
150 20:46:22.001088 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:46:22.002836 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:46:22.003403 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 20:46:22.003965 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 20:46:38.832490 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/930521/extract-nfsrootfs-pnzvseau
156 20:46:38.833102 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 20:46:38.833393 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 20:46:38.834166 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y
159 20:46:38.834621 makedir: /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin
160 20:46:38.834946 makedir: /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/tests
161 20:46:38.835260 makedir: /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/results
162 20:46:38.835592 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-add-keys
163 20:46:38.836150 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-add-sources
164 20:46:38.836672 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-background-process-start
165 20:46:38.837173 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-background-process-stop
166 20:46:38.837698 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-common-functions
167 20:46:38.838190 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-echo-ipv4
168 20:46:38.838670 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-install-packages
169 20:46:38.839147 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-installed-packages
170 20:46:38.839640 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-os-build
171 20:46:38.840182 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-probe-channel
172 20:46:38.840717 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-probe-ip
173 20:46:38.841190 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-target-ip
174 20:46:38.841663 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-target-mac
175 20:46:38.842129 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-target-storage
176 20:46:38.842611 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-case
177 20:46:38.843082 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-event
178 20:46:38.843568 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-feedback
179 20:46:38.844140 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-raise
180 20:46:38.844661 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-reference
181 20:46:38.845142 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-runner
182 20:46:38.845622 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-set
183 20:46:38.846155 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-test-shell
184 20:46:38.846647 Updating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-add-keys (debian)
185 20:46:38.847176 Updating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-add-sources (debian)
186 20:46:38.847696 Updating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-install-packages (debian)
187 20:46:38.848235 Updating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-installed-packages (debian)
188 20:46:38.848738 Updating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/bin/lava-os-build (debian)
189 20:46:38.849172 Creating /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/environment
190 20:46:38.849542 LAVA metadata
191 20:46:38.849798 - LAVA_JOB_ID=930521
192 20:46:38.850014 - LAVA_DISPATCHER_IP=192.168.6.2
193 20:46:38.850374 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 20:46:38.851334 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 20:46:38.851649 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 20:46:38.851859 skipped lava-vland-overlay
197 20:46:38.852135 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 20:46:38.852393 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 20:46:38.852610 skipped lava-multinode-overlay
200 20:46:38.852854 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 20:46:38.853103 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 20:46:38.853352 Loading test definitions
203 20:46:38.853632 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 20:46:38.853851 Using /lava-930521 at stage 0
205 20:46:38.854915 uuid=930521_1.6.2.4.1 testdef=None
206 20:46:38.855219 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 20:46:38.855479 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 20:46:38.857040 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 20:46:38.857825 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 20:46:38.859829 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 20:46:38.860681 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 20:46:38.862501 runner path: /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/0/tests/0_timesync-off test_uuid 930521_1.6.2.4.1
215 20:46:38.863046 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 20:46:38.863862 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 20:46:38.864172 Using /lava-930521 at stage 0
219 20:46:38.864530 Fetching tests from https://github.com/kernelci/test-definitions.git
220 20:46:38.864818 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/0/tests/1_kselftest-dt'
221 20:46:42.168830 Running '/usr/bin/git checkout kernelci.org
222 20:46:42.375410 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 20:46:42.377700 uuid=930521_1.6.2.4.5 testdef=None
224 20:46:42.378315 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 20:46:42.379765 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 20:46:42.385246 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 20:46:42.386815 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 20:46:42.393960 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 20:46:42.395609 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 20:46:42.402541 runner path: /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/0/tests/1_kselftest-dt test_uuid 930521_1.6.2.4.5
234 20:46:42.403062 BOARD='meson-g12b-a311d-libretech-cc'
235 20:46:42.403467 BRANCH='mainline'
236 20:46:42.403860 SKIPFILE='/dev/null'
237 20:46:42.404287 SKIP_INSTALL='True'
238 20:46:42.404678 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-366-g886b7e80ab198/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 20:46:42.405076 TST_CASENAME=''
240 20:46:42.405467 TST_CMDFILES='dt'
241 20:46:42.406432 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 20:46:42.407953 Creating lava-test-runner.conf files
244 20:46:42.408420 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/930521/lava-overlay-stch617y/lava-930521/0 for stage 0
245 20:46:42.409081 - 0_timesync-off
246 20:46:42.409531 - 1_kselftest-dt
247 20:46:42.410148 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 20:46:42.410681 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 20:47:05.728921 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 20:47:05.729367 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 20:47:05.729633 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 20:47:05.729905 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 20:47:05.730172 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 20:47:06.360291 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 20:47:06.360770 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 20:47:06.361024 extracting modules file /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930521/extract-nfsrootfs-pnzvseau
257 20:47:07.699138 extracting modules file /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/930521/extract-overlay-ramdisk-gzteud5b/ramdisk
258 20:47:09.081488 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 20:47:09.081970 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 20:47:09.082252 [common] Applying overlay to NFS
261 20:47:09.082468 [common] Applying overlay /var/lib/lava/dispatcher/tmp/930521/compress-overlay-e8_v6vy2/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/930521/extract-nfsrootfs-pnzvseau
262 20:47:11.808754 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 20:47:11.809237 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 20:47:11.809509 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 20:47:11.809744 Converting downloaded kernel to a uImage
266 20:47:11.810055 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/kernel/Image /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/kernel/uImage
267 20:47:12.329871 output: Image Name:
268 20:47:12.330299 output: Created: Sun Nov 3 20:47:11 2024
269 20:47:12.330510 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 20:47:12.330716 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 20:47:12.330918 output: Load Address: 01080000
272 20:47:12.331117 output: Entry Point: 01080000
273 20:47:12.331315 output:
274 20:47:12.331650 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 20:47:12.331921 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 20:47:12.332270 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 20:47:12.332535 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 20:47:12.332795 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 20:47:12.333052 Building ramdisk /var/lib/lava/dispatcher/tmp/930521/extract-overlay-ramdisk-gzteud5b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/930521/extract-overlay-ramdisk-gzteud5b/ramdisk
280 20:47:14.467323 >> 166824 blocks
281 20:47:22.182577 Adding RAMdisk u-boot header.
282 20:47:22.183036 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/930521/extract-overlay-ramdisk-gzteud5b/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/930521/extract-overlay-ramdisk-gzteud5b/ramdisk.cpio.gz.uboot
283 20:47:22.446596 output: Image Name:
284 20:47:22.447105 output: Created: Sun Nov 3 20:47:22 2024
285 20:47:22.447725 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 20:47:22.448364 output: Data Size: 23431309 Bytes = 22882.14 KiB = 22.35 MiB
287 20:47:22.448909 output: Load Address: 00000000
288 20:47:22.449431 output: Entry Point: 00000000
289 20:47:22.449949 output:
290 20:47:22.451029 rename /var/lib/lava/dispatcher/tmp/930521/extract-overlay-ramdisk-gzteud5b/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot
291 20:47:22.451942 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 20:47:22.452705 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 20:47:22.453420 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 20:47:22.454030 No LXC device requested
295 20:47:22.454710 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 20:47:22.455383 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 20:47:22.456065 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 20:47:22.456617 Checking files for TFTP limit of 4294967296 bytes.
299 20:47:22.460104 end: 1 tftp-deploy (duration 00:01:18) [common]
300 20:47:22.460839 start: 2 uboot-action (timeout 00:05:00) [common]
301 20:47:22.461539 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 20:47:22.462187 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 20:47:22.462854 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 20:47:22.463544 Using kernel file from prepare-kernel: 930521/tftp-deploy-wxotahsj/kernel/uImage
305 20:47:22.464453 substitutions:
306 20:47:22.465010 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 20:47:22.465547 - {DTB_ADDR}: 0x01070000
308 20:47:22.466065 - {DTB}: 930521/tftp-deploy-wxotahsj/dtb/meson-g12b-a311d-libretech-cc.dtb
309 20:47:22.466593 - {INITRD}: 930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot
310 20:47:22.467105 - {KERNEL_ADDR}: 0x01080000
311 20:47:22.467614 - {KERNEL}: 930521/tftp-deploy-wxotahsj/kernel/uImage
312 20:47:22.468154 - {LAVA_MAC}: None
313 20:47:22.468743 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/930521/extract-nfsrootfs-pnzvseau
314 20:47:22.469278 - {NFS_SERVER_IP}: 192.168.6.2
315 20:47:22.469800 - {PRESEED_CONFIG}: None
316 20:47:22.470317 - {PRESEED_LOCAL}: None
317 20:47:22.470855 - {RAMDISK_ADDR}: 0x08000000
318 20:47:22.471375 - {RAMDISK}: 930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot
319 20:47:22.471900 - {ROOT_PART}: None
320 20:47:22.472486 - {ROOT}: None
321 20:47:22.473001 - {SERVER_IP}: 192.168.6.2
322 20:47:22.473508 - {TEE_ADDR}: 0x83000000
323 20:47:22.474015 - {TEE}: None
324 20:47:22.474521 Parsed boot commands:
325 20:47:22.475017 - setenv autoload no
326 20:47:22.475520 - setenv initrd_high 0xffffffff
327 20:47:22.476083 - setenv fdt_high 0xffffffff
328 20:47:22.476600 - dhcp
329 20:47:22.477105 - setenv serverip 192.168.6.2
330 20:47:22.477624 - tftpboot 0x01080000 930521/tftp-deploy-wxotahsj/kernel/uImage
331 20:47:22.478135 - tftpboot 0x08000000 930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot
332 20:47:22.478641 - tftpboot 0x01070000 930521/tftp-deploy-wxotahsj/dtb/meson-g12b-a311d-libretech-cc.dtb
333 20:47:22.479149 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/930521/extract-nfsrootfs-pnzvseau,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 20:47:22.479668 - bootm 0x01080000 0x08000000 0x01070000
335 20:47:22.480355 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 20:47:22.482300 start: 2.3 connect-device (timeout 00:05:00) [common]
338 20:47:22.482852 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 20:47:22.499720 Setting prompt string to ['lava-test: # ']
340 20:47:22.501671 end: 2.3 connect-device (duration 00:00:00) [common]
341 20:47:22.502513 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 20:47:22.503257 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 20:47:22.503971 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 20:47:22.505509 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 20:47:22.544646 >> OK - accepted request
346 20:47:22.546766 Returned 0 in 0 seconds
347 20:47:22.648159 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 20:47:22.650243 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 20:47:22.650987 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 20:47:22.651637 Setting prompt string to ['Hit any key to stop autoboot']
352 20:47:22.652269 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 20:47:22.654223 Trying 192.168.56.21...
354 20:47:22.654849 Connected to conserv1.
355 20:47:22.655394 Escape character is '^]'.
356 20:47:22.655942
357 20:47:22.656529 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 20:47:22.657081
359 20:47:34.262930 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 20:47:34.263735 bl2_stage_init 0x01
361 20:47:34.264405 bl2_stage_init 0x81
362 20:47:34.268495 hw id: 0x0000 - pwm id 0x01
363 20:47:34.269164 bl2_stage_init 0xc1
364 20:47:34.269720 bl2_stage_init 0x02
365 20:47:34.270261
366 20:47:34.274033 L0:00000000
367 20:47:34.274701 L1:20000703
368 20:47:34.275263 L2:00008067
369 20:47:34.275814 L3:14000000
370 20:47:34.276840 B2:00402000
371 20:47:34.277455 B1:e0f83180
372 20:47:34.278010
373 20:47:34.278528 TE: 58124
374 20:47:34.279055
375 20:47:34.288023 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 20:47:34.288690
377 20:47:34.289210 Board ID = 1
378 20:47:34.289713 Set A53 clk to 24M
379 20:47:34.290457 Set A73 clk to 24M
380 20:47:34.293775 Set clk81 to 24M
381 20:47:34.294334 A53 clk: 1200 MHz
382 20:47:34.294841 A73 clk: 1200 MHz
383 20:47:34.297325 CLK81: 166.6M
384 20:47:34.297892 smccc: 00012a91
385 20:47:34.302665 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 20:47:34.308116 board id: 1
387 20:47:34.313429 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 20:47:34.324286 fw parse done
389 20:47:34.329278 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 20:47:34.371626 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 20:47:34.383712 PIEI prepare done
392 20:47:34.384406 fastboot data load
393 20:47:34.384937 fastboot data verify
394 20:47:34.389218 verify result: 266
395 20:47:34.394919 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 20:47:34.395406 LPDDR4 probe
397 20:47:34.395818 ddr clk to 1584MHz
398 20:47:34.402754 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 20:47:34.439902
400 20:47:34.440384 dmc_version 0001
401 20:47:34.445761 Check phy result
402 20:47:34.452530 INFO : End of CA training
403 20:47:34.453017 INFO : End of initialization
404 20:47:34.458130 INFO : Training has run successfully!
405 20:47:34.458570 Check phy result
406 20:47:34.463707 INFO : End of initialization
407 20:47:34.464158 INFO : End of read enable training
408 20:47:34.469357 INFO : End of fine write leveling
409 20:47:34.475005 INFO : End of Write leveling coarse delay
410 20:47:34.475433 INFO : Training has run successfully!
411 20:47:34.475830 Check phy result
412 20:47:34.480503 INFO : End of initialization
413 20:47:34.480927 INFO : End of read dq deskew training
414 20:47:34.486155 INFO : End of MPR read delay center optimization
415 20:47:34.491742 INFO : End of write delay center optimization
416 20:47:34.497300 INFO : End of read delay center optimization
417 20:47:34.497761 INFO : End of max read latency training
418 20:47:34.502987 INFO : Training has run successfully!
419 20:47:34.503423 1D training succeed
420 20:47:34.512215 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 20:47:34.559841 Check phy result
422 20:47:34.560404 INFO : End of initialization
423 20:47:34.581481 INFO : End of 2D read delay Voltage center optimization
424 20:47:34.600803 INFO : End of 2D read delay Voltage center optimization
425 20:47:34.653821 INFO : End of 2D write delay Voltage center optimization
426 20:47:34.703136 INFO : End of 2D write delay Voltage center optimization
427 20:47:34.708733 INFO : Training has run successfully!
428 20:47:34.709163
429 20:47:34.709564 channel==0
430 20:47:34.714273 RxClkDly_Margin_A0==88 ps 9
431 20:47:34.714704 TxDqDly_Margin_A0==98 ps 10
432 20:47:34.719873 RxClkDly_Margin_A1==88 ps 9
433 20:47:34.720356 TxDqDly_Margin_A1==98 ps 10
434 20:47:34.720752 TrainedVREFDQ_A0==74
435 20:47:34.725455 TrainedVREFDQ_A1==74
436 20:47:34.725884 VrefDac_Margin_A0==25
437 20:47:34.726278 DeviceVref_Margin_A0==40
438 20:47:34.731081 VrefDac_Margin_A1==25
439 20:47:34.731497 DeviceVref_Margin_A1==40
440 20:47:34.731885
441 20:47:34.732317
442 20:47:34.736706 channel==1
443 20:47:34.737135 RxClkDly_Margin_A0==98 ps 10
444 20:47:34.737526 TxDqDly_Margin_A0==98 ps 10
445 20:47:34.742275 RxClkDly_Margin_A1==98 ps 10
446 20:47:34.742732 TxDqDly_Margin_A1==88 ps 9
447 20:47:34.747892 TrainedVREFDQ_A0==77
448 20:47:34.748345 TrainedVREFDQ_A1==77
449 20:47:34.748740 VrefDac_Margin_A0==22
450 20:47:34.753483 DeviceVref_Margin_A0==37
451 20:47:34.753937 VrefDac_Margin_A1==22
452 20:47:34.759091 DeviceVref_Margin_A1==37
453 20:47:34.759539
454 20:47:34.759937 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 20:47:34.764633
456 20:47:34.792634 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 20:47:34.793177 2D training succeed
458 20:47:34.798278 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 20:47:34.803863 auto size-- 65535DDR cs0 size: 2048MB
460 20:47:34.804314 DDR cs1 size: 2048MB
461 20:47:34.809467 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 20:47:34.809884 cs0 DataBus test pass
463 20:47:34.815080 cs1 DataBus test pass
464 20:47:34.815495 cs0 AddrBus test pass
465 20:47:34.815886 cs1 AddrBus test pass
466 20:47:34.816316
467 20:47:34.820688 100bdlr_step_size ps== 420
468 20:47:34.821130 result report
469 20:47:34.826264 boot times 0Enable ddr reg access
470 20:47:34.831750 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 20:47:34.845191 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 20:47:35.419248 0.0;M3 CHK:0;cm4_sp_mode 0
473 20:47:35.419915 MVN_1=0x00000000
474 20:47:35.424583 MVN_2=0x00000000
475 20:47:35.430277 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 20:47:35.431248 OPS=0x10
477 20:47:35.431894 ring efuse init
478 20:47:35.432533 chipver efuse init
479 20:47:35.438478 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 20:47:35.439230 [0.018960 Inits done]
481 20:47:35.446032 secure task start!
482 20:47:35.446736 high task start!
483 20:47:35.447296 low task start!
484 20:47:35.447836 run into bl31
485 20:47:35.452674 NOTICE: BL31: v1.3(release):4fc40b1
486 20:47:35.460502 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 20:47:35.461272 NOTICE: BL31: G12A normal boot!
488 20:47:35.485877 NOTICE: BL31: BL33 decompress pass
489 20:47:35.491437 ERROR: Error initializing runtime service opteed_fast
490 20:47:36.724433
491 20:47:36.724919
492 20:47:36.732668 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 20:47:36.733178
494 20:47:36.733594 Model: Libre Computer AML-A311D-CC Alta
495 20:47:36.940781 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 20:47:36.964508 DRAM: 2 GiB (effective 3.8 GiB)
497 20:47:37.107507 Core: 408 devices, 31 uclasses, devicetree: separate
498 20:47:37.113303 WDT: Not starting watchdog@f0d0
499 20:47:37.145644 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 20:47:37.158086 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 20:47:37.163050 ** Bad device specification mmc 0 **
502 20:47:37.173397 Card did not respond to voltage select! : -110
503 20:47:37.181044 ** Bad device specification mmc 0 **
504 20:47:37.181405 Couldn't find partition mmc 0
505 20:47:37.189408 Card did not respond to voltage select! : -110
506 20:47:37.194898 ** Bad device specification mmc 0 **
507 20:47:37.195381 Couldn't find partition mmc 0
508 20:47:37.199959 Error: could not access storage.
509 20:47:38.462906 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 20:47:38.463425 bl2_stage_init 0x01
511 20:47:38.463714 bl2_stage_init 0x81
512 20:47:38.468448 hw id: 0x0000 - pwm id 0x01
513 20:47:38.468791 bl2_stage_init 0xc1
514 20:47:38.469066 bl2_stage_init 0x02
515 20:47:38.469322
516 20:47:38.474099 L0:00000000
517 20:47:38.474433 L1:20000703
518 20:47:38.474694 L2:00008067
519 20:47:38.474948 L3:14000000
520 20:47:38.479606 B2:00402000
521 20:47:38.480112 B1:e0f83180
522 20:47:38.480535
523 20:47:38.480944 TE: 58124
524 20:47:38.481350
525 20:47:38.485191 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 20:47:38.485701
527 20:47:38.485998 Board ID = 1
528 20:47:38.490783 Set A53 clk to 24M
529 20:47:38.491267 Set A73 clk to 24M
530 20:47:38.491569 Set clk81 to 24M
531 20:47:38.496442 A53 clk: 1200 MHz
532 20:47:38.496937 A73 clk: 1200 MHz
533 20:47:38.497357 CLK81: 166.6M
534 20:47:38.497647 smccc: 00012a91
535 20:47:38.502072 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 20:47:38.507615 board id: 1
537 20:47:38.513539 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 20:47:38.524143 fw parse done
539 20:47:38.530140 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 20:47:38.571803 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 20:47:38.583667 PIEI prepare done
542 20:47:38.584225 fastboot data load
543 20:47:38.584541 fastboot data verify
544 20:47:38.589372 verify result: 266
545 20:47:38.594916 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 20:47:38.595263 LPDDR4 probe
547 20:47:38.595528 ddr clk to 1584MHz
548 20:47:38.602904 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 20:47:38.640221
550 20:47:38.640801 dmc_version 0001
551 20:47:38.646817 Check phy result
552 20:47:38.652715 INFO : End of CA training
553 20:47:38.653051 INFO : End of initialization
554 20:47:38.658303 INFO : Training has run successfully!
555 20:47:38.658789 Check phy result
556 20:47:38.663951 INFO : End of initialization
557 20:47:38.664309 INFO : End of read enable training
558 20:47:38.667261 INFO : End of fine write leveling
559 20:47:38.672728 INFO : End of Write leveling coarse delay
560 20:47:38.678324 INFO : Training has run successfully!
561 20:47:38.678811 Check phy result
562 20:47:38.679105 INFO : End of initialization
563 20:47:38.683923 INFO : End of read dq deskew training
564 20:47:38.689558 INFO : End of MPR read delay center optimization
565 20:47:38.689892 INFO : End of write delay center optimization
566 20:47:38.695157 INFO : End of read delay center optimization
567 20:47:38.700725 INFO : End of max read latency training
568 20:47:38.701212 INFO : Training has run successfully!
569 20:47:38.706345 1D training succeed
570 20:47:38.712437 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 20:47:38.759952 Check phy result
572 20:47:38.760453 INFO : End of initialization
573 20:47:38.781788 INFO : End of 2D read delay Voltage center optimization
574 20:47:38.801726 INFO : End of 2D read delay Voltage center optimization
575 20:47:38.853514 INFO : End of 2D write delay Voltage center optimization
576 20:47:38.902729 INFO : End of 2D write delay Voltage center optimization
577 20:47:38.908287 INFO : Training has run successfully!
578 20:47:38.908731
579 20:47:38.909152 channel==0
580 20:47:38.913877 RxClkDly_Margin_A0==88 ps 9
581 20:47:38.914309 TxDqDly_Margin_A0==98 ps 10
582 20:47:38.917232 RxClkDly_Margin_A1==88 ps 9
583 20:47:38.917668 TxDqDly_Margin_A1==98 ps 10
584 20:47:38.922747 TrainedVREFDQ_A0==74
585 20:47:38.923181 TrainedVREFDQ_A1==74
586 20:47:38.928337 VrefDac_Margin_A0==25
587 20:47:38.928770 DeviceVref_Margin_A0==40
588 20:47:38.929175 VrefDac_Margin_A1==25
589 20:47:38.933948 DeviceVref_Margin_A1==40
590 20:47:38.934374
591 20:47:38.934787
592 20:47:38.935191 channel==1
593 20:47:38.935589 RxClkDly_Margin_A0==98 ps 10
594 20:47:38.939549 TxDqDly_Margin_A0==98 ps 10
595 20:47:38.940027 RxClkDly_Margin_A1==98 ps 10
596 20:47:38.945140 TxDqDly_Margin_A1==88 ps 9
597 20:47:38.945565 TrainedVREFDQ_A0==77
598 20:47:38.945970 TrainedVREFDQ_A1==77
599 20:47:38.950747 VrefDac_Margin_A0==22
600 20:47:38.951178 DeviceVref_Margin_A0==37
601 20:47:38.956327 VrefDac_Margin_A1==22
602 20:47:38.956756 DeviceVref_Margin_A1==37
603 20:47:38.957160
604 20:47:38.961940 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 20:47:38.962373
606 20:47:38.989917 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 20:47:38.995589 2D training succeed
608 20:47:39.001128 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 20:47:39.001566 auto size-- 65535DDR cs0 size: 2048MB
610 20:47:39.006736 DDR cs1 size: 2048MB
611 20:47:39.007159 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 20:47:39.012323 cs0 DataBus test pass
613 20:47:39.012762 cs1 DataBus test pass
614 20:47:39.013170 cs0 AddrBus test pass
615 20:47:39.017953 cs1 AddrBus test pass
616 20:47:39.018382
617 20:47:39.018788 100bdlr_step_size ps== 420
618 20:47:39.019199 result report
619 20:47:39.023570 boot times 0Enable ddr reg access
620 20:47:39.030961 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 20:47:39.043865 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 20:47:39.616908 0.0;M3 CHK:0;cm4_sp_mode 0
623 20:47:39.617485 MVN_1=0x00000000
624 20:47:39.622461 MVN_2=0x00000000
625 20:47:39.628182 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 20:47:39.628693 OPS=0x10
627 20:47:39.629151 ring efuse init
628 20:47:39.629555 chipver efuse init
629 20:47:39.636374 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 20:47:39.636850 [0.018961 Inits done]
631 20:47:39.644012 secure task start!
632 20:47:39.644458 high task start!
633 20:47:39.644876 low task start!
634 20:47:39.645267 run into bl31
635 20:47:39.650530 NOTICE: BL31: v1.3(release):4fc40b1
636 20:47:39.657677 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 20:47:39.658126 NOTICE: BL31: G12A normal boot!
638 20:47:39.683851 NOTICE: BL31: BL33 decompress pass
639 20:47:39.689206 ERROR: Error initializing runtime service opteed_fast
640 20:47:40.922380
641 20:47:40.922959
642 20:47:40.930770 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 20:47:40.931216
644 20:47:40.931629 Model: Libre Computer AML-A311D-CC Alta
645 20:47:41.138569 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 20:47:41.161648 DRAM: 2 GiB (effective 3.8 GiB)
647 20:47:41.305729 Core: 408 devices, 31 uclasses, devicetree: separate
648 20:47:41.310630 WDT: Not starting watchdog@f0d0
649 20:47:41.343661 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 20:47:41.356168 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 20:47:41.360360 ** Bad device specification mmc 0 **
652 20:47:41.371502 Card did not respond to voltage select! : -110
653 20:47:41.379215 ** Bad device specification mmc 0 **
654 20:47:41.379662 Couldn't find partition mmc 0
655 20:47:41.387409 Card did not respond to voltage select! : -110
656 20:47:41.392904 ** Bad device specification mmc 0 **
657 20:47:41.393404 Couldn't find partition mmc 0
658 20:47:41.397989 Error: could not access storage.
659 20:47:41.740500 Net: eth0: ethernet@ff3f0000
660 20:47:41.741039 starting USB...
661 20:47:41.992291 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 20:47:41.992841 Starting the controller
663 20:47:41.999304 USB XHCI 1.10
664 20:47:43.714707 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 20:47:43.715315 bl2_stage_init 0x01
666 20:47:43.715747 bl2_stage_init 0x81
667 20:47:43.720246 hw id: 0x0000 - pwm id 0x01
668 20:47:43.720698 bl2_stage_init 0xc1
669 20:47:43.721111 bl2_stage_init 0x02
670 20:47:43.721516
671 20:47:43.725901 L0:00000000
672 20:47:43.726334 L1:20000703
673 20:47:43.726740 L2:00008067
674 20:47:43.727135 L3:14000000
675 20:47:43.731497 B2:00402000
676 20:47:43.731932 B1:e0f83180
677 20:47:43.732374
678 20:47:43.732780 TE: 58159
679 20:47:43.733180
680 20:47:43.737022 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 20:47:43.737462
682 20:47:43.737872 Board ID = 1
683 20:47:43.742688 Set A53 clk to 24M
684 20:47:43.743125 Set A73 clk to 24M
685 20:47:43.743526 Set clk81 to 24M
686 20:47:43.748257 A53 clk: 1200 MHz
687 20:47:43.748689 A73 clk: 1200 MHz
688 20:47:43.749094 CLK81: 166.6M
689 20:47:43.749494 smccc: 00012ab5
690 20:47:43.753866 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 20:47:43.759474 board id: 1
692 20:47:43.765417 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 20:47:43.775920 fw parse done
694 20:47:43.781878 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 20:47:43.824532 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 20:47:43.835417 PIEI prepare done
697 20:47:43.835859 fastboot data load
698 20:47:43.836336 fastboot data verify
699 20:47:43.841062 verify result: 266
700 20:47:43.846682 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 20:47:43.847119 LPDDR4 probe
702 20:47:43.847525 ddr clk to 1584MHz
703 20:47:43.854645 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 20:47:43.892076
705 20:47:43.892527 dmc_version 0001
706 20:47:43.898656 Check phy result
707 20:47:43.904485 INFO : End of CA training
708 20:47:43.904917 INFO : End of initialization
709 20:47:43.910044 INFO : Training has run successfully!
710 20:47:43.910477 Check phy result
711 20:47:43.915639 INFO : End of initialization
712 20:47:43.916102 INFO : End of read enable training
713 20:47:43.921246 INFO : End of fine write leveling
714 20:47:43.926888 INFO : End of Write leveling coarse delay
715 20:47:43.927319 INFO : Training has run successfully!
716 20:47:43.927726 Check phy result
717 20:47:43.932542 INFO : End of initialization
718 20:47:43.932979 INFO : End of read dq deskew training
719 20:47:43.938161 INFO : End of MPR read delay center optimization
720 20:47:43.943724 INFO : End of write delay center optimization
721 20:47:43.949290 INFO : End of read delay center optimization
722 20:47:43.949717 INFO : End of max read latency training
723 20:47:43.954873 INFO : Training has run successfully!
724 20:47:43.955303 1D training succeed
725 20:47:43.964186 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 20:47:44.011669 Check phy result
727 20:47:44.012146 INFO : End of initialization
728 20:47:44.033459 INFO : End of 2D read delay Voltage center optimization
729 20:47:44.053603 INFO : End of 2D read delay Voltage center optimization
730 20:47:44.105728 INFO : End of 2D write delay Voltage center optimization
731 20:47:44.155055 INFO : End of 2D write delay Voltage center optimization
732 20:47:44.160652 INFO : Training has run successfully!
733 20:47:44.161085
734 20:47:44.161494 channel==0
735 20:47:44.166312 RxClkDly_Margin_A0==88 ps 9
736 20:47:44.166744 TxDqDly_Margin_A0==98 ps 10
737 20:47:44.171818 RxClkDly_Margin_A1==88 ps 9
738 20:47:44.172297 TxDqDly_Margin_A1==98 ps 10
739 20:47:44.172709 TrainedVREFDQ_A0==74
740 20:47:44.177441 TrainedVREFDQ_A1==74
741 20:47:44.177877 VrefDac_Margin_A0==25
742 20:47:44.178280 DeviceVref_Margin_A0==40
743 20:47:44.182951 VrefDac_Margin_A1==26
744 20:47:44.183381 DeviceVref_Margin_A1==40
745 20:47:44.183786
746 20:47:44.184226
747 20:47:44.188555 channel==1
748 20:47:44.188985 RxClkDly_Margin_A0==98 ps 10
749 20:47:44.189384 TxDqDly_Margin_A0==98 ps 10
750 20:47:44.194316 RxClkDly_Margin_A1==98 ps 10
751 20:47:44.194749 TxDqDly_Margin_A1==88 ps 9
752 20:47:44.199880 TrainedVREFDQ_A0==77
753 20:47:44.200345 TrainedVREFDQ_A1==77
754 20:47:44.200754 VrefDac_Margin_A0==22
755 20:47:44.205455 DeviceVref_Margin_A0==37
756 20:47:44.205882 VrefDac_Margin_A1==22
757 20:47:44.211019 DeviceVref_Margin_A1==37
758 20:47:44.211451
759 20:47:44.211861 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 20:47:44.216572
761 20:47:44.244576 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 20:47:44.245044 2D training succeed
763 20:47:44.250276 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 20:47:44.255782 auto size-- 65535DDR cs0 size: 2048MB
765 20:47:44.256242 DDR cs1 size: 2048MB
766 20:47:44.261388 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 20:47:44.261817 cs0 DataBus test pass
768 20:47:44.266984 cs1 DataBus test pass
769 20:47:44.267409 cs0 AddrBus test pass
770 20:47:44.267813 cs1 AddrBus test pass
771 20:47:44.268244
772 20:47:44.272573 100bdlr_step_size ps== 420
773 20:47:44.273015 result report
774 20:47:44.278280 boot times 0Enable ddr reg access
775 20:47:44.283643 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 20:47:44.297123 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 20:47:44.870732 0.0;M3 CHK:0;cm4_sp_mode 0
778 20:47:44.871332 MVN_1=0x00000000
779 20:47:44.876154 MVN_2=0x00000000
780 20:47:44.881947 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 20:47:44.882460 OPS=0x10
782 20:47:44.882861 ring efuse init
783 20:47:44.883247 chipver efuse init
784 20:47:44.887487 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 20:47:44.893080 [0.018960 Inits done]
786 20:47:44.893511 secure task start!
787 20:47:44.893900 high task start!
788 20:47:44.897676 low task start!
789 20:47:44.898092 run into bl31
790 20:47:44.904285 NOTICE: BL31: v1.3(release):4fc40b1
791 20:47:44.912147 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 20:47:44.912577 NOTICE: BL31: G12A normal boot!
793 20:47:44.937460 NOTICE: BL31: BL33 decompress pass
794 20:47:44.943131 ERROR: Error initializing runtime service opteed_fast
795 20:47:46.176104
796 20:47:46.176721
797 20:47:46.184386 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 20:47:46.184830
799 20:47:46.185241 Model: Libre Computer AML-A311D-CC Alta
800 20:47:46.391904 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 20:47:46.415284 DRAM: 2 GiB (effective 3.8 GiB)
802 20:47:46.559450 Core: 408 devices, 31 uclasses, devicetree: separate
803 20:47:46.564187 WDT: Not starting watchdog@f0d0
804 20:47:46.597437 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 20:47:46.609813 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 20:47:46.613830 ** Bad device specification mmc 0 **
807 20:47:46.625151 Card did not respond to voltage select! : -110
808 20:47:46.631849 ** Bad device specification mmc 0 **
809 20:47:46.632325 Couldn't find partition mmc 0
810 20:47:46.641090 Card did not respond to voltage select! : -110
811 20:47:46.646718 ** Bad device specification mmc 0 **
812 20:47:46.647158 Couldn't find partition mmc 0
813 20:47:46.650766 Error: could not access storage.
814 20:47:46.993350 Net: eth0: ethernet@ff3f0000
815 20:47:46.993892 starting USB...
816 20:47:47.245863 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 20:47:47.246312 Starting the controller
818 20:47:47.252091 USB XHCI 1.10
819 20:47:49.413406 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 20:47:49.413995 bl2_stage_init 0x01
821 20:47:49.414420 bl2_stage_init 0x81
822 20:47:49.418835 hw id: 0x0000 - pwm id 0x01
823 20:47:49.419301 bl2_stage_init 0xc1
824 20:47:49.419717 bl2_stage_init 0x02
825 20:47:49.420167
826 20:47:49.424537 L0:00000000
827 20:47:49.424993 L1:20000703
828 20:47:49.425401 L2:00008067
829 20:47:49.425802 L3:14000000
830 20:47:49.430106 B2:00402000
831 20:47:49.430570 B1:e0f83180
832 20:47:49.430987
833 20:47:49.431408 TE: 58124
834 20:47:49.431823
835 20:47:49.435732 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 20:47:49.436230
837 20:47:49.436662 Board ID = 1
838 20:47:49.441294 Set A53 clk to 24M
839 20:47:49.441751 Set A73 clk to 24M
840 20:47:49.442157 Set clk81 to 24M
841 20:47:49.446875 A53 clk: 1200 MHz
842 20:47:49.447326 A73 clk: 1200 MHz
843 20:47:49.447736 CLK81: 166.6M
844 20:47:49.448206 smccc: 00012a92
845 20:47:49.452430 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 20:47:49.458053 board id: 1
847 20:47:49.463943 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 20:47:49.474626 fw parse done
849 20:47:49.479566 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 20:47:49.523221 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 20:47:49.534065 PIEI prepare done
852 20:47:49.534534 fastboot data load
853 20:47:49.534970 fastboot data verify
854 20:47:49.539733 verify result: 266
855 20:47:49.545338 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 20:47:49.545809 LPDDR4 probe
857 20:47:49.546238 ddr clk to 1584MHz
858 20:47:49.553349 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 20:47:49.589715
860 20:47:49.590209 dmc_version 0001
861 20:47:49.597271 Check phy result
862 20:47:49.603115 INFO : End of CA training
863 20:47:49.603579 INFO : End of initialization
864 20:47:49.608756 INFO : Training has run successfully!
865 20:47:49.609207 Check phy result
866 20:47:49.614331 INFO : End of initialization
867 20:47:49.614797 INFO : End of read enable training
868 20:47:49.619883 INFO : End of fine write leveling
869 20:47:49.625519 INFO : End of Write leveling coarse delay
870 20:47:49.625993 INFO : Training has run successfully!
871 20:47:49.626419 Check phy result
872 20:47:49.631080 INFO : End of initialization
873 20:47:49.631513 INFO : End of read dq deskew training
874 20:47:49.636697 INFO : End of MPR read delay center optimization
875 20:47:49.642268 INFO : End of write delay center optimization
876 20:47:49.647900 INFO : End of read delay center optimization
877 20:47:49.648389 INFO : End of max read latency training
878 20:47:49.653502 INFO : Training has run successfully!
879 20:47:49.653933 1D training succeed
880 20:47:49.662686 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 20:47:49.710264 Check phy result
882 20:47:49.710703 INFO : End of initialization
883 20:47:49.732742 INFO : End of 2D read delay Voltage center optimization
884 20:47:49.752872 INFO : End of 2D read delay Voltage center optimization
885 20:47:49.804796 INFO : End of 2D write delay Voltage center optimization
886 20:47:49.854152 INFO : End of 2D write delay Voltage center optimization
887 20:47:49.859832 INFO : Training has run successfully!
888 20:47:49.860310
889 20:47:49.860725 channel==0
890 20:47:49.865227 RxClkDly_Margin_A0==88 ps 9
891 20:47:49.865658 TxDqDly_Margin_A0==98 ps 10
892 20:47:49.870857 RxClkDly_Margin_A1==88 ps 9
893 20:47:49.871282 TxDqDly_Margin_A1==98 ps 10
894 20:47:49.871688 TrainedVREFDQ_A0==74
895 20:47:49.876467 TrainedVREFDQ_A1==74
896 20:47:49.876931 VrefDac_Margin_A0==24
897 20:47:49.877338 DeviceVref_Margin_A0==40
898 20:47:49.882006 VrefDac_Margin_A1==25
899 20:47:49.882460 DeviceVref_Margin_A1==40
900 20:47:49.882847
901 20:47:49.883234
902 20:47:49.887604 channel==1
903 20:47:49.888059 RxClkDly_Margin_A0==98 ps 10
904 20:47:49.888453 TxDqDly_Margin_A0==88 ps 9
905 20:47:49.893228 RxClkDly_Margin_A1==98 ps 10
906 20:47:49.893641 TxDqDly_Margin_A1==88 ps 9
907 20:47:49.898828 TrainedVREFDQ_A0==76
908 20:47:49.899268 TrainedVREFDQ_A1==77
909 20:47:49.899658 VrefDac_Margin_A0==22
910 20:47:49.904442 DeviceVref_Margin_A0==38
911 20:47:49.904854 VrefDac_Margin_A1==24
912 20:47:49.909942 DeviceVref_Margin_A1==37
913 20:47:49.910354
914 20:47:49.910744 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 20:47:49.911130
916 20:47:49.943586 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 20:47:49.944074 2D training succeed
918 20:47:49.949516 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 20:47:49.954754 auto size-- 65535DDR cs0 size: 2048MB
920 20:47:49.955185 DDR cs1 size: 2048MB
921 20:47:49.960294 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 20:47:49.960715 cs0 DataBus test pass
923 20:47:49.965872 cs1 DataBus test pass
924 20:47:49.966289 cs0 AddrBus test pass
925 20:47:49.966674 cs1 AddrBus test pass
926 20:47:49.967054
927 20:47:49.971477 100bdlr_step_size ps== 420
928 20:47:49.971905 result report
929 20:47:49.977108 boot times 0Enable ddr reg access
930 20:47:49.982441 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 20:47:49.995953 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 20:47:50.568027 0.0;M3 CHK:0;cm4_sp_mode 0
933 20:47:50.568602 MVN_1=0x00000000
934 20:47:50.573435 MVN_2=0x00000000
935 20:47:50.579210 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 20:47:50.579641 OPS=0x10
937 20:47:50.580081 ring efuse init
938 20:47:50.580484 chipver efuse init
939 20:47:50.584759 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 20:47:50.590350 [0.018961 Inits done]
941 20:47:50.590777 secure task start!
942 20:47:50.591181 high task start!
943 20:47:50.594059 low task start!
944 20:47:50.594486 run into bl31
945 20:47:50.601591 NOTICE: BL31: v1.3(release):4fc40b1
946 20:47:50.608472 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 20:47:50.608907 NOTICE: BL31: G12A normal boot!
948 20:47:50.634874 NOTICE: BL31: BL33 decompress pass
949 20:47:50.640514 ERROR: Error initializing runtime service opteed_fast
950 20:47:51.873437
951 20:47:51.874020
952 20:47:51.880861 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 20:47:51.881310
954 20:47:51.881737 Model: Libre Computer AML-A311D-CC Alta
955 20:47:52.090136 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 20:47:52.113596 DRAM: 2 GiB (effective 3.8 GiB)
957 20:47:52.256600 Core: 408 devices, 31 uclasses, devicetree: separate
958 20:47:52.261414 WDT: Not starting watchdog@f0d0
959 20:47:52.294682 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 20:47:52.307279 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 20:47:52.312075 ** Bad device specification mmc 0 **
962 20:47:52.322422 Card did not respond to voltage select! : -110
963 20:47:52.330070 ** Bad device specification mmc 0 **
964 20:47:52.330506 Couldn't find partition mmc 0
965 20:47:52.338381 Card did not respond to voltage select! : -110
966 20:47:52.343882 ** Bad device specification mmc 0 **
967 20:47:52.344350 Couldn't find partition mmc 0
968 20:47:52.348102 Error: could not access storage.
969 20:47:52.691480 Net: eth0: ethernet@ff3f0000
970 20:47:52.692053 starting USB...
971 20:47:52.943558 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 20:47:52.944149 Starting the controller
973 20:47:52.950241 USB XHCI 1.10
974 20:47:54.715004 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
975 20:47:54.715589 bl2_stage_init 0x81
976 20:47:54.720568 hw id: 0x0000 - pwm id 0x01
977 20:47:54.721001 bl2_stage_init 0xc1
978 20:47:54.721407 bl2_stage_init 0x02
979 20:47:54.721807
980 20:47:54.726119 L0:00000000
981 20:47:54.726541 L1:20000703
982 20:47:54.726940 L2:00008067
983 20:47:54.727337 L3:14000000
984 20:47:54.727728 B2:00402000
985 20:47:54.731721 B1:e0f83180
986 20:47:54.732192
987 20:47:54.732609 TE: 58150
988 20:47:54.733012
989 20:47:54.737359 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 20:47:54.737791
991 20:47:54.738192 Board ID = 1
992 20:47:54.742937 Set A53 clk to 24M
993 20:47:54.743364 Set A73 clk to 24M
994 20:47:54.743763 Set clk81 to 24M
995 20:47:54.748571 A53 clk: 1200 MHz
996 20:47:54.748994 A73 clk: 1200 MHz
997 20:47:54.749391 CLK81: 166.6M
998 20:47:54.749782 smccc: 00012aab
999 20:47:54.754142 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 20:47:54.759744 board id: 1
1001 20:47:54.765642 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 20:47:54.776194 fw parse done
1003 20:47:54.782159 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 20:47:54.824796 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 20:47:54.835657 PIEI prepare done
1006 20:47:54.836132 fastboot data load
1007 20:47:54.836543 fastboot data verify
1008 20:47:54.841458 verify result: 266
1009 20:47:54.846946 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 20:47:54.847372 LPDDR4 probe
1011 20:47:54.847773 ddr clk to 1584MHz
1012 20:47:54.854011 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 20:47:54.891220
1014 20:47:54.891663 dmc_version 0001
1015 20:47:54.897888 Check phy result
1016 20:47:54.904730 INFO : End of CA training
1017 20:47:54.905174 INFO : End of initialization
1018 20:47:54.910330 INFO : Training has run successfully!
1019 20:47:54.910743 Check phy result
1020 20:47:54.915927 INFO : End of initialization
1021 20:47:54.916377 INFO : End of read enable training
1022 20:47:54.919208 INFO : End of fine write leveling
1023 20:47:54.924749 INFO : End of Write leveling coarse delay
1024 20:47:54.930446 INFO : Training has run successfully!
1025 20:47:54.930857 Check phy result
1026 20:47:54.931244 INFO : End of initialization
1027 20:47:54.935956 INFO : End of read dq deskew training
1028 20:47:54.939332 INFO : End of MPR read delay center optimization
1029 20:47:54.944915 INFO : End of write delay center optimization
1030 20:47:54.950795 INFO : End of read delay center optimization
1031 20:47:54.951208 INFO : End of max read latency training
1032 20:47:54.956355 INFO : Training has run successfully!
1033 20:47:54.956764 1D training succeed
1034 20:47:54.963620 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 20:47:55.012061 Check phy result
1036 20:47:55.012475 INFO : End of initialization
1037 20:47:55.033933 INFO : End of 2D read delay Voltage center optimization
1038 20:47:55.054007 INFO : End of 2D read delay Voltage center optimization
1039 20:47:55.105988 INFO : End of 2D write delay Voltage center optimization
1040 20:47:55.155351 INFO : End of 2D write delay Voltage center optimization
1041 20:47:55.160933 INFO : Training has run successfully!
1042 20:47:55.161371
1043 20:47:55.161779 channel==0
1044 20:47:55.166659 RxClkDly_Margin_A0==88 ps 9
1045 20:47:55.167088 TxDqDly_Margin_A0==98 ps 10
1046 20:47:55.172259 RxClkDly_Margin_A1==88 ps 9
1047 20:47:55.172682 TxDqDly_Margin_A1==98 ps 10
1048 20:47:55.173089 TrainedVREFDQ_A0==74
1049 20:47:55.177783 TrainedVREFDQ_A1==74
1050 20:47:55.178221 VrefDac_Margin_A0==25
1051 20:47:55.178624 DeviceVref_Margin_A0==40
1052 20:47:55.183367 VrefDac_Margin_A1==25
1053 20:47:55.183791 DeviceVref_Margin_A1==40
1054 20:47:55.184233
1055 20:47:55.184634
1056 20:47:55.188918 channel==1
1057 20:47:55.189344 RxClkDly_Margin_A0==98 ps 10
1058 20:47:55.189746 TxDqDly_Margin_A0==98 ps 10
1059 20:47:55.194511 RxClkDly_Margin_A1==98 ps 10
1060 20:47:55.194930 TxDqDly_Margin_A1==98 ps 10
1061 20:47:55.200063 TrainedVREFDQ_A0==77
1062 20:47:55.200493 TrainedVREFDQ_A1==78
1063 20:47:55.200896 VrefDac_Margin_A0==22
1064 20:47:55.205790 DeviceVref_Margin_A0==37
1065 20:47:55.206208 VrefDac_Margin_A1==22
1066 20:47:55.211315 DeviceVref_Margin_A1==36
1067 20:47:55.211739
1068 20:47:55.212175 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 20:47:55.216943
1070 20:47:55.244924 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1071 20:47:55.245372 2D training succeed
1072 20:47:55.250552 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 20:47:55.256065 auto size-- 65535DDR cs0 size: 2048MB
1074 20:47:55.256493 DDR cs1 size: 2048MB
1075 20:47:55.261711 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 20:47:55.262133 cs0 DataBus test pass
1077 20:47:55.267225 cs1 DataBus test pass
1078 20:47:55.267643 cs0 AddrBus test pass
1079 20:47:55.268075 cs1 AddrBus test pass
1080 20:47:55.268476
1081 20:47:55.272852 100bdlr_step_size ps== 420
1082 20:47:55.273286 result report
1083 20:47:55.278467 boot times 0Enable ddr reg access
1084 20:47:55.283962 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 20:47:55.297453 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 20:47:55.871047 0.0;M3 CHK:0;cm4_sp_mode 0
1087 20:47:55.871545 MVN_1=0x00000000
1088 20:47:55.876740 MVN_2=0x00000000
1089 20:47:55.882364 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 20:47:55.882795 OPS=0x10
1091 20:47:55.883199 ring efuse init
1092 20:47:55.883596 chipver efuse init
1093 20:47:55.888011 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 20:47:55.893564 [0.018961 Inits done]
1095 20:47:55.893991 secure task start!
1096 20:47:55.894395 high task start!
1097 20:47:55.897203 low task start!
1098 20:47:55.897622 run into bl31
1099 20:47:55.904813 NOTICE: BL31: v1.3(release):4fc40b1
1100 20:47:55.911613 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 20:47:55.912077 NOTICE: BL31: G12A normal boot!
1102 20:47:55.937924 NOTICE: BL31: BL33 decompress pass
1103 20:47:55.943626 ERROR: Error initializing runtime service opteed_fast
1104 20:47:57.176457
1105 20:47:57.177030
1106 20:47:57.185017 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 20:47:57.185457
1108 20:47:57.185862 Model: Libre Computer AML-A311D-CC Alta
1109 20:47:57.393271 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 20:47:57.416655 DRAM: 2 GiB (effective 3.8 GiB)
1111 20:47:57.559666 Core: 408 devices, 31 uclasses, devicetree: separate
1112 20:47:57.565546 WDT: Not starting watchdog@f0d0
1113 20:47:57.597797 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 20:47:57.610270 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 20:47:57.615240 ** Bad device specification mmc 0 **
1116 20:47:57.625613 Card did not respond to voltage select! : -110
1117 20:47:57.632301 ** Bad device specification mmc 0 **
1118 20:47:57.632737 Couldn't find partition mmc 0
1119 20:47:57.641561 Card did not respond to voltage select! : -110
1120 20:47:57.647103 ** Bad device specification mmc 0 **
1121 20:47:57.647532 Couldn't find partition mmc 0
1122 20:47:57.652139 Error: could not access storage.
1123 20:47:57.994566 Net: eth0: ethernet@ff3f0000
1124 20:47:57.995070 starting USB...
1125 20:47:58.246345 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 20:47:58.246806 Starting the controller
1127 20:47:58.253388 USB XHCI 1.10
1128 20:47:59.807328 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 20:47:59.814666 scanning usb for storage devices... 0 Storage Device(s) found
1131 20:47:59.866272 Hit any key to stop autoboot: 1
1132 20:47:59.867013 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 20:47:59.867587 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 20:47:59.868098 Setting prompt string to ['=>']
1135 20:47:59.868578 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 20:47:59.873161 0
1137 20:47:59.874001 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 20:47:59.874486 Sending with 10 millisecond of delay
1140 20:48:01.008918 => setenv autoload no
1141 20:48:01.019632 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1142 20:48:01.024481 setenv autoload no
1143 20:48:01.025189 Sending with 10 millisecond of delay
1145 20:48:02.821787 => setenv initrd_high 0xffffffff
1146 20:48:02.832543 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 20:48:02.833363 setenv initrd_high 0xffffffff
1148 20:48:02.834058 Sending with 10 millisecond of delay
1150 20:48:04.450281 => setenv fdt_high 0xffffffff
1151 20:48:04.461006 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 20:48:04.461782 setenv fdt_high 0xffffffff
1153 20:48:04.462496 Sending with 10 millisecond of delay
1155 20:48:04.754265 => dhcp
1156 20:48:04.764916 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 20:48:04.765663 dhcp
1158 20:48:04.766091 Speed: 1000, full duplex
1159 20:48:04.766500 BOOTP broadcast 1
1160 20:48:04.775745 DHCP client bound to address 192.168.6.27 (11 ms)
1161 20:48:04.776472 Sending with 10 millisecond of delay
1163 20:48:06.452771 => setenv serverip 192.168.6.2
1164 20:48:06.463508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 20:48:06.464394 setenv serverip 192.168.6.2
1166 20:48:06.465078 Sending with 10 millisecond of delay
1168 20:48:10.188092 => tftpboot 0x01080000 930521/tftp-deploy-wxotahsj/kernel/uImage
1169 20:48:10.198878 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 20:48:10.199710 tftpboot 0x01080000 930521/tftp-deploy-wxotahsj/kernel/uImage
1171 20:48:10.200213 Speed: 1000, full duplex
1172 20:48:10.200634 Using ethernet@ff3f0000 device
1173 20:48:10.201621 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 20:48:10.207176 Filename '930521/tftp-deploy-wxotahsj/kernel/uImage'.
1175 20:48:10.210874 Load address: 0x1080000
1176 20:48:12.974531 Loading: *################################################## 43.6 MiB
1177 20:48:12.975137 15.8 MiB/s
1178 20:48:12.975566 done
1179 20:48:12.978749 Bytes transferred = 45713984 (2b98a40 hex)
1180 20:48:12.979530 Sending with 10 millisecond of delay
1182 20:48:17.665199 => tftpboot 0x08000000 930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot
1183 20:48:17.676011 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 20:48:17.676798 tftpboot 0x08000000 930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot
1185 20:48:17.677240 Speed: 1000, full duplex
1186 20:48:17.677656 Using ethernet@ff3f0000 device
1187 20:48:17.678908 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 20:48:17.687393 Filename '930521/tftp-deploy-wxotahsj/ramdisk/ramdisk.cpio.gz.uboot'.
1189 20:48:17.687837 Load address: 0x8000000
1190 20:48:24.534793 Loading: *######################T ########################### UDP wrong checksum 00000005 00008581
1191 20:48:29.534533 T UDP wrong checksum 00000005 00008581
1192 20:48:39.538718 T T UDP wrong checksum 00000005 00008581
1193 20:48:59.542548 T T T T UDP wrong checksum 00000005 00008581
1194 20:49:14.546736 T T
1195 20:49:14.547369 Retry count exceeded; starting again
1197 20:49:14.548849 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1200 20:49:14.550746 end: 2.4 uboot-commands (duration 00:01:52) [common]
1202 20:49:14.552178 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1204 20:49:14.553205 end: 2 uboot-action (duration 00:01:52) [common]
1206 20:49:14.554725 Cleaning after the job
1207 20:49:14.555260 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/ramdisk
1208 20:49:14.556414 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/kernel
1209 20:49:14.600537 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/dtb
1210 20:49:14.601319 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/nfsrootfs
1211 20:49:14.638321 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/930521/tftp-deploy-wxotahsj/modules
1212 20:49:14.645159 start: 4.1 power-off (timeout 00:00:30) [common]
1213 20:49:14.645749 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1214 20:49:14.681054 >> OK - accepted request
1215 20:49:14.682839 Returned 0 in 0 seconds
1216 20:49:14.783542 end: 4.1 power-off (duration 00:00:00) [common]
1218 20:49:14.784491 start: 4.2 read-feedback (timeout 00:10:00) [common]
1219 20:49:14.785136 Listened to connection for namespace 'common' for up to 1s
1220 20:49:15.785110 Finalising connection for namespace 'common'
1221 20:49:15.785807 Disconnecting from shell: Finalise
1222 20:49:15.786373 =>
1223 20:49:15.887338 end: 4.2 read-feedback (duration 00:00:01) [common]
1224 20:49:15.887912 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/930521
1225 20:49:18.816791 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/930521
1226 20:49:18.817418 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.