Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 26
- Errors: 0
- Boot result: PASS
- Kernel Errors: 66
1 00:17:08.335696 lava-dispatcher, installed at version: 2024.01
2 00:17:08.336477 start: 0 validate
3 00:17:08.336956 Start time: 2024-11-04 00:17:08.336926+00:00 (UTC)
4 00:17:08.337472 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:17:08.338009 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:17:08.373045 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:17:08.373577 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 00:17:08.401976 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:17:08.402581 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:17:09.452273 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:17:09.452768 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:17:09.484702 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:17:09.485220 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:17:09.529921 validate duration: 1.19
16 00:17:09.531620 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:17:09.532319 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:17:09.532956 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:17:09.534017 Not decompressing ramdisk as can be used compressed.
20 00:17:09.534752 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:17:09.535291 saving as /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/ramdisk/initrd.cpio.gz
22 00:17:09.535851 total size: 4775763 (4 MB)
23 00:17:09.576601 progress 0 % (0 MB)
24 00:17:09.584263 progress 5 % (0 MB)
25 00:17:09.591180 progress 10 % (0 MB)
26 00:17:09.598057 progress 15 % (0 MB)
27 00:17:09.605713 progress 20 % (0 MB)
28 00:17:09.612213 progress 25 % (1 MB)
29 00:17:09.617259 progress 30 % (1 MB)
30 00:17:09.620813 progress 35 % (1 MB)
31 00:17:09.623918 progress 40 % (1 MB)
32 00:17:09.627102 progress 45 % (2 MB)
33 00:17:09.630275 progress 50 % (2 MB)
34 00:17:09.633827 progress 55 % (2 MB)
35 00:17:09.636963 progress 60 % (2 MB)
36 00:17:09.640065 progress 65 % (2 MB)
37 00:17:09.643621 progress 70 % (3 MB)
38 00:17:09.646741 progress 75 % (3 MB)
39 00:17:09.649840 progress 80 % (3 MB)
40 00:17:09.653089 progress 85 % (3 MB)
41 00:17:09.656610 progress 90 % (4 MB)
42 00:17:09.659507 progress 95 % (4 MB)
43 00:17:09.662393 progress 100 % (4 MB)
44 00:17:09.663041 4 MB downloaded in 0.13 s (35.81 MB/s)
45 00:17:09.663568 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:17:09.664484 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:17:09.664777 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:17:09.665046 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:17:09.665521 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 00:17:09.665769 saving as /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/kernel/zImage
52 00:17:09.665977 total size: 12050944 (11 MB)
53 00:17:09.666188 No compression specified
54 00:17:09.701670 progress 0 % (0 MB)
55 00:17:09.709952 progress 5 % (0 MB)
56 00:17:09.717711 progress 10 % (1 MB)
57 00:17:09.725911 progress 15 % (1 MB)
58 00:17:09.733824 progress 20 % (2 MB)
59 00:17:09.741521 progress 25 % (2 MB)
60 00:17:09.749749 progress 30 % (3 MB)
61 00:17:09.757542 progress 35 % (4 MB)
62 00:17:09.766163 progress 40 % (4 MB)
63 00:17:09.773944 progress 45 % (5 MB)
64 00:17:09.781784 progress 50 % (5 MB)
65 00:17:09.789982 progress 55 % (6 MB)
66 00:17:09.797854 progress 60 % (6 MB)
67 00:17:09.806167 progress 65 % (7 MB)
68 00:17:09.813971 progress 70 % (8 MB)
69 00:17:09.821672 progress 75 % (8 MB)
70 00:17:09.829873 progress 80 % (9 MB)
71 00:17:09.837755 progress 85 % (9 MB)
72 00:17:09.845542 progress 90 % (10 MB)
73 00:17:09.853661 progress 95 % (10 MB)
74 00:17:09.860905 progress 100 % (11 MB)
75 00:17:09.861609 11 MB downloaded in 0.20 s (58.75 MB/s)
76 00:17:09.862088 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:17:09.862895 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:17:09.863169 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:17:09.863431 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:17:09.863892 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 00:17:09.864203 saving as /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/dtb/am335x-boneblack.dtb
83 00:17:09.864411 total size: 70568 (0 MB)
84 00:17:09.864620 No compression specified
85 00:17:09.899720 progress 46 % (0 MB)
86 00:17:09.900625 progress 92 % (0 MB)
87 00:17:09.901324 progress 100 % (0 MB)
88 00:17:09.901743 0 MB downloaded in 0.04 s (1.80 MB/s)
89 00:17:09.902230 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:17:09.903255 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:17:09.903557 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:17:09.903839 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:17:09.904377 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:17:09.904650 saving as /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/nfsrootfs/full.rootfs.tar
96 00:17:09.904869 total size: 117747780 (112 MB)
97 00:17:09.905094 Using unxz to decompress xz
98 00:17:09.944252 progress 0 % (0 MB)
99 00:17:10.686705 progress 5 % (5 MB)
100 00:17:11.437348 progress 10 % (11 MB)
101 00:17:12.210044 progress 15 % (16 MB)
102 00:17:12.927828 progress 20 % (22 MB)
103 00:17:13.505813 progress 25 % (28 MB)
104 00:17:14.308840 progress 30 % (33 MB)
105 00:17:15.107634 progress 35 % (39 MB)
106 00:17:15.460991 progress 40 % (44 MB)
107 00:17:15.838811 progress 45 % (50 MB)
108 00:17:16.496421 progress 50 % (56 MB)
109 00:17:17.302244 progress 55 % (61 MB)
110 00:17:18.035865 progress 60 % (67 MB)
111 00:17:18.753635 progress 65 % (73 MB)
112 00:17:19.511930 progress 70 % (78 MB)
113 00:17:20.268663 progress 75 % (84 MB)
114 00:17:21.054875 progress 80 % (89 MB)
115 00:17:21.782195 progress 85 % (95 MB)
116 00:17:22.585033 progress 90 % (101 MB)
117 00:17:23.365526 progress 95 % (106 MB)
118 00:17:24.194627 progress 100 % (112 MB)
119 00:17:24.208218 112 MB downloaded in 14.30 s (7.85 MB/s)
120 00:17:24.209233 end: 1.4.1 http-download (duration 00:00:14) [common]
122 00:17:24.210990 end: 1.4 download-retry (duration 00:00:14) [common]
123 00:17:24.211549 start: 1.5 download-retry (timeout 00:09:45) [common]
124 00:17:24.212134 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 00:17:24.213137 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 00:17:24.213643 saving as /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/modules/modules.tar
127 00:17:24.214088 total size: 6912416 (6 MB)
128 00:17:24.214539 Using unxz to decompress xz
129 00:17:24.256475 progress 0 % (0 MB)
130 00:17:24.291855 progress 5 % (0 MB)
131 00:17:24.341284 progress 10 % (0 MB)
132 00:17:24.388691 progress 15 % (1 MB)
133 00:17:24.438885 progress 20 % (1 MB)
134 00:17:24.484941 progress 25 % (1 MB)
135 00:17:24.533211 progress 30 % (2 MB)
136 00:17:24.576976 progress 35 % (2 MB)
137 00:17:24.624556 progress 40 % (2 MB)
138 00:17:24.668095 progress 45 % (2 MB)
139 00:17:24.716547 progress 50 % (3 MB)
140 00:17:24.763143 progress 55 % (3 MB)
141 00:17:24.810137 progress 60 % (3 MB)
142 00:17:24.858210 progress 65 % (4 MB)
143 00:17:24.903184 progress 70 % (4 MB)
144 00:17:24.953323 progress 75 % (4 MB)
145 00:17:24.997378 progress 80 % (5 MB)
146 00:17:25.045772 progress 85 % (5 MB)
147 00:17:25.089675 progress 90 % (5 MB)
148 00:17:25.137568 progress 95 % (6 MB)
149 00:17:25.181215 progress 100 % (6 MB)
150 00:17:25.195320 6 MB downloaded in 0.98 s (6.72 MB/s)
151 00:17:25.195900 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:17:25.197717 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:17:25.198275 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 00:17:25.198819 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 00:17:42.308181 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf
157 00:17:42.308814 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 00:17:42.309146 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 00:17:42.310004 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d
160 00:17:42.310587 makedir: /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin
161 00:17:42.311047 makedir: /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/tests
162 00:17:42.311477 makedir: /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/results
163 00:17:42.311855 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-add-keys
164 00:17:42.312495 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-add-sources
165 00:17:42.313137 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-background-process-start
166 00:17:42.313676 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-background-process-stop
167 00:17:42.314238 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-common-functions
168 00:17:42.314790 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-echo-ipv4
169 00:17:42.315300 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-install-packages
170 00:17:42.315809 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-installed-packages
171 00:17:42.316378 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-os-build
172 00:17:42.316929 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-probe-channel
173 00:17:42.317447 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-probe-ip
174 00:17:42.317996 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-target-ip
175 00:17:42.318554 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-target-mac
176 00:17:42.319092 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-target-storage
177 00:17:42.319715 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-case
178 00:17:42.320314 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-event
179 00:17:42.320855 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-feedback
180 00:17:42.321377 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-raise
181 00:17:42.321890 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-reference
182 00:17:42.322423 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-runner
183 00:17:42.322964 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-set
184 00:17:42.323503 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-test-shell
185 00:17:42.324049 Updating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-add-keys (debian)
186 00:17:42.324656 Updating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-add-sources (debian)
187 00:17:42.325205 Updating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-install-packages (debian)
188 00:17:42.325784 Updating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-installed-packages (debian)
189 00:17:42.326335 Updating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/bin/lava-os-build (debian)
190 00:17:42.326807 Creating /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/environment
191 00:17:42.327222 LAVA metadata
192 00:17:42.327503 - LAVA_JOB_ID=931507
193 00:17:42.327721 - LAVA_DISPATCHER_IP=192.168.6.2
194 00:17:42.328157 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 00:17:42.329237 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:17:42.329594 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 00:17:42.329804 skipped lava-vland-overlay
198 00:17:42.330046 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:17:42.330305 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 00:17:42.330527 skipped lava-multinode-overlay
201 00:17:42.330770 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:17:42.331019 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 00:17:42.331275 Loading test definitions
204 00:17:42.331561 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 00:17:42.331782 Using /lava-931507 at stage 0
206 00:17:42.333018 uuid=931507_1.6.2.4.1 testdef=None
207 00:17:42.333371 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:17:42.333638 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 00:17:42.335318 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:17:42.336178 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 00:17:42.338699 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:17:42.339575 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 00:17:42.341645 runner path: /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/0/tests/0_timesync-off test_uuid 931507_1.6.2.4.1
216 00:17:42.342326 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:17:42.343187 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 00:17:42.343419 Using /lava-931507 at stage 0
220 00:17:42.343793 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:17:42.344126 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/0/tests/1_kselftest-dt'
222 00:17:45.735942 Running '/usr/bin/git checkout kernelci.org
223 00:17:46.182794 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:17:46.184569 uuid=931507_1.6.2.4.5 testdef=None
225 00:17:46.185239 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:17:46.186844 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 00:17:46.192884 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:17:46.194645 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 00:17:46.202632 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:17:46.204514 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 00:17:46.212219 runner path: /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/0/tests/1_kselftest-dt test_uuid 931507_1.6.2.4.5
235 00:17:46.212808 BOARD='beaglebone-black'
236 00:17:46.213254 BRANCH='mainline'
237 00:17:46.213682 SKIPFILE='/dev/null'
238 00:17:46.214114 SKIP_INSTALL='True'
239 00:17:46.214539 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 00:17:46.214974 TST_CASENAME=''
241 00:17:46.215405 TST_CMDFILES='dt'
242 00:17:46.216535 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:17:46.218223 Creating lava-test-runner.conf files
245 00:17:46.218663 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/931507/lava-overlay-qojizz7d/lava-931507/0 for stage 0
246 00:17:46.219394 - 0_timesync-off
247 00:17:46.219892 - 1_kselftest-dt
248 00:17:46.220608 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:17:46.221196 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 00:18:09.552792 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 00:18:09.553237 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 00:18:09.553505 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:18:09.553776 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 00:18:09.554037 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 00:18:09.938363 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:18:09.938840 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 00:18:09.939090 extracting modules file /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf
258 00:18:10.830225 extracting modules file /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931507/extract-overlay-ramdisk-q857wglk/ramdisk
259 00:18:11.756744 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:18:11.757233 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 00:18:11.757516 [common] Applying overlay to NFS
262 00:18:11.757733 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931507/compress-overlay-pgtb6_9q/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf
263 00:18:14.520312 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:18:14.520793 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 00:18:14.521087 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 00:18:14.521377 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:18:14.521643 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:18:14.521916 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 00:18:14.522183 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:18:14.522449 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 00:18:14.522711 Building ramdisk /var/lib/lava/dispatcher/tmp/931507/extract-overlay-ramdisk-q857wglk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/931507/extract-overlay-ramdisk-q857wglk/ramdisk
272 00:18:15.585759 >> 79012 blocks
273 00:18:20.602165 Adding RAMdisk u-boot header.
274 00:18:20.602959 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/931507/extract-overlay-ramdisk-q857wglk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/931507/extract-overlay-ramdisk-q857wglk/ramdisk.cpio.gz.uboot
275 00:18:20.780287 output: Image Name:
276 00:18:20.780723 output: Created: Mon Nov 4 00:18:20 2024
277 00:18:20.780936 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:18:20.781141 output: Data Size: 15349950 Bytes = 14990.19 KiB = 14.64 MiB
279 00:18:20.781345 output: Load Address: 00000000
280 00:18:20.781545 output: Entry Point: 00000000
281 00:18:20.781745 output:
282 00:18:20.782348 rename /var/lib/lava/dispatcher/tmp/931507/extract-overlay-ramdisk-q857wglk/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot
283 00:18:20.782768 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:18:20.783056 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 00:18:20.783329 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 00:18:20.783571 No LXC device requested
287 00:18:20.783823 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:18:20.784230 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 00:18:20.784812 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:18:20.785276 Checking files for TFTP limit of 4294967296 bytes.
291 00:18:20.788210 end: 1 tftp-deploy (duration 00:01:11) [common]
292 00:18:20.788843 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:18:20.789418 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:18:20.789962 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:18:20.790512 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:18:20.791326 substitutions:
297 00:18:20.791787 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:18:20.792267 - {DTB_ADDR}: 0x88000000
299 00:18:20.792709 - {DTB}: 931507/tftp-deploy-wp8lfxf2/dtb/am335x-boneblack.dtb
300 00:18:20.793146 - {INITRD}: 931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot
301 00:18:20.793582 - {KERNEL_ADDR}: 0x82000000
302 00:18:20.794013 - {KERNEL}: 931507/tftp-deploy-wp8lfxf2/kernel/zImage
303 00:18:20.794446 - {LAVA_MAC}: None
304 00:18:20.794919 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf
305 00:18:20.795359 - {NFS_SERVER_IP}: 192.168.6.2
306 00:18:20.795790 - {PRESEED_CONFIG}: None
307 00:18:20.796256 - {PRESEED_LOCAL}: None
308 00:18:20.796691 - {RAMDISK_ADDR}: 0x83000000
309 00:18:20.797119 - {RAMDISK}: 931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot
310 00:18:20.797553 - {ROOT_PART}: None
311 00:18:20.797980 - {ROOT}: None
312 00:18:20.798403 - {SERVER_IP}: 192.168.6.2
313 00:18:20.798825 - {TEE_ADDR}: 0x83000000
314 00:18:20.799247 - {TEE}: None
315 00:18:20.799669 Parsed boot commands:
316 00:18:20.800108 - setenv autoload no
317 00:18:20.800537 - setenv initrd_high 0xffffffff
318 00:18:20.800964 - setenv fdt_high 0xffffffff
319 00:18:20.801384 - dhcp
320 00:18:20.801807 - setenv serverip 192.168.6.2
321 00:18:20.802234 - tftp 0x82000000 931507/tftp-deploy-wp8lfxf2/kernel/zImage
322 00:18:20.802656 - tftp 0x83000000 931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot
323 00:18:20.803082 - setenv initrd_size ${filesize}
324 00:18:20.803502 - tftp 0x88000000 931507/tftp-deploy-wp8lfxf2/dtb/am335x-boneblack.dtb
325 00:18:20.803922 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:18:20.804388 - bootz 0x82000000 0x83000000 0x88000000
327 00:18:20.804936 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:18:20.806560 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:18:20.807025 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 00:18:20.822883 Setting prompt string to ['lava-test: # ']
332 00:18:20.824502 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:18:20.825164 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:18:20.825867 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:18:20.826526 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:18:20.827863 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 00:18:20.870158 >> OK - accepted request
338 00:18:20.872388 Returned 0 in 0 seconds
339 00:18:20.973699 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:18:20.975648 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:18:20.976383 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:18:20.976974 Setting prompt string to ['Hit any key to stop autoboot']
344 00:18:20.977524 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:18:20.979301 Trying 192.168.56.22...
346 00:18:20.979888 Connected to conserv3.
347 00:18:20.980439 Escape character is '^]'.
348 00:18:20.980921
349 00:18:20.981389 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 00:18:20.981866
351 00:18:58.555141
352 00:18:58.561063 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 00:18:58.561921 Trying to boot from MMC1
354 00:18:59.140445
355 00:18:59.141124
356 00:18:59.145869 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 00:18:59.146442
358 00:18:59.146930 CPU : AM335X-GP rev 2.0
359 00:18:59.151015 Model: TI AM335x BeagleBone Black
360 00:18:59.151532 DRAM: 512 MiB
361 00:18:59.235881 Core: 160 devices, 18 uclasses, devicetree: separate
362 00:18:59.249688 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 00:18:59.650464 NAND: 0 MiB
364 00:18:59.660701 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 00:18:59.735273 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 00:18:59.756718 <ethaddr> not set. Validating first E-fuse MAC
367 00:18:59.786400 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 00:18:59.843821 Hit any key to stop autoboot: 2
370 00:18:59.844641 end: 2.4.2 bootloader-interrupt (duration 00:00:39) [common]
371 00:18:59.845269 start: 2.4.3 bootloader-commands (timeout 00:04:21) [common]
372 00:18:59.845726 Setting prompt string to ['=>']
373 00:18:59.846194 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:21)
374 00:18:59.854759 0
375 00:18:59.855632 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 00:18:59.856164 Sending with 10 millisecond of delay
378 00:19:00.991036 => setenv autoload no
379 00:19:01.001799 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
380 00:19:01.006711 setenv autoload no
381 00:19:01.007460 Sending with 10 millisecond of delay
383 00:19:02.804648 => setenv initrd_high 0xffffffff
384 00:19:02.815390 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
385 00:19:02.816312 setenv initrd_high 0xffffffff
386 00:19:02.817016 Sending with 10 millisecond of delay
388 00:19:04.433135 => setenv fdt_high 0xffffffff
389 00:19:04.443928 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
390 00:19:04.444836 setenv fdt_high 0xffffffff
391 00:19:04.445533 Sending with 10 millisecond of delay
393 00:19:04.737271 => dhcp
394 00:19:04.748013 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
395 00:19:04.748816 dhcp
396 00:19:04.749458 link up on port 0, speed 100, full duplex
397 00:19:04.749891 BOOTP broadcast 1
398 00:19:04.831115 DHCP client bound to address 192.168.6.16 (78 ms)
399 00:19:04.831884 Sending with 10 millisecond of delay
401 00:19:06.508086 => setenv serverip 192.168.6.2
402 00:19:06.518853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
403 00:19:06.519685 setenv serverip 192.168.6.2
404 00:19:06.520433 Sending with 10 millisecond of delay
406 00:19:10.002197 => tftp 0x82000000 931507/tftp-deploy-wp8lfxf2/kernel/zImage
407 00:19:10.012957 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
408 00:19:10.013794 tftp 0x82000000 931507/tftp-deploy-wp8lfxf2/kernel/zImage
409 00:19:10.014235 link up on port 0, speed 100, full duplex
410 00:19:10.017578 Using ethernet@4a100000 device
411 00:19:10.023132 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 00:19:10.030418 Filename '931507/tftp-deploy-wp8lfxf2/kernel/zImage'.
413 00:19:10.030872 Load address: 0x82000000
414 00:19:12.328745 Loading: *################################################## 11.5 MiB
415 00:19:12.329350 5 MiB/s
416 00:19:12.329782 done
417 00:19:12.332991 Bytes transferred = 12050944 (b7e200 hex)
418 00:19:12.333747 Sending with 10 millisecond of delay
420 00:19:16.780246 => tftp 0x83000000 931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot
421 00:19:16.790982 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
422 00:19:16.978032 tftp 0x83000000 931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot
423 00:19:16.983492 link up on port 0, speed 100, full duplex
424 00:19:16.989112 Using ethernet@4a100000 device
425 00:19:16.994685 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 00:19:16.998238 Filename '931507/tftp-deploy-wp8lfxf2/ramdisk/ramdisk.cpio.gz.uboot'.
427 00:19:17.003294 Load address: 0x83000000
428 00:19:20.026747 Loading: *################################################## 14.6 MiB
429 00:19:20.027544 4.8 MiB/s
430 00:19:20.028160 done
431 00:19:20.030954 Bytes transferred = 15350014 (ea38fe hex)
432 00:19:20.031851 Sending with 10 millisecond of delay
434 00:19:21.889888 => setenv initrd_size ${filesize}
435 00:19:21.900831 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
436 00:19:21.901886 setenv initrd_size ${filesize}
437 00:19:21.902727 Sending with 10 millisecond of delay
439 00:19:26.049107 => tftp 0x88000000 931507/tftp-deploy-wp8lfxf2/dtb/am335x-boneblack.dtb
440 00:19:26.059651 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:55)
441 00:19:26.060180 tftp 0x88000000 931507/tftp-deploy-wp8lfxf2/dtb/am335x-boneblack.dtb
442 00:19:26.060421 link up on port 0, speed 100, full duplex
443 00:19:26.064480 Using ethernet@4a100000 device
444 00:19:26.069968 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 00:19:26.080896 Filename '931507/tftp-deploy-wp8lfxf2/dtb/am335x-boneblack.dtb'.
446 00:19:26.081384 Load address: 0x88000000
447 00:19:26.090969 Loading: *################################################## 68.9 KiB
448 00:19:26.091438 4.8 MiB/s
449 00:19:26.098621 done
450 00:19:26.099108 Bytes transferred = 70568 (113a8 hex)
451 00:19:26.100195 Sending with 10 millisecond of delay
453 00:19:39.275808 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 00:19:39.286620 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
455 00:19:39.287472 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 00:19:39.288182 Sending with 10 millisecond of delay
458 00:19:41.627756 => bootz 0x82000000 0x83000000 0x88000000
459 00:19:41.638918 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 00:19:41.639794 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
461 00:19:41.641230 bootz 0x82000000 0x83000000 0x88000000
462 00:19:41.642133 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
463 00:19:41.642739 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 00:19:41.646626 Image Name:
465 00:19:41.647304 Created: 2024-11-04 0:18:20 UTC
466 00:19:41.649994 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 00:19:41.655403 Data Size: 15349950 Bytes = 14.6 MiB
468 00:19:41.663803 Load Address: 00000000
469 00:19:41.664455 Entry Point: 00000000
470 00:19:41.838668 Verifying Checksum ... OK
471 00:19:41.839500 ## Flattened Device Tree blob at 88000000
472 00:19:41.844920 Booting using the fdt blob at 0x88000000
473 00:19:41.845578 Working FDT set to 88000000
474 00:19:41.850325 Using Device Tree in place at 88000000, end 880143a7
475 00:19:41.854742 Working FDT set to 88000000
476 00:19:41.868168
477 00:19:41.868989 Starting kernel ...
478 00:19:41.869573
479 00:19:41.870727 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 00:19:41.871577 start: 2.4.4 auto-login-action (timeout 00:03:39) [common]
481 00:19:41.872299 Setting prompt string to ['Linux version [0-9]']
482 00:19:41.872962 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 00:19:41.873875 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 00:19:42.762688 [ 0.000000] Booting Linux on physical CPU 0x0
485 00:19:42.768782 start: 2.4.4.1 login-action (timeout 00:03:38) [common]
486 00:19:42.769570 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 00:19:42.770199 Setting prompt string to []
488 00:19:42.770847 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 00:19:42.771445 Using line separator: #'\n'#
490 00:19:42.772023 No login prompt set.
491 00:19:42.772610 Parsing kernel messages
492 00:19:42.773126 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 00:19:42.774184 [login-action] Waiting for messages, (timeout 00:03:38)
494 00:19:42.774801 Waiting using forced prompt support (timeout 00:01:49)
495 00:19:42.779565 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j361102-arm-clang-15-multi-v7-defconfig-7vh4j) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sun Nov 3 23:10:46 UTC 2024
496 00:19:42.785279 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 00:19:42.796670 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 00:19:42.802475 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 00:19:42.808141 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 00:19:42.813942 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 00:19:42.820586 [ 0.000000] Memory policy: Data cache writeback
502 00:19:42.821173 [ 0.000000] efi: UEFI not found.
503 00:19:42.829400 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 00:19:42.835044 [ 0.000000] Zone ranges:
505 00:19:42.840776 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 00:19:42.841369 [ 0.000000] Normal empty
507 00:19:42.846498 [ 0.000000] HighMem empty
508 00:19:42.852283 [ 0.000000] Movable zone start for each node
509 00:19:42.852915 [ 0.000000] Early memory node ranges
510 00:19:42.858033 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 00:19:42.867839 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 00:19:42.885989 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 00:19:42.891604 [ 0.000000] AM335X ES2.0 (sgx neon)
514 00:19:42.903418 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
515 00:19:42.921048 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 00:19:42.932582 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 00:19:42.938342 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 00:19:42.944077 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 00:19:42.954114 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 00:19:42.983560 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 00:19:42.989507 <6>[ 0.000000] trace event string verifier disabled
522 00:19:42.990143 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 00:19:42.995323 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 00:19:43.006682 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 00:19:43.012377 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 00:19:43.019729 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 00:19:43.034782 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 00:19:43.052338 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 00:19:43.059132 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 00:19:43.158803 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 00:19:43.167406 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 00:19:43.179923 <6>[ 0.008343] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 00:19:43.188142 <6>[ 0.019195] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 00:19:43.197704 <6>[ 0.034223] Console: colour dummy device 80x30
535 00:19:43.203818 Matched prompt #6: WARNING:
536 00:19:43.204383 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 00:19:43.209319 <3>[ 0.039129] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 00:19:43.212089 <3>[ 0.046205] This ensures that you still see kernel messages. Please
539 00:19:43.218201 <3>[ 0.052932] update your kernel commandline.
540 00:19:43.258728 <6>[ 0.057547] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 00:19:43.264488 <6>[ 0.096204] CPU: Testing write buffer coherency: ok
542 00:19:43.267404 <6>[ 0.101574] CPU0: Spectre v2: using BPIALL workaround
543 00:19:43.273409 <6>[ 0.107039] pid_max: default: 32768 minimum: 301
544 00:19:43.279059 <6>[ 0.112233] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 00:19:43.291702 <6>[ 0.120058] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 00:19:43.298832 <6>[ 0.129518] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 00:19:43.307359 <6>[ 0.136478] Setting up static identity map for 0x80300000 - 0x803000ac
548 00:19:43.313023 <6>[ 0.146200] rcu: Hierarchical SRCU implementation.
549 00:19:43.317845 <6>[ 0.151488] rcu: Max phase no-delay instances is 1000.
550 00:19:43.326572 <6>[ 0.162827] EFI services will not be available.
551 00:19:43.332435 <6>[ 0.168117] smp: Bringing up secondary CPUs ...
552 00:19:43.338209 <6>[ 0.173175] smp: Brought up 1 node, 1 CPU
553 00:19:43.346404 <6>[ 0.177575] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 00:19:43.352320 <6>[ 0.184346] CPU: All CPU(s) started in SVC mode.
555 00:19:43.364506 <6>[ 0.189554] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
556 00:19:43.370338 <6>[ 0.205843] devtmpfs: initialized
557 00:19:43.393635 <6>[ 0.223970] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 00:19:43.401773 <6>[ 0.232589] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 00:19:43.411032 <6>[ 0.243060] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 00:19:43.421851 <6>[ 0.255371] pinctrl core: initialized pinctrl subsystem
561 00:19:43.431419 <6>[ 0.266225] DMI not present or invalid.
562 00:19:43.439787 <6>[ 0.272127] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 00:19:43.449243 <6>[ 0.281133] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 00:19:43.464437 <6>[ 0.292757] thermal_sys: Registered thermal governor 'step_wise'
565 00:19:43.464935 <6>[ 0.292927] cpuidle: using governor menu
566 00:19:43.491893 <6>[ 0.328342] No ATAGs?
567 00:19:43.498123 <6>[ 0.331085] hw-breakpoint: debug architecture 0x4 unsupported.
568 00:19:43.508533 <6>[ 0.343248] Serial: AMBA PL011 UART driver
569 00:19:43.539184 <6>[ 0.375567] iommu: Default domain type: Translated
570 00:19:43.548261 <6>[ 0.380919] iommu: DMA domain TLB invalidation policy: strict mode
571 00:19:43.574916 <5>[ 0.410648] SCSI subsystem initialized
572 00:19:43.580713 <6>[ 0.415573] usbcore: registered new interface driver usbfs
573 00:19:43.586644 <6>[ 0.421613] usbcore: registered new interface driver hub
574 00:19:43.593469 <6>[ 0.427404] usbcore: registered new device driver usb
575 00:19:43.599169 <6>[ 0.433963] pps_core: LinuxPPS API ver. 1 registered
576 00:19:43.610633 <6>[ 0.439354] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 00:19:43.617800 <6>[ 0.449084] PTP clock support registered
578 00:19:43.618276 <6>[ 0.453550] EDAC MC: Ver: 3.0.0
579 00:19:43.675579 <6>[ 0.509109] scmi_core: SCMI protocol bus registered
580 00:19:43.681161 <6>[ 0.517314] vgaarb: loaded
581 00:19:43.693584 <6>[ 0.530113] clocksource: Switched to clocksource dmtimer
582 00:19:43.732646 <6>[ 0.568699] NET: Registered PF_INET protocol family
583 00:19:43.745474 <6>[ 0.574435] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 00:19:43.751234 <6>[ 0.583452] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 00:19:43.762598 <6>[ 0.592391] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 00:19:43.768476 <6>[ 0.600656] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 00:19:43.779913 <6>[ 0.608929] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 00:19:43.785826 <6>[ 0.616646] TCP: Hash tables configured (established 4096 bind 4096)
589 00:19:43.791559 <6>[ 0.623566] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 00:19:43.797464 <6>[ 0.630610] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 00:19:43.804969 <6>[ 0.638195] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 00:19:43.886671 <6>[ 0.717512] RPC: Registered named UNIX socket transport module.
593 00:19:43.887373 <6>[ 0.723958] RPC: Registered udp transport module.
594 00:19:43.892430 <6>[ 0.729066] RPC: Registered tcp transport module.
595 00:19:43.898222 <6>[ 0.734192] RPC: Registered tcp-with-tls transport module.
596 00:19:43.911280 <6>[ 0.740121] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 00:19:43.911798 <6>[ 0.747026] PCI: CLS 0 bytes, default 64
598 00:19:43.918506 <5>[ 0.752881] Initialise system trusted keyrings
599 00:19:43.940574 <6>[ 0.773940] Trying to unpack rootfs image as initramfs...
600 00:19:44.010687 <6>[ 0.840927] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 00:19:44.015497 <6>[ 0.848453] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 00:19:44.072587 <5>[ 0.908905] NFS: Registering the id_resolver key type
603 00:19:44.078200 <5>[ 0.914576] Key type id_resolver registered
604 00:19:44.084015 <5>[ 0.919154] Key type id_legacy registered
605 00:19:44.089792 <6>[ 0.923620] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 00:19:44.099482 <6>[ 0.930818] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 00:19:44.164262 <5>[ 1.000754] Key type asymmetric registered
608 00:19:44.170233 <5>[ 1.005282] Asymmetric key parser 'x509' registered
609 00:19:44.181627 <6>[ 1.010823] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 00:19:44.182117 <6>[ 1.018713] io scheduler mq-deadline registered
611 00:19:44.187492 <6>[ 1.023688] io scheduler kyber registered
612 00:19:44.193034 <6>[ 1.028143] io scheduler bfq registered
613 00:19:44.307633 <6>[ 1.140379] ledtrig-cpu: registered to indicate activity on CPUs
614 00:19:44.650989 <6>[ 1.483627] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 00:19:44.688011 <6>[ 1.524364] msm_serial: driver initialized
616 00:19:44.694074 <6>[ 1.529154] SuperH (H)SCI(F) driver initialized
617 00:19:44.699973 <6>[ 1.534466] STMicroelectronics ASC driver initialized
618 00:19:44.705265 <6>[ 1.540135] STM32 USART driver initialized
619 00:19:44.815710 <6>[ 1.651587] brd: module loaded
620 00:19:44.852611 <6>[ 1.688433] loop: module loaded
621 00:19:44.892270 <6>[ 1.727850] CAN device driver interface
622 00:19:44.898909 <6>[ 1.733163] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 00:19:44.904616 <6>[ 1.740195] e1000e: Intel(R) PRO/1000 Network Driver
624 00:19:44.911298 <6>[ 1.745581] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 00:19:44.916984 <6>[ 1.752026] igb: Intel(R) Gigabit Ethernet Network Driver
626 00:19:44.924590 <6>[ 1.757849] igb: Copyright (c) 2007-2014 Intel Corporation.
627 00:19:44.936337 <6>[ 1.767136] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 00:19:44.942110 <6>[ 1.773299] usbcore: registered new interface driver pegasus
629 00:19:44.947908 <6>[ 1.779425] usbcore: registered new interface driver asix
630 00:19:44.953770 <6>[ 1.785327] usbcore: registered new interface driver ax88179_178a
631 00:19:44.959625 <6>[ 1.791952] usbcore: registered new interface driver cdc_ether
632 00:19:44.965360 <6>[ 1.798254] usbcore: registered new interface driver smsc75xx
633 00:19:44.971105 <6>[ 1.804493] usbcore: registered new interface driver smsc95xx
634 00:19:44.976865 <6>[ 1.810733] usbcore: registered new interface driver net1080
635 00:19:44.982638 <6>[ 1.816855] usbcore: registered new interface driver cdc_subset
636 00:19:44.988480 <6>[ 1.823266] usbcore: registered new interface driver zaurus
637 00:19:44.996096 <6>[ 1.829311] usbcore: registered new interface driver cdc_ncm
638 00:19:45.005898 <6>[ 1.838807] usbcore: registered new interface driver usb-storage
639 00:19:45.015277 <6>[ 1.849951] i2c_dev: i2c /dev entries driver
640 00:19:45.040534 <5>[ 1.868911] cpuidle: enable-method property 'ti,am3352' found operations
641 00:19:45.046305 <6>[ 1.878527] sdhci: Secure Digital Host Controller Interface driver
642 00:19:45.054218 <6>[ 1.885290] sdhci: Copyright(c) Pierre Ossman
643 00:19:45.061372 <6>[ 1.891873] Synopsys Designware Multimedia Card Interface Driver
644 00:19:45.066613 <6>[ 1.899791] sdhci-pltfm: SDHCI platform and OF driver helper
645 00:19:45.080972 <6>[ 1.910022] usbcore: registered new interface driver usbhid
646 00:19:45.081418 <6>[ 1.916142] usbhid: USB HID core driver
647 00:19:45.094107 <6>[ 1.928045] NET: Registered PF_INET6 protocol family
648 00:19:45.561281 <6>[ 2.397674] Segment Routing with IPv6
649 00:19:45.566973 <6>[ 2.401891] In-situ OAM (IOAM) with IPv6
650 00:19:45.573662 <6>[ 2.406302] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 00:19:45.581014 <6>[ 2.413645] NET: Registered PF_PACKET protocol family
652 00:19:45.586949 <6>[ 2.419129] can: controller area network core
653 00:19:45.587391 <6>[ 2.424032] NET: Registered PF_CAN protocol family
654 00:19:45.592713 <6>[ 2.429240] can: raw protocol
655 00:19:45.598463 <6>[ 2.432591] can: broadcast manager protocol
656 00:19:45.605335 <6>[ 2.437171] can: netlink gateway - max_hops=1
657 00:19:45.605766 <5>[ 2.442703] Key type dns_resolver registered
658 00:19:45.611154 <6>[ 2.447698] ThumbEE CPU extension supported.
659 00:19:45.617387 <5>[ 2.452489] Registering SWP/SWPB emulation handler
660 00:19:45.625668 <3>[ 2.458150] omap_voltage_late_init: Voltage driver support not added
661 00:19:45.833349 <5>[ 2.667405] Loading compiled-in X.509 certificates
662 00:19:45.976169 <6>[ 2.799750] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 00:19:45.983324 <6>[ 2.816470] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 00:19:46.010273 <3>[ 2.840833] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 00:19:46.203743 <3>[ 3.034243] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 00:19:46.396186 <6>[ 3.231000] OMAP GPIO hardware version 0.1
667 00:19:46.417306 <6>[ 3.250041] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 00:19:46.489791 <4>[ 3.322362] at24 2-0054: supply vcc not found, using dummy regulator
669 00:19:46.522891 <4>[ 3.355423] at24 2-0055: supply vcc not found, using dummy regulator
670 00:19:46.562920 <4>[ 3.395495] at24 2-0056: supply vcc not found, using dummy regulator
671 00:19:46.603580 <4>[ 3.436115] at24 2-0057: supply vcc not found, using dummy regulator
672 00:19:46.639496 <6>[ 3.472889] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 00:19:46.698203 <3>[ 3.527464] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 00:19:46.723074 <6>[ 3.548732] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 00:19:46.745833 <4>[ 3.575535] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 00:19:46.753450 <4>[ 3.584760] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 00:19:46.837519 <6>[ 3.673858] Freeing initrd memory: 14992K
678 00:19:46.845803 <6>[ 3.678517] omap_rng 48310000.rng: Random Number Generator ver. 20
679 00:19:46.869804 <5>[ 3.705361] random: crng init done
680 00:19:46.918888 <6>[ 3.750110] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 00:19:46.972197 <6>[ 3.802578] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 00:19:46.978058 <6>[ 3.812915] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 00:19:46.989800 <6>[ 3.820259] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 00:19:46.995616 <6>[ 3.827732] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 00:19:47.007176 <6>[ 3.835870] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 00:19:47.014608 <6>[ 3.847508] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 00:19:47.027884 <5>[ 3.856629] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 00:19:47.056257 <3>[ 3.887102] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 00:19:47.062026 <6>[ 3.895727] edma 49000000.dma: TI EDMA DMA engine driver
690 00:19:47.134967 <3>[ 3.965118] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 00:19:47.149924 <6>[ 3.979662] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 00:19:47.162959 <3>[ 3.996919] l3-aon-clkctrl:0000:0: failed to disable
693 00:19:47.218056 <6>[ 4.048864] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 00:19:47.223845 <6>[ 4.058391] printk: legacy console [ttyS0] enabled
695 00:19:47.229440 <6>[ 4.058391] printk: legacy console [ttyS0] enabled
696 00:19:47.235124 <6>[ 4.068735] printk: legacy bootconsole [omap8250] disabled
697 00:19:47.240986 <6>[ 4.068735] printk: legacy bootconsole [omap8250] disabled
698 00:19:47.271168 <4>[ 4.101007] tps65217-pmic: Failed to locate of_node [id: -1]
699 00:19:47.274784 <4>[ 4.108421] tps65217-bl: Failed to locate of_node [id: -1]
700 00:19:47.291867 <6>[ 4.128648] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 00:19:47.310270 <6>[ 4.135666] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 00:19:47.321991 <6>[ 4.149372] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 00:19:47.327730 <6>[ 4.161270] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 00:19:47.350351 <6>[ 4.181504] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 00:19:47.356272 <6>[ 4.190686] sdhci-omap 48060000.mmc: Got CD GPIO
706 00:19:47.364341 <4>[ 4.195840] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 00:19:47.379273 <4>[ 4.209659] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 00:19:47.385702 <4>[ 4.218422] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 00:19:47.395523 <4>[ 4.227077] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 00:19:47.495001 <6>[ 4.327256] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 00:19:47.534623 <6>[ 4.365995] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
712 00:19:47.555262 <6>[ 4.385661] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
713 00:19:47.562032 <6>[ 4.394651] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 00:19:47.602818 <6>[ 4.429559] mmc0: new high speed SDHC card at address 0001
715 00:19:47.603289 <6>[ 4.437599] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 00:19:47.609985 <6>[ 4.446550] mmcblk0: p1
717 00:19:47.642809 <6>[ 4.471401] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
718 00:19:47.658728 <4>[ 4.488229] mmc1: unexpected status 0x2000980 after switch
719 00:19:47.665374 <4>[ 4.495806] mmc1: unexpected status 0x2000900 after switch
720 00:19:47.671759 <4>[ 4.502580] mmc1: unexpected status 0x2000900 after switch
721 00:19:47.677433 <4>[ 4.509194] mmc1: unexpected status 0x2000900 after switch
722 00:19:47.687763 <6>[ 4.515080] mmc1: new high speed MMC card at address 0001
723 00:19:47.688232 <6>[ 4.522378] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 00:19:49.383683 <4>[ 6.212720] mmc1: unexpected status 0x2000980 after switch
725 00:19:49.390005 <4>[ 6.220419] mmc1: unexpected status 0x2000900 after switch
726 00:19:49.396183 <4>[ 6.226712] mmc1: unexpected status 0x2000900 after switch
727 00:19:49.399849 <4>[ 6.233450] mmc1: unexpected status 0x2000900 after switch
728 00:19:49.760625 <6>[ 6.591200] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 00:19:49.863972 <5>[ 6.620137] Sending DHCP requests ., OK
730 00:19:49.875246 <6>[ 6.704569] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 00:19:49.875710 <6>[ 6.712773] IP-Config: Complete:
732 00:19:49.889418 <6>[ 6.716313] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 00:19:49.895342 <6>[ 6.726846] host=192.168.6.16, domain=, nis-domain=(none)
734 00:19:49.898379 <6>[ 6.733065] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 00:19:49.905180 <6>[ 6.733102] nameserver0=10.255.253.1
736 00:19:49.911158 <6>[ 6.745716] clk: Disabling unused clocks
737 00:19:49.916472 <6>[ 6.750445] PM: genpd: Disabling unused power domains
738 00:19:49.934932 <6>[ 6.767956] Freeing unused kernel image (initmem) memory: 2048K
739 00:19:49.942640 <6>[ 6.777967] Run /init as init process
740 00:19:49.968666 Loading, please wait...
741 00:19:50.046627 Starting systemd-udevd version 252.22-1~deb12u1
742 00:19:50.133321 <3>[ 6.963889] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
743 00:19:50.871705 <3>[ 7.702255] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 00:19:51.605690 <3>[ 8.437388] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 00:19:52.344756 <3>[ 9.175553] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 00:19:53.109796 <3>[ 9.940556] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 00:19:53.232552 <4>[ 10.062013] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 00:19:53.461638 <4>[ 10.291170] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 00:19:53.655852 <6>[ 10.492757] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 00:19:53.666485 <6>[ 10.498446] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 00:19:53.849629 <3>[ 10.680451] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
752 00:19:53.875064 <6>[ 10.710636] hub 1-0:1.0: USB hub found
753 00:19:53.928429 <6>[ 10.763642] tda998x 0-0070: found TDA19988
754 00:19:53.943883 <6>[ 10.779228] hub 1-0:1.0: 1 port detected
755 00:19:54.634538 <3>[ 11.466268] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 00:19:54.936646 <6>[ 11.770375] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 00:19:55.126464 <3>[ 11.960402] usb 1-1: device descriptor read/64, error -71
758 00:19:55.376366 <3>[ 12.210275] usb 1-1: device descriptor read/64, error -71
759 00:19:55.407171 <3>[ 12.238513] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
760 00:19:55.415224 <3>[ 12.247415] Buffer I/O error on dev mmcblk1, logical block 0, async page read
761 00:19:55.617759 <6>[ 12.450533] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 00:19:55.796562 <3>[ 12.630518] usb 1-1: device descriptor read/64, error -71
763 00:19:56.035561 <3>[ 12.870436] usb 1-1: device descriptor read/64, error -71
764 00:19:56.201278 <6>[ 13.036079] usb usb1-port1: attempt power cycle
765 00:19:56.387562 <6>[ 13.220369] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 00:19:56.987008 <6>[ 13.819603] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 00:19:58.519840 <3>[ 15.350460] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
768 00:19:59.288073 <3>[ 16.118842] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
769 00:20:00.056426 <3>[ 16.887190] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
770 00:20:00.824766 <3>[ 17.655538] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
771 00:20:01.593059 <3>[ 18.423936] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
772 00:20:02.361562 <3>[ 19.192545] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
773 00:20:03.129903 <3>[ 19.960995] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
774 00:20:03.898011 <3>[ 20.729528] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
775 00:20:03.903768 <3>[ 20.738472] Buffer I/O error on dev mmcblk1, logical block 0, async page read
776 00:20:03.911469 <6>[ 20.746161] mmcblk1: unable to read partition table
777 00:20:03.926330 <6>[ 20.761054] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
778 00:20:03.943587 <6>[ 20.778330] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
779 00:20:03.955068 <6>[ 20.788531] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
780 00:20:07.194228 <3>[ 24.024400] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
781 00:20:07.963809 <3>[ 24.793930] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
782 00:20:08.733151 <3>[ 25.563201] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
783 00:20:09.502224 <3>[ 26.332527] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
784 00:20:10.271689 <3>[ 27.101994] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
785 00:20:11.041139 <3>[ 27.871462] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
786 00:20:11.810633 <3>[ 28.640866] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
787 00:20:12.579886 <3>[ 29.410282] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
788 00:20:15.808136 <3>[ 32.638870] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
789 00:20:16.577194 <3>[ 33.408036] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
790 00:20:17.346350 <3>[ 34.177117] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
791 00:20:18.115152 <3>[ 34.946082] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
792 00:20:18.884389 <3>[ 35.715284] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
793 00:20:19.653321 <3>[ 36.484284] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
794 00:20:20.422553 <3>[ 37.253500] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 00:20:21.190343 <3>[ 38.022392] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 00:20:21.199336 <3>[ 38.031838] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
797 00:20:21.242469 Begin: Loading essential drivers ... done.
798 00:20:21.248190 Begin: Running /scripts/init-premount ... done.
799 00:20:21.253738 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
800 00:20:21.267512 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
801 00:20:21.268027 Device /sys/class/net/eth0 found
802 00:20:21.268451 done.
803 00:20:21.326691 Begin: Waiting up to 180 secs for any network device to become available ... done.
804 00:20:21.395972 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
805 00:20:21.505546 IP-Config: eth0 guessed broadcast address 192.168.6.255
806 00:20:21.510998 IP-Config: eth0 complete (dhcp from 192.168.6.1):
807 00:20:21.516773 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
808 00:20:21.527951 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
809 00:20:21.528449 rootserver: 192.168.6.1 rootpath:
810 00:20:21.531427 filename :
811 00:20:21.657300 done.
812 00:20:21.668009 Begin: Running /scripts/nfs-bottom ... done.
813 00:20:21.735235 Begin: Running /scripts/init-bottom ... done.
814 00:20:23.344465 <30>[ 40.177820] systemd[1]: System time before build time, advancing clock.
815 00:20:23.543870 <30>[ 40.351185] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
816 00:20:23.552592 <30>[ 40.387852] systemd[1]: Detected architecture arm.
817 00:20:23.565220
818 00:20:23.565707 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
819 00:20:23.566125
820 00:20:23.596728 <30>[ 40.430753] systemd[1]: Hostname set to <debian-bookworm-armhf>.
821 00:20:26.092483 <30>[ 42.925402] systemd[1]: Queued start job for default target graphical.target.
822 00:20:26.109399 <30>[ 42.940578] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
823 00:20:26.117063 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
824 00:20:26.142624 <30>[ 42.972596] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
825 00:20:26.150117 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
826 00:20:26.175091 <30>[ 43.006450] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
827 00:20:26.188400 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
828 00:20:26.210534 <30>[ 43.042045] systemd[1]: Created slice user.slice - User and Session Slice.
829 00:20:26.217374 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
830 00:20:26.246887 <30>[ 43.072234] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
831 00:20:26.253040 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
832 00:20:26.280959 <30>[ 43.111272] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
833 00:20:26.291970 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
834 00:20:26.318478 <30>[ 43.141285] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
835 00:20:26.332356 <30>[ 43.163531] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
836 00:20:26.337854 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
837 00:20:26.358920 <30>[ 43.190660] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
838 00:20:26.367240 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
839 00:20:26.389606 <30>[ 43.221054] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
840 00:20:26.398154 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
841 00:20:26.419414 <30>[ 43.251100] systemd[1]: Reached target paths.target - Path Units.
842 00:20:26.424586 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
843 00:20:26.449129 <30>[ 43.280799] systemd[1]: Reached target remote-fs.target - Remote File Systems.
844 00:20:26.456566 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
845 00:20:26.478970 <30>[ 43.310683] systemd[1]: Reached target slices.target - Slice Units.
846 00:20:26.484515 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
847 00:20:26.509225 <30>[ 43.340895] systemd[1]: Reached target swap.target - Swaps.
848 00:20:26.513364 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
849 00:20:26.539456 <30>[ 43.370855] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
850 00:20:26.548321 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
851 00:20:26.570505 <30>[ 43.401882] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
852 00:20:26.578780 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
853 00:20:26.663636 <30>[ 43.490318] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
854 00:20:26.676419 <30>[ 43.507830] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
855 00:20:26.684856 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
856 00:20:26.711147 <30>[ 43.541908] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
857 00:20:26.718481 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
858 00:20:26.742529 <30>[ 43.573809] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
859 00:20:26.750801 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
860 00:20:26.774159 <30>[ 43.605298] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
861 00:20:26.779731 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
862 00:20:26.813338 <30>[ 43.643573] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
863 00:20:26.820790 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
864 00:20:26.846293 <30>[ 43.671767] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
865 00:20:26.862853 <30>[ 43.688334] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
866 00:20:26.909491 <30>[ 43.741868] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
867 00:20:26.929946 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
868 00:20:26.954994 <30>[ 43.787244] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
869 00:20:26.984483 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
870 00:20:27.093994 <30>[ 43.926056] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
871 00:20:27.128202 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
872 00:20:27.179314 <30>[ 44.011221] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
873 00:20:27.207200 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
874 00:20:27.259281 <30>[ 44.091559] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
875 00:20:27.282163 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
876 00:20:27.349727 <30>[ 44.182345] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
877 00:20:27.388018 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
878 00:20:27.441483 <30>[ 44.272765] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
879 00:20:27.460846 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
880 00:20:27.489522 <30>[ 44.321708] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
881 00:20:27.509910 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
882 00:20:27.568772 <30>[ 44.401391] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
883 00:20:27.583337 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
884 00:20:27.605833 <28>[ 44.432924] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
885 00:20:27.626704 <28>[ 44.458370] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
886 00:20:27.669580 <30>[ 44.501311] systemd[1]: Starting systemd-journald.service - Journal Service...
887 00:20:27.676080 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
888 00:20:27.715697 <30>[ 44.547915] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
889 00:20:27.739919 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
890 00:20:27.793821 <30>[ 44.626291] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
891 00:20:27.848104 Starting [0;1;39msystemd-network-g… units from Kernel command line...
892 00:20:27.914215 <30>[ 44.745176] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
893 00:20:27.973475 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
894 00:20:28.046113 <30>[ 44.877831] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
895 00:20:28.109105 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
896 00:20:28.159674 <30>[ 44.992270] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
897 00:20:28.205170 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
898 00:20:28.221267 <30>[ 45.053816] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
899 00:20:28.256848 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
900 00:20:28.283881 <30>[ 45.115190] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
901 00:20:28.299847 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
902 00:20:28.469679 <30>[ 45.302793] systemd[1]: modprobe@configfs.service: Deactivated successfully.
903 00:20:28.500196 <30>[ 45.332171] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
904 00:20:28.529114 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
905 00:20:28.559711 <30>[ 45.392967] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
906 00:20:28.589589 <30>[ 45.422027] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
907 00:20:28.619175 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
908 00:20:28.639786 <30>[ 45.473271] systemd[1]: modprobe@drm.service: Deactivated successfully.
909 00:20:28.658899 <30>[ 45.491857] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
910 00:20:28.687817 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
911 00:20:28.700033 <30>[ 45.532999] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
912 00:20:28.739110 <30>[ 45.570765] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
913 00:20:28.761529 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
914 00:20:28.779918 <30>[ 45.611814] systemd[1]: Started systemd-journald.service - Journal Service.
915 00:20:28.786829 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
916 00:20:28.820206 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
917 00:20:28.851621 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
918 00:20:28.879292 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
919 00:20:28.901612 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
920 00:20:28.921511 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
921 00:20:28.949187 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
922 00:20:29.008441 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
923 00:20:29.080887 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
924 00:20:29.160674 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
925 00:20:29.240288 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
926 00:20:29.330360 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
927 00:20:29.454469 <46>[ 46.286969] systemd-journald[164]: Received client request to flush runtime journal.
928 00:20:29.467585 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
929 00:20:29.589165 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
930 00:20:30.432697 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
931 00:20:30.815970 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
932 00:20:30.871142 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
933 00:20:31.316258 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
934 00:20:31.502265 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
935 00:20:31.531325 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
936 00:20:31.548817 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
937 00:20:31.643744 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
938 00:20:31.693952 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
939 00:20:32.624193 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
940 00:20:32.699675 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
941 00:20:32.903345 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
942 00:20:33.037496 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
943 00:20:33.137684 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
944 00:20:35.053561 <4>[ 51.882963] mmc1: unexpected status 0x2000980 after switch
945 00:20:35.058845 [[0m[0;31m* [0m] (1 of 5) Job dev-ttyS0.device/start running (8s / 1min 30s)
946 00:20:35.144747 <4>[ 51.979772] mmc1: unexpected status 0x2000900 after switch
947 00:20:35.182536 <4>[ 52.017609] mmc1: unexpected status 0x2000900 after switch
948 00:20:35.201389 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
949 00:20:35.255713 [K<4>[ 52.090729] mmc1: unexpected status 0x2000900 after switch
950 00:20:35.562023 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
951 00:20:36.041987 <5>[ 52.874613] cfg80211: Loading compiled-in X.509 certificates for regulatory database
952 00:20:36.536416 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
953 00:20:37.447728 <5>[ 54.282629] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
954 00:20:37.533470 <5>[ 54.366881] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
955 00:20:37.546319 <4>[ 54.379023] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
956 00:20:37.552241 <6>[ 54.388175] cfg80211: failed to load regulatory.db
957 00:20:38.011902 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
958 00:20:38.340019 <46>[ 55.163768] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
959 00:20:38.437357 <3>[ 55.268691] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
960 00:20:38.497873 <46>[ 55.323905] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
961 00:20:38.544370 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
962 00:20:39.203211 <3>[ 56.034485] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
963 00:20:39.948989 <3>[ 56.780380] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
964 00:20:40.696166 <3>[ 57.527491] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
965 00:20:41.440308 <3>[ 58.271768] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
966 00:20:42.185430 <3>[ 59.016867] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
967 00:20:42.930439 <3>[ 59.761955] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
968 00:20:43.699054 <3>[ 60.530468] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
969 00:20:46.823448 <3>[ 63.655349] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
970 00:20:47.557185 <3>[ 64.389206] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
971 00:20:47.968399 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
972 00:20:47.987647 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
973 00:20:48.010847 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
974 00:20:48.031158 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
975 00:20:48.088275 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
976 00:20:48.141803 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
977 00:20:48.188299 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
978 00:20:48.231355 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
979 00:20:48.297687 <3>[ 65.128988] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
980 00:20:48.305329 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
981 00:20:48.332437 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
982 00:20:48.368643 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
983 00:20:48.394739 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
984 00:20:48.423858 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
985 00:20:48.469403 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
986 00:20:48.492099 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
987 00:20:48.527612 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
988 00:20:48.554873 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
989 00:20:48.585014 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
990 00:20:48.624952 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
991 00:20:48.649694 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
992 00:20:48.679296 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
993 00:20:48.702482 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
994 00:20:48.731498 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
995 00:20:48.798604 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
996 00:20:48.842010 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
997 00:20:48.958344 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
998 00:20:49.031403 <3>[ 65.863440] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
999 00:20:49.080808 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1000 00:20:49.151325 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1001 00:20:49.202490 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1002 00:20:49.232282 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1003 00:20:49.421284 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1004 00:20:49.488509 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1005 00:20:49.550320 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1006 00:20:49.579029 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1007 00:20:49.607239 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1008 00:20:49.766113 <3>[ 66.598244] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1009 00:20:49.888821 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1010 00:20:50.154408 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1011 00:20:50.210538 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1012 00:20:50.244575 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1013 00:20:50.333771 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1014 00:20:50.500259 <3>[ 67.332280] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1015 00:20:50.538764 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1016 00:20:50.662206
1017 00:20:50.665532 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
1018 00:20:50.666002
1019 00:20:50.973476 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sun Nov 3 23:10:46 UTC 2024 armv7l
1020 00:20:50.974473
1021 00:20:50.978989 The programs included with the Debian GNU/Linux system are free software;
1022 00:20:50.984541 the exact distribution terms for each program are described in the
1023 00:20:50.990127 individual files in /usr/share/doc/*/copyright.
1024 00:20:50.990663
1025 00:20:50.998100 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1026 00:20:50.998645 permitted by applicable law.
1027 00:20:51.243591 <3>[ 68.075579] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1028 00:20:51.976532 <3>[ 68.809577] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1029 00:20:51.985455 <3>[ 68.818956] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1030 00:20:55.978537 Unable to match end of the kernel message
1032 00:20:55.979487 Setting prompt string to ['/ #']
1033 00:20:55.979808 end: 2.4.4.1 login-action (duration 00:01:13) [common]
1035 00:20:55.980587 end: 2.4.4 auto-login-action (duration 00:01:14) [common]
1036 00:20:55.980904 start: 2.4.5 expect-shell-connection (timeout 00:02:25) [common]
1037 00:20:55.981145 Setting prompt string to ['/ #']
1038 00:20:55.981361 Forcing a shell prompt, looking for ['/ #']
1040 00:20:56.031915 / #
1041 00:20:56.033013 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1042 00:20:56.033400 Waiting using forced prompt support (timeout 00:02:30)
1043 00:20:56.037754
1044 00:20:56.044810 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1045 00:20:56.045177 start: 2.4.6 export-device-env (timeout 00:02:25) [common]
1046 00:20:56.045439 Sending with 10 millisecond of delay
1048 00:21:01.034244 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf'
1049 00:21:01.045170 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/931507/extract-nfsrootfs-rvcljpyf'
1050 00:21:01.046206 Sending with 10 millisecond of delay
1052 00:21:03.143944 / # export NFS_SERVER_IP='192.168.6.2'
1053 00:21:03.154921 export NFS_SERVER_IP='192.168.6.2'
1054 00:21:03.156053 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1055 00:21:03.156646 end: 2.4 uboot-commands (duration 00:02:42) [common]
1056 00:21:03.157228 end: 2 uboot-action (duration 00:02:42) [common]
1057 00:21:03.157786 start: 3 lava-test-retry (timeout 00:06:06) [common]
1058 00:21:03.158353 start: 3.1 lava-test-shell (timeout 00:06:06) [common]
1059 00:21:03.158816 Using namespace: common
1061 00:21:03.260051 / # #
1062 00:21:03.260817 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1063 00:21:03.265731 #
1064 00:21:03.272469 Using /lava-931507
1066 00:21:03.373639 / # export SHELL=/bin/bash
1067 00:21:03.379190 export SHELL=/bin/bash
1069 00:21:03.485898 / # . /lava-931507/environment
1070 00:21:03.491331 . /lava-931507/environment
1072 00:21:03.605004 / # /lava-931507/bin/lava-test-runner /lava-931507/0
1073 00:21:03.605781 Test shell timeout: 10s (minimum of the action and connection timeout)
1074 00:21:03.610693 /lava-931507/bin/lava-test-runner /lava-931507/0
1075 00:21:04.016051 + export TESTRUN_ID=0_timesync-off
1076 00:21:04.023128 + TESTRUN_ID=0_timesync-off
1077 00:21:04.023591 + cd /lava-931507/0/tests/0_timesync-off
1078 00:21:04.024039 ++ cat uuid
1079 00:21:04.041349 + UUID=931507_1.6.2.4.1
1080 00:21:04.041838 + set +x
1081 00:21:04.049917 <LAVA_SIGNAL_STARTRUN 0_timesync-off 931507_1.6.2.4.1>
1082 00:21:04.050359 + systemctl stop systemd-timesyncd
1083 00:21:04.051052 Received signal: <STARTRUN> 0_timesync-off 931507_1.6.2.4.1
1084 00:21:04.051481 Starting test lava.0_timesync-off (931507_1.6.2.4.1)
1085 00:21:04.052015 Skipping test definition patterns.
1086 00:21:04.347060 + set +x
1087 00:21:04.347657 <LAVA_SIGNAL_ENDRUN 0_timesync-off 931507_1.6.2.4.1>
1088 00:21:04.348396 Received signal: <ENDRUN> 0_timesync-off 931507_1.6.2.4.1
1089 00:21:04.348899 Ending use of test pattern.
1090 00:21:04.349312 Ending test lava.0_timesync-off (931507_1.6.2.4.1), duration 0.30
1092 00:21:04.560419 + export TESTRUN_ID=1_kselftest-dt
1093 00:21:04.568349 + TESTRUN_ID=1_kselftest-dt
1094 00:21:04.568823 + cd /lava-931507/0/tests/1_kselftest-dt
1095 00:21:04.569239 ++ cat uuid
1096 00:21:04.585547 + UUID=931507_1.6.2.4.5
1097 00:21:04.585998 + set +x
1098 00:21:04.591242 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 931507_1.6.2.4.5>
1099 00:21:04.591682 + cd ./automated/linux/kselftest/
1100 00:21:04.592423 Received signal: <STARTRUN> 1_kselftest-dt 931507_1.6.2.4.5
1101 00:21:04.592865 Starting test lava.1_kselftest-dt (931507_1.6.2.4.5)
1102 00:21:04.593358 Skipping test definition patterns.
1103 00:21:04.619418 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1104 00:21:04.724093 INFO: install_deps skipped
1105 00:21:05.317827 --2024-11-04 00:21:05-- http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1106 00:21:05.593268 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1107 00:21:05.735412 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1108 00:21:05.876136 HTTP request sent, awaiting response... 200 OK
1109 00:21:05.876655 Length: 2540708 (2.4M) [application/octet-stream]
1110 00:21:05.881495 Saving to: 'kselftest_armhf.tar.gz'
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1114 00:21:07.919153 2024-11-04 00:21:07 (1.45 MB/s) - 'kselftest_armhf.tar.gz' saved [2540708/2540708]
1115 00:21:07.919778
1116 00:21:19.156026 skiplist:
1117 00:21:19.156662 ========================================
1118 00:21:19.160691 ========================================
1119 00:21:19.255797 dt:test_unprobed_devices.sh
1120 00:21:19.288866 ============== Tests to run ===============
1121 00:21:19.298473 dt:test_unprobed_devices.sh
1122 00:21:19.302506 ===========End Tests to run ===============
1123 00:21:19.311048 shardfile-dt pass
1124 00:21:19.548314 <12>[ 96.386068] kselftest: Running tests in dt
1125 00:21:19.577409 TAP version 13
1126 00:21:19.602247 1..1
1127 00:21:19.658421 # timeout set to 45
1128 00:21:19.658958 # selftests: dt: test_unprobed_devices.sh
1129 00:21:20.599947 # TAP version 13
1130 00:21:46.207010 # 1..257
1131 00:21:46.406241 # ok 1 / # SKIP
1132 00:21:46.430335 # ok 2 /clk_mcasp0
1133 00:21:46.506539 # ok 3 /clk_mcasp0_fixed # SKIP
1134 00:21:46.579385 # ok 4 /cpus/cpu@0 # SKIP
1135 00:21:46.649125 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1136 00:21:46.675671 # ok 6 /fixedregulator0
1137 00:21:46.695492 # ok 7 /leds
1138 00:21:46.713356 # ok 8 /ocp
1139 00:21:46.738739 # ok 9 /ocp/interconnect@44c00000
1140 00:21:46.766725 # ok 10 /ocp/interconnect@44c00000/segment@0
1141 00:21:46.789532 # ok 11 /ocp/interconnect@44c00000/segment@100000
1142 00:21:46.810592 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1143 00:21:46.888678 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1144 00:21:46.905650 # ok 14 /ocp/interconnect@44c00000/segment@200000
1145 00:21:46.932027 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1146 00:21:47.039321 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1147 00:21:47.113008 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1148 00:21:47.188951 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1149 00:21:47.263466 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1150 00:21:47.337881 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1151 00:21:47.411133 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1152 00:21:47.485869 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1153 00:21:47.561116 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1154 00:21:47.633516 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1155 00:21:47.708120 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1156 00:21:47.780859 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1157 00:21:47.855691 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1158 00:21:47.929018 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1159 00:21:48.002899 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1160 00:21:48.081284 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1161 00:21:48.155597 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1162 00:21:48.230462 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1163 00:21:48.299648 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1164 00:21:48.372273 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1165 00:21:48.447962 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1166 00:21:48.520065 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1167 00:21:48.594034 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1168 00:21:48.667756 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1169 00:21:48.742066 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1170 00:21:48.820115 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1171 00:21:48.890640 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1172 00:21:48.964364 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1173 00:21:49.039007 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1174 00:21:49.113521 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1175 00:21:49.187959 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1176 00:21:49.262187 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1177 00:21:49.337425 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1178 00:21:49.410918 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1179 00:21:49.484729 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1180 00:21:49.563168 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1181 00:21:49.636498 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1182 00:21:49.707661 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1183 00:21:49.782252 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1184 00:21:49.858611 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1185 00:21:49.930490 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1186 00:21:50.004548 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1187 00:21:50.079397 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1188 00:21:50.152686 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1189 00:21:50.231215 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1190 00:21:50.308662 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1191 00:21:50.383939 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1192 00:21:50.462276 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1193 00:21:50.535947 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1194 00:21:50.610764 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1195 00:21:50.684398 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1196 00:21:50.756418 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1197 00:21:50.830053 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1198 00:21:50.902611 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1199 00:21:50.975817 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1200 00:21:51.051830 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1201 00:21:51.126349 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1202 00:21:51.199633 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1203 00:21:51.274463 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1204 00:21:51.348909 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1205 00:21:51.425369 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1206 00:21:51.496750 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1207 00:21:51.572104 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1208 00:21:51.646151 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1209 00:21:51.719907 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1210 00:21:51.793855 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1211 00:21:51.868182 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1212 00:21:51.942550 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1213 00:21:52.018926 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1214 00:21:52.089960 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1215 00:21:52.164072 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1216 00:21:52.238776 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1217 00:21:52.312179 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1218 00:21:52.386305 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1219 00:21:52.467078 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1220 00:21:52.538265 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1221 00:21:52.615590 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1222 00:21:52.687063 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1223 00:21:52.765586 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1224 00:21:52.836543 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1225 00:21:52.857970 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1226 00:21:52.881319 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1227 00:21:52.907050 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1228 00:21:52.933905 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1229 00:21:52.960419 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1230 00:21:52.983116 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1231 00:21:53.005880 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1232 00:21:53.028735 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1233 00:21:53.138613 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1234 00:21:53.163725 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1235 00:21:53.188182 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1236 00:21:53.214074 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1237 00:21:53.323676 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1238 00:21:53.400807 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1239 00:21:53.474004 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1240 00:21:53.552418 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1241 00:21:53.623149 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1242 00:21:53.698098 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1243 00:21:53.769722 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1244 00:21:53.851522 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1245 00:21:53.926302 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1246 00:21:53.997417 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1247 00:21:54.075752 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1248 00:21:54.146732 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1249 00:21:54.219791 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1250 00:21:54.295180 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1251 00:21:54.370313 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1252 00:21:54.444381 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1253 00:21:54.470899 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1254 00:21:54.543422 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1255 00:21:54.612343 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1256 00:21:54.689532 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1257 00:21:54.712860 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1258 00:21:54.782747 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1259 00:21:54.806391 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1260 00:21:54.883841 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1261 00:21:54.909981 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1262 00:21:54.929246 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1263 00:21:54.954902 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1264 00:21:54.978209 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1265 00:21:55.001061 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1266 00:21:55.030308 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1267 00:21:55.054982 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1268 00:21:55.129489 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1269 00:21:55.151200 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1270 00:21:55.175090 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1271 00:21:55.249416 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1272 00:21:55.322699 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1273 00:21:55.345130 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1274 00:21:55.448299 # not ok 144 /ocp/interconnect@47c00000
1275 00:21:55.526235 # not ok 145 /ocp/interconnect@47c00000/segment@0
1276 00:21:55.548480 # ok 146 /ocp/interconnect@48000000
1277 00:21:55.568068 # ok 147 /ocp/interconnect@48000000/segment@0
1278 00:21:55.594003 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1279 00:21:55.622229 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1280 00:21:55.641706 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1281 00:21:55.669909 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1282 00:21:55.691607 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1283 00:21:55.715964 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1284 00:21:55.742345 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1285 00:21:55.812976 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1286 00:21:55.886959 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1287 00:21:55.909332 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1288 00:21:55.934743 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1289 00:21:55.958512 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1290 00:21:55.987084 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1291 00:21:56.010945 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1292 00:21:56.033206 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1293 00:21:56.053719 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1294 00:21:56.078916 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1295 00:21:56.108069 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1296 00:21:56.128090 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1297 00:21:56.150941 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1298 00:21:56.180704 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1299 00:21:56.198793 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1300 00:21:56.228064 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1301 00:21:56.251538 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1302 00:21:56.275698 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1303 00:21:56.295474 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1304 00:21:56.321988 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1305 00:21:56.342395 # ok 175 /ocp/interconnect@48000000/segment@100000
1306 00:21:56.368484 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1307 00:21:56.397557 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1308 00:21:56.469189 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1309 00:21:56.544541 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1310 00:21:56.620530 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1311 00:21:56.696374 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1312 00:21:56.766171 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1313 00:21:56.840759 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1314 00:21:56.913607 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1315 00:21:56.990054 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1316 00:21:57.010044 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1317 00:21:57.038518 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1318 00:21:57.062697 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1319 00:21:57.084911 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1320 00:21:57.106493 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1321 00:21:57.133447 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1322 00:21:57.156213 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1323 00:21:57.183331 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1324 00:21:57.208940 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1325 00:21:57.232958 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1326 00:21:57.254850 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1327 00:21:57.276955 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1328 00:21:57.300108 # ok 198 /ocp/interconnect@48000000/segment@200000
1329 00:21:57.324441 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1330 00:21:57.400254 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1331 00:21:57.421404 # ok 201 /ocp/interconnect@48000000/segment@300000
1332 00:21:57.450742 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1333 00:21:57.472829 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1334 00:21:57.496203 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1335 00:21:57.519176 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1336 00:21:57.547760 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1337 00:21:57.571621 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1338 00:21:57.646919 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1339 00:21:57.661934 # ok 209 /ocp/interconnect@4a000000
1340 00:21:57.686564 # ok 210 /ocp/interconnect@4a000000/segment@0
1341 00:21:57.716547 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1342 00:21:57.737659 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1343 00:21:57.762904 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1344 00:21:57.785487 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1345 00:21:57.862699 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1346 00:21:57.971261 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1347 00:21:58.044880 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1348 00:21:58.148270 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1349 00:21:58.223731 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1350 00:21:58.296098 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1351 00:21:58.397788 # not ok 221 /ocp/interconnect@4b140000
1352 00:21:58.471363 # not ok 222 /ocp/interconnect@4b140000/segment@0
1353 00:21:58.549510 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1354 00:21:58.567600 # ok 224 /ocp/target-module@40300000
1355 00:21:58.590927 # ok 225 /ocp/target-module@40300000/sram@0
1356 00:21:58.670109 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1357 00:21:58.742567 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1358 00:21:58.764414 # ok 228 /ocp/target-module@47400000
1359 00:21:58.789805 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1360 00:21:58.810068 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1361 00:21:58.832581 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1362 00:21:58.859305 # ok 232 /ocp/target-module@47400000/usb@1400
1363 00:21:58.880488 # ok 233 /ocp/target-module@47400000/usb@1800
1364 00:21:58.900236 # ok 234 /ocp/target-module@47810000
1365 00:21:58.927533 # ok 235 /ocp/target-module@49000000
1366 00:21:58.950476 # ok 236 /ocp/target-module@49000000/dma@0
1367 00:21:58.969221 # ok 237 /ocp/target-module@49800000
1368 00:21:58.992857 # ok 238 /ocp/target-module@49800000/dma@0
1369 00:21:59.019207 # ok 239 /ocp/target-module@49900000
1370 00:21:59.039259 # ok 240 /ocp/target-module@49900000/dma@0
1371 00:21:59.064671 # ok 241 /ocp/target-module@49a00000
1372 00:21:59.084056 # ok 242 /ocp/target-module@49a00000/dma@0
1373 00:21:59.109878 # ok 243 /ocp/target-module@4c000000
1374 00:21:59.180837 # not ok 244 /ocp/target-module@4c000000/emif@0
1375 00:21:59.207917 # ok 245 /ocp/target-module@50000000
1376 00:21:59.224637 # ok 246 /ocp/target-module@53100000
1377 00:21:59.300086 # not ok 247 /ocp/target-module@53100000/sham@0
1378 00:21:59.326391 # ok 248 /ocp/target-module@53500000
1379 00:21:59.400013 # not ok 249 /ocp/target-module@53500000/aes@0
1380 00:21:59.417566 # ok 250 /ocp/target-module@56000000
1381 00:21:59.530475 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1382 00:21:59.597193 # ok 252 /opp-table # SKIP
1383 00:21:59.674111 # ok 253 /soc # SKIP
1384 00:21:59.695855 # ok 254 /sound
1385 00:21:59.713877 # ok 255 /target-module@4b000000
1386 00:21:59.745289 # ok 256 /target-module@4b000000/target-module@140000
1387 00:21:59.762299 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1388 00:21:59.770645 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1389 00:21:59.778966 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1390 00:22:01.948079 dt_test_unprobed_devices_sh_ skip
1391 00:22:01.953612 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1392 00:22:01.959076 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1393 00:22:01.959597 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1394 00:22:01.967568 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1395 00:22:01.968139 dt_test_unprobed_devices_sh_fixedregulator0 pass
1396 00:22:01.973267 dt_test_unprobed_devices_sh_leds pass
1397 00:22:01.978915 dt_test_unprobed_devices_sh_ocp pass
1398 00:22:01.982827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1399 00:22:01.988321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1400 00:22:01.993925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1401 00:22:02.003078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1402 00:22:02.008639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1403 00:22:02.019932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1404 00:22:02.025497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1405 00:22:02.036910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1406 00:22:02.042655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1407 00:22:02.053407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1408 00:22:02.064621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1409 00:22:02.075891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1410 00:22:02.081514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1411 00:22:02.092744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1412 00:22:02.103931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1413 00:22:02.115060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1414 00:22:02.126274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1415 00:22:02.131963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1416 00:22:02.143070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1417 00:22:02.154248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1418 00:22:02.165473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1419 00:22:02.171161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1420 00:22:02.182270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1421 00:22:02.193469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1422 00:22:02.204632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1423 00:22:02.210394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1424 00:22:02.221467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1425 00:22:02.232661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1426 00:22:02.243910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1427 00:22:02.255043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1428 00:22:02.266229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1429 00:22:02.271935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1430 00:22:02.283040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1431 00:22:02.294182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1432 00:22:02.305448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1433 00:22:02.316600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1434 00:22:02.327806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1435 00:22:02.338983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1436 00:22:02.350251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1437 00:22:02.361385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1438 00:22:02.372590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1439 00:22:02.383812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1440 00:22:02.394992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1441 00:22:02.406102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1442 00:22:02.417347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1443 00:22:02.428527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1444 00:22:02.439795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1445 00:22:02.450919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1446 00:22:02.462119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1447 00:22:02.473311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1448 00:22:02.484480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1449 00:22:02.495637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1450 00:22:02.506881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1451 00:22:02.518111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1452 00:22:02.529256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1453 00:22:02.540482 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1454 00:22:02.546172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1455 00:22:02.557281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1456 00:22:02.568427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1457 00:22:02.579581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1458 00:22:02.590762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1459 00:22:02.601968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1460 00:22:02.613153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1461 00:22:02.624375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1462 00:22:02.635582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1463 00:22:02.646773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1464 00:22:02.657975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1465 00:22:02.669204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1466 00:22:02.680370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1467 00:22:02.691538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1468 00:22:02.702809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1469 00:22:02.713939 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1470 00:22:02.725138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1471 00:22:02.736314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1472 00:22:02.747514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1473 00:22:02.753177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1474 00:22:02.764310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1475 00:22:02.775508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1476 00:22:02.786672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1477 00:22:02.797953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1478 00:22:02.809108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1479 00:22:02.820327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1480 00:22:02.831464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1481 00:22:02.842696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1482 00:22:02.853852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1483 00:22:02.865066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1484 00:22:02.876286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1485 00:22:02.881872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1486 00:22:02.893032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1487 00:22:02.904238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1488 00:22:02.909872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1489 00:22:02.921024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1490 00:22:02.932231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1491 00:22:02.937860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1492 00:22:02.949016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1493 00:22:02.954754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1494 00:22:02.965838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1495 00:22:02.977016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1496 00:22:02.988256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1497 00:22:02.999424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1498 00:22:03.010597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1499 00:22:03.021900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1500 00:22:03.032996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1501 00:22:03.044253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1502 00:22:03.055377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1503 00:22:03.066559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1504 00:22:03.083381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1505 00:22:03.094662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1506 00:22:03.105913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1507 00:22:03.116998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1508 00:22:03.128181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1509 00:22:03.144935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1510 00:22:03.156193 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1511 00:22:03.167342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1512 00:22:03.178527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1513 00:22:03.189750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1514 00:22:03.200938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1515 00:22:03.206551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1516 00:22:03.217747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1517 00:22:03.223344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1518 00:22:03.234466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1519 00:22:03.240212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1520 00:22:03.251306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1521 00:22:03.256948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1522 00:22:03.268096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1523 00:22:03.273724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1524 00:22:03.284884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1525 00:22:03.290552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1526 00:22:03.301733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1527 00:22:03.312987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1528 00:22:03.324183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1529 00:22:03.335296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1530 00:22:03.346501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1531 00:22:03.352152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1532 00:22:03.363301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1533 00:22:03.368933 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1534 00:22:03.374560 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1535 00:22:03.380106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1536 00:22:03.385762 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1537 00:22:03.391356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1538 00:22:03.402513 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1539 00:22:03.408161 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1540 00:22:03.419276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1541 00:22:03.424970 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1542 00:22:03.436107 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1543 00:22:03.441708 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1544 00:22:03.447309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1545 00:22:03.458461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1546 00:22:03.464112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1547 00:22:03.475231 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1548 00:22:03.480953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1549 00:22:03.492094 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1550 00:22:03.497709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1551 00:22:03.508805 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1552 00:22:03.514459 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1553 00:22:03.525598 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1554 00:22:03.531236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1555 00:22:03.542410 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1556 00:22:03.548067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1557 00:22:03.559200 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1558 00:22:03.564842 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1559 00:22:03.570429 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1560 00:22:03.581595 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1561 00:22:03.587220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1562 00:22:03.598324 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1563 00:22:03.604032 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1564 00:22:03.615189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1565 00:22:03.620849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1566 00:22:03.631976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1567 00:22:03.637623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1568 00:22:03.648860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1569 00:22:03.660018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1570 00:22:03.671175 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1571 00:22:03.682388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1572 00:22:03.693565 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1573 00:22:03.704879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1574 00:22:03.716018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1575 00:22:03.727139 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1576 00:22:03.732781 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1577 00:22:03.743951 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1578 00:22:03.749566 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1579 00:22:03.755145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1580 00:22:03.766367 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1581 00:22:03.777509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1582 00:22:03.783151 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1583 00:22:03.794260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1584 00:22:03.800026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1585 00:22:03.811082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1586 00:22:03.816757 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1587 00:22:03.822341 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1588 00:22:03.833469 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1589 00:22:03.839179 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1590 00:22:03.844713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1591 00:22:03.855867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1592 00:22:03.861551 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1593 00:22:03.872651 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1594 00:22:03.878301 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1595 00:22:03.889448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1596 00:22:03.895103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1597 00:22:03.906246 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1598 00:22:03.911915 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1599 00:22:03.917488 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1600 00:22:03.923075 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1601 00:22:03.934242 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1602 00:22:03.945373 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1603 00:22:03.951018 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1604 00:22:03.962178 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1605 00:22:03.967813 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1606 00:22:03.978961 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1607 00:22:03.990148 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1608 00:22:04.001363 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1609 00:22:04.007070 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1610 00:22:04.012696 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1611 00:22:04.018348 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1612 00:22:04.029457 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1613 00:22:04.035094 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1614 00:22:04.040691 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1615 00:22:04.046349 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1616 00:22:04.051908 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1617 00:22:04.057572 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1618 00:22:04.063108 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1619 00:22:04.074281 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1620 00:22:04.079907 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1621 00:22:04.085569 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1622 00:22:04.091135 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1623 00:22:04.096743 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1624 00:22:04.102347 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1625 00:22:04.107917 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1626 00:22:04.113536 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1627 00:22:04.119190 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1628 00:22:04.124712 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1629 00:22:04.130309 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1630 00:22:04.135945 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1631 00:22:04.141534 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1632 00:22:04.147133 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1633 00:22:04.152700 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1634 00:22:04.158367 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1635 00:22:04.163923 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1636 00:22:04.169542 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1637 00:22:04.175181 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1638 00:22:04.180799 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1639 00:22:04.186422 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1640 00:22:04.192057 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1641 00:22:04.197682 dt_test_unprobed_devices_sh_opp-table skip
1642 00:22:04.198133 dt_test_unprobed_devices_sh_soc skip
1643 00:22:04.203273 dt_test_unprobed_devices_sh_sound pass
1644 00:22:04.208931 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1645 00:22:04.214571 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1646 00:22:04.220218 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1647 00:22:04.225760 dt_test_unprobed_devices_sh fail
1648 00:22:04.231353 + ../../utils/send-to-lava.sh ./output/result.txt
1649 00:22:04.231819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1650 00:22:04.232723 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1652 00:22:04.250979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1653 00:22:04.251706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1655 00:22:04.346285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1656 00:22:04.347051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1658 00:22:04.434593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1659 00:22:04.435365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1661 00:22:04.522514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1662 00:22:04.523298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1664 00:22:04.618749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1665 00:22:04.619509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1667 00:22:04.711335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1668 00:22:04.712098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1670 00:22:04.798228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1671 00:22:04.798969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1673 00:22:04.887084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1674 00:22:04.887825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1676 00:22:04.980840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1677 00:22:04.981591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1679 00:22:05.071360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1680 00:22:05.072115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1682 00:22:05.161235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1683 00:22:05.161998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1685 00:22:05.258220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1686 00:22:05.258978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1688 00:22:05.348043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1689 00:22:05.348824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1691 00:22:05.440782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1692 00:22:05.441532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1694 00:22:05.530131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1695 00:22:05.530889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1697 00:22:05.618610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1698 00:22:05.619367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1700 00:22:05.714923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1701 00:22:05.715675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1703 00:22:05.804210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1704 00:22:05.804967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1706 00:22:05.900317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1707 00:22:05.901084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1709 00:22:05.996481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1710 00:22:05.997257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1712 00:22:06.092952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1713 00:22:06.093703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1715 00:22:06.187705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1716 00:22:06.188500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1718 00:22:06.277159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1719 00:22:06.277957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1721 00:22:06.366778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1722 00:22:06.367536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1724 00:22:06.462346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1725 00:22:06.463116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1727 00:22:06.560606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1728 00:22:06.561387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1730 00:22:06.658511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1731 00:22:06.659290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1733 00:22:06.753700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1734 00:22:06.754463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1736 00:22:06.847876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1737 00:22:06.848665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1739 00:22:06.936093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1740 00:22:06.936848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1742 00:22:07.028159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1743 00:22:07.028927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1745 00:22:07.122512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1746 00:22:07.123338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1748 00:22:07.215506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1749 00:22:07.216313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1751 00:22:07.310866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1752 00:22:07.311667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1754 00:22:07.409099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1755 00:22:07.409987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1757 00:22:07.504558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1758 00:22:07.505366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1760 00:22:07.593966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1761 00:22:07.594726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1763 00:22:07.686244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1764 00:22:07.687010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1766 00:22:07.781226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1767 00:22:07.781987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1769 00:22:07.878136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1770 00:22:07.878911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1772 00:22:07.972904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1773 00:22:07.973660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1775 00:22:08.063637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1776 00:22:08.064449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1778 00:22:08.157915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1779 00:22:08.158669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1781 00:22:08.252721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1782 00:22:08.253466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1784 00:22:08.341995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1785 00:22:08.342732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1787 00:22:08.436748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1788 00:22:08.437496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1790 00:22:08.527700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1791 00:22:08.528481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1793 00:22:08.623059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1794 00:22:08.623798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1796 00:22:08.718792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1797 00:22:08.719620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1799 00:22:08.814055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1800 00:22:08.814843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1802 00:22:08.907857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1803 00:22:08.908709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1805 00:22:08.999062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1806 00:22:08.999861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1808 00:22:09.089047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1809 00:22:09.089855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1811 00:22:09.186469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1812 00:22:09.187255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1814 00:22:09.280902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1815 00:22:09.281777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1817 00:22:09.377170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1818 00:22:09.377959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1820 00:22:09.471589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1821 00:22:09.472575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1823 00:22:09.559897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1824 00:22:09.560828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1826 00:22:09.658634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1827 00:22:09.659501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1829 00:22:09.754747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1830 00:22:09.755605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1832 00:22:09.844025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1833 00:22:09.844843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1835 00:22:09.938660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1836 00:22:09.939483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1838 00:22:10.027513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1839 00:22:10.028337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1841 00:22:10.117143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1842 00:22:10.117950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1844 00:22:10.213996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1845 00:22:10.214807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1847 00:22:10.305298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1848 00:22:10.306110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1850 00:22:10.401452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1851 00:22:10.402245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1853 00:22:10.490420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1854 00:22:10.491265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1856 00:22:10.584619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1857 00:22:10.585506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1859 00:22:10.676304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1860 00:22:10.677251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1862 00:22:10.771778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1863 00:22:10.772797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1865 00:22:10.866729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1866 00:22:10.867717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1868 00:22:10.962470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1869 00:22:10.963309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1871 00:22:11.052085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1872 00:22:11.052901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1874 00:22:11.147949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1875 00:22:11.148767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1877 00:22:11.237995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1878 00:22:11.238791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1880 00:22:11.333713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1881 00:22:11.334523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1883 00:22:11.422898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1884 00:22:11.423716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1886 00:22:11.518875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1887 00:22:11.519672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1889 00:22:11.608571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1890 00:22:11.609363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1892 00:22:11.704526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1893 00:22:11.705313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1895 00:22:11.794740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1896 00:22:11.795502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1898 00:22:11.883340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1899 00:22:11.884103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1901 00:22:11.977259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1902 00:22:11.978048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1904 00:22:12.067072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1905 00:22:12.067946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1907 00:22:12.157931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1908 00:22:12.158776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1910 00:22:12.254930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1911 00:22:12.255729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1913 00:22:12.351749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1914 00:22:12.352527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1916 00:22:12.448771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1917 00:22:12.449576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1919 00:22:12.539779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1920 00:22:12.540612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1922 00:22:12.627153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1923 00:22:12.627925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1925 00:22:12.726002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1926 00:22:12.726751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1928 00:22:12.819755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1929 00:22:12.820584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1931 00:22:12.915872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1932 00:22:12.916745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1934 00:22:13.015646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1935 00:22:13.016626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1937 00:22:13.110834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1938 00:22:13.111819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1940 00:22:13.228548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1941 00:22:13.229483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1943 00:22:13.341975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1944 00:22:13.342809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1946 00:22:13.434450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1947 00:22:13.435825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1949 00:22:13.530964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1950 00:22:13.532215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1952 00:22:13.625163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1953 00:22:13.626493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1955 00:22:13.720242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1956 00:22:13.721837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1958 00:22:13.812516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1959 00:22:13.813389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1961 00:22:13.903966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1962 00:22:13.905024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1964 00:22:13.993577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1965 00:22:13.994851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1967 00:22:14.082264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1968 00:22:14.083535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1970 00:22:14.170670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1971 00:22:14.172102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1973 00:22:14.266987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1974 00:22:14.267881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1976 00:22:14.361124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1977 00:22:14.362034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1979 00:22:14.478573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1980 00:22:14.479417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1982 00:22:14.584826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1983 00:22:14.585656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1985 00:22:14.676156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1986 00:22:14.676975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1988 00:22:14.764610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1989 00:22:14.765424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1991 00:22:14.861192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1992 00:22:14.862016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1994 00:22:14.957385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1995 00:22:14.958197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1997 00:22:15.053167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1998 00:22:15.053988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2000 00:22:15.148272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2001 00:22:15.149078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2003 00:22:15.237587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2004 00:22:15.238375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2006 00:22:15.327087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2007 00:22:15.327873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2009 00:22:15.422845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2011 00:22:15.425947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2012 00:22:15.517447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2014 00:22:15.520211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2015 00:22:15.607606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2017 00:22:15.610339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2018 00:22:15.698615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2019 00:22:15.699488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2021 00:22:15.793065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2022 00:22:15.794115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2024 00:22:15.879327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2025 00:22:15.880233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2027 00:22:15.969414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2028 00:22:15.970283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2030 00:22:16.063462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2031 00:22:16.064319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2033 00:22:16.154488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2034 00:22:16.155364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2036 00:22:16.248813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2037 00:22:16.249689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2039 00:22:16.338954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2040 00:22:16.339819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2042 00:22:16.426786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2043 00:22:16.427667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2045 00:22:16.522384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2046 00:22:16.523242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2048 00:22:16.617071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2049 00:22:16.617921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2051 00:22:16.706403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2052 00:22:16.707432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2054 00:22:16.795893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2055 00:22:16.796728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2057 00:22:16.891353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2058 00:22:16.892193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2060 00:22:16.989953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2061 00:22:16.990797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2063 00:22:17.080983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2064 00:22:17.081846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2066 00:22:17.167935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2067 00:22:17.168796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2069 00:22:17.262991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2070 00:22:17.263800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2072 00:22:17.353785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2073 00:22:17.354677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2075 00:22:17.448277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2076 00:22:17.449157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2078 00:22:17.536374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2079 00:22:17.537223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2081 00:22:17.623091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2082 00:22:17.623957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2084 00:22:17.721365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2085 00:22:17.722205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2087 00:22:17.815431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2088 00:22:17.816333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2090 00:22:17.913950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2091 00:22:17.914800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2093 00:22:18.011218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2094 00:22:18.012129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2096 00:22:18.107150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2097 00:22:18.108455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2099 00:22:18.197016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2100 00:22:18.198215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2102 00:22:18.291444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2103 00:22:18.292734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2105 00:22:18.382141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2106 00:22:18.382939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2108 00:22:18.480145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2109 00:22:18.480897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2111 00:22:18.570350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2112 00:22:18.571401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2114 00:22:18.683363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2115 00:22:18.684339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2117 00:22:18.784703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2118 00:22:18.785537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2120 00:22:18.878764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2121 00:22:18.879624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2123 00:22:18.969287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2124 00:22:18.970058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2126 00:22:19.065146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2127 00:22:19.065964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2129 00:22:19.154758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2130 00:22:19.155528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2132 00:22:19.244217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2133 00:22:19.244996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2135 00:22:19.342235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2136 00:22:19.343038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2138 00:22:19.435224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2139 00:22:19.436030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2141 00:22:19.526194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2142 00:22:19.526992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2144 00:22:19.616102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2145 00:22:19.616868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2147 00:22:19.712953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2148 00:22:19.713732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2150 00:22:19.808232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2151 00:22:19.809012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2153 00:22:19.898419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2154 00:22:19.899196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2156 00:22:19.992637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2157 00:22:19.993408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2159 00:22:20.083283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2160 00:22:20.084095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2162 00:22:20.177025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2163 00:22:20.177810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2165 00:22:20.273239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2166 00:22:20.274027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2168 00:22:20.368894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2169 00:22:20.369678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2171 00:22:20.459536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2172 00:22:20.460341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2174 00:22:20.552061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2175 00:22:20.552836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2177 00:22:20.643693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2178 00:22:20.644507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2180 00:22:20.742114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2181 00:22:20.742908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2183 00:22:20.838377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2184 00:22:20.839192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2186 00:22:20.928708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2187 00:22:20.929508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2189 00:22:21.016704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2190 00:22:21.017565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2192 00:22:21.115065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2193 00:22:21.115888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2195 00:22:21.209197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2196 00:22:21.210009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2198 00:22:21.307106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2199 00:22:21.307911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2201 00:22:21.400722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2202 00:22:21.401550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2204 00:22:21.497133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2205 00:22:21.497944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2207 00:22:21.583392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2208 00:22:21.584202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2210 00:22:21.679444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2211 00:22:21.680279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2213 00:22:21.775108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2214 00:22:21.775907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2216 00:22:21.871207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2217 00:22:21.872049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2219 00:22:21.959596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2220 00:22:21.960407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2222 00:22:22.055344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2223 00:22:22.056152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2225 00:22:22.143884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2226 00:22:22.144746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2228 00:22:22.240390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2229 00:22:22.241241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2231 00:22:22.329230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2232 00:22:22.330004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2234 00:22:22.419236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2235 00:22:22.420081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2237 00:22:22.514079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2238 00:22:22.514873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2240 00:22:22.603952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2241 00:22:22.604791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2243 00:22:22.696448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2244 00:22:22.697239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2246 00:22:22.793223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2247 00:22:22.794021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2249 00:22:22.892986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2250 00:22:22.893792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2252 00:22:22.987795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2253 00:22:22.988635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2255 00:22:23.084181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2256 00:22:23.084983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2258 00:22:23.180703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2259 00:22:23.181494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2261 00:22:23.271337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2262 00:22:23.272145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2264 00:22:23.366259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2265 00:22:23.367062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2267 00:22:23.455015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2268 00:22:23.455810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2270 00:22:23.553071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2271 00:22:23.553875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2273 00:22:23.647953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2274 00:22:23.648796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2276 00:22:23.734206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2277 00:22:23.734997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2279 00:22:23.824274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2280 00:22:23.825085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2282 00:22:23.920532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2283 00:22:23.921349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2285 00:22:24.024250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2286 00:22:24.025161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2288 00:22:24.122018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2289 00:22:24.123048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2291 00:22:24.214011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2292 00:22:24.214831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2294 00:22:24.304643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2295 00:22:24.305439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2297 00:22:24.402238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2298 00:22:24.403015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2300 00:22:24.499909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2301 00:22:24.500729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2303 00:22:24.588699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2304 00:22:24.589811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2306 00:22:24.677644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2307 00:22:24.678403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2309 00:22:24.773567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2310 00:22:24.774363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2312 00:22:24.864117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2313 00:22:24.864898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2315 00:22:24.955045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2316 00:22:24.955847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2318 00:22:25.043871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2319 00:22:25.044732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2321 00:22:25.137719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2322 00:22:25.138500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2324 00:22:25.233463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2325 00:22:25.234260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2327 00:22:25.324276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2328 00:22:25.325058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2330 00:22:25.413052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2332 00:22:25.415122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2333 00:22:25.509808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2334 00:22:25.510657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2336 00:22:25.606937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2337 00:22:25.607745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2339 00:22:25.696189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2340 00:22:25.696973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2342 00:22:25.792019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2343 00:22:25.792854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2345 00:22:25.881018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2346 00:22:25.881833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2348 00:22:25.977783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2349 00:22:25.978602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2351 00:22:26.066906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2352 00:22:26.067713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2354 00:22:26.161336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2355 00:22:26.162125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2357 00:22:26.252662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2358 00:22:26.253459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2360 00:22:26.346832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2361 00:22:26.347621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2363 00:22:26.436521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2364 00:22:26.437302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2366 00:22:26.527072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2367 00:22:26.527894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2369 00:22:26.621872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2370 00:22:26.622663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2372 00:22:26.712616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2373 00:22:26.713413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2375 00:22:26.808257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2376 00:22:26.809111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2378 00:22:26.896840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2379 00:22:26.897716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2381 00:22:26.991861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2382 00:22:26.992754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2384 00:22:27.080916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2385 00:22:27.081799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2387 00:22:27.177513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2388 00:22:27.178406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2390 00:22:27.271505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2391 00:22:27.272376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2393 00:22:27.365231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2394 00:22:27.365985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2396 00:22:27.461421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2397 00:22:27.462510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2399 00:22:27.555241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2400 00:22:27.556532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2402 00:22:27.650292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2403 00:22:27.651442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2405 00:22:27.738103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2406 00:22:27.739194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2408 00:22:27.826669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2409 00:22:27.827751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2411 00:22:27.921044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2412 00:22:27.922140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2414 00:22:28.011512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2415 00:22:28.012731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2417 00:22:28.103554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2418 00:22:28.104773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2420 00:22:28.199914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2421 00:22:28.201148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2423 00:22:28.291287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2424 00:22:28.292206 + set +x
2425 00:22:28.292972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2427 00:22:28.300878 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 931507_1.6.2.4.5>
2428 00:22:28.301355 <LAVA_TEST_RUNNER EXIT>
2429 00:22:28.302070 Received signal: <ENDRUN> 1_kselftest-dt 931507_1.6.2.4.5
2430 00:22:28.302578 Ending use of test pattern.
2431 00:22:28.303052 Ending test lava.1_kselftest-dt (931507_1.6.2.4.5), duration 83.71
2433 00:22:28.304774 ok: lava_test_shell seems to have completed
2434 00:22:28.318552 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2435 00:22:28.320645 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2436 00:22:28.321282 end: 3 lava-test-retry (duration 00:01:25) [common]
2437 00:22:28.321977 start: 4 finalize (timeout 00:04:41) [common]
2438 00:22:28.322605 start: 4.1 power-off (timeout 00:00:30) [common]
2439 00:22:28.323753 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2440 00:22:28.359641 >> OK - accepted request
2441 00:22:28.362307 Returned 0 in 0 seconds
2442 00:22:28.464257 end: 4.1 power-off (duration 00:00:00) [common]
2444 00:22:28.467005 start: 4.2 read-feedback (timeout 00:04:41) [common]
2445 00:22:28.468969 Listened to connection for namespace 'common' for up to 1s
2446 00:22:29.469590 Finalising connection for namespace 'common'
2447 00:22:29.470784 Disconnecting from shell: Finalise
2448 00:22:29.471703 / #
2449 00:22:29.573317 end: 4.2 read-feedback (duration 00:00:01) [common]
2450 00:22:29.574125 end: 4 finalize (duration 00:00:01) [common]
2451 00:22:29.574926 Cleaning after the job
2452 00:22:29.575599 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/ramdisk
2453 00:22:29.586404 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/kernel
2454 00:22:29.594596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/dtb
2455 00:22:29.595949 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/nfsrootfs
2456 00:22:29.769605 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931507/tftp-deploy-wp8lfxf2/modules
2457 00:22:29.781405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/931507
2458 00:22:33.173375 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/931507
2459 00:22:33.174091 Job finished correctly