Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:25:45.815396 lava-dispatcher, installed at version: 2023.08
2 00:25:45.815701 start: 0 validate
3 00:25:45.815896 Start time: 2024-11-04 00:25:45.815885+00:00 (UTC)
4 00:25:45.816124 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 00:25:46.471639 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
6 00:25:46.586885 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
7 00:25:46.700898 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 00:25:46.815079 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
9 00:25:46.934302 validate duration: 1.12
11 00:25:46.935083 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 00:25:46.935425 start: 1.1 download-retry (timeout 00:10:00) [common]
13 00:25:46.935736 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 00:25:46.936206 Not decompressing ramdisk as can be used compressed.
15 00:25:46.936506 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 00:25:46.936762 saving as /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/ramdisk/initrd.cpio.gz
17 00:25:46.937007 total size: 4775763 (4 MB)
18 00:25:47.163881 progress 0 % (0 MB)
19 00:25:47.502232 progress 5 % (0 MB)
20 00:25:47.613928 progress 10 % (0 MB)
21 00:25:47.638863 progress 15 % (0 MB)
22 00:25:47.951941 progress 20 % (0 MB)
23 00:25:47.956755 progress 25 % (1 MB)
24 00:25:47.961135 progress 30 % (1 MB)
25 00:25:47.963448 progress 35 % (1 MB)
26 00:25:47.972257 progress 40 % (1 MB)
27 00:25:48.061819 progress 45 % (2 MB)
28 00:25:48.194064 progress 50 % (2 MB)
29 00:25:48.198759 progress 55 % (2 MB)
30 00:25:48.202184 progress 60 % (2 MB)
31 00:25:48.291651 progress 65 % (2 MB)
32 00:25:48.322516 progress 70 % (3 MB)
33 00:25:48.416274 progress 75 % (3 MB)
34 00:25:48.508036 progress 80 % (3 MB)
35 00:25:48.533748 progress 85 % (3 MB)
36 00:25:48.629434 progress 90 % (4 MB)
37 00:25:48.654010 progress 95 % (4 MB)
38 00:25:48.745525 progress 100 % (4 MB)
39 00:25:48.746311 4 MB downloaded in 1.81 s (2.52 MB/s)
40 00:25:48.746797 end: 1.1.1 http-download (duration 00:00:02) [common]
42 00:25:48.747637 end: 1.1 download-retry (duration 00:00:02) [common]
43 00:25:48.747937 start: 1.2 download-retry (timeout 00:09:58) [common]
44 00:25:48.748225 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 00:25:48.748636 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kernel/zImage
46 00:25:48.748902 saving as /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/kernel/zImage
47 00:25:48.749123 total size: 12050944 (11 MB)
48 00:25:48.749343 No compression specified
49 00:25:48.865500 progress 0 % (0 MB)
50 00:25:49.201814 progress 5 % (0 MB)
51 00:25:49.428296 progress 10 % (1 MB)
52 00:25:49.653652 progress 15 % (1 MB)
53 00:25:49.872996 progress 20 % (2 MB)
54 00:25:50.012659 progress 25 % (2 MB)
55 00:25:50.234499 progress 30 % (3 MB)
56 00:25:50.453228 progress 35 % (4 MB)
57 00:25:50.672559 progress 40 % (4 MB)
58 00:25:50.887631 progress 45 % (5 MB)
59 00:25:51.023731 progress 50 % (5 MB)
60 00:25:51.240660 progress 55 % (6 MB)
61 00:25:51.454916 progress 60 % (6 MB)
62 00:25:51.673447 progress 65 % (7 MB)
63 00:25:51.809060 progress 70 % (8 MB)
64 00:25:52.021347 progress 75 % (8 MB)
65 00:25:52.238615 progress 80 % (9 MB)
66 00:25:52.450835 progress 85 % (9 MB)
67 00:25:52.585588 progress 90 % (10 MB)
68 00:25:52.801735 progress 95 % (10 MB)
69 00:25:53.012160 progress 100 % (11 MB)
70 00:25:53.013005 11 MB downloaded in 4.26 s (2.70 MB/s)
71 00:25:53.013456 end: 1.2.1 http-download (duration 00:00:04) [common]
73 00:25:53.014261 end: 1.2 download-retry (duration 00:00:04) [common]
74 00:25:53.014557 start: 1.3 download-retry (timeout 00:09:54) [common]
75 00:25:53.014840 start: 1.3.1 http-download (timeout 00:09:54) [common]
76 00:25:53.015247 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
77 00:25:53.015476 saving as /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/dtb/am335x-boneblack.dtb
78 00:25:53.015692 total size: 70568 (0 MB)
79 00:25:53.015907 No compression specified
80 00:25:53.132071 progress 46 % (0 MB)
81 00:25:53.134901 progress 92 % (0 MB)
82 00:25:53.135788 progress 100 % (0 MB)
83 00:25:53.136154 0 MB downloaded in 0.12 s (0.56 MB/s)
84 00:25:53.136536 end: 1.3.1 http-download (duration 00:00:00) [common]
86 00:25:53.137312 end: 1.3 download-retry (duration 00:00:00) [common]
87 00:25:53.137579 start: 1.4 download-retry (timeout 00:09:54) [common]
88 00:25:53.137848 start: 1.4.1 http-download (timeout 00:09:54) [common]
89 00:25:53.138185 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 00:25:53.138398 saving as /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/nfsrootfs/full.rootfs.tar
91 00:25:53.138598 total size: 117747780 (112 MB)
92 00:25:53.138804 Using unxz to decompress xz
93 00:25:53.255215 progress 0 % (0 MB)
94 00:25:55.515688 progress 5 % (5 MB)
95 00:25:57.504277 progress 10 % (11 MB)
96 00:25:59.320402 progress 15 % (16 MB)
97 00:26:01.197257 progress 20 % (22 MB)
98 00:26:02.984450 progress 25 % (28 MB)
99 00:26:04.572393 progress 30 % (33 MB)
100 00:26:05.927653 progress 35 % (39 MB)
101 00:26:07.125508 progress 40 % (44 MB)
102 00:26:08.062596 progress 45 % (50 MB)
103 00:26:08.911635 progress 50 % (56 MB)
104 00:26:09.613903 progress 55 % (61 MB)
105 00:26:10.254630 progress 60 % (67 MB)
106 00:26:10.815664 progress 65 % (73 MB)
107 00:26:11.329998 progress 70 % (78 MB)
108 00:26:11.927994 progress 75 % (84 MB)
109 00:26:12.485982 progress 80 % (89 MB)
110 00:26:13.067881 progress 85 % (95 MB)
111 00:26:13.621508 progress 90 % (101 MB)
112 00:26:14.148461 progress 95 % (106 MB)
113 00:26:14.661715 progress 100 % (112 MB)
114 00:26:14.665435 112 MB downloaded in 21.53 s (5.22 MB/s)
115 00:26:14.665766 end: 1.4.1 http-download (duration 00:00:22) [common]
117 00:26:14.666344 end: 1.4 download-retry (duration 00:00:22) [common]
118 00:26:14.666546 start: 1.5 download-retry (timeout 00:09:32) [common]
119 00:26:14.666735 start: 1.5.1 http-download (timeout 00:09:32) [common]
120 00:26:14.667021 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/modules.tar.xz
121 00:26:14.667173 saving as /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/modules/modules.tar
122 00:26:14.667315 total size: 6912416 (6 MB)
123 00:26:14.667459 Using unxz to decompress xz
124 00:26:14.783413 progress 0 % (0 MB)
125 00:26:15.014460 progress 5 % (0 MB)
126 00:26:15.235413 progress 10 % (0 MB)
127 00:26:15.265208 progress 15 % (1 MB)
128 00:26:15.343947 progress 20 % (1 MB)
129 00:26:15.374599 progress 25 % (1 MB)
130 00:26:15.490678 progress 30 % (2 MB)
131 00:26:15.581232 progress 35 % (2 MB)
132 00:26:15.608644 progress 40 % (2 MB)
133 00:26:15.633016 progress 45 % (2 MB)
134 00:26:15.809654 progress 50 % (3 MB)
135 00:26:15.836486 progress 55 % (3 MB)
136 00:26:15.862467 progress 60 % (3 MB)
137 00:26:15.929306 progress 65 % (4 MB)
138 00:26:16.026725 progress 70 % (4 MB)
139 00:26:16.121973 progress 75 % (4 MB)
140 00:26:16.165013 progress 80 % (5 MB)
141 00:26:16.261645 progress 85 % (5 MB)
142 00:26:16.360323 progress 90 % (5 MB)
143 00:26:16.402314 progress 95 % (6 MB)
144 00:26:16.495560 progress 100 % (6 MB)
145 00:26:16.499034 6 MB downloaded in 1.83 s (3.60 MB/s)
146 00:26:16.499412 end: 1.5.1 http-download (duration 00:00:02) [common]
148 00:26:16.500035 end: 1.5 download-retry (duration 00:00:02) [common]
149 00:26:16.500256 start: 1.6 prepare-tftp-overlay (timeout 00:09:30) [common]
150 00:26:16.500477 start: 1.6.1 extract-nfsrootfs (timeout 00:09:30) [common]
151 00:26:22.113507 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr
152 00:26:22.113812 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 00:26:22.113965 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
154 00:26:22.114269 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi
155 00:26:22.114458 makedir: /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin
156 00:26:22.114604 makedir: /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/tests
157 00:26:22.114755 makedir: /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/results
158 00:26:22.114917 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-add-keys
159 00:26:22.115141 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-add-sources
160 00:26:22.115321 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-background-process-start
161 00:26:22.115508 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-background-process-stop
162 00:26:22.115712 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-common-functions
163 00:26:22.115896 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-echo-ipv4
164 00:26:22.116080 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-install-packages
165 00:26:22.116259 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-installed-packages
166 00:26:22.116431 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-os-build
167 00:26:22.116605 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-probe-channel
168 00:26:22.116808 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-probe-ip
169 00:26:22.116984 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-target-ip
170 00:26:22.117157 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-target-mac
171 00:26:22.117328 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-target-storage
172 00:26:22.117503 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-case
173 00:26:22.117675 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-event
174 00:26:22.117844 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-feedback
175 00:26:22.118015 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-raise
176 00:26:22.118185 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-reference
177 00:26:22.118355 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-runner
178 00:26:22.118526 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-set
179 00:26:22.118697 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-test-shell
180 00:26:22.118869 Updating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-add-keys (debian)
181 00:26:22.119092 Updating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-add-sources (debian)
182 00:26:22.119286 Updating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-install-packages (debian)
183 00:26:22.119481 Updating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-installed-packages (debian)
184 00:26:22.119674 Updating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/bin/lava-os-build (debian)
185 00:26:22.119845 Creating /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/environment
186 00:26:22.119976 LAVA metadata
187 00:26:22.120077 - LAVA_JOB_ID=1215884
188 00:26:22.120175 - LAVA_DISPATCHER_IP=192.168.11.5
189 00:26:22.120320 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
190 00:26:22.120665 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 00:26:22.120832 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
192 00:26:22.120928 skipped lava-vland-overlay
193 00:26:22.121044 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 00:26:22.121165 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
195 00:26:22.121264 skipped lava-multinode-overlay
196 00:26:22.121378 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 00:26:22.121495 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
198 00:26:22.121598 Loading test definitions
199 00:26:22.121722 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
200 00:26:22.121824 Using /lava-1215884 at stage 0
201 00:26:22.122241 uuid=1215884_1.6.2.4.1 testdef=None
202 00:26:22.122365 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 00:26:22.122485 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
204 00:26:22.123098 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 00:26:22.123441 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
207 00:26:22.124267 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 00:26:22.124629 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
210 00:26:22.125590 runner path: /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/0/tests/0_timesync-off test_uuid 1215884_1.6.2.4.1
211 00:26:22.125803 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 00:26:22.126161 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
214 00:26:22.126262 Using /lava-1215884 at stage 0
215 00:26:22.126402 Fetching tests from https://github.com/kernelci/test-definitions.git
216 00:26:22.126508 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/0/tests/1_kselftest-dt'
217 00:26:27.058472 Running '/usr/bin/git checkout kernelci.org
218 00:26:27.179830 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 00:26:27.180798 uuid=1215884_1.6.2.4.5 testdef=None
220 00:26:27.181040 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 00:26:27.181586 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
223 00:26:27.183390 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 00:26:27.183966 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
226 00:26:27.209762 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 00:26:27.210555 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
229 00:26:27.252521 runner path: /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/0/tests/1_kselftest-dt test_uuid 1215884_1.6.2.4.5
230 00:26:27.252826 BOARD='beaglebone-black'
231 00:26:27.253052 BRANCH='mainline'
232 00:26:27.253267 SKIPFILE='/dev/null'
233 00:26:27.253480 SKIP_INSTALL='True'
234 00:26:27.253688 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
235 00:26:27.253900 TST_CASENAME=''
236 00:26:27.254106 TST_CMDFILES='dt'
237 00:26:27.254579 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 00:26:27.255317 Creating lava-test-runner.conf files
240 00:26:27.255530 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1215884/lava-overlay-f3u1sudi/lava-1215884/0 for stage 0
241 00:26:27.255824 - 0_timesync-off
242 00:26:27.256050 - 1_kselftest-dt
243 00:26:27.256369 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 00:26:27.256649 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
245 00:26:35.748137 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 00:26:35.748341 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
247 00:26:35.748487 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 00:26:35.748642 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 00:26:35.748813 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
250 00:26:35.872596 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 00:26:35.872920 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
252 00:26:35.873095 extracting modules file /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr
253 00:26:36.183718 extracting modules file /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1215884/extract-overlay-ramdisk-x6pqt05j/ramdisk
254 00:26:36.494507 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 00:26:36.494724 start: 1.6.5 apply-overlay-tftp (timeout 00:09:10) [common]
256 00:26:36.494860 [common] Applying overlay to NFS
257 00:26:36.494967 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1215884/compress-overlay-mec08kxd/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr
258 00:26:37.682822 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 00:26:37.683037 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
260 00:26:37.683164 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
261 00:26:37.683293 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 00:26:37.683411 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 00:26:37.683532 start: 1.6.7 configure-preseed-file (timeout 00:09:09) [common]
264 00:26:37.683648 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 00:26:37.683765 start: 1.6.8 compress-ramdisk (timeout 00:09:09) [common]
266 00:26:37.683866 Building ramdisk /var/lib/lava/dispatcher/tmp/1215884/extract-overlay-ramdisk-x6pqt05j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1215884/extract-overlay-ramdisk-x6pqt05j/ramdisk
267 00:26:38.001173 >> 79012 blocks
268 00:26:40.134063 Adding RAMdisk u-boot header.
269 00:26:40.134340 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1215884/extract-overlay-ramdisk-x6pqt05j/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1215884/extract-overlay-ramdisk-x6pqt05j/ramdisk.cpio.gz.uboot
270 00:26:40.290501 output: Image Name:
271 00:26:40.290851 output: Created: Mon Nov 4 00:26:40 2024
272 00:26:40.291068 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 00:26:40.291278 output: Data Size: 15350258 Bytes = 14990.49 KiB = 14.64 MiB
274 00:26:40.291481 output: Load Address: 00000000
275 00:26:40.291679 output: Entry Point: 00000000
276 00:26:40.291876 output:
277 00:26:40.292196 rename /var/lib/lava/dispatcher/tmp/1215884/extract-overlay-ramdisk-x6pqt05j/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot
278 00:26:40.292530 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 00:26:40.292856 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 00:26:40.293145 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:07) [common]
281 00:26:40.293371 No LXC device requested
282 00:26:40.293640 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 00:26:40.293919 start: 1.8 deploy-device-env (timeout 00:09:07) [common]
284 00:26:40.294187 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 00:26:40.294402 Checking files for TFTP limit of 4294967296 bytes.
286 00:26:40.295724 end: 1 tftp-deploy (duration 00:00:53) [common]
287 00:26:40.296017 start: 2 uboot-action (timeout 00:05:00) [common]
288 00:26:40.296301 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 00:26:40.296570 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 00:26:40.296870 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 00:26:40.297280 substitutions:
292 00:26:40.297502 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 00:26:40.297718 - {DTB_ADDR}: 0x88000000
294 00:26:40.297927 - {DTB}: 1215884/tftp-deploy-57fxedvl/dtb/am335x-boneblack.dtb
295 00:26:40.298139 - {INITRD}: 1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot
296 00:26:40.298347 - {KERNEL_ADDR}: 0x82000000
297 00:26:40.298556 - {KERNEL}: 1215884/tftp-deploy-57fxedvl/kernel/zImage
298 00:26:40.298762 - {LAVA_MAC}: None
299 00:26:40.298979 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr
300 00:26:40.299185 - {NFS_SERVER_IP}: 192.168.11.5
301 00:26:40.299389 - {PRESEED_CONFIG}: None
302 00:26:40.299591 - {PRESEED_LOCAL}: None
303 00:26:40.299794 - {RAMDISK_ADDR}: 0x83000000
304 00:26:40.299996 - {RAMDISK}: 1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot
305 00:26:40.300198 - {ROOT_PART}: None
306 00:26:40.300398 - {ROOT}: None
307 00:26:40.300600 - {SERVER_IP}: 192.168.11.5
308 00:26:40.300831 - {TEE_ADDR}: 0x83000000
309 00:26:40.301032 - {TEE}: None
310 00:26:40.301233 Parsed boot commands:
311 00:26:40.301430 - setenv autoload no
312 00:26:40.301629 - setenv initrd_high 0xffffffff
313 00:26:40.301828 - setenv fdt_high 0xffffffff
314 00:26:40.302026 - dhcp
315 00:26:40.302223 - setenv serverip 192.168.11.5
316 00:26:40.302420 - tftp 0x82000000 1215884/tftp-deploy-57fxedvl/kernel/zImage
317 00:26:40.302619 - tftp 0x83000000 1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot
318 00:26:40.302820 - setenv initrd_size ${filesize}
319 00:26:40.303018 - tftp 0x88000000 1215884/tftp-deploy-57fxedvl/dtb/am335x-boneblack.dtb
320 00:26:40.303218 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 00:26:40.303426 - bootz 0x82000000 0x83000000 0x88000000
322 00:26:40.303687 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 00:26:40.304426 start: 2.3 connect-device (timeout 00:05:00) [common]
325 00:26:40.304639 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 00:26:40.662758 Setting prompt string to ['lava-test: # ']
327 00:26:40.663207 end: 2.3 connect-device (duration 00:00:00) [common]
328 00:26:40.663381 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 00:26:40.663556 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 00:26:40.663741 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 00:26:40.664064 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 00:26:41.028029 Returned 0 in 0 seconds
333 00:26:41.128956 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 00:26:41.129877 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 00:26:41.130189 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 00:26:41.130471 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 00:26:41.130718 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 00:26:41.131459 Trying 127.0.0.1...
340 00:26:41.131693 Connected to 127.0.0.1.
341 00:26:41.131909 Escape character is '^]'.
342 00:26:45.871537
343 00:26:45.875159 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 00:26:45.931640 Trying to boot from MMC2
345 00:26:45.980102 Loading Environment from EXT4... Card did not respond to voltage select!
346 00:26:46.047222
347 00:26:46.047547
348 00:26:46.052653 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 00:26:46.052931
350 00:26:46.057750 CPU : AM335X-GP rev 2.1
351 00:26:46.111725 I2C: ready
352 00:26:46.111998 DRAM: 512 MiB
353 00:26:46.165988 No match for driver 'omap_hsmmc'
354 00:26:46.171392 No match for driver 'omap_hsmmc'
355 00:26:46.171666 Some drivers were not found
356 00:26:46.177769 Reset Source: Power-on reset has occurred.
357 00:26:46.178040 RTC 32KCLK Source: External.
358 00:26:46.185242 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 00:26:46.198607 Loading Environment from EXT4... Card did not respond to voltage select!
360 00:26:46.263178 Board: BeagleBone Black
361 00:26:46.266894 <ethaddr> not set. Validating first E-fuse MAC
362 00:26:46.323561 BeagleBone Black:
363 00:26:46.323883 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 00:26:46.329155 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 00:26:46.335151 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 00:26:46.335405 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 00:26:46.340347 Net: eth0: MII MODE
368 00:26:46.349552 cpsw, usb_ether
369 00:26:46.349826 Press SPACE to abort autoboot in 2 seconds
370 00:26:46.400636 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 00:26:46.401053 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 00:26:46.401343 Setting prompt string to ['=> ']
373 00:26:46.401605 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 00:26:46.404856 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 00:26:46.405161 Sending with 10 millisecond of delay
377 00:26:47.539655 => setenv autoload no
378 00:26:47.550147 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 00:26:47.552485 setenv autoload no
380 00:26:47.552974 Sending with 10 millisecond of delay
382 00:26:49.349783 => setenv initrd_high 0xffffffff
383 00:26:49.360321 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 00:26:49.360813 setenv initrd_high 0xffffffff
385 00:26:49.361267 Sending with 10 millisecond of delay
387 00:26:50.977635 => setenv fdt_high 0xffffffff
388 00:26:50.988124 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 00:26:50.988595 setenv fdt_high 0xffffffff
390 00:26:50.989060 Sending with 10 millisecond of delay
392 00:26:51.280503 => dhcp
393 00:26:51.290981 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 00:26:51.291448 dhcp
395 00:26:51.291681 link up on port 0, speed 100, full duplex
396 00:26:51.291904 BOOTP broadcast 1
397 00:26:51.299938 DHCP client bound to address 192.168.11.6 (4 ms)
398 00:26:51.300377 Sending with 10 millisecond of delay
400 00:26:53.036963 => setenv serverip 192.168.11.5
401 00:26:53.047441 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 00:26:53.047914 setenv serverip 192.168.11.5
403 00:26:53.048365 Sending with 10 millisecond of delay
405 00:26:56.591543 => tftp 0x82000000 1215884/tftp-deploy-57fxedvl/kernel/zImage
406 00:26:56.602028 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 00:26:56.602584 tftp 0x82000000 1215884/tftp-deploy-57fxedvl/kernel/zImage
408 00:26:56.602894 link up on port 0, speed 100, full duplex
409 00:26:56.603162 Using cpsw device
410 00:26:56.606173 TFTP from server 192.168.11.5; our IP address is 192.168.11.6
411 00:26:56.611796 Filename '1215884/tftp-deploy-57fxedvl/kernel/zImage'.
412 00:26:56.679917 Load address: 0x82000000
413 00:26:56.809073 Loading: *#################################################################
414 00:26:56.976805 #################################################################
415 00:26:57.144068 #################################################################
416 00:26:57.326699 #################################################################
417 00:26:57.496255 #################################################################
418 00:26:57.670987 #################################################################
419 00:26:57.853249 #################################################################
420 00:26:58.027995 #################################################################
421 00:26:58.202296 #################################################################
422 00:26:58.377714 #################################################################
423 00:26:58.550543 #################################################################
424 00:26:58.722135 #################################################################
425 00:26:58.834782 #########################################
426 00:26:58.835062 5.2 MiB/s
427 00:26:58.835287 done
428 00:26:58.838562 Bytes transferred = 12050944 (b7e200 hex)
429 00:26:58.839091 Sending with 10 millisecond of delay
431 00:27:03.345867 => tftp 0x83000000 1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot
432 00:27:03.356345 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 00:27:03.356869 tftp 0x83000000 1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot
434 00:27:03.357130 link up on port 0, speed 100, full duplex
435 00:27:03.357373 Using cpsw device
436 00:27:03.360578 TFTP from server 192.168.11.5; our IP address is 192.168.11.6
437 00:27:03.374554 Filename '1215884/tftp-deploy-57fxedvl/ramdisk/ramdisk.cpio.gz.uboot'.
438 00:27:03.374843 Load address: 0x83000000
439 00:27:03.668842 Loading: *#################################################################
440 00:27:03.734825 #################################################################
441 00:27:03.909448 #################################################################
442 00:27:04.084079 #################################################################
443 00:27:04.281141 #################################################################
444 00:27:04.455927 #################################################################
445 00:27:04.623000 #################################################################
446 00:27:04.789364 #################################################################
447 00:27:04.962378 #################################################################
448 00:27:05.127871 #################################################################
449 00:27:05.318187 #################################################################
450 00:27:05.487438 #################################################################
451 00:27:05.652960 #################################################################
452 00:27:05.817665 #################################################################
453 00:27:05.992455 #################################################################
454 00:27:06.167034 #################################################################
455 00:27:06.185848 ######
456 00:27:06.186282 5.2 MiB/s
457 00:27:06.186523 done
458 00:27:06.189669 Bytes transferred = 15350322 (ea3a32 hex)
459 00:27:06.190244 Sending with 10 millisecond of delay
461 00:27:08.047665 => setenv initrd_size ${filesize}
462 00:27:08.058146 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 00:27:08.058601 setenv initrd_size ${filesize}
464 00:27:08.059047 Sending with 10 millisecond of delay
466 00:27:12.264800 => tftp 0x88000000 1215884/tftp-deploy-57fxedvl/dtb/am335x-boneblack.dtb
467 00:27:12.275292 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 00:27:12.275752 tftp 0x88000000 1215884/tftp-deploy-57fxedvl/dtb/am335x-boneblack.dtb
469 00:27:12.275983 link up on port 0, speed 100, full duplex
470 00:27:12.276197 Using cpsw device
471 00:27:12.279625 TFTP from server 192.168.11.5; our IP address is 192.168.11.6
472 00:27:12.293083 Filename '1215884/tftp-deploy-57fxedvl/dtb/am335x-boneblack.dtb'.
473 00:27:12.293334 Load address: 0x88000000
474 00:27:12.308506 Loading: *#####
475 00:27:12.308797 4.5 MiB/s
476 00:27:12.309017 done
477 00:27:12.309224 Bytes transferred = 70568 (113a8 hex)
478 00:27:12.311989 Sending with 10 millisecond of delay
480 00:27:25.610524 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 00:27:25.621028 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
482 00:27:25.621481 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 00:27:25.621935 Sending with 10 millisecond of delay
485 00:27:27.960663 => bootz 0x82000000 0x83000000 0x88000000
486 00:27:27.971175 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 00:27:27.971496 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 00:27:27.972025 bootz 0x82000000 0x83000000 0x88000000
489 00:27:27.972265 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 00:27:27.972772 Image Name:
491 00:27:27.972994 Created: 2024-11-04 0:26:40 UTC
492 00:27:27.978302 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 00:27:27.983937 Data Size: 15350258 Bytes = 14.6 MiB
494 00:27:27.984216 Load Address: 00000000
495 00:27:27.991095 Entry Point: 00000000
496 00:27:28.133456 Verifying Checksum ... OK
497 00:27:28.133733 ## Flattened Device Tree blob at 88000000
498 00:27:28.140049 Booting using the fdt blob at 0x88000000
499 00:27:28.144826 Using Device Tree in place at 88000000, end 880143a7
500 00:27:28.152568
501 00:27:28.152866 Starting kernel ...
502 00:27:28.153091
503 00:27:28.153628 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 00:27:28.153930 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 00:27:28.154178 Setting prompt string to ['Linux version [0-9]']
506 00:27:28.154420 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 00:27:28.154667 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 00:27:29.042819 [ 0.000000] Booting Linux on physical CPU 0x0
509 00:27:29.048972 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 00:27:29.049278 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 00:27:29.049536 Setting prompt string to []
512 00:27:29.049795 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 00:27:29.050045 Using line separator: #'\n'#
514 00:27:29.050262 No login prompt set.
515 00:27:29.050487 Parsing kernel messages
516 00:27:29.050691 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 00:27:29.051080 [login-action] Waiting for messages, (timeout 00:04:11)
518 00:27:29.060005 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j361102-arm-clang-15-multi-v7-defconfig-7vh4j) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sun Nov 3 23:10:46 UTC 2024
519 00:27:29.065637 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 00:27:29.077124 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 00:27:29.082872 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 00:27:29.088619 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 00:27:29.094242 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 00:27:29.101119 [ 0.000000] Memory policy: Data cache writeback
525 00:27:29.101397 [ 0.000000] efi: UEFI not found.
526 00:27:29.108669 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 00:27:29.114404 [ 0.000000] Zone ranges:
528 00:27:29.120124 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 00:27:29.125876 [ 0.000000] Normal empty
530 00:27:29.126154 [ 0.000000] HighMem empty
531 00:27:29.131620 [ 0.000000] Movable zone start for each node
532 00:27:29.131896 [ 0.000000] Early memory node ranges
533 00:27:29.143124 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 00:27:29.148311 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 00:27:29.166535 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 00:27:29.172213 [ 0.000000] AM335X ES2.1 (sgx neon)
537 00:27:29.183881 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
538 00:27:29.201630 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 00:27:29.213132 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 00:27:29.218927 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 00:27:29.224628 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 00:27:29.234795 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 00:27:29.264025 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 00:27:29.270010 <6>[ 0.000000] trace event string verifier disabled
545 00:27:29.270288 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 00:27:29.275753 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 00:27:29.287247 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 00:27:29.292887 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 00:27:29.300184 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 00:27:29.315178 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 00:27:29.332876 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 00:27:29.339671 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 00:27:29.439375 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 00:27:29.450879 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 00:27:29.457637 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 00:27:29.470662 <6>[ 0.019188] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 00:27:29.478287 <6>[ 0.034229] Console: colour dummy device 80x30
558 00:27:29.484323 Matched prompt #6: WARNING:
559 00:27:29.484618 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 00:27:29.489747 <3>[ 0.039133] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 00:27:29.495616 <3>[ 0.046208] This ensures that you still see kernel messages. Please
562 00:27:29.498811 <3>[ 0.052935] update your kernel commandline.
563 00:27:29.539238 <6>[ 0.057548] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 00:27:29.545002 <6>[ 0.096199] CPU: Testing write buffer coherency: ok
565 00:27:29.550869 <6>[ 0.101571] CPU0: Spectre v2: using BPIALL workaround
566 00:27:29.551147 <6>[ 0.107039] pid_max: default: 32768 minimum: 301
567 00:27:29.562357 <6>[ 0.112239] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 00:27:29.569369 <6>[ 0.120063] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 00:27:29.576490 <6>[ 0.129516] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 00:27:29.584991 <6>[ 0.136446] Setting up static identity map for 0x80300000 - 0x803000ac
571 00:27:29.590744 <6>[ 0.146155] rcu: Hierarchical SRCU implementation.
572 00:27:29.598306 <6>[ 0.151444] rcu: Max phase no-delay instances is 1000.
573 00:27:29.607146 <6>[ 0.162781] EFI services will not be available.
574 00:27:29.612997 <6>[ 0.168072] smp: Bringing up secondary CPUs ...
575 00:27:29.618741 <6>[ 0.173136] smp: Brought up 1 node, 1 CPU
576 00:27:29.624612 <6>[ 0.177539] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 00:27:29.630489 <6>[ 0.184310] CPU: All CPU(s) started in SVC mode.
578 00:27:29.650790 <6>[ 0.189521] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
579 00:27:29.651079 <6>[ 0.205797] devtmpfs: initialized
580 00:27:29.673987 <6>[ 0.223879] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 00:27:29.685606 <6>[ 0.232499] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 00:27:29.691411 <6>[ 0.242958] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 00:27:29.702322 <6>[ 0.255293] pinctrl core: initialized pinctrl subsystem
584 00:27:29.711886 <6>[ 0.266152] DMI not present or invalid.
585 00:27:29.720255 <6>[ 0.272042] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 00:27:29.729720 <6>[ 0.281052] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 00:27:29.744876 <6>[ 0.292707] thermal_sys: Registered thermal governor 'step_wise'
588 00:27:29.745155 <6>[ 0.292879] cpuidle: using governor menu
589 00:27:29.772388 <6>[ 0.328284] No ATAGs?
590 00:27:29.778668 <6>[ 0.331026] hw-breakpoint: debug architecture 0x4 unsupported.
591 00:27:29.788968 <6>[ 0.343168] Serial: AMBA PL011 UART driver
592 00:27:29.819637 <6>[ 0.375479] iommu: Default domain type: Translated
593 00:27:29.828649 <6>[ 0.380831] iommu: DMA domain TLB invalidation policy: strict mode
594 00:27:29.855409 <5>[ 0.410564] SCSI subsystem initialized
595 00:27:29.861233 <6>[ 0.415489] usbcore: registered new interface driver usbfs
596 00:27:29.866984 <6>[ 0.421555] usbcore: registered new interface driver hub
597 00:27:29.873856 <6>[ 0.427350] usbcore: registered new device driver usb
598 00:27:29.879604 <6>[ 0.433914] pps_core: LinuxPPS API ver. 1 registered
599 00:27:29.891093 <6>[ 0.439303] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 00:27:29.898284 <6>[ 0.449039] PTP clock support registered
601 00:27:29.898562 <6>[ 0.453510] EDAC MC: Ver: 3.0.0
602 00:27:29.956149 <6>[ 0.509061] scmi_core: SCMI protocol bus registered
603 00:27:29.961713 <6>[ 0.517273] vgaarb: loaded
604 00:27:29.973996 <6>[ 0.530033] clocksource: Switched to clocksource dmtimer
605 00:27:30.013006 <6>[ 0.568651] NET: Registered PF_INET protocol family
606 00:27:30.025841 <6>[ 0.574364] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 00:27:30.031592 <6>[ 0.583374] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 00:27:30.043098 <6>[ 0.592301] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 00:27:30.048826 <6>[ 0.600569] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 00:27:30.060343 <6>[ 0.608840] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 00:27:30.066223 <6>[ 0.616566] TCP: Hash tables configured (established 4096 bind 4096)
612 00:27:30.072097 <6>[ 0.623490] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 00:27:30.077969 <6>[ 0.630529] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 00:27:30.085394 <6>[ 0.638106] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 00:27:30.167231 <6>[ 0.717418] RPC: Registered named UNIX socket transport module.
616 00:27:30.167511 <6>[ 0.723868] RPC: Registered udp transport module.
617 00:27:30.172982 <6>[ 0.728978] RPC: Registered tcp transport module.
618 00:27:30.178721 <6>[ 0.734101] RPC: Registered tcp-with-tls transport module.
619 00:27:30.191734 <6>[ 0.740027] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 00:27:30.192013 <6>[ 0.746937] PCI: CLS 0 bytes, default 64
621 00:27:30.198892 <5>[ 0.752806] Initialise system trusted keyrings
622 00:27:30.220991 <6>[ 0.773856] Trying to unpack rootfs image as initramfs...
623 00:27:30.291105 <6>[ 0.840779] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 00:27:30.295772 <6>[ 0.848287] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 00:27:30.335120 <5>[ 0.890980] NFS: Registering the id_resolver key type
626 00:27:30.340830 <5>[ 0.896573] Key type id_resolver registered
627 00:27:30.346710 <5>[ 0.901268] Key type id_legacy registered
628 00:27:30.352590 <6>[ 0.905711] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 00:27:30.362009 <6>[ 0.912931] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 00:27:30.445124 <5>[ 1.001052] Key type asymmetric registered
631 00:27:30.451044 <5>[ 1.005584] Asymmetric key parser 'x509' registered
632 00:27:30.462607 <6>[ 1.011131] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 00:27:30.462896 <6>[ 1.019018] io scheduler mq-deadline registered
634 00:27:30.468298 <6>[ 1.024001] io scheduler kyber registered
635 00:27:30.473915 <6>[ 1.028454] io scheduler bfq registered
636 00:27:30.578109 <6>[ 1.130386] ledtrig-cpu: registered to indicate activity on CPUs
637 00:27:30.866949 <6>[ 1.419094] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 00:27:30.899965 <6>[ 1.455418] msm_serial: driver initialized
639 00:27:30.905791 <6>[ 1.460489] SuperH (H)SCI(F) driver initialized
640 00:27:30.911769 <6>[ 1.465624] STMicroelectronics ASC driver initialized
641 00:27:30.916939 <6>[ 1.471296] STM32 USART driver initialized
642 00:27:31.047989 <6>[ 1.603393] brd: module loaded
643 00:27:31.089050 <6>[ 1.644267] loop: module loaded
644 00:27:31.144747 <6>[ 1.699619] CAN device driver interface
645 00:27:31.151437 <6>[ 1.704960] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 00:27:31.157094 <6>[ 1.712069] e1000e: Intel(R) PRO/1000 Network Driver
647 00:27:31.162918 <6>[ 1.717457] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 00:27:31.168655 <6>[ 1.723938] igb: Intel(R) Gigabit Ethernet Network Driver
649 00:27:31.177016 <6>[ 1.729761] igb: Copyright (c) 2007-2014 Intel Corporation.
650 00:27:31.188916 <6>[ 1.739139] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 00:27:31.194703 <6>[ 1.745297] usbcore: registered new interface driver pegasus
652 00:27:31.200516 <6>[ 1.751459] usbcore: registered new interface driver asix
653 00:27:31.206303 <6>[ 1.757314] usbcore: registered new interface driver ax88179_178a
654 00:27:31.212012 <6>[ 1.763905] usbcore: registered new interface driver cdc_ether
655 00:27:31.217786 <6>[ 1.770227] usbcore: registered new interface driver smsc75xx
656 00:27:31.223665 <6>[ 1.776434] usbcore: registered new interface driver smsc95xx
657 00:27:31.229407 <6>[ 1.782686] usbcore: registered new interface driver net1080
658 00:27:31.235144 <6>[ 1.788812] usbcore: registered new interface driver cdc_subset
659 00:27:31.240892 <6>[ 1.795248] usbcore: registered new interface driver zaurus
660 00:27:31.248578 <6>[ 1.801316] usbcore: registered new interface driver cdc_ncm
661 00:27:31.258827 <6>[ 1.811144] usbcore: registered new interface driver usb-storage
662 00:27:31.268443 <6>[ 1.822493] i2c_dev: i2c /dev entries driver
663 00:27:31.293540 <5>[ 1.841489] cpuidle: enable-method property 'ti,am3352' found operations
664 00:27:31.299242 <6>[ 1.851057] sdhci: Secure Digital Host Controller Interface driver
665 00:27:31.306770 <6>[ 1.857713] sdhci: Copyright(c) Pierre Ossman
666 00:27:31.314011 <6>[ 1.864220] Synopsys Designware Multimedia Card Interface Driver
667 00:27:31.319543 <6>[ 1.872207] sdhci-pltfm: SDHCI platform and OF driver helper
668 00:27:31.333624 <6>[ 1.882148] usbcore: registered new interface driver usbhid
669 00:27:31.333863 <6>[ 1.888179] usbhid: USB HID core driver
670 00:27:31.346314 <6>[ 1.899754] NET: Registered PF_INET6 protocol family
671 00:27:31.785718 <6>[ 2.341637] Segment Routing with IPv6
672 00:27:31.791646 <6>[ 2.345786] In-situ OAM (IOAM) with IPv6
673 00:27:31.798223 <6>[ 2.350328] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 00:27:31.804115 <6>[ 2.357634] NET: Registered PF_PACKET protocol family
675 00:27:31.809867 <6>[ 2.363228] can: controller area network core
676 00:27:31.815590 <6>[ 2.368055] NET: Registered PF_CAN protocol family
677 00:27:31.815852 <6>[ 2.373287] can: raw protocol
678 00:27:31.821505 <6>[ 2.376614] can: broadcast manager protocol
679 00:27:31.828023 <6>[ 2.381214] can: netlink gateway - max_hops=1
680 00:27:31.834144 <5>[ 2.386717] Key type dns_resolver registered
681 00:27:31.840538 <6>[ 2.391809] ThumbEE CPU extension supported.
682 00:27:31.840837 <5>[ 2.396500] Registering SWP/SWPB emulation handler
683 00:27:31.850203 <3>[ 2.402204] omap_voltage_late_init: Voltage driver support not added
684 00:27:32.066970 <5>[ 2.620537] Loading compiled-in X.509 certificates
685 00:27:32.186267 <6>[ 2.729218] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 00:27:32.193444 <6>[ 2.745944] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 00:27:32.220319 <3>[ 2.770272] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 00:27:32.410931 <3>[ 2.960899] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 00:27:32.606615 <6>[ 3.160905] OMAP GPIO hardware version 0.1
690 00:27:32.627585 <6>[ 3.179889] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 00:27:32.730061 <4>[ 3.282099] at24 2-0054: supply vcc not found, using dummy regulator
692 00:27:32.766680 <4>[ 3.318697] at24 2-0055: supply vcc not found, using dummy regulator
693 00:27:32.803554 <4>[ 3.355536] at24 2-0056: supply vcc not found, using dummy regulator
694 00:27:32.843169 <4>[ 3.395198] at24 2-0057: supply vcc not found, using dummy regulator
695 00:27:32.892674 <6>[ 3.445450] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 00:27:32.944421 <3>[ 3.493203] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 00:27:32.969410 <6>[ 3.514497] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 00:27:32.991870 <4>[ 3.541601] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 00:27:32.999547 <4>[ 3.550340] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 00:27:33.088180 <6>[ 3.640380] omap_rng 48310000.rng: Random Number Generator ver. 20
701 00:27:33.112318 <5>[ 3.667335] random: crng init done
702 00:27:33.143228 <6>[ 3.697660] Freeing initrd memory: 14992K
703 00:27:33.159410 <6>[ 3.710088] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 00:27:33.212700 <6>[ 3.762486] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 00:27:33.218425 <6>[ 3.772841] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 00:27:33.230206 <6>[ 3.780184] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 00:27:33.236043 <6>[ 3.787650] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 00:27:33.247604 <6>[ 3.795784] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 00:27:33.255144 <6>[ 3.807427] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
710 00:27:33.268133 <5>[ 3.816530] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 00:27:33.296611 <3>[ 3.846896] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 00:27:33.302293 <6>[ 3.855496] edma 49000000.dma: TI EDMA DMA engine driver
713 00:27:33.374908 <3>[ 3.924546] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 00:27:33.389782 <6>[ 3.939040] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 00:27:33.402797 <3>[ 3.956300] l3-aon-clkctrl:0000:0: failed to disable
716 00:27:33.458635 <6>[ 4.008767] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 00:27:33.464235 <6>[ 4.018294] printk: legacy console [ttyS0] enabled
718 00:27:33.469981 <6>[ 4.018294] printk: legacy console [ttyS0] enabled
719 00:27:33.475601 <6>[ 4.028636] printk: legacy bootconsole [omap8250] disabled
720 00:27:33.481509 <6>[ 4.028636] printk: legacy bootconsole [omap8250] disabled
721 00:27:33.511601 <4>[ 4.060856] tps65217-pmic: Failed to locate of_node [id: -1]
722 00:27:33.515186 <4>[ 4.068268] tps65217-bl: Failed to locate of_node [id: -1]
723 00:27:33.532007 <6>[ 4.088334] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 00:27:33.550597 <6>[ 4.095375] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 00:27:33.562510 <6>[ 4.109087] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 00:27:33.568038 <6>[ 4.121051] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 00:27:33.590606 <6>[ 4.141186] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 00:27:33.596473 <6>[ 4.150351] sdhci-omap 48060000.mmc: Got CD GPIO
729 00:27:33.604587 <4>[ 4.155497] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 00:27:33.619472 <4>[ 4.169256] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 00:27:33.625850 <4>[ 4.177960] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 00:27:33.635663 <4>[ 4.186693] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 00:27:33.734793 <6>[ 4.286497] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 00:27:33.775053 <6>[ 4.325872] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 00:27:33.820216 <6>[ 4.370235] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 00:27:33.827035 <6>[ 4.379056] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 00:27:33.894544 <6>[ 4.440475] mmc1: new high speed MMC card at address 0001
738 00:27:33.894822 <6>[ 4.448579] mmcblk1: mmc1:0001 M62704 3.56 GiB
739 00:27:33.905859 <6>[ 4.460541] mmcblk1: p1
740 00:27:33.918836 <6>[ 4.464896] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 00:27:33.923944 <6>[ 4.477624] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
742 00:27:33.935528 <6>[ 4.489208] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
743 00:27:33.950042 <6>[ 4.502433] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
744 00:27:37.080655 <6>[ 7.631079] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 00:27:37.144140 <5>[ 7.660058] Sending DHCP requests ., OK
746 00:27:37.155452 <6>[ 7.704616] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.6
747 00:27:37.155723 <6>[ 7.712843] IP-Config: Complete:
748 00:27:37.166860 <6>[ 7.716383] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.6, mask=255.255.255.0, gw=192.168.11.1
749 00:27:37.172453 <6>[ 7.727013] host=192.168.11.6, domain=usen.ad.jp, nis-domain=(none)
750 00:27:37.184847 <6>[ 7.734114] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
751 00:27:37.185122 <6>[ 7.734153] nameserver0=192.168.11.1
752 00:27:37.191075 <6>[ 7.746459] clk: Disabling unused clocks
753 00:27:37.197656 <6>[ 7.751263] PM: genpd: Disabling unused power domains
754 00:27:37.215573 <6>[ 7.768283] Freeing unused kernel image (initmem) memory: 2048K
755 00:27:37.223175 <6>[ 7.778164] Run /init as init process
756 00:27:37.246493 Loading, please wait...
757 00:27:37.323920 Starting systemd-udevd version 252.22-1~deb12u1
758 00:27:40.409769 <4>[ 10.958900] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 00:27:40.582528 <4>[ 11.131642] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 00:27:40.724229 <6>[ 11.280746] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 00:27:40.734882 <6>[ 11.286421] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 00:27:40.965289 <6>[ 11.520392] hub 1-0:1.0: USB hub found
763 00:27:40.996734 <6>[ 11.551711] hub 1-0:1.0: 1 port detected
764 00:27:41.002778 <6>[ 11.557552] tda998x 0-0070: found TDA19988
765 00:27:44.239153 Begin: Loading essential drivers ... done.
766 00:27:44.244681 Begin: Running /scripts/init-premount ... done.
767 00:27:44.250157 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
768 00:27:44.260472 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
769 00:27:44.268598 Device /sys/class/net/eth0 found
770 00:27:44.268848 done.
771 00:27:44.348981 Begin: Waiting up to 180 secs for any network device to become available ... done.
772 00:27:44.419200 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
773 00:27:44.419480 IP-Config: eth0 guessed broadcast address 192.168.11.255
774 00:27:44.424664 IP-Config: eth0 complete (dhcp from 192.168.11.1):
775 00:27:44.435882 address: 192.168.11.6 broadcast: 192.168.11.255 netmask: 255.255.255.0
776 00:27:44.441423 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
777 00:27:44.447016 domain : usen.ad.jp
778 00:27:44.452174 rootserver: 192.168.11.1 rootpath:
779 00:27:44.452404 filename :
780 00:27:44.526897 done.
781 00:27:44.538324 Begin: Running /scripts/nfs-bottom ... done.
782 00:27:44.603609 Begin: Running /scripts/init-bottom ... done.
783 00:27:46.043443 <30>[ 16.595856] systemd[1]: System time before build time, advancing clock.
784 00:27:46.213215 <30>[ 16.739452] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 00:27:46.221961 <30>[ 16.776162] systemd[1]: Detected architecture arm.
786 00:27:46.234103
787 00:27:46.234389 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 00:27:46.234613
789 00:27:46.256585 <30>[ 16.809533] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 00:27:48.462480 <30>[ 19.014482] systemd[1]: Queued start job for default target graphical.target.
791 00:27:48.479386 <30>[ 19.029315] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 00:27:48.486948 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 00:27:48.517390 <30>[ 19.066123] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 00:27:48.524848 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 00:27:48.553950 <30>[ 19.102849] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 00:27:48.561227 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 00:27:48.594564 <30>[ 19.143834] systemd[1]: Created slice user.slice - User and Session Slice.
798 00:27:48.601236 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 00:27:48.626726 <30>[ 19.171310] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 00:27:48.632775 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 00:27:48.650973 <30>[ 19.201241] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 00:27:48.659880 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 00:27:48.691689 <30>[ 19.231103] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 00:27:48.698190 <30>[ 19.251649] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 00:27:48.706635 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 00:27:48.729941 <30>[ 19.280530] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 00:27:48.738132 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 00:27:48.760720 <30>[ 19.310969] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 00:27:48.769149 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 00:27:48.790560 <30>[ 19.341099] systemd[1]: Reached target paths.target - Path Units.
811 00:27:48.795623 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 00:27:48.820189 <30>[ 19.370708] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 00:27:48.827609 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 00:27:48.850062 <30>[ 19.400636] systemd[1]: Reached target slices.target - Slice Units.
815 00:27:48.855482 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 00:27:48.880324 <30>[ 19.430883] systemd[1]: Reached target swap.target - Swaps.
817 00:27:48.884387 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 00:27:48.910458 <30>[ 19.460676] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 00:27:48.919386 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 00:27:48.941482 <30>[ 19.491673] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 00:27:48.949772 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 00:27:49.033995 <30>[ 19.579381] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 00:27:49.046805 <30>[ 19.596955] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 00:27:49.055264 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 00:27:49.082317 <30>[ 19.631874] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 00:27:49.089633 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 00:27:49.113816 <30>[ 19.663796] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 00:27:49.121986 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 00:27:49.151925 <30>[ 19.701349] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 00:27:49.157568 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 00:27:49.181707 <30>[ 19.731815] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 00:27:49.190133 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 00:27:49.217118 <30>[ 19.761554] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 00:27:49.235990 <30>[ 19.780306] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 00:27:49.280501 <30>[ 19.831750] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 00:27:49.301426 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 00:27:49.362501 <30>[ 19.913632] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 00:27:49.390138 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 00:27:49.463608 <30>[ 20.013772] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 00:27:49.488750 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 00:27:49.540505 <30>[ 20.091248] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 00:27:49.569233 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 00:27:49.623246 <30>[ 20.174370] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 00:27:49.648972 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 00:27:49.700654 <30>[ 20.251288] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 00:27:49.707591 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 00:27:49.751265 <30>[ 20.301636] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 00:27:49.781322 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 00:27:49.846564 <30>[ 20.398007] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 00:27:49.878196 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 00:27:49.933195 <30>[ 20.484725] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 00:27:49.953432 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 00:27:49.988503 <28>[ 20.532291] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 00:27:49.996931 <28>[ 20.547602] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 00:27:50.039569 <30>[ 20.591459] systemd[1]: Starting systemd-journald.service - Journal Service...
856 00:27:50.051180 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 00:27:50.130344 <30>[ 20.681591] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 00:27:50.150299 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 00:27:50.181175 <30>[ 20.732556] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 00:27:50.233622 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 00:27:50.311520 <30>[ 20.861498] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 00:27:50.349930 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 00:27:50.438185 <30>[ 20.988904] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 00:27:50.500360 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 00:27:50.562128 <30>[ 21.113781] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 00:27:50.612185 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 00:27:50.619511 <30>[ 21.171838] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 00:27:50.654697 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 00:27:50.686257 <30>[ 21.236531] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 00:27:50.716440 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 00:27:50.883376 <30>[ 21.435481] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 00:27:50.920732 <30>[ 21.471726] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 00:27:50.949734 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 00:27:50.969873 <30>[ 21.521982] systemd[1]: Started systemd-journald.service - Journal Service.
875 00:27:50.998505 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
876 00:27:51.040095 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 00:27:51.072101 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 00:27:51.102500 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
879 00:27:51.131461 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
880 00:27:51.155744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
881 00:27:51.190072 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
882 00:27:51.222371 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
883 00:27:51.243603 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
884 00:27:51.274583 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
885 00:27:51.339510 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
886 00:27:51.389044 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
887 00:27:51.456188 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
888 00:27:51.552548 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
889 00:27:51.615968 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
890 00:27:51.768624 <46>[ 22.318943] systemd-journald[162]: Received client request to flush runtime journal.
891 00:27:51.777053 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
892 00:27:51.920203 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
893 00:27:52.751048 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
894 00:27:53.004963 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
895 00:27:53.087267 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
896 00:27:53.564097 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
897 00:27:53.732226 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
898 00:27:53.751925 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
899 00:27:53.770816 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
900 00:27:53.830151 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 00:27:53.874104 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 00:27:54.829794 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 00:27:54.891964 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 00:27:55.380425 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
905 00:27:55.521802 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 00:27:55.612703 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 00:27:57.485820 [[0m[0;31m* [0m] (1 of 5) Job systemd-udev-trigger.s…vice/start running (9s / no limit)
908 00:27:57.720402 M[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
909 00:27:57.753398 [K<5>[ 28.305245] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 00:27:57.764783 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
911 00:27:58.795877 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
912 00:27:59.308618 <5>[ 29.862626] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 00:27:59.398711 <5>[ 29.951083] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 00:27:59.412671 <4>[ 29.964270] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 00:27:59.418581 <6>[ 29.973430] cfg80211: failed to load regulatory.db
916 00:28:00.477689 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
917 00:28:00.512127 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
918 00:28:00.659357 <46>[ 31.201107] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
919 00:28:00.782964 <46>[ 31.327847] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 00:28:09.390180 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
921 00:28:09.414483 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
922 00:28:09.441609 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
923 00:28:09.461607 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
924 00:28:09.535664 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
925 00:28:09.581897 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 00:28:09.623493 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
927 00:28:09.696675 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 00:28:09.757520 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
929 00:28:09.784859 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
930 00:28:09.816261 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
931 00:28:09.854854 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
932 00:28:09.883224 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 00:28:09.939472 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 00:28:09.971597 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 00:28:09.992462 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
936 00:28:10.038725 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
937 00:28:10.084254 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
938 00:28:10.111235 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
939 00:28:10.129872 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
940 00:28:10.166876 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
941 00:28:10.190132 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
942 00:28:10.212279 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
943 00:28:10.279745 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
944 00:28:10.329513 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
945 00:28:10.440757 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
946 00:28:10.549502 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
947 00:28:10.601821 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
948 00:28:10.624297 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
949 00:28:10.642415 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
950 00:28:10.882943 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
951 00:28:10.901314 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
952 00:28:11.030518 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 00:28:11.093225 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 00:28:11.119977 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 00:28:11.225160 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
956 00:28:11.611310 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
957 00:28:11.655783 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
958 00:28:11.686277 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
959 00:28:11.776225 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
960 00:28:11.943653 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
961 00:28:12.081112
962 00:28:12.084593 Debian GNU/Linux 12 debworm-armhf login: root (automatic login)
963 00:28:12.084851
964 00:28:12.396655 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sun Nov 3 23:10:46 UTC 2024 armv7l
965 00:28:12.397041
966 00:28:12.402299 The programs included with the Debian GNU/Linux system are free software;
967 00:28:12.407905 the exact distribution terms for each program are described in the
968 00:28:12.413590 individual files in /usr/share/doc/*/copyright.
969 00:28:12.413842
970 00:28:12.421467 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
971 00:28:12.421699 permitted by applicable law.
972 00:28:17.083760 Unable to match end of the kernel message
974 00:28:17.084544 Setting prompt string to ['/ #']
975 00:28:17.084865 end: 2.4.4.1 login-action (duration 00:00:48) [common]
977 00:28:17.085547 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
978 00:28:17.085837 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
979 00:28:17.086081 Setting prompt string to ['/ #']
980 00:28:17.086291 Forcing a shell prompt, looking for ['/ #']
982 00:28:17.136813 / #
983 00:28:17.137210 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
984 00:28:17.137515 Waiting using forced prompt support (timeout 00:02:30)
985 00:28:17.141707
986 00:28:17.147715 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
987 00:28:17.148056 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
988 00:28:17.148318 Sending with 10 millisecond of delay
990 00:28:22.197000 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr'
991 00:28:22.207591 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1215884/extract-nfsrootfs-ap42lhhr'
992 00:28:22.208153 Sending with 10 millisecond of delay
994 00:28:24.366388 / # export NFS_SERVER_IP='192.168.11.5'
995 00:28:24.376957 export NFS_SERVER_IP='192.168.11.5'
996 00:28:24.377570 end: 2.4.6 export-device-env (duration 00:00:07) [common]
997 00:28:24.377889 end: 2.4 uboot-commands (duration 00:01:44) [common]
998 00:28:24.378199 end: 2 uboot-action (duration 00:01:44) [common]
999 00:28:24.378505 start: 3 lava-test-retry (timeout 00:07:23) [common]
1000 00:28:24.378814 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
1001 00:28:24.379065 Using namespace: common
1003 00:28:24.479752 / # #
1004 00:28:24.480136 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1005 00:28:24.484566 #
1006 00:28:24.491163 Using /lava-1215884
1008 00:28:24.591927 / # export SHELL=/bin/bash
1009 00:28:24.596787 export SHELL=/bin/bash
1011 00:28:24.704044 / # . /lava-1215884/environment
1012 00:28:24.708900 . /lava-1215884/environment
1014 00:28:24.822538 / # /lava-1215884/bin/lava-test-runner /lava-1215884/0
1015 00:28:24.822974 Test shell timeout: 10s (minimum of the action and connection timeout)
1016 00:28:24.827350 /lava-1215884/bin/lava-test-runner /lava-1215884/0
1017 00:28:25.306380 + export TESTRUN_ID=0_timesync-off
1018 00:28:25.314368 + TESTRUN_ID=0_timesync-off
1019 00:28:25.314612 + cd /lava-1215884/0/tests/0_timesync-off
1020 00:28:25.314839 ++ cat uuid
1021 00:28:25.331995 + UUID=1215884_1.6.2.4.1
1022 00:28:25.332317 + set +x
1023 00:28:25.337683 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1215884_1.6.2.4.1>
1024 00:28:25.338188 Received signal: <STARTRUN> 0_timesync-off 1215884_1.6.2.4.1
1025 00:28:25.338437 Starting test lava.0_timesync-off (1215884_1.6.2.4.1)
1026 00:28:25.338717 Skipping test definition patterns.
1027 00:28:25.340814 + systemctl stop systemd-timesyncd
1028 00:28:25.608772 + set +x
1029 00:28:25.609350 Received signal: <ENDRUN> 0_timesync-off 1215884_1.6.2.4.1
1030 00:28:25.609638 Ending use of test pattern.
1031 00:28:25.609869 Ending test lava.0_timesync-off (1215884_1.6.2.4.1), duration 0.27
1033 00:28:25.611894 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1215884_1.6.2.4.1>
1034 00:28:25.802364 + export TESTRUN_ID=1_kselftest-dt
1035 00:28:25.810341 + TESTRUN_ID=1_kselftest-dt
1036 00:28:25.810585 + cd /lava-1215884/0/tests/1_kselftest-dt
1037 00:28:25.810810 ++ cat uuid
1038 00:28:25.826962 + UUID=1215884_1.6.2.4.5
1039 00:28:25.827294 + set +x
1040 00:28:25.832546 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1215884_1.6.2.4.5>
1041 00:28:25.832868 + cd ./automated/linux/kselftest/
1042 00:28:25.833375 Received signal: <STARTRUN> 1_kselftest-dt 1215884_1.6.2.4.5
1043 00:28:25.833674 Starting test lava.1_kselftest-dt (1215884_1.6.2.4.5)
1044 00:28:25.834016 Skipping test definition patterns.
1045 00:28:25.861115 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1046 00:28:25.964384 INFO: install_deps skipped
1047 00:28:26.527546 --2024-11-04 00:28:26-- http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1048 00:28:26.548683 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1049 00:28:26.663250 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1050 00:28:26.774701 HTTP request sent, awaiting response... 200 OK
1051 00:28:26.775031 Length: 2540708 (2.4M) [application/octet-stream]
1052 00:28:26.780291 Saving to: 'kselftest_armhf.tar.gz'
1053 00:28:26.780585
1054 00:28:27.989604 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 2%[ ] 49.92K 224KB/s kselftest_armhf.tar 8%[> ] 218.67K 488KB/s kselftest_armhf.tar 26%[====> ] 658.82K 862KB/s kselftest_armhf.tar 47%[========> ] 1.14M 1.11MB/s kselftest_armhf.tar 100%[===================>] 2.42M 2.00MB/s in 1.2s
1055 00:28:27.989974
1056 00:28:28.367572 2024-11-04 00:28:27 (2.00 MB/s) - 'kselftest_armhf.tar.gz' saved [2540708/2540708]
1057 00:28:28.367905
1058 00:28:48.856688 skiplist:
1059 00:28:48.857088 ========================================
1060 00:28:48.862330 ========================================
1061 00:28:48.972409 dt:test_unprobed_devices.sh
1062 00:28:49.004795 ============== Tests to run ===============
1063 00:28:49.014879 dt:test_unprobed_devices.sh
1064 00:28:49.018770 ===========End Tests to run ===============
1065 00:28:49.028695 shardfile-dt pass
1066 00:28:49.261832 <12>[ 79.819363] kselftest: Running tests in dt
1067 00:28:49.290434 TAP version 13
1068 00:28:49.316482 1..1
1069 00:28:49.369718 # timeout set to 45
1070 00:28:49.369992 # selftests: dt: test_unprobed_devices.sh
1071 00:28:50.203080 # TAP version 13
1072 00:29:15.973695 # 1..257
1073 00:29:16.190785 # ok 1 / # SKIP
1074 00:29:16.214589 # ok 2 /clk_mcasp0
1075 00:29:16.293657 # ok 3 /clk_mcasp0_fixed # SKIP
1076 00:29:16.367685 # ok 4 /cpus/cpu@0 # SKIP
1077 00:29:16.440862 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1078 00:29:16.464582 # ok 6 /fixedregulator0
1079 00:29:16.486657 # ok 7 /leds
1080 00:29:16.503429 # ok 8 /ocp
1081 00:29:16.529013 # ok 9 /ocp/interconnect@44c00000
1082 00:29:16.557847 # ok 10 /ocp/interconnect@44c00000/segment@0
1083 00:29:16.577020 # ok 11 /ocp/interconnect@44c00000/segment@100000
1084 00:29:16.602971 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1085 00:29:16.676265 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1086 00:29:16.700984 # ok 14 /ocp/interconnect@44c00000/segment@200000
1087 00:29:16.722911 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1088 00:29:16.833988 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1089 00:29:16.907365 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1090 00:29:16.982488 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1091 00:29:17.058108 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1092 00:29:17.132271 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1093 00:29:17.211349 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1094 00:29:17.285691 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1095 00:29:17.358063 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1096 00:29:17.432341 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1097 00:29:17.507848 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1098 00:29:17.581963 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1099 00:29:17.660791 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1100 00:29:17.736733 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1101 00:29:17.810583 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1102 00:29:17.885960 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1103 00:29:17.962578 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1104 00:29:18.037281 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1105 00:29:18.112894 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1106 00:29:18.187523 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1107 00:29:18.262988 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1108 00:29:18.337513 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1109 00:29:18.412754 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1110 00:29:18.488945 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1111 00:29:18.563029 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1112 00:29:18.641894 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1113 00:29:18.716229 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1114 00:29:18.791135 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1115 00:29:18.866803 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1116 00:29:18.941611 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1117 00:29:19.022857 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1118 00:29:19.096739 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1119 00:29:19.170723 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1120 00:29:19.245602 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1121 00:29:19.321471 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1122 00:29:19.398753 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1123 00:29:19.473013 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1124 00:29:19.549238 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1125 00:29:19.624750 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1126 00:29:19.701291 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1127 00:29:19.776094 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1128 00:29:19.856874 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1129 00:29:19.931843 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1130 00:29:20.011504 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1131 00:29:20.082448 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1132 00:29:20.158596 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1133 00:29:20.232858 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1134 00:29:20.308475 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1135 00:29:20.383084 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1136 00:29:20.458721 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1137 00:29:20.532203 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1138 00:29:20.608655 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1139 00:29:20.684127 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1140 00:29:20.758990 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1141 00:29:20.833102 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1142 00:29:20.909042 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1143 00:29:20.984424 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1144 00:29:21.059676 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1145 00:29:21.135845 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1146 00:29:21.211455 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1147 00:29:21.293272 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1148 00:29:21.363323 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1149 00:29:21.438947 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1150 00:29:21.513569 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1151 00:29:21.589047 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1152 00:29:21.663404 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1153 00:29:21.739509 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1154 00:29:21.814788 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1155 00:29:21.889772 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1156 00:29:21.965658 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1157 00:29:22.040023 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1158 00:29:22.116430 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1159 00:29:22.192294 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1160 00:29:22.268198 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1161 00:29:22.345775 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1162 00:29:22.422659 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1163 00:29:22.497490 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1164 00:29:22.573904 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1165 00:29:22.649297 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1166 00:29:22.730672 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1167 00:29:22.748602 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1168 00:29:22.775815 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1169 00:29:22.803691 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1170 00:29:22.828246 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1171 00:29:22.852218 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1172 00:29:22.874117 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1173 00:29:22.901726 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1174 00:29:22.922933 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1175 00:29:23.032247 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1176 00:29:23.058031 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1177 00:29:23.082923 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1178 00:29:23.107726 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1179 00:29:23.218965 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1180 00:29:23.297202 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1181 00:29:23.377084 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1182 00:29:23.448020 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1183 00:29:23.523641 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1184 00:29:23.599905 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1185 00:29:23.675505 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1186 00:29:23.751507 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1187 00:29:23.827728 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1188 00:29:23.902936 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1189 00:29:23.980759 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1190 00:29:24.056042 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1191 00:29:24.131217 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1192 00:29:24.209952 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1193 00:29:24.287706 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1194 00:29:24.362697 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1195 00:29:24.384323 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1196 00:29:24.458825 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1197 00:29:24.531547 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1198 00:29:24.608087 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1199 00:29:24.630560 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1200 00:29:24.710525 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1201 00:29:24.732945 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1202 00:29:24.804889 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1203 00:29:24.828048 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1204 00:29:24.852791 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1205 00:29:24.876582 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1206 00:29:24.901532 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1207 00:29:24.925324 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1208 00:29:24.949542 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1209 00:29:24.976161 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1210 00:29:25.053769 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1211 00:29:25.080910 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1212 00:29:25.104052 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1213 00:29:25.181424 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1214 00:29:25.255231 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1215 00:29:25.275040 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1216 00:29:25.380691 # not ok 144 /ocp/interconnect@47c00000
1217 00:29:25.455900 # not ok 145 /ocp/interconnect@47c00000/segment@0
1218 00:29:25.477499 # ok 146 /ocp/interconnect@48000000
1219 00:29:25.506629 # ok 147 /ocp/interconnect@48000000/segment@0
1220 00:29:25.528014 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1221 00:29:25.552724 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1222 00:29:25.580297 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1223 00:29:25.602477 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1224 00:29:25.624452 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1225 00:29:25.649217 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1226 00:29:25.677999 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1227 00:29:25.749007 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1228 00:29:25.824988 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1229 00:29:25.847892 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1230 00:29:25.872522 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1231 00:29:25.900361 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1232 00:29:25.923137 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1233 00:29:25.944761 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1234 00:29:25.969137 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1235 00:29:25.996701 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1236 00:29:26.017930 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1237 00:29:26.040984 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1238 00:29:26.066421 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1239 00:29:26.089728 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1240 00:29:26.114865 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1241 00:29:26.142490 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1242 00:29:26.162206 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1243 00:29:26.186014 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1244 00:29:26.211307 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1245 00:29:26.234569 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1246 00:29:26.259557 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1247 00:29:26.288006 # ok 175 /ocp/interconnect@48000000/segment@100000
1248 00:29:26.308291 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1249 00:29:26.337663 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1250 00:29:26.410838 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1251 00:29:26.488345 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1252 00:29:26.565184 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1253 00:29:26.643414 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1254 00:29:26.713448 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1255 00:29:26.790939 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1256 00:29:26.864463 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1257 00:29:26.941549 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1258 00:29:26.961701 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1259 00:29:26.990533 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1260 00:29:27.012816 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1261 00:29:27.039097 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1262 00:29:27.062934 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1263 00:29:27.089321 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1264 00:29:27.107530 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1265 00:29:27.132401 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1266 00:29:27.156399 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1267 00:29:27.182823 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1268 00:29:27.204837 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1269 00:29:27.229812 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1270 00:29:27.256027 # ok 198 /ocp/interconnect@48000000/segment@200000
1271 00:29:27.281177 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1272 00:29:27.358407 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1273 00:29:27.375082 # ok 201 /ocp/interconnect@48000000/segment@300000
1274 00:29:27.402645 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1275 00:29:27.425316 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1276 00:29:27.450179 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1277 00:29:27.473758 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1278 00:29:27.497950 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1279 00:29:27.522728 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1280 00:29:27.598649 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1281 00:29:27.617517 # ok 209 /ocp/interconnect@4a000000
1282 00:29:27.646469 # ok 210 /ocp/interconnect@4a000000/segment@0
1283 00:29:27.668023 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1284 00:29:27.697506 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1285 00:29:27.719947 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1286 00:29:27.752560 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1287 00:29:27.825396 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1288 00:29:27.938014 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1289 00:29:28.011285 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1290 00:29:28.120156 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1291 00:29:28.194487 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1292 00:29:28.268242 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1293 00:29:28.372648 # not ok 221 /ocp/interconnect@4b140000
1294 00:29:28.450946 # not ok 222 /ocp/interconnect@4b140000/segment@0
1295 00:29:28.523077 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1296 00:29:28.544614 # ok 224 /ocp/target-module@40300000
1297 00:29:28.570387 # ok 225 /ocp/target-module@40300000/sram@0
1298 00:29:28.645208 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1299 00:29:28.719606 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1300 00:29:28.740330 # ok 228 /ocp/target-module@47400000
1301 00:29:28.765821 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1302 00:29:28.788530 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1303 00:29:28.816928 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1304 00:29:28.839699 # ok 232 /ocp/target-module@47400000/usb@1400
1305 00:29:28.858527 # ok 233 /ocp/target-module@47400000/usb@1800
1306 00:29:28.885504 # ok 234 /ocp/target-module@47810000
1307 00:29:28.908382 # ok 235 /ocp/target-module@49000000
1308 00:29:28.927677 # ok 236 /ocp/target-module@49000000/dma@0
1309 00:29:28.950493 # ok 237 /ocp/target-module@49800000
1310 00:29:28.978664 # ok 238 /ocp/target-module@49800000/dma@0
1311 00:29:28.996906 # ok 239 /ocp/target-module@49900000
1312 00:29:29.025155 # ok 240 /ocp/target-module@49900000/dma@0
1313 00:29:29.047544 # ok 241 /ocp/target-module@49a00000
1314 00:29:29.070539 # ok 242 /ocp/target-module@49a00000/dma@0
1315 00:29:29.098293 # ok 243 /ocp/target-module@4c000000
1316 00:29:29.165762 # not ok 244 /ocp/target-module@4c000000/emif@0
1317 00:29:29.188879 # ok 245 /ocp/target-module@50000000
1318 00:29:29.212154 # ok 246 /ocp/target-module@53100000
1319 00:29:29.291007 # not ok 247 /ocp/target-module@53100000/sham@0
1320 00:29:29.309841 # ok 248 /ocp/target-module@53500000
1321 00:29:29.384971 # not ok 249 /ocp/target-module@53500000/aes@0
1322 00:29:29.407394 # ok 250 /ocp/target-module@56000000
1323 00:29:29.517362 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1324 00:29:29.589283 # ok 252 /opp-table # SKIP
1325 00:29:29.667930 # ok 253 /soc # SKIP
1326 00:29:29.684573 # ok 254 /sound
1327 00:29:29.709790 # ok 255 /target-module@4b000000
1328 00:29:29.740007 # ok 256 /target-module@4b000000/target-module@140000
1329 00:29:29.756848 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1330 00:29:29.765068 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1331 00:29:29.773736 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1332 00:29:32.109028 dt_test_unprobed_devices_sh_ skip
1333 00:29:32.114554 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1334 00:29:32.120156 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1335 00:29:32.120417 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1336 00:29:32.125684 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1337 00:29:32.131253 dt_test_unprobed_devices_sh_fixedregulator0 pass
1338 00:29:32.136922 dt_test_unprobed_devices_sh_leds pass
1339 00:29:32.137213 dt_test_unprobed_devices_sh_ocp pass
1340 00:29:32.142501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1341 00:29:32.148125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1342 00:29:32.153747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1343 00:29:32.165091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1344 00:29:32.170526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1345 00:29:32.176151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1346 00:29:32.187427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1347 00:29:32.193088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1348 00:29:32.204302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1349 00:29:32.215584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1350 00:29:32.226746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1351 00:29:32.232372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1352 00:29:32.243667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1353 00:29:32.254767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1354 00:29:32.266125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1355 00:29:32.277274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1356 00:29:32.282746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1357 00:29:32.293994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1358 00:29:32.305339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1359 00:29:32.316377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1360 00:29:32.327578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1361 00:29:32.333171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1362 00:29:32.344400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1363 00:29:32.355517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1364 00:29:32.366749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1365 00:29:32.372370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1366 00:29:32.383577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1367 00:29:32.394795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1368 00:29:32.405886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1369 00:29:32.417189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1370 00:29:32.422698 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1371 00:29:32.433886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1372 00:29:32.445172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1373 00:29:32.456297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1374 00:29:32.467542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1375 00:29:32.478679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1376 00:29:32.489886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1377 00:29:32.501187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1378 00:29:32.512270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1379 00:29:32.523510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1380 00:29:32.534674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1381 00:29:32.545870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1382 00:29:32.557165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1383 00:29:32.568238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1384 00:29:32.579437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1385 00:29:32.590626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1386 00:29:32.601815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1387 00:29:32.613018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1388 00:29:32.624237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1389 00:29:32.635399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1390 00:29:32.646611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1391 00:29:32.657752 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1392 00:29:32.669032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1393 00:29:32.680233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1394 00:29:32.691355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1395 00:29:32.702606 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1396 00:29:32.708235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1397 00:29:32.719467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1398 00:29:32.730525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1399 00:29:32.741790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1400 00:29:32.753087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1401 00:29:32.764165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1402 00:29:32.775417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1403 00:29:32.786495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1404 00:29:32.797744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1405 00:29:32.809024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1406 00:29:32.820104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1407 00:29:32.831382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1408 00:29:32.842530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1409 00:29:32.853746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1410 00:29:32.864902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1411 00:29:32.876131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1412 00:29:32.887309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1413 00:29:32.898518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1414 00:29:32.904104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1415 00:29:32.915310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1416 00:29:32.926493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1417 00:29:32.937604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1418 00:29:32.948876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1419 00:29:32.954478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1420 00:29:32.971309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1421 00:29:32.982369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1422 00:29:32.988103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1423 00:29:33.004750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1424 00:29:33.016102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1425 00:29:33.027305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1426 00:29:33.032755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1427 00:29:33.043975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1428 00:29:33.055303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1429 00:29:33.060736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1430 00:29:33.071969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1431 00:29:33.083095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1432 00:29:33.088737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1433 00:29:33.099971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1434 00:29:33.105517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1435 00:29:33.116733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1436 00:29:33.127845 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1437 00:29:33.139132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1438 00:29:33.150394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1439 00:29:33.161506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1440 00:29:33.172731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1441 00:29:33.183935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1442 00:29:33.195088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1443 00:29:33.206233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1444 00:29:33.217575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1445 00:29:33.228793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1446 00:29:33.239869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1447 00:29:33.256747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1448 00:29:33.268098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1449 00:29:33.279314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1450 00:29:33.290472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1451 00:29:33.301742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1452 00:29:33.318486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1453 00:29:33.329720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1454 00:29:33.341009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1455 00:29:33.352222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1456 00:29:33.357851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1457 00:29:33.369143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1458 00:29:33.380216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1459 00:29:33.385848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1460 00:29:33.397128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1461 00:29:33.402596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1462 00:29:33.413840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1463 00:29:33.419562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1464 00:29:33.430592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1465 00:29:33.436220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1466 00:29:33.447555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1467 00:29:33.453184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1468 00:29:33.464212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1469 00:29:33.475554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1470 00:29:33.486588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1471 00:29:33.497847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1472 00:29:33.509201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1473 00:29:33.514702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1474 00:29:33.525948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1475 00:29:33.531544 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1476 00:29:33.537162 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1477 00:29:33.542655 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1478 00:29:33.548264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1479 00:29:33.553890 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1480 00:29:33.565155 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1481 00:29:33.570657 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1482 00:29:33.576282 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1483 00:29:33.587390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1484 00:29:33.593156 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1485 00:29:33.604260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1486 00:29:33.609921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1487 00:29:33.621161 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1488 00:29:33.626634 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1489 00:29:33.637777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1490 00:29:33.643336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1491 00:29:33.654624 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1492 00:29:33.660208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1493 00:29:33.671412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1494 00:29:33.676977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1495 00:29:33.688098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1496 00:29:33.693729 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1497 00:29:33.699407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1498 00:29:33.710469 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1499 00:29:33.716118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1500 00:29:33.727380 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1501 00:29:33.732979 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1502 00:29:33.744078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1503 00:29:33.749720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1504 00:29:33.760852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1505 00:29:33.766488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1506 00:29:33.772100 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1507 00:29:33.783258 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1508 00:29:33.788883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1509 00:29:33.800128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1510 00:29:33.811279 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1511 00:29:33.822510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1512 00:29:33.833633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1513 00:29:33.844879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1514 00:29:33.856148 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1515 00:29:33.867258 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1516 00:29:33.878504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1517 00:29:33.884133 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1518 00:29:33.895276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1519 00:29:33.900921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1520 00:29:33.912144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1521 00:29:33.917652 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1522 00:29:33.928888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1523 00:29:33.934402 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1524 00:29:33.945639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1525 00:29:33.951278 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1526 00:29:33.962395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1527 00:29:33.968006 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1528 00:29:33.979270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1529 00:29:33.984765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1530 00:29:33.996018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1531 00:29:34.001634 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1532 00:29:34.007147 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1533 00:29:34.018386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1534 00:29:34.024001 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1535 00:29:34.035141 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1536 00:29:34.040753 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1537 00:29:34.051999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1538 00:29:34.057524 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1539 00:29:34.068753 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1540 00:29:34.074373 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1541 00:29:34.079996 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1542 00:29:34.085518 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1543 00:29:34.096757 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1544 00:29:34.107899 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1545 00:29:34.113511 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1546 00:29:34.119144 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1547 00:29:34.130242 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1548 00:29:34.141579 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1549 00:29:34.152729 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1550 00:29:34.163882 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1551 00:29:34.169517 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1552 00:29:34.175144 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1553 00:29:34.180770 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1554 00:29:34.186403 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1555 00:29:34.192129 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1556 00:29:34.197623 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1557 00:29:34.208878 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1558 00:29:34.214400 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1559 00:29:34.220148 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1560 00:29:34.225643 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1561 00:29:34.231268 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1562 00:29:34.242390 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1563 00:29:34.248142 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1564 00:29:34.253641 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1565 00:29:34.259267 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1566 00:29:34.264875 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1567 00:29:34.270529 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1568 00:29:34.276141 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1569 00:29:34.281686 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1570 00:29:34.287269 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1571 00:29:34.292881 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1572 00:29:34.298514 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1573 00:29:34.304142 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1574 00:29:34.309664 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1575 00:29:34.315268 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1576 00:29:34.320869 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1577 00:29:34.326512 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1578 00:29:34.332137 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1579 00:29:34.337664 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1580 00:29:34.343263 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1581 00:29:34.348895 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1582 00:29:34.354526 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1583 00:29:34.354817 dt_test_unprobed_devices_sh_opp-table skip
1584 00:29:34.360136 dt_test_unprobed_devices_sh_soc skip
1585 00:29:34.365776 dt_test_unprobed_devices_sh_sound pass
1586 00:29:34.371268 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1587 00:29:34.376918 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1588 00:29:34.382509 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1589 00:29:34.388136 dt_test_unprobed_devices_sh fail
1590 00:29:34.388425 + ../../utils/send-to-lava.sh ./output/result.txt
1591 00:29:34.395964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1592 00:29:34.396545 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1594 00:29:34.411719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1595 00:29:34.412204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1597 00:29:34.514688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1598 00:29:34.515179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1600 00:29:34.617189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1601 00:29:34.617736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1603 00:29:34.718836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1604 00:29:34.719323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1606 00:29:34.819558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1607 00:29:34.820107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1609 00:29:34.919830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1610 00:29:34.920317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1612 00:29:35.019820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1613 00:29:35.020406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1615 00:29:35.118726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1616 00:29:35.119215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1618 00:29:35.220568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1619 00:29:35.221072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1621 00:29:35.317675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1622 00:29:35.318163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1624 00:29:35.417688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1625 00:29:35.418174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1627 00:29:35.519535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1628 00:29:35.520023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1630 00:29:35.617677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1631 00:29:35.618230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1633 00:29:35.715153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1634 00:29:35.715641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1636 00:29:35.819892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1637 00:29:35.820429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1639 00:29:35.920207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1640 00:29:35.920696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1642 00:29:36.017668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1643 00:29:36.018161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1645 00:29:36.118394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1646 00:29:36.118879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1648 00:29:36.217417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1649 00:29:36.217922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1651 00:29:36.315171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1652 00:29:36.315662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1654 00:29:36.411416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1655 00:29:36.411893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1657 00:29:36.512199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1658 00:29:36.512686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1660 00:29:36.611617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1661 00:29:36.612155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1663 00:29:36.712267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1664 00:29:36.712767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1666 00:29:36.815100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1667 00:29:36.815641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1669 00:29:36.916462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1670 00:29:36.916965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1672 00:29:37.022210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1673 00:29:37.022700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1675 00:29:37.122050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1676 00:29:37.122362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1678 00:29:37.229528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1679 00:29:37.230025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1681 00:29:37.347161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1682 00:29:37.347646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1684 00:29:37.451450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1685 00:29:37.451934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1687 00:29:37.552341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1688 00:29:37.552892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1690 00:29:37.653443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1691 00:29:37.653935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1693 00:29:37.753072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1694 00:29:37.753563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1696 00:29:37.855237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1697 00:29:37.855826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1699 00:29:37.954309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1700 00:29:37.954822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1702 00:29:38.056171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1703 00:29:38.056662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1705 00:29:38.157486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1706 00:29:38.158012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1708 00:29:38.255680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1709 00:29:38.256160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1711 00:29:38.352887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1712 00:29:38.353366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1714 00:29:38.449898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1715 00:29:38.450376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1717 00:29:38.551407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1718 00:29:38.551945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1720 00:29:38.655443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1721 00:29:38.655941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1723 00:29:38.757019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1724 00:29:38.757498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1726 00:29:38.856904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1727 00:29:38.857436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1729 00:29:38.956596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1730 00:29:38.957105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1732 00:29:39.058606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1733 00:29:39.059083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1735 00:29:39.160201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1736 00:29:39.160697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1738 00:29:39.263877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1739 00:29:39.264361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1741 00:29:39.365000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1742 00:29:39.365480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1744 00:29:39.467512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1745 00:29:39.467991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1747 00:29:39.567372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1748 00:29:39.567908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1750 00:29:39.668056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1751 00:29:39.668548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1753 00:29:39.773388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1754 00:29:39.773930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1756 00:29:39.873517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1757 00:29:39.874022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1759 00:29:39.976641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1760 00:29:39.977152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1762 00:29:40.077070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1763 00:29:40.077565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1765 00:29:40.174623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1766 00:29:40.175115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1768 00:29:40.276198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1769 00:29:40.276675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1771 00:29:40.378923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1772 00:29:40.379401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1774 00:29:40.483470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1775 00:29:40.483947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1777 00:29:40.592398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1778 00:29:40.592939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1780 00:29:40.691074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1781 00:29:40.691560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1783 00:29:40.790981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1784 00:29:40.791511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1786 00:29:40.891206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1787 00:29:40.891690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1789 00:29:40.992553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1790 00:29:40.993055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1792 00:29:41.092570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1793 00:29:41.093074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1795 00:29:41.192289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1796 00:29:41.192772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1798 00:29:41.293042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1799 00:29:41.293554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1801 00:29:41.393913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1802 00:29:41.394411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1804 00:29:41.495131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1805 00:29:41.495618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1807 00:29:41.596485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1808 00:29:41.597038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1810 00:29:41.698113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1811 00:29:41.698599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1813 00:29:41.796924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1814 00:29:41.797471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1816 00:29:41.896188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1817 00:29:41.896721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1819 00:29:41.996611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1820 00:29:41.997119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1822 00:29:42.100121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1823 00:29:42.100611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1825 00:29:42.202152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1826 00:29:42.202649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1828 00:29:42.303150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1829 00:29:42.303664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1831 00:29:42.403725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1832 00:29:42.404212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1834 00:29:42.503290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1835 00:29:42.503772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1837 00:29:42.604297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1838 00:29:42.604839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1840 00:29:42.701837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1841 00:29:42.702312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1843 00:29:42.801538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1844 00:29:42.802087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1846 00:29:42.902046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1847 00:29:42.902540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1849 00:29:43.003462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1850 00:29:43.003952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1852 00:29:43.105481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1853 00:29:43.105957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1855 00:29:43.208931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1856 00:29:43.209419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1858 00:29:43.315633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1859 00:29:43.316115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1861 00:29:43.416834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1862 00:29:43.417325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1864 00:29:43.515196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1865 00:29:43.515698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1867 00:29:43.617428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1868 00:29:43.617968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1870 00:29:43.714493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1871 00:29:43.714984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1873 00:29:43.811169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1874 00:29:43.811705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1876 00:29:43.906660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1877 00:29:43.907140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1879 00:29:44.006536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1880 00:29:44.007022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1882 00:29:44.111132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1883 00:29:44.111610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1885 00:29:44.211811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1886 00:29:44.212292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1888 00:29:44.313207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1889 00:29:44.313687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1891 00:29:44.418554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1892 00:29:44.419034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1894 00:29:44.521908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1895 00:29:44.522386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1897 00:29:44.622659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1898 00:29:44.623202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1900 00:29:44.719818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1901 00:29:44.720302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1903 00:29:44.821793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1904 00:29:44.822321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1906 00:29:44.919068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1907 00:29:44.919556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1909 00:29:45.016777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1910 00:29:45.017255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1912 00:29:45.114246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1913 00:29:45.114723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1915 00:29:45.214165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1916 00:29:45.214660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1918 00:29:45.316315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1919 00:29:45.316770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1921 00:29:45.413528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1922 00:29:45.414017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1924 00:29:45.514664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1925 00:29:45.515149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1927 00:29:45.617173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1928 00:29:45.617734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1930 00:29:45.719782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1931 00:29:45.720278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1933 00:29:45.824451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1934 00:29:45.825035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1936 00:29:45.926946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1937 00:29:45.927467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1939 00:29:46.030726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1940 00:29:46.031206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1942 00:29:46.134852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1943 00:29:46.135342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1945 00:29:46.235895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1946 00:29:46.236391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1948 00:29:46.337515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1949 00:29:46.338003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1951 00:29:46.440941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1953 00:29:46.444076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1954 00:29:46.541918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1956 00:29:46.544944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1957 00:29:46.642206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1959 00:29:46.645187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1960 00:29:46.746944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1961 00:29:46.747467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1963 00:29:46.846348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1964 00:29:46.846888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1966 00:29:46.943736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1967 00:29:46.944229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1969 00:29:47.044609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1970 00:29:47.045130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1972 00:29:47.144031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1973 00:29:47.144529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1975 00:29:47.239842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1976 00:29:47.240330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1978 00:29:47.337144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1979 00:29:47.337451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1981 00:29:47.439374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1982 00:29:47.439809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1984 00:29:47.538784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1985 00:29:47.539265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1987 00:29:47.638097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1988 00:29:47.638643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1990 00:29:47.735086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1991 00:29:47.735571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1993 00:29:47.833790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1994 00:29:47.834329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1996 00:29:47.929869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1997 00:29:47.930359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1999 00:29:48.029955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2000 00:29:48.030459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2002 00:29:48.129727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2003 00:29:48.130212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2005 00:29:48.229704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2006 00:29:48.230188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2008 00:29:48.331439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2009 00:29:48.331935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2011 00:29:48.430308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2012 00:29:48.430800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2014 00:29:48.531757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2015 00:29:48.532246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2017 00:29:48.632836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2018 00:29:48.633390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2020 00:29:48.729296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2021 00:29:48.729785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2023 00:29:48.825926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2024 00:29:48.826471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2026 00:29:48.926925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2027 00:29:48.927407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2029 00:29:49.023164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2030 00:29:49.023648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2032 00:29:49.123906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2033 00:29:49.124390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2035 00:29:49.227684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2036 00:29:49.228168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2038 00:29:49.328657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2039 00:29:49.329160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2041 00:29:49.428782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2042 00:29:49.429267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2044 00:29:49.531260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2045 00:29:49.531744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2047 00:29:49.630658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2048 00:29:49.631209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2050 00:29:49.729564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2051 00:29:49.730041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2053 00:29:49.828396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2054 00:29:49.828944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2056 00:29:49.929712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2057 00:29:49.930190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2059 00:29:50.031431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2060 00:29:50.031912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2062 00:29:50.128790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2063 00:29:50.129279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2065 00:29:50.232006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2066 00:29:50.232508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2068 00:29:50.331093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2069 00:29:50.331562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2071 00:29:50.432123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2072 00:29:50.432610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2074 00:29:50.528958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2075 00:29:50.529433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2077 00:29:50.632751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2078 00:29:50.633288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2080 00:29:50.732283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2081 00:29:50.732771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2083 00:29:50.832210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2084 00:29:50.832775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2086 00:29:50.931547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2087 00:29:50.932022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2089 00:29:51.034825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2090 00:29:51.035311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2092 00:29:51.136648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2093 00:29:51.137151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2095 00:29:51.239901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2096 00:29:51.240376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2098 00:29:51.341532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2099 00:29:51.342009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2101 00:29:51.443189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2102 00:29:51.443677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2104 00:29:51.543978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2105 00:29:51.544475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2107 00:29:51.644601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2108 00:29:51.645177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2110 00:29:51.742808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2111 00:29:51.743297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2113 00:29:51.845301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2114 00:29:51.845836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2116 00:29:51.947174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2117 00:29:51.947656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2119 00:29:52.050247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2120 00:29:52.050727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2122 00:29:52.152500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2123 00:29:52.153004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2125 00:29:52.254725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2126 00:29:52.255201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2128 00:29:52.356514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2129 00:29:52.357021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2131 00:29:52.461091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2132 00:29:52.461564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2134 00:29:52.563108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2135 00:29:52.563582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2137 00:29:52.664187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2138 00:29:52.664754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2140 00:29:52.772979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2141 00:29:52.773459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2143 00:29:52.872477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2144 00:29:52.873037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2146 00:29:52.975119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2147 00:29:52.975598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2149 00:29:53.073073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2150 00:29:53.073554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2152 00:29:53.171091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2153 00:29:53.171572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2155 00:29:53.270078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2156 00:29:53.270564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2158 00:29:53.370684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2159 00:29:53.371161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2161 00:29:53.473705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2162 00:29:53.474185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2164 00:29:53.573806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2165 00:29:53.574343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2167 00:29:53.671176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2168 00:29:53.671655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2170 00:29:53.771419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2171 00:29:53.771898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2173 00:29:53.872501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2174 00:29:53.873066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2176 00:29:53.972187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2177 00:29:53.972661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2179 00:29:54.072612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2180 00:29:54.073126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2182 00:29:54.177031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2183 00:29:54.177510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2185 00:29:54.277303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2186 00:29:54.277791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2188 00:29:54.379796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2189 00:29:54.380275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2191 00:29:54.480695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2192 00:29:54.481189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2194 00:29:54.577214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2195 00:29:54.577747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2197 00:29:54.676547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2198 00:29:54.677070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2200 00:29:54.776108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2201 00:29:54.776756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2203 00:29:54.875190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2204 00:29:54.875721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2206 00:29:54.974148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2207 00:29:54.974627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2209 00:29:55.070096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2210 00:29:55.070575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2212 00:29:55.167004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2213 00:29:55.167484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2215 00:29:55.266775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2216 00:29:55.267254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2218 00:29:55.361437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2219 00:29:55.361921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2221 00:29:55.459971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2222 00:29:55.460456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2224 00:29:55.558611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2225 00:29:55.559099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2227 00:29:55.657472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2228 00:29:55.658020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2230 00:29:55.757466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2231 00:29:55.757952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2233 00:29:55.858225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2234 00:29:55.858770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2236 00:29:55.957204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2237 00:29:55.957693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2239 00:29:56.056590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2240 00:29:56.057125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2242 00:29:56.155729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2243 00:29:56.156232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2245 00:29:56.253828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2246 00:29:56.254325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2248 00:29:56.355057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2249 00:29:56.355562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2251 00:29:56.454434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2252 00:29:56.454919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2254 00:29:56.549787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2255 00:29:56.550262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2257 00:29:56.646774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2258 00:29:56.647306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2260 00:29:56.743393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2261 00:29:56.743869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2263 00:29:56.841371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2264 00:29:56.841895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2266 00:29:56.937991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2267 00:29:56.938467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2269 00:29:57.035365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2270 00:29:57.035854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2272 00:29:57.130269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2274 00:29:57.133390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2275 00:29:57.227837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2276 00:29:57.228314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2278 00:29:57.325469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2279 00:29:57.325954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2281 00:29:57.428508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2282 00:29:57.429013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2284 00:29:57.528548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2285 00:29:57.529036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2287 00:29:57.628374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2288 00:29:57.628825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2290 00:29:57.730807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2291 00:29:57.731249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2293 00:29:57.835587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2294 00:29:57.836124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2296 00:29:57.936357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2297 00:29:57.936838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2299 00:29:58.037574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2300 00:29:58.038052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2302 00:29:58.137448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2303 00:29:58.137925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2305 00:29:58.239717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2306 00:29:58.240204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2308 00:29:58.338670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2309 00:29:58.339148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2311 00:29:58.440402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2312 00:29:58.440878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2314 00:29:58.544845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2315 00:29:58.545328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2317 00:29:58.646444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2318 00:29:58.646986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2320 00:29:58.747079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2321 00:29:58.747555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2323 00:29:58.849476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2324 00:29:58.850017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2326 00:29:58.951415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2327 00:29:58.951890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2329 00:29:59.051172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2330 00:29:59.051649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2332 00:29:59.153055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2333 00:29:59.153546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2335 00:29:59.253432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2336 00:29:59.253913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2338 00:29:59.359155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2339 00:29:59.359631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2341 00:29:59.459526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2342 00:29:59.460014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2344 00:29:59.560436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2345 00:29:59.560927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2347 00:29:59.658809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2348 00:29:59.659342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2350 00:29:59.763909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2351 00:29:59.764386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2353 00:29:59.865428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2354 00:29:59.865961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2356 00:29:59.968666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2357 00:29:59.969163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2359 00:30:00.091765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2360 00:30:00.092308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2362 00:30:00.197763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2363 00:30:00.198244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2365 00:30:00.298330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2366 00:30:00.298643 + set +x
2367 00:30:00.299111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2369 00:30:00.302546 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1215884_1.6.2.4.5>
2370 00:30:00.302989 Received signal: <ENDRUN> 1_kselftest-dt 1215884_1.6.2.4.5
2371 00:30:00.303230 Ending use of test pattern.
2372 00:30:00.303447 Ending test lava.1_kselftest-dt (1215884_1.6.2.4.5), duration 94.47
2374 00:30:00.311887 <LAVA_TEST_RUNNER EXIT>
2375 00:30:00.312316 ok: lava_test_shell seems to have completed
2376 00:30:00.318033 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2377 00:30:00.319028 end: 3.1 lava-test-shell (duration 00:01:36) [common]
2378 00:30:00.319305 end: 3 lava-test-retry (duration 00:01:36) [common]
2379 00:30:00.319586 start: 4 finalize (timeout 00:05:47) [common]
2380 00:30:00.319866 start: 4.1 power-off (timeout 00:00:30) [common]
2381 00:30:00.320224 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2382 00:30:00.689080 Returned 0 in 0 seconds
2383 00:30:00.789964 end: 4.1 power-off (duration 00:00:00) [common]
2385 00:30:00.790872 start: 4.2 read-feedback (timeout 00:05:46) [common]
2386 00:30:00.791492 Listened to connection for namespace 'common' for up to 1s
2387 00:30:00.792039 Listened to connection for namespace 'common' for up to 1s
2388 00:30:01.792387 Finalising connection for namespace 'common'
2389 00:30:01.792840 Disconnecting from shell: Finalise
2390 00:30:01.793118 / #
2391 00:30:01.893698 end: 4.2 read-feedback (duration 00:00:01) [common]
2392 00:30:01.894113 end: 4 finalize (duration 00:00:02) [common]
2393 00:30:01.894466 Cleaning after the job
2394 00:30:01.894781 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/ramdisk
2395 00:30:01.898589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/kernel
2396 00:30:01.901605 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/dtb
2397 00:30:01.902085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/nfsrootfs
2398 00:30:01.953659 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1215884/tftp-deploy-57fxedvl/modules
2399 00:30:01.957200 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1215884
2400 00:30:02.614572 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1215884
2401 00:30:02.614843 Job finished correctly