Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 23:57:03.981468 lava-dispatcher, installed at version: 2024.01
2 23:57:03.982281 start: 0 validate
3 23:57:03.982773 Start time: 2024-11-03 23:57:03.982744+00:00 (UTC)
4 23:57:03.983339 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 23:57:03.983893 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 23:57:04.017513 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 23:57:04.018095 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fkernel%2FzImage exists
8 23:57:04.041706 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 23:57:04.042339 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 23:57:04.065119 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 23:57:04.065636 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 23:57:04.089660 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 23:57:04.090154 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fmodules.tar.xz exists
14 23:57:04.121455 validate duration: 0.14
16 23:57:04.122444 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:57:04.122771 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:57:04.123062 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:57:04.123663 Not decompressing ramdisk as can be used compressed.
20 23:57:04.124098 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 23:57:04.124378 saving as /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/ramdisk/initrd.cpio.gz
22 23:57:04.124647 total size: 4775763 (4 MB)
23 23:57:04.154935 progress 0 % (0 MB)
24 23:57:04.158560 progress 5 % (0 MB)
25 23:57:04.161800 progress 10 % (0 MB)
26 23:57:04.165020 progress 15 % (0 MB)
27 23:57:04.168570 progress 20 % (0 MB)
28 23:57:04.171865 progress 25 % (1 MB)
29 23:57:04.174960 progress 30 % (1 MB)
30 23:57:04.178501 progress 35 % (1 MB)
31 23:57:04.181601 progress 40 % (1 MB)
32 23:57:04.184768 progress 45 % (2 MB)
33 23:57:04.187916 progress 50 % (2 MB)
34 23:57:04.191593 progress 55 % (2 MB)
35 23:57:04.194874 progress 60 % (2 MB)
36 23:57:04.198176 progress 65 % (2 MB)
37 23:57:04.201730 progress 70 % (3 MB)
38 23:57:04.204877 progress 75 % (3 MB)
39 23:57:04.208114 progress 80 % (3 MB)
40 23:57:04.211299 progress 85 % (3 MB)
41 23:57:04.215013 progress 90 % (4 MB)
42 23:57:04.218275 progress 95 % (4 MB)
43 23:57:04.221225 progress 100 % (4 MB)
44 23:57:04.221894 4 MB downloaded in 0.10 s (46.84 MB/s)
45 23:57:04.222430 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:57:04.223281 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:57:04.223571 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:57:04.223839 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:57:04.224305 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-16/kernel/zImage
51 23:57:04.224547 saving as /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/kernel/zImage
52 23:57:04.224778 total size: 12042752 (11 MB)
53 23:57:04.224992 No compression specified
54 23:57:04.259052 progress 0 % (0 MB)
55 23:57:04.266569 progress 5 % (0 MB)
56 23:57:04.274076 progress 10 % (1 MB)
57 23:57:04.281833 progress 15 % (1 MB)
58 23:57:04.289244 progress 20 % (2 MB)
59 23:57:04.296748 progress 25 % (2 MB)
60 23:57:04.304427 progress 30 % (3 MB)
61 23:57:04.311682 progress 35 % (4 MB)
62 23:57:04.319410 progress 40 % (4 MB)
63 23:57:04.326711 progress 45 % (5 MB)
64 23:57:04.334009 progress 50 % (5 MB)
65 23:57:04.341642 progress 55 % (6 MB)
66 23:57:04.349018 progress 60 % (6 MB)
67 23:57:04.356381 progress 65 % (7 MB)
68 23:57:04.364118 progress 70 % (8 MB)
69 23:57:04.371545 progress 75 % (8 MB)
70 23:57:04.379331 progress 80 % (9 MB)
71 23:57:04.386670 progress 85 % (9 MB)
72 23:57:04.394013 progress 90 % (10 MB)
73 23:57:04.401910 progress 95 % (10 MB)
74 23:57:04.408864 progress 100 % (11 MB)
75 23:57:04.409413 11 MB downloaded in 0.18 s (62.21 MB/s)
76 23:57:04.409904 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:57:04.410722 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:57:04.410998 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:57:04.411261 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:57:04.411798 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
82 23:57:04.412082 saving as /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/dtb/am335x-boneblack.dtb
83 23:57:04.412290 total size: 70568 (0 MB)
84 23:57:04.412499 No compression specified
85 23:57:04.444763 progress 46 % (0 MB)
86 23:57:04.445551 progress 92 % (0 MB)
87 23:57:04.446274 progress 100 % (0 MB)
88 23:57:04.446683 0 MB downloaded in 0.03 s (1.96 MB/s)
89 23:57:04.447134 end: 1.3.1 http-download (duration 00:00:00) [common]
91 23:57:04.447939 end: 1.3 download-retry (duration 00:00:00) [common]
92 23:57:04.448202 start: 1.4 download-retry (timeout 00:10:00) [common]
93 23:57:04.448463 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 23:57:04.448926 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 23:57:04.449165 saving as /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/nfsrootfs/full.rootfs.tar
96 23:57:04.449388 total size: 117747780 (112 MB)
97 23:57:04.449601 Using unxz to decompress xz
98 23:57:04.476231 progress 0 % (0 MB)
99 23:57:05.208309 progress 5 % (5 MB)
100 23:57:05.958581 progress 10 % (11 MB)
101 23:57:06.746528 progress 15 % (16 MB)
102 23:57:07.468984 progress 20 % (22 MB)
103 23:57:08.045348 progress 25 % (28 MB)
104 23:57:08.846186 progress 30 % (33 MB)
105 23:57:09.651652 progress 35 % (39 MB)
106 23:57:09.989501 progress 40 % (44 MB)
107 23:57:10.361137 progress 45 % (50 MB)
108 23:57:11.023233 progress 50 % (56 MB)
109 23:57:11.857863 progress 55 % (61 MB)
110 23:57:12.594066 progress 60 % (67 MB)
111 23:57:13.312768 progress 65 % (73 MB)
112 23:57:14.108218 progress 70 % (78 MB)
113 23:57:14.874061 progress 75 % (84 MB)
114 23:57:15.612319 progress 80 % (89 MB)
115 23:57:16.341637 progress 85 % (95 MB)
116 23:57:17.125268 progress 90 % (101 MB)
117 23:57:17.878845 progress 95 % (106 MB)
118 23:57:18.704502 progress 100 % (112 MB)
119 23:57:18.717943 112 MB downloaded in 14.27 s (7.87 MB/s)
120 23:57:18.718973 end: 1.4.1 http-download (duration 00:00:14) [common]
122 23:57:18.720804 end: 1.4 download-retry (duration 00:00:14) [common]
123 23:57:18.721404 start: 1.5 download-retry (timeout 00:09:45) [common]
124 23:57:18.722025 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 23:57:18.722917 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-16/modules.tar.xz
126 23:57:18.723433 saving as /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/modules/modules.tar
127 23:57:18.723894 total size: 6910668 (6 MB)
128 23:57:18.724363 Using unxz to decompress xz
129 23:57:18.763533 progress 0 % (0 MB)
130 23:57:18.799345 progress 5 % (0 MB)
131 23:57:18.849368 progress 10 % (0 MB)
132 23:57:18.895958 progress 15 % (1 MB)
133 23:57:18.949022 progress 20 % (1 MB)
134 23:57:18.997408 progress 25 % (1 MB)
135 23:57:19.047991 progress 30 % (2 MB)
136 23:57:19.092771 progress 35 % (2 MB)
137 23:57:19.142477 progress 40 % (2 MB)
138 23:57:19.187712 progress 45 % (2 MB)
139 23:57:19.237999 progress 50 % (3 MB)
140 23:57:19.285243 progress 55 % (3 MB)
141 23:57:19.335578 progress 60 % (3 MB)
142 23:57:19.383594 progress 65 % (4 MB)
143 23:57:19.428545 progress 70 % (4 MB)
144 23:57:19.478499 progress 75 % (4 MB)
145 23:57:19.521779 progress 80 % (5 MB)
146 23:57:19.570352 progress 85 % (5 MB)
147 23:57:19.614183 progress 90 % (5 MB)
148 23:57:19.661955 progress 95 % (6 MB)
149 23:57:19.705765 progress 100 % (6 MB)
150 23:57:19.720559 6 MB downloaded in 1.00 s (6.61 MB/s)
151 23:57:19.721705 end: 1.5.1 http-download (duration 00:00:01) [common]
153 23:57:19.723953 end: 1.5 download-retry (duration 00:00:01) [common]
154 23:57:19.724654 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 23:57:19.725362 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 23:57:38.952322 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s
157 23:57:38.952929 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
158 23:57:38.953212 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
159 23:57:38.953975 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x
160 23:57:38.954444 makedir: /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin
161 23:57:38.954771 makedir: /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/tests
162 23:57:38.955084 makedir: /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/results
163 23:57:38.955419 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-add-keys
164 23:57:38.955951 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-add-sources
165 23:57:38.956488 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-background-process-start
166 23:57:38.957052 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-background-process-stop
167 23:57:38.957608 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-common-functions
168 23:57:38.958295 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-echo-ipv4
169 23:57:38.958796 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-install-packages
170 23:57:38.959273 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-installed-packages
171 23:57:38.959760 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-os-build
172 23:57:38.960325 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-probe-channel
173 23:57:38.960924 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-probe-ip
174 23:57:38.961494 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-target-ip
175 23:57:38.962069 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-target-mac
176 23:57:38.962570 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-target-storage
177 23:57:38.963056 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-case
178 23:57:38.963536 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-event
179 23:57:38.964013 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-feedback
180 23:57:38.964495 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-raise
181 23:57:38.964974 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-reference
182 23:57:38.965454 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-runner
183 23:57:38.965975 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-set
184 23:57:38.966480 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-test-shell
185 23:57:38.967058 Updating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-add-keys (debian)
186 23:57:38.967613 Updating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-add-sources (debian)
187 23:57:38.968124 Updating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-install-packages (debian)
188 23:57:38.968633 Updating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-installed-packages (debian)
189 23:57:38.969149 Updating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/bin/lava-os-build (debian)
190 23:57:38.969586 Creating /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/environment
191 23:57:38.969990 LAVA metadata
192 23:57:38.970257 - LAVA_JOB_ID=931452
193 23:57:38.970471 - LAVA_DISPATCHER_IP=192.168.6.3
194 23:57:38.970836 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
195 23:57:38.971812 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 23:57:38.972125 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
197 23:57:38.972333 skipped lava-vland-overlay
198 23:57:38.972574 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 23:57:38.972826 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
200 23:57:38.973041 skipped lava-multinode-overlay
201 23:57:38.973281 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 23:57:38.973530 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
203 23:57:38.973778 Loading test definitions
204 23:57:38.974081 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
205 23:57:38.974314 Using /lava-931452 at stage 0
206 23:57:38.975417 uuid=931452_1.6.2.4.1 testdef=None
207 23:57:38.975713 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 23:57:38.975971 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
209 23:57:38.977507 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 23:57:38.978390 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
212 23:57:38.980306 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 23:57:38.981118 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
215 23:57:38.982936 runner path: /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/0/tests/0_timesync-off test_uuid 931452_1.6.2.4.1
216 23:57:38.983495 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 23:57:38.984304 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
219 23:57:38.984523 Using /lava-931452 at stage 0
220 23:57:38.984874 Fetching tests from https://github.com/kernelci/test-definitions.git
221 23:57:38.985165 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/0/tests/1_kselftest-dt'
222 23:57:42.315348 Running '/usr/bin/git checkout kernelci.org
223 23:57:42.601167 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 23:57:42.602664 uuid=931452_1.6.2.4.5 testdef=None
225 23:57:42.603014 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 23:57:42.603757 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
228 23:57:42.606618 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 23:57:42.607438 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
231 23:57:42.611193 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 23:57:42.612041 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
234 23:57:42.615634 runner path: /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/0/tests/1_kselftest-dt test_uuid 931452_1.6.2.4.5
235 23:57:42.615923 BOARD='beaglebone-black'
236 23:57:42.616125 BRANCH='mainline'
237 23:57:42.616320 SKIPFILE='/dev/null'
238 23:57:42.616516 SKIP_INSTALL='True'
239 23:57:42.616710 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
240 23:57:42.616907 TST_CASENAME=''
241 23:57:42.617101 TST_CMDFILES='dt'
242 23:57:42.617648 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 23:57:42.618454 Creating lava-test-runner.conf files
245 23:57:42.618659 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/931452/lava-overlay-wgeroj3x/lava-931452/0 for stage 0
246 23:57:42.619010 - 0_timesync-off
247 23:57:42.619245 - 1_kselftest-dt
248 23:57:42.619573 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 23:57:42.619849 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
250 23:58:05.872861 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 23:58:05.873312 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 23:58:05.873576 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 23:58:05.873871 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 23:58:05.874142 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 23:58:06.229469 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 23:58:06.229983 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 23:58:06.230265 extracting modules file /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s
258 23:58:07.122087 extracting modules file /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931452/extract-overlay-ramdisk-al7m1p_3/ramdisk
259 23:58:08.051226 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 23:58:08.051688 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 23:58:08.051934 [common] Applying overlay to NFS
262 23:58:08.052146 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931452/compress-overlay-rpvc3364/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s
263 23:58:10.817637 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 23:58:10.818142 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
265 23:58:10.818415 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
266 23:58:10.818719 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 23:58:10.818976 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 23:58:10.819233 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
269 23:58:10.819482 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 23:58:10.819735 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
271 23:58:10.819958 Building ramdisk /var/lib/lava/dispatcher/tmp/931452/extract-overlay-ramdisk-al7m1p_3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/931452/extract-overlay-ramdisk-al7m1p_3/ramdisk
272 23:58:11.887521 >> 78982 blocks
273 23:58:17.037849 Adding RAMdisk u-boot header.
274 23:58:17.038565 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/931452/extract-overlay-ramdisk-al7m1p_3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/931452/extract-overlay-ramdisk-al7m1p_3/ramdisk.cpio.gz.uboot
275 23:58:17.199157 output: Image Name:
276 23:58:17.199582 output: Created: Sun Nov 3 23:58:17 2024
277 23:58:17.199794 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 23:58:17.199999 output: Data Size: 15347004 Bytes = 14987.31 KiB = 14.64 MiB
279 23:58:17.200201 output: Load Address: 00000000
280 23:58:17.200401 output: Entry Point: 00000000
281 23:58:17.200598 output:
282 23:58:17.201294 rename /var/lib/lava/dispatcher/tmp/931452/extract-overlay-ramdisk-al7m1p_3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot
283 23:58:17.201718 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 23:58:17.202278 end: 1.6 prepare-tftp-overlay (duration 00:00:57) [common]
285 23:58:17.202865 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:47) [common]
286 23:58:17.203374 No LXC device requested
287 23:58:17.203925 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 23:58:17.204485 start: 1.8 deploy-device-env (timeout 00:08:47) [common]
289 23:58:17.205025 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 23:58:17.205478 Checking files for TFTP limit of 4294967296 bytes.
291 23:58:17.208426 end: 1 tftp-deploy (duration 00:01:13) [common]
292 23:58:17.209052 start: 2 uboot-action (timeout 00:05:00) [common]
293 23:58:17.209623 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 23:58:17.210217 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 23:58:17.210770 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 23:58:17.211586 substitutions:
297 23:58:17.212040 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 23:58:17.212487 - {DTB_ADDR}: 0x88000000
299 23:58:17.212924 - {DTB}: 931452/tftp-deploy-l8wn_vew/dtb/am335x-boneblack.dtb
300 23:58:17.213360 - {INITRD}: 931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot
301 23:58:17.213794 - {KERNEL_ADDR}: 0x82000000
302 23:58:17.214261 - {KERNEL}: 931452/tftp-deploy-l8wn_vew/kernel/zImage
303 23:58:17.214695 - {LAVA_MAC}: None
304 23:58:17.215168 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s
305 23:58:17.215603 - {NFS_SERVER_IP}: 192.168.6.3
306 23:58:17.216035 - {PRESEED_CONFIG}: None
307 23:58:17.216461 - {PRESEED_LOCAL}: None
308 23:58:17.216886 - {RAMDISK_ADDR}: 0x83000000
309 23:58:17.217310 - {RAMDISK}: 931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot
310 23:58:17.217739 - {ROOT_PART}: None
311 23:58:17.218192 - {ROOT}: None
312 23:58:17.218617 - {SERVER_IP}: 192.168.6.3
313 23:58:17.219039 - {TEE_ADDR}: 0x83000000
314 23:58:17.219457 - {TEE}: None
315 23:58:17.219879 Parsed boot commands:
316 23:58:17.220287 - setenv autoload no
317 23:58:17.220708 - setenv initrd_high 0xffffffff
318 23:58:17.221129 - setenv fdt_high 0xffffffff
319 23:58:17.221548 - dhcp
320 23:58:17.221995 - setenv serverip 192.168.6.3
321 23:58:17.222416 - tftp 0x82000000 931452/tftp-deploy-l8wn_vew/kernel/zImage
322 23:58:17.222839 - tftp 0x83000000 931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot
323 23:58:17.223263 - setenv initrd_size ${filesize}
324 23:58:17.223681 - tftp 0x88000000 931452/tftp-deploy-l8wn_vew/dtb/am335x-boneblack.dtb
325 23:58:17.224102 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 23:58:17.224534 - bootz 0x82000000 0x83000000 0x88000000
327 23:58:17.225068 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 23:58:17.226768 start: 2.3 connect-device (timeout 00:05:00) [common]
330 23:58:17.227235 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 23:58:17.242951 Setting prompt string to ['lava-test: # ']
332 23:58:17.244537 end: 2.3 connect-device (duration 00:00:00) [common]
333 23:58:17.245188 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 23:58:17.245798 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 23:58:17.246438 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 23:58:17.247899 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 23:58:17.285899 >> OK - accepted request
338 23:58:17.287881 Returned 0 in 0 seconds
339 23:58:17.389013 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 23:58:17.390815 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 23:58:17.391428 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 23:58:17.392006 Setting prompt string to ['Hit any key to stop autoboot']
344 23:58:17.392508 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 23:58:17.394193 Trying 192.168.56.22...
346 23:58:17.394729 Connected to conserv3.
347 23:58:17.395198 Escape character is '^]'.
348 23:58:17.395660
349 23:58:17.396121 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 23:58:17.396587
351 23:58:26.341229
352 23:58:26.348097 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 23:58:26.348632 Trying to boot from MMC1
354 23:58:26.934259
355 23:58:26.934865
356 23:58:26.939910 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 23:58:26.940410
358 23:58:26.940870 CPU : AM335X-GP rev 2.0
359 23:58:26.944842 Model: TI AM335x BeagleBone Black
360 23:58:26.945337 DRAM: 512 MiB
361 23:58:30.392129
362 23:58:30.398858 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 23:58:30.399439 Trying to boot from MMC1
364 23:58:30.985185
365 23:58:30.985879
366 23:58:30.990658 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 23:58:30.991152
368 23:58:30.991617 CPU : AM335X-GP rev 2.0
369 23:58:30.995745 Model: TI AM335x BeagleBone Black
370 23:58:30.996233 DRAM: 512 MiB
371 23:58:33.090821
372 23:58:33.097570 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 23:58:33.098121 Trying to boot from MMC1
374 23:58:33.683668
375 23:58:33.684199
376 23:58:33.689150 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 23:58:33.689635
378 23:58:33.690139 CPU : AM335X-GP rev 2.0
379 23:58:33.693522 Model: TI AM335x BeagleBone Black
380 23:58:33.694029 DRAM: 512 MiB
381 23:58:33.778909 Core: 160 devices, 18 uclasses, devicetree: separate
382 23:58:33.792616 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 23:58:34.192579 NAND: 0 MiB
384 23:58:34.203550 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 23:58:34.278128 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 23:58:34.299493 <ethaddr> not set. Validating first E-fuse MAC
387 23:58:34.329323 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 23:58:34.387831 Hit any key to stop autoboot: 2
390 23:58:34.388656 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 23:58:34.389295 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 23:58:34.389838 Setting prompt string to ['=>']
393 23:58:34.390363 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 23:58:34.397707 0
395 23:58:34.398655 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 23:58:34.399201 Sending with 10 millisecond of delay
398 23:58:35.534151 => setenv autoload no
399 23:58:35.544779 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 23:58:35.547550 setenv autoload no
401 23:58:35.548061 Sending with 10 millisecond of delay
403 23:58:37.344361 => setenv initrd_high 0xffffffff
404 23:58:37.355108 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 23:58:37.355632 setenv initrd_high 0xffffffff
406 23:58:37.356111 Sending with 10 millisecond of delay
408 23:58:38.972130 => setenv fdt_high 0xffffffff
409 23:58:38.982948 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
410 23:58:38.983775 setenv fdt_high 0xffffffff
411 23:58:38.984300 Sending with 10 millisecond of delay
413 23:58:39.275867 => dhcp
414 23:58:39.286566 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 23:58:39.287081 dhcp
416 23:58:39.287320 link up on port 0, speed 100, full duplex
417 23:58:39.287532 BOOTP broadcast 1
418 23:58:39.540733 BOOTP broadcast 2
419 23:58:40.042725 BOOTP broadcast 3
420 23:58:41.044740 BOOTP broadcast 4
421 23:58:41.157470 DHCP client bound to address 192.168.6.23 (1865 ms)
422 23:58:41.158462 Sending with 10 millisecond of delay
424 23:58:42.834915 => setenv serverip 192.168.6.3
425 23:58:42.845743 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
426 23:58:42.846658 setenv serverip 192.168.6.3
427 23:58:42.847441 Sending with 10 millisecond of delay
429 23:58:46.329726 => tftp 0x82000000 931452/tftp-deploy-l8wn_vew/kernel/zImage
430 23:58:46.340610 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
431 23:58:46.341581 tftp 0x82000000 931452/tftp-deploy-l8wn_vew/kernel/zImage
432 23:58:46.342105 link up on port 0, speed 100, full duplex
433 23:58:46.345431 Using ethernet@4a100000 device
434 23:58:46.350994 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
435 23:58:46.351468 Filename '931452/tftp-deploy-l8wn_vew/kernel/zImage'.
436 23:58:46.357168 Load address: 0x82000000
437 23:58:48.647010 Loading: *################################################## 11.5 MiB
438 23:58:48.647668 5 MiB/s
439 23:58:48.648136 done
440 23:58:48.651035 Bytes transferred = 12042752 (b7c200 hex)
441 23:58:48.651808 Sending with 10 millisecond of delay
443 23:58:53.097242 => tftp 0x83000000 931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot
444 23:58:53.108103 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
445 23:58:53.109037 tftp 0x83000000 931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot
446 23:58:53.109503 link up on port 0, speed 100, full duplex
447 23:58:53.113187 Using ethernet@4a100000 device
448 23:58:53.118691 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
449 23:58:53.127266 Filename '931452/tftp-deploy-l8wn_vew/ramdisk/ramdisk.cpio.gz.uboot'.
450 23:58:53.127789 Load address: 0x83000000
451 23:58:56.049057 Loading: *################################################## 14.6 MiB
452 23:58:56.049704 5 MiB/s
453 23:58:56.050230 done
454 23:58:56.052994 Bytes transferred = 15347068 (ea2d7c hex)
455 23:58:56.053773 Sending with 10 millisecond of delay
457 23:58:57.911137 => setenv initrd_size ${filesize}
458 23:58:57.921980 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
459 23:58:57.922826 setenv initrd_size ${filesize}
460 23:58:57.923579 Sending with 10 millisecond of delay
462 23:59:02.069099 => tftp 0x88000000 931452/tftp-deploy-l8wn_vew/dtb/am335x-boneblack.dtb
463 23:59:02.079981 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
464 23:59:02.080913 tftp 0x88000000 931452/tftp-deploy-l8wn_vew/dtb/am335x-boneblack.dtb
465 23:59:02.081387 link up on port 0, speed 100, full duplex
466 23:59:02.085410 Using ethernet@4a100000 device
467 23:59:02.091196 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
468 23:59:02.094188 Filename '931452/tftp-deploy-l8wn_vew/dtb/am335x-boneblack.dtb'.
469 23:59:02.107506 Load address: 0x88000000
470 23:59:02.115366 Loading: *################################################## 68.9 KiB
471 23:59:02.115871 4.8 MiB/s
472 23:59:02.116313 done
473 23:59:02.119766 Bytes transferred = 70568 (113a8 hex)
474 23:59:02.120540 Sending with 10 millisecond of delay
476 23:59:15.298350 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 23:59:15.309251 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
478 23:59:15.411828 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 23:59:15.412735 Sending with 10 millisecond of delay
481 23:59:17.753187 => bootz 0x82000000 0x83000000 0x88000000
482 23:59:17.764354 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 23:59:17.765148 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
484 23:59:17.766546 bootz 0x82000000 0x83000000 0x88000000
485 23:59:17.767162 Kernel image @ 0x82000000 [ 0x000000 - 0xb7c200 ]
486 23:59:17.767739 ## Loading init Ramdisk from Legacy Image at 83000000 ...
487 23:59:17.771868 Image Name:
488 23:59:17.772468 Created: 2024-11-03 23:58:17 UTC
489 23:59:17.777568 Image Type: ARM Linux RAMDisk Image (uncompressed)
490 23:59:17.783060 Data Size: 15347004 Bytes = 14.6 MiB
491 23:59:17.783654 Load Address: 00000000
492 23:59:17.789184 Entry Point: 00000000
493 23:59:17.963663 Verifying Checksum ... OK
494 23:59:17.964392 ## Flattened Device Tree blob at 88000000
495 23:59:17.970194 Booting using the fdt blob at 0x88000000
496 23:59:17.970791 Working FDT set to 88000000
497 23:59:17.975743 Using Device Tree in place at 88000000, end 880143a7
498 23:59:17.980061 Working FDT set to 88000000
499 23:59:17.993365
500 23:59:17.994012 Starting kernel ...
501 23:59:17.994597
502 23:59:17.995710 end: 2.4.3 bootloader-commands (duration 00:00:44) [common]
503 23:59:17.996476 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
504 23:59:17.997097 Setting prompt string to ['Linux version [0-9]']
505 23:59:17.997712 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 23:59:17.998403 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 23:59:18.890060 [ 0.000000] Booting Linux on physical CPU 0x0
508 23:59:18.896310 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
509 23:59:18.897059 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 23:59:18.897701 Setting prompt string to []
511 23:59:18.898447 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 23:59:18.899081 Using line separator: #'\n'#
513 23:59:18.899644 No login prompt set.
514 23:59:18.900238 Parsing kernel messages
515 23:59:18.900794 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 23:59:18.901940 [login-action] Waiting for messages, (timeout 00:03:58)
517 23:59:18.902548 Waiting using forced prompt support (timeout 00:01:59)
518 23:59:18.909917 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j361044-arm-clang-16-multi-v7-defconfig-t5j8q) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Sun Nov 3 22:58:49 UTC 2024
519 23:59:18.915632 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 23:59:18.927065 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 23:59:18.932822 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 23:59:18.938567 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 23:59:18.944391 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 23:59:18.944977 [ 0.000000] Memory policy: Data cache writeback
525 23:59:18.950972 [ 0.000000] efi: UEFI not found.
526 23:59:18.959838 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 23:59:18.960426 [ 0.000000] Zone ranges:
528 23:59:18.971391 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 23:59:18.971985 [ 0.000000] Normal empty
530 23:59:18.977043 [ 0.000000] HighMem empty
531 23:59:18.977621 [ 0.000000] Movable zone start for each node
532 23:59:18.982688 [ 0.000000] Early memory node ranges
533 23:59:18.988521 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 23:59:18.996616 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 23:59:19.014704 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 23:59:19.020353 [ 0.000000] AM335X ES2.0 (sgx neon)
537 23:59:19.032082 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
538 23:59:19.049773 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 23:59:19.061327 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 23:59:19.067066 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 23:59:19.072798 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 23:59:19.082815 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 23:59:19.112174 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 23:59:19.118105 <6>[ 0.000000] trace event string verifier disabled
545 23:59:19.118712 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 23:59:19.123828 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 23:59:19.135297 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 23:59:19.140999 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 23:59:19.148290 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 23:59:19.163636 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 23:59:19.181317 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 23:59:19.187997 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 23:59:19.288052 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 23:59:19.296634 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 23:59:19.309078 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 23:59:19.317371 <6>[ 0.019191] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 23:59:19.326853 <6>[ 0.034240] Console: colour dummy device 80x30
558 23:59:19.333033 Matched prompt #6: WARNING:
559 23:59:19.333514 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 23:59:19.338414 <3>[ 0.039142] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 23:59:19.341213 <3>[ 0.046219] This ensures that you still see kernel messages. Please
562 23:59:19.347410 <3>[ 0.052947] update your kernel commandline.
563 23:59:19.387800 <6>[ 0.057563] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 23:59:19.393570 <6>[ 0.096201] CPU: Testing write buffer coherency: ok
565 23:59:19.399597 <6>[ 0.101573] CPU0: Spectre v2: using BPIALL workaround
566 23:59:19.400037 <6>[ 0.107041] pid_max: default: 32768 minimum: 301
567 23:59:19.410990 <6>[ 0.112240] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 23:59:19.418000 <6>[ 0.120065] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 23:59:19.425100 <6>[ 0.129514] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 23:59:19.433587 <6>[ 0.136495] Setting up static identity map for 0x80300000 - 0x803000ac
571 23:59:19.439409 <6>[ 0.146208] rcu: Hierarchical SRCU implementation.
572 23:59:19.447034 <6>[ 0.151501] rcu: Max phase no-delay instances is 1000.
573 23:59:19.455856 <6>[ 0.162925] EFI services will not be available.
574 23:59:19.461674 <6>[ 0.168221] smp: Bringing up secondary CPUs ...
575 23:59:19.467418 <6>[ 0.173280] smp: Brought up 1 node, 1 CPU
576 23:59:19.475652 <6>[ 0.177681] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 23:59:19.481585 <6>[ 0.184453] CPU: All CPU(s) started in SVC mode.
578 23:59:19.496578 <6>[ 0.189657] Memory: 404436K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50612K reserved, 65536K cma-reserved, 0K highmem)
579 23:59:19.497028 <6>[ 0.205959] devtmpfs: initialized
580 23:59:19.522778 <6>[ 0.224011] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 23:59:19.531006 <6>[ 0.232633] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 23:59:19.540246 <6>[ 0.243093] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 23:59:19.550985 <6>[ 0.255427] pinctrl core: initialized pinctrl subsystem
584 23:59:19.560591 <6>[ 0.266303] DMI not present or invalid.
585 23:59:19.568911 <6>[ 0.272192] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 23:59:19.578601 <6>[ 0.281187] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 23:59:19.593737 <6>[ 0.292838] thermal_sys: Registered thermal governor 'step_wise'
588 23:59:19.594413 <6>[ 0.293014] cpuidle: using governor menu
589 23:59:19.621263 <6>[ 0.328544] No ATAGs?
590 23:59:19.627454 <6>[ 0.331286] hw-breakpoint: debug architecture 0x4 unsupported.
591 23:59:19.637850 <6>[ 0.343429] Serial: AMBA PL011 UART driver
592 23:59:19.668242 <6>[ 0.375502] iommu: Default domain type: Translated
593 23:59:19.677337 <6>[ 0.380853] iommu: DMA domain TLB invalidation policy: strict mode
594 23:59:19.703901 <5>[ 0.410539] SCSI subsystem initialized
595 23:59:19.709775 <6>[ 0.415460] usbcore: registered new interface driver usbfs
596 23:59:19.715660 <6>[ 0.421525] usbcore: registered new interface driver hub
597 23:59:19.722434 <6>[ 0.427313] usbcore: registered new device driver usb
598 23:59:19.728166 <6>[ 0.433882] pps_core: LinuxPPS API ver. 1 registered
599 23:59:19.739679 <6>[ 0.439273] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 23:59:19.746900 <6>[ 0.449010] PTP clock support registered
601 23:59:19.747490 <6>[ 0.453499] EDAC MC: Ver: 3.0.0
602 23:59:19.801009 <6>[ 0.505756] scmi_core: SCMI protocol bus registered
603 23:59:19.815745 <6>[ 0.522423] vgaarb: loaded
604 23:59:19.821888 <6>[ 0.526224] clocksource: Switched to clocksource dmtimer
605 23:59:19.856835 <6>[ 0.563822] NET: Registered PF_INET protocol family
606 23:59:19.869660 <6>[ 0.569527] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 23:59:19.876651 <6>[ 0.578553] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 23:59:19.887989 <6>[ 0.587486] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 23:59:19.893771 <6>[ 0.595732] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 23:59:19.899662 <6>[ 0.604019] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 23:59:19.905398 <6>[ 0.611746] TCP: Hash tables configured (established 4096 bind 4096)
612 23:59:19.916945 <6>[ 0.618667] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 23:59:19.922890 <6>[ 0.625683] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 23:59:19.929254 <6>[ 0.633292] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 23:59:20.021686 <6>[ 0.723212] RPC: Registered named UNIX socket transport module.
616 23:59:20.022351 <6>[ 0.729661] RPC: Registered udp transport module.
617 23:59:20.027329 <6>[ 0.734771] RPC: Registered tcp transport module.
618 23:59:20.033070 <6>[ 0.739890] RPC: Registered tcp-with-tls transport module.
619 23:59:20.046122 <6>[ 0.745798] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 23:59:20.046713 <6>[ 0.752722] PCI: CLS 0 bytes, default 64
621 23:59:20.053319 <5>[ 0.758593] Initialise system trusted keyrings
622 23:59:20.071757 <6>[ 0.775943] Trying to unpack rootfs image as initramfs...
623 23:59:20.145492 <6>[ 0.846556] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 23:59:20.150245 <6>[ 0.854090] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 23:59:20.186181 <5>[ 0.893420] NFS: Registering the id_resolver key type
626 23:59:20.191866 <5>[ 0.899076] Key type id_resolver registered
627 23:59:20.197692 <5>[ 0.903653] Key type id_legacy registered
628 23:59:20.203446 <6>[ 0.908122] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 23:59:20.213023 <6>[ 0.915288] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 23:59:20.289555 <5>[ 0.996962] Key type asymmetric registered
631 23:59:20.295546 <5>[ 1.001488] Asymmetric key parser 'x509' registered
632 23:59:20.303899 <6>[ 1.007045] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 23:59:20.309759 <6>[ 1.014937] io scheduler mq-deadline registered
634 23:59:20.318475 <6>[ 1.019917] io scheduler kyber registered
635 23:59:20.319119 <6>[ 1.024376] io scheduler bfq registered
636 23:59:20.422786 <6>[ 1.126453] ledtrig-cpu: registered to indicate activity on CPUs
637 23:59:20.700408 <6>[ 1.403853] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 23:59:20.734759 <6>[ 1.441717] msm_serial: driver initialized
639 23:59:20.740727 <6>[ 1.446765] SuperH (H)SCI(F) driver initialized
640 23:59:20.746702 <6>[ 1.451887] STMicroelectronics ASC driver initialized
641 23:59:20.751859 <6>[ 1.457581] STM32 USART driver initialized
642 23:59:20.881694 <6>[ 1.588439] brd: module loaded
643 23:59:20.911620 <6>[ 1.618295] loop: module loaded
644 23:59:20.957963 <6>[ 1.664334] CAN device driver interface
645 23:59:20.964742 <6>[ 1.669667] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 23:59:20.970514 <6>[ 1.676822] e1000e: Intel(R) PRO/1000 Network Driver
647 23:59:20.976983 <6>[ 1.682212] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 23:59:20.982747 <6>[ 1.688676] igb: Intel(R) Gigabit Ethernet Network Driver
649 23:59:20.990273 <6>[ 1.694497] igb: Copyright (c) 2007-2014 Intel Corporation.
650 23:59:21.002276 <6>[ 1.703847] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 23:59:21.008076 <6>[ 1.710024] usbcore: registered new interface driver pegasus
652 23:59:21.013909 <6>[ 1.716157] usbcore: registered new interface driver asix
653 23:59:21.019606 <6>[ 1.722047] usbcore: registered new interface driver ax88179_178a
654 23:59:21.025352 <6>[ 1.728641] usbcore: registered new interface driver cdc_ether
655 23:59:21.031177 <6>[ 1.734939] usbcore: registered new interface driver smsc75xx
656 23:59:21.036965 <6>[ 1.741184] usbcore: registered new interface driver smsc95xx
657 23:59:21.042821 <6>[ 1.747425] usbcore: registered new interface driver net1080
658 23:59:21.048579 <6>[ 1.753545] usbcore: registered new interface driver cdc_subset
659 23:59:21.054298 <6>[ 1.759957] usbcore: registered new interface driver zaurus
660 23:59:21.061941 <6>[ 1.766005] usbcore: registered new interface driver cdc_ncm
661 23:59:21.071893 <6>[ 1.775554] usbcore: registered new interface driver usb-storage
662 23:59:21.081652 <6>[ 1.787060] i2c_dev: i2c /dev entries driver
663 23:59:21.106486 <5>[ 1.805799] cpuidle: enable-method property 'ti,am3352' found operations
664 23:59:21.112372 <6>[ 1.815377] sdhci: Secure Digital Host Controller Interface driver
665 23:59:21.119841 <6>[ 1.822148] sdhci: Copyright(c) Pierre Ossman
666 23:59:21.127172 <6>[ 1.828665] Synopsys Designware Multimedia Card Interface Driver
667 23:59:21.132725 <6>[ 1.836726] sdhci-pltfm: SDHCI platform and OF driver helper
668 23:59:21.146877 <6>[ 1.846776] usbcore: registered new interface driver usbhid
669 23:59:21.147467 <6>[ 1.852805] usbhid: USB HID core driver
670 23:59:21.159679 <6>[ 1.864424] NET: Registered PF_INET6 protocol family
671 23:59:21.621854 <6>[ 2.329127] Segment Routing with IPv6
672 23:59:21.627744 <6>[ 2.333274] In-situ OAM (IOAM) with IPv6
673 23:59:21.634428 <6>[ 2.337820] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 23:59:21.641852 <6>[ 2.345178] NET: Registered PF_PACKET protocol family
675 23:59:21.647600 <6>[ 2.350740] can: controller area network core
676 23:59:21.648196 <6>[ 2.355574] NET: Registered PF_CAN protocol family
677 23:59:21.653366 <6>[ 2.360815] can: raw protocol
678 23:59:21.656230 <6>[ 2.364142] can: broadcast manager protocol
679 23:59:21.662861 <6>[ 2.368740] can: netlink gateway - max_hops=1
680 23:59:21.668902 <5>[ 2.374244] Key type dns_resolver registered
681 23:59:21.674652 <6>[ 2.379323] ThumbEE CPU extension supported.
682 23:59:21.680906 <5>[ 2.384029] Registering SWP/SWPB emulation handler
683 23:59:21.686306 <3>[ 2.389739] omap_voltage_late_init: Voltage driver support not added
684 23:59:21.902461 <5>[ 2.607471] Loading compiled-in X.509 certificates
685 23:59:22.021282 <6>[ 2.715723] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 23:59:22.028477 <6>[ 2.732434] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 23:59:22.055384 <3>[ 2.756740] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 23:59:22.249063 <3>[ 2.950396] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 23:59:22.449901 <6>[ 3.155588] OMAP GPIO hardware version 0.1
690 23:59:22.469939 <6>[ 3.174572] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 23:59:22.524497 <4>[ 3.227944] at24 2-0054: supply vcc not found, using dummy regulator
692 23:59:22.557896 <4>[ 3.262017] at24 2-0055: supply vcc not found, using dummy regulator
693 23:59:22.598650 <4>[ 3.302044] at24 2-0056: supply vcc not found, using dummy regulator
694 23:59:22.643946 <4>[ 3.347776] at24 2-0057: supply vcc not found, using dummy regulator
695 23:59:22.677127 <6>[ 3.381263] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 23:59:22.723309 <3>[ 3.423455] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 23:59:22.747979 <6>[ 3.444575] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 23:59:22.770562 <4>[ 3.471059] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 23:59:22.778292 <4>[ 3.480433] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 23:59:22.843394 <6>[ 3.546935] omap_rng 48310000.rng: Random Number Generator ver. 20
701 23:59:22.867171 <5>[ 3.573525] random: crng init done
702 23:59:22.914631 <6>[ 3.616660] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 23:59:22.937542 <6>[ 3.643301] Freeing initrd memory: 14988K
704 23:59:22.987590 <6>[ 3.688728] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 23:59:22.993424 <6>[ 3.699093] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 23:59:23.005180 <6>[ 3.706447] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 23:59:23.011113 <6>[ 3.713895] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 23:59:23.022526 <6>[ 3.722037] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 23:59:23.030100 <6>[ 3.733677] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
710 23:59:23.043190 <5>[ 3.742777] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 23:59:23.071407 <3>[ 3.773042] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 23:59:23.077175 <6>[ 3.781658] edma 49000000.dma: TI EDMA DMA engine driver
713 23:59:23.149343 <3>[ 3.850311] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 23:59:23.164215 <6>[ 3.864758] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 23:59:23.177210 <3>[ 3.882012] l3-aon-clkctrl:0000:0: failed to disable
716 23:59:23.233348 <6>[ 3.934934] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 23:59:23.239152 <6>[ 3.944456] printk: legacy console [ttyS0] enabled
718 23:59:23.244707 <6>[ 3.944456] printk: legacy console [ttyS0] enabled
719 23:59:23.250395 <6>[ 3.954788] printk: legacy bootconsole [omap8250] disabled
720 23:59:23.256242 <6>[ 3.954788] printk: legacy bootconsole [omap8250] disabled
721 23:59:23.286403 <4>[ 3.987054] tps65217-pmic: Failed to locate of_node [id: -1]
722 23:59:23.290037 <4>[ 3.994452] tps65217-bl: Failed to locate of_node [id: -1]
723 23:59:23.306680 <6>[ 4.014351] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 23:59:23.325188 <6>[ 4.021345] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 23:59:23.336901 <6>[ 4.035045] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 23:59:23.342592 <6>[ 4.046942] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 23:59:23.364915 <6>[ 4.066887] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 23:59:23.370775 <6>[ 4.075946] sdhci-omap 48060000.mmc: Got CD GPIO
729 23:59:23.377804 <4>[ 4.081164] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 23:59:23.393498 <4>[ 4.094773] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 23:59:23.399936 <4>[ 4.103479] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 23:59:23.409796 <4>[ 4.112186] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 23:59:23.448417 <6>[ 4.151446] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 23:59:23.471251 <6>[ 4.172695] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 23:59:23.479256 <6>[ 4.181295] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 23:59:23.490537 <6>[ 4.193932] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 23:59:23.538031 <6>[ 4.235446] mmc0: new high speed SDHC card at address 0001
738 23:59:23.538642 <6>[ 4.243541] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
739 23:59:23.545004 <6>[ 4.252338] mmcblk0: p1
740 23:59:23.578255 <6>[ 4.277485] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 23:59:23.599050 <6>[ 4.297377] mmc1: new high speed MMC card at address 0001
742 23:59:23.599652 <6>[ 4.304567] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
743 23:59:23.607438 <6>[ 4.314344] mmcblk1:
744 23:59:23.615672 <6>[ 4.317666] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
745 23:59:23.621220 <6>[ 4.325448] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
746 23:59:23.629264 <6>[ 4.332946] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
747 23:59:25.655017 <6>[ 6.357261] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
748 23:59:25.758996 <5>[ 6.386238] Sending DHCP requests ., OK
749 23:59:25.770331 <6>[ 6.470669] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
750 23:59:25.770933 <6>[ 6.478848] IP-Config: Complete:
751 23:59:25.784526 <6>[ 6.482388] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
752 23:59:25.790345 <6>[ 6.492914] host=192.168.6.23, domain=, nis-domain=(none)
753 23:59:25.795923 <6>[ 6.499129] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
754 23:59:25.802534 <6>[ 6.499165] nameserver0=10.255.253.1
755 23:59:25.811692 <6>[ 6.511779] clk: Disabling unused clocks
756 23:59:25.812259 <6>[ 6.516552] PM: genpd: Disabling unused power domains
757 23:59:25.829326 <6>[ 6.533272] Freeing unused kernel image (initmem) memory: 2048K
758 23:59:25.836123 <6>[ 6.543158] Run /init as init process
759 23:59:25.863263 Loading, please wait...
760 23:59:25.939885 Starting systemd-udevd version 252.22-1~deb12u1
761 23:59:28.970368 <4>[ 9.670752] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 23:59:29.137556 <4>[ 9.837945] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 23:59:29.252318 <6>[ 9.960233] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 23:59:29.263113 <6>[ 9.965912] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 23:59:29.502055 <6>[ 10.208318] hub 1-0:1.0: USB hub found
766 23:59:29.541014 <6>[ 10.247249] hub 1-0:1.0: 1 port detected
767 23:59:29.790085 <6>[ 10.496069] tda998x 0-0070: found TDA19988
768 23:59:32.575077 Begin: Loading essential drivers ... done.
769 23:59:32.585075 Begin: Running /scripts/init-premount ... done.
770 23:59:32.596259 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 23:59:32.604216 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 23:59:32.608618 Device /sys/class/net/eth0 found
773 23:59:32.609192 done.
774 23:59:32.690211 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 23:59:32.781756 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
776 23:59:33.085979 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 23:59:33.091433 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 23:59:33.096990 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 23:59:33.108244 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 23:59:33.108846 rootserver: 192.168.6.1 rootpath:
781 23:59:33.111680 filename :
782 23:59:33.192317 done.
783 23:59:33.201501 Begin: Running /scripts/nfs-bottom ... done.
784 23:59:33.282249 Begin: Running /scripts/init-bottom ... done.
785 23:59:34.711279 <30>[ 15.414757] systemd[1]: System time before build time, advancing clock.
786 23:59:34.926072 <30>[ 15.603301] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
787 23:59:34.935513 <30>[ 15.640734] systemd[1]: Detected architecture arm.
788 23:59:34.948074
789 23:59:34.948671 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
790 23:59:34.949236
791 23:59:34.972261 <30>[ 15.676423] systemd[1]: Hostname set to <debian-bookworm-armhf>.
792 23:59:37.167078 <30>[ 17.870035] systemd[1]: Queued start job for default target graphical.target.
793 23:59:37.183979 <30>[ 17.884700] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
794 23:59:37.191429 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
795 23:59:37.221949 <30>[ 17.922311] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
796 23:59:37.229319 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
797 23:59:37.261113 <30>[ 17.962563] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
798 23:59:37.274300 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
799 23:59:37.296620 <30>[ 17.998139] systemd[1]: Created slice user.slice - User and Session Slice.
800 23:59:37.303331 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
801 23:59:37.332917 <30>[ 18.027665] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
802 23:59:37.338910 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
803 23:59:37.366909 <30>[ 18.067335] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
804 23:59:37.378053 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
805 23:59:37.404419 <30>[ 18.097295] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
806 23:59:37.418487 <30>[ 18.119947] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
807 23:59:37.424072 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
808 23:59:37.445081 <30>[ 18.146734] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
809 23:59:37.453277 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
810 23:59:37.475796 <30>[ 18.177133] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
811 23:59:37.484212 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
812 23:59:37.505616 <30>[ 18.207258] systemd[1]: Reached target paths.target - Path Units.
813 23:59:37.510709 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
814 23:59:37.535161 <30>[ 18.236839] systemd[1]: Reached target remote-fs.target - Remote File Systems.
815 23:59:37.542528 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
816 23:59:37.565067 <30>[ 18.266817] systemd[1]: Reached target slices.target - Slice Units.
817 23:59:37.570560 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
818 23:59:37.595249 <30>[ 18.296988] systemd[1]: Reached target swap.target - Swaps.
819 23:59:37.599365 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
820 23:59:37.625579 <30>[ 18.327022] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
821 23:59:37.633515 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
822 23:59:37.656687 <30>[ 18.357986] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
823 23:59:37.665082 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
824 23:59:37.744607 <30>[ 18.441159] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
825 23:59:37.757464 <30>[ 18.458924] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
826 23:59:37.765904 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
827 23:59:37.788469 <30>[ 18.489029] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
828 23:59:37.795897 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
829 23:59:37.818046 <30>[ 18.519429] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
830 23:59:37.826341 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
831 23:59:37.849529 <30>[ 18.550899] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
832 23:59:37.855129 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
833 23:59:37.887843 <30>[ 18.588020] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
834 23:59:37.895365 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
835 23:59:37.922469 <30>[ 18.618062] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
836 23:59:37.941206 <30>[ 18.636749] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
837 23:59:37.985443 <30>[ 18.687875] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
838 23:59:38.005150 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
839 23:59:38.074737 <30>[ 18.776986] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
840 23:59:38.090637 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
841 23:59:38.159401 <30>[ 18.860757] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
842 23:59:38.193995 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
843 23:59:38.235754 <30>[ 18.937693] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
844 23:59:38.264199 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
845 23:59:38.315200 <30>[ 19.017435] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
846 23:59:38.343785 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
847 23:59:38.396680 <30>[ 19.099542] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
848 23:59:38.423757 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
849 23:59:38.475916 <30>[ 19.177552] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
850 23:59:38.495285 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
851 23:59:38.555026 <30>[ 19.257659] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
852 23:59:38.571809 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
853 23:59:38.634734 <30>[ 19.337417] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
854 23:59:38.663833 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
855 23:59:38.693382 <28>[ 19.388530] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
856 23:59:38.701903 <28>[ 19.403705] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
857 23:59:38.744520 <30>[ 19.447649] systemd[1]: Starting systemd-journald.service - Journal Service...
858 23:59:38.763410 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
859 23:59:38.835147 <30>[ 19.537577] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
860 23:59:38.855602 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
861 23:59:38.885273 <30>[ 19.587913] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
862 23:59:38.904956 Starting [0;1;39msystemd-network-g… units from Kernel command line...
863 23:59:38.968291 <30>[ 19.669342] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
864 23:59:39.026583 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
865 23:59:39.112295 <30>[ 19.814137] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
866 23:59:39.166363 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
867 23:59:39.236554 <30>[ 19.939336] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
868 23:59:39.299913 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
869 23:59:39.328331 <30>[ 20.030838] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
870 23:59:39.367346 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
871 23:59:39.390044 <30>[ 20.091561] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
872 23:59:39.418779 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
873 23:59:39.575553 <30>[ 20.278908] systemd[1]: modprobe@configfs.service: Deactivated successfully.
874 23:59:39.605772 <30>[ 20.307964] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
875 23:59:39.634822 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
876 23:59:39.655650 <30>[ 20.359158] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
877 23:59:39.695020 <30>[ 20.396935] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
878 23:59:39.703449 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
879 23:59:39.726016 <30>[ 20.427950] systemd[1]: Started systemd-journald.service - Journal Service.
880 23:59:39.732853 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
881 23:59:39.766849 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
882 23:59:39.796526 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
883 23:59:39.819772 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
884 23:59:39.859412 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
885 23:59:39.887639 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
886 23:59:39.915424 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
887 23:59:39.937424 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
888 23:59:39.965327 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
889 23:59:40.042253 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
890 23:59:40.098637 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
891 23:59:40.174845 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
892 23:59:40.280274 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
893 23:59:40.383499 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 23:59:40.467124 <46>[ 21.169772] systemd-journald[163]: Received client request to flush runtime journal.
895 23:59:40.542857 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
896 23:59:40.563284 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
897 23:59:41.455814 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
898 23:59:41.774664 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
899 23:59:41.854857 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
900 23:59:42.180865 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
901 23:59:42.409176 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
902 23:59:42.437311 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
903 23:59:42.466019 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
904 23:59:42.536451 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
905 23:59:42.577613 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
906 23:59:43.486551 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
907 23:59:43.555106 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
908 23:59:44.077689 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
909 23:59:44.203293 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
910 23:59:44.273565 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
911 23:59:46.215612 [[0m[0;31m* [0m] (1 of 5) Job systemd-update-utmp.service/start running (9s / no limit)
912 23:59:46.288913 <5>[ 26.991633] cfg80211: Loading compiled-in X.509 certificates for regulatory database
913 23:59:46.357598 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
914 23:59:46.415251 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
915 23:59:47.459828 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
916 23:59:47.663933 <5>[ 28.368689] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
917 23:59:47.744332 <5>[ 28.447606] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
918 23:59:47.774720 <4>[ 28.477318] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
919 23:59:47.780700 <6>[ 28.486544] cfg80211: failed to load regulatory.db
920 23:59:49.122846 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
921 23:59:49.145873 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
922 23:59:49.263532 <46>[ 29.957311] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
923 23:59:49.480714 <46>[ 30.176586] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
924 23:59:57.605122 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
925 23:59:57.631685 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
926 23:59:57.656786 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
927 23:59:57.677012 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
928 23:59:57.750309 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
929 23:59:57.826541 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
930 23:59:57.869524 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
931 23:59:57.958937 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
932 23:59:58.015768 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
933 23:59:58.039863 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
934 23:59:58.082328 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
935 23:59:58.109143 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
936 23:59:58.149180 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
937 23:59:58.187256 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
938 23:59:58.222211 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
939 23:59:58.247509 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
940 23:59:58.271876 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
941 23:59:58.299964 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
942 23:59:58.331836 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
943 23:59:58.355241 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
944 23:59:58.386758 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
945 23:59:58.405015 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
946 23:59:58.427920 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
947 23:59:58.505412 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
948 23:59:58.554119 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
949 23:59:58.649233 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
950 23:59:58.730247 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
951 23:59:58.804848 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
952 23:59:58.845779 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
953 23:59:58.894869 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
954 23:59:59.087415 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
955 23:59:59.154784 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
956 23:59:59.215725 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
957 23:59:59.244104 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
958 23:59:59.266834 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
959 23:59:59.467336 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
960 23:59:59.786019 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
961 23:59:59.831784 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
962 23:59:59.861070 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
963 23:59:59.937798 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
964 00:00:00.139118 Starting [0;1;39mdpkg-db-backup.se…ly dpkg database backup service...
965 00:00:00.189865 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
966 00:00:01.548057 [[0;32m OK [0m] Finished [0;1;39mdpkg-db-backup.se…aily dpkg database backup service.
967 00:00:01.704835
968 00:00:01.705356 Dworm-armhf login: root (automatic login)
969 00:00:01.705772
970 00:00:02.035114 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sun Nov 3 22:58:49 UTC 2024 armv7l
971 00:00:02.035656
972 00:00:02.040725 The programs included with the Debian GNU/Linux system are free software;
973 00:00:02.046326 the exact distribution terms for each program are described in the
974 00:00:02.051903 individual files in /usr/share/doc/*/copyright.
975 00:00:02.052360
976 00:00:02.059873 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
977 00:00:02.060328 permitted by applicable law.
978 00:00:06.751713 Unable to match end of the kernel message
980 00:00:06.753259 Setting prompt string to ['/ #']
981 00:00:06.753914 end: 2.4.4.1 login-action (duration 00:00:48) [common]
983 00:00:06.755325 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
984 00:00:06.755875 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
985 00:00:06.756319 Setting prompt string to ['/ #']
986 00:00:06.756734 Forcing a shell prompt, looking for ['/ #']
988 00:00:06.807727 / #
989 00:00:06.808365 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
990 00:00:06.808802 Waiting using forced prompt support (timeout 00:02:30)
991 00:00:06.813557
992 00:00:06.822552 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
993 00:00:06.823127 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
994 00:00:06.823613 Sending with 10 millisecond of delay
996 00:00:11.810107 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s'
997 00:00:11.820997 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/931452/extract-nfsrootfs-nishlu2s'
998 00:00:11.821783 Sending with 10 millisecond of delay
1000 00:00:13.919287 / # export NFS_SERVER_IP='192.168.6.3'
1001 00:00:13.930187 export NFS_SERVER_IP='192.168.6.3'
1002 00:00:13.931361 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1003 00:00:13.931956 end: 2.4 uboot-commands (duration 00:01:57) [common]
1004 00:00:13.932556 end: 2 uboot-action (duration 00:01:57) [common]
1005 00:00:13.933125 start: 3 lava-test-retry (timeout 00:06:50) [common]
1006 00:00:13.933700 start: 3.1 lava-test-shell (timeout 00:06:50) [common]
1007 00:00:13.934226 Using namespace: common
1009 00:00:14.035387 / # #
1010 00:00:14.036015 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1011 00:00:14.039876 #
1012 00:00:14.046950 Using /lava-931452
1014 00:00:14.148048 / # export SHELL=/bin/bash
1015 00:00:14.153278 export SHELL=/bin/bash
1017 00:00:14.260689 / # . /lava-931452/environment
1018 00:00:14.266094 . /lava-931452/environment
1020 00:00:14.380279 / # /lava-931452/bin/lava-test-runner /lava-931452/0
1021 00:00:14.380877 Test shell timeout: 10s (minimum of the action and connection timeout)
1022 00:00:14.384484 /lava-931452/bin/lava-test-runner /lava-931452/0
1023 00:00:14.736803 + export TESTRUN_ID=0_timesync-off
1024 00:00:14.744774 + TESTRUN_ID=0_timesync-off
1025 00:00:14.745223 + cd /lava-931452/0/tests/0_timesync-off
1026 00:00:14.745642 ++ cat uuid
1027 00:00:14.761895 + UUID=931452_1.6.2.4.1
1028 00:00:14.762347 + set +x
1029 00:00:14.770520 <LAVA_SIGNAL_STARTRUN 0_timesync-off 931452_1.6.2.4.1>
1030 00:00:14.770966 + systemctl stop systemd-timesyncd
1031 00:00:14.771655 Received signal: <STARTRUN> 0_timesync-off 931452_1.6.2.4.1
1032 00:00:14.772095 Starting test lava.0_timesync-off (931452_1.6.2.4.1)
1033 00:00:14.772614 Skipping test definition patterns.
1034 00:00:15.095900 + set +x
1035 00:00:15.096400 <LAVA_SIGNAL_ENDRUN 0_timesync-off 931452_1.6.2.4.1>
1036 00:00:15.097068 Received signal: <ENDRUN> 0_timesync-off 931452_1.6.2.4.1
1037 00:00:15.097555 Ending use of test pattern.
1038 00:00:15.098010 Ending test lava.0_timesync-off (931452_1.6.2.4.1), duration 0.33
1040 00:00:15.250637 + export TESTRUN_ID=1_kselftest-dt
1041 00:00:15.258674 + TESTRUN_ID=1_kselftest-dt
1042 00:00:15.259121 + cd /lava-931452/0/tests/1_kselftest-dt
1043 00:00:15.259538 ++ cat uuid
1044 00:00:15.274993 + UUID=931452_1.6.2.4.5
1045 00:00:15.275430 + set +x
1046 00:00:15.280609 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 931452_1.6.2.4.5>
1047 00:00:15.281043 + cd ./automated/linux/kselftest/
1048 00:00:15.281698 Received signal: <STARTRUN> 1_kselftest-dt 931452_1.6.2.4.5
1049 00:00:15.282201 Starting test lava.1_kselftest-dt (931452_1.6.2.4.5)
1050 00:00:15.282678 Skipping test definition patterns.
1051 00:00:15.308300 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1052 00:00:15.402421 INFO: install_deps skipped
1053 00:00:16.100756 --2024-11-04 00:00:16-- http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1054 00:00:16.126336 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1055 00:00:16.265976 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1056 00:00:16.402410 HTTP request sent, awaiting response... 200 OK
1057 00:00:16.402854 Length: 2556932 (2.4M) [application/octet-stream]
1058 00:00:16.407891 Saving to: 'kselftest_armhf.tar.gz'
1059 00:00:16.408315
1060 00:00:17.686755
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 186KB/s
kselftest_armhf.tar 8%[> ] 218.67K 406KB/s
kselftest_armhf.tar 32%[=====> ] 802.70K 851KB/s
kselftest_armhf.tar 73%[=============> ] 1.80M 1.54MB/s
kselftest_armhf.tar 100%[===================>] 2.44M 1.91MB/s in 1.3s
1061 00:00:17.687309
1062 00:00:18.064321 2024-11-04 00:00:17 (1.91 MB/s) - 'kselftest_armhf.tar.gz' saved [2556932/2556932]
1063 00:00:18.064933
1064 00:00:31.109565 skiplist:
1065 00:00:31.110047 ========================================
1066 00:00:31.115235 ========================================
1067 00:00:31.212821 dt:test_unprobed_devices.sh
1068 00:00:31.249374 ============== Tests to run ===============
1069 00:00:31.257286 dt:test_unprobed_devices.sh
1070 00:00:31.260464 ===========End Tests to run ===============
1071 00:00:31.271872 shardfile-dt pass
1072 00:00:31.499794 <12>[ 72.208294] kselftest: Running tests in dt
1073 00:00:31.531946 TAP version 13
1074 00:00:31.554089 1..1
1075 00:00:31.610318 # timeout set to 45
1076 00:00:31.610976 # selftests: dt: test_unprobed_devices.sh
1077 00:00:32.410636 # TAP version 13
1078 00:00:57.888820 # 1..257
1079 00:00:58.089883 # ok 1 / # SKIP
1080 00:00:58.106782 # ok 2 /clk_mcasp0
1081 00:00:58.180929 # ok 3 /clk_mcasp0_fixed # SKIP
1082 00:00:58.255316 # ok 4 /cpus/cpu@0 # SKIP
1083 00:00:58.326223 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1084 00:00:58.347918 # ok 6 /fixedregulator0
1085 00:00:58.368792 # ok 7 /leds
1086 00:00:58.394160 # ok 8 /ocp
1087 00:00:58.423866 # ok 9 /ocp/interconnect@44c00000
1088 00:00:58.445107 # ok 10 /ocp/interconnect@44c00000/segment@0
1089 00:00:58.467644 # ok 11 /ocp/interconnect@44c00000/segment@100000
1090 00:00:58.491114 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1091 00:00:58.567582 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1092 00:00:58.587617 # ok 14 /ocp/interconnect@44c00000/segment@200000
1093 00:00:58.615278 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1094 00:00:58.719000 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1095 00:00:58.793353 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1096 00:00:58.870962 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1097 00:00:58.941673 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1098 00:00:59.015359 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1099 00:00:59.090177 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1100 00:00:59.165027 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1101 00:00:59.238366 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1102 00:00:59.313654 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1103 00:00:59.391413 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1104 00:00:59.461900 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1105 00:00:59.534196 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1106 00:00:59.608085 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1107 00:00:59.682391 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1108 00:00:59.754131 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1109 00:00:59.828830 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1110 00:00:59.901851 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1111 00:00:59.975721 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1112 00:01:00.047791 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1113 00:01:00.128249 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1114 00:01:00.193608 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1115 00:01:00.268191 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1116 00:01:00.347050 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1117 00:01:00.416429 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1118 00:01:00.489477 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1119 00:01:00.563281 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1120 00:01:00.637837 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1121 00:01:00.711587 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1122 00:01:00.785540 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1123 00:01:00.859168 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1124 00:01:00.938387 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1125 00:01:01.012720 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1126 00:01:01.081862 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1127 00:01:01.162602 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1128 00:01:01.238391 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1129 00:01:01.307808 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1130 00:01:01.381702 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1131 00:01:01.455733 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1132 00:01:01.529996 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1133 00:01:01.608144 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1134 00:01:01.682900 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1135 00:01:01.751915 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1136 00:01:01.825301 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1137 00:01:01.899053 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1138 00:01:01.973181 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1139 00:01:02.048798 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1140 00:01:02.125722 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1141 00:01:02.199630 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1142 00:01:02.274568 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1143 00:01:02.351581 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1144 00:01:02.427966 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1145 00:01:02.502811 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1146 00:01:02.574530 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1147 00:01:02.649325 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1148 00:01:02.724127 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1149 00:01:02.799075 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1150 00:01:02.877539 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1151 00:01:02.952484 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1152 00:01:03.028288 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1153 00:01:03.102431 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1154 00:01:03.178791 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1155 00:01:03.252629 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1156 00:01:03.328293 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1157 00:01:03.398028 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1158 00:01:03.472181 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1159 00:01:03.550555 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1160 00:01:03.622216 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1161 00:01:03.697901 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1162 00:01:03.771356 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1163 00:01:03.843066 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1164 00:01:03.915507 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1165 00:01:03.991926 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1166 00:01:04.069701 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1167 00:01:04.143390 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1168 00:01:04.220415 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1169 00:01:04.290718 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1170 00:01:04.370782 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1171 00:01:04.438083 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1172 00:01:04.518932 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1173 00:01:04.540312 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1174 00:01:04.568557 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1175 00:01:04.589232 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1176 00:01:04.612105 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1177 00:01:04.637147 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1178 00:01:04.666398 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1179 00:01:04.690155 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1180 00:01:04.716475 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1181 00:01:04.819713 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1182 00:01:04.845311 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1183 00:01:04.870957 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1184 00:01:04.894849 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1185 00:01:05.002399 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1186 00:01:05.079867 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1187 00:01:05.156288 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1188 00:01:05.227210 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1189 00:01:05.302447 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1190 00:01:05.377217 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1191 00:01:05.451601 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1192 00:01:05.524642 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1193 00:01:05.600016 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1194 00:01:05.674232 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1195 00:01:05.750216 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1196 00:01:05.825889 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1197 00:01:05.898653 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1198 00:01:05.979398 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1199 00:01:06.051029 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1200 00:01:06.129654 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1201 00:01:06.150165 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1202 00:01:06.223837 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1203 00:01:06.294920 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1204 00:01:06.370509 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1205 00:01:06.392858 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1206 00:01:06.469250 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1207 00:01:06.490130 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1208 00:01:06.563553 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1209 00:01:06.587436 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1210 00:01:06.612850 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1211 00:01:06.635226 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1212 00:01:06.660757 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1213 00:01:06.689156 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1214 00:01:06.713999 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1215 00:01:06.736556 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1216 00:01:06.812599 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1217 00:01:06.834980 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1218 00:01:06.858914 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1219 00:01:06.932387 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1220 00:01:07.006339 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1221 00:01:07.027583 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1222 00:01:07.135617 # not ok 144 /ocp/interconnect@47c00000
1223 00:01:07.207006 # not ok 145 /ocp/interconnect@47c00000/segment@0
1224 00:01:07.232054 # ok 146 /ocp/interconnect@48000000
1225 00:01:07.255863 # ok 147 /ocp/interconnect@48000000/segment@0
1226 00:01:07.277017 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1227 00:01:07.305071 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1228 00:01:07.328234 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1229 00:01:07.355847 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1230 00:01:07.373207 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1231 00:01:07.399558 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1232 00:01:07.421363 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1233 00:01:07.495178 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1234 00:01:07.571251 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1235 00:01:07.591869 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1236 00:01:07.617276 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1237 00:01:07.639829 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1238 00:01:07.665426 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1239 00:01:07.693126 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1240 00:01:07.712912 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1241 00:01:07.736720 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1242 00:01:07.762005 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1243 00:01:07.784536 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1244 00:01:08.113700 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1245 00:01:08.114429 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1246 00:01:08.114931 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1247 00:01:08.115891 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1248 00:01:08.116416 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1249 00:01:08.116889 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1250 00:01:08.117335 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1251 00:01:08.117781 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1252 00:01:08.118271 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1253 00:01:08.118711 # ok 175 /ocp/interconnect@48000000/segment@100000
1254 00:01:08.119145 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1255 00:01:08.119674 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1256 00:01:08.156415 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1257 00:01:08.226664 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1258 00:01:08.300324 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1259 00:01:08.375561 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1260 00:01:08.448825 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1261 00:01:08.525244 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1262 00:01:08.597457 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1263 00:01:08.677909 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1264 00:01:08.694157 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1265 00:01:08.718134 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1266 00:01:08.742422 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1267 00:01:08.769161 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1268 00:01:08.790455 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1269 00:01:08.818808 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1270 00:01:08.844513 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1271 00:01:08.865594 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1272 00:01:08.893405 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1273 00:01:08.913589 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1274 00:01:08.937181 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1275 00:01:08.962218 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1276 00:01:08.983151 # ok 198 /ocp/interconnect@48000000/segment@200000
1277 00:01:09.008707 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1278 00:01:09.087423 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1279 00:01:09.107416 # ok 201 /ocp/interconnect@48000000/segment@300000
1280 00:01:09.129564 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1281 00:01:09.153854 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1282 00:01:09.178546 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1283 00:01:09.202180 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1284 00:01:09.225988 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1285 00:01:09.255393 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1286 00:01:09.329915 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1287 00:01:09.344517 # ok 209 /ocp/interconnect@4a000000
1288 00:01:09.369171 # ok 210 /ocp/interconnect@4a000000/segment@0
1289 00:01:09.394356 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1290 00:01:09.424547 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1291 00:01:09.445746 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1292 00:01:09.467671 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1293 00:01:09.541988 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1294 00:01:09.650426 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1295 00:01:09.729390 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1296 00:01:09.832258 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1297 00:01:09.905058 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1298 00:01:09.979845 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1299 00:01:10.084704 # not ok 221 /ocp/interconnect@4b140000
1300 00:01:10.157274 # not ok 222 /ocp/interconnect@4b140000/segment@0
1301 00:01:10.232049 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1302 00:01:10.250387 # ok 224 /ocp/target-module@40300000
1303 00:01:10.276762 # ok 225 /ocp/target-module@40300000/sram@0
1304 00:01:10.354100 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1305 00:01:10.428783 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1306 00:01:10.445529 # ok 228 /ocp/target-module@47400000
1307 00:01:10.470979 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1308 00:01:10.493592 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1309 00:01:10.522105 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1310 00:01:10.545134 # ok 232 /ocp/target-module@47400000/usb@1400
1311 00:01:10.566812 # ok 233 /ocp/target-module@47400000/usb@1800
1312 00:01:10.586679 # ok 234 /ocp/target-module@47810000
1313 00:01:10.613913 # ok 235 /ocp/target-module@49000000
1314 00:01:10.636548 # ok 236 /ocp/target-module@49000000/dma@0
1315 00:01:10.656331 # ok 237 /ocp/target-module@49800000
1316 00:01:10.679827 # ok 238 /ocp/target-module@49800000/dma@0
1317 00:01:10.706103 # ok 239 /ocp/target-module@49900000
1318 00:01:10.734615 # ok 240 /ocp/target-module@49900000/dma@0
1319 00:01:10.749313 # ok 241 /ocp/target-module@49a00000
1320 00:01:10.773916 # ok 242 /ocp/target-module@49a00000/dma@0
1321 00:01:10.796588 # ok 243 /ocp/target-module@4c000000
1322 00:01:10.874815 # not ok 244 /ocp/target-module@4c000000/emif@0
1323 00:01:10.892568 # ok 245 /ocp/target-module@50000000
1324 00:01:10.916196 # ok 246 /ocp/target-module@53100000
1325 00:01:10.993629 # not ok 247 /ocp/target-module@53100000/sham@0
1326 00:01:11.015074 # ok 248 /ocp/target-module@53500000
1327 00:01:11.086966 # not ok 249 /ocp/target-module@53500000/aes@0
1328 00:01:11.111834 # ok 250 /ocp/target-module@56000000
1329 00:01:11.217404 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1330 00:01:11.291949 # ok 252 /opp-table # SKIP
1331 00:01:11.363592 # ok 253 /soc # SKIP
1332 00:01:11.380307 # ok 254 /sound
1333 00:01:11.405358 # ok 255 /target-module@4b000000
1334 00:01:11.430606 # ok 256 /target-module@4b000000/target-module@140000
1335 00:01:11.452557 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1336 00:01:11.460800 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1337 00:01:11.469677 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1338 00:01:13.670909 dt_test_unprobed_devices_sh_ skip
1339 00:01:13.676334 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1340 00:01:13.682020 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1341 00:01:13.682567 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1342 00:01:13.687600 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1343 00:01:13.693179 dt_test_unprobed_devices_sh_fixedregulator0 pass
1344 00:01:13.698793 dt_test_unprobed_devices_sh_leds pass
1345 00:01:13.699292 dt_test_unprobed_devices_sh_ocp pass
1346 00:01:13.704343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1347 00:01:13.710008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1348 00:01:13.715552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1349 00:01:13.726772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1350 00:01:13.732368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1351 00:01:13.737929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1352 00:01:13.749087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1353 00:01:13.754724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1354 00:01:13.765994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1355 00:01:13.777124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1356 00:01:13.788399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1357 00:01:13.794060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1358 00:01:13.805181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1359 00:01:13.816433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1360 00:01:13.827717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1361 00:01:13.838777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1362 00:01:13.844441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1363 00:01:13.855534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1364 00:01:13.866782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1365 00:01:13.877941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1366 00:01:13.889159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1367 00:01:13.894944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1368 00:01:13.906064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1369 00:01:13.917238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1370 00:01:13.928456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1371 00:01:13.934142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1372 00:01:13.945347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1373 00:01:13.956529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1374 00:01:13.967739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1375 00:01:13.978967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1376 00:01:13.984622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1377 00:01:13.995802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1378 00:01:14.006994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1379 00:01:14.018185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1380 00:01:14.029394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1381 00:01:14.040582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1382 00:01:14.051806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1383 00:01:14.062998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1384 00:01:14.074152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1385 00:01:14.085346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1386 00:01:14.096568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1387 00:01:14.107759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1388 00:01:14.118973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1389 00:01:14.130120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1390 00:01:14.141303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1391 00:01:14.152598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1392 00:01:14.163726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1393 00:01:14.174898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1394 00:01:14.186139 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1395 00:01:14.197277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1396 00:01:14.208473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1397 00:01:14.219774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1398 00:01:14.230869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1399 00:01:14.242056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1400 00:01:14.253288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1401 00:01:14.264442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1402 00:01:14.270109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1403 00:01:14.281248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1404 00:01:14.292412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1405 00:01:14.303627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1406 00:01:14.314784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1407 00:01:14.326028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1408 00:01:14.337197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1409 00:01:14.348488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1410 00:01:14.359648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1411 00:01:14.370797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1412 00:01:14.382039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1413 00:01:14.393142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1414 00:01:14.404351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1415 00:01:14.415573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1416 00:01:14.426790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1417 00:01:14.437912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1418 00:01:14.449084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1419 00:01:14.460358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1420 00:01:14.466067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1421 00:01:14.477177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1422 00:01:14.488379 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1423 00:01:14.499541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1424 00:01:14.510777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1425 00:01:14.516439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1426 00:01:14.533166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1427 00:01:14.544328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1428 00:01:14.549991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1429 00:01:14.566792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1430 00:01:14.577915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1431 00:01:14.589112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1432 00:01:14.594837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1433 00:01:14.605922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1434 00:01:14.617160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1435 00:01:14.622722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1436 00:01:14.633894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1437 00:01:14.645074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1438 00:01:14.650720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1439 00:01:14.661868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1440 00:01:14.667483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1441 00:01:14.678653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1442 00:01:14.689887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1443 00:01:14.701030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1444 00:01:14.712220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1445 00:01:14.723443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1446 00:01:14.734567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1447 00:01:14.745829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1448 00:01:14.757002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1449 00:01:14.768213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1450 00:01:14.779357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1451 00:01:14.790579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1452 00:01:14.801798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1453 00:01:14.818543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1454 00:01:14.829859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1455 00:01:14.840957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1456 00:01:14.852116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1457 00:01:14.863334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1458 00:01:14.880086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1459 00:01:14.891318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1460 00:01:14.902485 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1461 00:01:14.913686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1462 00:01:14.919257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1463 00:01:14.930514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1464 00:01:14.941681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1465 00:01:14.947338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1466 00:01:14.958505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1467 00:01:14.964141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1468 00:01:14.975329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1469 00:01:14.980872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1470 00:01:14.992062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1471 00:01:14.997761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1472 00:01:15.008829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1473 00:01:15.014511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1474 00:01:15.025689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1475 00:01:15.036836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1476 00:01:15.048055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1477 00:01:15.059204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1478 00:01:15.070449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1479 00:01:15.076085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1480 00:01:15.087230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1481 00:01:15.092896 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1482 00:01:15.098434 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1483 00:01:15.104049 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1484 00:01:15.109649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1485 00:01:15.115260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1486 00:01:15.126380 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1487 00:01:15.132029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1488 00:01:15.137600 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1489 00:01:15.148916 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1490 00:01:15.154423 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1491 00:01:15.165574 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1492 00:01:15.171238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1493 00:01:15.182375 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1494 00:01:15.187967 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1495 00:01:15.199128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1496 00:01:15.204795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1497 00:01:15.215914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1498 00:01:15.221528 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1499 00:01:15.232841 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1500 00:01:15.238386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1501 00:01:15.249610 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1502 00:01:15.255218 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1503 00:01:15.260838 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1504 00:01:15.272025 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1505 00:01:15.277616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1506 00:01:15.288867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1507 00:01:15.294488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1508 00:01:15.305624 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1509 00:01:15.311364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1510 00:01:15.322503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1511 00:01:15.328144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1512 00:01:15.333834 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1513 00:01:15.345022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1514 00:01:15.350648 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1515 00:01:15.361918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1516 00:01:15.373045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1517 00:01:15.384213 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1518 00:01:15.395437 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1519 00:01:15.406600 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1520 00:01:15.417926 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1521 00:01:15.429033 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1522 00:01:15.440183 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1523 00:01:15.445944 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1524 00:01:15.456973 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1525 00:01:15.462565 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1526 00:01:15.473737 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1527 00:01:15.479422 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1528 00:01:15.490549 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1529 00:01:15.496211 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1530 00:01:15.507344 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1531 00:01:15.513007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1532 00:01:15.524129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1533 00:01:15.529875 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1534 00:01:15.540927 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1535 00:01:15.546553 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1536 00:01:15.557784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1537 00:01:15.563329 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1538 00:01:15.568973 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1539 00:01:15.580162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1540 00:01:15.585743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1541 00:01:15.596932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1542 00:01:15.602535 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1543 00:01:15.613680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1544 00:01:15.619296 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1545 00:01:15.630465 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1546 00:01:15.636150 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1547 00:01:15.641671 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1548 00:01:15.647315 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1549 00:01:15.658450 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1550 00:01:15.669651 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1551 00:01:15.675287 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1552 00:01:15.680977 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1553 00:01:15.692015 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1554 00:01:15.703212 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1555 00:01:15.714394 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1556 00:01:15.725635 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1557 00:01:15.731233 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1558 00:01:15.736964 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1559 00:01:15.742453 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1560 00:01:15.748056 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1561 00:01:15.753655 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1562 00:01:15.759233 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1563 00:01:15.770455 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1564 00:01:15.776091 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1565 00:01:15.781695 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1566 00:01:15.787461 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1567 00:01:15.792983 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1568 00:01:15.804068 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1569 00:01:15.809737 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1570 00:01:15.815337 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1571 00:01:15.821083 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1572 00:01:15.826513 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1573 00:01:15.832119 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1574 00:01:15.837733 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1575 00:01:15.843382 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1576 00:01:15.849018 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1577 00:01:15.854593 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1578 00:01:15.860214 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1579 00:01:15.865745 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1580 00:01:15.871361 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1581 00:01:15.876976 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1582 00:01:15.882525 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1583 00:01:15.888189 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1584 00:01:15.893758 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1585 00:01:15.899368 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1586 00:01:15.904982 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1587 00:01:15.910585 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1588 00:01:15.916146 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1589 00:01:15.916732 dt_test_unprobed_devices_sh_opp-table skip
1590 00:01:15.921774 dt_test_unprobed_devices_sh_soc skip
1591 00:01:15.927360 dt_test_unprobed_devices_sh_sound pass
1592 00:01:15.932988 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1593 00:01:15.938666 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1594 00:01:15.944186 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1595 00:01:15.949914 dt_test_unprobed_devices_sh fail
1596 00:01:15.950557 + ../../utils/send-to-lava.sh ./output/result.txt
1597 00:01:15.957843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1598 00:01:15.958781 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1600 00:01:15.973764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1601 00:01:15.974648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1603 00:01:16.076282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1604 00:01:16.077351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1606 00:01:16.174896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1607 00:01:16.175753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1609 00:01:16.275363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1610 00:01:16.276210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1612 00:01:16.377612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1613 00:01:16.378549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1615 00:01:16.478076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1616 00:01:16.478979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1618 00:01:16.578647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1619 00:01:16.579469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1621 00:01:16.680719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1622 00:01:16.681542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1624 00:01:16.783791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1625 00:01:16.784675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1627 00:01:16.885401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1628 00:01:16.886345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1630 00:01:16.987189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1631 00:01:16.988026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1633 00:01:17.090467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1634 00:01:17.091292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1636 00:01:17.192785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1637 00:01:17.193615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1639 00:01:17.292401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1640 00:01:17.293223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1642 00:01:17.395131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1643 00:01:17.396025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1645 00:01:17.496513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1646 00:01:17.497421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1648 00:01:17.592742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1649 00:01:17.593660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1651 00:01:17.697577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1652 00:01:17.698287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1654 00:01:17.793046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1655 00:01:17.793946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1657 00:01:17.888679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1658 00:01:17.889531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1660 00:01:17.981652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1661 00:01:17.982533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1663 00:01:18.076905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1664 00:01:18.077759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1666 00:01:18.172045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1667 00:01:18.172872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1669 00:01:18.267514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1670 00:01:18.268362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1672 00:01:18.363900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1673 00:01:18.364748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1675 00:01:18.460105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1676 00:01:18.461038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1678 00:01:18.556940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1679 00:01:18.557892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1681 00:01:18.653054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1682 00:01:18.653951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1684 00:01:18.748645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1685 00:01:18.749493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1687 00:01:18.842299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1688 00:01:18.843027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1690 00:01:18.938549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1691 00:01:18.939104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1693 00:01:19.039196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1694 00:01:19.039892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1696 00:01:19.141236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1697 00:01:19.141944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1699 00:01:19.240607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1700 00:01:19.241339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1702 00:01:19.342327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1703 00:01:19.343002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1705 00:01:19.444796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1706 00:01:19.445631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1708 00:01:19.545847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1709 00:01:19.546681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1711 00:01:19.647386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1712 00:01:19.648176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1714 00:01:19.748205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1715 00:01:19.748993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1717 00:01:19.849338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1718 00:01:19.850199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1720 00:01:19.950478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1721 00:01:19.951293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1723 00:01:20.053898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1724 00:01:20.054706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1726 00:01:20.155044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1727 00:01:20.155865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1729 00:01:20.255459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1730 00:01:20.256280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1732 00:01:20.357209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1733 00:01:20.358009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1735 00:01:20.458849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1736 00:01:20.459643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1738 00:01:20.559742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1739 00:01:20.560541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1741 00:01:20.660719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1742 00:01:20.661541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1744 00:01:20.762408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1745 00:01:20.763247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1747 00:01:20.863201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1748 00:01:20.864016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1750 00:01:20.965024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1751 00:01:20.965886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1753 00:01:21.066167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1754 00:01:21.066999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1756 00:01:21.168032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1757 00:01:21.168867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1759 00:01:21.268891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1760 00:01:21.269659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1762 00:01:21.369452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1763 00:01:21.370201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1765 00:01:21.471929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1766 00:01:21.472662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1768 00:01:21.572502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1769 00:01:21.573224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1771 00:01:21.672970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1772 00:01:21.673685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1774 00:01:21.773880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1775 00:01:21.774593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1777 00:01:21.875607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1778 00:01:21.876322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1780 00:01:21.977730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1781 00:01:21.978481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1783 00:01:22.078816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1784 00:01:22.079547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1786 00:01:22.180007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1787 00:01:22.180728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1789 00:01:22.283855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1790 00:01:22.284585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1792 00:01:22.384825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1793 00:01:22.385555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1795 00:01:22.487502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1796 00:01:22.488222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1798 00:01:22.589301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1799 00:01:22.590026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1801 00:01:22.690956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1802 00:01:22.691683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1804 00:01:22.788876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1805 00:01:22.789669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1807 00:01:22.910879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1808 00:01:22.911751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1810 00:01:23.015742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1811 00:01:23.016516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1813 00:01:23.119251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1814 00:01:23.120014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1816 00:01:23.219541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1817 00:01:23.220438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1819 00:01:23.319306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1820 00:01:23.320104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1822 00:01:23.420223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1823 00:01:23.420902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1825 00:01:23.517290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1826 00:01:23.517991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1828 00:01:23.671639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1829 00:01:23.672292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1831 00:01:23.780461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1832 00:01:23.781124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1834 00:01:23.882920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1835 00:01:23.883551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1837 00:01:23.978559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1838 00:01:23.979226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1840 00:01:24.077842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1841 00:01:24.078949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1843 00:01:24.174003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1844 00:01:24.174628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1846 00:01:24.278805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1847 00:01:24.279564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1849 00:01:24.378554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1850 00:01:24.379311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1852 00:01:24.478725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1853 00:01:24.479466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1855 00:01:24.580546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1856 00:01:24.581315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1858 00:01:24.682304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1859 00:01:24.683042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1861 00:01:24.783181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1862 00:01:24.783923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1864 00:01:24.886507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1865 00:01:24.887276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1867 00:01:24.988127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1868 00:01:24.988901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1870 00:01:25.088943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1871 00:01:25.089686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1873 00:01:25.188792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1874 00:01:25.189536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1876 00:01:25.290386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1877 00:01:25.291122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1879 00:01:25.392221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1880 00:01:25.392983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1882 00:01:25.489930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1883 00:01:25.490681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1885 00:01:25.591936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1886 00:01:25.592709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1888 00:01:25.692561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1889 00:01:25.693401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1891 00:01:25.793520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1892 00:01:25.794413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1894 00:01:25.894544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1895 00:01:25.895351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1897 00:01:25.995998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1898 00:01:25.996802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1900 00:01:26.095752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1901 00:01:26.096547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1903 00:01:26.197399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1904 00:01:26.198251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1906 00:01:26.290516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1907 00:01:26.291321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1909 00:01:26.393237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1910 00:01:26.394046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1912 00:01:26.485642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1913 00:01:26.486437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1915 00:01:26.588874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1916 00:01:26.589648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1918 00:01:26.686656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1919 00:01:26.687439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1921 00:01:26.790889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1922 00:01:26.791650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1924 00:01:26.891633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1925 00:01:26.892463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1927 00:01:26.983556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1928 00:01:26.984406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1930 00:01:27.085318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1931 00:01:27.086164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1933 00:01:27.186640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1934 00:01:27.187454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1936 00:01:27.288779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1937 00:01:27.289616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1939 00:01:27.388950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1940 00:01:27.389747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1942 00:01:27.490441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1943 00:01:27.491225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1945 00:01:27.591821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1946 00:01:27.592598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1948 00:01:27.693240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1949 00:01:27.694100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1951 00:01:27.794355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1952 00:01:27.795165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1954 00:01:27.888400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1955 00:01:27.889218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1957 00:01:27.981110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1959 00:01:27.984225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1960 00:01:28.074405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1962 00:01:28.077527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1963 00:01:28.175304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1965 00:01:28.178383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1966 00:01:28.277784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1967 00:01:28.278655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1969 00:01:28.377886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1970 00:01:28.378763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1972 00:01:28.477018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1973 00:01:28.477795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1975 00:01:28.578388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1976 00:01:28.579224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1978 00:01:28.670689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1979 00:01:28.671522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1981 00:01:28.765697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1982 00:01:28.766579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1984 00:01:28.859386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1985 00:01:28.860195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1987 00:01:28.953126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1988 00:01:28.953942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1990 00:01:29.054875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1991 00:01:29.055593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1993 00:01:29.155535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1994 00:01:29.156319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1996 00:01:29.248066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1997 00:01:29.248841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1999 00:01:29.350507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2000 00:01:29.351249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2002 00:01:29.450934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2003 00:01:29.451825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2005 00:01:29.552475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2006 00:01:29.553398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2008 00:01:29.655800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2009 00:01:29.656746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2011 00:01:29.759255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2012 00:01:29.760184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2014 00:01:29.857491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2015 00:01:29.858398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2017 00:01:29.951457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2018 00:01:29.952265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2020 00:01:30.053582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2021 00:01:30.054517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2023 00:01:30.153950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2024 00:01:30.154802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2026 00:01:30.256059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2027 00:01:30.256911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2029 00:01:30.351577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2030 00:01:30.352417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2032 00:01:30.454072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2033 00:01:30.454889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2035 00:01:30.554264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2036 00:01:30.555097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2038 00:01:30.656146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2039 00:01:30.656961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2041 00:01:30.758469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2042 00:01:30.759265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2044 00:01:30.861733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2045 00:01:30.862600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2047 00:01:30.962167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2048 00:01:30.962962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2050 00:01:31.064334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2051 00:01:31.065142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2053 00:01:31.165132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2054 00:01:31.166013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2056 00:01:31.263929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2057 00:01:31.264721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2059 00:01:31.365320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2060 00:01:31.366124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2062 00:01:31.460815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2063 00:01:31.461565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2065 00:01:31.563410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2066 00:01:31.564190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2068 00:01:31.663147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2069 00:01:31.663901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2071 00:01:31.766489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2072 00:01:31.767218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2074 00:01:31.866746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2075 00:01:31.867485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2077 00:01:31.968533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2078 00:01:31.969249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2080 00:01:32.068788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2081 00:01:32.069540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2083 00:01:32.169971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2084 00:01:32.170727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2086 00:01:32.271778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2087 00:01:32.272530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2089 00:01:32.366466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2090 00:01:32.367433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2092 00:01:32.466600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2093 00:01:32.467454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2095 00:01:32.567511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2096 00:01:32.568322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2098 00:01:32.669666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2099 00:01:32.670524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2101 00:01:32.771684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2102 00:01:32.772477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2104 00:01:32.871789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2105 00:01:32.872541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2107 00:01:32.973406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2108 00:01:32.974190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2110 00:01:33.070877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2111 00:01:33.071685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2113 00:01:33.166654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2114 00:01:33.167498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2116 00:01:33.275573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2117 00:01:33.276510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2119 00:01:33.366046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2120 00:01:33.366917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2122 00:01:33.464961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2123 00:01:33.465734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2125 00:01:33.568252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2126 00:01:33.569057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2128 00:01:33.669574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2129 00:01:33.670432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2131 00:01:33.772501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2132 00:01:33.773292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2134 00:01:33.875191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2135 00:01:33.876018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2137 00:01:33.975457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2138 00:01:33.976323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2140 00:01:34.077615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2141 00:01:34.078460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2143 00:01:34.177644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2144 00:01:34.178459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2146 00:01:34.280876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2147 00:01:34.281732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2149 00:01:34.373754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2150 00:01:34.374597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2152 00:01:34.476834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2153 00:01:34.477643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2155 00:01:34.574769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2156 00:01:34.575554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2158 00:01:34.675975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2159 00:01:34.676786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2161 00:01:34.777277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2162 00:01:34.778108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2164 00:01:34.878452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2165 00:01:34.879317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2167 00:01:34.978975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2168 00:01:34.979766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2170 00:01:35.081734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2171 00:01:35.082565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2173 00:01:35.181736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2174 00:01:35.182619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2176 00:01:35.283374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2177 00:01:35.284247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2179 00:01:35.385274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2180 00:01:35.386143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2182 00:01:35.486962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2183 00:01:35.487809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2185 00:01:35.587021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2186 00:01:35.587889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2188 00:01:35.689965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2189 00:01:35.690900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2191 00:01:35.781748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2192 00:01:35.782645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2194 00:01:35.884615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2195 00:01:35.885477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2197 00:01:35.986011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2198 00:01:35.986874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2200 00:01:36.084043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2201 00:01:36.084909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2203 00:01:36.187881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2204 00:01:36.188752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2206 00:01:36.281340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2207 00:01:36.282235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2209 00:01:36.383305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2210 00:01:36.384163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2212 00:01:36.483424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2213 00:01:36.484283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2215 00:01:36.583909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2216 00:01:36.584773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2218 00:01:36.685436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2219 00:01:36.686339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2221 00:01:36.786678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2222 00:01:36.787545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2224 00:01:36.885258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2225 00:01:36.886152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2227 00:01:36.986601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2228 00:01:36.987457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2230 00:01:37.089440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2231 00:01:37.090324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2233 00:01:37.191254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2234 00:01:37.192119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2236 00:01:37.293961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2237 00:01:37.294820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2239 00:01:37.393773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2240 00:01:37.394653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2242 00:01:37.495363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2243 00:01:37.496218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2245 00:01:37.597695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2246 00:01:37.598603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2248 00:01:37.698875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2249 00:01:37.699734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2251 00:01:37.800015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2252 00:01:37.800868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2254 00:01:37.900728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2255 00:01:37.901587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2257 00:01:38.001860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2258 00:01:38.002727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2260 00:01:38.098177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2261 00:01:38.099031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2263 00:01:38.193710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2264 00:01:38.194629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2266 00:01:38.288159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2267 00:01:38.289019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2269 00:01:38.382363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2270 00:01:38.383212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2272 00:01:38.484822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2273 00:01:38.485682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2275 00:01:38.587379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2276 00:01:38.588244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2278 00:01:38.677542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2280 00:01:38.680584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2281 00:01:38.779977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2282 00:01:38.780847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2284 00:01:38.883247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2285 00:01:38.884115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2287 00:01:38.983859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2288 00:01:38.984737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2290 00:01:39.085056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2291 00:01:39.085921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2293 00:01:39.185342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2294 00:01:39.186285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2296 00:01:39.287249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2297 00:01:39.288098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2299 00:01:39.387365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2300 00:01:39.388212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2302 00:01:39.488893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2303 00:01:39.489765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2305 00:01:39.590281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2306 00:01:39.591140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2308 00:01:39.691331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2309 00:01:39.692192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2311 00:01:39.793004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2312 00:01:39.793905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2314 00:01:39.890198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2315 00:01:39.891109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2317 00:01:39.985856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2318 00:01:39.986744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2320 00:01:40.088557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2321 00:01:40.089476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2323 00:01:40.190581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2324 00:01:40.191461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2326 00:01:40.291326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2327 00:01:40.292158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2329 00:01:40.392563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2330 00:01:40.393388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2332 00:01:40.493210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2333 00:01:40.494032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2335 00:01:40.594088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2336 00:01:40.594907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2338 00:01:40.695518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2339 00:01:40.696335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2341 00:01:40.796917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2342 00:01:40.797731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2344 00:01:40.898744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2345 00:01:40.899547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2347 00:01:40.998358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2348 00:01:40.999170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2350 00:01:41.100963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2351 00:01:41.101785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2353 00:01:41.489235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2354 00:01:41.489908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2355 00:01:41.490673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2357 00:01:41.492118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2359 00:01:41.493568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2360 00:01:41.494366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2362 00:01:41.505056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2363 00:01:41.505950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2365 00:01:41.608544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2366 00:01:41.609511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2368 00:01:41.710696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2369 00:01:41.711608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2371 00:01:41.808421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2372 00:01:41.809006 + set +x
2373 00:01:41.809738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2375 00:01:41.812787 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 931452_1.6.2.4.5>
2376 00:01:41.813575 Received signal: <ENDRUN> 1_kselftest-dt 931452_1.6.2.4.5
2377 00:01:41.814141 Ending use of test pattern.
2378 00:01:41.814609 Ending test lava.1_kselftest-dt (931452_1.6.2.4.5), duration 86.53
2380 00:01:41.821076 <LAVA_TEST_RUNNER EXIT>
2381 00:01:41.821879 ok: lava_test_shell seems to have completed
2382 00:01:41.836266 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2383 00:01:41.838392 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2384 00:01:41.839039 end: 3 lava-test-retry (duration 00:01:28) [common]
2385 00:01:41.839679 start: 4 finalize (timeout 00:05:22) [common]
2386 00:01:41.840308 start: 4.1 power-off (timeout 00:00:30) [common]
2387 00:01:41.841401 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2388 00:01:41.879248 >> OK - accepted request
2389 00:01:41.881055 Returned 0 in 0 seconds
2390 00:01:41.982283 end: 4.1 power-off (duration 00:00:00) [common]
2392 00:01:41.984072 start: 4.2 read-feedback (timeout 00:05:22) [common]
2393 00:01:41.985286 Listened to connection for namespace 'common' for up to 1s
2394 00:01:41.986265 Listened to connection for namespace 'common' for up to 1s
2395 00:01:42.985353 Finalising connection for namespace 'common'
2396 00:01:42.986130 Disconnecting from shell: Finalise
2397 00:01:42.986708 / #
2398 00:01:43.087727 end: 4.2 read-feedback (duration 00:00:01) [common]
2399 00:01:43.088466 end: 4 finalize (duration 00:00:01) [common]
2400 00:01:43.089183 Cleaning after the job
2401 00:01:43.089910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/ramdisk
2402 00:01:43.100396 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/kernel
2403 00:01:43.108855 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/dtb
2404 00:01:43.110253 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/nfsrootfs
2405 00:01:43.269222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931452/tftp-deploy-l8wn_vew/modules
2406 00:01:43.279894 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/931452
2407 00:01:46.288283 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/931452
2408 00:01:46.288852 Job finished correctly