Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:55:48.922778 lava-dispatcher, installed at version: 2024.01
2 22:55:48.923593 start: 0 validate
3 22:55:48.924103 Start time: 2024-11-03 22:55:48.924072+00:00 (UTC)
4 22:55:48.924663 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:55:48.925201 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:55:48.967177 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:55:48.967768 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 22:55:48.998905 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:55:48.999650 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:55:49.030970 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:55:49.031474 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
12 22:55:49.069264 validate duration: 0.15
14 22:55:49.070091 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:55:49.070419 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:55:49.070704 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:55:49.071290 Not decompressing ramdisk as can be used compressed.
18 22:55:49.071735 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:55:49.071970 saving as /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/ramdisk/rootfs.cpio.gz
20 22:55:49.072245 total size: 8181887 (7 MB)
21 22:55:49.106371 progress 0 % (0 MB)
22 22:55:49.113808 progress 5 % (0 MB)
23 22:55:49.120598 progress 10 % (0 MB)
24 22:55:49.127964 progress 15 % (1 MB)
25 22:55:49.134735 progress 20 % (1 MB)
26 22:55:49.142219 progress 25 % (1 MB)
27 22:55:49.148662 progress 30 % (2 MB)
28 22:55:49.155574 progress 35 % (2 MB)
29 22:55:49.163181 progress 40 % (3 MB)
30 22:55:49.169058 progress 45 % (3 MB)
31 22:55:49.174421 progress 50 % (3 MB)
32 22:55:49.180105 progress 55 % (4 MB)
33 22:55:49.185473 progress 60 % (4 MB)
34 22:55:49.191176 progress 65 % (5 MB)
35 22:55:49.196490 progress 70 % (5 MB)
36 22:55:49.202120 progress 75 % (5 MB)
37 22:55:49.207426 progress 80 % (6 MB)
38 22:55:49.213337 progress 85 % (6 MB)
39 22:55:49.218665 progress 90 % (7 MB)
40 22:55:49.224440 progress 95 % (7 MB)
41 22:55:49.229368 progress 100 % (7 MB)
42 22:55:49.230046 7 MB downloaded in 0.16 s (49.45 MB/s)
43 22:55:49.230613 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:55:49.231502 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:55:49.231794 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:55:49.232098 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:55:49.232576 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/clang-15/kernel/Image
49 22:55:49.232833 saving as /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/kernel/Image
50 22:55:49.233038 total size: 37878272 (36 MB)
51 22:55:49.233247 No compression specified
52 22:55:49.266632 progress 0 % (0 MB)
53 22:55:49.290091 progress 5 % (1 MB)
54 22:55:49.313330 progress 10 % (3 MB)
55 22:55:49.336533 progress 15 % (5 MB)
56 22:55:49.359608 progress 20 % (7 MB)
57 22:55:49.382233 progress 25 % (9 MB)
58 22:55:49.405601 progress 30 % (10 MB)
59 22:55:49.428627 progress 35 % (12 MB)
60 22:55:49.451572 progress 40 % (14 MB)
61 22:55:49.474756 progress 45 % (16 MB)
62 22:55:49.497804 progress 50 % (18 MB)
63 22:55:49.520711 progress 55 % (19 MB)
64 22:55:49.543700 progress 60 % (21 MB)
65 22:55:49.566470 progress 65 % (23 MB)
66 22:55:49.589723 progress 70 % (25 MB)
67 22:55:49.612203 progress 75 % (27 MB)
68 22:55:49.634984 progress 80 % (28 MB)
69 22:55:49.657807 progress 85 % (30 MB)
70 22:55:49.681008 progress 90 % (32 MB)
71 22:55:49.704005 progress 95 % (34 MB)
72 22:55:49.725849 progress 100 % (36 MB)
73 22:55:49.726594 36 MB downloaded in 0.49 s (73.19 MB/s)
74 22:55:49.727094 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:55:49.727912 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:55:49.728220 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:55:49.728487 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:55:49.728986 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 22:55:49.729275 saving as /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/dtb/meson-g12b-a311d-libretech-cc.dtb
81 22:55:49.729484 total size: 54703 (0 MB)
82 22:55:49.729694 No compression specified
83 22:55:49.769144 progress 59 % (0 MB)
84 22:55:49.769986 progress 100 % (0 MB)
85 22:55:49.770571 0 MB downloaded in 0.04 s (1.27 MB/s)
86 22:55:49.771111 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:55:49.772139 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:55:49.772461 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:55:49.772750 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:55:49.773249 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/clang-15/modules.tar.xz
92 22:55:49.773547 saving as /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/modules/modules.tar
93 22:55:49.773774 total size: 11773700 (11 MB)
94 22:55:49.774003 Using unxz to decompress xz
95 22:55:49.811336 progress 0 % (0 MB)
96 22:55:49.878731 progress 5 % (0 MB)
97 22:55:49.954007 progress 10 % (1 MB)
98 22:55:50.049405 progress 15 % (1 MB)
99 22:55:50.145337 progress 20 % (2 MB)
100 22:55:50.225178 progress 25 % (2 MB)
101 22:55:50.301022 progress 30 % (3 MB)
102 22:55:50.380685 progress 35 % (3 MB)
103 22:55:50.459484 progress 40 % (4 MB)
104 22:55:50.534603 progress 45 % (5 MB)
105 22:55:50.619414 progress 50 % (5 MB)
106 22:55:50.701429 progress 55 % (6 MB)
107 22:55:50.787950 progress 60 % (6 MB)
108 22:55:50.871681 progress 65 % (7 MB)
109 22:55:50.954867 progress 70 % (7 MB)
110 22:55:51.038365 progress 75 % (8 MB)
111 22:55:51.124815 progress 80 % (9 MB)
112 22:55:51.206379 progress 85 % (9 MB)
113 22:55:51.290868 progress 90 % (10 MB)
114 22:55:51.370772 progress 95 % (10 MB)
115 22:55:51.451187 progress 100 % (11 MB)
116 22:55:51.462458 11 MB downloaded in 1.69 s (6.65 MB/s)
117 22:55:51.463066 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:55:51.463917 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:55:51.464662 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 22:55:51.465229 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 22:55:51.465733 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:55:51.466237 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 22:55:51.467225 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq
125 22:55:51.468094 makedir: /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin
126 22:55:51.468745 makedir: /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/tests
127 22:55:51.469360 makedir: /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/results
128 22:55:51.469980 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-add-keys
129 22:55:51.470928 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-add-sources
130 22:55:51.471869 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-background-process-start
131 22:55:51.472873 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-background-process-stop
132 22:55:51.473873 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-common-functions
133 22:55:51.474795 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-echo-ipv4
134 22:55:51.475701 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-install-packages
135 22:55:51.476641 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-installed-packages
136 22:55:51.477531 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-os-build
137 22:55:51.478465 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-probe-channel
138 22:55:51.479373 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-probe-ip
139 22:55:51.480298 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-target-ip
140 22:55:51.481207 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-target-mac
141 22:55:51.482223 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-target-storage
142 22:55:51.483154 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-case
143 22:55:51.484085 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-event
144 22:55:51.484989 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-feedback
145 22:55:51.485892 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-raise
146 22:55:51.486776 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-reference
147 22:55:51.487675 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-runner
148 22:55:51.488632 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-set
149 22:55:51.489535 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-test-shell
150 22:55:51.490450 Updating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-install-packages (oe)
151 22:55:51.491430 Updating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/bin/lava-installed-packages (oe)
152 22:55:51.492293 Creating /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/environment
153 22:55:51.493011 LAVA metadata
154 22:55:51.493506 - LAVA_JOB_ID=931126
155 22:55:51.493928 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:55:51.494568 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 22:55:51.496385 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:55:51.497011 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 22:55:51.497423 skipped lava-vland-overlay
160 22:55:51.497902 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:55:51.498399 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 22:55:51.498820 skipped lava-multinode-overlay
163 22:55:51.499298 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:55:51.499788 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 22:55:51.500300 Loading test definitions
166 22:55:51.500842 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 22:55:51.501278 Using /lava-931126 at stage 0
168 22:55:51.503463 uuid=931126_1.5.2.4.1 testdef=None
169 22:55:51.504218 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:55:51.504968 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 22:55:51.508457 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:55:51.509323 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 22:55:51.511633 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:55:51.512553 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 22:55:51.514773 runner path: /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/0/tests/0_dmesg test_uuid 931126_1.5.2.4.1
178 22:55:51.515363 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:55:51.516195 Creating lava-test-runner.conf files
181 22:55:51.516401 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/931126/lava-overlay-v7m4uyzq/lava-931126/0 for stage 0
182 22:55:51.516738 - 0_dmesg
183 22:55:51.517108 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:55:51.517404 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 22:55:51.541094 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:55:51.541501 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:58) [common]
187 22:55:51.541769 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:55:51.542037 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:55:51.542300 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
190 22:55:52.451079 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 22:55:52.451535 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 22:55:52.451780 extracting modules file /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk
193 22:55:53.782096 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 22:55:53.782585 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 22:55:53.782862 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931126/compress-overlay-cb6o1ki8/overlay-1.5.2.5.tar.gz to ramdisk
196 22:55:53.783077 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931126/compress-overlay-cb6o1ki8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk
197 22:55:53.813002 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:55:53.813403 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 22:55:53.813674 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 22:55:53.813902 Converting downloaded kernel to a uImage
201 22:55:53.814208 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/kernel/Image /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/kernel/uImage
202 22:55:54.229989 output: Image Name:
203 22:55:54.230374 output: Created: Sun Nov 3 22:55:53 2024
204 22:55:54.230579 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:55:54.230779 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
206 22:55:54.230976 output: Load Address: 01080000
207 22:55:54.231171 output: Entry Point: 01080000
208 22:55:54.231363 output:
209 22:55:54.231689 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 22:55:54.231946 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 22:55:54.232262 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 22:55:54.232516 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:55:54.232765 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 22:55:54.233012 Building ramdisk /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk
215 22:55:56.886975 >> 188218 blocks
216 22:56:06.114205 Adding RAMdisk u-boot header.
217 22:56:06.114665 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk.cpio.gz.uboot
218 22:56:06.394079 output: Image Name:
219 22:56:06.394486 output: Created: Sun Nov 3 22:56:06 2024
220 22:56:06.394693 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:56:06.394898 output: Data Size: 26777513 Bytes = 26149.92 KiB = 25.54 MiB
222 22:56:06.395097 output: Load Address: 00000000
223 22:56:06.395297 output: Entry Point: 00000000
224 22:56:06.395491 output:
225 22:56:06.396197 rename /var/lib/lava/dispatcher/tmp/931126/extract-overlay-ramdisk-b9e5kzi9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot
226 22:56:06.396916 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 22:56:06.397448 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 22:56:06.397964 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 22:56:06.398417 No LXC device requested
230 22:56:06.398905 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:56:06.399401 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 22:56:06.399880 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:56:06.400337 Checking files for TFTP limit of 4294967296 bytes.
234 22:56:06.402966 end: 1 tftp-deploy (duration 00:00:17) [common]
235 22:56:06.403561 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:56:06.404137 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:56:06.404697 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:56:06.405254 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:56:06.405789 Using kernel file from prepare-kernel: 931126/tftp-deploy-e98soyl7/kernel/uImage
240 22:56:06.406386 substitutions:
241 22:56:06.406786 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:56:06.407185 - {DTB_ADDR}: 0x01070000
243 22:56:06.407577 - {DTB}: 931126/tftp-deploy-e98soyl7/dtb/meson-g12b-a311d-libretech-cc.dtb
244 22:56:06.407972 - {INITRD}: 931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot
245 22:56:06.408399 - {KERNEL_ADDR}: 0x01080000
246 22:56:06.408791 - {KERNEL}: 931126/tftp-deploy-e98soyl7/kernel/uImage
247 22:56:06.409180 - {LAVA_MAC}: None
248 22:56:06.409606 - {PRESEED_CONFIG}: None
249 22:56:06.409996 - {PRESEED_LOCAL}: None
250 22:56:06.410379 - {RAMDISK_ADDR}: 0x08000000
251 22:56:06.410758 - {RAMDISK}: 931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot
252 22:56:06.411148 - {ROOT_PART}: None
253 22:56:06.411532 - {ROOT}: None
254 22:56:06.411915 - {SERVER_IP}: 192.168.6.2
255 22:56:06.412333 - {TEE_ADDR}: 0x83000000
256 22:56:06.412719 - {TEE}: None
257 22:56:06.413102 Parsed boot commands:
258 22:56:06.413476 - setenv autoload no
259 22:56:06.413857 - setenv initrd_high 0xffffffff
260 22:56:06.414241 - setenv fdt_high 0xffffffff
261 22:56:06.414625 - dhcp
262 22:56:06.415006 - setenv serverip 192.168.6.2
263 22:56:06.415387 - tftpboot 0x01080000 931126/tftp-deploy-e98soyl7/kernel/uImage
264 22:56:06.415770 - tftpboot 0x08000000 931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot
265 22:56:06.416178 - tftpboot 0x01070000 931126/tftp-deploy-e98soyl7/dtb/meson-g12b-a311d-libretech-cc.dtb
266 22:56:06.416566 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:56:06.416958 - bootm 0x01080000 0x08000000 0x01070000
268 22:56:06.417439 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:56:06.418900 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:56:06.419333 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 22:56:06.434211 Setting prompt string to ['lava-test: # ']
273 22:56:06.435690 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:56:06.436321 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:56:06.436860 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:56:06.437386 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:56:06.438669 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 22:56:06.473241 >> OK - accepted request
279 22:56:06.475425 Returned 0 in 0 seconds
280 22:56:06.576656 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:56:06.578233 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:56:06.578781 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:56:06.579281 Setting prompt string to ['Hit any key to stop autoboot']
285 22:56:06.579731 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:56:06.581332 Trying 192.168.56.21...
287 22:56:06.581797 Connected to conserv1.
288 22:56:06.582196 Escape character is '^]'.
289 22:56:06.582602
290 22:56:06.583011 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 22:56:06.583427
292 22:56:17.991381 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 22:56:17.992046 bl2_stage_init 0x01
294 22:56:17.992486 bl2_stage_init 0x81
295 22:56:17.996846 hw id: 0x0000 - pwm id 0x01
296 22:56:17.997310 bl2_stage_init 0xc1
297 22:56:17.997724 bl2_stage_init 0x02
298 22:56:17.998141
299 22:56:18.002387 L0:00000000
300 22:56:18.002812 L1:20000703
301 22:56:18.003216 L2:00008067
302 22:56:18.003602 L3:14000000
303 22:56:18.008047 B2:00402000
304 22:56:18.008487 B1:e0f83180
305 22:56:18.008875
306 22:56:18.009264 TE: 58124
307 22:56:18.009650
308 22:56:18.013834 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 22:56:18.014297
310 22:56:18.014698 Board ID = 1
311 22:56:18.019206 Set A53 clk to 24M
312 22:56:18.019627 Set A73 clk to 24M
313 22:56:18.020045 Set clk81 to 24M
314 22:56:18.024765 A53 clk: 1200 MHz
315 22:56:18.025220 A73 clk: 1200 MHz
316 22:56:18.025607 CLK81: 166.6M
317 22:56:18.025992 smccc: 00012a91
318 22:56:18.030379 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 22:56:18.035933 board id: 1
320 22:56:18.041848 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:56:18.052636 fw parse done
322 22:56:18.058464 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:56:18.101173 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:56:18.112054 PIEI prepare done
325 22:56:18.112522 fastboot data load
326 22:56:18.112916 fastboot data verify
327 22:56:18.117709 verify result: 266
328 22:56:18.123307 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 22:56:18.123742 LPDDR4 probe
330 22:56:18.124219 ddr clk to 1584MHz
331 22:56:18.130391 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:56:18.168559
333 22:56:18.169020 dmc_version 0001
334 22:56:18.175206 Check phy result
335 22:56:18.181033 INFO : End of CA training
336 22:56:18.181461 INFO : End of initialization
337 22:56:18.186686 INFO : Training has run successfully!
338 22:56:18.187101 Check phy result
339 22:56:18.192225 INFO : End of initialization
340 22:56:18.192649 INFO : End of read enable training
341 22:56:18.197864 INFO : End of fine write leveling
342 22:56:18.203411 INFO : End of Write leveling coarse delay
343 22:56:18.203837 INFO : Training has run successfully!
344 22:56:18.204268 Check phy result
345 22:56:18.209016 INFO : End of initialization
346 22:56:18.209441 INFO : End of read dq deskew training
347 22:56:18.214652 INFO : End of MPR read delay center optimization
348 22:56:18.220204 INFO : End of write delay center optimization
349 22:56:18.225803 INFO : End of read delay center optimization
350 22:56:18.226221 INFO : End of max read latency training
351 22:56:18.231396 INFO : Training has run successfully!
352 22:56:18.231821 1D training succeed
353 22:56:18.239886 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:56:18.288323 Check phy result
355 22:56:18.288790 INFO : End of initialization
356 22:56:18.309983 INFO : End of 2D read delay Voltage center optimization
357 22:56:18.329099 INFO : End of 2D read delay Voltage center optimization
358 22:56:18.380996 INFO : End of 2D write delay Voltage center optimization
359 22:56:18.431073 INFO : End of 2D write delay Voltage center optimization
360 22:56:18.436729 INFO : Training has run successfully!
361 22:56:18.437163
362 22:56:18.437557 channel==0
363 22:56:18.442247 RxClkDly_Margin_A0==88 ps 9
364 22:56:18.442661 TxDqDly_Margin_A0==98 ps 10
365 22:56:18.447817 RxClkDly_Margin_A1==88 ps 9
366 22:56:18.448289 TxDqDly_Margin_A1==98 ps 10
367 22:56:18.448685 TrainedVREFDQ_A0==74
368 22:56:18.453517 TrainedVREFDQ_A1==74
369 22:56:18.453943 VrefDac_Margin_A0==25
370 22:56:18.454330 DeviceVref_Margin_A0==40
371 22:56:18.459085 VrefDac_Margin_A1==25
372 22:56:18.459510 DeviceVref_Margin_A1==40
373 22:56:18.459900
374 22:56:18.460324
375 22:56:18.464737 channel==1
376 22:56:18.465160 RxClkDly_Margin_A0==98 ps 10
377 22:56:18.465551 TxDqDly_Margin_A0==98 ps 10
378 22:56:18.470245 RxClkDly_Margin_A1==88 ps 9
379 22:56:18.470661 TxDqDly_Margin_A1==88 ps 9
380 22:56:18.475858 TrainedVREFDQ_A0==77
381 22:56:18.476318 TrainedVREFDQ_A1==77
382 22:56:18.476714 VrefDac_Margin_A0==22
383 22:56:18.481479 DeviceVref_Margin_A0==37
384 22:56:18.481903 VrefDac_Margin_A1==24
385 22:56:18.486994 DeviceVref_Margin_A1==37
386 22:56:18.487417
387 22:56:18.487816 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:56:18.488239
389 22:56:18.520760 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 22:56:18.521277 2D training succeed
391 22:56:18.526266 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:56:18.531741 auto size-- 65535DDR cs0 size: 2048MB
393 22:56:18.532197 DDR cs1 size: 2048MB
394 22:56:18.537432 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:56:18.537848 cs0 DataBus test pass
396 22:56:18.542933 cs1 DataBus test pass
397 22:56:18.543351 cs0 AddrBus test pass
398 22:56:18.543737 cs1 AddrBus test pass
399 22:56:18.544162
400 22:56:18.548669 100bdlr_step_size ps== 420
401 22:56:18.549106 result report
402 22:56:18.554164 boot times 0Enable ddr reg access
403 22:56:18.559497 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:56:18.572947 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 22:56:19.145025 0.0;M3 CHK:0;cm4_sp_mode 0
406 22:56:19.145596 MVN_1=0x00000000
407 22:56:19.150439 MVN_2=0x00000000
408 22:56:19.156206 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 22:56:19.156639 OPS=0x10
410 22:56:19.157041 ring efuse init
411 22:56:19.157434 chipver efuse init
412 22:56:19.161809 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 22:56:19.167439 [0.018960 Inits done]
414 22:56:19.167865 secure task start!
415 22:56:19.168324 high task start!
416 22:56:19.171082 low task start!
417 22:56:19.171499 run into bl31
418 22:56:19.178750 NOTICE: BL31: v1.3(release):4fc40b1
419 22:56:19.186427 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 22:56:19.186863 NOTICE: BL31: G12A normal boot!
421 22:56:19.212380 NOTICE: BL31: BL33 decompress pass
422 22:56:19.218071 ERROR: Error initializing runtime service opteed_fast
423 22:56:20.451065
424 22:56:20.451682
425 22:56:20.459360 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 22:56:20.459811
427 22:56:20.460250 Model: Libre Computer AML-A311D-CC Alta
428 22:56:20.668023 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 22:56:20.690268 DRAM: 2 GiB (effective 3.8 GiB)
430 22:56:20.834276 Core: 408 devices, 31 uclasses, devicetree: separate
431 22:56:20.840082 WDT: Not starting watchdog@f0d0
432 22:56:20.872440 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 22:56:20.884829 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 22:56:20.888877 ** Bad device specification mmc 0 **
435 22:56:20.900101 Card did not respond to voltage select! : -110
436 22:56:20.906887 ** Bad device specification mmc 0 **
437 22:56:20.907340 Couldn't find partition mmc 0
438 22:56:20.916112 Card did not respond to voltage select! : -110
439 22:56:20.921618 ** Bad device specification mmc 0 **
440 22:56:20.922048 Couldn't find partition mmc 0
441 22:56:20.925889 Error: could not access storage.
442 22:56:22.191696 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 22:56:22.192326 bl2_stage_init 0x01
444 22:56:22.192750 bl2_stage_init 0x81
445 22:56:22.197291 hw id: 0x0000 - pwm id 0x01
446 22:56:22.197778 bl2_stage_init 0xc1
447 22:56:22.198190 bl2_stage_init 0x02
448 22:56:22.198592
449 22:56:22.202863 L0:00000000
450 22:56:22.203327 L1:20000703
451 22:56:22.203733 L2:00008067
452 22:56:22.204166 L3:14000000
453 22:56:22.208446 B2:00402000
454 22:56:22.208899 B1:e0f83180
455 22:56:22.209304
456 22:56:22.209702 TE: 58167
457 22:56:22.210101
458 22:56:22.214185 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 22:56:22.214664
460 22:56:22.215097 Board ID = 1
461 22:56:22.219654 Set A53 clk to 24M
462 22:56:22.220149 Set A73 clk to 24M
463 22:56:22.220559 Set clk81 to 24M
464 22:56:22.225251 A53 clk: 1200 MHz
465 22:56:22.225744 A73 clk: 1200 MHz
466 22:56:22.226148 CLK81: 166.6M
467 22:56:22.226541 smccc: 00012abe
468 22:56:22.230838 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 22:56:22.236437 board id: 1
470 22:56:22.242311 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 22:56:22.253002 fw parse done
472 22:56:22.259054 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 22:56:22.300627 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 22:56:22.312535 PIEI prepare done
475 22:56:22.313023 fastboot data load
476 22:56:22.313436 fastboot data verify
477 22:56:22.318317 verify result: 266
478 22:56:22.323779 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 22:56:22.324295 LPDDR4 probe
480 22:56:22.324712 ddr clk to 1584MHz
481 22:56:22.331678 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 22:56:22.368275
483 22:56:22.368788 dmc_version 0001
484 22:56:22.374728 Check phy result
485 22:56:22.381590 INFO : End of CA training
486 22:56:22.382071 INFO : End of initialization
487 22:56:22.387171 INFO : Training has run successfully!
488 22:56:22.387632 Check phy result
489 22:56:22.392748 INFO : End of initialization
490 22:56:22.393202 INFO : End of read enable training
491 22:56:22.396078 INFO : End of fine write leveling
492 22:56:22.401590 INFO : End of Write leveling coarse delay
493 22:56:22.407304 INFO : Training has run successfully!
494 22:56:22.407761 Check phy result
495 22:56:22.408210 INFO : End of initialization
496 22:56:22.412789 INFO : End of read dq deskew training
497 22:56:22.418387 INFO : End of MPR read delay center optimization
498 22:56:22.418837 INFO : End of write delay center optimization
499 22:56:22.424075 INFO : End of read delay center optimization
500 22:56:22.429598 INFO : End of max read latency training
501 22:56:22.430058 INFO : Training has run successfully!
502 22:56:22.435293 1D training succeed
503 22:56:22.441186 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 22:56:22.488277 Check phy result
505 22:56:22.488822 INFO : End of initialization
506 22:56:22.510526 INFO : End of 2D read delay Voltage center optimization
507 22:56:22.530714 INFO : End of 2D read delay Voltage center optimization
508 22:56:22.581867 INFO : End of 2D write delay Voltage center optimization
509 22:56:22.632209 INFO : End of 2D write delay Voltage center optimization
510 22:56:22.637732 INFO : Training has run successfully!
511 22:56:22.638200
512 22:56:22.638608 channel==0
513 22:56:22.643359 RxClkDly_Margin_A0==88 ps 9
514 22:56:22.643820 TxDqDly_Margin_A0==98 ps 10
515 22:56:22.646593 RxClkDly_Margin_A1==88 ps 9
516 22:56:22.647048 TxDqDly_Margin_A1==98 ps 10
517 22:56:22.652314 TrainedVREFDQ_A0==74
518 22:56:22.652784 TrainedVREFDQ_A1==74
519 22:56:22.653193 VrefDac_Margin_A0==25
520 22:56:22.657803 DeviceVref_Margin_A0==40
521 22:56:22.658261 VrefDac_Margin_A1==25
522 22:56:22.663411 DeviceVref_Margin_A1==40
523 22:56:22.663882
524 22:56:22.664326
525 22:56:22.664725 channel==1
526 22:56:22.665116 RxClkDly_Margin_A0==98 ps 10
527 22:56:22.669154 TxDqDly_Margin_A0==88 ps 9
528 22:56:22.669620 RxClkDly_Margin_A1==98 ps 10
529 22:56:22.674601 TxDqDly_Margin_A1==88 ps 9
530 22:56:22.675065 TrainedVREFDQ_A0==76
531 22:56:22.675474 TrainedVREFDQ_A1==77
532 22:56:22.680350 VrefDac_Margin_A0==23
533 22:56:22.680813 DeviceVref_Margin_A0==38
534 22:56:22.686006 VrefDac_Margin_A1==24
535 22:56:22.686467 DeviceVref_Margin_A1==37
536 22:56:22.686874
537 22:56:22.691434 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 22:56:22.691904
539 22:56:22.719352 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 22:56:22.725029 2D training succeed
541 22:56:22.730601 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 22:56:22.731064 auto size-- 65535DDR cs0 size: 2048MB
543 22:56:22.736345 DDR cs1 size: 2048MB
544 22:56:22.736808 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 22:56:22.741814 cs0 DataBus test pass
546 22:56:22.742270 cs1 DataBus test pass
547 22:56:22.742672 cs0 AddrBus test pass
548 22:56:22.747434 cs1 AddrBus test pass
549 22:56:22.747906
550 22:56:22.748566 100bdlr_step_size ps== 420
551 22:56:22.749030 result report
552 22:56:22.753013 boot times 0Enable ddr reg access
553 22:56:22.760546 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 22:56:22.774082 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 22:56:23.347755 0.0;M3 CHK:0;cm4_sp_mode 0
556 22:56:23.348407 MVN_1=0x00000000
557 22:56:23.353348 MVN_2=0x00000000
558 22:56:23.359049 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 22:56:23.359583 OPS=0x10
560 22:56:23.360082 ring efuse init
561 22:56:23.360489 chipver efuse init
562 22:56:23.364622 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 22:56:23.370289 [0.018960 Inits done]
564 22:56:23.370732 secure task start!
565 22:56:23.371124 high task start!
566 22:56:23.374730 low task start!
567 22:56:23.375182 run into bl31
568 22:56:23.381350 NOTICE: BL31: v1.3(release):4fc40b1
569 22:56:23.388190 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 22:56:23.388635 NOTICE: BL31: G12A normal boot!
571 22:56:23.414695 NOTICE: BL31: BL33 decompress pass
572 22:56:23.419352 ERROR: Error initializing runtime service opteed_fast
573 22:56:24.653212
574 22:56:24.653825
575 22:56:24.660744 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 22:56:24.661212
577 22:56:24.661631 Model: Libre Computer AML-A311D-CC Alta
578 22:56:24.870029 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 22:56:24.892643 DRAM: 2 GiB (effective 3.8 GiB)
580 22:56:25.036644 Core: 408 devices, 31 uclasses, devicetree: separate
581 22:56:25.041421 WDT: Not starting watchdog@f0d0
582 22:56:25.074719 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 22:56:25.086987 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 22:56:25.092038 ** Bad device specification mmc 0 **
585 22:56:25.102309 Card did not respond to voltage select! : -110
586 22:56:25.109960 ** Bad device specification mmc 0 **
587 22:56:25.110402 Couldn't find partition mmc 0
588 22:56:25.118281 Card did not respond to voltage select! : -110
589 22:56:25.123932 ** Bad device specification mmc 0 **
590 22:56:25.124444 Couldn't find partition mmc 0
591 22:56:25.127882 Error: could not access storage.
592 22:56:25.471451 Net: eth0: ethernet@ff3f0000
593 22:56:25.472113 starting USB...
594 22:56:25.723095 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 22:56:25.723641 Starting the controller
596 22:56:25.730239 USB XHCI 1.10
597 22:56:27.443818 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 22:56:27.444525 bl2_stage_init 0x01
599 22:56:27.444970 bl2_stage_init 0x81
600 22:56:27.449297 hw id: 0x0000 - pwm id 0x01
601 22:56:27.449843 bl2_stage_init 0xc1
602 22:56:27.450270 bl2_stage_init 0x02
603 22:56:27.450689
604 22:56:27.454996 L0:00000000
605 22:56:27.455505 L1:20000703
606 22:56:27.455931 L2:00008067
607 22:56:27.456392 L3:14000000
608 22:56:27.457826 B2:00402000
609 22:56:27.458497 B1:e0f83180
610 22:56:27.458969
611 22:56:27.459400 TE: 58167
612 22:56:27.459833
613 22:56:27.469006 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 22:56:27.469724
615 22:56:27.470201 Board ID = 1
616 22:56:27.470625 Set A53 clk to 24M
617 22:56:27.471039 Set A73 clk to 24M
618 22:56:27.474700 Set clk81 to 24M
619 22:56:27.475123 A53 clk: 1200 MHz
620 22:56:27.475351 A73 clk: 1200 MHz
621 22:56:27.480159 CLK81: 166.6M
622 22:56:27.480448 smccc: 00012abd
623 22:56:27.485746 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 22:56:27.486030 board id: 1
625 22:56:27.494524 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 22:56:27.504933 fw parse done
627 22:56:27.510958 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 22:56:27.552925 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 22:56:27.564403 PIEI prepare done
630 22:56:27.564879 fastboot data load
631 22:56:27.565295 fastboot data verify
632 22:56:27.570055 verify result: 266
633 22:56:27.575688 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 22:56:27.576187 LPDDR4 probe
635 22:56:27.576593 ddr clk to 1584MHz
636 22:56:27.582745 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 22:56:27.620024
638 22:56:27.620567 dmc_version 0001
639 22:56:27.626701 Check phy result
640 22:56:27.633505 INFO : End of CA training
641 22:56:27.633977 INFO : End of initialization
642 22:56:27.639175 INFO : Training has run successfully!
643 22:56:27.639641 Check phy result
644 22:56:27.644658 INFO : End of initialization
645 22:56:27.645125 INFO : End of read enable training
646 22:56:27.648131 INFO : End of fine write leveling
647 22:56:27.653723 INFO : End of Write leveling coarse delay
648 22:56:27.659260 INFO : Training has run successfully!
649 22:56:27.659732 Check phy result
650 22:56:27.660183 INFO : End of initialization
651 22:56:27.664979 INFO : End of read dq deskew training
652 22:56:27.670472 INFO : End of MPR read delay center optimization
653 22:56:27.670940 INFO : End of write delay center optimization
654 22:56:27.676082 INFO : End of read delay center optimization
655 22:56:27.681659 INFO : End of max read latency training
656 22:56:27.682125 INFO : Training has run successfully!
657 22:56:27.687244 1D training succeed
658 22:56:27.693088 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 22:56:27.740634 Check phy result
660 22:56:27.741125 INFO : End of initialization
661 22:56:27.763052 INFO : End of 2D read delay Voltage center optimization
662 22:56:27.783110 INFO : End of 2D read delay Voltage center optimization
663 22:56:27.835084 INFO : End of 2D write delay Voltage center optimization
664 22:56:27.884235 INFO : End of 2D write delay Voltage center optimization
665 22:56:27.889798 INFO : Training has run successfully!
666 22:56:27.890270
667 22:56:27.890701 channel==0
668 22:56:27.895383 RxClkDly_Margin_A0==88 ps 9
669 22:56:27.895854 TxDqDly_Margin_A0==98 ps 10
670 22:56:27.898698 RxClkDly_Margin_A1==88 ps 9
671 22:56:27.899145 TxDqDly_Margin_A1==98 ps 10
672 22:56:27.904245 TrainedVREFDQ_A0==74
673 22:56:27.904720 TrainedVREFDQ_A1==74
674 22:56:27.909964 VrefDac_Margin_A0==24
675 22:56:27.910435 DeviceVref_Margin_A0==40
676 22:56:27.910852 VrefDac_Margin_A1==24
677 22:56:27.915451 DeviceVref_Margin_A1==40
678 22:56:27.915928
679 22:56:27.916402
680 22:56:27.916813 channel==1
681 22:56:27.917220 RxClkDly_Margin_A0==98 ps 10
682 22:56:27.921153 TxDqDly_Margin_A0==88 ps 9
683 22:56:27.921627 RxClkDly_Margin_A1==98 ps 10
684 22:56:27.926738 TxDqDly_Margin_A1==88 ps 9
685 22:56:27.927218 TrainedVREFDQ_A0==76
686 22:56:27.927644 TrainedVREFDQ_A1==77
687 22:56:27.932235 VrefDac_Margin_A0==22
688 22:56:27.932701 DeviceVref_Margin_A0==38
689 22:56:27.937968 VrefDac_Margin_A1==22
690 22:56:27.938432 DeviceVref_Margin_A1==37
691 22:56:27.938838
692 22:56:27.943438 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 22:56:27.943907
694 22:56:27.971460 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 22:56:27.977085 2D training succeed
696 22:56:27.982664 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 22:56:27.983136 auto size-- 65535DDR cs0 size: 2048MB
698 22:56:27.988238 DDR cs1 size: 2048MB
699 22:56:27.988729 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 22:56:27.993991 cs0 DataBus test pass
701 22:56:27.994482 cs1 DataBus test pass
702 22:56:27.994890 cs0 AddrBus test pass
703 22:56:27.999488 cs1 AddrBus test pass
704 22:56:28.000075
705 22:56:28.000548 100bdlr_step_size ps== 420
706 22:56:28.001010 result report
707 22:56:28.005229 boot times 0Enable ddr reg access
708 22:56:28.012870 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 22:56:28.026285 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 22:56:28.598297 0.0;M3 CHK:0;cm4_sp_mode 0
711 22:56:28.598907 MVN_1=0x00000000
712 22:56:28.603890 MVN_2=0x00000000
713 22:56:28.609599 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 22:56:28.610139 OPS=0x10
715 22:56:28.610542 ring efuse init
716 22:56:28.610928 chipver efuse init
717 22:56:28.615154 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 22:56:28.620758 [0.018961 Inits done]
719 22:56:28.621275 secure task start!
720 22:56:28.621689 high task start!
721 22:56:28.625311 low task start!
722 22:56:28.625797 run into bl31
723 22:56:28.632087 NOTICE: BL31: v1.3(release):4fc40b1
724 22:56:28.639759 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 22:56:28.640286 NOTICE: BL31: G12A normal boot!
726 22:56:28.665177 NOTICE: BL31: BL33 decompress pass
727 22:56:28.670876 ERROR: Error initializing runtime service opteed_fast
728 22:56:29.903670
729 22:56:29.904321
730 22:56:29.912158 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 22:56:29.912680
732 22:56:29.913105 Model: Libre Computer AML-A311D-CC Alta
733 22:56:30.120479 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 22:56:30.143817 DRAM: 2 GiB (effective 3.8 GiB)
735 22:56:30.286881 Core: 408 devices, 31 uclasses, devicetree: separate
736 22:56:30.292693 WDT: Not starting watchdog@f0d0
737 22:56:30.325075 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 22:56:30.337487 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 22:56:30.342461 ** Bad device specification mmc 0 **
740 22:56:30.352855 Card did not respond to voltage select! : -110
741 22:56:30.360467 ** Bad device specification mmc 0 **
742 22:56:30.360967 Couldn't find partition mmc 0
743 22:56:30.368799 Card did not respond to voltage select! : -110
744 22:56:30.374353 ** Bad device specification mmc 0 **
745 22:56:30.374907 Couldn't find partition mmc 0
746 22:56:30.379416 Error: could not access storage.
747 22:56:30.722876 Net: eth0: ethernet@ff3f0000
748 22:56:30.723499 starting USB...
749 22:56:30.974768 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 22:56:30.975356 Starting the controller
751 22:56:30.981656 USB XHCI 1.10
752 22:56:33.142081 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 22:56:33.142685 bl2_stage_init 0x01
754 22:56:33.143107 bl2_stage_init 0x81
755 22:56:33.147789 hw id: 0x0000 - pwm id 0x01
756 22:56:33.148301 bl2_stage_init 0xc1
757 22:56:33.148724 bl2_stage_init 0x02
758 22:56:33.149129
759 22:56:33.153195 L0:00000000
760 22:56:33.153667 L1:20000703
761 22:56:33.154076 L2:00008067
762 22:56:33.154480 L3:14000000
763 22:56:33.156226 B2:00402000
764 22:56:33.156688 B1:e0f83180
765 22:56:33.157102
766 22:56:33.157507 TE: 58159
767 22:56:33.157909
768 22:56:33.167347 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 22:56:33.167863
770 22:56:33.168323 Board ID = 1
771 22:56:33.168732 Set A53 clk to 24M
772 22:56:33.169132 Set A73 clk to 24M
773 22:56:33.172977 Set clk81 to 24M
774 22:56:33.173457 A53 clk: 1200 MHz
775 22:56:33.173868 A73 clk: 1200 MHz
776 22:56:33.178656 CLK81: 166.6M
777 22:56:33.179150 smccc: 00012ab5
778 22:56:33.184206 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 22:56:33.184705 board id: 1
780 22:56:33.192906 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 22:56:33.203435 fw parse done
782 22:56:33.209517 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 22:56:33.251863 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 22:56:33.262777 PIEI prepare done
785 22:56:33.263294 fastboot data load
786 22:56:33.263707 fastboot data verify
787 22:56:33.268501 verify result: 266
788 22:56:33.274101 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 22:56:33.274595 LPDDR4 probe
790 22:56:33.275000 ddr clk to 1584MHz
791 22:56:33.282059 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 22:56:33.319308
793 22:56:33.319822 dmc_version 0001
794 22:56:33.325978 Check phy result
795 22:56:33.331866 INFO : End of CA training
796 22:56:33.332400 INFO : End of initialization
797 22:56:33.337460 INFO : Training has run successfully!
798 22:56:33.337936 Check phy result
799 22:56:33.343039 INFO : End of initialization
800 22:56:33.343508 INFO : End of read enable training
801 22:56:33.348622 INFO : End of fine write leveling
802 22:56:33.354251 INFO : End of Write leveling coarse delay
803 22:56:33.354730 INFO : Training has run successfully!
804 22:56:33.355138 Check phy result
805 22:56:33.359850 INFO : End of initialization
806 22:56:33.360360 INFO : End of read dq deskew training
807 22:56:33.365474 INFO : End of MPR read delay center optimization
808 22:56:33.371029 INFO : End of write delay center optimization
809 22:56:33.376669 INFO : End of read delay center optimization
810 22:56:33.377162 INFO : End of max read latency training
811 22:56:33.382265 INFO : Training has run successfully!
812 22:56:33.382757 1D training succeed
813 22:56:33.391371 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 22:56:33.439028 Check phy result
815 22:56:33.439554 INFO : End of initialization
816 22:56:33.460698 INFO : End of 2D read delay Voltage center optimization
817 22:56:33.480771 INFO : End of 2D read delay Voltage center optimization
818 22:56:33.532697 INFO : End of 2D write delay Voltage center optimization
819 22:56:33.581836 INFO : End of 2D write delay Voltage center optimization
820 22:56:33.587474 INFO : Training has run successfully!
821 22:56:33.587970
822 22:56:33.588434 channel==0
823 22:56:33.593098 RxClkDly_Margin_A0==88 ps 9
824 22:56:33.593595 TxDqDly_Margin_A0==98 ps 10
825 22:56:33.598677 RxClkDly_Margin_A1==88 ps 9
826 22:56:33.599179 TxDqDly_Margin_A1==98 ps 10
827 22:56:33.599610 TrainedVREFDQ_A0==74
828 22:56:33.604355 TrainedVREFDQ_A1==74
829 22:56:33.604892 VrefDac_Margin_A0==25
830 22:56:33.605283 DeviceVref_Margin_A0==40
831 22:56:33.609944 VrefDac_Margin_A1==24
832 22:56:33.610461 DeviceVref_Margin_A1==40
833 22:56:33.610898
834 22:56:33.611298
835 22:56:33.615463 channel==1
836 22:56:33.615970 RxClkDly_Margin_A0==98 ps 10
837 22:56:33.616403 TxDqDly_Margin_A0==98 ps 10
838 22:56:33.621026 RxClkDly_Margin_A1==98 ps 10
839 22:56:33.621507 TxDqDly_Margin_A1==88 ps 9
840 22:56:33.626626 TrainedVREFDQ_A0==77
841 22:56:33.627116 TrainedVREFDQ_A1==77
842 22:56:33.627509 VrefDac_Margin_A0==22
843 22:56:33.632219 DeviceVref_Margin_A0==37
844 22:56:33.632688 VrefDac_Margin_A1==22
845 22:56:33.637812 DeviceVref_Margin_A1==37
846 22:56:33.638278
847 22:56:33.638667 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 22:56:33.643412
849 22:56:33.671444 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 22:56:33.672083 2D training succeed
851 22:56:33.677056 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 22:56:33.682675 auto size-- 65535DDR cs0 size: 2048MB
853 22:56:33.683161 DDR cs1 size: 2048MB
854 22:56:33.688246 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 22:56:33.688717 cs0 DataBus test pass
856 22:56:33.693873 cs1 DataBus test pass
857 22:56:33.694348 cs0 AddrBus test pass
858 22:56:33.694736 cs1 AddrBus test pass
859 22:56:33.695117
860 22:56:33.699450 100bdlr_step_size ps== 415
861 22:56:33.699933 result report
862 22:56:33.705043 boot times 0Enable ddr reg access
863 22:56:33.710467 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 22:56:33.723916 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 22:56:34.296062 0.0;M3 CHK:0;cm4_sp_mode 0
866 22:56:34.296702 MVN_1=0x00000000
867 22:56:34.301484 MVN_2=0x00000000
868 22:56:34.307222 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 22:56:34.307772 OPS=0x10
870 22:56:34.308230 ring efuse init
871 22:56:34.308647 chipver efuse init
872 22:56:34.315390 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 22:56:34.316016 [0.018961 Inits done]
874 22:56:34.323064 secure task start!
875 22:56:34.323666 high task start!
876 22:56:34.324127 low task start!
877 22:56:34.324543 run into bl31
878 22:56:34.329642 NOTICE: BL31: v1.3(release):4fc40b1
879 22:56:34.337427 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 22:56:34.338042 NOTICE: BL31: G12A normal boot!
881 22:56:34.363082 NOTICE: BL31: BL33 decompress pass
882 22:56:34.368471 ERROR: Error initializing runtime service opteed_fast
883 22:56:35.601218
884 22:56:35.601803
885 22:56:35.609078 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 22:56:35.609648
887 22:56:35.610081 Model: Libre Computer AML-A311D-CC Alta
888 22:56:35.818233 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 22:56:35.841558 DRAM: 2 GiB (effective 3.8 GiB)
890 22:56:35.984553 Core: 408 devices, 31 uclasses, devicetree: separate
891 22:56:35.990412 WDT: Not starting watchdog@f0d0
892 22:56:36.022655 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 22:56:36.035079 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 22:56:36.040202 ** Bad device specification mmc 0 **
895 22:56:36.050472 Card did not respond to voltage select! : -110
896 22:56:36.058176 ** Bad device specification mmc 0 **
897 22:56:36.058668 Couldn't find partition mmc 0
898 22:56:36.066430 Card did not respond to voltage select! : -110
899 22:56:36.072020 ** Bad device specification mmc 0 **
900 22:56:36.072528 Couldn't find partition mmc 0
901 22:56:36.077034 Error: could not access storage.
902 22:56:36.419238 Net: eth0: ethernet@ff3f0000
903 22:56:36.419832 starting USB...
904 22:56:36.671300 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 22:56:36.671878 Starting the controller
906 22:56:36.678492 USB XHCI 1.10
907 22:56:38.541835 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 22:56:38.542426 bl2_stage_init 0x01
909 22:56:38.542857 bl2_stage_init 0x81
910 22:56:38.547411 hw id: 0x0000 - pwm id 0x01
911 22:56:38.547898 bl2_stage_init 0xc1
912 22:56:38.548369 bl2_stage_init 0x02
913 22:56:38.548782
914 22:56:38.552950 L0:00000000
915 22:56:38.553439 L1:20000703
916 22:56:38.553873 L2:00008067
917 22:56:38.554291 L3:14000000
918 22:56:38.558595 B2:00402000
919 22:56:38.559074 B1:e0f83180
920 22:56:38.559486
921 22:56:38.559893 TE: 58167
922 22:56:38.560338
923 22:56:38.564094 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 22:56:38.564580
925 22:56:38.565000 Board ID = 1
926 22:56:38.569697 Set A53 clk to 24M
927 22:56:38.570164 Set A73 clk to 24M
928 22:56:38.570573 Set clk81 to 24M
929 22:56:38.575308 A53 clk: 1200 MHz
930 22:56:38.575773 A73 clk: 1200 MHz
931 22:56:38.576222 CLK81: 166.6M
932 22:56:38.576628 smccc: 00012abe
933 22:56:38.580866 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 22:56:38.586481 board id: 1
935 22:56:38.592540 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 22:56:38.603121 fw parse done
937 22:56:38.609116 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 22:56:38.651688 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 22:56:38.662590 PIEI prepare done
940 22:56:38.663087 fastboot data load
941 22:56:38.663485 fastboot data verify
942 22:56:38.668248 verify result: 266
943 22:56:38.673797 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 22:56:38.674262 LPDDR4 probe
945 22:56:38.674652 ddr clk to 1584MHz
946 22:56:38.681762 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 22:56:38.718154
948 22:56:38.718631 dmc_version 0001
949 22:56:38.725706 Check phy result
950 22:56:38.731683 INFO : End of CA training
951 22:56:38.732174 INFO : End of initialization
952 22:56:38.737291 INFO : Training has run successfully!
953 22:56:38.737801 Check phy result
954 22:56:38.742838 INFO : End of initialization
955 22:56:38.743332 INFO : End of read enable training
956 22:56:38.748591 INFO : End of fine write leveling
957 22:56:38.754051 INFO : End of Write leveling coarse delay
958 22:56:38.754529 INFO : Training has run successfully!
959 22:56:38.754943 Check phy result
960 22:56:38.759764 INFO : End of initialization
961 22:56:38.760278 INFO : End of read dq deskew training
962 22:56:38.765133 INFO : End of MPR read delay center optimization
963 22:56:38.770722 INFO : End of write delay center optimization
964 22:56:38.776354 INFO : End of read delay center optimization
965 22:56:38.776818 INFO : End of max read latency training
966 22:56:38.781948 INFO : Training has run successfully!
967 22:56:38.782415 1D training succeed
968 22:56:38.790137 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 22:56:38.838728 Check phy result
970 22:56:38.839271 INFO : End of initialization
971 22:56:38.861186 INFO : End of 2D read delay Voltage center optimization
972 22:56:38.880390 INFO : End of 2D read delay Voltage center optimization
973 22:56:38.933220 INFO : End of 2D write delay Voltage center optimization
974 22:56:38.982440 INFO : End of 2D write delay Voltage center optimization
975 22:56:38.988103 INFO : Training has run successfully!
976 22:56:38.988591
977 22:56:38.989009 channel==0
978 22:56:38.993667 RxClkDly_Margin_A0==78 ps 8
979 22:56:38.994135 TxDqDly_Margin_A0==98 ps 10
980 22:56:38.999220 RxClkDly_Margin_A1==88 ps 9
981 22:56:38.999682 TxDqDly_Margin_A1==98 ps 10
982 22:56:39.000128 TrainedVREFDQ_A0==74
983 22:56:39.004804 TrainedVREFDQ_A1==75
984 22:56:39.005277 VrefDac_Margin_A0==25
985 22:56:39.005679 DeviceVref_Margin_A0==40
986 22:56:39.010411 VrefDac_Margin_A1==25
987 22:56:39.010881 DeviceVref_Margin_A1==39
988 22:56:39.011290
989 22:56:39.011695
990 22:56:39.016014 channel==1
991 22:56:39.016479 RxClkDly_Margin_A0==98 ps 10
992 22:56:39.016886 TxDqDly_Margin_A0==98 ps 10
993 22:56:39.021609 RxClkDly_Margin_A1==88 ps 9
994 22:56:39.022076 TxDqDly_Margin_A1==88 ps 9
995 22:56:39.027221 TrainedVREFDQ_A0==76
996 22:56:39.027707 TrainedVREFDQ_A1==77
997 22:56:39.028148 VrefDac_Margin_A0==22
998 22:56:39.032814 DeviceVref_Margin_A0==38
999 22:56:39.033278 VrefDac_Margin_A1==24
1000 22:56:39.038407 DeviceVref_Margin_A1==37
1001 22:56:39.038877
1002 22:56:39.039286 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 22:56:39.039692
1004 22:56:39.071954 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 22:56:39.072538 2D training succeed
1006 22:56:39.077604 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 22:56:39.083197 auto size-- 65535DDR cs0 size: 2048MB
1008 22:56:39.083672 DDR cs1 size: 2048MB
1009 22:56:39.088814 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 22:56:39.089285 cs0 DataBus test pass
1011 22:56:39.094392 cs1 DataBus test pass
1012 22:56:39.094859 cs0 AddrBus test pass
1013 22:56:39.095262 cs1 AddrBus test pass
1014 22:56:39.095658
1015 22:56:39.100014 100bdlr_step_size ps== 420
1016 22:56:39.100495 result report
1017 22:56:39.105614 boot times 0Enable ddr reg access
1018 22:56:39.110958 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 22:56:39.124371 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 22:56:39.696433 0.0;M3 CHK:0;cm4_sp_mode 0
1021 22:56:39.697377 MVN_1=0x00000000
1022 22:56:39.702004 MVN_2=0x00000000
1023 22:56:39.707659 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 22:56:39.708360 OPS=0x10
1025 22:56:39.708860 ring efuse init
1026 22:56:39.709347 chipver efuse init
1027 22:56:39.715879 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 22:56:39.716483 [0.018961 Inits done]
1029 22:56:39.716935 secure task start!
1030 22:56:39.723387 high task start!
1031 22:56:39.723938 low task start!
1032 22:56:39.724431 run into bl31
1033 22:56:39.730048 NOTICE: BL31: v1.3(release):4fc40b1
1034 22:56:39.737831 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 22:56:39.738594 NOTICE: BL31: G12A normal boot!
1036 22:56:39.763669 NOTICE: BL31: BL33 decompress pass
1037 22:56:39.768958 ERROR: Error initializing runtime service opteed_fast
1038 22:56:41.001558
1039 22:56:41.001956
1040 22:56:41.009097 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 22:56:41.009389
1042 22:56:41.009607 Model: Libre Computer AML-A311D-CC Alta
1043 22:56:41.218483 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 22:56:41.240992 DRAM: 2 GiB (effective 3.8 GiB)
1045 22:56:41.384897 Core: 408 devices, 31 uclasses, devicetree: separate
1046 22:56:41.390861 WDT: Not starting watchdog@f0d0
1047 22:56:41.422941 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 22:56:41.435534 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 22:56:41.440422 ** Bad device specification mmc 0 **
1050 22:56:41.450787 Card did not respond to voltage select! : -110
1051 22:56:41.458398 ** Bad device specification mmc 0 **
1052 22:56:41.458853 Couldn't find partition mmc 0
1053 22:56:41.466768 Card did not respond to voltage select! : -110
1054 22:56:41.472293 ** Bad device specification mmc 0 **
1055 22:56:41.472768 Couldn't find partition mmc 0
1056 22:56:41.477326 Error: could not access storage.
1057 22:56:41.820942 Net: eth0: ethernet@ff3f0000
1058 22:56:41.821512 starting USB...
1059 22:56:42.072707 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 22:56:42.073298 Starting the controller
1061 22:56:42.078620 USB XHCI 1.10
1062 22:56:43.633585 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 22:56:43.641060 scanning usb for storage devices... 0 Storage Device(s) found
1065 22:56:43.692686 Hit any key to stop autoboot: 1
1066 22:56:43.693510 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 22:56:43.694137 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 22:56:43.694604 Setting prompt string to ['=>']
1069 22:56:43.695064 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 22:56:43.699386 0
1071 22:56:43.700240 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 22:56:43.700719 Sending with 10 millisecond of delay
1074 22:56:44.835392 => setenv autoload no
1075 22:56:44.846211 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 22:56:44.851045 setenv autoload no
1077 22:56:44.851782 Sending with 10 millisecond of delay
1079 22:56:46.648763 => setenv initrd_high 0xffffffff
1080 22:56:46.659524 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 22:56:46.660430 setenv initrd_high 0xffffffff
1082 22:56:46.661140 Sending with 10 millisecond of delay
1084 22:56:48.277654 => setenv fdt_high 0xffffffff
1085 22:56:48.288247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 22:56:48.288814 setenv fdt_high 0xffffffff
1087 22:56:48.289312 Sending with 10 millisecond of delay
1089 22:56:48.580921 => dhcp
1090 22:56:48.591518 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 22:56:48.592186 dhcp
1092 22:56:48.592463 Speed: 1000, full duplex
1093 22:56:48.592701 BOOTP broadcast 1
1094 22:56:48.604228 DHCP client bound to address 192.168.6.27 (13 ms)
1095 22:56:48.604861 Sending with 10 millisecond of delay
1097 22:56:50.281981 => setenv serverip 192.168.6.2
1098 22:56:50.292560 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 22:56:50.293169 setenv serverip 192.168.6.2
1100 22:56:50.293635 Sending with 10 millisecond of delay
1102 22:56:54.021399 => tftpboot 0x01080000 931126/tftp-deploy-e98soyl7/kernel/uImage
1103 22:56:54.032356 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 22:56:54.032949 tftpboot 0x01080000 931126/tftp-deploy-e98soyl7/kernel/uImage
1105 22:56:54.033215 Speed: 1000, full duplex
1106 22:56:54.033432 Using ethernet@ff3f0000 device
1107 22:56:54.034846 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 22:56:54.040301 Filename '931126/tftp-deploy-e98soyl7/kernel/uImage'.
1109 22:56:54.044324 Load address: 0x1080000
1110 22:56:56.549758 Loading: *################################################## 36.1 MiB
1111 22:56:56.550162 14.4 MiB/s
1112 22:56:56.550390 done
1113 22:56:56.554139 Bytes transferred = 37878336 (241fa40 hex)
1114 22:56:56.554654 Sending with 10 millisecond of delay
1116 22:57:01.243355 => tftpboot 0x08000000 931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot
1117 22:57:01.254311 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 22:57:01.255250 tftpboot 0x08000000 931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot
1119 22:57:01.255752 Speed: 1000, full duplex
1120 22:57:01.256261 Using ethernet@ff3f0000 device
1121 22:57:01.257068 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 22:57:01.267711 Filename '931126/tftp-deploy-e98soyl7/ramdisk/ramdisk.cpio.gz.uboot'.
1123 22:57:01.268283 Load address: 0x8000000
1124 22:57:03.538890 Loading: *#################### UDP wrong checksum 000000ff 0000ebf6
1125 22:57:03.578643 UDP wrong checksum 000000ff 000086e9
1126 22:57:04.655526 UDP wrong checksum 00000005 00003d78
1127 22:57:05.424048 UDP wrong checksum 000000ff 0000de84
1128 22:57:05.461020 UDP wrong checksum 000000ff 00006e77
1129 22:57:08.620663 T ############################# UDP wrong checksum 00000005 00001fbb
1130 22:57:13.620785 T UDP wrong checksum 00000005 00001fbb
1131 22:57:23.623859 T T UDP wrong checksum 00000005 00001fbb
1132 22:57:43.628125 T T T T UDP wrong checksum 00000005 00001fbb
1133 22:57:58.632030 T T
1134 22:57:58.632755 Retry count exceeded; starting again
1136 22:57:58.634956 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1139 22:57:58.637085 end: 2.4 uboot-commands (duration 00:01:52) [common]
1141 22:57:58.638662 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1143 22:57:58.639883 end: 2 uboot-action (duration 00:01:52) [common]
1145 22:57:58.641677 Cleaning after the job
1146 22:57:58.642346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/ramdisk
1147 22:57:58.643806 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/kernel
1148 22:57:58.677413 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/dtb
1149 22:57:58.678667 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931126/tftp-deploy-e98soyl7/modules
1150 22:57:58.702607 start: 4.1 power-off (timeout 00:00:30) [common]
1151 22:57:58.703356 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1152 22:57:58.736600 >> OK - accepted request
1153 22:57:58.738974 Returned 0 in 0 seconds
1154 22:57:58.839744 end: 4.1 power-off (duration 00:00:00) [common]
1156 22:57:58.840797 start: 4.2 read-feedback (timeout 00:10:00) [common]
1157 22:57:58.841462 Listened to connection for namespace 'common' for up to 1s
1158 22:57:59.842378 Finalising connection for namespace 'common'
1159 22:57:59.842886 Disconnecting from shell: Finalise
1160 22:57:59.843164 =>
1161 22:57:59.943830 end: 4.2 read-feedback (duration 00:00:01) [common]
1162 22:57:59.944325 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/931126
1163 22:58:00.246101 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/931126
1164 22:58:00.246714 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.