Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:01:33.200510 lava-dispatcher, installed at version: 2024.01
2 23:01:33.201312 start: 0 validate
3 23:01:33.201775 Start time: 2024-11-03 23:01:33.201745+00:00 (UTC)
4 23:01:33.202370 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:01:33.202911 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:01:33.244951 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:01:33.245501 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 23:01:33.276982 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:01:33.277626 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 23:01:33.307714 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:01:33.308225 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
12 23:01:33.350151 validate duration: 0.15
14 23:01:33.351076 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:01:33.351399 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:01:33.351694 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:01:33.352321 Not decompressing ramdisk as can be used compressed.
18 23:01:33.352775 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:01:33.353042 saving as /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/ramdisk/rootfs.cpio.gz
20 23:01:33.353311 total size: 47897469 (45 MB)
21 23:01:33.390305 progress 0 % (0 MB)
22 23:01:33.425317 progress 5 % (2 MB)
23 23:01:33.458746 progress 10 % (4 MB)
24 23:01:33.489150 progress 15 % (6 MB)
25 23:01:33.519793 progress 20 % (9 MB)
26 23:01:33.550326 progress 25 % (11 MB)
27 23:01:33.580569 progress 30 % (13 MB)
28 23:01:33.610937 progress 35 % (16 MB)
29 23:01:33.641232 progress 40 % (18 MB)
30 23:01:33.671594 progress 45 % (20 MB)
31 23:01:33.702388 progress 50 % (22 MB)
32 23:01:33.732458 progress 55 % (25 MB)
33 23:01:33.763081 progress 60 % (27 MB)
34 23:01:33.793543 progress 65 % (29 MB)
35 23:01:33.823752 progress 70 % (32 MB)
36 23:01:33.854236 progress 75 % (34 MB)
37 23:01:33.884796 progress 80 % (36 MB)
38 23:01:33.915412 progress 85 % (38 MB)
39 23:01:33.945528 progress 90 % (41 MB)
40 23:01:33.975486 progress 95 % (43 MB)
41 23:01:34.005440 progress 100 % (45 MB)
42 23:01:34.006213 45 MB downloaded in 0.65 s (69.96 MB/s)
43 23:01:34.006790 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:01:34.007691 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:01:34.008012 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:01:34.008292 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:01:34.008869 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/clang-15/kernel/Image
49 23:01:34.009129 saving as /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/kernel/Image
50 23:01:34.009338 total size: 37878272 (36 MB)
51 23:01:34.009551 No compression specified
52 23:01:34.052236 progress 0 % (0 MB)
53 23:01:34.076616 progress 5 % (1 MB)
54 23:01:34.100385 progress 10 % (3 MB)
55 23:01:34.124212 progress 15 % (5 MB)
56 23:01:34.148122 progress 20 % (7 MB)
57 23:01:34.171610 progress 25 % (9 MB)
58 23:01:34.195651 progress 30 % (10 MB)
59 23:01:34.218983 progress 35 % (12 MB)
60 23:01:34.242670 progress 40 % (14 MB)
61 23:01:34.266351 progress 45 % (16 MB)
62 23:01:34.289985 progress 50 % (18 MB)
63 23:01:34.313726 progress 55 % (19 MB)
64 23:01:34.337384 progress 60 % (21 MB)
65 23:01:34.361041 progress 65 % (23 MB)
66 23:01:34.384792 progress 70 % (25 MB)
67 23:01:34.408386 progress 75 % (27 MB)
68 23:01:34.432002 progress 80 % (28 MB)
69 23:01:34.455585 progress 85 % (30 MB)
70 23:01:34.479218 progress 90 % (32 MB)
71 23:01:34.503087 progress 95 % (34 MB)
72 23:01:34.525890 progress 100 % (36 MB)
73 23:01:34.526676 36 MB downloaded in 0.52 s (69.83 MB/s)
74 23:01:34.527166 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:01:34.528001 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:01:34.528286 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:01:34.528552 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:01:34.529035 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 23:01:34.529307 saving as /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 23:01:34.529514 total size: 53209 (0 MB)
82 23:01:34.529721 No compression specified
83 23:01:34.567548 progress 61 % (0 MB)
84 23:01:34.568445 progress 100 % (0 MB)
85 23:01:34.568977 0 MB downloaded in 0.04 s (1.29 MB/s)
86 23:01:34.569462 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:01:34.570266 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:01:34.570526 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:01:34.570789 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:01:34.571261 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/clang-15/modules.tar.xz
92 23:01:34.571502 saving as /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/modules/modules.tar
93 23:01:34.571705 total size: 11773700 (11 MB)
94 23:01:34.571914 Using unxz to decompress xz
95 23:01:34.609710 progress 0 % (0 MB)
96 23:01:34.676928 progress 5 % (0 MB)
97 23:01:34.752187 progress 10 % (1 MB)
98 23:01:34.849488 progress 15 % (1 MB)
99 23:01:34.947076 progress 20 % (2 MB)
100 23:01:35.026816 progress 25 % (2 MB)
101 23:01:35.104009 progress 30 % (3 MB)
102 23:01:35.185848 progress 35 % (3 MB)
103 23:01:35.265876 progress 40 % (4 MB)
104 23:01:35.342164 progress 45 % (5 MB)
105 23:01:35.427745 progress 50 % (5 MB)
106 23:01:35.510630 progress 55 % (6 MB)
107 23:01:35.596611 progress 60 % (6 MB)
108 23:01:35.678666 progress 65 % (7 MB)
109 23:01:35.761663 progress 70 % (7 MB)
110 23:01:35.845792 progress 75 % (8 MB)
111 23:01:35.930690 progress 80 % (9 MB)
112 23:01:36.012458 progress 85 % (9 MB)
113 23:01:36.097627 progress 90 % (10 MB)
114 23:01:36.178191 progress 95 % (10 MB)
115 23:01:36.256472 progress 100 % (11 MB)
116 23:01:36.267797 11 MB downloaded in 1.70 s (6.62 MB/s)
117 23:01:36.268831 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:01:36.270438 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:01:36.270961 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:01:36.271476 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:01:36.271964 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:01:36.272519 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:01:36.273524 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj
125 23:01:36.274338 makedir: /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin
126 23:01:36.274965 makedir: /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/tests
127 23:01:36.275579 makedir: /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/results
128 23:01:36.276265 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-add-keys
129 23:01:36.277227 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-add-sources
130 23:01:36.278151 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-background-process-start
131 23:01:36.279089 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-background-process-stop
132 23:01:36.280102 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-common-functions
133 23:01:36.281066 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-echo-ipv4
134 23:01:36.282011 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-install-packages
135 23:01:36.282910 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-installed-packages
136 23:01:36.283795 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-os-build
137 23:01:36.284734 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-probe-channel
138 23:01:36.285639 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-probe-ip
139 23:01:36.286535 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-target-ip
140 23:01:36.287421 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-target-mac
141 23:01:36.288342 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-target-storage
142 23:01:36.289270 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-case
143 23:01:36.290176 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-event
144 23:01:36.291075 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-feedback
145 23:01:36.291971 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-raise
146 23:01:36.292914 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-reference
147 23:01:36.293825 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-runner
148 23:01:36.294728 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-set
149 23:01:36.295615 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-test-shell
150 23:01:36.296559 Updating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-install-packages (oe)
151 23:01:36.297566 Updating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/bin/lava-installed-packages (oe)
152 23:01:36.298420 Creating /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/environment
153 23:01:36.299139 LAVA metadata
154 23:01:36.299631 - LAVA_JOB_ID=931057
155 23:01:36.300092 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:01:36.300767 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:01:36.302576 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:01:36.303220 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:01:36.303708 skipped lava-vland-overlay
160 23:01:36.304251 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:01:36.304795 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:01:36.305220 skipped lava-multinode-overlay
163 23:01:36.305700 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:01:36.306194 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:01:36.306673 Loading test definitions
166 23:01:36.307217 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:01:36.307651 Using /lava-931057 at stage 0
168 23:01:36.309152 uuid=931057_1.5.2.4.1 testdef=None
169 23:01:36.309493 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:01:36.309770 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:01:36.311560 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:01:36.312446 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:01:36.314705 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:01:36.315569 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:01:36.317767 runner path: /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/0/tests/0_igt-gpu-panfrost test_uuid 931057_1.5.2.4.1
178 23:01:36.318402 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:01:36.319241 Creating lava-test-runner.conf files
181 23:01:36.319452 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/931057/lava-overlay-qm0jjuuj/lava-931057/0 for stage 0
182 23:01:36.319818 - 0_igt-gpu-panfrost
183 23:01:36.320234 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:01:36.320532 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:01:36.344952 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:01:36.345385 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:01:36.345658 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:01:36.345931 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:01:36.346221 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:01:44.148610 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:08) [common]
191 23:01:44.149090 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
192 23:01:44.149341 extracting modules file /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk
193 23:01:45.581906 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:01:45.582382 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 23:01:45.582664 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931057/compress-overlay-jvy35cge/overlay-1.5.2.5.tar.gz to ramdisk
196 23:01:45.582879 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931057/compress-overlay-jvy35cge/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk
197 23:01:45.613161 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:01:45.613583 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 23:01:45.613854 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 23:01:45.614082 Converting downloaded kernel to a uImage
201 23:01:45.614385 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/kernel/Image /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/kernel/uImage
202 23:01:46.031323 output: Image Name:
203 23:01:46.031746 output: Created: Sun Nov 3 23:01:45 2024
204 23:01:46.031954 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:01:46.032194 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
206 23:01:46.032399 output: Load Address: 01080000
207 23:01:46.032599 output: Entry Point: 01080000
208 23:01:46.032799 output:
209 23:01:46.033130 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:01:46.033515 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:01:46.033801 start: 1.5.7 configure-preseed-file (timeout 00:09:47) [common]
212 23:01:46.034056 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:01:46.034311 start: 1.5.8 compress-ramdisk (timeout 00:09:47) [common]
214 23:01:46.034572 Building ramdisk /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk
215 23:01:53.363015 >> 509022 blocks
216 23:02:13.826264 Adding RAMdisk u-boot header.
217 23:02:13.826730 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk.cpio.gz.uboot
218 23:02:14.510273 output: Image Name:
219 23:02:14.510693 output: Created: Sun Nov 3 23:02:13 2024
220 23:02:14.510901 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:02:14.511105 output: Data Size: 66425301 Bytes = 64868.46 KiB = 63.35 MiB
222 23:02:14.511303 output: Load Address: 00000000
223 23:02:14.511501 output: Entry Point: 00000000
224 23:02:14.511696 output:
225 23:02:14.512684 rename /var/lib/lava/dispatcher/tmp/931057/extract-overlay-ramdisk-tsynijd3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot
226 23:02:14.513555 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 23:02:14.514154 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 23:02:14.514737 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 23:02:14.515241 No LXC device requested
230 23:02:14.515799 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:02:14.516425 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 23:02:14.516974 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:02:14.517439 Checking files for TFTP limit of 4294967296 bytes.
234 23:02:14.520376 end: 1 tftp-deploy (duration 00:00:41) [common]
235 23:02:14.521034 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:02:14.521607 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:02:14.522156 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:02:14.522706 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:02:14.523282 Using kernel file from prepare-kernel: 931057/tftp-deploy-ijlvr1hx/kernel/uImage
240 23:02:14.523944 substitutions:
241 23:02:14.524428 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:02:14.524871 - {DTB_ADDR}: 0x01070000
243 23:02:14.525310 - {DTB}: 931057/tftp-deploy-ijlvr1hx/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 23:02:14.525749 - {INITRD}: 931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot
245 23:02:14.526184 - {KERNEL_ADDR}: 0x01080000
246 23:02:14.526616 - {KERNEL}: 931057/tftp-deploy-ijlvr1hx/kernel/uImage
247 23:02:14.527054 - {LAVA_MAC}: None
248 23:02:14.527527 - {PRESEED_CONFIG}: None
249 23:02:14.527964 - {PRESEED_LOCAL}: None
250 23:02:14.528427 - {RAMDISK_ADDR}: 0x08000000
251 23:02:14.528855 - {RAMDISK}: 931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot
252 23:02:14.529290 - {ROOT_PART}: None
253 23:02:14.529719 - {ROOT}: None
254 23:02:14.530149 - {SERVER_IP}: 192.168.6.2
255 23:02:14.530586 - {TEE_ADDR}: 0x83000000
256 23:02:14.531013 - {TEE}: None
257 23:02:14.531440 Parsed boot commands:
258 23:02:14.531855 - setenv autoload no
259 23:02:14.532311 - setenv initrd_high 0xffffffff
260 23:02:14.532741 - setenv fdt_high 0xffffffff
261 23:02:14.533165 - dhcp
262 23:02:14.533592 - setenv serverip 192.168.6.2
263 23:02:14.534014 - tftpboot 0x01080000 931057/tftp-deploy-ijlvr1hx/kernel/uImage
264 23:02:14.534443 - tftpboot 0x08000000 931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot
265 23:02:14.534873 - tftpboot 0x01070000 931057/tftp-deploy-ijlvr1hx/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 23:02:14.535298 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:02:14.535730 - bootm 0x01080000 0x08000000 0x01070000
268 23:02:14.536313 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:02:14.537942 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:02:14.538432 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 23:02:14.553503 Setting prompt string to ['lava-test: # ']
273 23:02:14.555144 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:02:14.555795 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:02:14.556570 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:02:14.557279 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:02:14.558530 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 23:02:14.600875 >> OK - accepted request
279 23:02:14.603346 Returned 0 in 0 seconds
280 23:02:14.704657 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:02:14.706486 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:02:14.707120 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:02:14.707676 Setting prompt string to ['Hit any key to stop autoboot']
285 23:02:14.708242 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:02:14.709987 Trying 192.168.56.21...
287 23:02:14.710553 Connected to conserv1.
288 23:02:14.711012 Escape character is '^]'.
289 23:02:14.711468
290 23:02:14.711934 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 23:02:14.712438
292 23:02:22.010588 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 23:02:22.011278 bl2_stage_init 0x01
294 23:02:22.011744 bl2_stage_init 0x81
295 23:02:22.016072 hw id: 0x0000 - pwm id 0x01
296 23:02:22.016580 bl2_stage_init 0xc1
297 23:02:22.020588 bl2_stage_init 0x02
298 23:02:22.021086
299 23:02:22.021533 L0:00000000
300 23:02:22.021976 L1:00000703
301 23:02:22.022405 L2:00008067
302 23:02:22.025441 L3:15000000
303 23:02:22.025918 S1:00000000
304 23:02:22.026354 B2:20282000
305 23:02:22.026784 B1:a0f83180
306 23:02:22.027213
307 23:02:22.030978 TE: 70081
308 23:02:22.031454
309 23:02:22.036576 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 23:02:22.037055
311 23:02:22.037488 Board ID = 1
312 23:02:22.037915 Set cpu clk to 24M
313 23:02:22.042179 Set clk81 to 24M
314 23:02:22.042654 Use GP1_pll as DSU clk.
315 23:02:22.043088 DSU clk: 1200 Mhz
316 23:02:22.047837 CPU clk: 1200 MHz
317 23:02:22.048345 Set clk81 to 166.6M
318 23:02:22.053423 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 23:02:22.053891 board id: 1
320 23:02:22.058918 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:02:22.072943 fw parse done
322 23:02:22.078914 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:02:22.122091 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:02:22.133116 PIEI prepare done
325 23:02:22.133582 fastboot data load
326 23:02:22.134017 fastboot data verify
327 23:02:22.138691 verify result: 266
328 23:02:22.144313 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 23:02:22.144772 LPDDR4 probe
330 23:02:22.145198 ddr clk to 1584MHz
331 23:02:22.152290 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:02:22.189993
333 23:02:22.190482 dmc_version 0001
334 23:02:22.197083 Check phy result
335 23:02:22.202992 INFO : End of CA training
336 23:02:22.203461 INFO : End of initialization
337 23:02:22.208606 INFO : Training has run successfully!
338 23:02:22.209064 Check phy result
339 23:02:22.214211 INFO : End of initialization
340 23:02:22.214669 INFO : End of read enable training
341 23:02:22.219808 INFO : End of fine write leveling
342 23:02:22.225445 INFO : End of Write leveling coarse delay
343 23:02:22.225905 INFO : Training has run successfully!
344 23:02:22.226337 Check phy result
345 23:02:22.231009 INFO : End of initialization
346 23:02:22.231467 INFO : End of read dq deskew training
347 23:02:22.236600 INFO : End of MPR read delay center optimization
348 23:02:22.242214 INFO : End of write delay center optimization
349 23:02:22.247820 INFO : End of read delay center optimization
350 23:02:22.248321 INFO : End of max read latency training
351 23:02:22.253442 INFO : Training has run successfully!
352 23:02:22.253899 1D training succeed
353 23:02:22.262685 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:02:22.310897 Check phy result
355 23:02:22.311427 INFO : End of initialization
356 23:02:22.338268 INFO : End of 2D read delay Voltage center optimization
357 23:02:22.362426 INFO : End of 2D read delay Voltage center optimization
358 23:02:22.419159 INFO : End of 2D write delay Voltage center optimization
359 23:02:22.473186 INFO : End of 2D write delay Voltage center optimization
360 23:02:22.478730 INFO : Training has run successfully!
361 23:02:22.479237
362 23:02:22.479698 channel==0
363 23:02:22.484590 RxClkDly_Margin_A0==78 ps 8
364 23:02:22.485084 TxDqDly_Margin_A0==98 ps 10
365 23:02:22.490059 RxClkDly_Margin_A1==88 ps 9
366 23:02:22.490623 TxDqDly_Margin_A1==98 ps 10
367 23:02:22.491081 TrainedVREFDQ_A0==74
368 23:02:22.495498 TrainedVREFDQ_A1==74
369 23:02:22.496012 VrefDac_Margin_A0==24
370 23:02:22.496458 DeviceVref_Margin_A0==40
371 23:02:22.501223 VrefDac_Margin_A1==23
372 23:02:22.501676 DeviceVref_Margin_A1==40
373 23:02:22.501908
374 23:02:22.502114
375 23:02:22.506698 channel==1
376 23:02:22.507018 RxClkDly_Margin_A0==88 ps 9
377 23:02:22.507226 TxDqDly_Margin_A0==98 ps 10
378 23:02:22.512378 RxClkDly_Margin_A1==78 ps 8
379 23:02:22.512787 TxDqDly_Margin_A1==78 ps 8
380 23:02:22.517932 TrainedVREFDQ_A0==75
381 23:02:22.518329 TrainedVREFDQ_A1==75
382 23:02:22.518536 VrefDac_Margin_A0==23
383 23:02:22.523791 DeviceVref_Margin_A0==39
384 23:02:22.524317 VrefDac_Margin_A1==22
385 23:02:22.529238 DeviceVref_Margin_A1==39
386 23:02:22.529836
387 23:02:22.530069 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:02:22.530287
389 23:02:22.562724 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 23:02:22.563190 2D training succeed
391 23:02:22.568273 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:02:22.573867 auto size-- 65535DDR cs0 size: 2048MB
393 23:02:22.574175 DDR cs1 size: 2048MB
394 23:02:22.579564 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:02:22.579927 cs0 DataBus test pass
396 23:02:22.585144 cs1 DataBus test pass
397 23:02:22.585557 cs0 AddrBus test pass
398 23:02:22.585779 cs1 AddrBus test pass
399 23:02:22.585987
400 23:02:22.590695 100bdlr_step_size ps== 471
401 23:02:22.591045 result report
402 23:02:22.596358 boot times 0Enable ddr reg access
403 23:02:22.601532 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:02:22.615496 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 23:02:23.274984 bl2z: ptr: 05129330, size: 00001e40
406 23:02:23.283873 0.0;M3 CHK:0;cm4_sp_mode 0
407 23:02:23.284568 MVN_1=0x00000000
408 23:02:23.285047 MVN_2=0x00000000
409 23:02:23.295388 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 23:02:23.296097 OPS=0x04
411 23:02:23.296517 ring efuse init
412 23:02:23.298072 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 23:02:23.303879 [0.017354 Inits done]
414 23:02:23.304659 secure task start!
415 23:02:23.305165 high task start!
416 23:02:23.305666 low task start!
417 23:02:23.308134 run into bl31
418 23:02:23.316646 NOTICE: BL31: v1.3(release):4fc40b1
419 23:02:23.324427 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 23:02:23.324847 NOTICE: BL31: G12A normal boot!
421 23:02:23.340115 NOTICE: BL31: BL33 decompress pass
422 23:02:23.345719 ERROR: Error initializing runtime service opteed_fast
423 23:02:26.061017 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 23:02:26.061666 bl2_stage_init 0x01
425 23:02:26.062105 bl2_stage_init 0x81
426 23:02:26.066567 hw id: 0x0000 - pwm id 0x01
427 23:02:26.067075 bl2_stage_init 0xc1
428 23:02:26.072194 bl2_stage_init 0x02
429 23:02:26.072710
430 23:02:26.073110 L0:00000000
431 23:02:26.073499 L1:00000703
432 23:02:26.073884 L2:00008067
433 23:02:26.074266 L3:15000000
434 23:02:26.077766 S1:00000000
435 23:02:26.078192 B2:20282000
436 23:02:26.078586 B1:a0f83180
437 23:02:26.078970
438 23:02:26.079357 TE: 69872
439 23:02:26.079745
440 23:02:26.083369 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 23:02:26.083834
442 23:02:26.088965 Board ID = 1
443 23:02:26.089393 Set cpu clk to 24M
444 23:02:26.089779 Set clk81 to 24M
445 23:02:26.094567 Use GP1_pll as DSU clk.
446 23:02:26.094992 DSU clk: 1200 Mhz
447 23:02:26.095377 CPU clk: 1200 MHz
448 23:02:26.100161 Set clk81 to 166.6M
449 23:02:26.105767 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 23:02:26.106195 board id: 1
451 23:02:26.112996 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 23:02:26.123631 fw parse done
453 23:02:26.129582 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 23:02:26.172250 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 23:02:26.183247 PIEI prepare done
456 23:02:26.183680 fastboot data load
457 23:02:26.184108 fastboot data verify
458 23:02:26.188800 verify result: 266
459 23:02:26.194405 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 23:02:26.194828 LPDDR4 probe
461 23:02:26.195216 ddr clk to 1584MHz
462 23:02:26.202405 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 23:02:26.239666
464 23:02:26.240138 dmc_version 0001
465 23:02:26.246517 Check phy result
466 23:02:26.252229 INFO : End of CA training
467 23:02:26.252646 INFO : End of initialization
468 23:02:26.257808 INFO : Training has run successfully!
469 23:02:26.258235 Check phy result
470 23:02:26.263421 INFO : End of initialization
471 23:02:26.263907 INFO : End of read enable training
472 23:02:26.269070 INFO : End of fine write leveling
473 23:02:26.274622 INFO : End of Write leveling coarse delay
474 23:02:26.275069 INFO : Training has run successfully!
475 23:02:26.275479 Check phy result
476 23:02:26.280214 INFO : End of initialization
477 23:02:26.280643 INFO : End of read dq deskew training
478 23:02:26.285844 INFO : End of MPR read delay center optimization
479 23:02:26.291405 INFO : End of write delay center optimization
480 23:02:26.297013 INFO : End of read delay center optimization
481 23:02:26.297499 INFO : End of max read latency training
482 23:02:26.302626 INFO : Training has run successfully!
483 23:02:26.303066 1D training succeed
484 23:02:26.311775 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 23:02:26.359504 Check phy result
486 23:02:26.359966 INFO : End of initialization
487 23:02:26.381713 INFO : End of 2D read delay Voltage center optimization
488 23:02:26.400948 INFO : End of 2D read delay Voltage center optimization
489 23:02:26.452802 INFO : End of 2D write delay Voltage center optimization
490 23:02:26.501998 INFO : End of 2D write delay Voltage center optimization
491 23:02:26.507563 INFO : Training has run successfully!
492 23:02:26.508069
493 23:02:26.508486 channel==0
494 23:02:26.513092 RxClkDly_Margin_A0==78 ps 8
495 23:02:26.513549 TxDqDly_Margin_A0==98 ps 10
496 23:02:26.518679 RxClkDly_Margin_A1==88 ps 9
497 23:02:26.519105 TxDqDly_Margin_A1==98 ps 10
498 23:02:26.519508 TrainedVREFDQ_A0==74
499 23:02:26.524303 TrainedVREFDQ_A1==74
500 23:02:26.524742 VrefDac_Margin_A0==23
501 23:02:26.525140 DeviceVref_Margin_A0==40
502 23:02:26.529880 VrefDac_Margin_A1==23
503 23:02:26.530312 DeviceVref_Margin_A1==40
504 23:02:26.530713
505 23:02:26.531111
506 23:02:26.535465 channel==1
507 23:02:26.535911 RxClkDly_Margin_A0==78 ps 8
508 23:02:26.536346 TxDqDly_Margin_A0==98 ps 10
509 23:02:26.541059 RxClkDly_Margin_A1==78 ps 8
510 23:02:26.541485 TxDqDly_Margin_A1==88 ps 9
511 23:02:26.546661 TrainedVREFDQ_A0==78
512 23:02:26.547088 TrainedVREFDQ_A1==75
513 23:02:26.547493 VrefDac_Margin_A0==22
514 23:02:26.552284 DeviceVref_Margin_A0==36
515 23:02:26.552710 VrefDac_Margin_A1==22
516 23:02:26.557905 DeviceVref_Margin_A1==39
517 23:02:26.558352
518 23:02:26.558760 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 23:02:26.559158
520 23:02:26.591495 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 23:02:26.592055 2D training succeed
522 23:02:26.597121 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 23:02:26.602687 auto size-- 65535DDR cs0 size: 2048MB
524 23:02:26.603111 DDR cs1 size: 2048MB
525 23:02:26.608272 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 23:02:26.608692 cs0 DataBus test pass
527 23:02:26.613871 cs1 DataBus test pass
528 23:02:26.614291 cs0 AddrBus test pass
529 23:02:26.614692 cs1 AddrBus test pass
530 23:02:26.615089
531 23:02:26.619468 100bdlr_step_size ps== 478
532 23:02:26.619912 result report
533 23:02:26.625103 boot times 0Enable ddr reg access
534 23:02:26.630365 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 23:02:26.644212 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 23:02:27.299520 bl2z: ptr: 05129330, size: 00001e40
537 23:02:27.305326 0.0;M3 CHK:0;cm4_sp_mode 0
538 23:02:27.305784 MVN_1=0x00000000
539 23:02:27.306183 MVN_2=0x00000000
540 23:02:27.316918 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 23:02:27.317373 OPS=0x04
542 23:02:27.317783 ring efuse init
543 23:02:27.320509 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 23:02:27.326121 [0.017319 Inits done]
545 23:02:27.326558 secure task start!
546 23:02:27.326957 high task start!
547 23:02:27.327350 low task start!
548 23:02:27.329567 run into bl31
549 23:02:27.338463 NOTICE: BL31: v1.3(release):4fc40b1
550 23:02:27.345862 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 23:02:27.346302 NOTICE: BL31: G12A normal boot!
552 23:02:27.361368 NOTICE: BL31: BL33 decompress pass
553 23:02:27.367005 ERROR: Error initializing runtime service opteed_fast
554 23:02:28.759803 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 23:02:28.760394 bl2_stage_init 0x01
556 23:02:28.760709 bl2_stage_init 0x81
557 23:02:28.765310 hw id: 0x0000 - pwm id 0x01
558 23:02:28.765701 bl2_stage_init 0xc1
559 23:02:28.770704 bl2_stage_init 0x02
560 23:02:28.771081
561 23:02:28.771681 L0:00000000
562 23:02:28.772417 L1:00000703
563 23:02:28.772724 L2:00008067
564 23:02:28.773028 L3:15000000
565 23:02:28.776239 S1:00000000
566 23:02:28.776607 B2:20282000
567 23:02:28.776921 B1:a0f83180
568 23:02:28.777224
569 23:02:28.777538 TE: 69521
570 23:02:28.777866
571 23:02:28.782006 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 23:02:28.782795
573 23:02:28.787533 Board ID = 1
574 23:02:28.787904 Set cpu clk to 24M
575 23:02:28.788245 Set clk81 to 24M
576 23:02:28.793066 Use GP1_pll as DSU clk.
577 23:02:28.793390 DSU clk: 1200 Mhz
578 23:02:28.793707 CPU clk: 1200 MHz
579 23:02:28.798640 Set clk81 to 166.6M
580 23:02:28.804274 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 23:02:28.804605 board id: 1
582 23:02:28.811775 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 23:02:28.822685 fw parse done
584 23:02:28.828628 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 23:02:28.871666 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 23:02:28.882724 PIEI prepare done
587 23:02:28.883114 fastboot data load
588 23:02:28.883405 fastboot data verify
589 23:02:28.888348 verify result: 266
590 23:02:28.893903 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 23:02:28.894189 LPDDR4 probe
592 23:02:28.894427 ddr clk to 1584MHz
593 23:02:28.901893 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 23:02:28.939659
595 23:02:28.940018 dmc_version 0001
596 23:02:28.946667 Check phy result
597 23:02:28.952679 INFO : End of CA training
598 23:02:28.953063 INFO : End of initialization
599 23:02:28.958260 INFO : Training has run successfully!
600 23:02:28.958553 Check phy result
601 23:02:28.963861 INFO : End of initialization
602 23:02:28.964253 INFO : End of read enable training
603 23:02:28.967149 INFO : End of fine write leveling
604 23:02:28.972687 INFO : End of Write leveling coarse delay
605 23:02:28.978305 INFO : Training has run successfully!
606 23:02:28.978581 Check phy result
607 23:02:28.978818 INFO : End of initialization
608 23:02:28.983923 INFO : End of read dq deskew training
609 23:02:28.989547 INFO : End of MPR read delay center optimization
610 23:02:28.989843 INFO : End of write delay center optimization
611 23:02:28.995105 INFO : End of read delay center optimization
612 23:02:29.000703 INFO : End of max read latency training
613 23:02:29.001023 INFO : Training has run successfully!
614 23:02:29.006293 1D training succeed
615 23:02:29.012258 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 23:02:29.060874 Check phy result
617 23:02:29.061488 INFO : End of initialization
618 23:02:29.087946 INFO : End of 2D read delay Voltage center optimization
619 23:02:29.112123 INFO : End of 2D read delay Voltage center optimization
620 23:02:29.169052 INFO : End of 2D write delay Voltage center optimization
621 23:02:29.222953 INFO : End of 2D write delay Voltage center optimization
622 23:02:29.228545 INFO : Training has run successfully!
623 23:02:29.228836
624 23:02:29.229081 channel==0
625 23:02:29.234099 RxClkDly_Margin_A0==78 ps 8
626 23:02:29.234390 TxDqDly_Margin_A0==98 ps 10
627 23:02:29.239685 RxClkDly_Margin_A1==88 ps 9
628 23:02:29.240097 TxDqDly_Margin_A1==98 ps 10
629 23:02:29.240596 TrainedVREFDQ_A0==74
630 23:02:29.245275 TrainedVREFDQ_A1==74
631 23:02:29.245655 VrefDac_Margin_A0==24
632 23:02:29.246113 DeviceVref_Margin_A0==40
633 23:02:29.250809 VrefDac_Margin_A1==22
634 23:02:29.251093 DeviceVref_Margin_A1==40
635 23:02:29.251329
636 23:02:29.251557
637 23:02:29.251785 channel==1
638 23:02:29.256495 RxClkDly_Margin_A0==78 ps 8
639 23:02:29.256790 TxDqDly_Margin_A0==98 ps 10
640 23:02:29.262130 RxClkDly_Margin_A1==78 ps 8
641 23:02:29.262410 TxDqDly_Margin_A1==88 ps 9
642 23:02:29.267625 TrainedVREFDQ_A0==77
643 23:02:29.268020 TrainedVREFDQ_A1==77
644 23:02:29.268505 VrefDac_Margin_A0==22
645 23:02:29.273166 DeviceVref_Margin_A0==37
646 23:02:29.273544 VrefDac_Margin_A1==22
647 23:02:29.278823 DeviceVref_Margin_A1==37
648 23:02:29.279198
649 23:02:29.279701 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 23:02:29.280430
651 23:02:29.312442 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
652 23:02:29.312797 2D training succeed
653 23:02:29.318001 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 23:02:29.323697 auto size-- 65535DDR cs0 size: 2048MB
655 23:02:29.324106 DDR cs1 size: 2048MB
656 23:02:29.329183 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 23:02:29.329466 cs0 DataBus test pass
658 23:02:29.334821 cs1 DataBus test pass
659 23:02:29.335244 cs0 AddrBus test pass
660 23:02:29.335601 cs1 AddrBus test pass
661 23:02:29.335969
662 23:02:29.340438 100bdlr_step_size ps== 485
663 23:02:29.340714 result report
664 23:02:29.346010 boot times 0Enable ddr reg access
665 23:02:29.351175 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 23:02:29.365114 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 23:02:30.024634 bl2z: ptr: 05129330, size: 00001e40
668 23:02:30.032273 0.0;M3 CHK:0;cm4_sp_mode 0
669 23:02:30.032569 MVN_1=0x00000000
670 23:02:30.032809 MVN_2=0x00000000
671 23:02:30.043708 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 23:02:30.044020 OPS=0x04
673 23:02:30.044259 ring efuse init
674 23:02:30.046632 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 23:02:30.052349 [0.017354 Inits done]
676 23:02:30.052608 secure task start!
677 23:02:30.052830 high task start!
678 23:02:30.053045 low task start!
679 23:02:30.056607 run into bl31
680 23:02:30.065251 NOTICE: BL31: v1.3(release):4fc40b1
681 23:02:30.073038 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 23:02:30.073313 NOTICE: BL31: G12A normal boot!
683 23:02:30.088716 NOTICE: BL31: BL33 decompress pass
684 23:02:30.094374 ERROR: Error initializing runtime service opteed_fast
685 23:02:30.889750
686 23:02:30.890389
687 23:02:30.895087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 23:02:30.895576
689 23:02:30.898607 Model: Libre Computer AML-S905D3-CC Solitude
690 23:02:31.045635 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 23:02:31.061014 DRAM: 2 GiB (effective 3.8 GiB)
692 23:02:31.162018 Core: 406 devices, 33 uclasses, devicetree: separate
693 23:02:31.167863 WDT: Not starting watchdog@f0d0
694 23:02:31.192909 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 23:02:31.205195 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 23:02:31.210110 ** Bad device specification mmc 0 **
697 23:02:31.220180 Card did not respond to voltage select! : -110
698 23:02:31.227819 ** Bad device specification mmc 0 **
699 23:02:31.228365 Couldn't find partition mmc 0
700 23:02:31.236201 Card did not respond to voltage select! : -110
701 23:02:31.241679 ** Bad device specification mmc 0 **
702 23:02:31.242146 Couldn't find partition mmc 0
703 23:02:31.246722 Error: could not access storage.
704 23:02:31.543241 Net: eth0: ethernet@ff3f0000
705 23:02:31.543891 starting USB...
706 23:02:31.788015 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 23:02:31.788431 Starting the controller
708 23:02:31.794909 USB XHCI 1.10
709 23:02:33.351165 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 23:02:33.359402 scanning usb for storage devices... 0 Storage Device(s) found
712 23:02:33.410937 Hit any key to stop autoboot: 1
713 23:02:33.411827 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 23:02:33.412481 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 23:02:33.412981 Setting prompt string to ['=>']
716 23:02:33.413486 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 23:02:33.425459 0
718 23:02:33.426349 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 23:02:33.527639 => setenv autoload no
721 23:02:33.528432 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 23:02:33.533720 setenv autoload no
724 23:02:33.635261 => setenv initrd_high 0xffffffff
725 23:02:33.636018 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 23:02:33.640229 setenv initrd_high 0xffffffff
728 23:02:33.741725 => setenv fdt_high 0xffffffff
729 23:02:33.742478 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 23:02:33.746721 setenv fdt_high 0xffffffff
732 23:02:33.848277 => dhcp
733 23:02:33.849011 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 23:02:33.853053 dhcp
735 23:02:34.408810 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 23:02:34.409441 Speed: 1000, full duplex
737 23:02:34.409885 BOOTP broadcast 1
738 23:02:34.656948 BOOTP broadcast 2
739 23:02:34.672981 DHCP client bound to address 192.168.6.21 (264 ms)
741 23:02:34.774673 => setenv serverip 192.168.6.2
742 23:02:34.775506 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 23:02:34.780299 setenv serverip 192.168.6.2
745 23:02:34.882009 => tftpboot 0x01080000 931057/tftp-deploy-ijlvr1hx/kernel/uImage
746 23:02:34.882803 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 23:02:34.889505 tftpboot 0x01080000 931057/tftp-deploy-ijlvr1hx/kernel/uImage
748 23:02:34.890075 Speed: 1000, full duplex
749 23:02:34.890527 Using ethernet@ff3f0000 device
750 23:02:34.895010 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 23:02:34.900479 Filename '931057/tftp-deploy-ijlvr1hx/kernel/uImage'.
752 23:02:34.904384 Load address: 0x1080000
753 23:02:35.593954 Loading: *############## UDP wrong checksum 000000ff 00002c14
754 23:02:35.609064 UDP wrong checksum 000000ff 0000b506
755 23:02:37.304735 #################################### 36.1 MiB
756 23:02:37.305361 15 MiB/s
757 23:02:37.305800 done
758 23:02:37.308915 Bytes transferred = 37878336 (241fa40 hex)
760 23:02:37.410548 => tftpboot 0x08000000 931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot
761 23:02:37.411325 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
762 23:02:37.418038 tftpboot 0x08000000 931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot
763 23:02:37.418543 Speed: 1000, full duplex
764 23:02:37.418982 Using ethernet@ff3f0000 device
765 23:02:37.423512 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
766 23:02:37.433395 Filename '931057/tftp-deploy-ijlvr1hx/ramdisk/ramdisk.cpio.gz.uboot'.
767 23:02:37.433882 Load address: 0x8000000
768 23:02:46.608623 Loading: *################################T ################# UDP wrong checksum 0000000f 00001757
769 23:02:51.608482 T UDP wrong checksum 0000000f 00001757
770 23:03:01.610464 T T UDP wrong checksum 0000000f 00001757
771 23:03:12.156416 T T UDP wrong checksum 000000ff 00009bd2
772 23:03:12.212754 UDP wrong checksum 000000ff 000037c5
773 23:03:21.614534 T T UDP wrong checksum 0000000f 00001757
774 23:03:36.618534 T T
775 23:03:36.618950 Retry count exceeded; starting again
777 23:03:36.620957 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
780 23:03:36.622696 end: 2.4 uboot-commands (duration 00:01:22) [common]
782 23:03:36.624029 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
784 23:03:36.625005 end: 2 uboot-action (duration 00:01:22) [common]
786 23:03:36.626446 Cleaning after the job
787 23:03:36.626984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/ramdisk
788 23:03:36.628171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/kernel
789 23:03:36.668231 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/dtb
790 23:03:36.669013 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931057/tftp-deploy-ijlvr1hx/modules
791 23:03:36.689340 start: 4.1 power-off (timeout 00:00:30) [common]
792 23:03:36.690004 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
793 23:03:36.722781 >> OK - accepted request
794 23:03:36.725065 Returned 0 in 0 seconds
795 23:03:36.825921 end: 4.1 power-off (duration 00:00:00) [common]
797 23:03:36.826936 start: 4.2 read-feedback (timeout 00:10:00) [common]
798 23:03:36.827633 Listened to connection for namespace 'common' for up to 1s
799 23:03:37.828173 Finalising connection for namespace 'common'
800 23:03:37.828688 Disconnecting from shell: Finalise
801 23:03:37.829009 =>
802 23:03:37.929679 end: 4.2 read-feedback (duration 00:00:01) [common]
803 23:03:37.930160 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/931057
804 23:03:38.554852 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/931057
805 23:03:38.555476 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.