Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:25:26.518431 lava-dispatcher, installed at version: 2024.01
2 23:25:26.519209 start: 0 validate
3 23:25:26.519675 Start time: 2024-11-03 23:25:26.519645+00:00 (UTC)
4 23:25:26.520236 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:25:26.520765 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:25:26.562240 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:25:26.562794 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:25:26.589312 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:25:26.589933 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 23:25:27.640342 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:25:27.640844 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-403-ga8cc7432728d0%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 23:25:27.680959 validate duration: 1.16
14 23:25:27.681847 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:25:27.682184 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:25:27.682495 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:25:27.683106 Not decompressing ramdisk as can be used compressed.
18 23:25:27.683554 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:25:27.683830 saving as /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/ramdisk/rootfs.cpio.gz
20 23:25:27.684139 total size: 8181887 (7 MB)
21 23:25:27.723958 progress 0 % (0 MB)
22 23:25:27.732335 progress 5 % (0 MB)
23 23:25:27.742921 progress 10 % (0 MB)
24 23:25:27.753203 progress 15 % (1 MB)
25 23:25:27.758694 progress 20 % (1 MB)
26 23:25:27.764711 progress 25 % (1 MB)
27 23:25:27.770139 progress 30 % (2 MB)
28 23:25:27.776016 progress 35 % (2 MB)
29 23:25:27.781489 progress 40 % (3 MB)
30 23:25:27.787173 progress 45 % (3 MB)
31 23:25:27.792632 progress 50 % (3 MB)
32 23:25:27.798332 progress 55 % (4 MB)
33 23:25:27.803639 progress 60 % (4 MB)
34 23:25:27.809376 progress 65 % (5 MB)
35 23:25:27.814675 progress 70 % (5 MB)
36 23:25:27.820399 progress 75 % (5 MB)
37 23:25:27.825706 progress 80 % (6 MB)
38 23:25:27.831466 progress 85 % (6 MB)
39 23:25:27.836860 progress 90 % (7 MB)
40 23:25:27.842586 progress 95 % (7 MB)
41 23:25:27.847707 progress 100 % (7 MB)
42 23:25:27.848453 7 MB downloaded in 0.16 s (47.49 MB/s)
43 23:25:27.849022 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:25:27.849920 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:25:27.850215 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:25:27.850484 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:25:27.850943 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/gcc-12/kernel/Image
49 23:25:27.851190 saving as /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/kernel/Image
50 23:25:27.851397 total size: 45713920 (43 MB)
51 23:25:27.851606 No compression specified
52 23:25:27.894663 progress 0 % (0 MB)
53 23:25:27.923399 progress 5 % (2 MB)
54 23:25:27.952106 progress 10 % (4 MB)
55 23:25:27.980798 progress 15 % (6 MB)
56 23:25:28.009137 progress 20 % (8 MB)
57 23:25:28.037023 progress 25 % (10 MB)
58 23:25:28.065289 progress 30 % (13 MB)
59 23:25:28.093554 progress 35 % (15 MB)
60 23:25:28.121745 progress 40 % (17 MB)
61 23:25:28.149282 progress 45 % (19 MB)
62 23:25:28.177056 progress 50 % (21 MB)
63 23:25:28.205078 progress 55 % (24 MB)
64 23:25:28.232935 progress 60 % (26 MB)
65 23:25:28.260193 progress 65 % (28 MB)
66 23:25:28.287581 progress 70 % (30 MB)
67 23:25:28.314813 progress 75 % (32 MB)
68 23:25:28.342071 progress 80 % (34 MB)
69 23:25:28.369259 progress 85 % (37 MB)
70 23:25:28.396742 progress 90 % (39 MB)
71 23:25:28.424130 progress 95 % (41 MB)
72 23:25:28.451354 progress 100 % (43 MB)
73 23:25:28.451909 43 MB downloaded in 0.60 s (72.60 MB/s)
74 23:25:28.452424 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:25:28.453233 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:25:28.453504 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:25:28.453766 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:25:28.454353 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 23:25:28.454635 saving as /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 23:25:28.454844 total size: 53209 (0 MB)
82 23:25:28.455054 No compression specified
83 23:25:28.493139 progress 61 % (0 MB)
84 23:25:28.493981 progress 100 % (0 MB)
85 23:25:28.494501 0 MB downloaded in 0.04 s (1.28 MB/s)
86 23:25:28.494981 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:25:28.495790 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:25:28.496095 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:25:28.496371 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:25:28.496856 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-403-ga8cc7432728d0/arm64/defconfig/gcc-12/modules.tar.xz
92 23:25:28.497094 saving as /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/modules/modules.tar
93 23:25:28.497297 total size: 11612440 (11 MB)
94 23:25:28.497506 Using unxz to decompress xz
95 23:25:28.534662 progress 0 % (0 MB)
96 23:25:28.601474 progress 5 % (0 MB)
97 23:25:28.677889 progress 10 % (1 MB)
98 23:25:28.774738 progress 15 % (1 MB)
99 23:25:28.869155 progress 20 % (2 MB)
100 23:25:28.949363 progress 25 % (2 MB)
101 23:25:29.026177 progress 30 % (3 MB)
102 23:25:29.106478 progress 35 % (3 MB)
103 23:25:29.180558 progress 40 % (4 MB)
104 23:25:29.257558 progress 45 % (5 MB)
105 23:25:29.342589 progress 50 % (5 MB)
106 23:25:29.420918 progress 55 % (6 MB)
107 23:25:29.506925 progress 60 % (6 MB)
108 23:25:29.588285 progress 65 % (7 MB)
109 23:25:29.669556 progress 70 % (7 MB)
110 23:25:29.748367 progress 75 % (8 MB)
111 23:25:29.832138 progress 80 % (8 MB)
112 23:25:29.911972 progress 85 % (9 MB)
113 23:25:29.990539 progress 90 % (9 MB)
114 23:25:30.068214 progress 95 % (10 MB)
115 23:25:30.145227 progress 100 % (11 MB)
116 23:25:30.156836 11 MB downloaded in 1.66 s (6.67 MB/s)
117 23:25:30.157743 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:25:30.159932 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:25:30.160690 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 23:25:30.161376 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 23:25:30.162024 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:25:30.162688 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 23:25:30.164175 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo
125 23:25:30.165335 makedir: /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin
126 23:25:30.166204 makedir: /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/tests
127 23:25:30.167050 makedir: /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/results
128 23:25:30.167865 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-add-keys
129 23:25:30.169182 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-add-sources
130 23:25:30.170403 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-background-process-start
131 23:25:30.171637 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-background-process-stop
132 23:25:30.173000 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-common-functions
133 23:25:30.174248 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-echo-ipv4
134 23:25:30.175521 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-install-packages
135 23:25:30.176755 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-installed-packages
136 23:25:30.177941 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-os-build
137 23:25:30.179166 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-probe-channel
138 23:25:30.180414 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-probe-ip
139 23:25:30.181603 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-target-ip
140 23:25:30.182779 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-target-mac
141 23:25:30.183958 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-target-storage
142 23:25:30.185211 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-case
143 23:25:30.186460 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-event
144 23:25:30.187651 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-feedback
145 23:25:30.188936 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-raise
146 23:25:30.190141 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-reference
147 23:25:30.191335 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-runner
148 23:25:30.192543 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-set
149 23:25:30.193803 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-test-shell
150 23:25:30.195035 Updating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-install-packages (oe)
151 23:25:30.196370 Updating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/bin/lava-installed-packages (oe)
152 23:25:30.197545 Creating /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/environment
153 23:25:30.198497 LAVA metadata
154 23:25:30.199126 - LAVA_JOB_ID=931333
155 23:25:30.199694 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:25:30.200626 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:25:30.202939 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:25:30.203692 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:25:30.204291 skipped lava-vland-overlay
160 23:25:30.204962 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:25:30.205641 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:25:30.206199 skipped lava-multinode-overlay
163 23:25:30.206843 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:25:30.207498 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:25:30.208160 Loading test definitions
166 23:25:30.208913 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:25:30.209507 Using /lava-931333 at stage 0
168 23:25:30.212277 uuid=931333_1.5.2.4.1 testdef=None
169 23:25:30.212664 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:25:30.213015 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:25:30.215305 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:25:30.216329 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:25:30.219103 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:25:30.220178 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:25:30.222937 runner path: /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/0/tests/0_dmesg test_uuid 931333_1.5.2.4.1
178 23:25:30.223665 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:25:30.224636 Creating lava-test-runner.conf files
181 23:25:30.224893 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/931333/lava-overlay-2sb6xuxo/lava-931333/0 for stage 0
182 23:25:30.225340 - 0_dmesg
183 23:25:30.225788 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:25:30.226135 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:25:30.254926 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:25:30.255426 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:25:30.255770 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:25:30.256154 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:25:30.256508 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:25:31.218429 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 23:25:31.218904 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 23:25:31.219154 extracting modules file /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk
193 23:25:32.589473 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:25:32.589967 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 23:25:32.590249 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931333/compress-overlay-6siz732l/overlay-1.5.2.5.tar.gz to ramdisk
196 23:25:32.590465 [common] Applying overlay /var/lib/lava/dispatcher/tmp/931333/compress-overlay-6siz732l/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk
197 23:25:32.622079 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:25:32.622520 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 23:25:32.622789 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 23:25:32.623020 Converting downloaded kernel to a uImage
201 23:25:32.623335 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/kernel/Image /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/kernel/uImage
202 23:25:33.098337 output: Image Name:
203 23:25:33.098766 output: Created: Sun Nov 3 23:25:32 2024
204 23:25:33.098981 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:25:33.099185 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 23:25:33.099385 output: Load Address: 01080000
207 23:25:33.099581 output: Entry Point: 01080000
208 23:25:33.099777 output:
209 23:25:33.100163 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:25:33.100554 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:25:33.100869 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 23:25:33.101205 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:25:33.101501 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 23:25:33.101786 Building ramdisk /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk
215 23:25:36.367158 >> 181607 blocks
216 23:25:44.967169 Adding RAMdisk u-boot header.
217 23:25:44.967645 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk.cpio.gz.uboot
218 23:25:45.244808 output: Image Name:
219 23:25:45.245226 output: Created: Sun Nov 3 23:25:44 2024
220 23:25:45.245435 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:25:45.245638 output: Data Size: 26060489 Bytes = 25449.70 KiB = 24.85 MiB
222 23:25:45.245839 output: Load Address: 00000000
223 23:25:45.246037 output: Entry Point: 00000000
224 23:25:45.246231 output:
225 23:25:45.246823 rename /var/lib/lava/dispatcher/tmp/931333/extract-overlay-ramdisk-ag7kbanc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot
226 23:25:45.247242 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 23:25:45.247522 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 23:25:45.247792 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 23:25:45.248112 No LXC device requested
230 23:25:45.248689 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:25:45.249250 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 23:25:45.249785 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:25:45.250231 Checking files for TFTP limit of 4294967296 bytes.
234 23:25:45.253265 end: 1 tftp-deploy (duration 00:00:18) [common]
235 23:25:45.253913 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:25:45.254482 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:25:45.255029 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:25:45.255575 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:25:45.256186 Using kernel file from prepare-kernel: 931333/tftp-deploy-3gwy2jyf/kernel/uImage
240 23:25:45.256871 substitutions:
241 23:25:45.257322 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:25:45.257763 - {DTB_ADDR}: 0x01070000
243 23:25:45.258195 - {DTB}: 931333/tftp-deploy-3gwy2jyf/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 23:25:45.258631 - {INITRD}: 931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot
245 23:25:45.259064 - {KERNEL_ADDR}: 0x01080000
246 23:25:45.259494 - {KERNEL}: 931333/tftp-deploy-3gwy2jyf/kernel/uImage
247 23:25:45.259925 - {LAVA_MAC}: None
248 23:25:45.260427 - {PRESEED_CONFIG}: None
249 23:25:45.260864 - {PRESEED_LOCAL}: None
250 23:25:45.261292 - {RAMDISK_ADDR}: 0x08000000
251 23:25:45.261718 - {RAMDISK}: 931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot
252 23:25:45.262151 - {ROOT_PART}: None
253 23:25:45.262578 - {ROOT}: None
254 23:25:45.263003 - {SERVER_IP}: 192.168.6.2
255 23:25:45.263434 - {TEE_ADDR}: 0x83000000
256 23:25:45.263863 - {TEE}: None
257 23:25:45.264318 Parsed boot commands:
258 23:25:45.264733 - setenv autoload no
259 23:25:45.265161 - setenv initrd_high 0xffffffff
260 23:25:45.265588 - setenv fdt_high 0xffffffff
261 23:25:45.266012 - dhcp
262 23:25:45.266437 - setenv serverip 192.168.6.2
263 23:25:45.266860 - tftpboot 0x01080000 931333/tftp-deploy-3gwy2jyf/kernel/uImage
264 23:25:45.267290 - tftpboot 0x08000000 931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot
265 23:25:45.267716 - tftpboot 0x01070000 931333/tftp-deploy-3gwy2jyf/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 23:25:45.268165 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:25:45.268602 - bootm 0x01080000 0x08000000 0x01070000
268 23:25:45.269151 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:25:45.270785 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:25:45.271273 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 23:25:45.285538 Setting prompt string to ['lava-test: # ']
273 23:25:45.287190 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:25:45.287875 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:25:45.288548 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:25:45.289280 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:25:45.290613 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 23:25:45.324931 >> OK - accepted request
279 23:25:45.327084 Returned 0 in 0 seconds
280 23:25:45.428368 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:25:45.430165 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:25:45.430777 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:25:45.431329 Setting prompt string to ['Hit any key to stop autoboot']
285 23:25:45.431826 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:25:45.433647 Trying 192.168.56.21...
287 23:25:45.434207 Connected to conserv1.
288 23:25:45.434710 Escape character is '^]'.
289 23:25:45.435201
290 23:25:45.435692 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 23:25:45.436237
292 23:25:52.928189 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 23:25:52.928585 bl2_stage_init 0x01
294 23:25:52.928826 bl2_stage_init 0x81
295 23:25:52.933704 hw id: 0x0000 - pwm id 0x01
296 23:25:52.933996 bl2_stage_init 0xc1
297 23:25:52.939313 bl2_stage_init 0x02
298 23:25:52.939593
299 23:25:52.939818 L0:00000000
300 23:25:52.940070 L1:00000703
301 23:25:52.940282 L2:00008067
302 23:25:52.940486 L3:15000000
303 23:25:52.944906 S1:00000000
304 23:25:52.945185 B2:20282000
305 23:25:52.945409 B1:a0f83180
306 23:25:52.945633
307 23:25:52.945848 TE: 69076
308 23:25:52.946069
309 23:25:52.950563 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 23:25:52.950840
311 23:25:52.956120 Board ID = 1
312 23:25:52.956391 Set cpu clk to 24M
313 23:25:52.956601 Set clk81 to 24M
314 23:25:52.961686 Use GP1_pll as DSU clk.
315 23:25:52.961957 DSU clk: 1200 Mhz
316 23:25:52.962168 CPU clk: 1200 MHz
317 23:25:52.967361 Set clk81 to 166.6M
318 23:25:52.972918 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 23:25:52.973191 board id: 1
320 23:25:52.979247 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:25:52.990773 fw parse done
322 23:25:52.996020 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:25:53.039458 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:25:53.050372 PIEI prepare done
325 23:25:53.050924 fastboot data load
326 23:25:53.051418 fastboot data verify
327 23:25:53.055956 verify result: 266
328 23:25:53.061681 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 23:25:53.062217 LPDDR4 probe
330 23:25:53.062698 ddr clk to 1584MHz
331 23:25:53.069297 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:25:53.106151
333 23:25:53.106725 dmc_version 0001
334 23:25:53.112908 Check phy result
335 23:25:53.119377 INFO : End of CA training
336 23:25:53.119923 INFO : End of initialization
337 23:25:53.125006 INFO : Training has run successfully!
338 23:25:53.125548 Check phy result
339 23:25:53.130672 INFO : End of initialization
340 23:25:53.131198 INFO : End of read enable training
341 23:25:53.136250 INFO : End of fine write leveling
342 23:25:53.141873 INFO : End of Write leveling coarse delay
343 23:25:53.142360 INFO : Training has run successfully!
344 23:25:53.142770 Check phy result
345 23:25:53.147478 INFO : End of initialization
346 23:25:53.147952 INFO : End of read dq deskew training
347 23:25:53.153048 INFO : End of MPR read delay center optimization
348 23:25:53.158738 INFO : End of write delay center optimization
349 23:25:53.164238 INFO : End of read delay center optimization
350 23:25:53.164748 INFO : End of max read latency training
351 23:25:53.169853 INFO : Training has run successfully!
352 23:25:53.170334 1D training succeed
353 23:25:53.178358 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:25:53.226651 Check phy result
355 23:25:53.227148 INFO : End of initialization
356 23:25:53.248940 INFO : End of 2D read delay Voltage center optimization
357 23:25:53.268134 INFO : End of 2D read delay Voltage center optimization
358 23:25:53.320045 INFO : End of 2D write delay Voltage center optimization
359 23:25:53.369201 INFO : End of 2D write delay Voltage center optimization
360 23:25:53.374759 INFO : Training has run successfully!
361 23:25:53.375247
362 23:25:53.375653 channel==0
363 23:25:53.380357 RxClkDly_Margin_A0==69 ps 7
364 23:25:53.380850 TxDqDly_Margin_A0==98 ps 10
365 23:25:53.383773 RxClkDly_Margin_A1==88 ps 9
366 23:25:53.384318 TxDqDly_Margin_A1==88 ps 9
367 23:25:53.389274 TrainedVREFDQ_A0==74
368 23:25:53.389773 TrainedVREFDQ_A1==74
369 23:25:53.390176 VrefDac_Margin_A0==22
370 23:25:53.394895 DeviceVref_Margin_A0==40
371 23:25:53.395381 VrefDac_Margin_A1==23
372 23:25:53.400503 DeviceVref_Margin_A1==40
373 23:25:53.400993
374 23:25:53.401398
375 23:25:53.401792 channel==1
376 23:25:53.402181 RxClkDly_Margin_A0==78 ps 8
377 23:25:53.406075 TxDqDly_Margin_A0==88 ps 9
378 23:25:53.406563 RxClkDly_Margin_A1==78 ps 8
379 23:25:53.411797 TxDqDly_Margin_A1==88 ps 9
380 23:25:53.412325 TrainedVREFDQ_A0==75
381 23:25:53.412730 TrainedVREFDQ_A1==77
382 23:25:53.417293 VrefDac_Margin_A0==22
383 23:25:53.417775 DeviceVref_Margin_A0==39
384 23:25:53.418174 VrefDac_Margin_A1==22
385 23:25:53.422892 DeviceVref_Margin_A1==37
386 23:25:53.423377
387 23:25:53.428536 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:25:53.429035
389 23:25:53.456446 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 23:25:53.462143 2D training succeed
391 23:25:53.467845 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:25:53.468406 auto size-- 65535DDR cs0 size: 2048MB
393 23:25:53.473308 DDR cs1 size: 2048MB
394 23:25:53.473798 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:25:53.478907 cs0 DataBus test pass
396 23:25:53.479396 cs1 DataBus test pass
397 23:25:53.479793 cs0 AddrBus test pass
398 23:25:53.484517 cs1 AddrBus test pass
399 23:25:53.485004
400 23:25:53.485401 100bdlr_step_size ps== 478
401 23:25:53.485804 result report
402 23:25:53.490083 boot times 0Enable ddr reg access
403 23:25:53.497230 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:25:53.510441 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 23:25:54.166717 bl2z: ptr: 05129330, size: 00001e40
406 23:25:54.176101 0.0;M3 CHK:0;cm4_sp_mode 0
407 23:25:54.176626 MVN_1=0x00000000
408 23:25:54.177057 MVN_2=0x00000000
409 23:25:54.187524 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 23:25:54.188064 OPS=0x04
411 23:25:54.188499 ring efuse init
412 23:25:54.190551 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 23:25:54.196214 [0.017319 Inits done]
414 23:25:54.196715 secure task start!
415 23:25:54.197137 high task start!
416 23:25:54.197543 low task start!
417 23:25:54.199970 run into bl31
418 23:25:54.209030 NOTICE: BL31: v1.3(release):4fc40b1
419 23:25:54.216024 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 23:25:54.216535 NOTICE: BL31: G12A normal boot!
421 23:25:54.232447 NOTICE: BL31: BL33 decompress pass
422 23:25:54.237249 ERROR: Error initializing runtime service opteed_fast
423 23:25:56.982091 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 23:25:56.982710 bl2_stage_init 0x01
425 23:25:56.983155 bl2_stage_init 0x81
426 23:25:56.987777 hw id: 0x0000 - pwm id 0x01
427 23:25:56.988355 bl2_stage_init 0xc1
428 23:25:56.993501 bl2_stage_init 0x02
429 23:25:56.994048
430 23:25:56.994456 L0:00000000
431 23:25:56.994843 L1:00000703
432 23:25:56.995229 L2:00008067
433 23:25:56.995614 L3:15000000
434 23:25:56.999129 S1:00000000
435 23:25:56.999639 B2:20282000
436 23:25:57.000090 B1:a0f83180
437 23:25:57.000497
438 23:25:57.000891 TE: 72025
439 23:25:57.001285
440 23:25:57.004771 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 23:25:57.005260
442 23:25:57.010444 Board ID = 1
443 23:25:57.010929 Set cpu clk to 24M
444 23:25:57.011327 Set clk81 to 24M
445 23:25:57.014155 Use GP1_pll as DSU clk.
446 23:25:57.014632 DSU clk: 1200 Mhz
447 23:25:57.019705 CPU clk: 1200 MHz
448 23:25:57.020235 Set clk81 to 166.6M
449 23:25:57.025324 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 23:25:57.025828 board id: 1
451 23:25:57.034009 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 23:25:57.044934 fw parse done
453 23:25:57.050906 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 23:25:57.094012 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 23:25:57.105197 PIEI prepare done
456 23:25:57.105692 fastboot data load
457 23:25:57.106097 fastboot data verify
458 23:25:57.110756 verify result: 266
459 23:25:57.116322 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 23:25:57.116808 LPDDR4 probe
461 23:25:57.117201 ddr clk to 1584MHz
462 23:25:57.124424 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 23:25:57.162069
464 23:25:57.162565 dmc_version 0001
465 23:25:57.169128 Check phy result
466 23:25:57.175072 INFO : End of CA training
467 23:25:57.175544 INFO : End of initialization
468 23:25:57.180716 INFO : Training has run successfully!
469 23:25:57.181187 Check phy result
470 23:25:57.186443 INFO : End of initialization
471 23:25:57.186942 INFO : End of read enable training
472 23:25:57.189604 INFO : End of fine write leveling
473 23:25:57.195155 INFO : End of Write leveling coarse delay
474 23:25:57.200755 INFO : Training has run successfully!
475 23:25:57.201269 Check phy result
476 23:25:57.201690 INFO : End of initialization
477 23:25:57.206385 INFO : End of read dq deskew training
478 23:25:57.209788 INFO : End of MPR read delay center optimization
479 23:25:57.215133 INFO : End of write delay center optimization
480 23:25:57.220779 INFO : End of read delay center optimization
481 23:25:57.221275 INFO : End of max read latency training
482 23:25:57.226375 INFO : Training has run successfully!
483 23:25:57.226868 1D training succeed
484 23:25:57.234622 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 23:25:57.282954 Check phy result
486 23:25:57.283464 INFO : End of initialization
487 23:25:57.310444 INFO : End of 2D read delay Voltage center optimization
488 23:25:57.335355 INFO : End of 2D read delay Voltage center optimization
489 23:25:57.391307 INFO : End of 2D write delay Voltage center optimization
490 23:25:57.445268 INFO : End of 2D write delay Voltage center optimization
491 23:25:57.450881 INFO : Training has run successfully!
492 23:25:57.451383
493 23:25:57.451808 channel==0
494 23:25:57.456437 RxClkDly_Margin_A0==78 ps 8
495 23:25:57.456936 TxDqDly_Margin_A0==98 ps 10
496 23:25:57.459693 RxClkDly_Margin_A1==78 ps 8
497 23:25:57.460221 TxDqDly_Margin_A1==88 ps 9
498 23:25:57.465306 TrainedVREFDQ_A0==74
499 23:25:57.465799 TrainedVREFDQ_A1==75
500 23:25:57.466216 VrefDac_Margin_A0==24
501 23:25:57.470914 DeviceVref_Margin_A0==40
502 23:25:57.471412 VrefDac_Margin_A1==23
503 23:25:57.476419 DeviceVref_Margin_A1==39
504 23:25:57.476916
505 23:25:57.477338
506 23:25:57.477751 channel==1
507 23:25:57.478149 RxClkDly_Margin_A0==78 ps 8
508 23:25:57.479925 TxDqDly_Margin_A0==98 ps 10
509 23:25:57.485494 RxClkDly_Margin_A1==78 ps 8
510 23:25:57.486000 TxDqDly_Margin_A1==88 ps 9
511 23:25:57.486427 TrainedVREFDQ_A0==78
512 23:25:57.491161 TrainedVREFDQ_A1==77
513 23:25:57.491660 VrefDac_Margin_A0==22
514 23:25:57.496730 DeviceVref_Margin_A0==36
515 23:25:57.497237 VrefDac_Margin_A1==22
516 23:25:57.497649 DeviceVref_Margin_A1==37
517 23:25:57.498050
518 23:25:57.505665 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 23:25:57.506173
520 23:25:57.531623 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 23:25:57.537011 2D training succeed
522 23:25:57.542606 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 23:25:57.543127 auto size-- 65535DDR cs0 size: 2048MB
524 23:25:57.548248 DDR cs1 size: 2048MB
525 23:25:57.548753 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 23:25:57.553794 cs0 DataBus test pass
527 23:25:57.554286 cs1 DataBus test pass
528 23:25:57.559389 cs0 AddrBus test pass
529 23:25:57.559916 cs1 AddrBus test pass
530 23:25:57.560379
531 23:25:57.560789 100bdlr_step_size ps== 471
532 23:25:57.564985 result report
533 23:25:57.565483 boot times 0Enable ddr reg access
534 23:25:57.573523 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 23:25:57.587116 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 23:25:58.246677 bl2z: ptr: 05129330, size: 00001e40
537 23:25:58.255521 0.0;M3 CHK:0;cm4_sp_mode 0
538 23:25:58.256079 MVN_1=0x00000000
539 23:25:58.256514 MVN_2=0x00000000
540 23:25:58.266900 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 23:25:58.267409 OPS=0x04
542 23:25:58.267833 ring efuse init
543 23:25:58.269883 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 23:25:58.275697 [0.017354 Inits done]
545 23:25:58.276220 secure task start!
546 23:25:58.276644 high task start!
547 23:25:58.277052 low task start!
548 23:25:58.279486 run into bl31
549 23:25:58.288611 NOTICE: BL31: v1.3(release):4fc40b1
550 23:25:58.296548 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 23:25:58.297057 NOTICE: BL31: G12A normal boot!
552 23:25:58.312082 NOTICE: BL31: BL33 decompress pass
553 23:25:58.317712 ERROR: Error initializing runtime service opteed_fast
554 23:25:59.681245 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 23:25:59.681824 bl2_stage_init 0x01
556 23:25:59.682248 bl2_stage_init 0x81
557 23:25:59.686897 hw id: 0x0000 - pwm id 0x01
558 23:25:59.687390 bl2_stage_init 0xc1
559 23:25:59.692524 bl2_stage_init 0x02
560 23:25:59.693020
561 23:25:59.693445 L0:00000000
562 23:25:59.693854 L1:00000703
563 23:25:59.694255 L2:00008067
564 23:25:59.694654 L3:15000000
565 23:25:59.698082 S1:00000000
566 23:25:59.698572 B2:20282000
567 23:25:59.698988 B1:a0f83180
568 23:25:59.699396
569 23:25:59.699802 TE: 71942
570 23:25:59.700244
571 23:25:59.703694 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 23:25:59.704222
573 23:25:59.709279 Board ID = 1
574 23:25:59.709769 Set cpu clk to 24M
575 23:25:59.710183 Set clk81 to 24M
576 23:25:59.714890 Use GP1_pll as DSU clk.
577 23:25:59.715381 DSU clk: 1200 Mhz
578 23:25:59.715798 CPU clk: 1200 MHz
579 23:25:59.720519 Set clk81 to 166.6M
580 23:25:59.726328 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 23:25:59.726823 board id: 1
582 23:25:59.732592 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 23:25:59.743924 fw parse done
584 23:25:59.749878 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 23:25:59.792423 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 23:25:59.803462 PIEI prepare done
587 23:25:59.803952 fastboot data load
588 23:25:59.804428 fastboot data verify
589 23:25:59.809058 verify result: 266
590 23:25:59.814692 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 23:25:59.815187 LPDDR4 probe
592 23:25:59.815604 ddr clk to 1584MHz
593 23:25:59.822637 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 23:25:59.859870
595 23:25:59.860400 dmc_version 0001
596 23:25:59.866603 Check phy result
597 23:25:59.872466 INFO : End of CA training
598 23:25:59.872959 INFO : End of initialization
599 23:25:59.878136 INFO : Training has run successfully!
600 23:25:59.878630 Check phy result
601 23:25:59.883687 INFO : End of initialization
602 23:25:59.884209 INFO : End of read enable training
603 23:25:59.889277 INFO : End of fine write leveling
604 23:25:59.894866 INFO : End of Write leveling coarse delay
605 23:25:59.895361 INFO : Training has run successfully!
606 23:25:59.895779 Check phy result
607 23:25:59.900445 INFO : End of initialization
608 23:25:59.900934 INFO : End of read dq deskew training
609 23:25:59.906057 INFO : End of MPR read delay center optimization
610 23:25:59.911683 INFO : End of write delay center optimization
611 23:25:59.917278 INFO : End of read delay center optimization
612 23:25:59.917783 INFO : End of max read latency training
613 23:25:59.922869 INFO : Training has run successfully!
614 23:25:59.923361 1D training succeed
615 23:25:59.932008 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 23:25:59.979652 Check phy result
617 23:25:59.980173 INFO : End of initialization
618 23:26:00.001989 INFO : End of 2D read delay Voltage center optimization
619 23:26:00.021152 INFO : End of 2D read delay Voltage center optimization
620 23:26:00.073010 INFO : End of 2D write delay Voltage center optimization
621 23:26:00.122227 INFO : End of 2D write delay Voltage center optimization
622 23:26:00.127844 INFO : Training has run successfully!
623 23:26:00.128382
624 23:26:00.128812 channel==0
625 23:26:00.133370 RxClkDly_Margin_A0==88 ps 9
626 23:26:00.133861 TxDqDly_Margin_A0==98 ps 10
627 23:26:00.138983 RxClkDly_Margin_A1==88 ps 9
628 23:26:00.139479 TxDqDly_Margin_A1==98 ps 10
629 23:26:00.139899 TrainedVREFDQ_A0==74
630 23:26:00.144599 TrainedVREFDQ_A1==74
631 23:26:00.145100 VrefDac_Margin_A0==24
632 23:26:00.145520 DeviceVref_Margin_A0==40
633 23:26:00.150201 VrefDac_Margin_A1==23
634 23:26:00.150691 DeviceVref_Margin_A1==40
635 23:26:00.151107
636 23:26:00.151515
637 23:26:00.155758 channel==1
638 23:26:00.156282 RxClkDly_Margin_A0==88 ps 9
639 23:26:00.156702 TxDqDly_Margin_A0==98 ps 10
640 23:26:00.161383 RxClkDly_Margin_A1==78 ps 8
641 23:26:00.161872 TxDqDly_Margin_A1==88 ps 9
642 23:26:00.166975 TrainedVREFDQ_A0==78
643 23:26:00.167469 TrainedVREFDQ_A1==75
644 23:26:00.167889 VrefDac_Margin_A0==22
645 23:26:00.172592 DeviceVref_Margin_A0==36
646 23:26:00.173083 VrefDac_Margin_A1==22
647 23:26:00.178177 DeviceVref_Margin_A1==38
648 23:26:00.178671
649 23:26:00.179089 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 23:26:00.179493
651 23:26:00.211731 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
652 23:26:00.212290 2D training succeed
653 23:26:00.217365 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 23:26:00.222974 auto size-- 65535DDR cs0 size: 2048MB
655 23:26:00.223470 DDR cs1 size: 2048MB
656 23:26:00.228600 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 23:26:00.229094 cs0 DataBus test pass
658 23:26:00.234170 cs1 DataBus test pass
659 23:26:00.234658 cs0 AddrBus test pass
660 23:26:00.235079 cs1 AddrBus test pass
661 23:26:00.235486
662 23:26:00.239774 100bdlr_step_size ps== 478
663 23:26:00.240337 result report
664 23:26:00.245369 boot times 0Enable ddr reg access
665 23:26:00.250655 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 23:26:00.264435 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 23:26:00.918401 bl2z: ptr: 05129330, size: 00001e40
668 23:26:00.926836 0.0;M3 CHK:0;cm4_sp_mode 0
669 23:26:00.927349 MVN_1=0x00000000
670 23:26:00.927767 MVN_2=0x00000000
671 23:26:00.938503 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 23:26:00.939015 OPS=0x04
673 23:26:00.939438 ring efuse init
674 23:26:00.943956 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 23:26:00.944485 [0.017310 Inits done]
676 23:26:00.944904 secure task start!
677 23:26:00.951661 high task start!
678 23:26:00.952172 low task start!
679 23:26:00.952599 run into bl31
680 23:26:00.960256 NOTICE: BL31: v1.3(release):4fc40b1
681 23:26:00.968077 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 23:26:00.968624 NOTICE: BL31: G12A normal boot!
683 23:26:00.983659 NOTICE: BL31: BL33 decompress pass
684 23:26:00.988345 ERROR: Error initializing runtime service opteed_fast
685 23:26:01.783369
686 23:26:01.783956
687 23:26:01.788810 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 23:26:01.789309
689 23:26:01.792309 Model: Libre Computer AML-S905D3-CC Solitude
690 23:26:01.939115 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 23:26:01.954526 DRAM: 2 GiB (effective 3.8 GiB)
692 23:26:02.055544 Core: 406 devices, 33 uclasses, devicetree: separate
693 23:26:02.061417 WDT: Not starting watchdog@f0d0
694 23:26:02.086422 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 23:26:02.098617 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 23:26:02.103656 ** Bad device specification mmc 0 **
697 23:26:02.113717 Card did not respond to voltage select! : -110
698 23:26:02.121358 ** Bad device specification mmc 0 **
699 23:26:02.121852 Couldn't find partition mmc 0
700 23:26:02.129696 Card did not respond to voltage select! : -110
701 23:26:02.135186 ** Bad device specification mmc 0 **
702 23:26:02.135671 Couldn't find partition mmc 0
703 23:26:02.140276 Error: could not access storage.
704 23:26:02.437664 Net: eth0: ethernet@ff3f0000
705 23:26:02.438260 starting USB...
706 23:26:02.683010 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 23:26:02.683536 Starting the controller
708 23:26:02.689569 USB XHCI 1.10
709 23:26:04.243328 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 23:26:04.251546 scanning usb for storage devices... 0 Storage Device(s) found
712 23:26:04.303123 Hit any key to stop autoboot: 1
713 23:26:04.304015 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 23:26:04.304732 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 23:26:04.305238 Setting prompt string to ['=>']
716 23:26:04.305727 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 23:26:04.317607 0
718 23:26:04.318569 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 23:26:04.419784 => setenv autoload no
721 23:26:04.420825 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 23:26:04.425985 setenv autoload no
724 23:26:04.527503 => setenv initrd_high 0xffffffff
725 23:26:04.528472 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 23:26:04.533083 setenv initrd_high 0xffffffff
728 23:26:04.634547 => setenv fdt_high 0xffffffff
729 23:26:04.635424 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 23:26:04.639931 setenv fdt_high 0xffffffff
732 23:26:04.741455 => dhcp
733 23:26:04.742452 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 23:26:04.746392 dhcp
735 23:26:05.251939 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 23:26:05.252643 Speed: 1000, full duplex
737 23:26:05.253107 BOOTP broadcast 1
738 23:26:05.260926 DHCP client bound to address 192.168.6.21 (9 ms)
740 23:26:05.362492 => setenv serverip 192.168.6.2
741 23:26:05.363189 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 23:26:05.367782 setenv serverip 192.168.6.2
744 23:26:05.469323 => tftpboot 0x01080000 931333/tftp-deploy-3gwy2jyf/kernel/uImage
745 23:26:05.470031 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 23:26:05.477056 tftpboot 0x01080000 931333/tftp-deploy-3gwy2jyf/kernel/uImage
747 23:26:05.477575 Speed: 1000, full duplex
748 23:26:05.478029 Using ethernet@ff3f0000 device
749 23:26:05.482601 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 23:26:05.487853 Filename '931333/tftp-deploy-3gwy2jyf/kernel/uImage'.
751 23:26:05.491718 Load address: 0x1080000
752 23:26:08.339557 Loading: *################################################## 43.6 MiB
753 23:26:08.340263 15.3 MiB/s
754 23:26:08.340733 done
755 23:26:08.343278 Bytes transferred = 45713984 (2b98a40 hex)
757 23:26:08.444925 => tftpboot 0x08000000 931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot
758 23:26:08.445703 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
759 23:26:08.454687 tftpboot 0x08000000 931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot
760 23:26:08.455254 Speed: 1000, full duplex
761 23:26:08.455675 Using ethernet@ff3f0000 device
762 23:26:08.458019 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 23:26:08.469912 Filename '931333/tftp-deploy-3gwy2jyf/ramdisk/ramdisk.cpio.gz.uboot'.
764 23:26:08.470453 Load address: 0x8000000
765 23:26:10.162592 Loading: *################################################# UDP wrong checksum 00000005 00004e9e
766 23:26:15.163373 T UDP wrong checksum 00000005 00004e9e
767 23:26:15.551424 UDP wrong checksum 000000ff 00007fc0
768 23:26:15.560130 UDP wrong checksum 000000ff 000013b3
769 23:26:25.165712 T T UDP wrong checksum 00000005 00004e9e
770 23:26:45.167736 T T T UDP wrong checksum 00000005 00004e9e
771 23:26:45.986805 T UDP wrong checksum 000000ff 000025b1
772 23:26:46.057800 UDP wrong checksum 000000ff 0000aaa3
773 23:27:05.174442 T T T
774 23:27:05.175071 Retry count exceeded; starting again
776 23:27:05.176564 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
779 23:27:05.178459 end: 2.4 uboot-commands (duration 00:01:20) [common]
781 23:27:05.179845 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
783 23:27:05.180957 end: 2 uboot-action (duration 00:01:20) [common]
785 23:27:05.182466 Cleaning after the job
786 23:27:05.183008 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/ramdisk
787 23:27:05.184352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/kernel
788 23:27:05.230464 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/dtb
789 23:27:05.231405 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/931333/tftp-deploy-3gwy2jyf/modules
790 23:27:05.251576 start: 4.1 power-off (timeout 00:00:30) [common]
791 23:27:05.252284 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
792 23:27:05.286897 >> OK - accepted request
793 23:27:05.288992 Returned 0 in 0 seconds
794 23:27:05.389763 end: 4.1 power-off (duration 00:00:00) [common]
796 23:27:05.390754 start: 4.2 read-feedback (timeout 00:10:00) [common]
797 23:27:05.391401 Listened to connection for namespace 'common' for up to 1s
798 23:27:06.392406 Finalising connection for namespace 'common'
799 23:27:06.393307 Disconnecting from shell: Finalise
800 23:27:06.393970 =>
801 23:27:06.495487 end: 4.2 read-feedback (duration 00:00:01) [common]
802 23:27:06.496871 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/931333
803 23:27:06.895681 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/931333
804 23:27:06.896298 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.