Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 20:51:50.589757 lava-dispatcher, installed at version: 2024.01
2 20:51:50.590547 start: 0 validate
3 20:51:50.591019 Start time: 2024-10-30 20:51:50.590989+00:00 (UTC)
4 20:51:50.591568 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 20:51:50.592103 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 20:51:50.624628 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 20:51:50.625170 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 20:51:50.650524 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 20:51:50.651132 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 20:51:50.676996 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 20:51:50.677516 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 20:51:50.703307 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 20:51:50.703799 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:51:50.735126 validate duration: 0.14
16 20:51:50.736017 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:51:50.736323 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:51:50.736606 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:51:50.737335 Not decompressing ramdisk as can be used compressed.
20 20:51:50.737768 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 20:51:50.738060 saving as /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/ramdisk/initrd.cpio.gz
22 20:51:50.738317 total size: 4775763 (4 MB)
23 20:51:50.769453 progress 0 % (0 MB)
24 20:51:50.773177 progress 5 % (0 MB)
25 20:51:50.776887 progress 10 % (0 MB)
26 20:51:50.780373 progress 15 % (0 MB)
27 20:51:50.784165 progress 20 % (0 MB)
28 20:51:50.787562 progress 25 % (1 MB)
29 20:51:50.790903 progress 30 % (1 MB)
30 20:51:50.794768 progress 35 % (1 MB)
31 20:51:50.798207 progress 40 % (1 MB)
32 20:51:50.801501 progress 45 % (2 MB)
33 20:51:50.804846 progress 50 % (2 MB)
34 20:51:50.808537 progress 55 % (2 MB)
35 20:51:50.811950 progress 60 % (2 MB)
36 20:51:50.815277 progress 65 % (2 MB)
37 20:51:50.819007 progress 70 % (3 MB)
38 20:51:50.822332 progress 75 % (3 MB)
39 20:51:50.825630 progress 80 % (3 MB)
40 20:51:50.829126 progress 85 % (3 MB)
41 20:51:50.832760 progress 90 % (4 MB)
42 20:51:50.838079 progress 95 % (4 MB)
43 20:51:50.841012 progress 100 % (4 MB)
44 20:51:50.841637 4 MB downloaded in 0.10 s (44.09 MB/s)
45 20:51:50.842206 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:51:50.843078 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:51:50.843372 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:51:50.843645 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:51:50.844107 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 20:51:50.844355 saving as /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/kernel/zImage
52 20:51:50.844585 total size: 11440640 (10 MB)
53 20:51:50.844798 No compression specified
54 20:51:50.875311 progress 0 % (0 MB)
55 20:51:50.882864 progress 5 % (0 MB)
56 20:51:50.890073 progress 10 % (1 MB)
57 20:51:50.897571 progress 15 % (1 MB)
58 20:51:50.904713 progress 20 % (2 MB)
59 20:51:50.912215 progress 25 % (2 MB)
60 20:51:50.919232 progress 30 % (3 MB)
61 20:51:50.926687 progress 35 % (3 MB)
62 20:51:50.933703 progress 40 % (4 MB)
63 20:51:50.941391 progress 45 % (4 MB)
64 20:51:50.948553 progress 50 % (5 MB)
65 20:51:50.956039 progress 55 % (6 MB)
66 20:51:50.963087 progress 60 % (6 MB)
67 20:51:50.970313 progress 65 % (7 MB)
68 20:51:50.978383 progress 70 % (7 MB)
69 20:51:50.985339 progress 75 % (8 MB)
70 20:51:50.993073 progress 80 % (8 MB)
71 20:51:51.000134 progress 85 % (9 MB)
72 20:51:51.007541 progress 90 % (9 MB)
73 20:51:51.014567 progress 95 % (10 MB)
74 20:51:51.021506 progress 100 % (10 MB)
75 20:51:51.022056 10 MB downloaded in 0.18 s (61.48 MB/s)
76 20:51:51.022557 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:51:51.023376 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:51:51.023656 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:51:51.023920 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:51:51.024389 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 20:51:51.024672 saving as /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/dtb/am335x-boneblack.dtb
83 20:51:51.024885 total size: 70568 (0 MB)
84 20:51:51.025095 No compression specified
85 20:51:51.054681 progress 46 % (0 MB)
86 20:51:51.055504 progress 92 % (0 MB)
87 20:51:51.056233 progress 100 % (0 MB)
88 20:51:51.056713 0 MB downloaded in 0.03 s (2.12 MB/s)
89 20:51:51.057255 end: 1.3.1 http-download (duration 00:00:00) [common]
91 20:51:51.058231 end: 1.3 download-retry (duration 00:00:00) [common]
92 20:51:51.058575 start: 1.4 download-retry (timeout 00:10:00) [common]
93 20:51:51.058892 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 20:51:51.059392 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 20:51:51.059683 saving as /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/nfsrootfs/full.rootfs.tar
96 20:51:51.059930 total size: 117747780 (112 MB)
97 20:51:51.060183 Using unxz to decompress xz
98 20:51:51.089323 progress 0 % (0 MB)
99 20:51:51.808489 progress 5 % (5 MB)
100 20:51:52.544437 progress 10 % (11 MB)
101 20:51:53.306552 progress 15 % (16 MB)
102 20:51:54.014788 progress 20 % (22 MB)
103 20:51:54.587522 progress 25 % (28 MB)
104 20:51:55.382031 progress 30 % (33 MB)
105 20:51:56.173491 progress 35 % (39 MB)
106 20:51:56.502289 progress 40 % (44 MB)
107 20:51:56.853326 progress 45 % (50 MB)
108 20:51:57.513852 progress 50 % (56 MB)
109 20:51:58.315060 progress 55 % (61 MB)
110 20:51:59.078824 progress 60 % (67 MB)
111 20:51:59.816423 progress 65 % (73 MB)
112 20:52:00.573241 progress 70 % (78 MB)
113 20:52:01.322962 progress 75 % (84 MB)
114 20:52:02.046459 progress 80 % (89 MB)
115 20:52:02.756330 progress 85 % (95 MB)
116 20:52:03.536356 progress 90 % (101 MB)
117 20:52:04.281345 progress 95 % (106 MB)
118 20:52:05.085639 progress 100 % (112 MB)
119 20:52:05.097936 112 MB downloaded in 14.04 s (8.00 MB/s)
120 20:52:05.098866 end: 1.4.1 http-download (duration 00:00:14) [common]
122 20:52:05.100465 end: 1.4 download-retry (duration 00:00:14) [common]
123 20:52:05.100978 start: 1.5 download-retry (timeout 00:09:46) [common]
124 20:52:05.101482 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 20:52:05.102471 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 20:52:05.102946 saving as /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/modules/modules.tar
127 20:52:05.103350 total size: 6604028 (6 MB)
128 20:52:05.103761 Using unxz to decompress xz
129 20:52:05.140616 progress 0 % (0 MB)
130 20:52:05.178033 progress 5 % (0 MB)
131 20:52:05.220727 progress 10 % (0 MB)
132 20:52:05.264443 progress 15 % (0 MB)
133 20:52:05.308349 progress 20 % (1 MB)
134 20:52:05.350176 progress 25 % (1 MB)
135 20:52:05.392349 progress 30 % (1 MB)
136 20:52:05.434856 progress 35 % (2 MB)
137 20:52:05.477900 progress 40 % (2 MB)
138 20:52:05.520630 progress 45 % (2 MB)
139 20:52:05.562849 progress 50 % (3 MB)
140 20:52:05.604933 progress 55 % (3 MB)
141 20:52:05.647189 progress 60 % (3 MB)
142 20:52:05.693563 progress 65 % (4 MB)
143 20:52:05.736000 progress 70 % (4 MB)
144 20:52:05.779856 progress 75 % (4 MB)
145 20:52:05.825968 progress 80 % (5 MB)
146 20:52:05.869021 progress 85 % (5 MB)
147 20:52:05.912737 progress 90 % (5 MB)
148 20:52:05.959428 progress 95 % (6 MB)
149 20:52:06.001677 progress 100 % (6 MB)
150 20:52:06.014029 6 MB downloaded in 0.91 s (6.92 MB/s)
151 20:52:06.014952 end: 1.5.1 http-download (duration 00:00:01) [common]
153 20:52:06.016703 end: 1.5 download-retry (duration 00:00:01) [common]
154 20:52:06.017270 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 20:52:06.017876 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 20:52:22.498421 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y
157 20:52:22.499024 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 20:52:22.499310 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 20:52:22.500036 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0
160 20:52:22.500584 makedir: /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin
161 20:52:22.500958 makedir: /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/tests
162 20:52:22.501278 makedir: /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/results
163 20:52:22.501610 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-add-keys
164 20:52:22.502180 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-add-sources
165 20:52:22.502703 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-background-process-start
166 20:52:22.503200 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-background-process-stop
167 20:52:22.503734 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-common-functions
168 20:52:22.504234 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-echo-ipv4
169 20:52:22.504726 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-install-packages
170 20:52:22.505204 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-installed-packages
171 20:52:22.505692 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-os-build
172 20:52:22.506217 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-probe-channel
173 20:52:22.506769 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-probe-ip
174 20:52:22.507258 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-target-ip
175 20:52:22.507737 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-target-mac
176 20:52:22.508217 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-target-storage
177 20:52:22.508700 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-case
178 20:52:22.509183 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-event
179 20:52:22.509658 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-feedback
180 20:52:22.510166 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-raise
181 20:52:22.510642 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-reference
182 20:52:22.511146 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-runner
183 20:52:22.511681 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-set
184 20:52:22.512177 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-test-shell
185 20:52:22.512682 Updating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-add-keys (debian)
186 20:52:22.513234 Updating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-add-sources (debian)
187 20:52:22.513772 Updating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-install-packages (debian)
188 20:52:22.514336 Updating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-installed-packages (debian)
189 20:52:22.514843 Updating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/bin/lava-os-build (debian)
190 20:52:22.515336 Creating /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/environment
191 20:52:22.515733 LAVA metadata
192 20:52:22.515993 - LAVA_JOB_ID=914717
193 20:52:22.516206 - LAVA_DISPATCHER_IP=192.168.6.3
194 20:52:22.516570 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 20:52:22.517531 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 20:52:22.517890 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 20:52:22.518105 skipped lava-vland-overlay
198 20:52:22.518346 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 20:52:22.518600 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 20:52:22.518802 skipped lava-multinode-overlay
201 20:52:22.519037 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 20:52:22.519284 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 20:52:22.519531 Loading test definitions
204 20:52:22.519802 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 20:52:22.520040 Using /lava-914717 at stage 0
206 20:52:22.521177 uuid=914717_1.6.2.4.1 testdef=None
207 20:52:22.521477 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 20:52:22.521737 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 20:52:22.523341 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 20:52:22.524129 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 20:52:22.526109 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 20:52:22.526940 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 20:52:22.528775 runner path: /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/0/tests/0_timesync-off test_uuid 914717_1.6.2.4.1
216 20:52:22.529336 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 20:52:22.530171 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 20:52:22.530395 Using /lava-914717 at stage 0
220 20:52:22.530751 Fetching tests from https://github.com/kernelci/test-definitions.git
221 20:52:22.531040 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/0/tests/1_kselftest-dt'
222 20:52:26.106493 Running '/usr/bin/git checkout kernelci.org
223 20:52:26.261311 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 20:52:26.263210 uuid=914717_1.6.2.4.5 testdef=None
225 20:52:26.263659 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 20:52:26.264625 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 20:52:26.268212 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 20:52:26.269263 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 20:52:26.274199 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 20:52:26.275308 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 20:52:26.279974 runner path: /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/0/tests/1_kselftest-dt test_uuid 914717_1.6.2.4.5
235 20:52:26.280386 BOARD='beaglebone-black'
236 20:52:26.280657 BRANCH='mainline'
237 20:52:26.280915 SKIPFILE='/dev/null'
238 20:52:26.281162 SKIP_INSTALL='True'
239 20:52:26.281409 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 20:52:26.281667 TST_CASENAME=''
241 20:52:26.281940 TST_CMDFILES='dt'
242 20:52:26.282668 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 20:52:26.283678 Creating lava-test-runner.conf files
245 20:52:26.283939 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/914717/lava-overlay-gg79dgh0/lava-914717/0 for stage 0
246 20:52:26.284437 - 0_timesync-off
247 20:52:26.284764 - 1_kselftest-dt
248 20:52:26.285191 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 20:52:26.285556 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 20:52:49.965538 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 20:52:49.966011 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 20:52:49.966310 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 20:52:49.966619 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 20:52:49.966910 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 20:52:50.376570 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 20:52:50.377057 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 20:52:50.377329 extracting modules file /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y
258 20:52:51.257028 extracting modules file /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914717/extract-overlay-ramdisk-6q0p18fy/ramdisk
259 20:52:52.164240 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 20:52:52.164715 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 20:52:52.165011 [common] Applying overlay to NFS
262 20:52:52.165239 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914717/compress-overlay-cp1lnfa3/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y
263 20:52:54.900082 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 20:52:54.900569 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 20:52:54.900868 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 20:52:54.901191 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 20:52:54.901463 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 20:52:54.901737 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 20:52:54.902029 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 20:52:54.902309 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 20:52:54.902547 Building ramdisk /var/lib/lava/dispatcher/tmp/914717/extract-overlay-ramdisk-6q0p18fy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/914717/extract-overlay-ramdisk-6q0p18fy/ramdisk
272 20:52:55.881957 >> 74897 blocks
273 20:53:00.518045 Adding RAMdisk u-boot header.
274 20:53:00.518768 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/914717/extract-overlay-ramdisk-6q0p18fy/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/914717/extract-overlay-ramdisk-6q0p18fy/ramdisk.cpio.gz.uboot
275 20:53:00.679061 output: Image Name:
276 20:53:00.679486 output: Created: Wed Oct 30 20:53:00 2024
277 20:53:00.679696 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 20:53:00.679901 output: Data Size: 14793899 Bytes = 14447.17 KiB = 14.11 MiB
279 20:53:00.680103 output: Load Address: 00000000
280 20:53:00.680302 output: Entry Point: 00000000
281 20:53:00.680498 output:
282 20:53:00.681128 rename /var/lib/lava/dispatcher/tmp/914717/extract-overlay-ramdisk-6q0p18fy/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot
283 20:53:00.681546 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 20:53:00.681871 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 20:53:00.682421 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 20:53:00.682875 No LXC device requested
287 20:53:00.683368 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 20:53:00.683869 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 20:53:00.684355 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 20:53:00.684762 Checking files for TFTP limit of 4294967296 bytes.
291 20:53:00.687464 end: 1 tftp-deploy (duration 00:01:10) [common]
292 20:53:00.688046 start: 2 uboot-action (timeout 00:05:00) [common]
293 20:53:00.688588 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 20:53:00.689082 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 20:53:00.689575 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 20:53:00.690355 substitutions:
297 20:53:00.690772 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 20:53:00.691174 - {DTB_ADDR}: 0x88000000
299 20:53:00.691568 - {DTB}: 914717/tftp-deploy-s16kyw2i/dtb/am335x-boneblack.dtb
300 20:53:00.691965 - {INITRD}: 914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot
301 20:53:00.692358 - {KERNEL_ADDR}: 0x82000000
302 20:53:00.692749 - {KERNEL}: 914717/tftp-deploy-s16kyw2i/kernel/zImage
303 20:53:00.693138 - {LAVA_MAC}: None
304 20:53:00.693561 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y
305 20:53:00.693986 - {NFS_SERVER_IP}: 192.168.6.3
306 20:53:00.694378 - {PRESEED_CONFIG}: None
307 20:53:00.694764 - {PRESEED_LOCAL}: None
308 20:53:00.695148 - {RAMDISK_ADDR}: 0x83000000
309 20:53:00.695533 - {RAMDISK}: 914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot
310 20:53:00.695922 - {ROOT_PART}: None
311 20:53:00.696306 - {ROOT}: None
312 20:53:00.696688 - {SERVER_IP}: 192.168.6.3
313 20:53:00.697070 - {TEE_ADDR}: 0x83000000
314 20:53:00.697451 - {TEE}: None
315 20:53:00.697852 Parsed boot commands:
316 20:53:00.698230 - setenv autoload no
317 20:53:00.698613 - setenv initrd_high 0xffffffff
318 20:53:00.698993 - setenv fdt_high 0xffffffff
319 20:53:00.699373 - dhcp
320 20:53:00.699750 - setenv serverip 192.168.6.3
321 20:53:00.700129 - tftp 0x82000000 914717/tftp-deploy-s16kyw2i/kernel/zImage
322 20:53:00.700508 - tftp 0x83000000 914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot
323 20:53:00.700890 - setenv initrd_size ${filesize}
324 20:53:00.701266 - tftp 0x88000000 914717/tftp-deploy-s16kyw2i/dtb/am335x-boneblack.dtb
325 20:53:00.701646 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 20:53:00.702067 - bootz 0x82000000 0x83000000 0x88000000
327 20:53:00.702551 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 20:53:00.704014 start: 2.3 connect-device (timeout 00:05:00) [common]
330 20:53:00.704427 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 20:53:00.718812 Setting prompt string to ['lava-test: # ']
332 20:53:00.720267 end: 2.3 connect-device (duration 00:00:00) [common]
333 20:53:00.720868 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 20:53:00.721543 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 20:53:00.722220 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 20:53:00.723549 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 20:53:00.760872 >> OK - accepted request
338 20:53:00.762890 Returned 0 in 0 seconds
339 20:53:00.863979 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 20:53:00.865580 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 20:53:00.866204 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 20:53:00.866716 Setting prompt string to ['Hit any key to stop autoboot']
344 20:53:00.867172 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 20:53:00.868699 Trying 192.168.56.22...
346 20:53:00.869177 Connected to conserv3.
347 20:53:00.869595 Escape character is '^]'.
348 20:53:00.870045
349 20:53:00.870466 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 20:53:00.870898
351 20:53:08.829648
352 20:53:08.836564 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 20:53:08.836891 Trying to boot from MMC1
354 20:53:09.422405
355 20:53:09.422851
356 20:53:09.427800 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 20:53:09.428371
358 20:53:09.428805 CPU : AM335X-GP rev 2.0
359 20:53:09.433020 Model: TI AM335x BeagleBone Black
360 20:53:09.433601 DRAM: 512 MiB
361 20:53:12.884452
362 20:53:12.891437 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 20:53:12.892057 Trying to boot from MMC1
364 20:53:13.477285
365 20:53:13.478009
366 20:53:13.482755 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 20:53:13.483278
368 20:53:13.483735 CPU : AM335X-GP rev 2.0
369 20:53:13.487995 Model: TI AM335x BeagleBone Black
370 20:53:13.488581 DRAM: 512 MiB
371 20:53:15.579980
372 20:53:15.586796 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 20:53:15.587334 Trying to boot from MMC1
374 20:53:16.173043
375 20:53:16.173965
376 20:53:16.178538 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 20:53:16.179277
378 20:53:16.179932 CPU : AM335X-GP rev 2.0
379 20:53:16.183677 Model: TI AM335x BeagleBone Black
380 20:53:16.184386 DRAM: 512 MiB
381 20:53:16.267234 Core: 160 devices, 18 uclasses, devicetree: separate
382 20:53:16.281942 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 20:53:16.682783 NAND: 0 MiB
384 20:53:16.692710 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 20:53:16.767423 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 20:53:16.788867 <ethaddr> not set. Validating first E-fuse MAC
387 20:53:16.818465 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 20:53:16.877128 Hit any key to stop autoboot: 2
390 20:53:16.878184 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
391 20:53:16.878929 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 20:53:16.879580 Setting prompt string to ['=>']
393 20:53:16.880145 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 20:53:16.886887 0
395 20:53:16.888099 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 20:53:16.888777 Sending with 10 millisecond of delay
398 20:53:18.024937 => setenv autoload no
399 20:53:18.036149 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
400 20:53:18.043069 setenv autoload no
401 20:53:18.044121 Sending with 10 millisecond of delay
403 20:53:19.842726 => setenv initrd_high 0xffffffff
404 20:53:19.853505 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 20:53:19.854370 setenv initrd_high 0xffffffff
406 20:53:19.855086 Sending with 10 millisecond of delay
408 20:53:21.471152 => setenv fdt_high 0xffffffff
409 20:53:21.481893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 20:53:21.482704 setenv fdt_high 0xffffffff
411 20:53:21.483410 Sending with 10 millisecond of delay
413 20:53:21.775155 => dhcp
414 20:53:21.785865 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 20:53:21.786671 dhcp
416 20:53:21.788198 link up on port 0, speed 100, full duplex
417 20:53:21.788636 BOOTP broadcast 1
418 20:53:22.040592 BOOTP broadcast 2
419 20:53:22.542771 BOOTP broadcast 3
420 20:53:23.544783 BOOTP broadcast 4
421 20:53:25.546782 BOOTP broadcast 5
422 20:53:25.636366 DHCP client bound to address 192.168.6.23 (3845 ms)
423 20:53:25.637213 Sending with 10 millisecond of delay
425 20:53:27.313904 => setenv serverip 192.168.6.3
426 20:53:27.324746 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
427 20:53:27.325699 setenv serverip 192.168.6.3
428 20:53:27.326518 Sending with 10 millisecond of delay
430 20:53:30.809497 => tftp 0x82000000 914717/tftp-deploy-s16kyw2i/kernel/zImage
431 20:53:30.820372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
432 20:53:30.821330 tftp 0x82000000 914717/tftp-deploy-s16kyw2i/kernel/zImage
433 20:53:30.821799 link up on port 0, speed 100, full duplex
434 20:53:30.825566 Using ethernet@4a100000 device
435 20:53:31.122378 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
436 20:53:31.122976 Filename '914717/tftp-deploy-s16kyw2i/kernel/zImage'.
437 20:53:31.124933 Load address: 0x82000000
438 20:53:33.067475 Loading: *################################################## 10.9 MiB
439 20:53:33.068140 4.9 MiB/s
440 20:53:33.068606 done
441 20:53:33.071988 Bytes transferred = 11440640 (ae9200 hex)
442 20:53:33.072791 Sending with 10 millisecond of delay
444 20:53:37.518425 => tftp 0x83000000 914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot
445 20:53:37.529298 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
446 20:53:37.530320 tftp 0x83000000 914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot
447 20:53:37.530802 link up on port 0, speed 100, full duplex
448 20:53:37.534315 Using ethernet@4a100000 device
449 20:53:37.539795 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
450 20:53:37.548377 Filename '914717/tftp-deploy-s16kyw2i/ramdisk/ramdisk.cpio.gz.uboot'.
451 20:53:37.548890 Load address: 0x83000000
452 20:53:40.373930 Loading: *################################################## 14.1 MiB
453 20:53:40.374580 5 MiB/s
454 20:53:40.375049 done
455 20:53:40.378127 Bytes transferred = 14793963 (e1bceb hex)
456 20:53:40.378941 Sending with 10 millisecond of delay
458 20:53:42.236199 => setenv initrd_size ${filesize}
459 20:53:42.247006 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
460 20:53:42.247878 setenv initrd_size ${filesize}
461 20:53:42.248632 Sending with 10 millisecond of delay
463 20:53:46.393479 => tftp 0x88000000 914717/tftp-deploy-s16kyw2i/dtb/am335x-boneblack.dtb
464 20:53:46.404341 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
465 20:53:46.405293 tftp 0x88000000 914717/tftp-deploy-s16kyw2i/dtb/am335x-boneblack.dtb
466 20:53:46.405766 link up on port 0, speed 100, full duplex
467 20:53:46.409402 Using ethernet@4a100000 device
468 20:53:46.416014 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
469 20:53:46.427727 Filename '914717/tftp-deploy-s16kyw2i/dtb/am335x-boneblack.dtb'.
470 20:53:46.428542 Load address: 0x88000000
471 20:53:46.440079 Loading: *################################################## 68.9 KiB
472 20:53:46.440982 4 MiB/s
473 20:53:46.441445 done
474 20:53:46.447514 Bytes transferred = 70568 (113a8 hex)
475 20:53:46.449345 Sending with 10 millisecond of delay
477 20:53:59.628893 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 20:53:59.639959 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
479 20:53:59.641106 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 20:53:59.642003 Sending with 10 millisecond of delay
482 20:54:01.981629 => bootz 0x82000000 0x83000000 0x88000000
483 20:54:01.992448 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 20:54:01.992993 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
485 20:54:01.994017 bootz 0x82000000 0x83000000 0x88000000
486 20:54:01.994466 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
487 20:54:01.994954 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 20:54:02.000078 Image Name:
489 20:54:02.000515 Created: 2024-10-30 20:53:00 UTC
490 20:54:02.003512 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 20:54:02.009065 Data Size: 14793899 Bytes = 14.1 MiB
492 20:54:02.017477 Load Address: 00000000
493 20:54:02.018031 Entry Point: 00000000
494 20:54:02.185680 Verifying Checksum ... OK
495 20:54:02.186284 ## Flattened Device Tree blob at 88000000
496 20:54:02.192216 Booting using the fdt blob at 0x88000000
497 20:54:02.192658 Working FDT set to 88000000
498 20:54:02.197773 Using Device Tree in place at 88000000, end 880143a7
499 20:54:02.202140 Working FDT set to 88000000
500 20:54:02.215407
501 20:54:02.215845 Starting kernel ...
502 20:54:02.216256
503 20:54:02.217118 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 20:54:02.217698 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
505 20:54:02.218194 Setting prompt string to ['Linux version [0-9]']
506 20:54:02.218669 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 20:54:02.219170 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 20:54:03.056515 [ 0.000000] Booting Linux on physical CPU 0x0
509 20:54:03.062486 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
510 20:54:03.063045 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 20:54:03.063519 Setting prompt string to []
512 20:54:03.064009 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 20:54:03.064459 Using line separator: #'\n'#
514 20:54:03.064866 No login prompt set.
515 20:54:03.065293 Parsing kernel messages
516 20:54:03.065688 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 20:54:03.066551 [login-action] Waiting for messages, (timeout 00:03:58)
518 20:54:03.067004 Waiting using forced prompt support (timeout 00:01:59)
519 20:54:03.079144 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j357433-arm-gcc-12-multi-v7-defconfig-6kvtn) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Oct 30 20:18:13 UTC 2024
520 20:54:03.084896 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 20:54:03.090498 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 20:54:03.101919 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 20:54:03.107708 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 20:54:03.113430 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 20:54:03.113894 [ 0.000000] Memory policy: Data cache writeback
526 20:54:03.120073 [ 0.000000] efi: UEFI not found.
527 20:54:03.128838 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 20:54:03.129264 [ 0.000000] Zone ranges:
529 20:54:03.134621 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 20:54:03.140314 [ 0.000000] Normal empty
531 20:54:03.146081 [ 0.000000] HighMem empty
532 20:54:03.146517 [ 0.000000] Movable zone start for each node
533 20:54:03.151907 [ 0.000000] Early memory node ranges
534 20:54:03.157600 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 20:54:03.165372 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 20:54:03.190672 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 20:54:03.196255 [ 0.000000] AM335X ES2.0 (sgx neon)
538 20:54:03.207911 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
539 20:54:03.225587 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 20:54:03.237204 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 20:54:03.242876 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 20:54:03.248614 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 20:54:03.258680 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 20:54:03.287562 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 20:54:03.294038 <6>[ 0.000000] trace event string verifier disabled
546 20:54:03.294485 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 20:54:03.299243 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 20:54:03.310743 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 20:54:03.316427 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
550 20:54:03.323701 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
551 20:54:03.338700 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
552 20:54:03.355924 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
553 20:54:03.362652 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
554 20:54:03.455227 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
555 20:54:03.463855 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
556 20:54:03.476294 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
557 20:54:03.484490 <6>[ 0.019164] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
558 20:54:03.493884 <6>[ 0.034035] Console: colour dummy device 80x30
559 20:54:03.500055 Matched prompt #6: WARNING:
560 20:54:03.500698 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
561 20:54:03.505418 <3>[ 0.038930] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
562 20:54:03.511136 <3>[ 0.045999] This ensures that you still see kernel messages. Please
563 20:54:03.514390 <3>[ 0.052726] update your kernel commandline.
564 20:54:03.555025 <6>[ 0.057340] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
565 20:54:03.560776 <6>[ 0.096174] CPU: Testing write buffer coherency: ok
566 20:54:03.566687 <6>[ 0.101540] CPU0: Spectre v2: using BPIALL workaround
567 20:54:03.567129 <6>[ 0.107006] pid_max: default: 32768 minimum: 301
568 20:54:03.578149 <6>[ 0.112199] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 20:54:03.585105 <6>[ 0.120023] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
570 20:54:03.592194 <6>[ 0.129376] CPU0: thread -1, cpu 0, socket -1, mpidr 0
571 20:54:03.600578 <6>[ 0.136368] Setting up static identity map for 0x80300000 - 0x803000ac
572 20:54:03.606389 <6>[ 0.145997] rcu: Hierarchical SRCU implementation.
573 20:54:03.613178 <6>[ 0.151284] rcu: Max phase no-delay instances is 1000.
574 20:54:03.622584 <6>[ 0.162473] EFI services will not be available.
575 20:54:03.628387 <6>[ 0.167753] smp: Bringing up secondary CPUs ...
576 20:54:03.634513 <6>[ 0.172795] smp: Brought up 1 node, 1 CPU
577 20:54:03.640015 <6>[ 0.177195] SMP: Total of 1 processors activated (996.14 BogoMIPS).
578 20:54:03.645905 <6>[ 0.183965] CPU: All CPU(s) started in SVC mode.
579 20:54:03.666232 <6>[ 0.189153] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
580 20:54:03.666861 <6>[ 0.205436] devtmpfs: initialized
581 20:54:03.688944 <6>[ 0.222982] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
582 20:54:03.700442 <6>[ 0.231572] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
583 20:54:03.706387 <6>[ 0.242034] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
584 20:54:03.717152 <6>[ 0.254352] pinctrl core: initialized pinctrl subsystem
585 20:54:03.726456 <6>[ 0.265044] DMI not present or invalid.
586 20:54:03.733517 <6>[ 0.270888] NET: Registered PF_NETLINK/PF_ROUTE protocol family
587 20:54:03.744327 <6>[ 0.279840] DMA: preallocated 256 KiB pool for atomic coherent allocations
588 20:54:03.759289 <6>[ 0.291277] thermal_sys: Registered thermal governor 'step_wise'
589 20:54:03.759902 <6>[ 0.291440] cpuidle: using governor menu
590 20:54:03.786964 <6>[ 0.327047] No ATAGs?
591 20:54:03.792411 <6>[ 0.329781] hw-breakpoint: debug architecture 0x4 unsupported.
592 20:54:03.803328 <6>[ 0.341736] Serial: AMBA PL011 UART driver
593 20:54:03.835381 <6>[ 0.375437] iommu: Default domain type: Translated
594 20:54:03.844520 <6>[ 0.380786] iommu: DMA domain TLB invalidation policy: strict mode
595 20:54:03.870915 <5>[ 0.410392] SCSI subsystem initialized
596 20:54:03.876814 <6>[ 0.415269] usbcore: registered new interface driver usbfs
597 20:54:03.882536 <6>[ 0.421323] usbcore: registered new interface driver hub
598 20:54:03.891288 <6>[ 0.427106] usbcore: registered new device driver usb
599 20:54:03.897019 <6>[ 0.433598] pps_core: LinuxPPS API ver. 1 registered
600 20:54:03.902865 <6>[ 0.438986] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
601 20:54:03.910492 <6>[ 0.448718] PTP clock support registered
602 20:54:03.912905 <6>[ 0.453181] EDAC MC: Ver: 3.0.0
603 20:54:03.963180 <6>[ 0.500703] scmi_core: SCMI protocol bus registered
604 20:54:03.978572 <6>[ 0.518024] vgaarb: loaded
605 20:54:03.984682 <6>[ 0.521863] clocksource: Switched to clocksource dmtimer
606 20:54:04.027398 <6>[ 0.567269] NET: Registered PF_INET protocol family
607 20:54:04.039943 <6>[ 0.572934] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
608 20:54:04.047236 <6>[ 0.581740] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
609 20:54:04.052906 <6>[ 0.590671] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
610 20:54:04.061499 <6>[ 0.598929] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
611 20:54:04.073026 <6>[ 0.607217] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
612 20:54:04.078907 <6>[ 0.614943] TCP: Hash tables configured (established 4096 bind 4096)
613 20:54:04.084678 <6>[ 0.621876] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
614 20:54:04.090602 <6>[ 0.628887] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
615 20:54:04.099658 <6>[ 0.636494] NET: Registered PF_UNIX/PF_LOCAL protocol family
616 20:54:04.176504 <6>[ 0.710977] RPC: Registered named UNIX socket transport module.
617 20:54:04.177027 <6>[ 0.717409] RPC: Registered udp transport module.
618 20:54:04.182258 <6>[ 0.722541] RPC: Registered tcp transport module.
619 20:54:04.188003 <6>[ 0.727647] RPC: Registered tcp-with-tls transport module.
620 20:54:04.200997 <6>[ 0.733571] RPC: Registered tcp NFSv4.1 backchannel transport module.
621 20:54:04.201432 <6>[ 0.740477] PCI: CLS 0 bytes, default 64
622 20:54:04.208207 <5>[ 0.746271] Initialise system trusted keyrings
623 20:54:04.229191 <6>[ 0.766332] Trying to unpack rootfs image as initramfs...
624 20:54:04.308220 <6>[ 0.842131] workingset: timestamp_bits=30 max_order=17 bucket_order=0
625 20:54:04.313006 <6>[ 0.849636] squashfs: version 4.0 (2009/01/31) Phillip Lougher
626 20:54:04.352714 <5>[ 0.892820] NFS: Registering the id_resolver key type
627 20:54:04.358539 <5>[ 0.898419] Key type id_resolver registered
628 20:54:04.364323 <5>[ 0.903113] Key type id_legacy registered
629 20:54:04.370088 <6>[ 0.907562] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
630 20:54:04.379712 <6>[ 0.914766] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
631 20:54:04.452282 <5>[ 0.992355] Key type asymmetric registered
632 20:54:04.458063 <5>[ 0.996877] Asymmetric key parser 'x509' registered
633 20:54:04.466471 <6>[ 1.002362] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
634 20:54:04.472247 <6>[ 1.010248] io scheduler mq-deadline registered
635 20:54:04.481010 <6>[ 1.015226] io scheduler kyber registered
636 20:54:04.481609 <6>[ 1.019681] io scheduler bfq registered
637 20:54:04.581878 <6>[ 1.118285] ledtrig-cpu: registered to indicate activity on CPUs
638 20:54:04.866987 <6>[ 1.403230] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
639 20:54:04.897453 <6>[ 1.437172] msm_serial: driver initialized
640 20:54:04.903302 <6>[ 1.442188] SuperH (H)SCI(F) driver initialized
641 20:54:04.909251 <6>[ 1.447316] STMicroelectronics ASC driver initialized
642 20:54:04.914486 <6>[ 1.452999] STM32 USART driver initialized
643 20:54:05.050626 <6>[ 1.590113] brd: module loaded
644 20:54:05.087636 <6>[ 1.627075] loop: module loaded
645 20:54:05.133751 <6>[ 1.673321] CAN device driver interface
646 20:54:05.140456 <6>[ 1.678296] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
647 20:54:05.146162 <6>[ 1.685348] e1000e: Intel(R) PRO/1000 Network Driver
648 20:54:05.152009 <6>[ 1.690734] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
649 20:54:05.157753 <6>[ 1.697196] igb: Intel(R) Gigabit Ethernet Network Driver
650 20:54:05.166055 <6>[ 1.703044] igb: Copyright (c) 2007-2014 Intel Corporation.
651 20:54:05.177832 <6>[ 1.712336] pegasus: Pegasus/Pegasus II USB Ethernet driver
652 20:54:05.183661 <6>[ 1.718400] usbcore: registered new interface driver pegasus
653 20:54:05.189411 <6>[ 1.724586] usbcore: registered new interface driver asix
654 20:54:05.195198 <6>[ 1.730440] usbcore: registered new interface driver ax88179_178a
655 20:54:05.201013 <6>[ 1.737036] usbcore: registered new interface driver cdc_ether
656 20:54:05.206760 <6>[ 1.743356] usbcore: registered new interface driver smsc75xx
657 20:54:05.212545 <6>[ 1.749565] usbcore: registered new interface driver smsc95xx
658 20:54:05.218337 <6>[ 1.755808] usbcore: registered new interface driver net1080
659 20:54:05.224089 <6>[ 1.761949] usbcore: registered new interface driver cdc_subset
660 20:54:05.229901 <6>[ 1.768338] usbcore: registered new interface driver zaurus
661 20:54:05.237542 <6>[ 1.774406] usbcore: registered new interface driver cdc_ncm
662 20:54:05.247478 <6>[ 1.783978] usbcore: registered new interface driver usb-storage
663 20:54:05.519499 <6>[ 2.057673] i2c_dev: i2c /dev entries driver
664 20:54:05.586240 <5>[ 2.118385] cpuidle: enable-method property 'ti,am3352' found operations
665 20:54:05.592082 <6>[ 2.128011] sdhci: Secure Digital Host Controller Interface driver
666 20:54:05.599446 <6>[ 2.134782] sdhci: Copyright(c) Pierre Ossman
667 20:54:05.606682 <6>[ 2.141167] Synopsys Designware Multimedia Card Interface Driver
668 20:54:05.612165 <6>[ 2.149112] sdhci-pltfm: SDHCI platform and OF driver helper
669 20:54:05.720554 <6>[ 2.253330] usbcore: registered new interface driver usbhid
670 20:54:05.721311 <6>[ 2.259368] usbhid: USB HID core driver
671 20:54:05.781027 <6>[ 2.318579] NET: Registered PF_INET6 protocol family
672 20:54:05.812740 <6>[ 2.352972] Segment Routing with IPv6
673 20:54:05.818544 <6>[ 2.357126] In-situ OAM (IOAM) with IPv6
674 20:54:05.825316 <6>[ 2.361523] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
675 20:54:05.832704 <6>[ 2.368893] NET: Registered PF_PACKET protocol family
676 20:54:05.838586 <6>[ 2.374456] can: controller area network core
677 20:54:05.839175 <6>[ 2.379281] NET: Registered PF_CAN protocol family
678 20:54:05.844370 <6>[ 2.384508] can: raw protocol
679 20:54:05.847192 <6>[ 2.387837] can: broadcast manager protocol
680 20:54:05.853682 <6>[ 2.392434] can: netlink gateway - max_hops=1
681 20:54:05.859865 <5>[ 2.397943] Key type dns_resolver registered
682 20:54:05.865621 <6>[ 2.403045] ThumbEE CPU extension supported.
683 20:54:05.871900 <5>[ 2.407743] Registering SWP/SWPB emulation handler
684 20:54:05.877254 <3>[ 2.413437] omap_voltage_late_init: Voltage driver support not added
685 20:54:06.085155 <5>[ 2.622861] Loading compiled-in X.509 certificates
686 20:54:06.213755 <6>[ 2.741022] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
687 20:54:06.220913 <6>[ 2.757688] pinctrl-single 44e10800.pinmux: 142 pins, size 568
688 20:54:06.246425 <3>[ 2.781379] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
689 20:54:06.466935 <3>[ 3.001082] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
690 20:54:06.664635 <6>[ 3.203080] OMAP GPIO hardware version 0.1
691 20:54:06.685261 <6>[ 3.221700] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
692 20:54:06.769800 <4>[ 3.306011] at24 2-0054: supply vcc not found, using dummy regulator
693 20:54:06.812341 <4>[ 3.348540] at24 2-0055: supply vcc not found, using dummy regulator
694 20:54:06.850971 <4>[ 3.387447] at24 2-0056: supply vcc not found, using dummy regulator
695 20:54:06.889155 <4>[ 3.425372] at24 2-0057: supply vcc not found, using dummy regulator
696 20:54:06.929466 <6>[ 3.466520] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
697 20:54:06.985152 <3>[ 3.518092] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
698 20:54:07.009625 <6>[ 3.538883] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 20:54:07.029536 <4>[ 3.565284] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
700 20:54:07.057427 <4>[ 3.592371] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
701 20:54:07.166073 <6>[ 3.702424] omap_rng 48310000.rng: Random Number Generator ver. 20
702 20:54:07.189524 <5>[ 3.728731] random: crng init done
703 20:54:07.240443 <6>[ 3.780487] Freeing initrd memory: 14448K
704 20:54:07.250268 <6>[ 3.785150] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
705 20:54:07.300418 <6>[ 3.834347] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
706 20:54:07.306226 <6>[ 3.844696] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
707 20:54:07.317978 <6>[ 3.852052] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
708 20:54:07.323760 <6>[ 3.859501] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
709 20:54:07.335314 <6>[ 3.867641] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
710 20:54:07.342688 <6>[ 3.879276] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
711 20:54:07.355855 <5>[ 3.888310] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
712 20:54:07.383636 <3>[ 3.918084] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
713 20:54:07.389418 <6>[ 3.926688] edma 49000000.dma: TI EDMA DMA engine driver
714 20:54:07.460538 <3>[ 3.994312] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
715 20:54:07.475251 <6>[ 4.008681] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
716 20:54:07.488152 <3>[ 4.025774] l3-aon-clkctrl:0000:0: failed to disable
717 20:54:07.541522 <6>[ 4.075925] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
718 20:54:07.547161 <6>[ 4.085427] printk: legacy console [ttyS0] enabled
719 20:54:07.552873 <6>[ 4.085427] printk: legacy console [ttyS0] enabled
720 20:54:07.558536 <6>[ 4.095763] printk: legacy bootconsole [omap8250] disabled
721 20:54:07.564414 <6>[ 4.095763] printk: legacy bootconsole [omap8250] disabled
722 20:54:07.599264 <4>[ 4.132667] tps65217-pmic: Failed to locate of_node [id: -1]
723 20:54:07.602841 <4>[ 4.140084] tps65217-bl: Failed to locate of_node [id: -1]
724 20:54:07.619165 <6>[ 4.159651] tps65217 0-0024: TPS65217 ID 0xe version 1.2
725 20:54:07.637621 <6>[ 4.166605] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
726 20:54:07.649412 <6>[ 4.180285] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
727 20:54:07.654977 <6>[ 4.192167] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
728 20:54:07.677121 <6>[ 4.212026] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
729 20:54:07.683021 <6>[ 4.221083] sdhci-omap 48060000.mmc: Got CD GPIO
730 20:54:07.691072 <4>[ 4.226269] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
731 20:54:07.705833 <4>[ 4.239854] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
732 20:54:07.712131 <4>[ 4.248594] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
733 20:54:07.722027 <4>[ 4.257177] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
734 20:54:07.820808 <6>[ 4.356653] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
735 20:54:07.868365 <6>[ 4.402667] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 20:54:07.874835 <6>[ 4.411315] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
737 20:54:07.883996 <6>[ 4.420248] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
738 20:54:07.936784 <6>[ 4.473972] mmc0: new high speed SDHC card at address 0001
739 20:54:07.945179 <6>[ 4.483537] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
740 20:54:07.954237 <6>[ 4.494435] mmcblk0: p1
741 20:54:07.971552 <6>[ 4.503718] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 20:54:07.993661 <6>[ 4.525986] mmc1: new high speed MMC card at address 0001
743 20:54:07.994133 <6>[ 4.532869] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
744 20:54:08.002081 <6>[ 4.541704] mmcblk1:
745 20:54:08.010380 <6>[ 4.545089] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
746 20:54:08.018408 <6>[ 4.552979] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
747 20:54:08.023930 <6>[ 4.560519] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
748 20:54:10.068619 <6>[ 6.602923] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
749 20:54:10.181950 <5>[ 6.642062] Sending DHCP requests ., OK
750 20:54:10.193350 <6>[ 6.726418] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
751 20:54:10.193862 <6>[ 6.734586] IP-Config: Complete:
752 20:54:10.207431 <6>[ 6.738128] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
753 20:54:10.213083 <6>[ 6.748655] host=192.168.6.23, domain=, nis-domain=(none)
754 20:54:10.216384 <6>[ 6.754869] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
755 20:54:10.223073 <6>[ 6.754905] nameserver0=10.255.253.1
756 20:54:10.229192 <6>[ 6.767488] clk: Disabling unused clocks
757 20:54:10.234555 <6>[ 6.772211] PM: genpd: Disabling unused power domains
758 20:54:10.253502 <6>[ 6.790374] Freeing unused kernel image (initmem) memory: 2048K
759 20:54:10.261010 <6>[ 6.800130] Run /init as init process
760 20:54:10.286021 Loading, please wait...
761 20:54:10.362650 Starting systemd-udevd version 252.22-1~deb12u1
762 20:54:13.370792 <4>[ 9.903869] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 20:54:13.590389 <4>[ 10.123425] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
764 20:54:13.723045 <6>[ 10.263499] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
765 20:54:13.733666 <6>[ 10.269174] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
766 20:54:13.945776 <6>[ 10.484696] hub 1-0:1.0: USB hub found
767 20:54:13.971775 <6>[ 10.510574] hub 1-0:1.0: 1 port detected
768 20:54:14.057607 <6>[ 10.596250] tda998x 0-0070: found TDA19988
769 20:54:17.366604 Begin: Loading essential drivers ... done.
770 20:54:17.373006 Begin: Running /scripts/init-premount ... done.
771 20:54:17.381323 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
772 20:54:17.386858 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
773 20:54:17.391241 Device /sys/class/net/eth0 found
774 20:54:17.391725 done.
775 20:54:17.466331 Begin: Waiting up to 180 secs for any network device to become available ... done.
776 20:54:17.564664 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
777 20:54:17.732955 IP-Config: eth0 guessed broadcast address 192.168.6.255
778 20:54:17.738545 IP-Config: eth0 complete (dhcp from 192.168.6.1):
779 20:54:17.744138 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
780 20:54:17.753017 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
781 20:54:17.758512 rootserver: 192.168.6.1 rootpath:
782 20:54:17.759023 filename :
783 20:54:17.832303 done.
784 20:54:17.840752 Begin: Running /scripts/nfs-bottom ... done.
785 20:54:17.904195 Begin: Running /scripts/init-bottom ... done.
786 20:54:19.322380 <30>[ 15.858634] systemd[1]: System time before build time, advancing clock.
787 20:54:19.483149 <30>[ 15.993350] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
788 20:54:19.492442 <30>[ 16.030507] systemd[1]: Detected architecture arm.
789 20:54:19.507293
790 20:54:19.507857 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
791 20:54:19.508323
792 20:54:19.535333 <30>[ 16.072369] systemd[1]: Hostname set to <debian-bookworm-armhf>.
793 20:54:21.741220 <30>[ 18.277152] systemd[1]: Queued start job for default target graphical.target.
794 20:54:21.758205 <30>[ 18.292201] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
795 20:54:21.765879 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
796 20:54:21.791553 <30>[ 18.324251] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
797 20:54:21.798921 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
798 20:54:21.823908 <30>[ 18.358048] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
799 20:54:21.836935 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
800 20:54:21.859165 <30>[ 18.393735] systemd[1]: Created slice user.slice - User and Session Slice.
801 20:54:21.865941 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
802 20:54:21.894711 <30>[ 18.423282] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
803 20:54:21.900854 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
804 20:54:21.918781 <30>[ 18.453069] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
805 20:54:21.929872 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
806 20:54:21.959207 <30>[ 18.482666] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
807 20:54:21.965631 <30>[ 18.503058] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
808 20:54:21.974139 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
809 20:54:21.997852 <30>[ 18.532360] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
810 20:54:22.006152 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
811 20:54:22.028561 <30>[ 18.562766] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
812 20:54:22.037037 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
813 20:54:22.058181 <30>[ 18.592772] systemd[1]: Reached target paths.target - Path Units.
814 20:54:22.063366 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
815 20:54:22.087941 <30>[ 18.622508] systemd[1]: Reached target remote-fs.target - Remote File Systems.
816 20:54:22.095367 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
817 20:54:22.117838 <30>[ 18.652385] systemd[1]: Reached target slices.target - Slice Units.
818 20:54:22.123339 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
819 20:54:22.148057 <30>[ 18.682641] systemd[1]: Reached target swap.target - Swaps.
820 20:54:22.152174 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
821 20:54:22.178233 <30>[ 18.712630] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
822 20:54:22.187176 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
823 20:54:22.209195 <30>[ 18.743473] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
824 20:54:22.217486 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
825 20:54:22.296131 <30>[ 18.825636] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
826 20:54:22.308707 <30>[ 18.843063] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
827 20:54:22.317162 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
828 20:54:22.341092 <30>[ 18.874617] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
829 20:54:22.348579 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
830 20:54:22.370760 <30>[ 18.905086] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
831 20:54:22.378986 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
832 20:54:22.403666 <30>[ 18.936899] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
833 20:54:22.409328 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
834 20:54:22.440471 <30>[ 18.973479] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
835 20:54:22.447106 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
836 20:54:22.474284 <30>[ 19.003681] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
837 20:54:22.493031 <30>[ 19.022286] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
838 20:54:22.541216 <30>[ 19.077395] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
839 20:54:22.572160 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
840 20:54:22.630624 <30>[ 19.166626] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
841 20:54:22.650999 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
842 20:54:22.707894 <30>[ 19.243002] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
843 20:54:22.737920 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
844 20:54:22.790768 <30>[ 19.325548] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
845 20:54:22.818158 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
846 20:54:22.869142 <30>[ 19.405216] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
847 20:54:22.895827 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
848 20:54:22.946657 <30>[ 19.483179] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
849 20:54:22.968146 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
850 20:54:23.027669 <30>[ 19.562973] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
851 20:54:23.046807 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
852 20:54:23.106770 <30>[ 19.643092] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
853 20:54:23.126025 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
854 20:54:23.162669 <30>[ 19.698164] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
855 20:54:23.181413 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
856 20:54:23.214680 <28>[ 19.744228] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
857 20:54:23.223222 <28>[ 19.757809] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
858 20:54:23.266476 <30>[ 19.803285] systemd[1]: Starting systemd-journald.service - Journal Service...
859 20:54:23.277671 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
860 20:54:23.359168 <30>[ 19.895268] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
861 20:54:23.376544 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
862 20:54:23.403223 <30>[ 19.938686] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
863 20:54:23.446966 Starting [0;1;39msystemd-network-g… units from Kernel command line...
864 20:54:23.494272 <30>[ 20.028607] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
865 20:54:23.548176 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
866 20:54:23.611805 <30>[ 20.147509] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
867 20:54:23.677937 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
868 20:54:23.746831 <30>[ 20.283301] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
869 20:54:23.810398 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
870 20:54:23.816799 <30>[ 20.354112] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
871 20:54:23.856668 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
872 20:54:23.882127 <30>[ 20.416519] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
873 20:54:23.915560 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
874 20:54:24.061040 <30>[ 20.597153] systemd[1]: modprobe@configfs.service: Deactivated successfully.
875 20:54:24.098547 <30>[ 20.633531] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
876 20:54:24.127664 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
877 20:54:24.148339 <30>[ 20.684654] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
878 20:54:24.187596 <30>[ 20.722300] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
879 20:54:24.196084 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
880 20:54:24.218977 <30>[ 20.753719] systemd[1]: Started systemd-journald.service - Journal Service.
881 20:54:24.225898 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
882 20:54:24.259794 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
883 20:54:24.288151 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
884 20:54:24.317892 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
885 20:54:24.352308 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
886 20:54:24.380496 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
887 20:54:24.408009 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
888 20:54:24.437952 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
889 20:54:24.467781 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
890 20:54:24.521018 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
891 20:54:24.563770 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
892 20:54:24.628666 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
893 20:54:24.697879 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
894 20:54:24.761184 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
895 20:54:24.912513 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
896 20:54:24.931157 <46>[ 21.467498] systemd-journald[163]: Received client request to flush runtime journal.
897 20:54:25.097961 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
898 20:54:25.200073 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
899 20:54:26.231953 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
900 20:54:26.290211 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
901 20:54:26.686854 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
902 20:54:26.839425 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
903 20:54:26.858879 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
904 20:54:26.887141 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
905 20:54:26.959567 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
906 20:54:27.006760 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
907 20:54:27.940475 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
908 20:54:28.009428 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
909 20:54:28.087999 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
910 20:54:28.150167 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
911 20:54:28.206899 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
912 20:54:29.408882 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
913 20:54:30.827039 <5>[ 27.362913] cfg80211: Loading compiled-in X.509 certificates for regulatory database
914 20:54:30.867871 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
915 20:54:31.633749 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
916 20:54:32.392341 <5>[ 28.930373] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
917 20:54:32.423925 <5>[ 28.958129] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
918 20:54:32.429758 <4>[ 28.967305] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
919 20:54:32.437489 <6>[ 28.976402] cfg80211: failed to load regulatory.db
920 20:54:32.700284 <46>[ 29.227133] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 20:54:32.849740 <46>[ 29.378699] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
922 20:54:32.865035 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
923 20:54:33.669038 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
924 20:54:42.051282 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
925 20:54:42.077546 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
926 20:54:42.101645 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
927 20:54:42.128639 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
928 20:54:42.207213 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
929 20:54:42.249894 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
930 20:54:42.318121 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
931 20:54:42.351179 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
932 20:54:42.405164 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
933 20:54:42.432537 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
934 20:54:42.464378 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
935 20:54:42.495172 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
936 20:54:42.524596 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
937 20:54:42.560098 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
938 20:54:42.593311 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
939 20:54:42.619949 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
940 20:54:42.657596 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
941 20:54:42.681790 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
942 20:54:42.709217 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
943 20:54:42.730134 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
944 20:54:42.778591 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
945 20:54:42.795692 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
946 20:54:42.820097 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
947 20:54:42.898058 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
948 20:54:42.939414 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
949 20:54:43.008294 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
950 20:54:43.089157 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
951 20:54:43.170671 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
952 20:54:43.213255 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
953 20:54:43.256480 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
954 20:54:43.421687 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
955 20:54:43.479875 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
956 20:54:43.548691 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
957 20:54:43.566589 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
958 20:54:43.628758 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
959 20:54:43.845235 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
960 20:54:44.205583 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
961 20:54:44.257448 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
962 20:54:44.283020 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
963 20:54:44.360077 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
964 20:54:44.544524 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
965 20:54:44.681928
966 20:54:44.685657 Debian GNU/Linux 12 debian-rm-armhf login: root (automatic login)
967 20:54:44.686192
968 20:54:44.975206 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Wed Oct 30 20:18:13 UTC 2024 armv7l
969 20:54:44.975641
970 20:54:44.980818 The programs included with the Debian GNU/Linux system are free software;
971 20:54:44.986431 the exact distribution terms for each program are described in the
972 20:54:44.991972 individual files in /usr/share/doc/*/copyright.
973 20:54:44.992609
974 20:54:45.000011 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
975 20:54:45.000477 permitted by applicable law.
976 20:54:49.721757 Unable to match end of the kernel message
978 20:54:49.723980 Setting prompt string to ['/ #']
979 20:54:49.724768 end: 2.4.4.1 login-action (duration 00:00:47) [common]
981 20:54:49.726749 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
982 20:54:49.727549 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
983 20:54:49.728244 Setting prompt string to ['/ #']
984 20:54:49.728854 Forcing a shell prompt, looking for ['/ #']
986 20:54:49.780254 / #
987 20:54:49.781097 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
988 20:54:49.781702 Waiting using forced prompt support (timeout 00:02:30)
989 20:54:49.785898
990 20:54:49.792457 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
991 20:54:49.793212 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
992 20:54:49.793910 Sending with 10 millisecond of delay
994 20:54:54.784297 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y'
995 20:54:54.795195 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/914717/extract-nfsrootfs-w1kmp32y'
996 20:54:54.796213 Sending with 10 millisecond of delay
998 20:54:56.894087 / # export NFS_SERVER_IP='192.168.6.3'
999 20:54:56.904997 export NFS_SERVER_IP='192.168.6.3'
1000 20:54:56.906099 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1001 20:54:56.906686 end: 2.4 uboot-commands (duration 00:01:56) [common]
1002 20:54:56.907262 end: 2 uboot-action (duration 00:01:56) [common]
1003 20:54:56.907826 start: 3 lava-test-retry (timeout 00:06:54) [common]
1004 20:54:56.908401 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
1005 20:54:56.908863 Using namespace: common
1007 20:54:57.010023 / # #
1008 20:54:57.010651 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1009 20:54:57.014612 #
1010 20:54:57.021723 Using /lava-914717
1012 20:54:57.122895 / # export SHELL=/bin/bash
1013 20:54:57.127306 export SHELL=/bin/bash
1015 20:54:57.234951 / # . /lava-914717/environment
1016 20:54:57.240351 . /lava-914717/environment
1018 20:54:57.353171 / # /lava-914717/bin/lava-test-runner /lava-914717/0
1019 20:54:57.353790 Test shell timeout: 10s (minimum of the action and connection timeout)
1020 20:54:57.358615 /lava-914717/bin/lava-test-runner /lava-914717/0
1021 20:54:57.738522 + export TESTRUN_ID=0_timesync-off
1022 20:54:57.746415 + TESTRUN_ID=0_timesync-off
1023 20:54:57.746870 + cd /lava-914717/0/tests/0_timesync-off
1024 20:54:57.747294 ++ cat uuid
1025 20:54:57.762480 + UUID=914717_1.6.2.4.1
1026 20:54:57.762921 + set +x
1027 20:54:57.770944 <LAVA_SIGNAL_STARTRUN 0_timesync-off 914717_1.6.2.4.1>
1028 20:54:57.771391 + systemctl stop systemd-timesyncd
1029 20:54:57.772089 Received signal: <STARTRUN> 0_timesync-off 914717_1.6.2.4.1
1030 20:54:57.772527 Starting test lava.0_timesync-off (914717_1.6.2.4.1)
1031 20:54:57.773047 Skipping test definition patterns.
1032 20:54:58.051692 + set +x
1033 20:54:58.052283 <LAVA_SIGNAL_ENDRUN 0_timesync-off 914717_1.6.2.4.1>
1034 20:54:58.052975 Received signal: <ENDRUN> 0_timesync-off 914717_1.6.2.4.1
1035 20:54:58.053479 Ending use of test pattern.
1036 20:54:58.053939 Ending test lava.0_timesync-off (914717_1.6.2.4.1), duration 0.28
1038 20:54:58.277295 + export TESTRUN_ID=1_kselftest-dt
1039 20:54:58.285085 + TESTRUN_ID=1_kselftest-dt
1040 20:54:58.285540 + cd /lava-914717/0/tests/1_kselftest-dt
1041 20:54:58.285990 ++ cat uuid
1042 20:54:58.301062 + UUID=914717_1.6.2.4.5
1043 20:54:58.301506 + set +x
1044 20:54:58.306552 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 914717_1.6.2.4.5>
1045 20:54:58.306990 + cd ./automated/linux/kselftest/
1046 20:54:58.307653 Received signal: <STARTRUN> 1_kselftest-dt 914717_1.6.2.4.5
1047 20:54:58.308074 Starting test lava.1_kselftest-dt (914717_1.6.2.4.5)
1048 20:54:58.308557 Skipping test definition patterns.
1049 20:54:58.334772 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1050 20:54:58.443771 INFO: install_deps skipped
1051 20:54:59.039207 --2024-10-30 20:54:59-- http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1052 20:54:59.069032 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1053 20:54:59.206990 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1054 20:54:59.343326 HTTP request sent, awaiting response... 200 OK
1055 20:54:59.343817 Length: 4111596 (3.9M) [application/octet-stream]
1056 20:54:59.349009 Saving to: 'kselftest_armhf.tar.gz'
1057 20:54:59.349445
1058 20:55:01.103963
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 186KB/s
kselftest_armhf.tar 5%[> ] 213.48K 398KB/s
kselftest_armhf.tar 20%[===> ] 823.79K 876KB/s
kselftest_armhf.tar 59%[==========> ] 2.32M 1.91MB/s
kselftest_armhf.tar 72%[=============> ] 2.86M 1.93MB/s
kselftest_armhf.tar 99%[==================> ] 3.92M 2.28MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.24MB/s in 1.8s
1059 20:55:01.104602
1060 20:55:01.738876 2024-10-30 20:55:01 (2.24 MB/s) - 'kselftest_armhf.tar.gz' saved [4111596/4111596]
1061 20:55:01.739469
1062 20:55:15.917513 skiplist:
1063 20:55:15.918227 ========================================
1064 20:55:15.923269 ========================================
1065 20:55:16.036055 dt:test_unprobed_devices.sh
1066 20:55:16.069272 ============== Tests to run ===============
1067 20:55:16.077136 dt:test_unprobed_devices.sh
1068 20:55:16.081126 ===========End Tests to run ===============
1069 20:55:16.092637 shardfile-dt pass
1070 20:55:16.327825 <12>[ 72.868611] kselftest: Running tests in dt
1071 20:55:16.355901 TAP version 13
1072 20:55:16.380351 1..1
1073 20:55:16.434506 # timeout set to 45
1074 20:55:16.435008 # selftests: dt: test_unprobed_devices.sh
1075 20:55:17.274696 # TAP version 13
1076 20:55:42.168249 # 1..257
1077 20:55:42.340740 # ok 1 / # SKIP
1078 20:55:42.367091 # ok 2 /clk_mcasp0
1079 20:55:42.432695 # ok 3 /clk_mcasp0_fixed # SKIP
1080 20:55:42.503201 # ok 4 /cpus/cpu@0 # SKIP
1081 20:55:42.578789 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1082 20:55:42.593882 # ok 6 /fixedregulator0
1083 20:55:42.617152 # ok 7 /leds
1084 20:55:42.636925 # ok 8 /ocp
1085 20:55:42.665286 # ok 9 /ocp/interconnect@44c00000
1086 20:55:42.688599 # ok 10 /ocp/interconnect@44c00000/segment@0
1087 20:55:42.707405 # ok 11 /ocp/interconnect@44c00000/segment@100000
1088 20:55:42.734741 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1089 20:55:42.801742 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1090 20:55:42.823195 # ok 14 /ocp/interconnect@44c00000/segment@200000
1091 20:55:42.851424 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1092 20:55:42.952023 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1093 20:55:43.024455 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1094 20:55:43.096840 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1095 20:55:43.169414 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1096 20:55:43.240493 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1097 20:55:43.311883 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1098 20:55:43.383574 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1099 20:55:43.458085 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1100 20:55:43.526590 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1101 20:55:43.597679 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1102 20:55:43.667471 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1103 20:55:43.738943 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1104 20:55:43.811154 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1105 20:55:43.882315 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1106 20:55:43.953945 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1107 20:55:44.024484 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1108 20:55:44.095800 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1109 20:55:44.168051 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1110 20:55:44.238606 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1111 20:55:44.310514 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1112 20:55:44.380920 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1113 20:55:44.454378 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1114 20:55:44.525065 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1115 20:55:44.597347 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1116 20:55:44.668933 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1117 20:55:44.740644 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1118 20:55:44.812873 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1119 20:55:44.883721 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1120 20:55:44.956797 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1121 20:55:45.029499 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1122 20:55:45.101269 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1123 20:55:45.172527 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1124 20:55:45.244786 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1125 20:55:45.316583 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1126 20:55:45.392090 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1127 20:55:45.463500 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1128 20:55:45.535151 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1129 20:55:45.603467 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1130 20:55:45.682203 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1131 20:55:45.750243 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1132 20:55:45.821904 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1133 20:55:45.893521 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1134 20:55:45.966120 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1135 20:55:46.036461 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1136 20:55:46.109794 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1137 20:55:46.181755 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1138 20:55:46.253624 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1139 20:55:46.330066 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1140 20:55:46.397748 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1141 20:55:46.472434 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1142 20:55:46.541172 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1143 20:55:46.613292 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1144 20:55:46.686927 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1145 20:55:46.754432 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1146 20:55:46.832928 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1147 20:55:46.904980 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1148 20:55:46.976941 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1149 20:55:47.048803 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1150 20:55:47.120624 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1151 20:55:47.191500 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1152 20:55:47.264002 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1153 20:55:47.337446 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1154 20:55:47.408342 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1155 20:55:47.479131 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1156 20:55:47.551861 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1157 20:55:47.623045 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1158 20:55:47.699483 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1159 20:55:47.766947 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1160 20:55:47.838259 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1161 20:55:47.909853 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1162 20:55:47.980289 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1163 20:55:48.053520 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1164 20:55:48.125172 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1165 20:55:48.204252 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1166 20:55:48.276298 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1167 20:55:48.341295 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1168 20:55:48.417267 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1169 20:55:48.487101 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1170 20:55:48.560095 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1171 20:55:48.580431 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1172 20:55:48.604670 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1173 20:55:48.628570 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1174 20:55:48.652127 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1175 20:55:48.680253 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1176 20:55:48.702334 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1177 20:55:48.728541 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1178 20:55:48.751115 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1179 20:55:48.855875 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1180 20:55:48.876569 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1181 20:55:48.901373 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1182 20:55:48.929580 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1183 20:55:49.033707 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1184 20:55:49.103815 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1185 20:55:49.178198 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1186 20:55:49.253323 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1187 20:55:49.325778 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1188 20:55:49.395025 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1189 20:55:49.467077 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1190 20:55:49.538726 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1191 20:55:49.609406 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1192 20:55:49.682559 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1193 20:55:49.754729 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1194 20:55:49.834761 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1195 20:55:49.899429 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1196 20:55:49.973640 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1197 20:55:50.046052 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1198 20:55:50.118773 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1199 20:55:50.140002 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1200 20:55:50.209633 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1201 20:55:50.278570 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1202 20:55:50.350966 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1203 20:55:50.377578 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1204 20:55:50.448372 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1205 20:55:50.471641 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1206 20:55:50.538473 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1207 20:55:50.560602 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1208 20:55:50.585283 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1209 20:55:50.607859 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1210 20:55:50.634722 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1211 20:55:50.659550 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1212 20:55:50.682089 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1213 20:55:50.707551 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1214 20:55:50.781879 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1215 20:55:50.809245 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1216 20:55:50.826616 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1217 20:55:50.898645 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1218 20:55:50.969554 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1219 20:55:50.989843 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1220 20:55:51.094912 # not ok 144 /ocp/interconnect@47c00000
1221 20:55:51.162298 # not ok 145 /ocp/interconnect@47c00000/segment@0
1222 20:55:51.187411 # ok 146 /ocp/interconnect@48000000
1223 20:55:51.213302 # ok 147 /ocp/interconnect@48000000/segment@0
1224 20:55:51.230671 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1225 20:55:51.258699 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1226 20:55:51.280597 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1227 20:55:51.302072 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1228 20:55:51.325042 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1229 20:55:51.351012 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1230 20:55:51.376137 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1231 20:55:51.442363 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1232 20:55:51.518552 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1233 20:55:51.540730 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1234 20:55:51.560402 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1235 20:55:51.587313 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1236 20:55:51.611664 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1237 20:55:51.629393 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1238 20:55:51.657122 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1239 20:55:51.680444 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1240 20:55:51.701106 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1241 20:55:51.722948 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1242 20:55:51.746983 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1243 20:55:51.770283 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1244 20:55:51.798116 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1245 20:55:51.820719 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1246 20:55:51.841582 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1247 20:55:51.867652 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1248 20:55:51.892003 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1249 20:55:51.909838 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1250 20:55:51.934694 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1251 20:55:51.954784 # ok 175 /ocp/interconnect@48000000/segment@100000
1252 20:55:51.979518 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1253 20:55:52.003325 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1254 20:55:52.080475 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1255 20:55:52.153402 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1256 20:55:52.222525 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1257 20:55:52.295202 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1258 20:55:52.360417 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1259 20:55:52.433760 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1260 20:55:52.503763 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1261 20:55:52.576516 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1262 20:55:52.596876 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1263 20:55:52.620117 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1264 20:55:52.644694 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1265 20:55:52.671507 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1266 20:55:52.698669 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1267 20:55:52.716998 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1268 20:55:52.741574 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1269 20:55:52.768496 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1270 20:55:52.790851 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1271 20:55:52.811659 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1272 20:55:52.838076 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1273 20:55:52.862055 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1274 20:55:52.877118 # ok 198 /ocp/interconnect@48000000/segment@200000
1275 20:55:52.902295 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1276 20:55:52.974883 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1277 20:55:52.999033 # ok 201 /ocp/interconnect@48000000/segment@300000
1278 20:55:53.021297 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1279 20:55:53.047588 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1280 20:55:53.071638 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1281 20:55:53.089748 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1282 20:55:53.117408 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1283 20:55:53.140753 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1284 20:55:53.206773 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1285 20:55:53.228448 # ok 209 /ocp/interconnect@4a000000
1286 20:55:53.255179 # ok 210 /ocp/interconnect@4a000000/segment@0
1287 20:55:53.276263 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1288 20:55:53.301941 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1289 20:55:53.328604 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1290 20:55:53.350926 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1291 20:55:53.421574 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1292 20:55:53.526753 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1293 20:55:53.594235 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1294 20:55:53.697169 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1295 20:55:53.769111 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1296 20:55:53.840416 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1297 20:55:53.940321 # not ok 221 /ocp/interconnect@4b140000
1298 20:55:54.008914 # not ok 222 /ocp/interconnect@4b140000/segment@0
1299 20:55:54.080506 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1300 20:55:54.105913 # ok 224 /ocp/target-module@40300000
1301 20:55:54.124749 # ok 225 /ocp/target-module@40300000/sram@0
1302 20:55:54.200230 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1303 20:55:54.269671 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1304 20:55:54.293882 # ok 228 /ocp/target-module@47400000
1305 20:55:54.314713 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1306 20:55:54.339692 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1307 20:55:54.363699 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1308 20:55:54.386686 # ok 232 /ocp/target-module@47400000/usb@1400
1309 20:55:54.409332 # ok 233 /ocp/target-module@47400000/usb@1800
1310 20:55:54.427579 # ok 234 /ocp/target-module@47810000
1311 20:55:54.454215 # ok 235 /ocp/target-module@49000000
1312 20:55:54.477235 # ok 236 /ocp/target-module@49000000/dma@0
1313 20:55:54.497803 # ok 237 /ocp/target-module@49800000
1314 20:55:54.517805 # ok 238 /ocp/target-module@49800000/dma@0
1315 20:55:54.539387 # ok 239 /ocp/target-module@49900000
1316 20:55:54.562874 # ok 240 /ocp/target-module@49900000/dma@0
1317 20:55:54.584441 # ok 241 /ocp/target-module@49a00000
1318 20:55:54.607562 # ok 242 /ocp/target-module@49a00000/dma@0
1319 20:55:54.629035 # ok 243 /ocp/target-module@4c000000
1320 20:55:54.700243 # not ok 244 /ocp/target-module@4c000000/emif@0
1321 20:55:54.726067 # ok 245 /ocp/target-module@50000000
1322 20:55:54.748587 # ok 246 /ocp/target-module@53100000
1323 20:55:54.815246 # not ok 247 /ocp/target-module@53100000/sham@0
1324 20:55:54.838522 # ok 248 /ocp/target-module@53500000
1325 20:55:54.907781 # not ok 249 /ocp/target-module@53500000/aes@0
1326 20:55:54.933724 # ok 250 /ocp/target-module@56000000
1327 20:55:55.034730 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1328 20:55:55.106138 # ok 252 /opp-table # SKIP
1329 20:55:55.171397 # ok 253 /soc # SKIP
1330 20:55:55.196762 # ok 254 /sound
1331 20:55:55.224750 # ok 255 /target-module@4b000000
1332 20:55:55.243318 # ok 256 /target-module@4b000000/target-module@140000
1333 20:55:55.264314 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1334 20:55:55.272789 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1335 20:55:55.279988 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1336 20:55:57.454574 dt_test_unprobed_devices_sh_ skip
1337 20:55:57.460251 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1338 20:55:57.466054 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1339 20:55:57.466586 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1340 20:55:57.474714 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1341 20:55:57.475205 dt_test_unprobed_devices_sh_fixedregulator0 pass
1342 20:55:57.480301 dt_test_unprobed_devices_sh_leds pass
1343 20:55:57.485806 dt_test_unprobed_devices_sh_ocp pass
1344 20:55:57.491519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1345 20:55:57.497175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1346 20:55:57.502681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1347 20:55:57.508530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1348 20:55:57.519595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1349 20:55:57.525302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1350 20:55:57.530786 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1351 20:55:57.542143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1352 20:55:57.547869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1353 20:55:57.558974 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1354 20:55:57.570014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1355 20:55:57.581178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1356 20:55:57.592401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1357 20:55:57.598061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1358 20:55:57.609219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1359 20:55:57.620411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1360 20:55:57.631612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1361 20:55:57.642793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1362 20:55:57.648474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1363 20:55:57.659579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1364 20:55:57.670901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1365 20:55:57.682081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1366 20:55:57.693247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1367 20:55:57.698882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1368 20:55:57.710052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1369 20:55:57.721195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1370 20:55:57.732394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1371 20:55:57.738092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1372 20:55:57.749266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1373 20:55:57.760377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1374 20:55:57.771650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1375 20:55:57.782767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1376 20:55:57.793985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1377 20:55:57.805133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1378 20:55:57.816342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1379 20:55:57.827538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1380 20:55:57.838732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1381 20:55:57.849921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1382 20:55:57.861136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1383 20:55:57.872258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1384 20:55:57.883472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1385 20:55:57.894687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1386 20:55:57.905925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1387 20:55:57.917068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1388 20:55:57.928225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1389 20:55:57.939437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1390 20:55:57.950673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1391 20:55:57.961792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1392 20:55:57.973012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1393 20:55:57.984181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1394 20:55:57.989866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1395 20:55:58.000960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1396 20:55:58.012162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1397 20:55:58.023362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1398 20:55:58.034551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1399 20:55:58.045762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1400 20:55:58.056938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1401 20:55:58.068187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1402 20:55:58.079316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1403 20:55:58.090510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1404 20:55:58.096136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1405 20:55:58.107331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1406 20:55:58.118509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1407 20:55:58.129667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1408 20:55:58.140949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1409 20:55:58.152097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1410 20:55:58.163288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1411 20:55:58.174475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1412 20:55:58.185664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1413 20:55:58.196864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1414 20:55:58.208045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1415 20:55:58.219244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1416 20:55:58.230519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1417 20:55:58.241690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1418 20:55:58.252841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1419 20:55:58.263943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1420 20:55:58.269637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1421 20:55:58.280795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1422 20:55:58.291985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1423 20:55:58.303157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1424 20:55:58.314334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1425 20:55:58.325535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1426 20:55:58.336751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1427 20:55:58.347959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1428 20:55:58.359149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1429 20:55:58.370326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1430 20:55:58.381521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1431 20:55:58.392717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1432 20:55:58.398337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1433 20:55:58.409484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1434 20:55:58.420739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1435 20:55:58.426293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1436 20:55:58.437501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1437 20:55:58.443104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1438 20:55:58.454249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1439 20:55:58.465445 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1440 20:55:58.471096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1441 20:55:58.482232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1442 20:55:58.493426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1443 20:55:58.504613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1444 20:55:58.515768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1445 20:55:58.527010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1446 20:55:58.538182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1447 20:55:58.554981 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1448 20:55:58.566193 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1449 20:55:58.577378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1450 20:55:58.588633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1451 20:55:58.599796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1452 20:55:58.610957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1453 20:55:58.622159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1454 20:55:58.633356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1455 20:55:58.650122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1456 20:55:58.661333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1457 20:55:58.678124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1458 20:55:58.689298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1459 20:55:58.694943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1460 20:55:58.706078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1461 20:55:58.711823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1462 20:55:58.722893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1463 20:55:58.734077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1464 20:55:58.739670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1465 20:55:58.750815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1466 20:55:58.756481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1467 20:55:58.767695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1468 20:55:58.773341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1469 20:55:58.784444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1470 20:55:58.790129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1471 20:55:58.801218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1472 20:55:58.812403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1473 20:55:58.823604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1474 20:55:58.829245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1475 20:55:58.840415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1476 20:55:58.851590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1477 20:55:58.862788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1478 20:55:58.868469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1479 20:55:58.874060 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1480 20:55:58.879631 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1481 20:55:58.885223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1482 20:55:58.890814 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1483 20:55:58.901980 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1484 20:55:58.907606 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1485 20:55:58.913238 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1486 20:55:58.924319 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1487 20:55:58.930045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1488 20:55:58.941096 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1489 20:55:58.946874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1490 20:55:58.957918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1491 20:55:58.963529 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1492 20:55:58.974699 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1493 20:55:58.980347 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1494 20:55:58.991485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1495 20:55:58.997154 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1496 20:55:59.002706 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1497 20:55:59.013848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1498 20:55:59.019527 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1499 20:55:59.030625 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1500 20:55:59.036309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1501 20:55:59.047427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1502 20:55:59.053067 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1503 20:55:59.064232 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1504 20:55:59.069867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1505 20:55:59.081003 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1506 20:55:59.086630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1507 20:55:59.097849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1508 20:55:59.103410 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1509 20:55:59.114572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1510 20:55:59.120224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1511 20:55:59.125875 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1512 20:55:59.136998 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1513 20:55:59.148150 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1514 20:55:59.159342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1515 20:55:59.170517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1516 20:55:59.181687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1517 20:55:59.187360 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1518 20:55:59.198507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1519 20:55:59.209718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1520 20:55:59.220889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1521 20:55:59.232059 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1522 20:55:59.237720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1523 20:55:59.248881 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1524 20:55:59.254517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1525 20:55:59.265636 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1526 20:55:59.271298 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1527 20:55:59.282434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1528 20:55:59.288099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1529 20:55:59.299260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1530 20:55:59.304900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1531 20:55:59.316037 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1532 20:55:59.321653 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1533 20:55:59.332849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1534 20:55:59.338440 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1535 20:55:59.349581 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1536 20:55:59.355227 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1537 20:55:59.360918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1538 20:55:59.371992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1539 20:55:59.377615 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1540 20:55:59.388759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1541 20:55:59.394403 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1542 20:55:59.405550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1543 20:55:59.411190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1544 20:55:59.416789 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1545 20:55:59.422374 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1546 20:55:59.433506 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1547 20:55:59.439166 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1548 20:55:59.450289 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1549 20:55:59.455884 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1550 20:55:59.467072 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1551 20:55:59.478291 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1552 20:55:59.489475 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1553 20:55:59.495123 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1554 20:55:59.506239 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1555 20:55:59.517483 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1556 20:55:59.523187 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1557 20:55:59.528793 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1558 20:55:59.534381 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1559 20:55:59.539982 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1560 20:55:59.545596 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1561 20:55:59.551192 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1562 20:55:59.556811 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1563 20:55:59.562375 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1564 20:55:59.573527 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1565 20:55:59.579194 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1566 20:55:59.584802 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1567 20:55:59.590420 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1568 20:55:59.596016 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1569 20:55:59.601603 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1570 20:55:59.607227 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1571 20:55:59.612809 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1572 20:55:59.618407 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1573 20:55:59.624017 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1574 20:55:59.629626 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1575 20:55:59.635232 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1576 20:55:59.640842 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1577 20:55:59.646433 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1578 20:55:59.652033 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1579 20:55:59.657676 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1580 20:55:59.663253 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1581 20:55:59.668839 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1582 20:55:59.674442 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1583 20:55:59.680097 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1584 20:55:59.685641 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1585 20:55:59.691226 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1586 20:55:59.696849 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1587 20:55:59.702454 dt_test_unprobed_devices_sh_opp-table skip
1588 20:55:59.702944 dt_test_unprobed_devices_sh_soc skip
1589 20:55:59.708095 dt_test_unprobed_devices_sh_sound pass
1590 20:55:59.713681 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1591 20:55:59.719249 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1592 20:55:59.724867 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1593 20:55:59.730471 dt_test_unprobed_devices_sh fail
1594 20:55:59.736090 + ../../utils/send-to-lava.sh ./output/result.txt
1595 20:55:59.743132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1596 20:55:59.744079 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1598 20:55:59.748861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1599 20:55:59.749628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1601 20:55:59.842110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1602 20:55:59.842903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1604 20:55:59.944109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1605 20:55:59.944928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1607 20:56:00.044308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1608 20:56:00.045117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1610 20:56:00.139003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1611 20:56:00.139828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1613 20:56:00.233802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1614 20:56:00.234678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1616 20:56:00.324765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1617 20:56:00.325571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1619 20:56:00.415420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1620 20:56:00.416234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1622 20:56:00.509547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1623 20:56:00.510401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1625 20:56:00.603124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1626 20:56:00.603954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1628 20:56:00.696349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1629 20:56:00.697168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1631 20:56:00.789547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1632 20:56:00.790480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1634 20:56:00.882623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1635 20:56:00.883447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1637 20:56:00.973330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1638 20:56:00.974232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1640 20:56:01.068472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1641 20:56:01.069279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1643 20:56:01.161244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1644 20:56:01.162041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1646 20:56:01.253922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1647 20:56:01.254749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1649 20:56:01.355909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1650 20:56:01.356703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1652 20:56:01.457223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1653 20:56:01.458014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1655 20:56:01.551638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1656 20:56:01.552429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1658 20:56:01.642563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1659 20:56:01.643346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1661 20:56:01.743962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1662 20:56:01.744746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1664 20:56:01.834966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1665 20:56:01.835756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1667 20:56:01.927832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1668 20:56:01.928635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1670 20:56:02.020076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1671 20:56:02.020866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1673 20:56:02.111348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1674 20:56:02.112137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1676 20:56:02.203156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1677 20:56:02.203950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1679 20:56:02.295592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1680 20:56:02.296380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1682 20:56:02.391046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1683 20:56:02.391832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1685 20:56:02.481062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1686 20:56:02.481885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1688 20:56:02.573335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1689 20:56:02.574187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1691 20:56:02.665731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1692 20:56:02.666545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1694 20:56:02.761102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1695 20:56:02.761919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1697 20:56:02.852409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1698 20:56:02.853185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1700 20:56:02.945166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1701 20:56:02.945952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1703 20:56:03.037721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1704 20:56:03.038624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1706 20:56:03.140111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1707 20:56:03.141002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1709 20:56:03.235012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1710 20:56:03.235832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1712 20:56:03.330310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1713 20:56:03.331094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1715 20:56:03.422522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1716 20:56:03.423301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1718 20:56:03.512569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1719 20:56:03.513388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1721 20:56:03.606864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1722 20:56:03.607664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1724 20:56:03.709237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1725 20:56:03.710020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1727 20:56:03.802672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1728 20:56:03.803459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1730 20:56:03.894229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1731 20:56:03.895011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1733 20:56:03.995341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1734 20:56:03.996141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1736 20:56:04.088417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1737 20:56:04.089214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1739 20:56:04.181217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1740 20:56:04.182015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1742 20:56:04.274151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1743 20:56:04.274935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1745 20:56:04.366740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1746 20:56:04.367521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1748 20:56:04.459496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1749 20:56:04.460275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1751 20:56:04.552567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1752 20:56:04.553356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1754 20:56:04.644159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1755 20:56:04.644943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1757 20:56:04.738327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1758 20:56:04.739119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1760 20:56:04.832454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1761 20:56:04.833235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1763 20:56:04.923882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1764 20:56:04.924666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1766 20:56:05.015962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1767 20:56:05.016757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1769 20:56:05.116731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1770 20:56:05.117525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1772 20:56:05.218176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1773 20:56:05.218978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1775 20:56:05.312209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1776 20:56:05.313058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1778 20:56:05.402913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1779 20:56:05.403721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1781 20:56:05.495530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1782 20:56:05.496329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1784 20:56:05.595717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1785 20:56:05.596518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1787 20:56:05.697906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1788 20:56:05.698688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1790 20:56:05.798330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1791 20:56:05.799134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1793 20:56:05.891610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1794 20:56:05.892403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1796 20:56:05.983580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1797 20:56:05.984385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1799 20:56:06.075851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1800 20:56:06.076646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1802 20:56:06.168504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1803 20:56:06.169310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1805 20:56:06.261666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1806 20:56:06.262497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1808 20:56:06.353442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1809 20:56:06.354261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1811 20:56:06.444330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1812 20:56:06.445117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1814 20:56:06.538800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1815 20:56:06.539582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1817 20:56:06.631121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1818 20:56:06.631909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1820 20:56:06.723706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1821 20:56:06.724495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1823 20:56:06.816768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1824 20:56:06.817566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1826 20:56:06.911062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1827 20:56:06.911920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1829 20:56:07.004010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1830 20:56:07.004830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1832 20:56:07.095421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1833 20:56:07.096220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1835 20:56:07.187636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1836 20:56:07.188434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1838 20:56:07.290393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1839 20:56:07.291189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1841 20:56:07.390750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1842 20:56:07.391528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1844 20:56:07.485139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1845 20:56:07.485968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1847 20:56:07.586273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1848 20:56:07.587098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1850 20:56:07.687374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1851 20:56:07.688157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1853 20:56:07.781303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1854 20:56:07.782143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1856 20:56:07.873946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1857 20:56:07.874724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1859 20:56:07.965715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1860 20:56:07.966552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1862 20:56:08.059913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1863 20:56:08.060700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1865 20:56:08.152119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1866 20:56:08.152933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1868 20:56:08.242693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1869 20:56:08.243482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1871 20:56:08.337752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1872 20:56:08.338578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1874 20:56:08.430683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1875 20:56:08.431462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1877 20:56:08.524354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1878 20:56:08.525138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1880 20:56:08.612375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1881 20:56:08.613169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1883 20:56:08.706608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1884 20:56:08.707389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1886 20:56:08.799733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1887 20:56:08.800515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1889 20:56:08.899505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1890 20:56:08.900286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1892 20:56:08.991463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1893 20:56:08.992241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1895 20:56:09.085145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1896 20:56:09.085933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1898 20:56:09.179155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1899 20:56:09.179950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1901 20:56:09.269954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1902 20:56:09.270759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1904 20:56:09.372290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1905 20:56:09.373078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1907 20:56:09.466519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1908 20:56:09.467303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1910 20:56:09.559221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1911 20:56:09.560012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1913 20:56:09.651559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1914 20:56:09.652348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1916 20:56:09.743657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1917 20:56:09.744463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1919 20:56:09.837359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1920 20:56:09.838177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1922 20:56:09.930657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1923 20:56:09.931459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1925 20:56:10.023758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1926 20:56:10.024602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1928 20:56:10.114266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1929 20:56:10.115109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1931 20:56:10.209025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1932 20:56:10.209934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1934 20:56:10.302234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1935 20:56:10.303083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1937 20:56:10.394109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1938 20:56:10.394948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1940 20:56:10.482192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1941 20:56:10.483037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1943 20:56:10.574865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1944 20:56:10.575744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1946 20:56:10.667204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1947 20:56:10.668052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1949 20:56:10.761998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1950 20:56:10.762852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1952 20:56:10.852453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1953 20:56:10.853502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1955 20:56:10.943899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1957 20:56:10.947119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1958 20:56:11.036770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1960 20:56:11.039130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1961 20:56:11.129995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1963 20:56:11.133097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1964 20:56:11.222643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1965 20:56:11.223281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1967 20:56:11.312740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1968 20:56:11.313375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1970 20:56:11.402094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1971 20:56:11.403011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1973 20:56:11.494950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1974 20:56:11.495869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1976 20:56:11.587457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1977 20:56:11.588367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1979 20:56:11.680128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1980 20:56:11.681045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1982 20:56:11.770197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1983 20:56:11.771089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1985 20:56:11.871267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1986 20:56:11.872200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1988 20:56:11.964408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1989 20:56:11.965326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1991 20:56:12.058853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1992 20:56:12.059788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1994 20:56:12.149934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1995 20:56:12.150860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1997 20:56:12.241779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1998 20:56:12.242747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2000 20:56:12.333138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2001 20:56:12.334094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2003 20:56:12.427133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2004 20:56:12.428053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2006 20:56:12.522078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2007 20:56:12.523017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2009 20:56:12.613843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2010 20:56:12.614763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2012 20:56:12.706094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2013 20:56:12.706974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2015 20:56:12.797598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2016 20:56:12.798564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2018 20:56:12.891884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2019 20:56:12.892860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2021 20:56:12.983501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2022 20:56:12.984402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2024 20:56:13.073914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2025 20:56:13.074727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2027 20:56:13.163275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2028 20:56:13.164083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2030 20:56:13.256232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2031 20:56:13.257054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2033 20:56:13.349573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2034 20:56:13.350570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2036 20:56:13.444609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2037 20:56:13.445501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2039 20:56:13.538254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2040 20:56:13.539040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2042 20:56:13.629428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2043 20:56:13.630329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2045 20:56:13.721909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2046 20:56:13.722765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2048 20:56:13.813069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2049 20:56:13.813936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2051 20:56:13.905854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2052 20:56:13.906770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2054 20:56:14.000689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2055 20:56:14.001584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2057 20:56:14.090758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2058 20:56:14.091637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2060 20:56:14.184122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2061 20:56:14.184955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2063 20:56:14.278206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2064 20:56:14.279020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2066 20:56:14.378806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2067 20:56:14.379606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2069 20:56:14.472486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2070 20:56:14.473277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2072 20:56:14.563099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2073 20:56:14.564007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2075 20:56:14.658967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2076 20:56:14.659884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2078 20:56:14.750605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2079 20:56:14.751522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2081 20:56:14.843485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2082 20:56:14.844518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2084 20:56:14.943082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2085 20:56:14.944002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2087 20:56:15.045751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2088 20:56:15.046721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2090 20:56:15.146380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2091 20:56:15.147354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2093 20:56:15.241700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2094 20:56:15.242665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2096 20:56:15.334243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2097 20:56:15.335155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2099 20:56:15.428275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2100 20:56:15.429186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2102 20:56:15.519543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2103 20:56:15.520471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2105 20:56:15.610809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2106 20:56:15.611720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2108 20:56:15.701440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2109 20:56:15.702406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2111 20:56:15.798302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2112 20:56:15.799206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2114 20:56:15.899303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2115 20:56:15.900195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2117 20:56:15.998982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2118 20:56:15.999874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2120 20:56:16.087822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2121 20:56:16.088728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2123 20:56:16.181243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2124 20:56:16.182216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2126 20:56:16.273895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2127 20:56:16.274828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2129 20:56:16.367252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2130 20:56:16.368187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2132 20:56:16.460803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2133 20:56:16.461721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2135 20:56:16.551915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2136 20:56:16.552807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2138 20:56:16.643940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2139 20:56:16.644840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2141 20:56:16.743070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2142 20:56:16.743953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2144 20:56:16.837360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2145 20:56:16.838784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2147 20:56:16.930905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2148 20:56:16.931874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2150 20:56:17.030835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2151 20:56:17.031773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2153 20:56:17.120928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2154 20:56:17.121930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2156 20:56:17.213868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2157 20:56:17.214791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2159 20:56:17.308625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2160 20:56:17.309560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2162 20:56:17.400559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2163 20:56:17.401458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2165 20:56:17.491197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2166 20:56:17.492211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2168 20:56:17.584203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2169 20:56:17.585098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2171 20:56:17.678422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2172 20:56:17.679198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2174 20:56:17.770036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2175 20:56:17.770774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2177 20:56:17.863162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2178 20:56:17.864054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2180 20:56:17.954204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2181 20:56:17.955084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2183 20:56:18.048051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2184 20:56:18.048925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2186 20:56:18.139890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2187 20:56:18.140731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2189 20:56:18.229083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2190 20:56:18.229926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2192 20:56:18.324297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2193 20:56:18.325123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2195 20:56:18.419140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2196 20:56:18.419943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2198 20:56:18.507903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2199 20:56:18.508731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2201 20:56:18.599510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2202 20:56:18.600363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2204 20:56:18.691928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2205 20:56:18.692868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2207 20:56:18.785555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2208 20:56:18.786476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2210 20:56:18.878646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2211 20:56:18.879547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2213 20:56:18.967379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2214 20:56:18.968317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2216 20:56:19.059841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2217 20:56:19.060728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2219 20:56:19.153327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2220 20:56:19.154265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2222 20:56:19.242736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2223 20:56:19.243655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2225 20:56:19.335783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2226 20:56:19.336648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2228 20:56:19.430408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2229 20:56:19.431256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2231 20:56:19.523199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2232 20:56:19.524060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2234 20:56:19.619292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2235 20:56:19.620232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2237 20:56:19.717540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2238 20:56:19.718491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2240 20:56:19.819341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2241 20:56:19.820377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2243 20:56:19.914170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2244 20:56:19.915096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2246 20:56:20.017317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2247 20:56:20.018032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2249 20:56:20.116067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2250 20:56:20.116968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2252 20:56:20.211865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2253 20:56:20.212783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2255 20:56:20.310275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2256 20:56:20.311140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2258 20:56:20.399084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2259 20:56:20.399953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2261 20:56:20.493100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2262 20:56:20.494006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2264 20:56:20.585389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2265 20:56:20.586279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2267 20:56:20.684606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2268 20:56:20.685483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2270 20:56:20.777653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2271 20:56:20.778541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2273 20:56:20.873102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2274 20:56:20.873985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2276 20:56:20.962269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2278 20:56:20.965253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2279 20:56:21.053944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2280 20:56:21.054835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2282 20:56:21.147971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2283 20:56:21.148792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2285 20:56:21.237318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2286 20:56:21.238236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2288 20:56:21.325338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2289 20:56:21.326237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2291 20:56:21.418145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2292 20:56:21.419003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2294 20:56:21.508731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2295 20:56:21.509567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2297 20:56:21.602355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2298 20:56:21.603312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2300 20:56:21.696069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2301 20:56:21.696995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2303 20:56:21.785853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2304 20:56:21.786697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2306 20:56:21.876285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2307 20:56:21.877123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2309 20:56:21.967099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2310 20:56:21.967967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2312 20:56:22.052927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2313 20:56:22.053552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2315 20:56:22.146157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2316 20:56:22.147086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2318 20:56:22.235983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2319 20:56:22.236810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2321 20:56:22.327584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2322 20:56:22.328479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2324 20:56:22.417258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2325 20:56:22.418137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2327 20:56:22.509571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2328 20:56:22.510490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2330 20:56:22.600572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2331 20:56:22.601427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2333 20:56:22.692893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2334 20:56:22.693865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2336 20:56:22.785383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2337 20:56:22.786295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2339 20:56:22.875502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2340 20:56:22.876437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2342 20:56:22.967836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2343 20:56:22.968781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2345 20:56:23.058371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2346 20:56:23.059313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2348 20:56:23.159747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2349 20:56:23.160396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2351 20:56:23.249074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2352 20:56:23.249995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2354 20:56:23.338581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2355 20:56:23.339480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2357 20:56:23.430511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2358 20:56:23.431409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2360 20:56:23.522384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2361 20:56:23.523268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2363 20:56:23.616107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2364 20:56:23.617021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2366 20:56:23.707748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2367 20:56:23.708721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2369 20:56:23.794937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2370 20:56:23.795561 + set +x
2371 20:56:23.796291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2373 20:56:23.799196 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 914717_1.6.2.4.5>
2374 20:56:23.799973 Received signal: <ENDRUN> 1_kselftest-dt 914717_1.6.2.4.5
2375 20:56:23.800469 Ending use of test pattern.
2376 20:56:23.800916 Ending test lava.1_kselftest-dt (914717_1.6.2.4.5), duration 85.49
2378 20:56:23.804808 <LAVA_TEST_RUNNER EXIT>
2379 20:56:23.805572 ok: lava_test_shell seems to have completed
2380 20:56:23.819078 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2381 20:56:23.821080 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2382 20:56:23.821712 end: 3 lava-test-retry (duration 00:01:27) [common]
2383 20:56:23.822376 start: 4 finalize (timeout 00:05:27) [common]
2384 20:56:23.822948 start: 4.1 power-off (timeout 00:00:30) [common]
2385 20:56:23.823926 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2386 20:56:23.863087 >> OK - accepted request
2387 20:56:23.864918 Returned 0 in 0 seconds
2388 20:56:23.966223 end: 4.1 power-off (duration 00:00:00) [common]
2390 20:56:23.968064 start: 4.2 read-feedback (timeout 00:05:27) [common]
2391 20:56:23.969262 Listened to connection for namespace 'common' for up to 1s
2392 20:56:23.970215 Listened to connection for namespace 'common' for up to 1s
2393 20:56:24.969181 Finalising connection for namespace 'common'
2394 20:56:24.969980 Disconnecting from shell: Finalise
2395 20:56:24.970514 / #
2396 20:56:25.071508 end: 4.2 read-feedback (duration 00:00:01) [common]
2397 20:56:25.072281 end: 4 finalize (duration 00:00:01) [common]
2398 20:56:25.072944 Cleaning after the job
2399 20:56:25.073570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/ramdisk
2400 20:56:25.082182 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/kernel
2401 20:56:25.088573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/dtb
2402 20:56:25.089772 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/nfsrootfs
2403 20:56:25.236781 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914717/tftp-deploy-s16kyw2i/modules
2404 20:56:25.246215 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/914717
2405 20:56:28.210205 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/914717
2406 20:56:28.210897 Job finished correctly