Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:55:15.212372 lava-dispatcher, installed at version: 2024.01
2 19:55:15.213193 start: 0 validate
3 19:55:15.213680 Start time: 2024-10-30 19:55:15.213649+00:00 (UTC)
4 19:55:15.214233 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:55:15.214786 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 19:55:15.258692 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:55:15.259236 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 19:55:15.287213 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:55:15.287821 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:55:16.335343 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:55:16.335862 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
12 19:55:16.377483 validate duration: 1.16
14 19:55:16.378334 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:55:16.378675 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:55:16.378983 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:55:16.379558 Not decompressing ramdisk as can be used compressed.
18 19:55:16.380007 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 19:55:16.380261 saving as /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/ramdisk/rootfs.cpio.gz
20 19:55:16.380521 total size: 8181887 (7 MB)
21 19:55:16.419599 progress 0 % (0 MB)
22 19:55:16.427644 progress 5 % (0 MB)
23 19:55:16.438444 progress 10 % (0 MB)
24 19:55:16.447062 progress 15 % (1 MB)
25 19:55:16.452437 progress 20 % (1 MB)
26 19:55:16.458194 progress 25 % (1 MB)
27 19:55:16.463411 progress 30 % (2 MB)
28 19:55:16.469235 progress 35 % (2 MB)
29 19:55:16.474433 progress 40 % (3 MB)
30 19:55:16.480188 progress 45 % (3 MB)
31 19:55:16.485482 progress 50 % (3 MB)
32 19:55:16.491112 progress 55 % (4 MB)
33 19:55:16.496333 progress 60 % (4 MB)
34 19:55:16.501909 progress 65 % (5 MB)
35 19:55:16.507090 progress 70 % (5 MB)
36 19:55:16.512709 progress 75 % (5 MB)
37 19:55:16.517892 progress 80 % (6 MB)
38 19:55:16.523432 progress 85 % (6 MB)
39 19:55:16.528652 progress 90 % (7 MB)
40 19:55:16.534624 progress 95 % (7 MB)
41 19:55:16.539531 progress 100 % (7 MB)
42 19:55:16.540194 7 MB downloaded in 0.16 s (48.87 MB/s)
43 19:55:16.540741 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:55:16.541633 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:55:16.541924 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:55:16.542193 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:55:16.542645 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/kernel/Image
49 19:55:16.542884 saving as /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/kernel/Image
50 19:55:16.543088 total size: 37812736 (36 MB)
51 19:55:16.543295 No compression specified
52 19:55:16.578614 progress 0 % (0 MB)
53 19:55:16.601765 progress 5 % (1 MB)
54 19:55:16.625175 progress 10 % (3 MB)
55 19:55:16.648743 progress 15 % (5 MB)
56 19:55:16.671844 progress 20 % (7 MB)
57 19:55:16.695398 progress 25 % (9 MB)
58 19:55:16.719245 progress 30 % (10 MB)
59 19:55:16.742935 progress 35 % (12 MB)
60 19:55:16.766999 progress 40 % (14 MB)
61 19:55:16.790842 progress 45 % (16 MB)
62 19:55:16.814519 progress 50 % (18 MB)
63 19:55:16.838489 progress 55 % (19 MB)
64 19:55:16.862262 progress 60 % (21 MB)
65 19:55:16.886469 progress 65 % (23 MB)
66 19:55:16.909923 progress 70 % (25 MB)
67 19:55:16.933813 progress 75 % (27 MB)
68 19:55:16.957406 progress 80 % (28 MB)
69 19:55:16.981048 progress 85 % (30 MB)
70 19:55:17.004700 progress 90 % (32 MB)
71 19:55:17.028742 progress 95 % (34 MB)
72 19:55:17.052009 progress 100 % (36 MB)
73 19:55:17.052820 36 MB downloaded in 0.51 s (70.75 MB/s)
74 19:55:17.053328 end: 1.2.1 http-download (duration 00:00:01) [common]
76 19:55:17.054176 end: 1.2 download-retry (duration 00:00:01) [common]
77 19:55:17.054454 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:55:17.054721 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:55:17.055318 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 19:55:17.055615 saving as /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/dtb/meson-g12b-a311d-libretech-cc.dtb
81 19:55:17.055826 total size: 54703 (0 MB)
82 19:55:17.056068 No compression specified
83 19:55:17.097218 progress 59 % (0 MB)
84 19:55:17.098109 progress 100 % (0 MB)
85 19:55:17.098674 0 MB downloaded in 0.04 s (1.22 MB/s)
86 19:55:17.099156 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:55:17.099971 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:55:17.100273 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:55:17.100585 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:55:17.101057 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/modules.tar.xz
92 19:55:17.101297 saving as /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/modules/modules.tar
93 19:55:17.101502 total size: 11751036 (11 MB)
94 19:55:17.101711 Using unxz to decompress xz
95 19:55:17.134989 progress 0 % (0 MB)
96 19:55:17.212821 progress 5 % (0 MB)
97 19:55:17.298454 progress 10 % (1 MB)
98 19:55:17.390597 progress 15 % (1 MB)
99 19:55:17.472547 progress 20 % (2 MB)
100 19:55:17.551170 progress 25 % (2 MB)
101 19:55:17.633561 progress 30 % (3 MB)
102 19:55:17.712888 progress 35 % (3 MB)
103 19:55:17.795601 progress 40 % (4 MB)
104 19:55:17.886186 progress 45 % (5 MB)
105 19:55:17.972155 progress 50 % (5 MB)
106 19:55:18.057217 progress 55 % (6 MB)
107 19:55:18.141836 progress 60 % (6 MB)
108 19:55:18.227635 progress 65 % (7 MB)
109 19:55:18.311613 progress 70 % (7 MB)
110 19:55:18.390412 progress 75 % (8 MB)
111 19:55:18.474916 progress 80 % (8 MB)
112 19:55:18.555934 progress 85 % (9 MB)
113 19:55:18.630853 progress 90 % (10 MB)
114 19:55:18.732362 progress 95 % (10 MB)
115 19:55:18.831522 progress 100 % (11 MB)
116 19:55:18.845743 11 MB downloaded in 1.74 s (6.43 MB/s)
117 19:55:18.846387 end: 1.4.1 http-download (duration 00:00:02) [common]
119 19:55:18.847223 end: 1.4 download-retry (duration 00:00:02) [common]
120 19:55:18.847499 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 19:55:18.847770 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 19:55:18.848072 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:55:18.848601 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 19:55:18.849571 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_
125 19:55:18.850431 makedir: /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin
126 19:55:18.851080 makedir: /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/tests
127 19:55:18.851696 makedir: /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/results
128 19:55:18.852352 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-add-keys
129 19:55:18.853363 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-add-sources
130 19:55:18.854341 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-background-process-start
131 19:55:18.855302 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-background-process-stop
132 19:55:18.856339 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-common-functions
133 19:55:18.857293 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-echo-ipv4
134 19:55:18.858277 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-install-packages
135 19:55:18.859200 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-installed-packages
136 19:55:18.860153 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-os-build
137 19:55:18.861209 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-probe-channel
138 19:55:18.862144 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-probe-ip
139 19:55:18.863072 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-target-ip
140 19:55:18.864015 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-target-mac
141 19:55:18.864954 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-target-storage
142 19:55:18.865885 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-case
143 19:55:18.866814 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-event
144 19:55:18.867723 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-feedback
145 19:55:18.868684 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-raise
146 19:55:18.869636 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-reference
147 19:55:18.870552 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-runner
148 19:55:18.871491 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-set
149 19:55:18.872452 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-test-shell
150 19:55:18.873413 Updating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-install-packages (oe)
151 19:55:18.874494 Updating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/bin/lava-installed-packages (oe)
152 19:55:18.875395 Creating /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/environment
153 19:55:18.876173 LAVA metadata
154 19:55:18.876680 - LAVA_JOB_ID=914518
155 19:55:18.877105 - LAVA_DISPATCHER_IP=192.168.6.2
156 19:55:18.877784 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 19:55:18.879611 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 19:55:18.880266 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 19:55:18.880680 skipped lava-vland-overlay
160 19:55:18.881166 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 19:55:18.881671 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 19:55:18.882092 skipped lava-multinode-overlay
163 19:55:18.882574 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 19:55:18.883072 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 19:55:18.883545 Loading test definitions
166 19:55:18.884129 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 19:55:18.884581 Using /lava-914518 at stage 0
168 19:55:18.886800 uuid=914518_1.5.2.4.1 testdef=None
169 19:55:18.887387 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 19:55:18.887905 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 19:55:18.891375 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 19:55:18.892537 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 19:55:18.894927 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 19:55:18.895818 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 19:55:18.898207 runner path: /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/0/tests/0_dmesg test_uuid 914518_1.5.2.4.1
178 19:55:18.898840 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 19:55:18.899639 Creating lava-test-runner.conf files
181 19:55:18.899846 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/914518/lava-overlay-5qz31de_/lava-914518/0 for stage 0
182 19:55:18.900238 - 0_dmesg
183 19:55:18.900618 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 19:55:18.900910 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 19:55:18.925316 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 19:55:18.925763 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 19:55:18.926031 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 19:55:18.926299 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 19:55:18.926564 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 19:55:19.853027 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 19:55:19.853487 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 19:55:19.853735 extracting modules file /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk
193 19:55:21.232097 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 19:55:21.232546 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 19:55:21.232816 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914518/compress-overlay-hlo0tjnj/overlay-1.5.2.5.tar.gz to ramdisk
196 19:55:21.233026 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914518/compress-overlay-hlo0tjnj/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk
197 19:55:21.263010 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 19:55:21.263424 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 19:55:21.263692 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 19:55:21.263914 Converting downloaded kernel to a uImage
201 19:55:21.264240 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/kernel/Image /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/kernel/uImage
202 19:55:21.673380 output: Image Name:
203 19:55:21.673795 output: Created: Wed Oct 30 19:55:21 2024
204 19:55:21.674006 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 19:55:21.674211 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
206 19:55:21.674412 output: Load Address: 01080000
207 19:55:21.674608 output: Entry Point: 01080000
208 19:55:21.674804 output:
209 19:55:21.675133 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 19:55:21.675402 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 19:55:21.675670 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 19:55:21.675922 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 19:55:21.676229 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 19:55:21.676487 Building ramdisk /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk
215 19:55:24.159757 >> 188205 blocks
216 19:55:33.176840 Adding RAMdisk u-boot header.
217 19:55:33.177290 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk.cpio.gz.uboot
218 19:55:33.456250 output: Image Name:
219 19:55:33.456715 output: Created: Wed Oct 30 19:55:33 2024
220 19:55:33.457159 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 19:55:33.457575 output: Data Size: 26773313 Bytes = 26145.81 KiB = 25.53 MiB
222 19:55:33.457998 output: Load Address: 00000000
223 19:55:33.458398 output: Entry Point: 00000000
224 19:55:33.458794 output:
225 19:55:33.459916 rename /var/lib/lava/dispatcher/tmp/914518/extract-overlay-ramdisk-n4wowi1i/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot
226 19:55:33.460700 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 19:55:33.461251 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 19:55:33.461781 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 19:55:33.462252 No LXC device requested
230 19:55:33.462756 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 19:55:33.463263 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 19:55:33.463758 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 19:55:33.464206 Checking files for TFTP limit of 4294967296 bytes.
234 19:55:33.466856 end: 1 tftp-deploy (duration 00:00:17) [common]
235 19:55:33.467436 start: 2 uboot-action (timeout 00:05:00) [common]
236 19:55:33.467970 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 19:55:33.468512 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 19:55:33.469022 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 19:55:33.469563 Using kernel file from prepare-kernel: 914518/tftp-deploy-qddaq8x2/kernel/uImage
240 19:55:33.470196 substitutions:
241 19:55:33.470613 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 19:55:33.471016 - {DTB_ADDR}: 0x01070000
243 19:55:33.471417 - {DTB}: 914518/tftp-deploy-qddaq8x2/dtb/meson-g12b-a311d-libretech-cc.dtb
244 19:55:33.471816 - {INITRD}: 914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot
245 19:55:33.472241 - {KERNEL_ADDR}: 0x01080000
246 19:55:33.472639 - {KERNEL}: 914518/tftp-deploy-qddaq8x2/kernel/uImage
247 19:55:33.473032 - {LAVA_MAC}: None
248 19:55:33.473472 - {PRESEED_CONFIG}: None
249 19:55:33.473873 - {PRESEED_LOCAL}: None
250 19:55:33.474263 - {RAMDISK_ADDR}: 0x08000000
251 19:55:33.474652 - {RAMDISK}: 914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot
252 19:55:33.475047 - {ROOT_PART}: None
253 19:55:33.475438 - {ROOT}: None
254 19:55:33.475830 - {SERVER_IP}: 192.168.6.2
255 19:55:33.476261 - {TEE_ADDR}: 0x83000000
256 19:55:33.476661 - {TEE}: None
257 19:55:33.477052 Parsed boot commands:
258 19:55:33.477435 - setenv autoload no
259 19:55:33.477826 - setenv initrd_high 0xffffffff
260 19:55:33.478212 - setenv fdt_high 0xffffffff
261 19:55:33.478598 - dhcp
262 19:55:33.478983 - setenv serverip 192.168.6.2
263 19:55:33.479367 - tftpboot 0x01080000 914518/tftp-deploy-qddaq8x2/kernel/uImage
264 19:55:33.479754 - tftpboot 0x08000000 914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot
265 19:55:33.480178 - tftpboot 0x01070000 914518/tftp-deploy-qddaq8x2/dtb/meson-g12b-a311d-libretech-cc.dtb
266 19:55:33.480574 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 19:55:33.480970 - bootm 0x01080000 0x08000000 0x01070000
268 19:55:33.481473 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 19:55:33.482970 start: 2.3 connect-device (timeout 00:05:00) [common]
271 19:55:33.483424 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 19:55:33.498040 Setting prompt string to ['lava-test: # ']
273 19:55:33.499528 end: 2.3 connect-device (duration 00:00:00) [common]
274 19:55:33.500168 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 19:55:33.500738 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 19:55:33.501292 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 19:55:33.502609 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 19:55:33.539262 >> OK - accepted request
279 19:55:33.541603 Returned 0 in 0 seconds
280 19:55:33.642703 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 19:55:33.644369 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 19:55:33.644956 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 19:55:33.645477 Setting prompt string to ['Hit any key to stop autoboot']
285 19:55:33.645937 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 19:55:33.647561 Trying 192.168.56.21...
287 19:55:33.648069 Connected to conserv1.
288 19:55:33.648506 Escape character is '^]'.
289 19:55:33.648934
290 19:55:33.649361 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 19:55:33.649785
292 19:55:45.296087 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 19:55:45.296722 bl2_stage_init 0x01
294 19:55:45.297173 bl2_stage_init 0x81
295 19:55:45.301518 hw id: 0x0000 - pwm id 0x01
296 19:55:45.302045 bl2_stage_init 0xc1
297 19:55:45.302457 bl2_stage_init 0x02
298 19:55:45.302862
299 19:55:45.307046 L0:00000000
300 19:55:45.307491 L1:20000703
301 19:55:45.307879 L2:00008067
302 19:55:45.308315 L3:14000000
303 19:55:45.310036 B2:00402000
304 19:55:45.310453 B1:e0f83180
305 19:55:45.310839
306 19:55:45.311225 TE: 58167
307 19:55:45.311610
308 19:55:45.321196 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 19:55:45.321684
310 19:55:45.322077 Board ID = 1
311 19:55:45.322461 Set A53 clk to 24M
312 19:55:45.322845 Set A73 clk to 24M
313 19:55:45.326791 Set clk81 to 24M
314 19:55:45.327212 A53 clk: 1200 MHz
315 19:55:45.327595 A73 clk: 1200 MHz
316 19:55:45.332456 CLK81: 166.6M
317 19:55:45.332873 smccc: 00012abd
318 19:55:45.337846 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 19:55:45.338264 board id: 1
320 19:55:45.346564 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 19:55:45.357194 fw parse done
322 19:55:45.363308 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 19:55:45.405677 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 19:55:45.416532 PIEI prepare done
325 19:55:45.416955 fastboot data load
326 19:55:45.417345 fastboot data verify
327 19:55:45.422239 verify result: 266
328 19:55:45.427787 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 19:55:45.428234 LPDDR4 probe
330 19:55:45.428622 ddr clk to 1584MHz
331 19:55:45.435797 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 19:55:45.473095
333 19:55:45.473620 dmc_version 0001
334 19:55:45.479736 Check phy result
335 19:55:45.485604 INFO : End of CA training
336 19:55:45.486059 INFO : End of initialization
337 19:55:45.491235 INFO : Training has run successfully!
338 19:55:45.491665 Check phy result
339 19:55:45.496777 INFO : End of initialization
340 19:55:45.497226 INFO : End of read enable training
341 19:55:45.500172 INFO : End of fine write leveling
342 19:55:45.505624 INFO : End of Write leveling coarse delay
343 19:55:45.511262 INFO : Training has run successfully!
344 19:55:45.511695 Check phy result
345 19:55:45.512125 INFO : End of initialization
346 19:55:45.516856 INFO : End of read dq deskew training
347 19:55:45.522477 INFO : End of MPR read delay center optimization
348 19:55:45.522904 INFO : End of write delay center optimization
349 19:55:45.528063 INFO : End of read delay center optimization
350 19:55:45.533645 INFO : End of max read latency training
351 19:55:45.534072 INFO : Training has run successfully!
352 19:55:45.539267 1D training succeed
353 19:55:45.545246 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 19:55:45.592856 Check phy result
355 19:55:45.593338 INFO : End of initialization
356 19:55:45.614388 INFO : End of 2D read delay Voltage center optimization
357 19:55:45.634544 INFO : End of 2D read delay Voltage center optimization
358 19:55:45.685557 INFO : End of 2D write delay Voltage center optimization
359 19:55:45.735044 INFO : End of 2D write delay Voltage center optimization
360 19:55:45.740499 INFO : Training has run successfully!
361 19:55:45.740928
362 19:55:45.741332 channel==0
363 19:55:45.746017 RxClkDly_Margin_A0==88 ps 9
364 19:55:45.746438 TxDqDly_Margin_A0==98 ps 10
365 19:55:45.749506 RxClkDly_Margin_A1==88 ps 9
366 19:55:45.749930 TxDqDly_Margin_A1==88 ps 9
367 19:55:45.754898 TrainedVREFDQ_A0==74
368 19:55:45.755326 TrainedVREFDQ_A1==74
369 19:55:45.755729 VrefDac_Margin_A0==25
370 19:55:45.760541 DeviceVref_Margin_A0==40
371 19:55:45.760964 VrefDac_Margin_A1==25
372 19:55:45.766151 DeviceVref_Margin_A1==40
373 19:55:45.766580
374 19:55:45.766984
375 19:55:45.767378 channel==1
376 19:55:45.767768 RxClkDly_Margin_A0==98 ps 10
377 19:55:45.771773 TxDqDly_Margin_A0==98 ps 10
378 19:55:45.772225 RxClkDly_Margin_A1==88 ps 9
379 19:55:45.777435 TxDqDly_Margin_A1==88 ps 9
380 19:55:45.777862 TrainedVREFDQ_A0==77
381 19:55:45.778265 TrainedVREFDQ_A1==77
382 19:55:45.782894 VrefDac_Margin_A0==23
383 19:55:45.783314 DeviceVref_Margin_A0==37
384 19:55:45.788574 VrefDac_Margin_A1==24
385 19:55:45.789013 DeviceVref_Margin_A1==37
386 19:55:45.789417
387 19:55:45.794156 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 19:55:45.794599
389 19:55:45.822161 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 19:55:45.827610 2D training succeed
391 19:55:45.833243 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 19:55:45.833672 auto size-- 65535DDR cs0 size: 2048MB
393 19:55:45.838801 DDR cs1 size: 2048MB
394 19:55:45.839223 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 19:55:45.844412 cs0 DataBus test pass
396 19:55:45.844837 cs1 DataBus test pass
397 19:55:45.845235 cs0 AddrBus test pass
398 19:55:45.849976 cs1 AddrBus test pass
399 19:55:45.850396
400 19:55:45.850796 100bdlr_step_size ps== 420
401 19:55:45.851207 result report
402 19:55:45.855576 boot times 0Enable ddr reg access
403 19:55:45.863147 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 19:55:45.876593 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 19:55:46.448547 0.0;M3 CHK:0;cm4_sp_mode 0
406 19:55:46.448964 MVN_1=0x00000000
407 19:55:46.454098 MVN_2=0x00000000
408 19:55:46.459788 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 19:55:46.460093 OPS=0x10
410 19:55:46.460306 ring efuse init
411 19:55:46.460510 chipver efuse init
412 19:55:46.465418 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 19:55:46.471012 [0.018961 Inits done]
414 19:55:46.471418 secure task start!
415 19:55:46.471774 high task start!
416 19:55:46.475578 low task start!
417 19:55:46.475976 run into bl31
418 19:55:46.482683 NOTICE: BL31: v1.3(release):4fc40b1
419 19:55:46.490026 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 19:55:46.490315 NOTICE: BL31: G12A normal boot!
421 19:55:46.515442 NOTICE: BL31: BL33 decompress pass
422 19:55:46.521119 ERROR: Error initializing runtime service opteed_fast
423 19:55:47.754052
424 19:55:47.754673
425 19:55:47.762412 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 19:55:47.762872
427 19:55:47.763288 Model: Libre Computer AML-A311D-CC Alta
428 19:55:47.971084 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 19:55:47.994443 DRAM: 2 GiB (effective 3.8 GiB)
430 19:55:48.137344 Core: 408 devices, 31 uclasses, devicetree: separate
431 19:55:48.143183 WDT: Not starting watchdog@f0d0
432 19:55:48.175406 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 19:55:48.187877 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 19:55:48.192861 ** Bad device specification mmc 0 **
435 19:55:48.203201 Card did not respond to voltage select! : -110
436 19:55:48.210861 ** Bad device specification mmc 0 **
437 19:55:48.211308 Couldn't find partition mmc 0
438 19:55:48.219178 Card did not respond to voltage select! : -110
439 19:55:48.224686 ** Bad device specification mmc 0 **
440 19:55:48.225115 Couldn't find partition mmc 0
441 19:55:48.229775 Error: could not access storage.
442 19:55:49.496301 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 19:55:49.496909 bl2_stage_init 0x01
444 19:55:49.497332 bl2_stage_init 0x81
445 19:55:49.501877 hw id: 0x0000 - pwm id 0x01
446 19:55:49.502314 bl2_stage_init 0xc1
447 19:55:49.502720 bl2_stage_init 0x02
448 19:55:49.503120
449 19:55:49.507441 L0:00000000
450 19:55:49.507869 L1:20000703
451 19:55:49.508322 L2:00008067
452 19:55:49.508725 L3:14000000
453 19:55:49.513067 B2:00402000
454 19:55:49.513497 B1:e0f83180
455 19:55:49.513895
456 19:55:49.514298 TE: 58124
457 19:55:49.514699
458 19:55:49.518652 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 19:55:49.519085
460 19:55:49.519489 Board ID = 1
461 19:55:49.524252 Set A53 clk to 24M
462 19:55:49.524682 Set A73 clk to 24M
463 19:55:49.525084 Set clk81 to 24M
464 19:55:49.529836 A53 clk: 1200 MHz
465 19:55:49.530260 A73 clk: 1200 MHz
466 19:55:49.530660 CLK81: 166.6M
467 19:55:49.531054 smccc: 00012a92
468 19:55:49.535450 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 19:55:49.541043 board id: 1
470 19:55:49.546933 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 19:55:49.557563 fw parse done
472 19:55:49.563475 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 19:55:49.606130 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 19:55:49.617027 PIEI prepare done
475 19:55:49.617462 fastboot data load
476 19:55:49.617870 fastboot data verify
477 19:55:49.622673 verify result: 266
478 19:55:49.628199 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 19:55:49.628627 LPDDR4 probe
480 19:55:49.629030 ddr clk to 1584MHz
481 19:55:49.636250 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 19:55:49.673512
483 19:55:49.673957 dmc_version 0001
484 19:55:49.680188 Check phy result
485 19:55:49.686033 INFO : End of CA training
486 19:55:49.686524 INFO : End of initialization
487 19:55:49.691623 INFO : Training has run successfully!
488 19:55:49.692108 Check phy result
489 19:55:49.697291 INFO : End of initialization
490 19:55:49.697789 INFO : End of read enable training
491 19:55:49.702908 INFO : End of fine write leveling
492 19:55:49.708444 INFO : End of Write leveling coarse delay
493 19:55:49.708877 INFO : Training has run successfully!
494 19:55:49.709282 Check phy result
495 19:55:49.714048 INFO : End of initialization
496 19:55:49.714536 INFO : End of read dq deskew training
497 19:55:49.719634 INFO : End of MPR read delay center optimization
498 19:55:49.725340 INFO : End of write delay center optimization
499 19:55:49.730928 INFO : End of read delay center optimization
500 19:55:49.731382 INFO : End of max read latency training
501 19:55:49.736459 INFO : Training has run successfully!
502 19:55:49.736907 1D training succeed
503 19:55:49.745608 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 19:55:49.793254 Check phy result
505 19:55:49.793773 INFO : End of initialization
506 19:55:49.815076 INFO : End of 2D read delay Voltage center optimization
507 19:55:49.835374 INFO : End of 2D read delay Voltage center optimization
508 19:55:49.887456 INFO : End of 2D write delay Voltage center optimization
509 19:55:49.936927 INFO : End of 2D write delay Voltage center optimization
510 19:55:49.942388 INFO : Training has run successfully!
511 19:55:49.943012
512 19:55:49.943429 channel==0
513 19:55:49.947929 RxClkDly_Margin_A0==88 ps 9
514 19:55:49.948479 TxDqDly_Margin_A0==98 ps 10
515 19:55:49.954810 RxClkDly_Margin_A1==88 ps 9
516 19:55:49.955287 TxDqDly_Margin_A1==98 ps 10
517 19:55:49.955692 TrainedVREFDQ_A0==74
518 19:55:49.959513 TrainedVREFDQ_A1==74
519 19:55:49.960016 VrefDac_Margin_A0==25
520 19:55:49.960429 DeviceVref_Margin_A0==40
521 19:55:49.966144 VrefDac_Margin_A1==25
522 19:55:49.966604 DeviceVref_Margin_A1==40
523 19:55:49.967000
524 19:55:49.967393
525 19:55:49.970357 channel==1
526 19:55:49.970838 RxClkDly_Margin_A0==98 ps 10
527 19:55:49.971237 TxDqDly_Margin_A0==98 ps 10
528 19:55:49.976230 RxClkDly_Margin_A1==98 ps 10
529 19:55:49.976711 TxDqDly_Margin_A1==108 ps 11
530 19:55:49.982616 TrainedVREFDQ_A0==77
531 19:55:49.983079 TrainedVREFDQ_A1==78
532 19:55:49.983481 VrefDac_Margin_A0==22
533 19:55:49.987287 DeviceVref_Margin_A0==37
534 19:55:49.987739 VrefDac_Margin_A1==22
535 19:55:49.993648 DeviceVref_Margin_A1==36
536 19:55:49.994271
537 19:55:49.998427 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 19:55:49.998989
539 19:55:50.026328 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 19:55:50.026984 2D training succeed
541 19:55:50.031872 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 19:55:50.037373 auto size-- 65535DDR cs0 size: 2048MB
543 19:55:50.037832 DDR cs1 size: 2048MB
544 19:55:50.042986 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 19:55:50.043431 cs0 DataBus test pass
546 19:55:50.048871 cs1 DataBus test pass
547 19:55:50.049332 cs0 AddrBus test pass
548 19:55:50.049731 cs1 AddrBus test pass
549 19:55:50.050123
550 19:55:50.054228 100bdlr_step_size ps== 420
551 19:55:50.054697 result report
552 19:55:50.060139 boot times 0Enable ddr reg access
553 19:55:50.065571 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 19:55:50.079171 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 19:55:50.652679 0.0;M3 CHK:0;cm4_sp_mode 0
556 19:55:50.653320 MVN_1=0x00000000
557 19:55:50.658051 MVN_2=0x00000000
558 19:55:50.663762 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 19:55:50.664297 OPS=0x10
560 19:55:50.664717 ring efuse init
561 19:55:50.665130 chipver efuse init
562 19:55:50.669462 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 19:55:50.674981 [0.018961 Inits done]
564 19:55:50.675555 secure task start!
565 19:55:50.676235 high task start!
566 19:55:50.679530 low task start!
567 19:55:50.680114 run into bl31
568 19:55:50.686230 NOTICE: BL31: v1.3(release):4fc40b1
569 19:55:50.694050 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 19:55:50.694624 NOTICE: BL31: G12A normal boot!
571 19:55:50.719507 NOTICE: BL31: BL33 decompress pass
572 19:55:50.725143 ERROR: Error initializing runtime service opteed_fast
573 19:55:51.958234
574 19:55:51.959068
575 19:55:51.966657 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 19:55:51.967331
577 19:55:51.967887 Model: Libre Computer AML-A311D-CC Alta
578 19:55:52.175134 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 19:55:52.198459 DRAM: 2 GiB (effective 3.8 GiB)
580 19:55:52.341496 Core: 408 devices, 31 uclasses, devicetree: separate
581 19:55:52.347231 WDT: Not starting watchdog@f0d0
582 19:55:52.379371 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 19:55:52.391876 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 19:55:52.396910 ** Bad device specification mmc 0 **
585 19:55:52.407125 Card did not respond to voltage select! : -110
586 19:55:52.414867 ** Bad device specification mmc 0 **
587 19:55:52.415499 Couldn't find partition mmc 0
588 19:55:52.423200 Card did not respond to voltage select! : -110
589 19:55:52.428628 ** Bad device specification mmc 0 **
590 19:55:52.429193 Couldn't find partition mmc 0
591 19:55:52.433841 Error: could not access storage.
592 19:55:52.776222 Net: eth0: ethernet@ff3f0000
593 19:55:52.776954 starting USB...
594 19:55:53.028017 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 19:55:53.028699 Starting the controller
596 19:55:53.035089 USB XHCI 1.10
597 19:55:54.748138 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 19:55:54.748939 bl2_stage_init 0x01
599 19:55:54.749505 bl2_stage_init 0x81
600 19:55:54.753597 hw id: 0x0000 - pwm id 0x01
601 19:55:54.754177 bl2_stage_init 0xc1
602 19:55:54.754704 bl2_stage_init 0x02
603 19:55:54.755236
604 19:55:54.759180 L0:00000000
605 19:55:54.759747 L1:20000703
606 19:55:54.760311 L2:00008067
607 19:55:54.760827 L3:14000000
608 19:55:54.764847 B2:00402000
609 19:55:54.765397 B1:e0f83180
610 19:55:54.765926
611 19:55:54.766446 TE: 58124
612 19:55:54.766963
613 19:55:54.770498 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 19:55:54.771055
615 19:55:54.771588 Board ID = 1
616 19:55:54.776108 Set A53 clk to 24M
617 19:55:54.776689 Set A73 clk to 24M
618 19:55:54.777212 Set clk81 to 24M
619 19:55:54.781672 A53 clk: 1200 MHz
620 19:55:54.782231 A73 clk: 1200 MHz
621 19:55:54.782760 CLK81: 166.6M
622 19:55:54.783271 smccc: 00012a92
623 19:55:54.787280 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 19:55:54.792891 board id: 1
625 19:55:54.798848 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 19:55:54.809248 fw parse done
627 19:55:54.815256 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 19:55:54.857873 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 19:55:54.868750 PIEI prepare done
630 19:55:54.869331 fastboot data load
631 19:55:54.869876 fastboot data verify
632 19:55:54.874410 verify result: 266
633 19:55:54.879975 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 19:55:54.880564 LPDDR4 probe
635 19:55:54.881081 ddr clk to 1584MHz
636 19:55:54.887942 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 19:55:54.925263
638 19:55:54.925906 dmc_version 0001
639 19:55:54.931922 Check phy result
640 19:55:54.937785 INFO : End of CA training
641 19:55:54.938346 INFO : End of initialization
642 19:55:54.943399 INFO : Training has run successfully!
643 19:55:54.943954 Check phy result
644 19:55:54.948970 INFO : End of initialization
645 19:55:54.949555 INFO : End of read enable training
646 19:55:54.954598 INFO : End of fine write leveling
647 19:55:54.960201 INFO : End of Write leveling coarse delay
648 19:55:54.960753 INFO : Training has run successfully!
649 19:55:54.961271 Check phy result
650 19:55:54.965759 INFO : End of initialization
651 19:55:54.966307 INFO : End of read dq deskew training
652 19:55:54.971388 INFO : End of MPR read delay center optimization
653 19:55:54.976942 INFO : End of write delay center optimization
654 19:55:54.982572 INFO : End of read delay center optimization
655 19:55:54.983142 INFO : End of max read latency training
656 19:55:54.988178 INFO : Training has run successfully!
657 19:55:54.988748 1D training succeed
658 19:55:54.997341 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 19:55:55.044969 Check phy result
660 19:55:55.045589 INFO : End of initialization
661 19:55:55.067392 INFO : End of 2D read delay Voltage center optimization
662 19:55:55.086697 INFO : End of 2D read delay Voltage center optimization
663 19:55:55.138705 INFO : End of 2D write delay Voltage center optimization
664 19:55:55.187799 INFO : End of 2D write delay Voltage center optimization
665 19:55:55.193445 INFO : Training has run successfully!
666 19:55:55.194005
667 19:55:55.194541 channel==0
668 19:55:55.198963 RxClkDly_Margin_A0==88 ps 9
669 19:55:55.199517 TxDqDly_Margin_A0==98 ps 10
670 19:55:55.204565 RxClkDly_Margin_A1==88 ps 9
671 19:55:55.205120 TxDqDly_Margin_A1==88 ps 9
672 19:55:55.205656 TrainedVREFDQ_A0==74
673 19:55:55.210177 TrainedVREFDQ_A1==74
674 19:55:55.210744 VrefDac_Margin_A0==25
675 19:55:55.211278 DeviceVref_Margin_A0==40
676 19:55:55.215753 VrefDac_Margin_A1==24
677 19:55:55.216344 DeviceVref_Margin_A1==40
678 19:55:55.216873
679 19:55:55.217398
680 19:55:55.217921 channel==1
681 19:55:55.221461 RxClkDly_Margin_A0==88 ps 9
682 19:55:55.222069 TxDqDly_Margin_A0==98 ps 10
683 19:55:55.226957 RxClkDly_Margin_A1==88 ps 9
684 19:55:55.227530 TxDqDly_Margin_A1==98 ps 10
685 19:55:55.232568 TrainedVREFDQ_A0==77
686 19:55:55.233130 TrainedVREFDQ_A1==77
687 19:55:55.233659 VrefDac_Margin_A0==23
688 19:55:55.238321 DeviceVref_Margin_A0==37
689 19:55:55.238871 VrefDac_Margin_A1==23
690 19:55:55.243900 DeviceVref_Margin_A1==37
691 19:55:55.244485
692 19:55:55.245011 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 19:55:55.245530
694 19:55:55.277445 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 19:55:55.278043 2D training succeed
696 19:55:55.283039 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 19:55:55.288667 auto size-- 65535DDR cs0 size: 2048MB
698 19:55:55.289231 DDR cs1 size: 2048MB
699 19:55:55.294250 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 19:55:55.294795 cs0 DataBus test pass
701 19:55:55.299855 cs1 DataBus test pass
702 19:55:55.300447 cs0 AddrBus test pass
703 19:55:55.300965 cs1 AddrBus test pass
704 19:55:55.301476
705 19:55:55.305536 100bdlr_step_size ps== 420
706 19:55:55.306109 result report
707 19:55:55.311129 boot times 0Enable ddr reg access
708 19:55:55.316335 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 19:55:55.329805 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 19:55:55.901895 0.0;M3 CHK:0;cm4_sp_mode 0
711 19:55:55.902408 MVN_1=0x00000000
712 19:55:55.907327 MVN_2=0x00000000
713 19:55:55.912953 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 19:55:55.913248 OPS=0x10
715 19:55:55.913484 ring efuse init
716 19:55:55.913707 chipver efuse init
717 19:55:55.918599 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 19:55:55.924142 [0.018961 Inits done]
719 19:55:55.924432 secure task start!
720 19:55:55.924663 high task start!
721 19:55:55.928732 low task start!
722 19:55:55.929008 run into bl31
723 19:55:55.935369 NOTICE: BL31: v1.3(release):4fc40b1
724 19:55:55.943146 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 19:55:55.943419 NOTICE: BL31: G12A normal boot!
726 19:55:55.968787 NOTICE: BL31: BL33 decompress pass
727 19:55:55.974367 ERROR: Error initializing runtime service opteed_fast
728 19:55:57.207301
729 19:55:57.207958
730 19:55:57.215688 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 19:55:57.216277
732 19:55:57.216752 Model: Libre Computer AML-A311D-CC Alta
733 19:55:57.424182 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 19:55:57.447527 DRAM: 2 GiB (effective 3.8 GiB)
735 19:55:57.590558 Core: 408 devices, 31 uclasses, devicetree: separate
736 19:55:57.596377 WDT: Not starting watchdog@f0d0
737 19:55:57.628611 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 19:55:57.641049 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 19:55:57.646099 ** Bad device specification mmc 0 **
740 19:55:57.656427 Card did not respond to voltage select! : -110
741 19:55:57.664106 ** Bad device specification mmc 0 **
742 19:55:57.664638 Couldn't find partition mmc 0
743 19:55:57.672380 Card did not respond to voltage select! : -110
744 19:55:57.678009 ** Bad device specification mmc 0 **
745 19:55:57.678534 Couldn't find partition mmc 0
746 19:55:57.682967 Error: could not access storage.
747 19:55:58.026414 Net: eth0: ethernet@ff3f0000
748 19:55:58.027028 starting USB...
749 19:55:58.278252 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 19:55:58.278855 Starting the controller
751 19:55:58.285222 USB XHCI 1.10
752 19:56:00.446903 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 19:56:00.447536 bl2_stage_init 0x01
754 19:56:00.448052 bl2_stage_init 0x81
755 19:56:00.452344 hw id: 0x0000 - pwm id 0x01
756 19:56:00.452886 bl2_stage_init 0xc1
757 19:56:00.453350 bl2_stage_init 0x02
758 19:56:00.453799
759 19:56:00.457981 L0:00000000
760 19:56:00.458498 L1:20000703
761 19:56:00.458951 L2:00008067
762 19:56:00.459394 L3:14000000
763 19:56:00.463573 B2:00402000
764 19:56:00.464124 B1:e0f83180
765 19:56:00.464584
766 19:56:00.465033 TE: 58167
767 19:56:00.465478
768 19:56:00.469211 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 19:56:00.469725
770 19:56:00.470180 Board ID = 1
771 19:56:00.474873 Set A53 clk to 24M
772 19:56:00.475386 Set A73 clk to 24M
773 19:56:00.475838 Set clk81 to 24M
774 19:56:00.480338 A53 clk: 1200 MHz
775 19:56:00.480846 A73 clk: 1200 MHz
776 19:56:00.481296 CLK81: 166.6M
777 19:56:00.481733 smccc: 00012abd
778 19:56:00.485962 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 19:56:00.491590 board id: 1
780 19:56:00.497642 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 19:56:00.507971 fw parse done
782 19:56:00.513921 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 19:56:00.556583 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 19:56:00.567493 PIEI prepare done
785 19:56:00.568085 fastboot data load
786 19:56:00.568558 fastboot data verify
787 19:56:00.573170 verify result: 266
788 19:56:00.578750 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 19:56:00.579274 LPDDR4 probe
790 19:56:00.579733 ddr clk to 1584MHz
791 19:56:00.586756 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 19:56:00.624038
793 19:56:00.624616 dmc_version 0001
794 19:56:00.630689 Check phy result
795 19:56:00.636614 INFO : End of CA training
796 19:56:00.637204 INFO : End of initialization
797 19:56:00.642215 INFO : Training has run successfully!
798 19:56:00.642816 Check phy result
799 19:56:00.647831 INFO : End of initialization
800 19:56:00.648422 INFO : End of read enable training
801 19:56:00.653415 INFO : End of fine write leveling
802 19:56:00.658965 INFO : End of Write leveling coarse delay
803 19:56:00.659498 INFO : Training has run successfully!
804 19:56:00.659956 Check phy result
805 19:56:00.664586 INFO : End of initialization
806 19:56:00.665117 INFO : End of read dq deskew training
807 19:56:00.670176 INFO : End of MPR read delay center optimization
808 19:56:00.675797 INFO : End of write delay center optimization
809 19:56:00.681380 INFO : End of read delay center optimization
810 19:56:00.681914 INFO : End of max read latency training
811 19:56:00.686954 INFO : Training has run successfully!
812 19:56:00.687482 1D training succeed
813 19:56:00.696111 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 19:56:00.743817 Check phy result
815 19:56:00.744501 INFO : End of initialization
816 19:56:00.765576 INFO : End of 2D read delay Voltage center optimization
817 19:56:00.785706 INFO : End of 2D read delay Voltage center optimization
818 19:56:00.837816 INFO : End of 2D write delay Voltage center optimization
819 19:56:00.887293 INFO : End of 2D write delay Voltage center optimization
820 19:56:00.892651 INFO : Training has run successfully!
821 19:56:00.893170
822 19:56:00.893608 channel==0
823 19:56:00.898286 RxClkDly_Margin_A0==88 ps 9
824 19:56:00.898795 TxDqDly_Margin_A0==98 ps 10
825 19:56:00.903928 RxClkDly_Margin_A1==88 ps 9
826 19:56:00.904532 TxDqDly_Margin_A1==98 ps 10
827 19:56:00.904973 TrainedVREFDQ_A0==74
828 19:56:00.909511 TrainedVREFDQ_A1==74
829 19:56:00.910076 VrefDac_Margin_A0==25
830 19:56:00.910499 DeviceVref_Margin_A0==40
831 19:56:00.916147 VrefDac_Margin_A1==25
832 19:56:00.916745 DeviceVref_Margin_A1==40
833 19:56:00.917141
834 19:56:00.917533
835 19:56:00.920774 channel==1
836 19:56:00.921246 RxClkDly_Margin_A0==98 ps 10
837 19:56:00.921644 TxDqDly_Margin_A0==98 ps 10
838 19:56:00.926631 RxClkDly_Margin_A1==98 ps 10
839 19:56:00.927075 TxDqDly_Margin_A1==98 ps 10
840 19:56:00.931818 TrainedVREFDQ_A0==77
841 19:56:00.932355 TrainedVREFDQ_A1==77
842 19:56:00.932756 VrefDac_Margin_A0==22
843 19:56:00.937892 DeviceVref_Margin_A0==37
844 19:56:00.938374 VrefDac_Margin_A1==22
845 19:56:00.943023 DeviceVref_Margin_A1==37
846 19:56:00.943565
847 19:56:00.943963 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 19:56:00.948931
849 19:56:00.978611 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
850 19:56:00.979224 2D training succeed
851 19:56:00.982428 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 19:56:00.988083 auto size-- 65535DDR cs0 size: 2048MB
853 19:56:00.988576 DDR cs1 size: 2048MB
854 19:56:00.993644 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 19:56:00.994255 cs0 DataBus test pass
856 19:56:00.999002 cs1 DataBus test pass
857 19:56:00.999622 cs0 AddrBus test pass
858 19:56:01.000092 cs1 AddrBus test pass
859 19:56:01.000701
860 19:56:01.004583 100bdlr_step_size ps== 420
861 19:56:01.005157 result report
862 19:56:01.010373 boot times 0Enable ddr reg access
863 19:56:01.015679 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 19:56:01.030680 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 19:56:01.602237 0.0;M3 CHK:0;cm4_sp_mode 0
866 19:56:01.602855 MVN_1=0x00000000
867 19:56:01.607613 MVN_2=0x00000000
868 19:56:01.613440 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 19:56:01.613898 OPS=0x10
870 19:56:01.614315 ring efuse init
871 19:56:01.614728 chipver efuse init
872 19:56:01.618998 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 19:56:01.624563 [0.018960 Inits done]
874 19:56:01.624998 secure task start!
875 19:56:01.625407 high task start!
876 19:56:01.629157 low task start!
877 19:56:01.629592 run into bl31
878 19:56:01.635805 NOTICE: BL31: v1.3(release):4fc40b1
879 19:56:01.643651 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 19:56:01.644126 NOTICE: BL31: G12A normal boot!
881 19:56:01.669121 NOTICE: BL31: BL33 decompress pass
882 19:56:01.674711 ERROR: Error initializing runtime service opteed_fast
883 19:56:02.907693
884 19:56:02.908361
885 19:56:02.915956 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 19:56:02.916468
887 19:56:02.916890 Model: Libre Computer AML-A311D-CC Alta
888 19:56:03.124440 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 19:56:03.147763 DRAM: 2 GiB (effective 3.8 GiB)
890 19:56:03.290848 Core: 408 devices, 31 uclasses, devicetree: separate
891 19:56:03.296663 WDT: Not starting watchdog@f0d0
892 19:56:03.328855 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 19:56:03.341321 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 19:56:03.346381 ** Bad device specification mmc 0 **
895 19:56:03.356738 Card did not respond to voltage select! : -110
896 19:56:03.364340 ** Bad device specification mmc 0 **
897 19:56:03.364798 Couldn't find partition mmc 0
898 19:56:03.372689 Card did not respond to voltage select! : -110
899 19:56:03.378126 ** Bad device specification mmc 0 **
900 19:56:03.378562 Couldn't find partition mmc 0
901 19:56:03.383218 Error: could not access storage.
902 19:56:03.725755 Net: eth0: ethernet@ff3f0000
903 19:56:03.726304 starting USB...
904 19:56:03.977532 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 19:56:03.978017 Starting the controller
906 19:56:03.984427 USB XHCI 1.10
907 19:56:05.538841 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 19:56:05.547196 scanning usb for storage devices... 0 Storage Device(s) found
910 19:56:05.598774 Hit any key to stop autoboot: 1
911 19:56:05.599608 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 19:56:05.600246 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 19:56:05.600725 Setting prompt string to ['=>']
914 19:56:05.601210 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 19:56:05.614608 0
916 19:56:05.615470 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 19:56:05.615958 Sending with 10 millisecond of delay
919 19:56:06.752103 => setenv autoload no
920 19:56:06.763038 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 19:56:06.768606 setenv autoload no
922 19:56:06.769434 Sending with 10 millisecond of delay
924 19:56:08.566258 => setenv initrd_high 0xffffffff
925 19:56:08.577098 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 19:56:08.577994 setenv initrd_high 0xffffffff
927 19:56:08.578752 Sending with 10 millisecond of delay
929 19:56:10.194887 => setenv fdt_high 0xffffffff
930 19:56:10.205629 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 19:56:10.206474 setenv fdt_high 0xffffffff
932 19:56:10.207230 Sending with 10 millisecond of delay
934 19:56:10.499145 => dhcp
935 19:56:10.509835 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 19:56:10.510667 dhcp
937 19:56:10.511137 Speed: 1000, full duplex
938 19:56:10.511586 BOOTP broadcast 1
939 19:56:10.521675 DHCP client bound to address 192.168.6.27 (12 ms)
940 19:56:10.522418 Sending with 10 millisecond of delay
942 19:56:12.198977 => setenv serverip 192.168.6.2
943 19:56:12.209803 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 19:56:12.210753 setenv serverip 192.168.6.2
945 19:56:12.211492 Sending with 10 millisecond of delay
947 19:56:15.935532 => tftpboot 0x01080000 914518/tftp-deploy-qddaq8x2/kernel/uImage
948 19:56:15.946398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 19:56:15.947267 tftpboot 0x01080000 914518/tftp-deploy-qddaq8x2/kernel/uImage
950 19:56:15.947755 Speed: 1000, full duplex
951 19:56:15.948256 Using ethernet@ff3f0000 device
952 19:56:15.949228 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 19:56:15.954721 Filename '914518/tftp-deploy-qddaq8x2/kernel/uImage'.
954 19:56:15.958691 Load address: 0x1080000
955 19:56:18.259735 Loading: *################################################## 36.1 MiB
956 19:56:18.260436 15.7 MiB/s
957 19:56:18.260925 done
958 19:56:18.264527 Bytes transferred = 37812800 (240fa40 hex)
959 19:56:18.265408 Sending with 10 millisecond of delay
961 19:56:22.952351 => tftpboot 0x08000000 914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot
962 19:56:22.963192 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
963 19:56:22.964174 tftpboot 0x08000000 914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot
964 19:56:22.964677 Speed: 1000, full duplex
965 19:56:22.965141 Using ethernet@ff3f0000 device
966 19:56:22.966061 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 19:56:22.974655 Filename '914518/tftp-deploy-qddaq8x2/ramdisk/ramdisk.cpio.gz.uboot'.
968 19:56:22.975194 Load address: 0x8000000
969 19:56:23.071776 Loading: *## UDP wrong checksum 000000ff 00002398
970 19:56:23.097954 # UDP wrong checksum 000000ff 0000b98a
971 19:56:29.666910 T ############################################## UDP wrong checksum 00000005 00000d45
972 19:56:34.668448 T UDP wrong checksum 00000005 00000d45
973 19:56:35.009956 UDP wrong checksum 0000000f 000040b4
974 19:56:44.670474 T T UDP wrong checksum 00000005 00000d45
975 19:57:04.674444 T T T T UDP wrong checksum 00000005 00000d45
976 19:57:05.608969 UDP wrong checksum 000000ff 00000f02
977 19:57:05.615327 UDP wrong checksum 000000ff 00009cf4
978 19:57:15.533244 T T UDP wrong checksum 000000ff 0000c53d
979 19:57:19.678770
980 19:57:19.679566 Retry count exceeded; starting again
982 19:57:19.681449 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
985 19:57:19.683940 end: 2.4 uboot-commands (duration 00:01:46) [common]
987 19:57:19.685800 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
989 19:57:19.687098 end: 2 uboot-action (duration 00:01:46) [common]
991 19:57:19.689099 Cleaning after the job
992 19:57:19.689801 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/ramdisk
993 19:57:19.691570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/kernel
994 19:57:19.736448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/dtb
995 19:57:19.737842 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914518/tftp-deploy-qddaq8x2/modules
996 19:57:19.771269 start: 4.1 power-off (timeout 00:00:30) [common]
997 19:57:19.772106 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
998 19:57:19.806564 >> OK - accepted request
999 19:57:19.808861 Returned 0 in 0 seconds
1000 19:57:19.910153 end: 4.1 power-off (duration 00:00:00) [common]
1002 19:57:19.911377 start: 4.2 read-feedback (timeout 00:10:00) [common]
1003 19:57:19.912197 Listened to connection for namespace 'common' for up to 1s
1004 19:57:20.912255 Finalising connection for namespace 'common'
1005 19:57:20.913167 Disconnecting from shell: Finalise
1006 19:57:20.913832 =>
1007 19:57:21.015010 end: 4.2 read-feedback (duration 00:00:01) [common]
1008 19:57:21.015833 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/914518
1009 19:57:21.386069 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/914518
1010 19:57:21.386809 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.