Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:34:37.143088 lava-dispatcher, installed at version: 2024.01
2 20:34:37.143879 start: 0 validate
3 20:34:37.144383 Start time: 2024-10-30 20:34:37.144353+00:00 (UTC)
4 20:34:37.144945 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:34:37.145479 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 20:34:37.184740 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:34:37.185302 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 20:34:37.220021 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:34:37.220654 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:34:37.257667 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:34:37.258127 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
12 20:34:37.297203 validate duration: 0.15
14 20:34:37.298028 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:34:37.298339 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:34:37.298629 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:34:37.299192 Not decompressing ramdisk as can be used compressed.
18 20:34:37.299603 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 20:34:37.299858 saving as /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/ramdisk/rootfs.cpio.gz
20 20:34:37.300154 total size: 47897469 (45 MB)
21 20:34:37.335767 progress 0 % (0 MB)
22 20:34:37.365171 progress 5 % (2 MB)
23 20:34:37.393651 progress 10 % (4 MB)
24 20:34:37.422070 progress 15 % (6 MB)
25 20:34:37.450366 progress 20 % (9 MB)
26 20:34:37.479370 progress 25 % (11 MB)
27 20:34:37.507494 progress 30 % (13 MB)
28 20:34:37.535714 progress 35 % (16 MB)
29 20:34:37.563969 progress 40 % (18 MB)
30 20:34:37.592267 progress 45 % (20 MB)
31 20:34:37.620358 progress 50 % (22 MB)
32 20:34:37.648672 progress 55 % (25 MB)
33 20:34:37.677074 progress 60 % (27 MB)
34 20:34:37.705302 progress 65 % (29 MB)
35 20:34:37.733681 progress 70 % (32 MB)
36 20:34:37.761825 progress 75 % (34 MB)
37 20:34:37.789924 progress 80 % (36 MB)
38 20:34:37.817960 progress 85 % (38 MB)
39 20:34:37.846156 progress 90 % (41 MB)
40 20:34:37.874374 progress 95 % (43 MB)
41 20:34:37.901408 progress 100 % (45 MB)
42 20:34:37.902152 45 MB downloaded in 0.60 s (75.88 MB/s)
43 20:34:37.902768 end: 1.1.1 http-download (duration 00:00:01) [common]
45 20:34:37.903676 end: 1.1 download-retry (duration 00:00:01) [common]
46 20:34:37.903967 start: 1.2 download-retry (timeout 00:09:59) [common]
47 20:34:37.904284 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 20:34:37.904762 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/kernel/Image
49 20:34:37.905005 saving as /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/kernel/Image
50 20:34:37.905213 total size: 37812736 (36 MB)
51 20:34:37.905425 No compression specified
52 20:34:37.949510 progress 0 % (0 MB)
53 20:34:37.974046 progress 5 % (1 MB)
54 20:34:37.999904 progress 10 % (3 MB)
55 20:34:38.023205 progress 15 % (5 MB)
56 20:34:38.045693 progress 20 % (7 MB)
57 20:34:38.068733 progress 25 % (9 MB)
58 20:34:38.091651 progress 30 % (10 MB)
59 20:34:38.114331 progress 35 % (12 MB)
60 20:34:38.137327 progress 40 % (14 MB)
61 20:34:38.160505 progress 45 % (16 MB)
62 20:34:38.183172 progress 50 % (18 MB)
63 20:34:38.206187 progress 55 % (19 MB)
64 20:34:38.228882 progress 60 % (21 MB)
65 20:34:38.251617 progress 65 % (23 MB)
66 20:34:38.273977 progress 70 % (25 MB)
67 20:34:38.297085 progress 75 % (27 MB)
68 20:34:38.320482 progress 80 % (28 MB)
69 20:34:38.342861 progress 85 % (30 MB)
70 20:34:38.365632 progress 90 % (32 MB)
71 20:34:38.388429 progress 95 % (34 MB)
72 20:34:38.410386 progress 100 % (36 MB)
73 20:34:38.411131 36 MB downloaded in 0.51 s (71.28 MB/s)
74 20:34:38.411619 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:34:38.412474 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:34:38.412753 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:34:38.413018 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:34:38.413530 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:34:38.413814 saving as /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:34:38.414023 total size: 53209 (0 MB)
82 20:34:38.414232 No compression specified
83 20:34:38.452800 progress 61 % (0 MB)
84 20:34:38.453646 progress 100 % (0 MB)
85 20:34:38.454186 0 MB downloaded in 0.04 s (1.26 MB/s)
86 20:34:38.454649 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:34:38.455461 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:34:38.455727 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:34:38.456016 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:34:38.456538 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/modules.tar.xz
92 20:34:38.456794 saving as /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/modules/modules.tar
93 20:34:38.457000 total size: 11751036 (11 MB)
94 20:34:38.457212 Using unxz to decompress xz
95 20:34:38.494008 progress 0 % (0 MB)
96 20:34:38.561104 progress 5 % (0 MB)
97 20:34:38.646718 progress 10 % (1 MB)
98 20:34:38.728801 progress 15 % (1 MB)
99 20:34:38.811741 progress 20 % (2 MB)
100 20:34:38.889935 progress 25 % (2 MB)
101 20:34:38.971130 progress 30 % (3 MB)
102 20:34:39.048986 progress 35 % (3 MB)
103 20:34:39.131005 progress 40 % (4 MB)
104 20:34:39.216987 progress 45 % (5 MB)
105 20:34:39.298467 progress 50 % (5 MB)
106 20:34:39.381734 progress 55 % (6 MB)
107 20:34:39.463762 progress 60 % (6 MB)
108 20:34:39.547737 progress 65 % (7 MB)
109 20:34:39.630888 progress 70 % (7 MB)
110 20:34:39.708641 progress 75 % (8 MB)
111 20:34:39.791763 progress 80 % (8 MB)
112 20:34:39.871332 progress 85 % (9 MB)
113 20:34:39.944698 progress 90 % (10 MB)
114 20:34:40.043625 progress 95 % (10 MB)
115 20:34:40.140394 progress 100 % (11 MB)
116 20:34:40.153318 11 MB downloaded in 1.70 s (6.61 MB/s)
117 20:34:40.153925 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:34:40.154777 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:34:40.155054 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 20:34:40.155327 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 20:34:40.155576 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:34:40.155831 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 20:34:40.156703 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei
125 20:34:40.157536 makedir: /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin
126 20:34:40.158155 makedir: /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/tests
127 20:34:40.158750 makedir: /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/results
128 20:34:40.159356 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-add-keys
129 20:34:40.160325 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-add-sources
130 20:34:40.161252 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-background-process-start
131 20:34:40.162169 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-background-process-stop
132 20:34:40.163133 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-common-functions
133 20:34:40.164064 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-echo-ipv4
134 20:34:40.164976 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-install-packages
135 20:34:40.165851 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-installed-packages
136 20:34:40.166712 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-os-build
137 20:34:40.167587 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-probe-channel
138 20:34:40.168503 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-probe-ip
139 20:34:40.169513 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-target-ip
140 20:34:40.170405 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-target-mac
141 20:34:40.171271 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-target-storage
142 20:34:40.172198 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-case
143 20:34:40.173099 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-event
144 20:34:40.173960 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-feedback
145 20:34:40.174825 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-raise
146 20:34:40.175681 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-reference
147 20:34:40.176624 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-runner
148 20:34:40.177502 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-set
149 20:34:40.178362 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-test-shell
150 20:34:40.179256 Updating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-install-packages (oe)
151 20:34:40.180236 Updating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/bin/lava-installed-packages (oe)
152 20:34:40.181064 Creating /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/environment
153 20:34:40.181766 LAVA metadata
154 20:34:40.182252 - LAVA_JOB_ID=914453
155 20:34:40.182691 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:34:40.183409 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:34:40.185274 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:34:40.185879 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:34:40.186298 skipped lava-vland-overlay
160 20:34:40.186794 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:34:40.187310 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:34:40.187743 skipped lava-multinode-overlay
163 20:34:40.188288 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:34:40.188814 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:34:40.189303 Loading test definitions
166 20:34:40.189860 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:34:40.190311 Using /lava-914453 at stage 0
168 20:34:40.192302 uuid=914453_1.5.2.4.1 testdef=None
169 20:34:40.192634 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:34:40.192924 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:34:40.194695 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:34:40.195531 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:34:40.197734 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:34:40.198613 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:34:40.200770 runner path: /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/0/tests/0_igt-gpu-panfrost test_uuid 914453_1.5.2.4.1
178 20:34:40.201360 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:34:40.202196 Creating lava-test-runner.conf files
181 20:34:40.202416 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/914453/lava-overlay-7yaupuei/lava-914453/0 for stage 0
182 20:34:40.202774 - 0_igt-gpu-panfrost
183 20:34:40.203147 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:34:40.203444 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:34:40.226875 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:34:40.227274 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:34:40.227563 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:34:40.227843 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:34:40.228159 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:34:47.187742 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 20:34:47.188276 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 20:34:47.188562 extracting modules file /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk
193 20:34:48.597250 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:34:48.597735 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 20:34:48.598013 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914453/compress-overlay-nou2eyjg/overlay-1.5.2.5.tar.gz to ramdisk
196 20:34:48.598228 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914453/compress-overlay-nou2eyjg/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk
197 20:34:48.627968 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:34:48.628398 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 20:34:48.628674 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 20:34:48.628900 Converting downloaded kernel to a uImage
201 20:34:48.629204 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/kernel/Image /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/kernel/uImage
202 20:34:49.026129 output: Image Name:
203 20:34:49.026540 output: Created: Wed Oct 30 20:34:48 2024
204 20:34:49.026752 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:34:49.026957 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
206 20:34:49.027158 output: Load Address: 01080000
207 20:34:49.027358 output: Entry Point: 01080000
208 20:34:49.027558 output:
209 20:34:49.027885 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:34:49.028199 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:34:49.028470 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 20:34:49.028726 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:34:49.028982 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 20:34:49.029235 Building ramdisk /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk
215 20:34:55.652783 >> 509009 blocks
216 20:35:16.101984 Adding RAMdisk u-boot header.
217 20:35:16.102678 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk.cpio.gz.uboot
218 20:35:16.790574 output: Image Name:
219 20:35:16.790988 output: Created: Wed Oct 30 20:35:16 2024
220 20:35:16.791199 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:35:16.791403 output: Data Size: 66430495 Bytes = 64873.53 KiB = 63.35 MiB
222 20:35:16.791603 output: Load Address: 00000000
223 20:35:16.791804 output: Entry Point: 00000000
224 20:35:16.792053 output:
225 20:35:16.793030 rename /var/lib/lava/dispatcher/tmp/914453/extract-overlay-ramdisk-mc3dt9hp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot
226 20:35:16.793742 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 20:35:16.794279 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 20:35:16.794799 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:21) [common]
229 20:35:16.795256 No LXC device requested
230 20:35:16.795782 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:35:16.796327 start: 1.7 deploy-device-env (timeout 00:09:21) [common]
232 20:35:16.796822 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:35:16.797230 Checking files for TFTP limit of 4294967296 bytes.
234 20:35:16.799852 end: 1 tftp-deploy (duration 00:00:40) [common]
235 20:35:16.800565 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:35:16.801156 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:35:16.801727 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:35:16.802280 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:35:16.802838 Using kernel file from prepare-kernel: 914453/tftp-deploy-6gs855oe/kernel/uImage
240 20:35:16.803519 substitutions:
241 20:35:16.804031 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:35:16.804490 - {DTB_ADDR}: 0x01070000
243 20:35:16.804907 - {DTB}: 914453/tftp-deploy-6gs855oe/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:35:16.805303 - {INITRD}: 914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot
245 20:35:16.805693 - {KERNEL_ADDR}: 0x01080000
246 20:35:16.806082 - {KERNEL}: 914453/tftp-deploy-6gs855oe/kernel/uImage
247 20:35:16.806475 - {LAVA_MAC}: None
248 20:35:16.806913 - {PRESEED_CONFIG}: None
249 20:35:16.807308 - {PRESEED_LOCAL}: None
250 20:35:16.807696 - {RAMDISK_ADDR}: 0x08000000
251 20:35:16.808117 - {RAMDISK}: 914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot
252 20:35:16.808513 - {ROOT_PART}: None
253 20:35:16.808901 - {ROOT}: None
254 20:35:16.809290 - {SERVER_IP}: 192.168.6.2
255 20:35:16.809681 - {TEE_ADDR}: 0x83000000
256 20:35:16.810067 - {TEE}: None
257 20:35:16.810454 Parsed boot commands:
258 20:35:16.810829 - setenv autoload no
259 20:35:16.811218 - setenv initrd_high 0xffffffff
260 20:35:16.811601 - setenv fdt_high 0xffffffff
261 20:35:16.812001 - dhcp
262 20:35:16.812392 - setenv serverip 192.168.6.2
263 20:35:16.812776 - tftpboot 0x01080000 914453/tftp-deploy-6gs855oe/kernel/uImage
264 20:35:16.813162 - tftpboot 0x08000000 914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot
265 20:35:16.813550 - tftpboot 0x01070000 914453/tftp-deploy-6gs855oe/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:35:16.813936 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:35:16.814324 - bootm 0x01080000 0x08000000 0x01070000
268 20:35:16.814837 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:35:16.816384 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:35:16.816826 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:35:16.831280 Setting prompt string to ['lava-test: # ']
273 20:35:16.832817 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:35:16.833418 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:35:16.833946 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:35:16.834460 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:35:16.835577 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:35:16.872098 >> OK - accepted request
279 20:35:16.874169 Returned 0 in 0 seconds
280 20:35:16.975076 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:35:16.976761 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:35:16.977327 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:35:16.977819 Setting prompt string to ['Hit any key to stop autoboot']
285 20:35:16.978263 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:35:16.979837 Trying 192.168.56.21...
287 20:35:16.980333 Connected to conserv1.
288 20:35:16.980742 Escape character is '^]'.
289 20:35:16.981144
290 20:35:16.981562 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:35:16.981982
292 20:35:24.266369 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:35:24.266997 bl2_stage_init 0x01
294 20:35:24.267416 bl2_stage_init 0x81
295 20:35:24.272037 hw id: 0x0000 - pwm id 0x01
296 20:35:24.272590 bl2_stage_init 0xc1
297 20:35:24.273015 bl2_stage_init 0x02
298 20:35:24.273415
299 20:35:24.277586 L0:00000000
300 20:35:24.278082 L1:00000703
301 20:35:24.278481 L2:00008067
302 20:35:24.278871 L3:15000000
303 20:35:24.279277 S1:00000000
304 20:35:24.283157 B2:20282000
305 20:35:24.283655 B1:a0f83180
306 20:35:24.284095
307 20:35:24.284496 TE: 70119
308 20:35:24.284903
309 20:35:24.288635 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:35:24.289250
311 20:35:24.294299 Board ID = 1
312 20:35:24.294879 Set cpu clk to 24M
313 20:35:24.295370 Set clk81 to 24M
314 20:35:24.300003 Use GP1_pll as DSU clk.
315 20:35:24.300512 DSU clk: 1200 Mhz
316 20:35:24.300912 CPU clk: 1200 MHz
317 20:35:24.301299 Set clk81 to 166.6M
318 20:35:24.311065 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:35:24.311601 board id: 1
320 20:35:24.316565 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:35:24.328177 fw parse done
322 20:35:24.333176 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:35:24.375810 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:35:24.387644 PIEI prepare done
325 20:35:24.388165 fastboot data load
326 20:35:24.388583 fastboot data verify
327 20:35:24.393307 verify result: 266
328 20:35:24.398852 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:35:24.399317 LPDDR4 probe
330 20:35:24.399722 ddr clk to 1584MHz
331 20:35:24.405894 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:35:24.444225
333 20:35:24.444768 dmc_version 0001
334 20:35:24.450830 Check phy result
335 20:35:24.456739 INFO : End of CA training
336 20:35:24.457235 INFO : End of initialization
337 20:35:24.462327 INFO : Training has run successfully!
338 20:35:24.462807 Check phy result
339 20:35:24.467916 INFO : End of initialization
340 20:35:24.468502 INFO : End of read enable training
341 20:35:24.473643 INFO : End of fine write leveling
342 20:35:24.479155 INFO : End of Write leveling coarse delay
343 20:35:24.479637 INFO : Training has run successfully!
344 20:35:24.480085 Check phy result
345 20:35:24.484749 INFO : End of initialization
346 20:35:24.485209 INFO : End of read dq deskew training
347 20:35:24.490357 INFO : End of MPR read delay center optimization
348 20:35:24.495946 INFO : End of write delay center optimization
349 20:35:24.501650 INFO : End of read delay center optimization
350 20:35:24.502114 INFO : End of max read latency training
351 20:35:24.507123 INFO : Training has run successfully!
352 20:35:24.507577 1D training succeed
353 20:35:24.516264 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:35:24.564040 Check phy result
355 20:35:24.564640 INFO : End of initialization
356 20:35:24.586304 INFO : End of 2D read delay Voltage center optimization
357 20:35:24.605097 INFO : End of 2D read delay Voltage center optimization
358 20:35:24.656321 INFO : End of 2D write delay Voltage center optimization
359 20:35:24.706588 INFO : End of 2D write delay Voltage center optimization
360 20:35:24.712098 INFO : Training has run successfully!
361 20:35:24.712684
362 20:35:24.713105 channel==0
363 20:35:24.717709 RxClkDly_Margin_A0==78 ps 8
364 20:35:24.718210 TxDqDly_Margin_A0==98 ps 10
365 20:35:24.723229 RxClkDly_Margin_A1==78 ps 8
366 20:35:24.723799 TxDqDly_Margin_A1==98 ps 10
367 20:35:24.724319 TrainedVREFDQ_A0==74
368 20:35:24.728881 TrainedVREFDQ_A1==74
369 20:35:24.729494 VrefDac_Margin_A0==24
370 20:35:24.729957 DeviceVref_Margin_A0==40
371 20:35:24.734467 VrefDac_Margin_A1==23
372 20:35:24.734952 DeviceVref_Margin_A1==40
373 20:35:24.735355
374 20:35:24.735753
375 20:35:24.740053 channel==1
376 20:35:24.740552 RxClkDly_Margin_A0==78 ps 8
377 20:35:24.740953 TxDqDly_Margin_A0==98 ps 10
378 20:35:24.745681 RxClkDly_Margin_A1==78 ps 8
379 20:35:24.746160 TxDqDly_Margin_A1==88 ps 9
380 20:35:24.751234 TrainedVREFDQ_A0==75
381 20:35:24.751742 TrainedVREFDQ_A1==75
382 20:35:24.752192 VrefDac_Margin_A0==22
383 20:35:24.756827 DeviceVref_Margin_A0==39
384 20:35:24.757307 VrefDac_Margin_A1==22
385 20:35:24.762459 DeviceVref_Margin_A1==39
386 20:35:24.762944
387 20:35:24.763358 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:35:24.763758
389 20:35:24.796077 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 20:35:24.796726 2D training succeed
391 20:35:24.801639 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:35:24.807478 auto size-- 65535DDR cs0 size: 2048MB
393 20:35:24.808081 DDR cs1 size: 2048MB
394 20:35:24.812840 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:35:24.813365 cs0 DataBus test pass
396 20:35:24.818462 cs1 DataBus test pass
397 20:35:24.819015 cs0 AddrBus test pass
398 20:35:24.819434 cs1 AddrBus test pass
399 20:35:24.819899
400 20:35:24.824114 100bdlr_step_size ps== 478
401 20:35:24.824694 result report
402 20:35:24.829667 boot times 0Enable ddr reg access
403 20:35:24.833938 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:35:24.847735 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:35:25.503300 bl2z: ptr: 05129330, size: 00001e40
406 20:35:25.508767 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:35:25.509332 MVN_1=0x00000000
408 20:35:25.509742 MVN_2=0x00000000
409 20:35:25.520196 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:35:25.520803 OPS=0x04
411 20:35:25.521224 ring efuse init
412 20:35:25.523195 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:35:25.529210 [0.017319 Inits done]
414 20:35:25.529765 secure task start!
415 20:35:25.530159 high task start!
416 20:35:25.530616 low task start!
417 20:35:25.533436 run into bl31
418 20:35:25.542061 NOTICE: BL31: v1.3(release):4fc40b1
419 20:35:25.549506 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:35:25.550067 NOTICE: BL31: G12A normal boot!
421 20:35:25.565449 NOTICE: BL31: BL33 decompress pass
422 20:35:25.571111 ERROR: Error initializing runtime service opteed_fast
423 20:35:26.815083 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:35:26.815673 bl2_stage_init 0x01
425 20:35:26.816197 bl2_stage_init 0x81
426 20:35:26.820630 hw id: 0x0000 - pwm id 0x01
427 20:35:26.821083 bl2_stage_init 0xc1
428 20:35:26.826205 bl2_stage_init 0x02
429 20:35:26.826648
430 20:35:26.827045 L0:00000000
431 20:35:26.827434 L1:00000703
432 20:35:26.827816 L2:00008067
433 20:35:26.828240 L3:15000000
434 20:35:26.831870 S1:00000000
435 20:35:26.832415 B2:20282000
436 20:35:26.832814 B1:a0f83180
437 20:35:26.833260
438 20:35:26.833710 TE: 68096
439 20:35:26.834103
440 20:35:26.837449 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:35:26.837985
442 20:35:26.843042 Board ID = 1
443 20:35:26.843482 Set cpu clk to 24M
444 20:35:26.843950 Set clk81 to 24M
445 20:35:26.848663 Use GP1_pll as DSU clk.
446 20:35:26.849168 DSU clk: 1200 Mhz
447 20:35:26.849579 CPU clk: 1200 MHz
448 20:35:26.854227 Set clk81 to 166.6M
449 20:35:26.859834 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:35:26.860311 board id: 1
451 20:35:26.866035 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:35:26.877980 fw parse done
453 20:35:26.882981 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:35:26.926997 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:35:26.938209 PIEI prepare done
456 20:35:26.938729 fastboot data load
457 20:35:26.939134 fastboot data verify
458 20:35:26.943803 verify result: 266
459 20:35:26.949403 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:35:26.950119 LPDDR4 probe
461 20:35:26.950529 ddr clk to 1584MHz
462 20:35:28.316029 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 20:35:28.316456 bl2_stage_init 0x01
464 20:35:28.316670 bl2_stage_init 0x81
465 20:35:28.321496 hw id: 0x0000 - pwm id 0x01
466 20:35:28.321763 bl2_stage_init 0xc1
467 20:35:28.321968 bl2_stage_init 0x02
468 20:35:28.322165
469 20:35:28.327108 L0:00000000
470 20:35:28.327361 L1:00000703
471 20:35:28.327563 L2:00008067
472 20:35:28.327759 L3:15000000
473 20:35:28.327954 S1:00000000
474 20:35:28.332680 B2:20282000
475 20:35:28.332933 B1:a0f83180
476 20:35:28.333132
477 20:35:28.333328 TE: 69879
478 20:35:28.333522
479 20:35:28.338286 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 20:35:28.338544
481 20:35:28.343993 Board ID = 1
482 20:35:28.344248 Set cpu clk to 24M
483 20:35:28.344449 Set clk81 to 24M
484 20:35:28.349493 Use GP1_pll as DSU clk.
485 20:35:28.349743 DSU clk: 1200 Mhz
486 20:35:28.349943 CPU clk: 1200 MHz
487 20:35:28.350139 Set clk81 to 166.6M
488 20:35:28.360759 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 20:35:28.361034 board id: 1
490 20:35:28.367130 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 20:35:28.378037 fw parse done
492 20:35:28.384113 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 20:35:28.427126 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 20:35:28.438190 PIEI prepare done
495 20:35:28.438446 fastboot data load
496 20:35:28.438648 fastboot data verify
497 20:35:28.443768 verify result: 266
498 20:35:28.449375 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 20:35:28.449626 LPDDR4 probe
500 20:35:28.449825 ddr clk to 1584MHz
501 20:35:28.457414 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 20:35:28.766845
503 20:35:28.767272 dmc_version 0001
504 20:35:28.767494 Check phy result
505 20:35:28.767700 INFO : End of CA training
506 20:35:28.767905 INFO : End of initialization
507 20:35:28.768180 INFO : Training has run successfully!
508 20:35:28.768393 Check phy result
509 20:35:28.768592 INFO : End of initialization
510 20:35:28.768793 INFO : End of read enable training
511 20:35:28.768995 INFO : End of fine write leveling
512 20:35:28.769193 INFO : End of Write leveling coarse delay
513 20:35:28.769391 INFO : Training has run successfully!
514 20:35:28.769588 Check phy result
515 20:35:28.769780 INFO : End of initialization
516 20:35:28.769974 INFO : End of read dq deskew training
517 20:35:28.770165 INFO : End of MPR read delay center optimization
518 20:35:28.770360 INFO : End of write delay center optimization
519 20:35:28.770552 INFO : End of read delay center optimization
520 20:35:28.770746 INFO : End of max read latency training
521 20:35:28.770937 INFO : Training has run successfully!
522 20:35:28.771129 1D training succeed
523 20:35:28.771328 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 20:35:28.771546 Check phy result
525 20:35:28.771751 INFO : End of initialization
526 20:35:28.771945 INFO : End of 2D read delay Voltage center optimization
527 20:35:28.772172 INFO : End of 2D read delay Voltage center optimization
528 20:35:28.772673 INFO : End of 2D write delay Voltage center optimization
529 20:35:28.779753 INFO : End of 2D write delay Voltage center optimization
530 20:35:28.784050 INFO : Training has run successfully!
531 20:35:28.784366
532 20:35:28.784572 channel==0
533 20:35:28.789508 RxClkDly_Margin_A0==78 ps 8
534 20:35:28.789812 TxDqDly_Margin_A0==88 ps 9
535 20:35:28.795068 RxClkDly_Margin_A1==88 ps 9
536 20:35:28.795410 TxDqDly_Margin_A1==88 ps 9
537 20:35:28.795622 TrainedVREFDQ_A0==74
538 20:35:28.800666 TrainedVREFDQ_A1==74
539 20:35:28.800982 VrefDac_Margin_A0==23
540 20:35:28.801189 DeviceVref_Margin_A0==40
541 20:35:28.806593 VrefDac_Margin_A1==23
542 20:35:28.806900 DeviceVref_Margin_A1==40
543 20:35:28.807114
544 20:35:28.807317
545 20:35:28.807513 channel==1
546 20:35:28.811936 RxClkDly_Margin_A0==78 ps 8
547 20:35:28.812268 TxDqDly_Margin_A0==98 ps 10
548 20:35:28.817598 RxClkDly_Margin_A1==78 ps 8
549 20:35:28.817888 TxDqDly_Margin_A1==88 ps 9
550 20:35:28.823217 TrainedVREFDQ_A0==78
551 20:35:28.823544 TrainedVREFDQ_A1==75
552 20:35:28.823762 VrefDac_Margin_A0==22
553 20:35:28.828833 DeviceVref_Margin_A0==36
554 20:35:28.829163 VrefDac_Margin_A1==22
555 20:35:28.829368 DeviceVref_Margin_A1==39
556 20:35:28.834474
557 20:35:28.834776 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 20:35:28.834982
559 20:35:28.868160 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
560 20:35:28.868548 2D training succeed
561 20:35:28.873604 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 20:35:28.879173 auto size-- 65535DDR cs0 size: 2048MB
563 20:35:28.879470 DDR cs1 size: 2048MB
564 20:35:28.884693 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 20:35:28.884976 cs0 DataBus test pass
566 20:35:28.890472 cs1 DataBus test pass
567 20:35:28.890730 cs0 AddrBus test pass
568 20:35:28.890938 cs1 AddrBus test pass
569 20:35:28.891140
570 20:35:28.895975 100bdlr_step_size ps== 471
571 20:35:28.896264 result report
572 20:35:28.901622 boot times 0Enable ddr reg access
573 20:35:28.906541 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 20:35:28.920420 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 20:35:29.580756 bl2z: ptr: 05129330, size: 00001e40
576 20:35:29.589630 0.0;M3 CHK:0;cm4_sp_mode 0
577 20:35:29.589980 MVN_1=0x00000000
578 20:35:29.590186 MVN_2=0x00000000
579 20:35:29.601112 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 20:35:29.601455 OPS=0x04
581 20:35:29.601672 ring efuse init
582 20:35:29.603976 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 20:35:29.609764 [0.017354 Inits done]
584 20:35:29.610122 secure task start!
585 20:35:29.610334 high task start!
586 20:35:29.610534 low task start!
587 20:35:29.614036 run into bl31
588 20:35:29.622694 NOTICE: BL31: v1.3(release):4fc40b1
589 20:35:29.630477 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 20:35:29.630794 NOTICE: BL31: G12A normal boot!
591 20:35:29.646168 NOTICE: BL31: BL33 decompress pass
592 20:35:29.654458 ERROR: Error initializing runtime service opteed_fast
593 20:35:30.866197 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 20:35:30.866805 bl2_stage_init 0x01
595 20:35:30.867244 bl2_stage_init 0x81
596 20:35:30.871752 hw id: 0x0000 - pwm id 0x01
597 20:35:30.872261 bl2_stage_init 0xc1
598 20:35:30.877367 bl2_stage_init 0x02
599 20:35:30.877829
600 20:35:30.878261 L0:00000000
601 20:35:30.878684 L1:00000703
602 20:35:30.879108 L2:00008067
603 20:35:30.879529 L3:15000000
604 20:35:30.882943 S1:00000000
605 20:35:30.883404 B2:20282000
606 20:35:30.883831 B1:a0f83180
607 20:35:30.884291
608 20:35:30.884716 TE: 70495
609 20:35:30.885137
610 20:35:30.888547 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 20:35:30.889010
612 20:35:30.894119 Board ID = 1
613 20:35:30.894577 Set cpu clk to 24M
614 20:35:30.895003 Set clk81 to 24M
615 20:35:30.899748 Use GP1_pll as DSU clk.
616 20:35:30.900245 DSU clk: 1200 Mhz
617 20:35:30.900672 CPU clk: 1200 MHz
618 20:35:30.905351 Set clk81 to 166.6M
619 20:35:30.910954 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 20:35:30.911421 board id: 1
621 20:35:30.918152 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 20:35:30.928809 fw parse done
623 20:35:30.934789 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 20:35:30.977416 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 20:35:30.988356 PIEI prepare done
626 20:35:30.988829 fastboot data load
627 20:35:30.989263 fastboot data verify
628 20:35:30.993890 verify result: 266
629 20:35:30.999495 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 20:35:30.999959 LPDDR4 probe
631 20:35:31.000441 ddr clk to 1584MHz
632 20:35:31.007473 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 20:35:31.044760
634 20:35:31.045269 dmc_version 0001
635 20:35:31.051450 Check phy result
636 20:35:31.057364 INFO : End of CA training
637 20:35:31.057846 INFO : End of initialization
638 20:35:31.062941 INFO : Training has run successfully!
639 20:35:31.063425 Check phy result
640 20:35:31.068533 INFO : End of initialization
641 20:35:31.069009 INFO : End of read enable training
642 20:35:31.074134 INFO : End of fine write leveling
643 20:35:31.079729 INFO : End of Write leveling coarse delay
644 20:35:31.080249 INFO : Training has run successfully!
645 20:35:31.080685 Check phy result
646 20:35:31.085369 INFO : End of initialization
647 20:35:31.085847 INFO : End of read dq deskew training
648 20:35:31.090944 INFO : End of MPR read delay center optimization
649 20:35:31.096531 INFO : End of write delay center optimization
650 20:35:31.102127 INFO : End of read delay center optimization
651 20:35:31.102594 INFO : End of max read latency training
652 20:35:31.107735 INFO : Training has run successfully!
653 20:35:31.108249 1D training succeed
654 20:35:31.116909 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 20:35:31.164562 Check phy result
656 20:35:31.165099 INFO : End of initialization
657 20:35:31.186857 INFO : End of 2D read delay Voltage center optimization
658 20:35:31.206039 INFO : End of 2D read delay Voltage center optimization
659 20:35:31.257872 INFO : End of 2D write delay Voltage center optimization
660 20:35:31.307081 INFO : End of 2D write delay Voltage center optimization
661 20:35:31.312662 INFO : Training has run successfully!
662 20:35:31.313124
663 20:35:31.313557 channel==0
664 20:35:31.318259 RxClkDly_Margin_A0==78 ps 8
665 20:35:31.318763 TxDqDly_Margin_A0==98 ps 10
666 20:35:31.323876 RxClkDly_Margin_A1==88 ps 9
667 20:35:31.324411 TxDqDly_Margin_A1==98 ps 10
668 20:35:31.324842 TrainedVREFDQ_A0==75
669 20:35:31.329470 TrainedVREFDQ_A1==75
670 20:35:31.329939 VrefDac_Margin_A0==24
671 20:35:31.330364 DeviceVref_Margin_A0==39
672 20:35:31.335067 VrefDac_Margin_A1==23
673 20:35:31.335525 DeviceVref_Margin_A1==39
674 20:35:31.335952
675 20:35:31.336411
676 20:35:31.340666 channel==1
677 20:35:31.341123 RxClkDly_Margin_A0==78 ps 8
678 20:35:31.341549 TxDqDly_Margin_A0==88 ps 9
679 20:35:31.346233 RxClkDly_Margin_A1==78 ps 8
680 20:35:31.346697 TxDqDly_Margin_A1==88 ps 9
681 20:35:31.351838 TrainedVREFDQ_A0==75
682 20:35:31.352335 TrainedVREFDQ_A1==77
683 20:35:31.352765 VrefDac_Margin_A0==22
684 20:35:31.357456 DeviceVref_Margin_A0==38
685 20:35:31.357912 VrefDac_Margin_A1==20
686 20:35:31.363075 DeviceVref_Margin_A1==37
687 20:35:31.363528
688 20:35:31.363955 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 20:35:31.364422
690 20:35:31.396685 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
691 20:35:31.397244 2D training succeed
692 20:35:31.402293 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 20:35:31.407901 auto size-- 65535DDR cs0 size: 2048MB
694 20:35:31.408453 DDR cs1 size: 2048MB
695 20:35:31.413482 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 20:35:31.413988 cs0 DataBus test pass
697 20:35:31.419222 cs1 DataBus test pass
698 20:35:31.419886 cs0 AddrBus test pass
699 20:35:31.420399 cs1 AddrBus test pass
700 20:35:31.420997
701 20:35:31.424806 100bdlr_step_size ps== 478
702 20:35:31.425358 result report
703 20:35:31.430414 boot times 0Enable ddr reg access
704 20:35:31.435600 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 20:35:31.449368 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 20:35:32.105695 bl2z: ptr: 05129330, size: 00001e40
707 20:35:32.112742 0.0;M3 CHK:0;cm4_sp_mode 0
708 20:35:32.113267 MVN_1=0x00000000
709 20:35:32.113704 MVN_2=0x00000000
710 20:35:32.124210 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 20:35:32.124720 OPS=0x04
712 20:35:32.125161 ring efuse init
713 20:35:32.129841 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 20:35:32.130347 [0.017319 Inits done]
715 20:35:32.130782 secure task start!
716 20:35:32.137480 high task start!
717 20:35:32.137983 low task start!
718 20:35:32.138425 run into bl31
719 20:35:32.146433 NOTICE: BL31: v1.3(release):4fc40b1
720 20:35:32.153947 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 20:35:32.154495 NOTICE: BL31: G12A normal boot!
722 20:35:32.169550 NOTICE: BL31: BL33 decompress pass
723 20:35:32.175187 ERROR: Error initializing runtime service opteed_fast
724 20:35:32.970550
725 20:35:32.971131
726 20:35:32.975974 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 20:35:32.976487
728 20:35:32.979430 Model: Libre Computer AML-S905D3-CC Solitude
729 20:35:33.126408 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 20:35:33.141788 DRAM: 2 GiB (effective 3.8 GiB)
731 20:35:33.242806 Core: 406 devices, 33 uclasses, devicetree: separate
732 20:35:33.248655 WDT: Not starting watchdog@f0d0
733 20:35:33.273697 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 20:35:33.285951 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 20:35:33.290918 ** Bad device specification mmc 0 **
736 20:35:33.301000 Card did not respond to voltage select! : -110
737 20:35:33.308490 ** Bad device specification mmc 0 **
738 20:35:33.308958 Couldn't find partition mmc 0
739 20:35:33.316962 Card did not respond to voltage select! : -110
740 20:35:33.322504 ** Bad device specification mmc 0 **
741 20:35:33.323024 Couldn't find partition mmc 0
742 20:35:33.327554 Error: could not access storage.
743 20:35:33.624016 Net: eth0: ethernet@ff3f0000
744 20:35:33.624621 starting USB...
745 20:35:33.868672 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 20:35:33.869192 Starting the controller
747 20:35:33.875607 USB XHCI 1.10
748 20:35:35.432267 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 20:35:35.440403 scanning usb for storage devices... 0 Storage Device(s) found
751 20:35:35.491923 Hit any key to stop autoboot: 1
752 20:35:35.492811 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 20:35:35.493445 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 20:35:35.493955 Setting prompt string to ['=>']
755 20:35:35.494470 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 20:35:35.506489 0
757 20:35:35.507408 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 20:35:35.608715 => setenv autoload no
760 20:35:35.609411 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 20:35:35.614659 setenv autoload no
763 20:35:35.716156 => setenv initrd_high 0xffffffff
764 20:35:35.716797 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 20:35:35.721387 setenv initrd_high 0xffffffff
767 20:35:35.822862 => setenv fdt_high 0xffffffff
768 20:35:35.823525 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 20:35:35.828171 setenv fdt_high 0xffffffff
771 20:35:35.929674 => dhcp
772 20:35:35.930319 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 20:35:35.933657 dhcp
774 20:35:36.439944 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 20:35:36.440524 Speed: 1000, full duplex
776 20:35:36.440976 BOOTP broadcast 1
777 20:35:36.457399 DHCP client bound to address 192.168.6.21 (16 ms)
779 20:35:36.558892 => setenv serverip 192.168.6.2
780 20:35:36.559568 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
781 20:35:36.564190 setenv serverip 192.168.6.2
783 20:35:36.665697 => tftpboot 0x01080000 914453/tftp-deploy-6gs855oe/kernel/uImage
784 20:35:36.666388 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
785 20:35:36.673240 tftpboot 0x01080000 914453/tftp-deploy-6gs855oe/kernel/uImage
786 20:35:36.673733 Speed: 1000, full duplex
787 20:35:36.674180 Using ethernet@ff3f0000 device
788 20:35:36.678710 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 20:35:36.684337 Filename '914453/tftp-deploy-6gs855oe/kernel/uImage'.
790 20:35:36.688147 Load address: 0x1080000
791 20:35:38.974150 Loading: *################################################## 36.1 MiB
792 20:35:38.974783 15.8 MiB/s
793 20:35:38.975251 done
794 20:35:38.978596 Bytes transferred = 37812800 (240fa40 hex)
796 20:35:39.080182 => tftpboot 0x08000000 914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot
797 20:35:39.080910 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
798 20:35:39.087653 tftpboot 0x08000000 914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot
799 20:35:39.088182 Speed: 1000, full duplex
800 20:35:39.088613 Using ethernet@ff3f0000 device
801 20:35:39.093137 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 20:35:39.102923 Filename '914453/tftp-deploy-6gs855oe/ramdisk/ramdisk.cpio.gz.uboot'.
803 20:35:39.103390 Load address: 0x8000000
804 20:35:48.964541 Loading: *#################################T ################ UDP wrong checksum 0000000f 00003e4a
805 20:35:53.965367 T UDP wrong checksum 0000000f 00003e4a
806 20:36:03.967461 T T UDP wrong checksum 0000000f 00003e4a
807 20:36:23.971615 T T T T UDP wrong checksum 0000000f 00003e4a
808 20:36:38.975432 T T
809 20:36:38.976115 Retry count exceeded; starting again
811 20:36:38.977652 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
814 20:36:38.979691 end: 2.4 uboot-commands (duration 00:01:22) [common]
816 20:36:38.981424 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
818 20:36:38.982570 end: 2 uboot-action (duration 00:01:22) [common]
820 20:36:38.984232 Cleaning after the job
821 20:36:38.984831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/ramdisk
822 20:36:38.986218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/kernel
823 20:36:39.022832 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/dtb
824 20:36:39.024264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914453/tftp-deploy-6gs855oe/modules
825 20:36:39.036769 start: 4.1 power-off (timeout 00:00:30) [common]
826 20:36:39.037384 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
827 20:36:39.071841 >> OK - accepted request
828 20:36:39.073932 Returned 0 in 0 seconds
829 20:36:39.175111 end: 4.1 power-off (duration 00:00:00) [common]
831 20:36:39.177018 start: 4.2 read-feedback (timeout 00:10:00) [common]
832 20:36:39.178235 Listened to connection for namespace 'common' for up to 1s
833 20:36:40.179031 Finalising connection for namespace 'common'
834 20:36:40.179826 Disconnecting from shell: Finalise
835 20:36:40.180443 =>
836 20:36:40.281452 end: 4.2 read-feedback (duration 00:00:01) [common]
837 20:36:40.282149 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/914453
838 20:36:40.895778 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/914453
839 20:36:40.896417 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.