Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:37:57.070373 lava-dispatcher, installed at version: 2024.01
2 20:37:57.071169 start: 0 validate
3 20:37:57.071663 Start time: 2024-10-30 20:37:57.071632+00:00 (UTC)
4 20:37:57.072222 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:37:57.072779 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:37:57.108520 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:37:57.109058 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 20:37:57.139290 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:37:57.139897 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:37:57.170404 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:37:57.170926 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:37:57.201737 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:37:57.202251 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 20:37:57.248667 validate duration: 0.18
16 20:37:57.249530 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:37:57.249861 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:37:57.250181 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:37:57.250775 Not decompressing ramdisk as can be used compressed.
20 20:37:57.251236 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 20:37:57.251520 saving as /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/ramdisk/initrd.cpio.gz
22 20:37:57.251782 total size: 5628169 (5 MB)
23 20:37:57.286538 progress 0 % (0 MB)
24 20:37:57.290588 progress 5 % (0 MB)
25 20:37:57.294748 progress 10 % (0 MB)
26 20:37:57.298544 progress 15 % (0 MB)
27 20:37:57.302725 progress 20 % (1 MB)
28 20:37:57.306432 progress 25 % (1 MB)
29 20:37:57.310474 progress 30 % (1 MB)
30 20:37:57.314573 progress 35 % (1 MB)
31 20:37:57.318186 progress 40 % (2 MB)
32 20:37:57.322143 progress 45 % (2 MB)
33 20:37:57.325766 progress 50 % (2 MB)
34 20:37:57.329797 progress 55 % (2 MB)
35 20:37:57.333842 progress 60 % (3 MB)
36 20:37:57.337413 progress 65 % (3 MB)
37 20:37:57.341470 progress 70 % (3 MB)
38 20:37:57.345063 progress 75 % (4 MB)
39 20:37:57.349040 progress 80 % (4 MB)
40 20:37:57.352643 progress 85 % (4 MB)
41 20:37:57.356573 progress 90 % (4 MB)
42 20:37:57.360204 progress 95 % (5 MB)
43 20:37:57.363442 progress 100 % (5 MB)
44 20:37:57.364124 5 MB downloaded in 0.11 s (47.79 MB/s)
45 20:37:57.364701 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:37:57.365630 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:37:57.365945 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:37:57.366231 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:37:57.366726 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/kernel/Image
51 20:37:57.366989 saving as /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/kernel/Image
52 20:37:57.367211 total size: 37812736 (36 MB)
53 20:37:57.367428 No compression specified
54 20:37:57.402442 progress 0 % (0 MB)
55 20:37:57.426046 progress 5 % (1 MB)
56 20:37:57.449621 progress 10 % (3 MB)
57 20:37:57.473327 progress 15 % (5 MB)
58 20:37:57.496452 progress 20 % (7 MB)
59 20:37:57.521052 progress 25 % (9 MB)
60 20:37:57.544784 progress 30 % (10 MB)
61 20:37:57.567768 progress 35 % (12 MB)
62 20:37:57.590952 progress 40 % (14 MB)
63 20:37:57.614645 progress 45 % (16 MB)
64 20:37:57.637521 progress 50 % (18 MB)
65 20:37:57.660758 progress 55 % (19 MB)
66 20:37:57.684087 progress 60 % (21 MB)
67 20:37:57.707404 progress 65 % (23 MB)
68 20:37:57.730318 progress 70 % (25 MB)
69 20:37:57.753553 progress 75 % (27 MB)
70 20:37:57.776595 progress 80 % (28 MB)
71 20:37:57.799365 progress 85 % (30 MB)
72 20:37:57.822687 progress 90 % (32 MB)
73 20:37:57.845844 progress 95 % (34 MB)
74 20:37:57.867962 progress 100 % (36 MB)
75 20:37:57.868766 36 MB downloaded in 0.50 s (71.90 MB/s)
76 20:37:57.869255 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:37:57.870073 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:37:57.870348 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:37:57.870615 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:37:57.871083 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:37:57.871360 saving as /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:37:57.871567 total size: 54703 (0 MB)
84 20:37:57.871777 No compression specified
85 20:37:57.914444 progress 59 % (0 MB)
86 20:37:57.915274 progress 100 % (0 MB)
87 20:37:57.915831 0 MB downloaded in 0.04 s (1.18 MB/s)
88 20:37:57.916378 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:37:57.917205 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:37:57.917466 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:37:57.917731 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:37:57.918188 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 20:37:57.918469 saving as /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/nfsrootfs/full.rootfs.tar
95 20:37:57.918678 total size: 120894716 (115 MB)
96 20:37:57.918890 Using unxz to decompress xz
97 20:37:57.953296 progress 0 % (0 MB)
98 20:37:58.755935 progress 5 % (5 MB)
99 20:37:59.614766 progress 10 % (11 MB)
100 20:38:00.416136 progress 15 % (17 MB)
101 20:38:01.157688 progress 20 % (23 MB)
102 20:38:01.757684 progress 25 % (28 MB)
103 20:38:02.632398 progress 30 % (34 MB)
104 20:38:03.535256 progress 35 % (40 MB)
105 20:38:03.908386 progress 40 % (46 MB)
106 20:38:04.317385 progress 45 % (51 MB)
107 20:38:05.179406 progress 50 % (57 MB)
108 20:38:06.076200 progress 55 % (63 MB)
109 20:38:06.872543 progress 60 % (69 MB)
110 20:38:07.640576 progress 65 % (74 MB)
111 20:38:08.435428 progress 70 % (80 MB)
112 20:38:09.272595 progress 75 % (86 MB)
113 20:38:10.069660 progress 80 % (92 MB)
114 20:38:10.845040 progress 85 % (98 MB)
115 20:38:11.762395 progress 90 % (103 MB)
116 20:38:12.586989 progress 95 % (109 MB)
117 20:38:13.424895 progress 100 % (115 MB)
118 20:38:13.441289 115 MB downloaded in 15.52 s (7.43 MB/s)
119 20:38:13.442431 end: 1.4.1 http-download (duration 00:00:16) [common]
121 20:38:13.444397 end: 1.4 download-retry (duration 00:00:16) [common]
122 20:38:13.445003 start: 1.5 download-retry (timeout 00:09:44) [common]
123 20:38:13.445580 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 20:38:13.446803 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/modules.tar.xz
125 20:38:13.447332 saving as /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/modules/modules.tar
126 20:38:13.447774 total size: 11751036 (11 MB)
127 20:38:13.448284 Using unxz to decompress xz
128 20:38:13.493585 progress 0 % (0 MB)
129 20:38:13.563450 progress 5 % (0 MB)
130 20:38:13.641119 progress 10 % (1 MB)
131 20:38:13.725081 progress 15 % (1 MB)
132 20:38:13.808582 progress 20 % (2 MB)
133 20:38:13.886976 progress 25 % (2 MB)
134 20:38:13.968467 progress 30 % (3 MB)
135 20:38:14.046118 progress 35 % (3 MB)
136 20:38:14.130202 progress 40 % (4 MB)
137 20:38:14.216312 progress 45 % (5 MB)
138 20:38:14.298711 progress 50 % (5 MB)
139 20:38:14.382931 progress 55 % (6 MB)
140 20:38:14.467538 progress 60 % (6 MB)
141 20:38:14.552081 progress 65 % (7 MB)
142 20:38:14.637370 progress 70 % (7 MB)
143 20:38:14.716125 progress 75 % (8 MB)
144 20:38:14.800548 progress 80 % (8 MB)
145 20:38:14.881295 progress 85 % (9 MB)
146 20:38:14.955326 progress 90 % (10 MB)
147 20:38:15.054462 progress 95 % (10 MB)
148 20:38:15.150336 progress 100 % (11 MB)
149 20:38:15.164037 11 MB downloaded in 1.72 s (6.53 MB/s)
150 20:38:15.165018 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:38:15.166805 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:38:15.167372 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 20:38:15.167936 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 20:38:32.667783 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/914538/extract-nfsrootfs-lcc7qs41
156 20:38:32.668423 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 20:38:32.668742 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 20:38:32.669381 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1
159 20:38:32.669860 makedir: /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin
160 20:38:32.670241 makedir: /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/tests
161 20:38:32.670629 makedir: /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/results
162 20:38:32.670997 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-add-keys
163 20:38:32.671617 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-add-sources
164 20:38:32.672197 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-background-process-start
165 20:38:32.672769 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-background-process-stop
166 20:38:32.673329 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-common-functions
167 20:38:32.673819 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-echo-ipv4
168 20:38:32.674295 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-install-packages
169 20:38:32.674762 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-installed-packages
170 20:38:32.675229 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-os-build
171 20:38:32.675727 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-probe-channel
172 20:38:32.676268 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-probe-ip
173 20:38:32.676753 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-target-ip
174 20:38:32.677226 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-target-mac
175 20:38:32.677723 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-target-storage
176 20:38:32.678202 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-case
177 20:38:32.678674 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-event
178 20:38:32.679133 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-feedback
179 20:38:32.679634 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-raise
180 20:38:32.680191 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-reference
181 20:38:32.680681 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-runner
182 20:38:32.681160 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-set
183 20:38:32.681636 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-test-shell
184 20:38:32.682123 Updating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-add-keys (debian)
185 20:38:32.682648 Updating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-add-sources (debian)
186 20:38:32.683145 Updating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-install-packages (debian)
187 20:38:32.683632 Updating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-installed-packages (debian)
188 20:38:32.684144 Updating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/bin/lava-os-build (debian)
189 20:38:32.684582 Creating /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/environment
190 20:38:32.684946 LAVA metadata
191 20:38:32.685202 - LAVA_JOB_ID=914538
192 20:38:32.685416 - LAVA_DISPATCHER_IP=192.168.6.2
193 20:38:32.685779 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 20:38:32.686731 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 20:38:32.687037 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 20:38:32.687247 skipped lava-vland-overlay
197 20:38:32.687487 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 20:38:32.687739 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 20:38:32.687956 skipped lava-multinode-overlay
200 20:38:32.688264 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 20:38:32.688515 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 20:38:32.688763 Loading test definitions
203 20:38:32.689038 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 20:38:32.689256 Using /lava-914538 at stage 0
205 20:38:32.690426 uuid=914538_1.6.2.4.1 testdef=None
206 20:38:32.690739 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 20:38:32.691003 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 20:38:32.692576 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 20:38:32.693352 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 20:38:32.695247 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 20:38:32.696085 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 20:38:32.697891 runner path: /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/0/tests/0_timesync-off test_uuid 914538_1.6.2.4.1
215 20:38:32.698427 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 20:38:32.699224 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 20:38:32.699445 Using /lava-914538 at stage 0
219 20:38:32.699790 Fetching tests from https://github.com/kernelci/test-definitions.git
220 20:38:32.700104 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/0/tests/1_kselftest-alsa'
221 20:38:36.203755 Running '/usr/bin/git checkout kernelci.org
222 20:38:36.430273 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 20:38:36.431711 uuid=914538_1.6.2.4.5 testdef=None
224 20:38:36.432077 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 20:38:36.432828 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 20:38:36.435637 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 20:38:36.436475 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 20:38:36.440160 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 20:38:36.441030 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 20:38:36.444594 runner path: /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/0/tests/1_kselftest-alsa test_uuid 914538_1.6.2.4.5
234 20:38:36.444877 BOARD='meson-g12b-a311d-libretech-cc'
235 20:38:36.445082 BRANCH='mainline'
236 20:38:36.445278 SKIPFILE='/dev/null'
237 20:38:36.445473 SKIP_INSTALL='True'
238 20:38:36.445669 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/kselftest.tar.xz'
239 20:38:36.445866 TST_CASENAME=''
240 20:38:36.446059 TST_CMDFILES='alsa'
241 20:38:36.446597 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 20:38:36.447368 Creating lava-test-runner.conf files
244 20:38:36.447570 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/914538/lava-overlay-gibprrj1/lava-914538/0 for stage 0
245 20:38:36.447905 - 0_timesync-off
246 20:38:36.448163 - 1_kselftest-alsa
247 20:38:36.448493 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 20:38:36.448770 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 20:38:59.932925 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 20:38:59.933553 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 20:38:59.933943 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 20:38:59.934340 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 20:38:59.934724 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 20:39:00.555002 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 20:39:00.555493 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 20:39:00.555769 extracting modules file /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914538/extract-nfsrootfs-lcc7qs41
257 20:39:01.946812 extracting modules file /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914538/extract-overlay-ramdisk-650tknb3/ramdisk
258 20:39:03.341760 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 20:39:03.342246 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 20:39:03.342544 [common] Applying overlay to NFS
261 20:39:03.342777 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914538/compress-overlay-zuhvpdim/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/914538/extract-nfsrootfs-lcc7qs41
262 20:39:06.112742 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 20:39:06.113237 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 20:39:06.113545 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 20:39:06.113811 Converting downloaded kernel to a uImage
266 20:39:06.114155 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/kernel/Image /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/kernel/uImage
267 20:39:06.535689 output: Image Name:
268 20:39:06.536140 output: Created: Wed Oct 30 20:39:06 2024
269 20:39:06.536355 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 20:39:06.536561 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
271 20:39:06.536763 output: Load Address: 01080000
272 20:39:06.536963 output: Entry Point: 01080000
273 20:39:06.537161 output:
274 20:39:06.537496 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 20:39:06.537766 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 20:39:06.538038 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 20:39:06.538294 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 20:39:06.538553 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 20:39:06.538808 Building ramdisk /var/lib/lava/dispatcher/tmp/914538/extract-overlay-ramdisk-650tknb3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/914538/extract-overlay-ramdisk-650tknb3/ramdisk
280 20:39:08.795437 >> 173422 blocks
281 20:39:16.529732 Adding RAMdisk u-boot header.
282 20:39:16.530425 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/914538/extract-overlay-ramdisk-650tknb3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/914538/extract-overlay-ramdisk-650tknb3/ramdisk.cpio.gz.uboot
283 20:39:16.790352 output: Image Name:
284 20:39:16.790753 output: Created: Wed Oct 30 20:39:16 2024
285 20:39:16.790964 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 20:39:16.791169 output: Data Size: 24145683 Bytes = 23579.77 KiB = 23.03 MiB
287 20:39:16.791369 output: Load Address: 00000000
288 20:39:16.791569 output: Entry Point: 00000000
289 20:39:16.791768 output:
290 20:39:16.792511 rename /var/lib/lava/dispatcher/tmp/914538/extract-overlay-ramdisk-650tknb3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot
291 20:39:16.793232 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 20:39:16.793772 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 20:39:16.794293 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 20:39:16.794745 No LXC device requested
295 20:39:16.795255 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 20:39:16.795766 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 20:39:16.796301 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 20:39:16.796713 Checking files for TFTP limit of 4294967296 bytes.
299 20:39:16.799428 end: 1 tftp-deploy (duration 00:01:20) [common]
300 20:39:16.800065 start: 2 uboot-action (timeout 00:05:00) [common]
301 20:39:16.800605 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 20:39:16.801099 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 20:39:16.801601 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 20:39:16.802128 Using kernel file from prepare-kernel: 914538/tftp-deploy-mnlx03pg/kernel/uImage
305 20:39:16.802755 substitutions:
306 20:39:16.803160 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 20:39:16.803558 - {DTB_ADDR}: 0x01070000
308 20:39:16.803955 - {DTB}: 914538/tftp-deploy-mnlx03pg/dtb/meson-g12b-a311d-libretech-cc.dtb
309 20:39:16.804410 - {INITRD}: 914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot
310 20:39:16.804817 - {KERNEL_ADDR}: 0x01080000
311 20:39:16.805207 - {KERNEL}: 914538/tftp-deploy-mnlx03pg/kernel/uImage
312 20:39:16.805597 - {LAVA_MAC}: None
313 20:39:16.806026 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/914538/extract-nfsrootfs-lcc7qs41
314 20:39:16.806421 - {NFS_SERVER_IP}: 192.168.6.2
315 20:39:16.806806 - {PRESEED_CONFIG}: None
316 20:39:16.807195 - {PRESEED_LOCAL}: None
317 20:39:16.807584 - {RAMDISK_ADDR}: 0x08000000
318 20:39:16.807967 - {RAMDISK}: 914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot
319 20:39:16.808385 - {ROOT_PART}: None
320 20:39:16.808770 - {ROOT}: None
321 20:39:16.809153 - {SERVER_IP}: 192.168.6.2
322 20:39:16.809533 - {TEE_ADDR}: 0x83000000
323 20:39:16.809915 - {TEE}: None
324 20:39:16.810299 Parsed boot commands:
325 20:39:16.810672 - setenv autoload no
326 20:39:16.811056 - setenv initrd_high 0xffffffff
327 20:39:16.811434 - setenv fdt_high 0xffffffff
328 20:39:16.811809 - dhcp
329 20:39:16.812244 - setenv serverip 192.168.6.2
330 20:39:16.812633 - tftpboot 0x01080000 914538/tftp-deploy-mnlx03pg/kernel/uImage
331 20:39:16.813022 - tftpboot 0x08000000 914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot
332 20:39:16.813407 - tftpboot 0x01070000 914538/tftp-deploy-mnlx03pg/dtb/meson-g12b-a311d-libretech-cc.dtb
333 20:39:16.813792 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/914538/extract-nfsrootfs-lcc7qs41,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 20:39:16.814186 - bootm 0x01080000 0x08000000 0x01070000
335 20:39:16.814692 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 20:39:16.816201 start: 2.3 connect-device (timeout 00:05:00) [common]
338 20:39:16.816623 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 20:39:16.831571 Setting prompt string to ['lava-test: # ']
340 20:39:16.833136 end: 2.3 connect-device (duration 00:00:00) [common]
341 20:39:16.833741 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 20:39:16.834298 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 20:39:16.834819 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 20:39:16.835940 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 20:39:16.870957 >> OK - accepted request
346 20:39:16.873046 Returned 0 in 0 seconds
347 20:39:16.974103 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 20:39:16.975684 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 20:39:16.976280 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 20:39:16.976784 Setting prompt string to ['Hit any key to stop autoboot']
352 20:39:16.977228 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 20:39:16.978766 Trying 192.168.56.21...
354 20:39:16.979235 Connected to conserv1.
355 20:39:16.979640 Escape character is '^]'.
356 20:39:16.980081
357 20:39:16.980502 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 20:39:16.980916
359 20:39:27.642207 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 20:39:27.642834 bl2_stage_init 0x01
361 20:39:27.643250 bl2_stage_init 0x81
362 20:39:27.647711 hw id: 0x0000 - pwm id 0x01
363 20:39:27.648314 bl2_stage_init 0xc1
364 20:39:27.648742 bl2_stage_init 0x02
365 20:39:27.649149
366 20:39:27.653357 L0:00000000
367 20:39:27.653868 L1:20000703
368 20:39:27.654274 L2:00008067
369 20:39:27.654675 L3:14000000
370 20:39:27.658940 B2:00402000
371 20:39:27.659442 B1:e0f83180
372 20:39:27.659834
373 20:39:27.660262 TE: 58124
374 20:39:27.660655
375 20:39:27.664503 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 20:39:27.664991
377 20:39:27.665386 Board ID = 1
378 20:39:27.670135 Set A53 clk to 24M
379 20:39:27.670623 Set A73 clk to 24M
380 20:39:27.671011 Set clk81 to 24M
381 20:39:27.675734 A53 clk: 1200 MHz
382 20:39:27.676262 A73 clk: 1200 MHz
383 20:39:27.676661 CLK81: 166.6M
384 20:39:27.677043 smccc: 00012a92
385 20:39:27.681322 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 20:39:27.686911 board id: 1
387 20:39:27.691917 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 20:39:27.703467 fw parse done
389 20:39:27.708518 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 20:39:27.752056 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 20:39:27.762977 PIEI prepare done
392 20:39:27.763498 fastboot data load
393 20:39:27.763892 fastboot data verify
394 20:39:27.768532 verify result: 266
395 20:39:27.774181 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 20:39:27.774689 LPDDR4 probe
397 20:39:27.775083 ddr clk to 1584MHz
398 20:39:27.782163 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 20:39:27.829643
400 20:39:27.830125 dmc_version 0001
401 20:39:27.830677 Check phy result
402 20:39:27.830915 INFO : End of CA training
403 20:39:27.835915 INFO : End of initialization
404 20:39:27.836339 INFO : Training has run successfully!
405 20:39:27.841457 Check phy result
406 20:39:27.841764 INFO : End of initialization
407 20:39:27.847197 INFO : End of read enable training
408 20:39:27.847705 INFO : End of fine write leveling
409 20:39:27.852816 INFO : End of Write leveling coarse delay
410 20:39:27.853502 INFO : Training has run successfully!
411 20:39:27.858527 Check phy result
412 20:39:27.859186 INFO : End of initialization
413 20:39:27.864044 INFO : End of read dq deskew training
414 20:39:27.869619 INFO : End of MPR read delay center optimization
415 20:39:27.870303 INFO : End of write delay center optimization
416 20:39:27.875209 INFO : End of read delay center optimization
417 20:39:27.880779 INFO : End of max read latency training
418 20:39:27.881281 INFO : Training has run successfully!
419 20:39:27.886352 1D training succeed
420 20:39:27.891601 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 20:39:27.939380 Check phy result
422 20:39:27.940162 INFO : End of initialization
423 20:39:27.960891 INFO : End of 2D read delay Voltage center optimization
424 20:39:27.981182 INFO : End of 2D read delay Voltage center optimization
425 20:39:28.033147 INFO : End of 2D write delay Voltage center optimization
426 20:39:28.082522 INFO : End of 2D write delay Voltage center optimization
427 20:39:28.088169 INFO : Training has run successfully!
428 20:39:28.088819
429 20:39:28.089376 channel==0
430 20:39:28.093705 RxClkDly_Margin_A0==88 ps 9
431 20:39:28.094344 TxDqDly_Margin_A0==98 ps 10
432 20:39:28.099438 RxClkDly_Margin_A1==88 ps 9
433 20:39:28.100110 TxDqDly_Margin_A1==98 ps 10
434 20:39:28.100666 TrainedVREFDQ_A0==74
435 20:39:28.104850 TrainedVREFDQ_A1==74
436 20:39:28.105475 VrefDac_Margin_A0==25
437 20:39:28.106016 DeviceVref_Margin_A0==40
438 20:39:28.110693 VrefDac_Margin_A1==25
439 20:39:28.111314 DeviceVref_Margin_A1==40
440 20:39:28.111854
441 20:39:28.112444
442 20:39:28.116121 channel==1
443 20:39:28.116749 RxClkDly_Margin_A0==98 ps 10
444 20:39:28.117287 TxDqDly_Margin_A0==98 ps 10
445 20:39:28.121671 RxClkDly_Margin_A1==98 ps 10
446 20:39:28.122309 TxDqDly_Margin_A1==88 ps 9
447 20:39:28.127206 TrainedVREFDQ_A0==77
448 20:39:28.127864 TrainedVREFDQ_A1==77
449 20:39:28.128459 VrefDac_Margin_A0==22
450 20:39:28.132897 DeviceVref_Margin_A0==37
451 20:39:28.133529 VrefDac_Margin_A1==22
452 20:39:28.138496 DeviceVref_Margin_A1==37
453 20:39:28.139128
454 20:39:28.139679 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 20:39:28.144123
456 20:39:28.172067 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 20:39:28.172827 2D training succeed
458 20:39:28.177670 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 20:39:28.183264 auto size-- 65535DDR cs0 size: 2048MB
460 20:39:28.183921 DDR cs1 size: 2048MB
461 20:39:28.188826 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 20:39:28.189466 cs0 DataBus test pass
463 20:39:28.194523 cs1 DataBus test pass
464 20:39:28.195168 cs0 AddrBus test pass
465 20:39:28.195721 cs1 AddrBus test pass
466 20:39:28.196304
467 20:39:28.200128 100bdlr_step_size ps== 420
468 20:39:28.200780 result report
469 20:39:28.205733 boot times 0Enable ddr reg access
470 20:39:28.211095 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 20:39:28.223614 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 20:39:28.798276 0.0;M3 CHK:0;cm4_sp_mode 0
473 20:39:28.799078 MVN_1=0x00000000
474 20:39:28.803740 MVN_2=0x00000000
475 20:39:28.809475 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 20:39:28.810108 OPS=0x10
477 20:39:28.810655 ring efuse init
478 20:39:28.811190 chipver efuse init
479 20:39:28.817659 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 20:39:28.818310 [0.018961 Inits done]
481 20:39:28.825314 secure task start!
482 20:39:28.825966 high task start!
483 20:39:28.826519 low task start!
484 20:39:28.827055 run into bl31
485 20:39:28.831871 NOTICE: BL31: v1.3(release):4fc40b1
486 20:39:28.839705 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 20:39:28.840356 NOTICE: BL31: G12A normal boot!
488 20:39:28.865060 NOTICE: BL31: BL33 decompress pass
489 20:39:28.870770 ERROR: Error initializing runtime service opteed_fast
490 20:39:30.103699
491 20:39:30.104531
492 20:39:30.112115 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 20:39:30.112837
494 20:39:30.113924 Model: Libre Computer AML-A311D-CC Alta
495 20:39:30.320524 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 20:39:30.343833 DRAM: 2 GiB (effective 3.8 GiB)
497 20:39:30.486793 Core: 408 devices, 31 uclasses, devicetree: separate
498 20:39:30.492713 WDT: Not starting watchdog@f0d0
499 20:39:30.524920 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 20:39:30.537315 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 20:39:30.541412 ** Bad device specification mmc 0 **
502 20:39:30.552679 Card did not respond to voltage select! : -110
503 20:39:30.559453 ** Bad device specification mmc 0 **
504 20:39:30.559972 Couldn't find partition mmc 0
505 20:39:30.568696 Card did not respond to voltage select! : -110
506 20:39:30.574223 ** Bad device specification mmc 0 **
507 20:39:30.574722 Couldn't find partition mmc 0
508 20:39:30.578374 Error: could not access storage.
509 20:39:31.842777 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 20:39:31.843218 bl2_stage_init 0x01
511 20:39:31.843452 bl2_stage_init 0x81
512 20:39:31.848234 hw id: 0x0000 - pwm id 0x01
513 20:39:31.848634 bl2_stage_init 0xc1
514 20:39:31.848860 bl2_stage_init 0x02
515 20:39:31.849064
516 20:39:31.853795 L0:00000000
517 20:39:31.854183 L1:20000703
518 20:39:31.854404 L2:00008067
519 20:39:31.854616 L3:14000000
520 20:39:31.856843 B2:00402000
521 20:39:31.857202 B1:e0f83180
522 20:39:31.857443
523 20:39:31.857662 TE: 58124
524 20:39:31.857877
525 20:39:31.867966 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 20:39:31.868396
527 20:39:31.868631 Board ID = 1
528 20:39:31.868844 Set A53 clk to 24M
529 20:39:31.869054 Set A73 clk to 24M
530 20:39:31.873605 Set clk81 to 24M
531 20:39:31.873935 A53 clk: 1200 MHz
532 20:39:31.874151 A73 clk: 1200 MHz
533 20:39:31.879156 CLK81: 166.6M
534 20:39:31.879473 smccc: 00012a92
535 20:39:31.884875 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 20:39:31.885322 board id: 1
537 20:39:31.894875 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 20:39:31.903969 fw parse done
539 20:39:31.909891 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 20:39:31.952593 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 20:39:31.963421 PIEI prepare done
542 20:39:31.963794 fastboot data load
543 20:39:31.964047 fastboot data verify
544 20:39:31.969182 verify result: 266
545 20:39:31.974891 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 20:39:31.975307 LPDDR4 probe
547 20:39:31.975561 ddr clk to 1584MHz
548 20:39:31.982691 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 20:39:32.020020
550 20:39:32.020427 dmc_version 0001
551 20:39:32.026685 Check phy result
552 20:39:32.032551 INFO : End of CA training
553 20:39:32.032953 INFO : End of initialization
554 20:39:32.038152 INFO : Training has run successfully!
555 20:39:32.038557 Check phy result
556 20:39:32.043743 INFO : End of initialization
557 20:39:32.044147 INFO : End of read enable training
558 20:39:32.049357 INFO : End of fine write leveling
559 20:39:32.054978 INFO : End of Write leveling coarse delay
560 20:39:32.055356 INFO : Training has run successfully!
561 20:39:32.055592 Check phy result
562 20:39:32.060512 INFO : End of initialization
563 20:39:32.060879 INFO : End of read dq deskew training
564 20:39:32.066193 INFO : End of MPR read delay center optimization
565 20:39:32.071739 INFO : End of write delay center optimization
566 20:39:32.077323 INFO : End of read delay center optimization
567 20:39:32.077665 INFO : End of max read latency training
568 20:39:32.083022 INFO : Training has run successfully!
569 20:39:32.083399 1D training succeed
570 20:39:32.092259 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 20:39:32.139909 Check phy result
572 20:39:32.140784 INFO : End of initialization
573 20:39:32.161569 INFO : End of 2D read delay Voltage center optimization
574 20:39:32.181748 INFO : End of 2D read delay Voltage center optimization
575 20:39:32.232891 INFO : End of 2D write delay Voltage center optimization
576 20:39:32.283208 INFO : End of 2D write delay Voltage center optimization
577 20:39:32.288704 INFO : Training has run successfully!
578 20:39:32.289466
579 20:39:32.290009 channel==0
580 20:39:32.294260 RxClkDly_Margin_A0==88 ps 9
581 20:39:32.294891 TxDqDly_Margin_A0==98 ps 10
582 20:39:32.299902 RxClkDly_Margin_A1==88 ps 9
583 20:39:32.300509 TxDqDly_Margin_A1==98 ps 10
584 20:39:32.301008 TrainedVREFDQ_A0==74
585 20:39:32.305446 TrainedVREFDQ_A1==74
586 20:39:32.305993 VrefDac_Margin_A0==25
587 20:39:32.306398 DeviceVref_Margin_A0==40
588 20:39:32.311029 VrefDac_Margin_A1==25
589 20:39:32.311629 DeviceVref_Margin_A1==40
590 20:39:32.312397
591 20:39:32.312840
592 20:39:32.316662 channel==1
593 20:39:32.317305 RxClkDly_Margin_A0==98 ps 10
594 20:39:32.317772 TxDqDly_Margin_A0==88 ps 9
595 20:39:32.322211 RxClkDly_Margin_A1==88 ps 9
596 20:39:32.322736 TxDqDly_Margin_A1==98 ps 10
597 20:39:32.328172 TrainedVREFDQ_A0==76
598 20:39:32.328686 TrainedVREFDQ_A1==78
599 20:39:32.329091 VrefDac_Margin_A0==22
600 20:39:32.333597 DeviceVref_Margin_A0==38
601 20:39:32.334088 VrefDac_Margin_A1==24
602 20:39:32.339154 DeviceVref_Margin_A1==36
603 20:39:32.339665
604 20:39:32.340107 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 20:39:32.340513
606 20:39:32.372913 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 20:39:32.373719 2D training succeed
608 20:39:32.378255 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 20:39:32.384062 auto size-- 65535DDR cs0 size: 2048MB
610 20:39:32.384692 DDR cs1 size: 2048MB
611 20:39:32.389504 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 20:39:32.390122 cs0 DataBus test pass
613 20:39:32.395140 cs1 DataBus test pass
614 20:39:32.395732 cs0 AddrBus test pass
615 20:39:32.396332 cs1 AddrBus test pass
616 20:39:32.396869
617 20:39:32.400745 100bdlr_step_size ps== 420
618 20:39:32.401366 result report
619 20:39:32.406330 boot times 0Enable ddr reg access
620 20:39:32.411642 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 20:39:32.425165 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 20:39:32.998143 0.0;M3 CHK:0;cm4_sp_mode 0
623 20:39:32.998917 MVN_1=0x00000000
624 20:39:33.003578 MVN_2=0x00000000
625 20:39:33.009309 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 20:39:33.009942 OPS=0x10
627 20:39:33.010651 ring efuse init
628 20:39:33.011190 chipver efuse init
629 20:39:33.014914 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 20:39:33.020515 [0.018961 Inits done]
631 20:39:33.021105 secure task start!
632 20:39:33.021614 high task start!
633 20:39:33.025069 low task start!
634 20:39:33.025658 run into bl31
635 20:39:33.031741 NOTICE: BL31: v1.3(release):4fc40b1
636 20:39:33.039535 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 20:39:33.040178 NOTICE: BL31: G12A normal boot!
638 20:39:33.064945 NOTICE: BL31: BL33 decompress pass
639 20:39:33.070551 ERROR: Error initializing runtime service opteed_fast
640 20:39:34.303423
641 20:39:34.304264
642 20:39:34.312323 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 20:39:34.312967
644 20:39:34.313530 Model: Libre Computer AML-A311D-CC Alta
645 20:39:34.520300 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 20:39:34.543614 DRAM: 2 GiB (effective 3.8 GiB)
647 20:39:34.686720 Core: 408 devices, 31 uclasses, devicetree: separate
648 20:39:34.692524 WDT: Not starting watchdog@f0d0
649 20:39:34.724799 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 20:39:34.737251 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 20:39:34.742303 ** Bad device specification mmc 0 **
652 20:39:34.752578 Card did not respond to voltage select! : -110
653 20:39:34.760300 ** Bad device specification mmc 0 **
654 20:39:34.760879 Couldn't find partition mmc 0
655 20:39:34.768710 Card did not respond to voltage select! : -110
656 20:39:34.774333 ** Bad device specification mmc 0 **
657 20:39:34.774863 Couldn't find partition mmc 0
658 20:39:34.779404 Error: could not access storage.
659 20:39:35.121693 Net: eth0: ethernet@ff3f0000
660 20:39:35.122320 starting USB...
661 20:39:35.373479 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 20:39:35.374131 Starting the controller
663 20:39:35.380495 USB XHCI 1.10
664 20:39:37.091525 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
665 20:39:37.092298 bl2_stage_init 0x81
666 20:39:37.097938 hw id: 0x0000 - pwm id 0x01
667 20:39:37.098432 bl2_stage_init 0xc1
668 20:39:37.098850 bl2_stage_init 0x02
669 20:39:37.099260
670 20:39:37.102645 L0:00000000
671 20:39:37.103184 L1:20000703
672 20:39:37.103665 L2:00008067
673 20:39:37.104196 L3:14000000
674 20:39:37.104674 B2:00402000
675 20:39:37.105650 B1:e0f83180
676 20:39:37.106171
677 20:39:37.106655 TE: 58150
678 20:39:37.107126
679 20:39:37.116625 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 20:39:37.117274
681 20:39:37.117840 Board ID = 1
682 20:39:37.118385 Set A53 clk to 24M
683 20:39:37.118913 Set A73 clk to 24M
684 20:39:37.122245 Set clk81 to 24M
685 20:39:37.122851 A53 clk: 1200 MHz
686 20:39:37.123395 A73 clk: 1200 MHz
687 20:39:37.127801 CLK81: 166.6M
688 20:39:37.128451 smccc: 00012aac
689 20:39:37.133392 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 20:39:37.134016 board id: 1
691 20:39:37.141632 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 20:39:37.152645 fw parse done
693 20:39:37.158702 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 20:39:37.201245 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 20:39:37.212220 PIEI prepare done
696 20:39:37.212878 fastboot data load
697 20:39:37.213422 fastboot data verify
698 20:39:37.217895 verify result: 266
699 20:39:37.223442 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 20:39:37.224095 LPDDR4 probe
701 20:39:37.224672 ddr clk to 1584MHz
702 20:39:37.231377 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 20:39:37.268849
704 20:39:37.269572 dmc_version 0001
705 20:39:37.276677 Check phy result
706 20:39:37.282356 INFO : End of CA training
707 20:39:37.283085 INFO : End of initialization
708 20:39:37.288484 INFO : Training has run successfully!
709 20:39:37.289183 Check phy result
710 20:39:37.293562 INFO : End of initialization
711 20:39:37.294249 INFO : End of read enable training
712 20:39:37.295798 INFO : End of fine write leveling
713 20:39:37.301169 INFO : End of Write leveling coarse delay
714 20:39:37.306859 INFO : Training has run successfully!
715 20:39:37.307492 Check phy result
716 20:39:37.307960 INFO : End of initialization
717 20:39:37.312424 INFO : End of read dq deskew training
718 20:39:37.315801 INFO : End of MPR read delay center optimization
719 20:39:37.321515 INFO : End of write delay center optimization
720 20:39:37.327033 INFO : End of read delay center optimization
721 20:39:37.327524 INFO : End of max read latency training
722 20:39:37.332652 INFO : Training has run successfully!
723 20:39:37.333136 1D training succeed
724 20:39:37.340786 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 20:39:37.388411 Check phy result
726 20:39:37.388972 INFO : End of initialization
727 20:39:37.410857 INFO : End of 2D read delay Voltage center optimization
728 20:39:37.431296 INFO : End of 2D read delay Voltage center optimization
729 20:39:37.484677 INFO : End of 2D write delay Voltage center optimization
730 20:39:37.532821 INFO : End of 2D write delay Voltage center optimization
731 20:39:37.539895 INFO : Training has run successfully!
732 20:39:37.540524
733 20:39:37.540975 channel==0
734 20:39:37.543866 RxClkDly_Margin_A0==88 ps 9
735 20:39:37.544454 TxDqDly_Margin_A0==98 ps 10
736 20:39:37.548960 RxClkDly_Margin_A1==88 ps 9
737 20:39:37.549493 TxDqDly_Margin_A1==88 ps 9
738 20:39:37.552795 TrainedVREFDQ_A0==74
739 20:39:37.553375 TrainedVREFDQ_A1==74
740 20:39:37.553832 VrefDac_Margin_A0==24
741 20:39:37.559095 DeviceVref_Margin_A0==40
742 20:39:37.559628 VrefDac_Margin_A1==24
743 20:39:37.564675 DeviceVref_Margin_A1==40
744 20:39:37.565241
745 20:39:37.565687
746 20:39:37.566125 channel==1
747 20:39:37.566557 RxClkDly_Margin_A0==98 ps 10
748 20:39:37.567832 TxDqDly_Margin_A0==98 ps 10
749 20:39:37.574619 RxClkDly_Margin_A1==98 ps 10
750 20:39:37.575159 TxDqDly_Margin_A1==88 ps 9
751 20:39:37.575604 TrainedVREFDQ_A0==77
752 20:39:37.578701 TrainedVREFDQ_A1==77
753 20:39:37.579222 VrefDac_Margin_A0==22
754 20:39:37.584335 DeviceVref_Margin_A0==37
755 20:39:37.584946 VrefDac_Margin_A1==24
756 20:39:37.585386 DeviceVref_Margin_A1==37
757 20:39:37.585823
758 20:39:37.589877 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 20:39:37.590447
760 20:39:37.623297 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
761 20:39:37.623955 2D training succeed
762 20:39:37.629030 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 20:39:37.634478 auto size-- 65535DDR cs0 size: 2048MB
764 20:39:37.635025 DDR cs1 size: 2048MB
765 20:39:37.640069 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 20:39:37.640601 cs0 DataBus test pass
767 20:39:37.641037 cs1 DataBus test pass
768 20:39:37.645723 cs0 AddrBus test pass
769 20:39:37.646234 cs1 AddrBus test pass
770 20:39:37.646669
771 20:39:37.651259 100bdlr_step_size ps== 420
772 20:39:37.651784 result report
773 20:39:37.652262 boot times 0Enable ddr reg access
774 20:39:37.661036 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 20:39:37.674585 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 20:39:38.248255 0.0;M3 CHK:0;cm4_sp_mode 0
777 20:39:38.248885 MVN_1=0x00000000
778 20:39:38.253947 MVN_2=0x00000000
779 20:39:38.259632 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 20:39:38.260242 OPS=0x10
781 20:39:38.260684 ring efuse init
782 20:39:38.261112 chipver efuse init
783 20:39:38.268243 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 20:39:38.268760 [0.018961 Inits done]
785 20:39:38.269190 secure task start!
786 20:39:38.275859 high task start!
787 20:39:38.276415 low task start!
788 20:39:38.276862 run into bl31
789 20:39:38.282100 NOTICE: BL31: v1.3(release):4fc40b1
790 20:39:38.289799 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 20:39:38.290302 NOTICE: BL31: G12A normal boot!
792 20:39:38.315196 NOTICE: BL31: BL33 decompress pass
793 20:39:38.320848 ERROR: Error initializing runtime service opteed_fast
794 20:39:39.553598
795 20:39:39.554207
796 20:39:39.561168 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 20:39:39.561747
798 20:39:39.562230 Model: Libre Computer AML-A311D-CC Alta
799 20:39:39.769571 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 20:39:39.792908 DRAM: 2 GiB (effective 3.8 GiB)
801 20:39:39.936834 Core: 408 devices, 31 uclasses, devicetree: separate
802 20:39:39.941799 WDT: Not starting watchdog@f0d0
803 20:39:39.974982 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 20:39:39.987473 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 20:39:39.991386 ** Bad device specification mmc 0 **
806 20:39:40.002804 Card did not respond to voltage select! : -110
807 20:39:40.009398 ** Bad device specification mmc 0 **
808 20:39:40.009921 Couldn't find partition mmc 0
809 20:39:40.018750 Card did not respond to voltage select! : -110
810 20:39:40.024222 ** Bad device specification mmc 0 **
811 20:39:40.024734 Couldn't find partition mmc 0
812 20:39:40.028393 Error: could not access storage.
813 20:39:40.370894 Net: eth0: ethernet@ff3f0000
814 20:39:40.371654 starting USB...
815 20:39:40.623554 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 20:39:40.624211 Starting the controller
817 20:39:40.629602 USB XHCI 1.10
818 20:39:42.791631 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 20:39:42.792336 bl2_stage_init 0x01
820 20:39:42.792830 bl2_stage_init 0x81
821 20:39:42.797377 hw id: 0x0000 - pwm id 0x01
822 20:39:42.797928 bl2_stage_init 0xc1
823 20:39:42.798421 bl2_stage_init 0x02
824 20:39:42.798896
825 20:39:42.802848 L0:00000000
826 20:39:42.803371 L1:20000703
827 20:39:42.803870 L2:00008067
828 20:39:42.804379 L3:14000000
829 20:39:42.805879 B2:00402000
830 20:39:42.806407 B1:e0f83180
831 20:39:42.806893
832 20:39:42.807367 TE: 58167
833 20:39:42.807842
834 20:39:42.816959 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 20:39:42.817496
836 20:39:42.817982 Board ID = 1
837 20:39:42.818466 Set A53 clk to 24M
838 20:39:42.818935 Set A73 clk to 24M
839 20:39:42.822461 Set clk81 to 24M
840 20:39:42.822984 A53 clk: 1200 MHz
841 20:39:42.823465 A73 clk: 1200 MHz
842 20:39:42.826274 CLK81: 166.6M
843 20:39:42.827044 smccc: 00012abe
844 20:39:42.831696 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 20:39:42.837202 board id: 1
846 20:39:42.841361 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 20:39:42.852937 fw parse done
848 20:39:42.858464 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 20:39:42.900916 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 20:39:42.912467 PIEI prepare done
851 20:39:42.913200 fastboot data load
852 20:39:42.913858 fastboot data verify
853 20:39:42.918268 verify result: 266
854 20:39:42.923857 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 20:39:42.924628 LPDDR4 probe
856 20:39:42.925285 ddr clk to 1584MHz
857 20:39:42.930874 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 20:39:42.967875
859 20:39:42.968614 dmc_version 0001
860 20:39:42.974665 Check phy result
861 20:39:42.981386 INFO : End of CA training
862 20:39:42.981911 INFO : End of initialization
863 20:39:42.987137 INFO : Training has run successfully!
864 20:39:42.987643 Check phy result
865 20:39:42.992626 INFO : End of initialization
866 20:39:42.993132 INFO : End of read enable training
867 20:39:42.998264 INFO : End of fine write leveling
868 20:39:43.003946 INFO : End of Write leveling coarse delay
869 20:39:43.004478 INFO : Training has run successfully!
870 20:39:43.004942 Check phy result
871 20:39:43.009470 INFO : End of initialization
872 20:39:43.009973 INFO : End of read dq deskew training
873 20:39:43.015189 INFO : End of MPR read delay center optimization
874 20:39:43.020720 INFO : End of write delay center optimization
875 20:39:43.026403 INFO : End of read delay center optimization
876 20:39:43.026905 INFO : End of max read latency training
877 20:39:43.031857 INFO : Training has run successfully!
878 20:39:43.032408 1D training succeed
879 20:39:43.040018 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 20:39:43.087715 Check phy result
881 20:39:43.088262 INFO : End of initialization
882 20:39:43.110129 INFO : End of 2D read delay Voltage center optimization
883 20:39:43.129545 INFO : End of 2D read delay Voltage center optimization
884 20:39:43.181258 INFO : End of 2D write delay Voltage center optimization
885 20:39:43.231448 INFO : End of 2D write delay Voltage center optimization
886 20:39:43.236847 INFO : Training has run successfully!
887 20:39:43.237168
888 20:39:43.237391 channel==0
889 20:39:43.242733 RxClkDly_Margin_A0==88 ps 9
890 20:39:43.243269 TxDqDly_Margin_A0==98 ps 10
891 20:39:43.245877 RxClkDly_Margin_A1==88 ps 9
892 20:39:43.246350 TxDqDly_Margin_A1==88 ps 9
893 20:39:43.251387 TrainedVREFDQ_A0==74
894 20:39:43.251943 TrainedVREFDQ_A1==74
895 20:39:43.252312 VrefDac_Margin_A0==24
896 20:39:43.257135 DeviceVref_Margin_A0==40
897 20:39:43.258034 VrefDac_Margin_A1==25
898 20:39:43.262574 DeviceVref_Margin_A1==40
899 20:39:43.262888
900 20:39:43.263120
901 20:39:43.263355 channel==1
902 20:39:43.263582 RxClkDly_Margin_A0==98 ps 10
903 20:39:43.265865 TxDqDly_Margin_A0==98 ps 10
904 20:39:43.271534 RxClkDly_Margin_A1==88 ps 9
905 20:39:43.272065 TxDqDly_Margin_A1==88 ps 9
906 20:39:43.272502 TrainedVREFDQ_A0==77
907 20:39:43.277070 TrainedVREFDQ_A1==77
908 20:39:43.277573 VrefDac_Margin_A0==23
909 20:39:43.282517 DeviceVref_Margin_A0==37
910 20:39:43.282827 VrefDac_Margin_A1==24
911 20:39:43.283081 DeviceVref_Margin_A1==37
912 20:39:43.283318
913 20:39:43.288436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 20:39:43.288817
915 20:39:43.321851 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 20:39:43.322405 2D training succeed
917 20:39:43.327423 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 20:39:43.333006 auto size-- 65535DDR cs0 size: 2048MB
919 20:39:43.333388 DDR cs1 size: 2048MB
920 20:39:43.338596 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 20:39:43.339107 cs0 DataBus test pass
922 20:39:43.339425 cs1 DataBus test pass
923 20:39:43.344267 cs0 AddrBus test pass
924 20:39:43.344751 cs1 AddrBus test pass
925 20:39:43.345092
926 20:39:43.349821 100bdlr_step_size ps== 420
927 20:39:43.350323 result report
928 20:39:43.350682 boot times 0Enable ddr reg access
929 20:39:43.358892 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 20:39:43.372530 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 20:39:43.945425 0.0;M3 CHK:0;cm4_sp_mode 0
932 20:39:43.946043 MVN_1=0x00000000
933 20:39:43.950758 MVN_2=0x00000000
934 20:39:43.956555 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 20:39:43.957072 OPS=0x10
936 20:39:43.957481 ring efuse init
937 20:39:43.957877 chipver efuse init
938 20:39:43.962127 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 20:39:43.967711 [0.018961 Inits done]
940 20:39:43.968818 secure task start!
941 20:39:43.969283 high task start!
942 20:39:43.971427 low task start!
943 20:39:43.971900 run into bl31
944 20:39:43.979033 NOTICE: BL31: v1.3(release):4fc40b1
945 20:39:43.985880 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 20:39:43.986410 NOTICE: BL31: G12A normal boot!
947 20:39:44.012210 NOTICE: BL31: BL33 decompress pass
948 20:39:44.018643 ERROR: Error initializing runtime service opteed_fast
949 20:39:45.250724
950 20:39:45.251381
951 20:39:45.258224 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 20:39:45.258763
953 20:39:45.259227 Model: Libre Computer AML-A311D-CC Alta
954 20:39:45.467586 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 20:39:45.489867 DRAM: 2 GiB (effective 3.8 GiB)
956 20:39:45.633914 Core: 408 devices, 31 uclasses, devicetree: separate
957 20:39:45.639700 WDT: Not starting watchdog@f0d0
958 20:39:45.672051 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 20:39:45.684509 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 20:39:45.689379 ** Bad device specification mmc 0 **
961 20:39:45.699704 Card did not respond to voltage select! : -110
962 20:39:45.707408 ** Bad device specification mmc 0 **
963 20:39:45.707745 Couldn't find partition mmc 0
964 20:39:45.715781 Card did not respond to voltage select! : -110
965 20:39:45.721224 ** Bad device specification mmc 0 **
966 20:39:45.721524 Couldn't find partition mmc 0
967 20:39:45.725317 Error: could not access storage.
968 20:39:46.068765 Net: eth0: ethernet@ff3f0000
969 20:39:46.069180 starting USB...
970 20:39:46.320650 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 20:39:46.321226 Starting the controller
972 20:39:46.327479 USB XHCI 1.10
973 20:39:48.191220 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 20:39:48.191776 bl2_stage_init 0x01
975 20:39:48.192266 bl2_stage_init 0x81
976 20:39:48.196763 hw id: 0x0000 - pwm id 0x01
977 20:39:48.197202 bl2_stage_init 0xc1
978 20:39:48.197609 bl2_stage_init 0x02
979 20:39:48.198008
980 20:39:48.202421 L0:00000000
981 20:39:48.202853 L1:20000703
982 20:39:48.203259 L2:00008067
983 20:39:48.203680 L3:14000000
984 20:39:48.205392 B2:00402000
985 20:39:48.205826 B1:e0f83180
986 20:39:48.206232
987 20:39:48.206636 TE: 58167
988 20:39:48.207033
989 20:39:48.216382 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 20:39:48.216822
991 20:39:48.217228 Board ID = 1
992 20:39:48.217622 Set A53 clk to 24M
993 20:39:48.218011 Set A73 clk to 24M
994 20:39:48.221956 Set clk81 to 24M
995 20:39:48.222383 A53 clk: 1200 MHz
996 20:39:48.222780 A73 clk: 1200 MHz
997 20:39:48.227673 CLK81: 166.6M
998 20:39:48.228129 smccc: 00012abd
999 20:39:48.233503 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 20:39:48.233941 board id: 1
1001 20:39:48.238756 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 20:39:48.252570 fw parse done
1003 20:39:48.258020 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 20:39:48.301484 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 20:39:48.311922 PIEI prepare done
1006 20:39:48.312389 fastboot data load
1007 20:39:48.312779 fastboot data verify
1008 20:39:48.317585 verify result: 266
1009 20:39:48.323197 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 20:39:48.323612 LPDDR4 probe
1011 20:39:48.324028 ddr clk to 1584MHz
1012 20:39:48.331187 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 20:39:48.368457
1014 20:39:48.368881 dmc_version 0001
1015 20:39:48.375080 Check phy result
1016 20:39:48.380940 INFO : End of CA training
1017 20:39:48.381354 INFO : End of initialization
1018 20:39:48.386539 INFO : Training has run successfully!
1019 20:39:48.386948 Check phy result
1020 20:39:48.392174 INFO : End of initialization
1021 20:39:48.392648 INFO : End of read enable training
1022 20:39:48.397768 INFO : End of fine write leveling
1023 20:39:48.403403 INFO : End of Write leveling coarse delay
1024 20:39:48.403833 INFO : Training has run successfully!
1025 20:39:48.404275 Check phy result
1026 20:39:48.408953 INFO : End of initialization
1027 20:39:48.409376 INFO : End of read dq deskew training
1028 20:39:48.414542 INFO : End of MPR read delay center optimization
1029 20:39:48.420172 INFO : End of write delay center optimization
1030 20:39:48.425724 INFO : End of read delay center optimization
1031 20:39:48.426151 INFO : End of max read latency training
1032 20:39:48.431345 INFO : Training has run successfully!
1033 20:39:48.431771 1D training succeed
1034 20:39:48.440581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 20:39:48.488257 Check phy result
1036 20:39:48.488697 INFO : End of initialization
1037 20:39:48.508986 INFO : End of 2D read delay Voltage center optimization
1038 20:39:48.528378 INFO : End of 2D read delay Voltage center optimization
1039 20:39:48.580351 INFO : End of 2D write delay Voltage center optimization
1040 20:39:48.630706 INFO : End of 2D write delay Voltage center optimization
1041 20:39:48.636251 INFO : Training has run successfully!
1042 20:39:48.636678
1043 20:39:48.637086 channel==0
1044 20:39:48.641824 RxClkDly_Margin_A0==88 ps 9
1045 20:39:48.642250 TxDqDly_Margin_A0==98 ps 10
1046 20:39:48.647434 RxClkDly_Margin_A1==88 ps 9
1047 20:39:48.647860 TxDqDly_Margin_A1==98 ps 10
1048 20:39:48.648320 TrainedVREFDQ_A0==74
1049 20:39:48.653030 TrainedVREFDQ_A1==74
1050 20:39:48.653463 VrefDac_Margin_A0==25
1051 20:39:48.653862 DeviceVref_Margin_A0==40
1052 20:39:48.658629 VrefDac_Margin_A1==25
1053 20:39:48.659054 DeviceVref_Margin_A1==40
1054 20:39:48.659452
1055 20:39:48.659848
1056 20:39:48.664264 channel==1
1057 20:39:48.664691 RxClkDly_Margin_A0==98 ps 10
1058 20:39:48.665090 TxDqDly_Margin_A0==98 ps 10
1059 20:39:48.669860 RxClkDly_Margin_A1==88 ps 9
1060 20:39:48.670289 TxDqDly_Margin_A1==88 ps 9
1061 20:39:48.675455 TrainedVREFDQ_A0==77
1062 20:39:48.675885 TrainedVREFDQ_A1==77
1063 20:39:48.676327 VrefDac_Margin_A0==22
1064 20:39:48.681034 DeviceVref_Margin_A0==37
1065 20:39:48.681460 VrefDac_Margin_A1==24
1066 20:39:48.686658 DeviceVref_Margin_A1==37
1067 20:39:48.687085
1068 20:39:48.687486 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 20:39:48.687884
1070 20:39:48.720300 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1071 20:39:48.720769 2D training succeed
1072 20:39:48.725879 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 20:39:48.731424 auto size-- 65535DDR cs0 size: 2048MB
1074 20:39:48.731853 DDR cs1 size: 2048MB
1075 20:39:48.737068 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 20:39:48.737497 cs0 DataBus test pass
1077 20:39:48.742639 cs1 DataBus test pass
1078 20:39:48.743069 cs0 AddrBus test pass
1079 20:39:48.743468 cs1 AddrBus test pass
1080 20:39:48.743862
1081 20:39:48.748249 100bdlr_step_size ps== 420
1082 20:39:48.748687 result report
1083 20:39:48.753861 boot times 0Enable ddr reg access
1084 20:39:48.759185 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 20:39:48.772800 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 20:39:49.345727 0.0;M3 CHK:0;cm4_sp_mode 0
1087 20:39:49.346213 MVN_1=0x00000000
1088 20:39:49.351226 MVN_2=0x00000000
1089 20:39:49.357090 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 20:39:49.357534 OPS=0x10
1091 20:39:49.357939 ring efuse init
1092 20:39:49.358331 chipver efuse init
1093 20:39:49.362602 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 20:39:49.368269 [0.018961 Inits done]
1095 20:39:49.368700 secure task start!
1096 20:39:49.369098 high task start!
1097 20:39:49.371812 low task start!
1098 20:39:49.372277 run into bl31
1099 20:39:49.379449 NOTICE: BL31: v1.3(release):4fc40b1
1100 20:39:49.387227 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 20:39:49.387662 NOTICE: BL31: G12A normal boot!
1102 20:39:49.412627 NOTICE: BL31: BL33 decompress pass
1103 20:39:49.418265 ERROR: Error initializing runtime service opteed_fast
1104 20:39:50.651177
1105 20:39:50.651734
1106 20:39:50.658595 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 20:39:50.659037
1108 20:39:50.659445 Model: Libre Computer AML-A311D-CC Alta
1109 20:39:50.868090 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 20:39:50.890464 DRAM: 2 GiB (effective 3.8 GiB)
1111 20:39:51.034454 Core: 408 devices, 31 uclasses, devicetree: separate
1112 20:39:51.040269 WDT: Not starting watchdog@f0d0
1113 20:39:51.072472 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 20:39:51.084931 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 20:39:51.089909 ** Bad device specification mmc 0 **
1116 20:39:51.100309 Card did not respond to voltage select! : -110
1117 20:39:51.107883 ** Bad device specification mmc 0 **
1118 20:39:51.108358 Couldn't find partition mmc 0
1119 20:39:51.116299 Card did not respond to voltage select! : -110
1120 20:39:51.121783 ** Bad device specification mmc 0 **
1121 20:39:51.122221 Couldn't find partition mmc 0
1122 20:39:51.126864 Error: could not access storage.
1123 20:39:51.469364 Net: eth0: ethernet@ff3f0000
1124 20:39:51.469906 starting USB...
1125 20:39:51.721045 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 20:39:51.721565 Starting the controller
1127 20:39:51.728058 USB XHCI 1.10
1128 20:39:53.282268 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 20:39:53.290619 scanning usb for storage devices... 0 Storage Device(s) found
1131 20:39:53.342241 Hit any key to stop autoboot: 1
1132 20:39:53.342976 end: 2.4.2 bootloader-interrupt (duration 00:00:36) [common]
1133 20:39:53.343531 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 20:39:53.344004 Setting prompt string to ['=>']
1135 20:39:53.344474 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 20:39:53.357146 0
1137 20:39:53.357959 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 20:39:53.358431 Sending with 10 millisecond of delay
1140 20:39:54.493046 => setenv autoload no
1141 20:39:54.503803 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 20:39:54.508660 setenv autoload no
1143 20:39:54.509393 Sending with 10 millisecond of delay
1145 20:39:56.306335 => setenv initrd_high 0xffffffff
1146 20:39:56.317084 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 20:39:56.317912 setenv initrd_high 0xffffffff
1148 20:39:56.318613 Sending with 10 millisecond of delay
1150 20:39:57.934975 => setenv fdt_high 0xffffffff
1151 20:39:57.945715 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1152 20:39:57.946501 setenv fdt_high 0xffffffff
1153 20:39:57.947208 Sending with 10 millisecond of delay
1155 20:39:58.239032 => dhcp
1156 20:39:58.249718 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1157 20:39:58.250509 dhcp
1158 20:39:58.250946 Speed: 1000, full duplex
1159 20:39:58.251358 BOOTP broadcast 1
1160 20:39:58.422002 DHCP client bound to address 192.168.6.27 (171 ms)
1161 20:39:58.422803 Sending with 10 millisecond of delay
1163 20:40:00.099429 => setenv serverip 192.168.6.2
1164 20:40:00.110249 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1165 20:40:00.111087 setenv serverip 192.168.6.2
1166 20:40:00.111793 Sending with 10 millisecond of delay
1168 20:40:03.835172 => tftpboot 0x01080000 914538/tftp-deploy-mnlx03pg/kernel/uImage
1169 20:40:03.845953 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1170 20:40:03.846821 tftpboot 0x01080000 914538/tftp-deploy-mnlx03pg/kernel/uImage
1171 20:40:03.847272 Speed: 1000, full duplex
1172 20:40:03.847675 Using ethernet@ff3f0000 device
1173 20:40:03.848533 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 20:40:03.854030 Filename '914538/tftp-deploy-mnlx03pg/kernel/uImage'.
1175 20:40:03.857899 Load address: 0x1080000
1176 20:40:06.166320 Loading: *################################################## 36.1 MiB
1177 20:40:06.166911 15.6 MiB/s
1178 20:40:06.167341 done
1179 20:40:06.170643 Bytes transferred = 37812800 (240fa40 hex)
1180 20:40:06.171369 Sending with 10 millisecond of delay
1182 20:40:10.859292 => tftpboot 0x08000000 914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot
1183 20:40:10.870180 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:06)
1184 20:40:10.871117 tftpboot 0x08000000 914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot
1185 20:40:10.871597 Speed: 1000, full duplex
1186 20:40:10.872209 Using ethernet@ff3f0000 device
1187 20:40:10.873009 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 20:40:10.884846 Filename '914538/tftp-deploy-mnlx03pg/ramdisk/ramdisk.cpio.gz.uboot'.
1189 20:40:10.885420 Load address: 0x8000000
1190 20:40:13.255081 Loading: *# UDP wrong checksum 000000ff 00003a97
1191 20:40:13.265664 UDP wrong checksum 000000ff 0000cf89
1192 20:40:17.648134 T ################################################ UDP wrong checksum 00000005 000096ee
1193 20:40:22.650365 T UDP wrong checksum 00000005 000096ee
1194 20:40:32.652247 T T UDP wrong checksum 00000005 000096ee
1195 20:40:52.656355 T T T T UDP wrong checksum 00000005 000096ee
1196 20:41:03.927695 T T UDP wrong checksum 000000ff 000092a9
1197 20:41:03.998681 UDP wrong checksum 000000ff 00002b9c
1198 20:41:05.657921 UDP wrong checksum 000000ff 000013cd
1199 20:41:05.708933 UDP wrong checksum 000000ff 00009fbf
1200 20:41:07.659680
1201 20:41:07.660141 Retry count exceeded; starting again
1203 20:41:07.661005 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1206 20:41:07.662866 end: 2.4 uboot-commands (duration 00:01:51) [common]
1208 20:41:07.664241 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1210 20:41:07.665223 end: 2 uboot-action (duration 00:01:51) [common]
1212 20:41:07.666745 Cleaning after the job
1213 20:41:07.667307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/ramdisk
1214 20:41:07.668640 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/kernel
1215 20:41:07.708504 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/dtb
1216 20:41:07.709826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/nfsrootfs
1217 20:41:07.745511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914538/tftp-deploy-mnlx03pg/modules
1218 20:41:07.752599 start: 4.1 power-off (timeout 00:00:30) [common]
1219 20:41:07.753187 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1220 20:41:07.786448 >> OK - accepted request
1221 20:41:07.788780 Returned 0 in 0 seconds
1222 20:41:07.889874 end: 4.1 power-off (duration 00:00:00) [common]
1224 20:41:07.890929 start: 4.2 read-feedback (timeout 00:10:00) [common]
1225 20:41:07.891792 Listened to connection for namespace 'common' for up to 1s
1226 20:41:08.892559 Finalising connection for namespace 'common'
1227 20:41:08.893077 Disconnecting from shell: Finalise
1228 20:41:08.893387 =>
1229 20:41:08.994206 end: 4.2 read-feedback (duration 00:00:01) [common]
1230 20:41:08.994925 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/914538
1231 20:41:12.070823 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/914538
1232 20:41:12.071586 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.