Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:34:37.024965 lava-dispatcher, installed at version: 2024.01
2 20:34:37.025927 start: 0 validate
3 20:34:37.026502 Start time: 2024-10-30 20:34:37.026471+00:00 (UTC)
4 20:34:37.027148 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:34:37.027810 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:34:37.066927 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:34:37.067498 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 20:34:37.099753 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:34:37.100444 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:34:37.131914 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:34:37.132470 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:34:37.163677 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:34:37.164246 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-47-g4236f913808ce%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 20:34:37.203237 validate duration: 0.18
16 20:34:37.204255 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:34:37.204641 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:34:37.205004 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:34:37.205627 Not decompressing ramdisk as can be used compressed.
20 20:34:37.206109 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 20:34:37.206435 saving as /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/ramdisk/initrd.cpio.gz
22 20:34:37.206755 total size: 5628140 (5 MB)
23 20:34:37.251734 progress 0 % (0 MB)
24 20:34:37.256274 progress 5 % (0 MB)
25 20:34:37.260831 progress 10 % (0 MB)
26 20:34:37.264908 progress 15 % (0 MB)
27 20:34:37.269292 progress 20 % (1 MB)
28 20:34:37.273223 progress 25 % (1 MB)
29 20:34:37.277648 progress 30 % (1 MB)
30 20:34:37.282048 progress 35 % (1 MB)
31 20:34:37.286064 progress 40 % (2 MB)
32 20:34:37.290562 progress 45 % (2 MB)
33 20:34:37.294616 progress 50 % (2 MB)
34 20:34:37.298929 progress 55 % (2 MB)
35 20:34:37.303287 progress 60 % (3 MB)
36 20:34:37.307341 progress 65 % (3 MB)
37 20:34:37.311640 progress 70 % (3 MB)
38 20:34:37.315237 progress 75 % (4 MB)
39 20:34:37.319319 progress 80 % (4 MB)
40 20:34:37.322950 progress 85 % (4 MB)
41 20:34:37.326915 progress 90 % (4 MB)
42 20:34:37.330724 progress 95 % (5 MB)
43 20:34:37.334052 progress 100 % (5 MB)
44 20:34:37.334703 5 MB downloaded in 0.13 s (41.96 MB/s)
45 20:34:37.335252 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:34:37.336163 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:34:37.336459 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:34:37.336729 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:34:37.337223 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/kernel/Image
51 20:34:37.337473 saving as /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/kernel/Image
52 20:34:37.337682 total size: 37812736 (36 MB)
53 20:34:37.337893 No compression specified
54 20:34:37.376182 progress 0 % (0 MB)
55 20:34:37.400016 progress 5 % (1 MB)
56 20:34:37.424215 progress 10 % (3 MB)
57 20:34:37.448135 progress 15 % (5 MB)
58 20:34:37.471858 progress 20 % (7 MB)
59 20:34:37.496001 progress 25 % (9 MB)
60 20:34:37.519794 progress 30 % (10 MB)
61 20:34:37.543578 progress 35 % (12 MB)
62 20:34:37.567711 progress 40 % (14 MB)
63 20:34:37.591432 progress 45 % (16 MB)
64 20:34:37.614998 progress 50 % (18 MB)
65 20:34:37.639183 progress 55 % (19 MB)
66 20:34:37.662899 progress 60 % (21 MB)
67 20:34:37.686897 progress 65 % (23 MB)
68 20:34:37.710535 progress 70 % (25 MB)
69 20:34:37.734462 progress 75 % (27 MB)
70 20:34:37.758421 progress 80 % (28 MB)
71 20:34:37.782041 progress 85 % (30 MB)
72 20:34:37.805827 progress 90 % (32 MB)
73 20:34:37.829764 progress 95 % (34 MB)
74 20:34:37.852946 progress 100 % (36 MB)
75 20:34:37.853709 36 MB downloaded in 0.52 s (69.88 MB/s)
76 20:34:37.854191 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:34:37.855011 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:34:37.855284 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:34:37.855545 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:34:37.856031 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:34:37.856304 saving as /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:34:37.856514 total size: 54703 (0 MB)
84 20:34:37.856722 No compression specified
85 20:34:37.894605 progress 59 % (0 MB)
86 20:34:37.895461 progress 100 % (0 MB)
87 20:34:37.896078 0 MB downloaded in 0.04 s (1.32 MB/s)
88 20:34:37.896562 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:34:37.897378 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:34:37.897640 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:34:37.897903 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:34:37.898363 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 20:34:37.898602 saving as /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/nfsrootfs/full.rootfs.tar
95 20:34:37.898806 total size: 474398908 (452 MB)
96 20:34:37.899015 Using unxz to decompress xz
97 20:34:37.936368 progress 0 % (0 MB)
98 20:34:39.034090 progress 5 % (22 MB)
99 20:34:40.474370 progress 10 % (45 MB)
100 20:34:40.908195 progress 15 % (67 MB)
101 20:34:41.714737 progress 20 % (90 MB)
102 20:34:42.239711 progress 25 % (113 MB)
103 20:34:42.597355 progress 30 % (135 MB)
104 20:34:43.208954 progress 35 % (158 MB)
105 20:34:44.132581 progress 40 % (181 MB)
106 20:34:44.980835 progress 45 % (203 MB)
107 20:34:45.707034 progress 50 % (226 MB)
108 20:34:46.483282 progress 55 % (248 MB)
109 20:34:47.695261 progress 60 % (271 MB)
110 20:34:49.193338 progress 65 % (294 MB)
111 20:34:50.837174 progress 70 % (316 MB)
112 20:34:53.920934 progress 75 % (339 MB)
113 20:34:56.345690 progress 80 % (361 MB)
114 20:34:59.230997 progress 85 % (384 MB)
115 20:35:02.397762 progress 90 % (407 MB)
116 20:35:05.598069 progress 95 % (429 MB)
117 20:35:08.850234 progress 100 % (452 MB)
118 20:35:08.863323 452 MB downloaded in 30.96 s (14.61 MB/s)
119 20:35:08.864017 end: 1.4.1 http-download (duration 00:00:31) [common]
121 20:35:08.865635 end: 1.4 download-retry (duration 00:00:31) [common]
122 20:35:08.866152 start: 1.5 download-retry (timeout 00:09:28) [common]
123 20:35:08.866763 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 20:35:08.867744 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-47-g4236f913808ce/arm64/defconfig/clang-16/modules.tar.xz
125 20:35:08.868270 saving as /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/modules/modules.tar
126 20:35:08.868677 total size: 11751036 (11 MB)
127 20:35:08.869092 Using unxz to decompress xz
128 20:35:08.907636 progress 0 % (0 MB)
129 20:35:08.975314 progress 5 % (0 MB)
130 20:35:09.052497 progress 10 % (1 MB)
131 20:35:09.133595 progress 15 % (1 MB)
132 20:35:09.214751 progress 20 % (2 MB)
133 20:35:09.292627 progress 25 % (2 MB)
134 20:35:09.373659 progress 30 % (3 MB)
135 20:35:09.450361 progress 35 % (3 MB)
136 20:35:09.532288 progress 40 % (4 MB)
137 20:35:09.618300 progress 45 % (5 MB)
138 20:35:09.700113 progress 50 % (5 MB)
139 20:35:09.786495 progress 55 % (6 MB)
140 20:35:09.871928 progress 60 % (6 MB)
141 20:35:09.957496 progress 65 % (7 MB)
142 20:35:10.040909 progress 70 % (7 MB)
143 20:35:10.119221 progress 75 % (8 MB)
144 20:35:10.205093 progress 80 % (8 MB)
145 20:35:10.284981 progress 85 % (9 MB)
146 20:35:10.359742 progress 90 % (10 MB)
147 20:35:10.460977 progress 95 % (10 MB)
148 20:35:10.557478 progress 100 % (11 MB)
149 20:35:10.570405 11 MB downloaded in 1.70 s (6.59 MB/s)
150 20:35:10.571011 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:35:10.571851 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:35:10.572310 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 20:35:10.572855 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 20:35:26.027663 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/914508/extract-nfsrootfs-2trawe8r
156 20:35:26.028289 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 20:35:26.028576 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 20:35:26.029256 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2
159 20:35:26.029703 makedir: /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin
160 20:35:26.030020 makedir: /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/tests
161 20:35:26.030325 makedir: /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/results
162 20:35:26.030652 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-add-keys
163 20:35:26.031172 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-add-sources
164 20:35:26.031670 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-background-process-start
165 20:35:26.032204 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-background-process-stop
166 20:35:26.032747 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-common-functions
167 20:35:26.033245 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-echo-ipv4
168 20:35:26.033725 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-install-packages
169 20:35:26.034211 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-installed-packages
170 20:35:26.034711 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-os-build
171 20:35:26.035231 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-probe-channel
172 20:35:26.035710 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-probe-ip
173 20:35:26.036202 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-target-ip
174 20:35:26.036676 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-target-mac
175 20:35:26.037146 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-target-storage
176 20:35:26.037618 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-case
177 20:35:26.038082 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-event
178 20:35:26.038541 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-feedback
179 20:35:26.039022 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-raise
180 20:35:26.039518 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-reference
181 20:35:26.040005 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-runner
182 20:35:26.040517 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-set
183 20:35:26.040987 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-test-shell
184 20:35:26.041463 Updating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-install-packages (oe)
185 20:35:26.041975 Updating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/bin/lava-installed-packages (oe)
186 20:35:26.042406 Creating /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/environment
187 20:35:26.042768 LAVA metadata
188 20:35:26.043019 - LAVA_JOB_ID=914508
189 20:35:26.043231 - LAVA_DISPATCHER_IP=192.168.6.2
190 20:35:26.043579 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 20:35:26.044535 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 20:35:26.044845 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 20:35:26.045057 skipped lava-vland-overlay
194 20:35:26.045297 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 20:35:26.045562 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 20:35:26.045781 skipped lava-multinode-overlay
197 20:35:26.046021 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 20:35:26.046271 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 20:35:26.046517 Loading test definitions
200 20:35:26.046790 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 20:35:26.047008 Using /lava-914508 at stage 0
202 20:35:26.048187 uuid=914508_1.6.2.4.1 testdef=None
203 20:35:26.048491 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 20:35:26.048751 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 20:35:26.050457 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 20:35:26.051236 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 20:35:26.053390 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 20:35:26.054216 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 20:35:26.056296 runner path: /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 914508_1.6.2.4.1
212 20:35:26.056860 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 20:35:26.057614 Creating lava-test-runner.conf files
215 20:35:26.057812 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/914508/lava-overlay-q3aaj0s2/lava-914508/0 for stage 0
216 20:35:26.058139 - 0_v4l2-decoder-conformance-h264
217 20:35:26.058469 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 20:35:26.058738 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 20:35:26.080106 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 20:35:26.080467 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 20:35:26.080721 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 20:35:26.080981 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 20:35:26.081237 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 20:35:26.697364 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 20:35:26.697812 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 20:35:26.698065 extracting modules file /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914508/extract-nfsrootfs-2trawe8r
227 20:35:28.064377 extracting modules file /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/914508/extract-overlay-ramdisk-wmyr0pr2/ramdisk
228 20:35:29.500032 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 20:35:29.500556 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 20:35:29.500860 [common] Applying overlay to NFS
231 20:35:29.501084 [common] Applying overlay /var/lib/lava/dispatcher/tmp/914508/compress-overlay-0qdj1oiy/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/914508/extract-nfsrootfs-2trawe8r
232 20:35:29.530608 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 20:35:29.531014 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 20:35:29.531283 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 20:35:29.531509 Converting downloaded kernel to a uImage
236 20:35:29.531815 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/kernel/Image /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/kernel/uImage
237 20:35:29.926774 output: Image Name:
238 20:35:29.927191 output: Created: Wed Oct 30 20:35:29 2024
239 20:35:29.927400 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 20:35:29.927604 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
241 20:35:29.927802 output: Load Address: 01080000
242 20:35:29.928033 output: Entry Point: 01080000
243 20:35:29.928235 output:
244 20:35:29.928571 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 20:35:29.928836 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 20:35:29.929102 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 20:35:29.929353 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 20:35:29.929607 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 20:35:29.929869 Building ramdisk /var/lib/lava/dispatcher/tmp/914508/extract-overlay-ramdisk-wmyr0pr2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/914508/extract-overlay-ramdisk-wmyr0pr2/ramdisk
250 20:35:32.170157 >> 173422 blocks
251 20:35:39.902986 Adding RAMdisk u-boot header.
252 20:35:39.903679 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/914508/extract-overlay-ramdisk-wmyr0pr2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/914508/extract-overlay-ramdisk-wmyr0pr2/ramdisk.cpio.gz.uboot
253 20:35:40.163650 output: Image Name:
254 20:35:40.164142 output: Created: Wed Oct 30 20:35:39 2024
255 20:35:40.164631 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 20:35:40.165086 output: Data Size: 24145923 Bytes = 23580.00 KiB = 23.03 MiB
257 20:35:40.165531 output: Load Address: 00000000
258 20:35:40.165966 output: Entry Point: 00000000
259 20:35:40.166402 output:
260 20:35:40.167442 rename /var/lib/lava/dispatcher/tmp/914508/extract-overlay-ramdisk-wmyr0pr2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot
261 20:35:40.168248 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 20:35:40.168870 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 20:35:40.169465 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 20:35:40.169994 No LXC device requested
265 20:35:40.170561 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 20:35:40.171134 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 20:35:40.171689 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 20:35:40.172184 Checking files for TFTP limit of 4294967296 bytes.
269 20:35:40.175101 end: 1 tftp-deploy (duration 00:01:03) [common]
270 20:35:40.175733 start: 2 uboot-action (timeout 00:05:00) [common]
271 20:35:40.176368 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 20:35:40.176932 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 20:35:40.177493 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 20:35:40.178078 Using kernel file from prepare-kernel: 914508/tftp-deploy-bsysustu/kernel/uImage
275 20:35:40.178778 substitutions:
276 20:35:40.179230 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 20:35:40.179676 - {DTB_ADDR}: 0x01070000
278 20:35:40.180147 - {DTB}: 914508/tftp-deploy-bsysustu/dtb/meson-g12b-a311d-libretech-cc.dtb
279 20:35:40.180593 - {INITRD}: 914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot
280 20:35:40.181034 - {KERNEL_ADDR}: 0x01080000
281 20:35:40.181470 - {KERNEL}: 914508/tftp-deploy-bsysustu/kernel/uImage
282 20:35:40.181906 - {LAVA_MAC}: None
283 20:35:40.182381 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/914508/extract-nfsrootfs-2trawe8r
284 20:35:40.182826 - {NFS_SERVER_IP}: 192.168.6.2
285 20:35:40.183258 - {PRESEED_CONFIG}: None
286 20:35:40.183691 - {PRESEED_LOCAL}: None
287 20:35:40.184159 - {RAMDISK_ADDR}: 0x08000000
288 20:35:40.184589 - {RAMDISK}: 914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot
289 20:35:40.185024 - {ROOT_PART}: None
290 20:35:40.185450 - {ROOT}: None
291 20:35:40.185877 - {SERVER_IP}: 192.168.6.2
292 20:35:40.186302 - {TEE_ADDR}: 0x83000000
293 20:35:40.186728 - {TEE}: None
294 20:35:40.187156 Parsed boot commands:
295 20:35:40.187575 - setenv autoload no
296 20:35:40.188023 - setenv initrd_high 0xffffffff
297 20:35:40.188454 - setenv fdt_high 0xffffffff
298 20:35:40.188883 - dhcp
299 20:35:40.189306 - setenv serverip 192.168.6.2
300 20:35:40.189732 - tftpboot 0x01080000 914508/tftp-deploy-bsysustu/kernel/uImage
301 20:35:40.190163 - tftpboot 0x08000000 914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot
302 20:35:40.190590 - tftpboot 0x01070000 914508/tftp-deploy-bsysustu/dtb/meson-g12b-a311d-libretech-cc.dtb
303 20:35:40.191013 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/914508/extract-nfsrootfs-2trawe8r,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 20:35:40.191453 - bootm 0x01080000 0x08000000 0x01070000
305 20:35:40.192019 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 20:35:40.193671 start: 2.3 connect-device (timeout 00:05:00) [common]
308 20:35:40.194133 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 20:35:40.209618 Setting prompt string to ['lava-test: # ']
310 20:35:40.211198 end: 2.3 connect-device (duration 00:00:00) [common]
311 20:35:40.211863 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 20:35:40.212519 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 20:35:40.213122 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 20:35:40.214351 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 20:35:40.252210 >> OK - accepted request
316 20:35:40.254026 Returned 0 in 0 seconds
317 20:35:40.355231 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 20:35:40.357061 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 20:35:40.357709 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 20:35:40.358293 Setting prompt string to ['Hit any key to stop autoboot']
322 20:35:40.358819 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 20:35:40.360559 Trying 192.168.56.21...
324 20:35:40.361093 Connected to conserv1.
325 20:35:40.361570 Escape character is '^]'.
326 20:35:40.362037
327 20:35:40.362508 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 20:35:40.362977
329 20:35:52.489676 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 20:35:52.490300 bl2_stage_init 0x01
331 20:35:52.490788 bl2_stage_init 0x81
332 20:35:52.495430 hw id: 0x0000 - pwm id 0x01
333 20:35:52.496063 bl2_stage_init 0xc1
334 20:35:52.496531 bl2_stage_init 0x02
335 20:35:52.496964
336 20:35:52.500820 L0:00000000
337 20:35:52.501300 L1:20000703
338 20:35:52.501731 L2:00008067
339 20:35:52.502164 L3:14000000
340 20:35:52.503758 B2:00402000
341 20:35:52.504249 B1:e0f83180
342 20:35:52.504676
343 20:35:52.505104 TE: 58124
344 20:35:52.505533
345 20:35:52.514969 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 20:35:52.515434
347 20:35:52.515865 Board ID = 1
348 20:35:52.516326 Set A53 clk to 24M
349 20:35:52.516751 Set A73 clk to 24M
350 20:35:52.520474 Set clk81 to 24M
351 20:35:52.520928 A53 clk: 1200 MHz
352 20:35:52.521354 A73 clk: 1200 MHz
353 20:35:52.526087 CLK81: 166.6M
354 20:35:52.526547 smccc: 00012a92
355 20:35:52.531679 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 20:35:52.532164 board id: 1
357 20:35:52.537266 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 20:35:52.550955 fw parse done
359 20:35:52.557010 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 20:35:52.598673 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 20:35:52.610386 PIEI prepare done
362 20:35:52.610842 fastboot data load
363 20:35:52.611276 fastboot data verify
364 20:35:52.616061 verify result: 266
365 20:35:52.621661 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 20:35:52.622165 LPDDR4 probe
367 20:35:52.622605 ddr clk to 1584MHz
368 20:35:52.629675 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 20:35:52.666850
370 20:35:52.667318 dmc_version 0001
371 20:35:52.673670 Check phy result
372 20:35:52.679414 INFO : End of CA training
373 20:35:52.679874 INFO : End of initialization
374 20:35:52.685018 INFO : Training has run successfully!
375 20:35:52.685483 Check phy result
376 20:35:52.690634 INFO : End of initialization
377 20:35:52.691099 INFO : End of read enable training
378 20:35:52.696230 INFO : End of fine write leveling
379 20:35:52.701818 INFO : End of Write leveling coarse delay
380 20:35:52.702276 INFO : Training has run successfully!
381 20:35:52.702717 Check phy result
382 20:35:52.707408 INFO : End of initialization
383 20:35:52.707869 INFO : End of read dq deskew training
384 20:35:52.712992 INFO : End of MPR read delay center optimization
385 20:35:52.718639 INFO : End of write delay center optimization
386 20:35:52.724235 INFO : End of read delay center optimization
387 20:35:52.724700 INFO : End of max read latency training
388 20:35:52.729825 INFO : Training has run successfully!
389 20:35:52.730286 1D training succeed
390 20:35:52.738025 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 20:35:52.786696 Check phy result
392 20:35:52.787198 INFO : End of initialization
393 20:35:52.808348 INFO : End of 2D read delay Voltage center optimization
394 20:35:52.828713 INFO : End of 2D read delay Voltage center optimization
395 20:35:52.880763 INFO : End of 2D write delay Voltage center optimization
396 20:35:52.930037 INFO : End of 2D write delay Voltage center optimization
397 20:35:52.935632 INFO : Training has run successfully!
398 20:35:52.936149
399 20:35:52.936611 channel==0
400 20:35:52.941170 RxClkDly_Margin_A0==88 ps 9
401 20:35:52.941638 TxDqDly_Margin_A0==98 ps 10
402 20:35:52.946783 RxClkDly_Margin_A1==88 ps 9
403 20:35:52.947246 TxDqDly_Margin_A1==98 ps 10
404 20:35:52.947692 TrainedVREFDQ_A0==74
405 20:35:52.952375 TrainedVREFDQ_A1==74
406 20:35:52.952851 VrefDac_Margin_A0==25
407 20:35:52.953299 DeviceVref_Margin_A0==40
408 20:35:52.957974 VrefDac_Margin_A1==25
409 20:35:52.958442 DeviceVref_Margin_A1==40
410 20:35:52.958879
411 20:35:52.959316
412 20:35:52.963629 channel==1
413 20:35:52.964129 RxClkDly_Margin_A0==98 ps 10
414 20:35:52.964577 TxDqDly_Margin_A0==88 ps 9
415 20:35:52.969161 RxClkDly_Margin_A1==88 ps 9
416 20:35:52.969630 TxDqDly_Margin_A1==88 ps 9
417 20:35:52.974763 TrainedVREFDQ_A0==77
418 20:35:52.975236 TrainedVREFDQ_A1==77
419 20:35:52.975687 VrefDac_Margin_A0==22
420 20:35:52.980376 DeviceVref_Margin_A0==37
421 20:35:52.980848 VrefDac_Margin_A1==24
422 20:35:52.985995 DeviceVref_Margin_A1==37
423 20:35:52.986457
424 20:35:52.986903 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 20:35:52.987341
426 20:35:53.019626 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 20:35:53.020212 2D training succeed
428 20:35:53.025163 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 20:35:53.030781 auto size-- 65535DDR cs0 size: 2048MB
430 20:35:53.031260 DDR cs1 size: 2048MB
431 20:35:53.036376 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 20:35:53.036848 cs0 DataBus test pass
433 20:35:53.041969 cs1 DataBus test pass
434 20:35:53.042436 cs0 AddrBus test pass
435 20:35:53.042886 cs1 AddrBus test pass
436 20:35:53.043325
437 20:35:53.047643 100bdlr_step_size ps== 420
438 20:35:53.048155 result report
439 20:35:53.053188 boot times 0Enable ddr reg access
440 20:35:53.058528 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 20:35:53.071945 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 20:35:53.644935 0.0;M3 CHK:0;cm4_sp_mode 0
443 20:35:53.645547 MVN_1=0x00000000
444 20:35:53.650438 MVN_2=0x00000000
445 20:35:53.656182 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 20:35:53.656649 OPS=0x10
447 20:35:53.657090 ring efuse init
448 20:35:53.657526 chipver efuse init
449 20:35:53.661766 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 20:35:53.667422 [0.018961 Inits done]
451 20:35:53.667879 secure task start!
452 20:35:53.668375 high task start!
453 20:35:53.671960 low task start!
454 20:35:53.672453 run into bl31
455 20:35:53.678683 NOTICE: BL31: v1.3(release):4fc40b1
456 20:35:53.686486 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 20:35:53.686954 NOTICE: BL31: G12A normal boot!
458 20:35:53.712189 NOTICE: BL31: BL33 decompress pass
459 20:35:53.717890 ERROR: Error initializing runtime service opteed_fast
460 20:35:54.950885
461 20:35:54.951543
462 20:35:54.959169 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 20:35:54.959673
464 20:35:54.960176 Model: Libre Computer AML-A311D-CC Alta
465 20:35:55.166706 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 20:35:55.190972 DRAM: 2 GiB (effective 3.8 GiB)
467 20:35:55.333940 Core: 408 devices, 31 uclasses, devicetree: separate
468 20:35:55.339812 WDT: Not starting watchdog@f0d0
469 20:35:55.372070 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 20:35:55.384526 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 20:35:55.389494 ** Bad device specification mmc 0 **
472 20:35:55.399921 Card did not respond to voltage select! : -110
473 20:35:55.407493 ** Bad device specification mmc 0 **
474 20:35:55.407957 Couldn't find partition mmc 0
475 20:35:55.415914 Card did not respond to voltage select! : -110
476 20:35:55.421361 ** Bad device specification mmc 0 **
477 20:35:55.421825 Couldn't find partition mmc 0
478 20:35:55.426413 Error: could not access storage.
479 20:35:56.689957 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 20:35:56.690636 bl2_stage_init 0x01
481 20:35:56.691111 bl2_stage_init 0x81
482 20:35:56.695753 hw id: 0x0000 - pwm id 0x01
483 20:35:56.696336 bl2_stage_init 0xc1
484 20:35:56.696810 bl2_stage_init 0x02
485 20:35:56.697326
486 20:35:56.705092 L0:00000000
487 20:35:56.705604 L1:20000703
488 20:35:56.706076 L2:00008067
489 20:35:56.706529 L3:14000000
490 20:35:56.707169 B2:00402000
491 20:35:56.707797 B1:e0f83180
492 20:35:56.708308
493 20:35:56.708700 TE: 58124
494 20:35:56.709057
495 20:35:56.715410 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 20:35:56.716062
497 20:35:56.716511 Board ID = 1
498 20:35:56.716896 Set A53 clk to 24M
499 20:35:56.717255 Set A73 clk to 24M
500 20:35:56.721173 Set clk81 to 24M
501 20:35:56.721679 A53 clk: 1200 MHz
502 20:35:56.722005 A73 clk: 1200 MHz
503 20:35:56.726673 CLK81: 166.6M
504 20:35:56.727473 smccc: 00012a92
505 20:35:56.732411 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 20:35:56.733433 board id: 1
507 20:35:56.740726 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 20:35:56.751206 fw parse done
509 20:35:56.757151 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 20:35:56.799840 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 20:35:56.810827 PIEI prepare done
512 20:35:56.811458 fastboot data load
513 20:35:56.812052 fastboot data verify
514 20:35:56.816537 verify result: 266
515 20:35:56.822074 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 20:35:56.822438 LPDDR4 probe
517 20:35:56.822700 ddr clk to 1584MHz
518 20:35:56.830243 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 20:35:56.867512
520 20:35:56.868313 dmc_version 0001
521 20:35:56.874090 Check phy result
522 20:35:56.879939 INFO : End of CA training
523 20:35:56.880650 INFO : End of initialization
524 20:35:56.885525 INFO : Training has run successfully!
525 20:35:56.886156 Check phy result
526 20:35:56.891157 INFO : End of initialization
527 20:35:56.891805 INFO : End of read enable training
528 20:35:56.896760 INFO : End of fine write leveling
529 20:35:56.902337 INFO : End of Write leveling coarse delay
530 20:35:56.903009 INFO : Training has run successfully!
531 20:35:56.903554 Check phy result
532 20:35:56.907908 INFO : End of initialization
533 20:35:56.908572 INFO : End of read dq deskew training
534 20:35:56.913506 INFO : End of MPR read delay center optimization
535 20:35:56.919131 INFO : End of write delay center optimization
536 20:35:56.924750 INFO : End of read delay center optimization
537 20:35:56.925446 INFO : End of max read latency training
538 20:35:56.930374 INFO : Training has run successfully!
539 20:35:56.931022 1D training succeed
540 20:35:56.939442 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 20:35:56.987129 Check phy result
542 20:35:56.987849 INFO : End of initialization
543 20:35:57.008824 INFO : End of 2D read delay Voltage center optimization
544 20:35:57.029024 INFO : End of 2D read delay Voltage center optimization
545 20:35:57.081055 INFO : End of 2D write delay Voltage center optimization
546 20:35:57.130466 INFO : End of 2D write delay Voltage center optimization
547 20:35:57.136031 INFO : Training has run successfully!
548 20:35:57.136635
549 20:35:57.137176 channel==0
550 20:35:57.141540 RxClkDly_Margin_A0==88 ps 9
551 20:35:57.142166 TxDqDly_Margin_A0==98 ps 10
552 20:35:57.147157 RxClkDly_Margin_A1==88 ps 9
553 20:35:57.147776 TxDqDly_Margin_A1==88 ps 9
554 20:35:57.148354 TrainedVREFDQ_A0==74
555 20:35:57.152748 TrainedVREFDQ_A1==74
556 20:35:57.153357 VrefDac_Margin_A0==25
557 20:35:57.153893 DeviceVref_Margin_A0==40
558 20:35:57.158392 VrefDac_Margin_A1==25
559 20:35:57.158987 DeviceVref_Margin_A1==40
560 20:35:57.159509
561 20:35:57.160076
562 20:35:57.160615 channel==1
563 20:35:57.163966 RxClkDly_Margin_A0==98 ps 10
564 20:35:57.164602 TxDqDly_Margin_A0==98 ps 10
565 20:35:57.169542 RxClkDly_Margin_A1==98 ps 10
566 20:35:57.170139 TxDqDly_Margin_A1==88 ps 9
567 20:35:57.175163 TrainedVREFDQ_A0==77
568 20:35:57.175766 TrainedVREFDQ_A1==75
569 20:35:57.176344 VrefDac_Margin_A0==22
570 20:35:57.180763 DeviceVref_Margin_A0==37
571 20:35:57.181389 VrefDac_Margin_A1==24
572 20:35:57.186357 DeviceVref_Margin_A1==38
573 20:35:57.186958
574 20:35:57.187496 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 20:35:57.188060
576 20:35:57.219891 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 20:35:57.220614 2D training succeed
578 20:35:57.225587 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 20:35:57.231125 auto size-- 65535DDR cs0 size: 2048MB
580 20:35:57.231722 DDR cs1 size: 2048MB
581 20:35:57.236749 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 20:35:57.237347 cs0 DataBus test pass
583 20:35:57.242364 cs1 DataBus test pass
584 20:35:57.242979 cs0 AddrBus test pass
585 20:35:57.243502 cs1 AddrBus test pass
586 20:35:57.244072
587 20:35:57.248014 100bdlr_step_size ps== 420
588 20:35:57.248687 result report
589 20:35:57.253593 boot times 0Enable ddr reg access
590 20:35:57.258916 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 20:35:57.272395 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 20:35:57.845522 0.0;M3 CHK:0;cm4_sp_mode 0
593 20:35:57.846054 MVN_1=0x00000000
594 20:35:57.850977 MVN_2=0x00000000
595 20:35:57.856683 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 20:35:57.856940 OPS=0x10
597 20:35:57.857159 ring efuse init
598 20:35:57.857358 chipver efuse init
599 20:35:57.862417 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 20:35:57.867922 [0.018961 Inits done]
601 20:35:57.868469 secure task start!
602 20:35:57.868880 high task start!
603 20:35:57.872547 low task start!
604 20:35:57.872988 run into bl31
605 20:35:57.879233 NOTICE: BL31: v1.3(release):4fc40b1
606 20:35:57.887005 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 20:35:57.887461 NOTICE: BL31: G12A normal boot!
608 20:35:57.912325 NOTICE: BL31: BL33 decompress pass
609 20:35:57.918037 ERROR: Error initializing runtime service opteed_fast
610 20:35:59.150929
611 20:35:59.151551
612 20:35:59.159170 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 20:35:59.159650
614 20:35:59.160107 Model: Libre Computer AML-A311D-CC Alta
615 20:35:59.367097 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 20:35:59.390058 DRAM: 2 GiB (effective 3.8 GiB)
617 20:35:59.534132 Core: 408 devices, 31 uclasses, devicetree: separate
618 20:35:59.539096 WDT: Not starting watchdog@f0d0
619 20:35:59.572278 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 20:35:59.584913 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 20:35:59.588821 ** Bad device specification mmc 0 **
622 20:35:59.600129 Card did not respond to voltage select! : -110
623 20:35:59.607423 ** Bad device specification mmc 0 **
624 20:35:59.607869 Couldn't find partition mmc 0
625 20:35:59.616216 Card did not respond to voltage select! : -110
626 20:35:59.621754 ** Bad device specification mmc 0 **
627 20:35:59.622200 Couldn't find partition mmc 0
628 20:35:59.625568 Error: could not access storage.
629 20:35:59.968419 Net: eth0: ethernet@ff3f0000
630 20:35:59.968857 starting USB...
631 20:36:00.221097 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 20:36:00.221522 Starting the controller
633 20:36:00.227452 USB XHCI 1.10
634 20:36:01.940486 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 20:36:01.940963 bl2_stage_init 0x01
636 20:36:01.941202 bl2_stage_init 0x81
637 20:36:01.945987 hw id: 0x0000 - pwm id 0x01
638 20:36:01.946366 bl2_stage_init 0xc1
639 20:36:01.946596 bl2_stage_init 0x02
640 20:36:01.946813
641 20:36:01.951540 L0:00000000
642 20:36:01.951926 L1:20000703
643 20:36:01.952193 L2:00008067
644 20:36:01.952402 L3:14000000
645 20:36:01.957290 B2:00402000
646 20:36:01.957662 B1:e0f83180
647 20:36:01.957883
648 20:36:01.958106 TE: 58124
649 20:36:01.958329
650 20:36:01.962829 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 20:36:01.963225
652 20:36:01.963463 Board ID = 1
653 20:36:01.968254 Set A53 clk to 24M
654 20:36:01.968618 Set A73 clk to 24M
655 20:36:01.968839 Set clk81 to 24M
656 20:36:01.974106 A53 clk: 1200 MHz
657 20:36:01.975242 A73 clk: 1200 MHz
658 20:36:01.975507 CLK81: 166.6M
659 20:36:01.976329 smccc: 00012a92
660 20:36:01.979364 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 20:36:01.985170 board id: 1
662 20:36:01.990518 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 20:36:02.001668 fw parse done
664 20:36:02.006965 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 20:36:02.050225 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 20:36:02.061143 PIEI prepare done
667 20:36:02.061671 fastboot data load
668 20:36:02.061939 fastboot data verify
669 20:36:02.066727 verify result: 266
670 20:36:02.072300 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 20:36:02.072651 LPDDR4 probe
672 20:36:02.072895 ddr clk to 1584MHz
673 20:36:02.079530 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 20:36:02.116712
675 20:36:02.117276 dmc_version 0001
676 20:36:02.123442 Check phy result
677 20:36:02.130091 INFO : End of CA training
678 20:36:02.130454 INFO : End of initialization
679 20:36:02.135852 INFO : Training has run successfully!
680 20:36:02.136602 Check phy result
681 20:36:02.141282 INFO : End of initialization
682 20:36:02.141955 INFO : End of read enable training
683 20:36:02.146930 INFO : End of fine write leveling
684 20:36:02.152494 INFO : End of Write leveling coarse delay
685 20:36:02.153058 INFO : Training has run successfully!
686 20:36:02.153721 Check phy result
687 20:36:02.158117 INFO : End of initialization
688 20:36:02.158859 INFO : End of read dq deskew training
689 20:36:02.163719 INFO : End of MPR read delay center optimization
690 20:36:02.169258 INFO : End of write delay center optimization
691 20:36:02.174987 INFO : End of read delay center optimization
692 20:36:02.175561 INFO : End of max read latency training
693 20:36:02.180578 INFO : Training has run successfully!
694 20:36:02.181273 1D training succeed
695 20:36:02.188836 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 20:36:02.236465 Check phy result
697 20:36:02.237189 INFO : End of initialization
698 20:36:02.259768 INFO : End of 2D read delay Voltage center optimization
699 20:36:02.279786 INFO : End of 2D read delay Voltage center optimization
700 20:36:02.331246 INFO : End of 2D write delay Voltage center optimization
701 20:36:02.381747 INFO : End of 2D write delay Voltage center optimization
702 20:36:02.387024 INFO : Training has run successfully!
703 20:36:02.387574
704 20:36:02.388209 channel==0
705 20:36:02.392824 RxClkDly_Margin_A0==88 ps 9
706 20:36:02.393363 TxDqDly_Margin_A0==98 ps 10
707 20:36:02.396090 RxClkDly_Margin_A1==88 ps 9
708 20:36:02.396622 TxDqDly_Margin_A1==98 ps 10
709 20:36:02.401637 TrainedVREFDQ_A0==74
710 20:36:02.402188 TrainedVREFDQ_A1==74
711 20:36:02.402672 VrefDac_Margin_A0==25
712 20:36:02.407532 DeviceVref_Margin_A0==40
713 20:36:02.408101 VrefDac_Margin_A1==24
714 20:36:02.412815 DeviceVref_Margin_A1==40
715 20:36:02.413308
716 20:36:02.413749
717 20:36:02.414175 channel==1
718 20:36:02.414589 RxClkDly_Margin_A0==98 ps 10
719 20:36:02.418511 TxDqDly_Margin_A0==88 ps 9
720 20:36:02.419011 RxClkDly_Margin_A1==88 ps 9
721 20:36:02.424113 TxDqDly_Margin_A1==88 ps 9
722 20:36:02.424610 TrainedVREFDQ_A0==77
723 20:36:02.425049 TrainedVREFDQ_A1==77
724 20:36:02.429667 VrefDac_Margin_A0==22
725 20:36:02.430219 DeviceVref_Margin_A0==37
726 20:36:02.435175 VrefDac_Margin_A1==24
727 20:36:02.435679 DeviceVref_Margin_A1==37
728 20:36:02.436148
729 20:36:02.440889 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 20:36:02.441373
731 20:36:02.468754 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 20:36:02.474310 2D training succeed
733 20:36:02.479924 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 20:36:02.480720 auto size-- 65535DDR cs0 size: 2048MB
735 20:36:02.485469 DDR cs1 size: 2048MB
736 20:36:02.486023 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 20:36:02.491078 cs0 DataBus test pass
738 20:36:02.491609 cs1 DataBus test pass
739 20:36:02.492127 cs0 AddrBus test pass
740 20:36:02.496717 cs1 AddrBus test pass
741 20:36:02.497261
742 20:36:02.497731 100bdlr_step_size ps== 420
743 20:36:02.498221 result report
744 20:36:02.502311 boot times 0Enable ddr reg access
745 20:36:02.508909 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 20:36:02.522687 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 20:36:03.097150 0.0;M3 CHK:0;cm4_sp_mode 0
748 20:36:03.097793 MVN_1=0x00000000
749 20:36:03.102499 MVN_2=0x00000000
750 20:36:03.108267 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 20:36:03.108807 OPS=0x10
752 20:36:03.109219 ring efuse init
753 20:36:03.109612 chipver efuse init
754 20:36:03.116545 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 20:36:03.117034 [0.018960 Inits done]
756 20:36:03.117440 secure task start!
757 20:36:03.123238 high task start!
758 20:36:03.123693 low task start!
759 20:36:03.124154 run into bl31
760 20:36:03.130715 NOTICE: BL31: v1.3(release):4fc40b1
761 20:36:03.137686 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 20:36:03.138252 NOTICE: BL31: G12A normal boot!
763 20:36:03.163900 NOTICE: BL31: BL33 decompress pass
764 20:36:03.168595 ERROR: Error initializing runtime service opteed_fast
765 20:36:04.402421
766 20:36:04.403239
767 20:36:04.410851 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 20:36:04.411542
769 20:36:04.412187 Model: Libre Computer AML-A311D-CC Alta
770 20:36:04.619265 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 20:36:04.642677 DRAM: 2 GiB (effective 3.8 GiB)
772 20:36:04.785655 Core: 408 devices, 31 uclasses, devicetree: separate
773 20:36:04.791492 WDT: Not starting watchdog@f0d0
774 20:36:04.823798 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 20:36:04.836269 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 20:36:04.841080 ** Bad device specification mmc 0 **
777 20:36:04.851454 Card did not respond to voltage select! : -110
778 20:36:04.859128 ** Bad device specification mmc 0 **
779 20:36:04.859661 Couldn't find partition mmc 0
780 20:36:04.867430 Card did not respond to voltage select! : -110
781 20:36:04.873004 ** Bad device specification mmc 0 **
782 20:36:04.873516 Couldn't find partition mmc 0
783 20:36:04.878054 Error: could not access storage.
784 20:36:05.220471 Net: eth0: ethernet@ff3f0000
785 20:36:05.221107 starting USB...
786 20:36:05.472428 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 20:36:05.473079 Starting the controller
788 20:36:05.479206 USB XHCI 1.10
789 20:36:07.641990 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 20:36:07.642417 bl2_stage_init 0x01
791 20:36:07.642635 bl2_stage_init 0x81
792 20:36:07.647818 hw id: 0x0000 - pwm id 0x01
793 20:36:07.648494 bl2_stage_init 0xc1
794 20:36:07.649003 bl2_stage_init 0x02
795 20:36:07.649463
796 20:36:07.653299 L0:00000000
797 20:36:07.654047 L1:20000703
798 20:36:07.654553 L2:00008067
799 20:36:07.655017 L3:14000000
800 20:36:07.658815 B2:00402000
801 20:36:07.659342 B1:e0f83180
802 20:36:07.659803
803 20:36:07.660298 TE: 58167
804 20:36:07.660755
805 20:36:07.664458 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 20:36:07.665012
807 20:36:07.665480 Board ID = 1
808 20:36:07.670129 Set A53 clk to 24M
809 20:36:07.670727 Set A73 clk to 24M
810 20:36:07.671229 Set clk81 to 24M
811 20:36:07.675572 A53 clk: 1200 MHz
812 20:36:07.676165 A73 clk: 1200 MHz
813 20:36:07.676651 CLK81: 166.6M
814 20:36:07.677112 smccc: 00012abd
815 20:36:07.681170 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 20:36:07.686793 board id: 1
817 20:36:07.692799 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 20:36:07.703195 fw parse done
819 20:36:07.709162 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 20:36:07.751800 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 20:36:07.762675 PIEI prepare done
822 20:36:07.763258 fastboot data load
823 20:36:07.763738 fastboot data verify
824 20:36:07.768418 verify result: 266
825 20:36:07.773926 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 20:36:07.774426 LPDDR4 probe
827 20:36:07.774852 ddr clk to 1584MHz
828 20:36:07.781926 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 20:36:07.819199
830 20:36:07.819740 dmc_version 0001
831 20:36:07.825870 Check phy result
832 20:36:07.831748 INFO : End of CA training
833 20:36:07.832251 INFO : End of initialization
834 20:36:07.837360 INFO : Training has run successfully!
835 20:36:07.837839 Check phy result
836 20:36:07.842998 INFO : End of initialization
837 20:36:07.843462 INFO : End of read enable training
838 20:36:07.848511 INFO : End of fine write leveling
839 20:36:07.854187 INFO : End of Write leveling coarse delay
840 20:36:07.854652 INFO : Training has run successfully!
841 20:36:07.855068 Check phy result
842 20:36:07.859797 INFO : End of initialization
843 20:36:07.860289 INFO : End of read dq deskew training
844 20:36:07.865439 INFO : End of MPR read delay center optimization
845 20:36:07.871130 INFO : End of write delay center optimization
846 20:36:07.876659 INFO : End of read delay center optimization
847 20:36:07.877337 INFO : End of max read latency training
848 20:36:07.882371 INFO : Training has run successfully!
849 20:36:07.883049 1D training succeed
850 20:36:07.891468 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 20:36:07.939086 Check phy result
852 20:36:07.939824 INFO : End of initialization
853 20:36:07.960829 INFO : End of 2D read delay Voltage center optimization
854 20:36:07.981041 INFO : End of 2D read delay Voltage center optimization
855 20:36:08.033225 INFO : End of 2D write delay Voltage center optimization
856 20:36:08.082603 INFO : End of 2D write delay Voltage center optimization
857 20:36:08.088147 INFO : Training has run successfully!
858 20:36:08.088821
859 20:36:08.089403 channel==0
860 20:36:08.093721 RxClkDly_Margin_A0==88 ps 9
861 20:36:08.094382 TxDqDly_Margin_A0==98 ps 10
862 20:36:08.099213 RxClkDly_Margin_A1==88 ps 9
863 20:36:08.099862 TxDqDly_Margin_A1==98 ps 10
864 20:36:08.100509 TrainedVREFDQ_A0==74
865 20:36:08.105035 TrainedVREFDQ_A1==74
866 20:36:08.105720 VrefDac_Margin_A0==25
867 20:36:08.106278 DeviceVref_Margin_A0==40
868 20:36:08.110514 VrefDac_Margin_A1==25
869 20:36:08.111162 DeviceVref_Margin_A1==40
870 20:36:08.111670
871 20:36:08.112235
872 20:36:08.116139 channel==1
873 20:36:08.116780 RxClkDly_Margin_A0==98 ps 10
874 20:36:08.117294 TxDqDly_Margin_A0==88 ps 9
875 20:36:08.121713 RxClkDly_Margin_A1==98 ps 10
876 20:36:08.122349 TxDqDly_Margin_A1==88 ps 9
877 20:36:08.127208 TrainedVREFDQ_A0==77
878 20:36:08.127846 TrainedVREFDQ_A1==77
879 20:36:08.128418 VrefDac_Margin_A0==22
880 20:36:08.133006 DeviceVref_Margin_A0==37
881 20:36:08.133637 VrefDac_Margin_A1==23
882 20:36:08.138380 DeviceVref_Margin_A1==37
883 20:36:08.139008
884 20:36:08.139516 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 20:36:08.140056
886 20:36:08.171946 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 20:36:08.172724 2D training succeed
888 20:36:08.177675 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 20:36:08.183193 auto size-- 65535DDR cs0 size: 2048MB
890 20:36:08.183825 DDR cs1 size: 2048MB
891 20:36:08.188921 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 20:36:08.189552 cs0 DataBus test pass
893 20:36:08.194374 cs1 DataBus test pass
894 20:36:08.195012 cs0 AddrBus test pass
895 20:36:08.195524 cs1 AddrBus test pass
896 20:36:08.196055
897 20:36:08.200063 100bdlr_step_size ps== 420
898 20:36:08.200698 result report
899 20:36:08.205662 boot times 0Enable ddr reg access
900 20:36:08.210979 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 20:36:08.224401 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 20:36:08.797377 0.0;M3 CHK:0;cm4_sp_mode 0
903 20:36:08.798149 MVN_1=0x00000000
904 20:36:08.802908 MVN_2=0x00000000
905 20:36:08.808649 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 20:36:08.809270 OPS=0x10
907 20:36:08.809812 ring efuse init
908 20:36:08.810343 chipver efuse init
909 20:36:08.814244 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 20:36:08.819851 [0.018961 Inits done]
911 20:36:08.820541 secure task start!
912 20:36:08.821079 high task start!
913 20:36:08.823855 low task start!
914 20:36:08.824497 run into bl31
915 20:36:08.831057 NOTICE: BL31: v1.3(release):4fc40b1
916 20:36:08.838935 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 20:36:08.839617 NOTICE: BL31: G12A normal boot!
918 20:36:08.864269 NOTICE: BL31: BL33 decompress pass
919 20:36:08.870009 ERROR: Error initializing runtime service opteed_fast
920 20:36:10.102601
921 20:36:10.103032
922 20:36:10.110471 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 20:36:10.110824
924 20:36:10.111045 Model: Libre Computer AML-A311D-CC Alta
925 20:36:10.318837 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 20:36:10.342541 DRAM: 2 GiB (effective 3.8 GiB)
927 20:36:10.486022 Core: 408 devices, 31 uclasses, devicetree: separate
928 20:36:10.490969 WDT: Not starting watchdog@f0d0
929 20:36:10.524196 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 20:36:10.536495 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 20:36:10.541562 ** Bad device specification mmc 0 **
932 20:36:10.551866 Card did not respond to voltage select! : -110
933 20:36:10.558547 ** Bad device specification mmc 0 **
934 20:36:10.559026 Couldn't find partition mmc 0
935 20:36:10.567873 Card did not respond to voltage select! : -110
936 20:36:10.573374 ** Bad device specification mmc 0 **
937 20:36:10.573856 Couldn't find partition mmc 0
938 20:36:10.578273 Error: could not access storage.
939 20:36:10.920998 Net: eth0: ethernet@ff3f0000
940 20:36:10.921589 starting USB...
941 20:36:11.173765 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 20:36:11.174322 Starting the controller
943 20:36:11.179871 USB XHCI 1.10
944 20:36:12.734797 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 20:36:12.742716 scanning usb for storage devices... 0 Storage Device(s) found
947 20:36:12.794305 Hit any key to stop autoboot: 1
948 20:36:12.795152 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 20:36:12.795912 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
950 20:36:12.796436 Setting prompt string to ['=>']
951 20:36:12.796926 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
952 20:36:12.810061 0
953 20:36:12.811241 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 20:36:12.811901 Sending with 10 millisecond of delay
956 20:36:13.947206 => setenv autoload no
957 20:36:13.958299 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
958 20:36:13.964780 setenv autoload no
959 20:36:13.965697 Sending with 10 millisecond of delay
961 20:36:15.763179 => setenv initrd_high 0xffffffff
962 20:36:15.774200 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
963 20:36:15.775314 setenv initrd_high 0xffffffff
964 20:36:15.776186 Sending with 10 millisecond of delay
966 20:36:17.393125 => setenv fdt_high 0xffffffff
967 20:36:17.403900 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 20:36:17.404765 setenv fdt_high 0xffffffff
969 20:36:17.405475 Sending with 10 millisecond of delay
971 20:36:17.697246 => dhcp
972 20:36:17.708031 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
973 20:36:17.708916 dhcp
974 20:36:17.709351 Speed: 1000, full duplex
975 20:36:17.709761 BOOTP broadcast 1
976 20:36:17.717118 DHCP client bound to address 192.168.6.27 (10 ms)
977 20:36:17.717868 Sending with 10 millisecond of delay
979 20:36:19.394322 => setenv serverip 192.168.6.2
980 20:36:19.404926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 20:36:19.405558 setenv serverip 192.168.6.2
982 20:36:19.406019 Sending with 10 millisecond of delay
984 20:36:23.135100 => tftpboot 0x01080000 914508/tftp-deploy-bsysustu/kernel/uImage
985 20:36:23.145975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 20:36:23.146877 tftpboot 0x01080000 914508/tftp-deploy-bsysustu/kernel/uImage
987 20:36:23.147387 Speed: 1000, full duplex
988 20:36:23.147832 Using ethernet@ff3f0000 device
989 20:36:23.149014 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 20:36:23.154544 Filename '914508/tftp-deploy-bsysustu/kernel/uImage'.
991 20:36:23.158393 Load address: 0x1080000
992 20:36:25.865872 Loading: *################################################## 36.1 MiB
993 20:36:25.866498 13.3 MiB/s
994 20:36:25.866906 done
995 20:36:25.870535 Bytes transferred = 37812800 (240fa40 hex)
996 20:36:25.871297 Sending with 10 millisecond of delay
998 20:36:30.558255 => tftpboot 0x08000000 914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot
999 20:36:30.569020 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 20:36:30.569828 tftpboot 0x08000000 914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot
1001 20:36:30.570266 Speed: 1000, full duplex
1002 20:36:30.570678 Using ethernet@ff3f0000 device
1003 20:36:30.571956 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 20:36:30.583763 Filename '914508/tftp-deploy-bsysustu/ramdisk/ramdisk.cpio.gz.uboot'.
1005 20:36:30.584288 Load address: 0x8000000
1006 20:36:37.558915 Loading: *#######################T ########################## UDP wrong checksum 00000005 00001ab3
1007 20:36:42.559713 T UDP wrong checksum 00000005 00001ab3
1008 20:36:52.562920 T T UDP wrong checksum 00000005 00001ab3
1009 20:37:03.735050 T T UDP wrong checksum 000000ff 00003624
1010 20:37:03.747420 UDP wrong checksum 000000ff 0000cb16
1011 20:37:12.566901 T T UDP wrong checksum 00000005 00001ab3
1012 20:37:27.570921 T T
1013 20:37:27.571725 Retry count exceeded; starting again
1015 20:37:27.573635 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1018 20:37:27.576223 end: 2.4 uboot-commands (duration 00:01:47) [common]
1020 20:37:27.578074 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 20:37:27.579395 end: 2 uboot-action (duration 00:01:47) [common]
1024 20:37:27.581421 Cleaning after the job
1025 20:37:27.582123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/ramdisk
1026 20:37:27.584613 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/kernel
1027 20:37:27.624448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/dtb
1028 20:37:27.625500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/nfsrootfs
1029 20:37:27.790151 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/914508/tftp-deploy-bsysustu/modules
1030 20:37:27.797444 start: 4.1 power-off (timeout 00:00:30) [common]
1031 20:37:27.798052 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 20:37:27.831608 >> OK - accepted request
1033 20:37:27.833826 Returned 0 in 0 seconds
1034 20:37:27.934591 end: 4.1 power-off (duration 00:00:00) [common]
1036 20:37:27.935580 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 20:37:27.936339 Listened to connection for namespace 'common' for up to 1s
1038 20:37:28.936264 Finalising connection for namespace 'common'
1039 20:37:28.936751 Disconnecting from shell: Finalise
1040 20:37:28.937039 =>
1041 20:37:29.037778 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 20:37:29.038433 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/914508
1043 20:37:31.446706 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/914508
1044 20:37:31.447337 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.