Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:14:45.439510 lava-dispatcher, installed at version: 2024.01
2 00:14:45.440343 start: 0 validate
3 00:14:45.440829 Start time: 2024-10-31 00:14:45.440799+00:00 (UTC)
4 00:14:45.441369 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:14:45.441921 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:14:45.487430 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:14:45.488040 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 00:14:45.515972 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:14:45.516618 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:14:45.548125 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:14:45.548634 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:14:45.579023 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:14:45.579525 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:14:45.616236 validate duration: 0.18
16 00:14:45.617186 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:14:45.617559 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:14:45.617879 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:14:45.618472 Not decompressing ramdisk as can be used compressed.
20 00:14:45.618906 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:14:45.619175 saving as /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/ramdisk/initrd.cpio.gz
22 00:14:45.619466 total size: 4775763 (4 MB)
23 00:14:45.654427 progress 0 % (0 MB)
24 00:14:45.660939 progress 5 % (0 MB)
25 00:14:45.667374 progress 10 % (0 MB)
26 00:14:45.673870 progress 15 % (0 MB)
27 00:14:45.678777 progress 20 % (0 MB)
28 00:14:45.682082 progress 25 % (1 MB)
29 00:14:45.685452 progress 30 % (1 MB)
30 00:14:45.689225 progress 35 % (1 MB)
31 00:14:45.692602 progress 40 % (1 MB)
32 00:14:45.696002 progress 45 % (2 MB)
33 00:14:45.699292 progress 50 % (2 MB)
34 00:14:45.703025 progress 55 % (2 MB)
35 00:14:45.706333 progress 60 % (2 MB)
36 00:14:45.709646 progress 65 % (2 MB)
37 00:14:45.713372 progress 70 % (3 MB)
38 00:14:45.716631 progress 75 % (3 MB)
39 00:14:45.719887 progress 80 % (3 MB)
40 00:14:45.723127 progress 85 % (3 MB)
41 00:14:45.726754 progress 90 % (4 MB)
42 00:14:45.729688 progress 95 % (4 MB)
43 00:14:45.732629 progress 100 % (4 MB)
44 00:14:45.733270 4 MB downloaded in 0.11 s (40.03 MB/s)
45 00:14:45.733802 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:14:45.734686 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:14:45.734978 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:14:45.735248 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:14:45.735761 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 00:14:45.736050 saving as /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/kernel/zImage
52 00:14:45.736266 total size: 12050944 (11 MB)
53 00:14:45.736481 No compression specified
54 00:14:45.774134 progress 0 % (0 MB)
55 00:14:45.782378 progress 5 % (0 MB)
56 00:14:45.790202 progress 10 % (1 MB)
57 00:14:45.798764 progress 15 % (1 MB)
58 00:14:45.806599 progress 20 % (2 MB)
59 00:14:45.814852 progress 25 % (2 MB)
60 00:14:45.823425 progress 30 % (3 MB)
61 00:14:45.831473 progress 35 % (4 MB)
62 00:14:45.839922 progress 40 % (4 MB)
63 00:14:45.848053 progress 45 % (5 MB)
64 00:14:45.856168 progress 50 % (5 MB)
65 00:14:45.864653 progress 55 % (6 MB)
66 00:14:45.872734 progress 60 % (6 MB)
67 00:14:45.881381 progress 65 % (7 MB)
68 00:14:45.889403 progress 70 % (8 MB)
69 00:14:45.897649 progress 75 % (8 MB)
70 00:14:45.906127 progress 80 % (9 MB)
71 00:14:45.914274 progress 85 % (9 MB)
72 00:14:45.922414 progress 90 % (10 MB)
73 00:14:45.931296 progress 95 % (10 MB)
74 00:14:45.938661 progress 100 % (11 MB)
75 00:14:45.939377 11 MB downloaded in 0.20 s (56.59 MB/s)
76 00:14:45.939890 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:14:45.940782 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:14:45.941080 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:14:45.941362 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:14:45.941835 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 00:14:45.942125 saving as /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/dtb/am335x-boneblack.dtb
83 00:14:45.942346 total size: 70568 (0 MB)
84 00:14:45.942568 No compression specified
85 00:14:45.977787 progress 46 % (0 MB)
86 00:14:45.978710 progress 92 % (0 MB)
87 00:14:45.979428 progress 100 % (0 MB)
88 00:14:45.979872 0 MB downloaded in 0.04 s (1.79 MB/s)
89 00:14:45.980436 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:14:45.981346 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:14:45.981655 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:14:45.981963 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:14:45.982510 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:14:45.982798 saving as /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/nfsrootfs/full.rootfs.tar
96 00:14:45.983033 total size: 117747780 (112 MB)
97 00:14:45.983274 Using unxz to decompress xz
98 00:14:46.019231 progress 0 % (0 MB)
99 00:14:46.755666 progress 5 % (5 MB)
100 00:14:47.510719 progress 10 % (11 MB)
101 00:14:48.307101 progress 15 % (16 MB)
102 00:14:49.089987 progress 20 % (22 MB)
103 00:14:49.676758 progress 25 % (28 MB)
104 00:14:50.485012 progress 30 % (33 MB)
105 00:14:51.297183 progress 35 % (39 MB)
106 00:14:51.659132 progress 40 % (44 MB)
107 00:14:52.040458 progress 45 % (50 MB)
108 00:14:52.871796 progress 50 % (56 MB)
109 00:14:53.832398 progress 55 % (61 MB)
110 00:14:54.680549 progress 60 % (67 MB)
111 00:14:55.511614 progress 65 % (73 MB)
112 00:14:56.404701 progress 70 % (78 MB)
113 00:14:57.288032 progress 75 % (84 MB)
114 00:14:58.146517 progress 80 % (89 MB)
115 00:14:58.968144 progress 85 % (95 MB)
116 00:14:59.886684 progress 90 % (101 MB)
117 00:15:00.778134 progress 95 % (106 MB)
118 00:15:01.732190 progress 100 % (112 MB)
119 00:15:01.747647 112 MB downloaded in 15.76 s (7.12 MB/s)
120 00:15:01.748724 end: 1.4.1 http-download (duration 00:00:16) [common]
122 00:15:01.750584 end: 1.4 download-retry (duration 00:00:16) [common]
123 00:15:01.751188 start: 1.5 download-retry (timeout 00:09:44) [common]
124 00:15:01.751768 start: 1.5.1 http-download (timeout 00:09:44) [common]
125 00:15:01.752664 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 00:15:01.753171 saving as /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/modules/modules.tar
127 00:15:01.753632 total size: 6911096 (6 MB)
128 00:15:01.754099 Using unxz to decompress xz
129 00:15:01.804121 progress 0 % (0 MB)
130 00:15:01.839572 progress 5 % (0 MB)
131 00:15:01.887145 progress 10 % (0 MB)
132 00:15:01.933034 progress 15 % (1 MB)
133 00:15:01.983174 progress 20 % (1 MB)
134 00:15:02.028071 progress 25 % (1 MB)
135 00:15:02.077299 progress 30 % (2 MB)
136 00:15:02.120990 progress 35 % (2 MB)
137 00:15:02.170411 progress 40 % (2 MB)
138 00:15:02.215149 progress 45 % (2 MB)
139 00:15:02.263765 progress 50 % (3 MB)
140 00:15:02.311414 progress 55 % (3 MB)
141 00:15:02.355957 progress 60 % (3 MB)
142 00:15:02.403606 progress 65 % (4 MB)
143 00:15:02.447495 progress 70 % (4 MB)
144 00:15:02.497849 progress 75 % (4 MB)
145 00:15:02.544102 progress 80 % (5 MB)
146 00:15:02.592865 progress 85 % (5 MB)
147 00:15:02.637504 progress 90 % (5 MB)
148 00:15:02.690540 progress 95 % (6 MB)
149 00:15:02.734041 progress 100 % (6 MB)
150 00:15:02.749133 6 MB downloaded in 1.00 s (6.62 MB/s)
151 00:15:02.749959 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:15:02.751837 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:15:02.752516 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
155 00:15:02.753122 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
156 00:15:19.680597 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp
157 00:15:19.681195 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 00:15:19.681485 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
159 00:15:19.682116 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo
160 00:15:19.682575 makedir: /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin
161 00:15:19.682911 makedir: /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/tests
162 00:15:19.683226 makedir: /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/results
163 00:15:19.683563 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-add-keys
164 00:15:19.684131 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-add-sources
165 00:15:19.684656 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-background-process-start
166 00:15:19.685201 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-background-process-stop
167 00:15:19.685801 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-common-functions
168 00:15:19.686304 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-echo-ipv4
169 00:15:19.686788 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-install-packages
170 00:15:19.687264 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-installed-packages
171 00:15:19.687731 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-os-build
172 00:15:19.688233 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-probe-channel
173 00:15:19.688715 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-probe-ip
174 00:15:19.689184 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-target-ip
175 00:15:19.689658 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-target-mac
176 00:15:19.690129 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-target-storage
177 00:15:19.690617 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-case
178 00:15:19.691099 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-event
179 00:15:19.691573 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-feedback
180 00:15:19.692067 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-raise
181 00:15:19.692551 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-reference
182 00:15:19.693057 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-runner
183 00:15:19.693564 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-set
184 00:15:19.694118 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-test-shell
185 00:15:19.694622 Updating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-add-keys (debian)
186 00:15:19.695152 Updating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-add-sources (debian)
187 00:15:19.695654 Updating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-install-packages (debian)
188 00:15:19.696176 Updating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-installed-packages (debian)
189 00:15:19.696679 Updating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/bin/lava-os-build (debian)
190 00:15:19.697108 Creating /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/environment
191 00:15:19.697479 LAVA metadata
192 00:15:19.697739 - LAVA_JOB_ID=915354
193 00:15:19.697956 - LAVA_DISPATCHER_IP=192.168.6.2
194 00:15:19.698319 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
195 00:15:19.699280 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:15:19.699592 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
197 00:15:19.699800 skipped lava-vland-overlay
198 00:15:19.700102 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:15:19.700370 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
200 00:15:19.700589 skipped lava-multinode-overlay
201 00:15:19.700832 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:15:19.701085 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
203 00:15:19.701335 Loading test definitions
204 00:15:19.701611 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
205 00:15:19.701832 Using /lava-915354 at stage 0
206 00:15:19.702915 uuid=915354_1.6.2.4.1 testdef=None
207 00:15:19.703221 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:15:19.703486 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
209 00:15:19.705054 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:15:19.705847 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
212 00:15:19.707770 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:15:19.708623 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
215 00:15:19.710445 runner path: /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/0/tests/0_timesync-off test_uuid 915354_1.6.2.4.1
216 00:15:19.710998 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:15:19.711818 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
219 00:15:19.712066 Using /lava-915354 at stage 0
220 00:15:19.712426 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:15:19.712722 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/0/tests/1_kselftest-dt'
222 00:15:23.121745 Running '/usr/bin/git checkout kernelci.org
223 00:15:23.287234 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:15:23.288749 uuid=915354_1.6.2.4.5 testdef=None
225 00:15:23.289101 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:15:23.289851 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
228 00:15:23.292765 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:15:23.293587 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
231 00:15:23.297305 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:15:23.298173 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
234 00:15:23.301844 runner path: /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/0/tests/1_kselftest-dt test_uuid 915354_1.6.2.4.5
235 00:15:23.302142 BOARD='beaglebone-black'
236 00:15:23.302347 BRANCH='mainline'
237 00:15:23.302546 SKIPFILE='/dev/null'
238 00:15:23.302744 SKIP_INSTALL='True'
239 00:15:23.302938 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 00:15:23.303138 TST_CASENAME=''
241 00:15:23.303334 TST_CMDFILES='dt'
242 00:15:23.303896 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:15:23.304715 Creating lava-test-runner.conf files
245 00:15:23.304919 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915354/lava-overlay-npvgulzo/lava-915354/0 for stage 0
246 00:15:23.305271 - 0_timesync-off
247 00:15:23.305514 - 1_kselftest-dt
248 00:15:23.305847 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:15:23.306129 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
250 00:15:46.932925 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 00:15:46.933459 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 00:15:46.933765 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:15:46.934088 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 00:15:46.934392 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 00:15:47.363793 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:15:47.364308 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 00:15:47.364580 extracting modules file /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp
258 00:15:48.359691 extracting modules file /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915354/extract-overlay-ramdisk-34_utqa7/ramdisk
259 00:15:49.289519 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:15:49.290008 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 00:15:49.290309 [common] Applying overlay to NFS
262 00:15:49.290536 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915354/compress-overlay-dok7l6mg/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp
263 00:15:52.034929 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:15:52.035423 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 00:15:52.035731 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 00:15:52.036087 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:15:52.036388 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:15:52.036671 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 00:15:52.036944 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:15:52.037229 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 00:15:52.037500 Building ramdisk /var/lib/lava/dispatcher/tmp/915354/extract-overlay-ramdisk-34_utqa7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915354/extract-overlay-ramdisk-34_utqa7/ramdisk
272 00:15:53.165488 >> 79010 blocks
273 00:15:58.226619 Adding RAMdisk u-boot header.
274 00:15:58.227072 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915354/extract-overlay-ramdisk-34_utqa7/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915354/extract-overlay-ramdisk-34_utqa7/ramdisk.cpio.gz.uboot
275 00:15:58.391965 output: Image Name:
276 00:15:58.392606 output: Created: Thu Oct 31 00:15:58 2024
277 00:15:58.393024 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:15:58.393432 output: Data Size: 15354378 Bytes = 14994.51 KiB = 14.64 MiB
279 00:15:58.393835 output: Load Address: 00000000
280 00:15:58.394232 output: Entry Point: 00000000
281 00:15:58.394624 output:
282 00:15:58.395756 rename /var/lib/lava/dispatcher/tmp/915354/extract-overlay-ramdisk-34_utqa7/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot
283 00:15:58.396513 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:15:58.397056 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 00:15:58.397589 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:47) [common]
286 00:15:58.398044 No LXC device requested
287 00:15:58.398538 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:15:58.399044 start: 1.8 deploy-device-env (timeout 00:08:47) [common]
289 00:15:58.399535 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:15:58.399947 Checking files for TFTP limit of 4294967296 bytes.
291 00:15:58.402699 end: 1 tftp-deploy (duration 00:01:13) [common]
292 00:15:58.403275 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:15:58.403797 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:15:58.404341 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:15:58.404845 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:15:58.405595 substitutions:
297 00:15:58.406017 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:15:58.406424 - {DTB_ADDR}: 0x88000000
299 00:15:58.406824 - {DTB}: 915354/tftp-deploy-5s3mhpbf/dtb/am335x-boneblack.dtb
300 00:15:58.407220 - {INITRD}: 915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot
301 00:15:58.407616 - {KERNEL_ADDR}: 0x82000000
302 00:15:58.408032 - {KERNEL}: 915354/tftp-deploy-5s3mhpbf/kernel/zImage
303 00:15:58.408434 - {LAVA_MAC}: None
304 00:15:58.408863 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp
305 00:15:58.409262 - {NFS_SERVER_IP}: 192.168.6.2
306 00:15:58.409655 - {PRESEED_CONFIG}: None
307 00:15:58.410046 - {PRESEED_LOCAL}: None
308 00:15:58.410438 - {RAMDISK_ADDR}: 0x83000000
309 00:15:58.410827 - {RAMDISK}: 915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot
310 00:15:58.411221 - {ROOT_PART}: None
311 00:15:58.411608 - {ROOT}: None
312 00:15:58.412013 - {SERVER_IP}: 192.168.6.2
313 00:15:58.412405 - {TEE_ADDR}: 0x83000000
314 00:15:58.412793 - {TEE}: None
315 00:15:58.413180 Parsed boot commands:
316 00:15:58.413557 - setenv autoload no
317 00:15:58.413942 - setenv initrd_high 0xffffffff
318 00:15:58.414328 - setenv fdt_high 0xffffffff
319 00:15:58.414712 - dhcp
320 00:15:58.415095 - setenv serverip 192.168.6.2
321 00:15:58.415480 - tftp 0x82000000 915354/tftp-deploy-5s3mhpbf/kernel/zImage
322 00:15:58.415867 - tftp 0x83000000 915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot
323 00:15:58.416279 - setenv initrd_size ${filesize}
324 00:15:58.416666 - tftp 0x88000000 915354/tftp-deploy-5s3mhpbf/dtb/am335x-boneblack.dtb
325 00:15:58.417056 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:15:58.417454 - bootz 0x82000000 0x83000000 0x88000000
327 00:15:58.417943 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:15:58.419417 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:15:58.419837 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 00:15:58.434344 Setting prompt string to ['lava-test: # ']
332 00:15:58.435818 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:15:58.436444 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:15:58.436986 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:15:58.437520 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:15:58.438755 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 00:15:58.477460 >> OK - accepted request
338 00:15:58.479595 Returned 0 in 0 seconds
339 00:15:58.580743 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:15:58.582366 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:15:58.582929 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:15:58.583441 Setting prompt string to ['Hit any key to stop autoboot']
344 00:15:58.583900 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:15:58.585514 Trying 192.168.56.21...
346 00:15:58.586013 Connected to conserv1.
347 00:15:58.586430 Escape character is '^]'.
348 00:15:58.586838
349 00:15:58.587255 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 00:15:58.587679
351 00:16:06.343042
352 00:16:06.343661 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 00:16:06.348038 Trying to boot from MMC1
354 00:16:06.921382
355 00:16:06.921944
356 00:16:06.922369 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 00:16:06.922783
358 00:16:06.926796 CPU : AM335X-GP rev 2.1
359 00:16:06.927249 Model: TI AM335x BeagleBone Black
360 00:16:06.930890 DRAM: 512 MiB
361 00:16:07.013789 Core: 160 devices, 18 uclasses, devicetree: separate
362 00:16:07.023424 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 00:16:10.390817 7[r[999;999H[6n8NAND:
364 00:16:10.391556 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 00:16:10.395062 Trying to boot from MMC1
366 00:16:10.968200
367 00:16:10.969086
368 00:16:10.969775 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 00:16:10.970376
370 00:16:10.973584 CPU : AM335X-GP rev 2.1
371 00:16:10.974255 Model: TI AM335x BeagleBone Black
372 00:16:10.977016 DRAM: 512 MiB
373 00:16:11.059622 Core: 160 devices, 18 uclasses, devicetree: separate
374 00:16:11.070146 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 00:16:13.093577 7[r[999;999H[6n8NAND:
376 00:16:13.094387 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 00:16:13.098503 Trying to boot from MMC1
378 00:16:13.670595
379 00:16:13.671346
380 00:16:13.671899 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 00:16:13.672505
382 00:16:13.676012 CPU : AM335X-GP rev 2.1
383 00:16:13.676596 Model: TI AM335x BeagleBone Black
384 00:16:13.680117 DRAM: 512 MiB
385 00:16:13.762944 Core: 160 devices, 18 uclasses, devicetree: separate
386 00:16:13.772601 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 00:16:14.277218 7[r[999;999H[6n8NAND: 0 MiB
388 00:16:14.288156 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 00:16:14.360559 Loading Environment from FAT... Unable to use mmc 0:1...
390 00:16:14.381726 <ethaddr> not set. Validating first E-fuse MAC
391 00:16:14.412286 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 00:16:14.471613 Hit any key to stop autoboot: 2
394 00:16:14.472780 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 00:16:14.473442 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 00:16:14.473979 Setting prompt string to ['=>']
397 00:16:14.474549 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 00:16:14.481240 0
399 00:16:14.482194 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 00:16:14.482779 Sending with 10 millisecond of delay
402 00:16:15.619063 => setenv autoload no
403 00:16:15.629938 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 00:16:15.636885 setenv autoload no
405 00:16:15.637922 Sending with 10 millisecond of delay
407 00:16:17.435366 => setenv initrd_high 0xffffffff
408 00:16:17.446164 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 00:16:17.447009 setenv initrd_high 0xffffffff
410 00:16:17.447724 Sending with 10 millisecond of delay
412 00:16:19.064111 => setenv fdt_high 0xffffffff
413 00:16:19.074856 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 00:16:19.075702 setenv fdt_high 0xffffffff
415 00:16:19.076470 Sending with 10 millisecond of delay
417 00:16:19.368307 => dhcp
418 00:16:19.379012 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 00:16:19.379815 dhcp
420 00:16:19.381343 link up on port 0, speed 100, full duplex
421 00:16:19.381821 BOOTP broadcast 1
422 00:16:19.426539 DHCP client bound to address 192.168.6.12 (42 ms)
423 00:16:19.427289 Sending with 10 millisecond of delay
425 00:16:21.104742 => setenv serverip 192.168.6.2
426 00:16:21.115693 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 00:16:21.116850 setenv serverip 192.168.6.2
428 00:16:21.117698 Sending with 10 millisecond of delay
430 00:16:24.602028 => tftp 0x82000000 915354/tftp-deploy-5s3mhpbf/kernel/zImage
431 00:16:24.612785 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 00:16:24.613594 tftp 0x82000000 915354/tftp-deploy-5s3mhpbf/kernel/zImage
433 00:16:24.614037 link up on port 0, speed 100, full duplex
434 00:16:24.617354 Using ethernet@4a100000 device
435 00:16:24.622957 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 00:16:24.630245 Filename '915354/tftp-deploy-5s3mhpbf/kernel/zImage'.
437 00:16:24.630708 Load address: 0x82000000
438 00:16:27.151960 Loading: *################################################## 11.5 MiB
439 00:16:27.152655 4.6 MiB/s
440 00:16:27.153127 done
441 00:16:27.155589 Bytes transferred = 12050944 (b7e200 hex)
442 00:16:27.156472 Sending with 10 millisecond of delay
444 00:16:31.604637 => tftp 0x83000000 915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot
445 00:16:31.615435 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 00:16:31.616268 tftp 0x83000000 915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot
447 00:16:31.616721 link up on port 0, speed 100, full duplex
448 00:16:31.620157 Using ethernet@4a100000 device
449 00:16:31.625731 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 00:16:31.634318 Filename '915354/tftp-deploy-5s3mhpbf/ramdisk/ramdisk.cpio.gz.uboot'.
451 00:16:31.634806 Load address: 0x83000000
452 00:16:34.782476 Loading: *################################################## 14.6 MiB
453 00:16:34.783101 4.7 MiB/s
454 00:16:34.783535 done
455 00:16:34.785998 Bytes transferred = 15354442 (ea4a4a hex)
456 00:16:34.786809 Sending with 10 millisecond of delay
458 00:16:36.644544 => setenv initrd_size ${filesize}
459 00:16:36.655348 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 00:16:36.656246 setenv initrd_size ${filesize}
461 00:16:36.656964 Sending with 10 millisecond of delay
463 00:16:40.804103 => tftp 0x88000000 915354/tftp-deploy-5s3mhpbf/dtb/am335x-boneblack.dtb
464 00:16:40.814892 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 00:16:40.815788 tftp 0x88000000 915354/tftp-deploy-5s3mhpbf/dtb/am335x-boneblack.dtb
466 00:16:40.816306 link up on port 0, speed 100, full duplex
467 00:16:40.819624 Using ethernet@4a100000 device
468 00:16:40.825297 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 00:16:40.838435 Filename '915354/tftp-deploy-5s3mhpbf/dtb/am335x-boneblack.dtb'.
470 00:16:40.838950 Load address: 0x88000000
471 00:16:40.849362 Loading: *################################################## 68.9 KiB
472 00:16:40.849842 4.5 MiB/s
473 00:16:40.850280 done
474 00:16:40.855800 Bytes transferred = 70568 (113a8 hex)
475 00:16:40.856582 Sending with 10 millisecond of delay
477 00:16:54.033301 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 00:16:54.044171 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 00:16:54.045145 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 00:16:54.045912 Sending with 10 millisecond of delay
482 00:16:56.388110 => bootz 0x82000000 0x83000000 0x88000000
483 00:16:56.399262 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 00:16:56.400025 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 00:16:56.401346 bootz 0x82000000 0x83000000 0x88000000
486 00:16:56.401934 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
487 00:16:56.402478 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 00:16:56.406806 Image Name:
489 00:16:56.407388 Created: 2024-10-31 0:15:58 UTC
490 00:16:56.410217 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 00:16:56.415781 Data Size: 15354378 Bytes = 14.6 MiB
492 00:16:56.423925 Load Address: 00000000
493 00:16:56.424547 Entry Point: 00000000
494 00:16:56.598939 Verifying Checksum ... OK
495 00:16:56.599692 ## Flattened Device Tree blob at 88000000
496 00:16:56.605434 Booting using the fdt blob at 0x88000000
497 00:16:56.609401 Using Device Tree in place at 88000000, end 880143a7
498 00:16:56.623128
499 00:16:56.623834 Starting kernel ...
500 00:16:56.624417
501 00:16:56.625505 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 00:16:56.626257 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 00:16:56.626856 Setting prompt string to ['Linux version [0-9]']
504 00:16:56.627585 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 00:16:56.628303 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 00:16:57.514105 [ 0.000000] Booting Linux on physical CPU 0x0
507 00:16:57.520041 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 00:16:57.520747 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 00:16:57.521348 Setting prompt string to []
510 00:16:57.521984 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 00:16:57.522596 Using line separator: #'\n'#
512 00:16:57.523125 No login prompt set.
513 00:16:57.523681 Parsing kernel messages
514 00:16:57.524364 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 00:16:57.525416 [login-action] Waiting for messages, (timeout 00:04:01)
516 00:16:57.526007 Waiting using forced prompt support (timeout 00:02:00)
517 00:16:57.534165 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j357684-arm-clang-15-multi-v7-defconfig-5cmr8) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Wed Oct 30 23:48:33 UTC 2024
518 00:16:57.540178 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 00:16:57.545677 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 00:16:57.551883 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 00:16:57.557270 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 00:16:57.562729 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 00:16:57.568487 [ 0.000000] Memory policy: Data cache writeback
524 00:16:57.575321 [ 0.000000] efi: UEFI not found.
525 00:16:57.579872 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 00:16:57.585578 [ 0.000000] Zone ranges:
527 00:16:57.591360 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 00:16:57.597069 [ 0.000000] Normal empty
529 00:16:57.597707 [ 0.000000] HighMem empty
530 00:16:57.602802 [ 0.000000] Movable zone start for each node
531 00:16:57.603442 [ 0.000000] Early memory node ranges
532 00:16:57.614205 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 00:16:57.619558 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 00:16:57.637572 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 00:16:57.643200 [ 0.000000] AM335X ES2.1 (sgx neon)
536 00:16:57.654943 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
537 00:16:57.672831 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 00:16:57.684383 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 00:16:57.690440 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 00:16:57.696167 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 00:16:57.705897 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 00:16:57.735110 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 00:16:57.741030 <6>[ 0.000000] trace event string verifier disabled
544 00:16:57.741702 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 00:16:57.749148 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 00:16:57.754778 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 00:16:57.766270 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 00:16:57.771178 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 00:16:57.786421 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 00:16:57.804013 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 00:16:57.809728 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 00:16:57.910475 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 00:16:57.919112 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 00:16:57.931669 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 00:16:57.939637 <6>[ 0.019184] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 00:16:57.949395 <6>[ 0.034213] Console: colour dummy device 80x30
557 00:16:57.955513 Matched prompt #6: WARNING:
558 00:16:57.956268 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 00:16:57.960836 <3>[ 0.039115] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 00:16:57.969982 <3>[ 0.046193] This ensures that you still see kernel messages. Please
561 00:16:57.970635 <3>[ 0.052924] update your kernel commandline.
562 00:16:58.010352 <6>[ 0.057538] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 00:16:58.015963 <6>[ 0.096194] CPU: Testing write buffer coherency: ok
564 00:16:58.021913 <6>[ 0.101564] CPU0: Spectre v2: using BPIALL workaround
565 00:16:58.022475 <6>[ 0.107032] pid_max: default: 32768 minimum: 301
566 00:16:58.033426 <6>[ 0.112229] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 00:16:58.040394 <6>[ 0.120054] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 00:16:58.047493 <6>[ 0.129432] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 00:16:58.055912 <6>[ 0.136448] Setting up static identity map for 0x80300000 - 0x803000ac
570 00:16:58.061706 <6>[ 0.146140] rcu: Hierarchical SRCU implementation.
571 00:16:58.069419 <6>[ 0.151423] rcu: Max phase no-delay instances is 1000.
572 00:16:58.078094 <6>[ 0.162757] EFI services will not be available.
573 00:16:58.083970 <6>[ 0.168050] smp: Bringing up secondary CPUs ...
574 00:16:58.089696 <6>[ 0.173110] smp: Brought up 1 node, 1 CPU
575 00:16:58.097877 <6>[ 0.177510] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 00:16:58.103838 <6>[ 0.184284] CPU: All CPU(s) started in SVC mode.
577 00:16:58.116031 <6>[ 0.189504] Memory: 404428K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50620K reserved, 65536K cma-reserved, 0K highmem)
578 00:16:58.121793 <6>[ 0.205792] devtmpfs: initialized
579 00:16:58.144823 <6>[ 0.223632] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 00:16:58.156359 <6>[ 0.232253] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 00:16:58.162248 <6>[ 0.242723] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 00:16:58.172058 <6>[ 0.255010] pinctrl core: initialized pinctrl subsystem
583 00:16:58.182503 <6>[ 0.265842] DMI not present or invalid.
584 00:16:58.190883 <6>[ 0.271743] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 00:16:58.200423 <6>[ 0.280755] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 00:16:58.215643 <6>[ 0.292421] thermal_sys: Registered thermal governor 'step_wise'
587 00:16:58.216284 <6>[ 0.292595] cpuidle: using governor menu
588 00:16:58.243242 <6>[ 0.328131] No ATAGs?
589 00:16:58.249446 <6>[ 0.330871] hw-breakpoint: debug architecture 0x4 unsupported.
590 00:16:58.259800 <6>[ 0.343017] Serial: AMBA PL011 UART driver
591 00:16:58.290782 <6>[ 0.375638] iommu: Default domain type: Translated
592 00:16:58.299896 <6>[ 0.380993] iommu: DMA domain TLB invalidation policy: strict mode
593 00:16:58.326482 <5>[ 0.410723] SCSI subsystem initialized
594 00:16:58.332358 <6>[ 0.415646] usbcore: registered new interface driver usbfs
595 00:16:58.338152 <6>[ 0.421709] usbcore: registered new interface driver hub
596 00:16:58.345014 <6>[ 0.427504] usbcore: registered new device driver usb
597 00:16:58.350788 <6>[ 0.434069] pps_core: LinuxPPS API ver. 1 registered
598 00:16:58.362234 <6>[ 0.439502] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 00:16:58.369479 <6>[ 0.449188] PTP clock support registered
600 00:16:58.370038 <6>[ 0.453654] EDAC MC: Ver: 3.0.0
601 00:16:58.427279 <6>[ 0.509292] scmi_core: SCMI protocol bus registered
602 00:16:58.432904 <6>[ 0.517494] vgaarb: loaded
603 00:16:58.445230 <6>[ 0.530284] clocksource: Switched to clocksource dmtimer
604 00:16:58.484489 <6>[ 0.568908] NET: Registered PF_INET protocol family
605 00:16:58.497571 <6>[ 0.574634] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 00:16:58.503084 <6>[ 0.583638] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 00:16:58.515076 <6>[ 0.592572] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 00:16:58.520408 <6>[ 0.600836] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 00:16:58.531642 <6>[ 0.609105] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 00:16:58.537492 <6>[ 0.616825] TCP: Hash tables configured (established 4096 bind 4096)
611 00:16:58.543406 <6>[ 0.623743] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 00:16:58.549398 <6>[ 0.630788] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 00:16:58.556123 <6>[ 0.638374] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 00:16:58.638494 <6>[ 0.717746] RPC: Registered named UNIX socket transport module.
615 00:16:58.639017 <6>[ 0.724186] RPC: Registered udp transport module.
616 00:16:58.644308 <6>[ 0.729289] RPC: Registered tcp transport module.
617 00:16:58.653254 <6>[ 0.734422] RPC: Registered tcp-with-tls transport module.
618 00:16:58.658528 <6>[ 0.740349] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 00:16:58.666705 <6>[ 0.747261] PCI: CLS 0 bytes, default 64
620 00:16:58.669622 <5>[ 0.753127] Initialise system trusted keyrings
621 00:16:58.693939 <6>[ 0.774199] Trying to unpack rootfs image as initramfs...
622 00:16:58.762873 <6>[ 0.841613] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 00:16:58.767674 <6>[ 0.849129] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 00:16:58.806552 <5>[ 0.891475] NFS: Registering the id_resolver key type
625 00:16:58.812498 <5>[ 0.897061] Key type id_resolver registered
626 00:16:58.818690 <5>[ 0.901768] Key type id_legacy registered
627 00:16:58.823963 <6>[ 0.906214] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 00:16:58.833361 <6>[ 0.913428] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 00:16:58.916196 <5>[ 1.001188] Key type asymmetric registered
630 00:16:58.922363 <5>[ 1.005714] Asymmetric key parser 'x509' registered
631 00:16:58.930493 <6>[ 1.011289] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 00:16:58.936491 <6>[ 1.019177] io scheduler mq-deadline registered
633 00:16:58.941997 <6>[ 1.024158] io scheduler kyber registered
634 00:16:58.942515 <6>[ 1.028615] io scheduler bfq registered
635 00:16:59.039854 <6>[ 1.121131] ledtrig-cpu: registered to indicate activity on CPUs
636 00:16:59.336262 <6>[ 1.416993] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 00:16:59.382285 <6>[ 1.466003] msm_serial: driver initialized
638 00:16:59.387347 <6>[ 1.471047] SuperH (H)SCI(F) driver initialized
639 00:16:59.393402 <6>[ 1.476168] STMicroelectronics ASC driver initialized
640 00:16:59.399277 <6>[ 1.481868] STM32 USART driver initialized
641 00:16:59.527494 <6>[ 1.611423] brd: module loaded
642 00:16:59.567383 <6>[ 1.650920] loop: module loaded
643 00:16:59.611840 <6>[ 1.695716] CAN device driver interface
644 00:16:59.618127 <6>[ 1.700901] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 00:16:59.624588 <6>[ 1.707839] e1000e: Intel(R) PRO/1000 Network Driver
646 00:16:59.629710 <6>[ 1.713292] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 00:16:59.635849 <6>[ 1.719710] igb: Intel(R) Gigabit Ethernet Network Driver
648 00:16:59.643787 <6>[ 1.725557] igb: Copyright (c) 2007-2014 Intel Corporation.
649 00:16:59.655598 <6>[ 1.734746] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 00:16:59.661247 <6>[ 1.740920] usbcore: registered new interface driver pegasus
651 00:16:59.667558 <6>[ 1.747050] usbcore: registered new interface driver asix
652 00:16:59.674198 <6>[ 1.752938] usbcore: registered new interface driver ax88179_178a
653 00:16:59.678615 <6>[ 1.759507] usbcore: registered new interface driver cdc_ether
654 00:16:59.684401 <6>[ 1.765832] usbcore: registered new interface driver smsc75xx
655 00:16:59.690186 <6>[ 1.772061] usbcore: registered new interface driver smsc95xx
656 00:16:59.696765 <6>[ 1.778281] usbcore: registered new interface driver net1080
657 00:16:59.701741 <6>[ 1.784426] usbcore: registered new interface driver cdc_subset
658 00:16:59.707580 <6>[ 1.790860] usbcore: registered new interface driver zaurus
659 00:16:59.717962 <6>[ 1.796906] usbcore: registered new interface driver cdc_ncm
660 00:16:59.725058 <6>[ 1.806358] usbcore: registered new interface driver usb-storage
661 00:17:00.020043 <6>[ 2.102843] i2c_dev: i2c /dev entries driver
662 00:17:00.070429 <5>[ 2.147264] cpuidle: enable-method property 'ti,am3352' found operations
663 00:17:00.076230 <6>[ 2.156942] sdhci: Secure Digital Host Controller Interface driver
664 00:17:00.083670 <6>[ 2.163719] sdhci: Copyright(c) Pierre Ossman
665 00:17:00.090880 <6>[ 2.170122] Synopsys Designware Multimedia Card Interface Driver
666 00:17:00.095687 <6>[ 2.178056] sdhci-pltfm: SDHCI platform and OF driver helper
667 00:17:00.225032 <6>[ 2.303532] usbcore: registered new interface driver usbhid
668 00:17:00.225454 <6>[ 2.309572] usbhid: USB HID core driver
669 00:17:00.274346 <6>[ 2.356655] NET: Registered PF_INET6 protocol family
670 00:17:00.313309 <6>[ 2.398214] Segment Routing with IPv6
671 00:17:00.319068 <6>[ 2.402439] In-situ OAM (IOAM) with IPv6
672 00:17:00.325795 <6>[ 2.406844] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 00:17:00.331441 <6>[ 2.414160] NET: Registered PF_PACKET protocol family
674 00:17:00.337366 <6>[ 2.419648] can: controller area network core
675 00:17:00.343209 <6>[ 2.424543] NET: Registered PF_CAN protocol family
676 00:17:00.343532 <6>[ 2.429747] can: raw protocol
677 00:17:00.349024 <6>[ 2.433110] can: broadcast manager protocol
678 00:17:00.355461 <6>[ 2.437690] can: netlink gateway - max_hops=1
679 00:17:00.361527 <5>[ 2.443214] Key type dns_resolver registered
680 00:17:00.367870 <6>[ 2.448205] ThumbEE CPU extension supported.
681 00:17:00.368188 <5>[ 2.453045] Registering SWP/SWPB emulation handler
682 00:17:00.377707 <3>[ 2.458705] omap_voltage_late_init: Voltage driver support not added
683 00:17:00.584172 <5>[ 2.667538] Loading compiled-in X.509 certificates
684 00:17:00.727962 <6>[ 2.799966] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 00:17:00.735142 <6>[ 2.816694] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 00:17:00.761633 <3>[ 2.841000] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 00:17:00.961728 <3>[ 3.040619] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 00:17:01.158391 <6>[ 3.241512] OMAP GPIO hardware version 0.1
689 00:17:01.179439 <6>[ 3.260698] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 00:17:01.251174 <4>[ 3.332173] at24 2-0054: supply vcc not found, using dummy regulator
691 00:17:01.285008 <4>[ 3.366021] at24 2-0055: supply vcc not found, using dummy regulator
692 00:17:01.323157 <4>[ 3.404180] at24 2-0056: supply vcc not found, using dummy regulator
693 00:17:01.364117 <4>[ 3.446057] at24 2-0057: supply vcc not found, using dummy regulator
694 00:17:01.401032 <6>[ 3.483657] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 00:17:01.455522 <3>[ 3.533334] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 00:17:01.480648 <6>[ 3.554721] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 00:17:01.503042 <4>[ 3.581537] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 00:17:01.510799 <4>[ 3.590569] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 00:17:01.593116 <6>[ 3.677062] Freeing initrd memory: 14996K
700 00:17:01.601436 <6>[ 3.682607] omap_rng 48310000.rng: Random Number Generator ver. 20
701 00:17:01.625524 <5>[ 3.709541] random: crng init done
702 00:17:01.670596 <6>[ 3.750318] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 00:17:01.723900 <6>[ 3.802750] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 00:17:01.729800 <6>[ 3.813071] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 00:17:01.741510 <6>[ 3.820410] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 00:17:01.747379 <6>[ 3.827892] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 00:17:01.758866 <6>[ 3.836026] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 00:17:01.766389 <6>[ 3.847668] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 00:17:01.779511 <5>[ 3.856792] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 00:17:01.807951 <3>[ 3.887260] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 00:17:01.813763 <6>[ 3.895861] edma 49000000.dma: TI EDMA DMA engine driver
712 00:17:01.886361 <3>[ 3.965003] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 00:17:01.901239 <6>[ 3.979494] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 00:17:01.914405 <3>[ 3.996811] l3-aon-clkctrl:0000:0: failed to disable
715 00:17:01.969965 <6>[ 4.049064] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 00:17:01.975604 <6>[ 4.058576] printk: legacy console [ttyS0] enabled
717 00:17:01.981239 <6>[ 4.058576] printk: legacy console [ttyS0] enabled
718 00:17:01.986960 <6>[ 4.068908] printk: legacy bootconsole [omap8250] disabled
719 00:17:01.992784 <6>[ 4.068908] printk: legacy bootconsole [omap8250] disabled
720 00:17:02.022939 <4>[ 4.101115] tps65217-pmic: Failed to locate of_node [id: -1]
721 00:17:02.026131 <4>[ 4.108521] tps65217-bl: Failed to locate of_node [id: -1]
722 00:17:02.043393 <6>[ 4.128656] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 00:17:02.061922 <6>[ 4.135671] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 00:17:02.073546 <6>[ 4.149384] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 00:17:02.079317 <6>[ 4.161281] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 00:17:02.101922 <6>[ 4.181416] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 00:17:02.107717 <6>[ 4.190582] sdhci-omap 48060000.mmc: Got CD GPIO
728 00:17:02.115817 <4>[ 4.195726] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 00:17:02.130725 <4>[ 4.209556] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 00:17:02.137165 <4>[ 4.218353] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 00:17:02.146610 <4>[ 4.227005] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 00:17:02.270713 <6>[ 4.352336] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 00:17:02.318222 <6>[ 4.397341] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 00:17:02.324823 <6>[ 4.406006] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 00:17:02.334034 <6>[ 4.415014] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 00:17:02.384620 <6>[ 4.460022] mmc0: new high speed SDHC card at address 1234
737 00:17:02.385126 <6>[ 4.467854] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 00:17:02.391320 <6>[ 4.477211] mmcblk0: p1
739 00:17:02.414794 <6>[ 4.491771] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 00:17:02.436304 <6>[ 4.511972] mmc1: new high speed MMC card at address 0001
741 00:17:02.436782 <6>[ 4.519446] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 00:17:02.446027 <6>[ 4.529354] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 00:17:02.453672 <6>[ 4.536481] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 00:17:02.459219 <6>[ 4.543681] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 00:17:04.512035 <6>[ 6.591358] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 00:17:04.575319 <5>[ 6.620314] Sending DHCP requests ., OK
747 00:17:04.586673 <6>[ 6.664832] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 00:17:04.587147 <6>[ 6.672985] IP-Config: Complete:
749 00:17:04.597972 <6>[ 6.676524] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 00:17:04.603740 <6>[ 6.687068] host=192.168.6.12, domain=, nis-domain=(none)
751 00:17:04.616105 <6>[ 6.693286] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 00:17:04.616569 <6>[ 6.693323] nameserver0=10.255.253.1
753 00:17:04.622289 <6>[ 6.705933] clk: Disabling unused clocks
754 00:17:04.628120 <6>[ 6.710725] PM: genpd: Disabling unused power domains
755 00:17:04.645371 <6>[ 6.727163] Freeing unused kernel image (initmem) memory: 2048K
756 00:17:04.652950 <6>[ 6.736989] Run /init as init process
757 00:17:04.677696 Loading, please wait...
758 00:17:04.754604 Starting systemd-udevd version 252.22-1~deb12u1
759 00:17:07.781628 <4>[ 9.859650] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 00:17:07.964085 <4>[ 10.041879] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 00:17:08.106674 <6>[ 10.192163] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 00:17:08.117437 <6>[ 10.197839] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 00:17:08.347033 <6>[ 10.430886] hub 1-0:1.0: USB hub found
764 00:17:08.416659 <6>[ 10.500487] hub 1-0:1.0: 1 port detected
765 00:17:08.440047 <6>[ 10.523548] tda998x 0-0070: found TDA19988
766 00:17:11.808255 Begin: Loading essential drivers ... done.
767 00:17:11.815800 Begin: Running /scripts/init-premount ... done.
768 00:17:11.826977 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 00:17:11.833442 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 00:17:11.840545 Device /sys/class/net/eth0 found
771 00:17:11.840811 done.
772 00:17:11.917527 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 00:17:11.987830 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 00:17:12.006053 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 00:17:12.011728 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 00:17:12.017243 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 00:17:12.026121 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 00:17:12.032047 rootserver: 192.168.6.1 rootpath:
779 00:17:12.032440 filename :
780 00:17:12.166491 done.
781 00:17:12.174343 Begin: Running /scripts/nfs-bottom ... done.
782 00:17:12.249009 Begin: Running /scripts/init-bottom ... done.
783 00:17:13.685165 <30>[ 15.766406] systemd[1]: System time before build time, advancing clock.
784 00:17:13.868456 <30>[ 15.924444] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 00:17:13.878256 <30>[ 15.961387] systemd[1]: Detected architecture arm.
786 00:17:13.890913
787 00:17:13.891524 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 00:17:13.892051
789 00:17:13.919064 <30>[ 16.001114] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 00:17:16.165280 <30>[ 18.246169] systemd[1]: Queued start job for default target graphical.target.
791 00:17:16.182355 <30>[ 18.261386] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 00:17:16.190107 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 00:17:16.214277 <30>[ 18.293363] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 00:17:16.222700 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 00:17:16.244785 <30>[ 18.323776] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 00:17:16.253283 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 00:17:16.272943 <30>[ 18.352351] systemd[1]: Created slice user.slice - User and Session Slice.
798 00:17:16.279704 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 00:17:16.308046 <30>[ 18.381691] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 00:17:16.314111 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 00:17:16.332014 <30>[ 18.411481] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 00:17:16.343122 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 00:17:16.372954 <30>[ 18.441471] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 00:17:16.379434 <30>[ 18.462026] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 00:17:16.388016 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 00:17:16.411024 <30>[ 18.490756] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 00:17:16.419293 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 00:17:16.441699 <30>[ 18.521111] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 00:17:16.450195 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 00:17:16.471648 <30>[ 18.551248] systemd[1]: Reached target paths.target - Path Units.
811 00:17:16.476773 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 00:17:16.501293 <30>[ 18.580963] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 00:17:16.508778 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 00:17:16.531125 <30>[ 18.610805] systemd[1]: Reached target slices.target - Slice Units.
815 00:17:16.536594 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 00:17:16.561451 <30>[ 18.641134] systemd[1]: Reached target swap.target - Swaps.
817 00:17:16.565530 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 00:17:16.591552 <30>[ 18.671004] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 00:17:16.599471 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 00:17:16.622733 <30>[ 18.702038] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 00:17:16.631012 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 00:17:16.712886 <30>[ 18.787342] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 00:17:16.725683 <30>[ 18.804955] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 00:17:16.734107 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 00:17:16.763419 <30>[ 18.842122] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 00:17:16.770894 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 00:17:16.795005 <30>[ 18.874079] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 00:17:16.803083 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 00:17:16.833361 <30>[ 18.911951] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 00:17:16.839028 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 00:17:16.862743 <30>[ 18.942029] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 00:17:16.871244 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 00:17:16.898753 <30>[ 18.972113] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 00:17:16.915391 <30>[ 18.988799] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 00:17:16.965298 <30>[ 19.045619] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 00:17:16.996562 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 00:17:17.051213 <30>[ 19.131388] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 00:17:17.070719 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 00:17:17.142315 <30>[ 19.221559] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 00:17:17.169542 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 00:17:17.221758 <30>[ 19.301504] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 00:17:17.251287 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 00:17:17.302189 <30>[ 19.382257] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 00:17:17.323727 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 00:17:17.349028 <30>[ 19.429737] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 00:17:17.371271 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 00:17:17.414326 <30>[ 19.493829] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 00:17:17.432698 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 00:17:17.480928 <30>[ 19.561555] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 00:17:17.498333 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 00:17:17.567532 <30>[ 19.647952] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 00:17:17.588660 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 00:17:17.622137 <28>[ 19.694432] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 00:17:17.630661 <28>[ 19.710218] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 00:17:17.671306 <30>[ 19.752326] systemd[1]: Starting systemd-journald.service - Journal Service...
856 00:17:17.689199 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 00:17:17.771551 <30>[ 19.851814] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 00:17:17.795603 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 00:17:17.842875 <30>[ 19.923468] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 00:17:17.884351 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 00:17:17.935839 <30>[ 20.014885] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 00:17:17.982505 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 00:17:18.073684 <30>[ 20.153412] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 00:17:18.121035 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 00:17:18.178076 <30>[ 20.258680] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 00:17:18.241006 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 00:17:18.261939 <30>[ 20.342313] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 00:17:18.294695 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 00:17:18.324031 <30>[ 20.403381] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 00:17:18.349717 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 00:17:18.521846 <30>[ 20.603021] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 00:17:18.552269 <30>[ 20.632263] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 00:17:18.581133 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 00:17:18.611844 <30>[ 20.693184] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 00:17:18.641071 <30>[ 20.720891] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 00:17:18.649628 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 00:17:18.667137 <30>[ 20.748444] systemd[1]: Started systemd-journald.service - Journal Service.
878 00:17:18.690222 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 00:17:18.730979 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 00:17:18.757153 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 00:17:18.792420 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 00:17:18.823187 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 00:17:18.844832 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 00:17:18.881185 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 00:17:18.911435 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 00:17:18.935705 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 00:17:19.000686 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 00:17:19.048826 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 00:17:19.115274 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 00:17:19.195301 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 00:17:19.262544 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 00:17:19.441307 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 00:17:19.462012 <46>[ 21.542413] systemd-journald[163]: Received client request to flush runtime journal.
894 00:17:19.572484 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 00:17:19.717513 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 00:17:20.487833 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 00:17:20.556144 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 00:17:21.218549 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 00:17:21.383410 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 00:17:21.403088 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 00:17:21.420921 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 00:17:21.483813 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 00:17:21.525980 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 00:17:22.479121 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 00:17:22.552319 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 00:17:22.851042 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 00:17:22.922499 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 00:17:23.015506 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 00:17:24.934314 <5>[ 27.015110] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 00:17:24.984728 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
911 00:17:25.679905 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 00:17:26.683905 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 00:17:26.749323 <5>[ 28.832448] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 00:17:26.859937 <5>[ 28.941504] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
915 00:17:26.874435 <4>[ 28.955228] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
916 00:17:26.880335 <6>[ 28.964350] cfg80211: failed to load regulatory.db
917 00:17:28.199083 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
918 00:17:28.234550 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
919 00:17:28.296351 <46>[ 30.368338] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
920 00:17:28.429480 <46>[ 30.503573] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
921 00:17:37.062225 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 00:17:37.093908 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 00:17:37.122506 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 00:17:37.142664 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 00:17:37.215107 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 00:17:37.280350 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 00:17:37.321450 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 00:17:37.363682 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 00:17:37.424012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 00:17:37.458089 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 00:17:37.490535 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 00:17:37.516960 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 00:17:37.546360 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 00:17:37.594231 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 00:17:37.626627 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 00:17:37.653009 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 00:17:37.701011 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 00:17:37.732824 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 00:17:37.753766 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 00:17:37.786164 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 00:17:37.822296 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 00:17:37.839351 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 00:17:37.863482 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 00:17:37.941144 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 00:17:37.977505 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 00:17:38.128920 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 00:17:38.221846 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 00:17:38.254641 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 00:17:38.341258 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 00:17:38.351177 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 00:17:38.551282 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 00:17:38.630365 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 00:17:38.662910 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 00:17:38.690848 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 00:17:38.712395 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 00:17:38.991534 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 00:17:39.331293 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 00:17:39.382877 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 00:17:39.415685 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 00:17:39.491477 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 00:17:39.696961 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 00:17:39.814051
963 00:17:39.817564 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
964 00:17:39.818097
965 00:17:40.184038 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Wed Oct 30 23:48:33 UTC 2024 armv7l
966 00:17:40.184650
967 00:17:40.189652 The programs included with the Debian GNU/Linux system are free software;
968 00:17:40.195354 the exact distribution terms for each program are described in the
969 00:17:40.200828 individual files in /usr/share/doc/*/copyright.
970 00:17:40.201402
971 00:17:40.208903 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 00:17:40.209406 permitted by applicable law.
973 00:17:44.960770 Unable to match end of the kernel message
975 00:17:44.962339 Setting prompt string to ['/ #']
976 00:17:44.962918 end: 2.4.4.1 login-action (duration 00:00:47) [common]
978 00:17:44.964364 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
979 00:17:44.964897 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
980 00:17:44.965351 Setting prompt string to ['/ #']
981 00:17:44.965784 Forcing a shell prompt, looking for ['/ #']
983 00:17:45.016812 / #
984 00:17:45.017598 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 00:17:45.018214 Waiting using forced prompt support (timeout 00:02:30)
986 00:17:45.030521
987 00:17:45.043215 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 00:17:45.043835 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
989 00:17:45.044348 Sending with 10 millisecond of delay
991 00:17:50.031649 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp'
992 00:17:50.042657 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/915354/extract-nfsrootfs-tajroarp'
993 00:17:50.044603 Sending with 10 millisecond of delay
995 00:17:52.143194 / # export NFS_SERVER_IP='192.168.6.2'
996 00:17:52.154201 export NFS_SERVER_IP='192.168.6.2'
997 00:17:52.155402 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 00:17:52.156103 end: 2.4 uboot-commands (duration 00:01:54) [common]
999 00:17:52.156756 end: 2 uboot-action (duration 00:01:54) [common]
1000 00:17:52.157381 start: 3 lava-test-retry (timeout 00:06:53) [common]
1001 00:17:52.158008 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1002 00:17:52.158517 Using namespace: common
1004 00:17:52.259800 / # #
1005 00:17:52.260607 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 00:17:52.264950 #
1007 00:17:52.271606 Using /lava-915354
1009 00:17:52.372910 / # export SHELL=/bin/bash
1010 00:17:52.377848 export SHELL=/bin/bash
1012 00:17:52.485220 / # . /lava-915354/environment
1013 00:17:52.490665 . /lava-915354/environment
1015 00:17:52.617066 / # /lava-915354/bin/lava-test-runner /lava-915354/0
1016 00:17:52.617779 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 00:17:52.622240 /lava-915354/bin/lava-test-runner /lava-915354/0
1018 00:17:53.035876 + export TESTRUN_ID=0_timesync-off
1019 00:17:53.043469 + TESTRUN_ID=0_timesync-off
1020 00:17:53.044019 + cd /lava-915354/0/tests/0_timesync-off
1021 00:17:53.044502 ++ cat uuid
1022 00:17:53.060944 + UUID=915354_1.6.2.4.1
1023 00:17:53.061447 + set +x
1024 00:17:53.069218 <LAVA_SIGNAL_STARTRUN 0_timesync-off 915354_1.6.2.4.1>
1025 00:17:53.069704 + systemctl stop systemd-timesyncd
1026 00:17:53.070459 Received signal: <STARTRUN> 0_timesync-off 915354_1.6.2.4.1
1027 00:17:53.070936 Starting test lava.0_timesync-off (915354_1.6.2.4.1)
1028 00:17:53.071502 Skipping test definition patterns.
1029 00:17:53.353898 + set +x
1030 00:17:53.354554 <LAVA_SIGNAL_ENDRUN 0_timesync-off 915354_1.6.2.4.1>
1031 00:17:53.355306 Received signal: <ENDRUN> 0_timesync-off 915354_1.6.2.4.1
1032 00:17:53.355857 Ending use of test pattern.
1033 00:17:53.356376 Ending test lava.0_timesync-off (915354_1.6.2.4.1), duration 0.29
1035 00:17:53.541707 + export TESTRUN_ID=1_kselftest-dt
1036 00:17:53.548692 + TESTRUN_ID=1_kselftest-dt
1037 00:17:53.549208 + cd /lava-915354/0/tests/1_kselftest-dt
1038 00:17:53.549680 ++ cat uuid
1039 00:17:53.567351 + UUID=915354_1.6.2.4.5
1040 00:17:53.567950 + set +x
1041 00:17:53.572917 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 915354_1.6.2.4.5>
1042 00:17:53.573441 + cd ./automated/linux/kselftest/
1043 00:17:53.574203 Received signal: <STARTRUN> 1_kselftest-dt 915354_1.6.2.4.5
1044 00:17:53.574683 Starting test lava.1_kselftest-dt (915354_1.6.2.4.5)
1045 00:17:53.575231 Skipping test definition patterns.
1046 00:17:53.600426 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 00:17:53.711086 INFO: install_deps skipped
1048 00:17:54.351281 --2024-10-31 00:17:54-- http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1049 00:17:54.375794 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 00:17:54.521557 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 00:17:54.665164 HTTP request sent, awaiting response... 200 OK
1052 00:17:54.665779 Length: 2714384 (2.6M) [application/octet-stream]
1053 00:17:54.670523 Saving to: 'kselftest_armhf.tar.gz'
1054 00:17:54.670980
1055 00:17:55.912306
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 8%[> ] 218.67K 383KB/s
kselftest_armhf.tar 26%[====> ] 701.45K 900KB/s
kselftest_armhf.tar 54%[=========> ] 1.42M 1.28MB/s
kselftest_armhf.tar 100%[===================>] 2.59M 2.09MB/s in 1.2s
1056 00:17:55.912967
1057 00:17:56.238557 2024-10-31 00:17:55 (2.09 MB/s) - 'kselftest_armhf.tar.gz' saved [2714384/2714384]
1058 00:17:56.239184
1059 00:18:07.761460 skiplist:
1060 00:18:07.762093 ========================================
1061 00:18:07.767316 ========================================
1062 00:18:07.890230 dt:test_unprobed_devices.sh
1063 00:18:07.921466 ============== Tests to run ===============
1064 00:18:07.929602 dt:test_unprobed_devices.sh
1065 00:18:07.933630 ===========End Tests to run ===============
1066 00:18:07.945183 shardfile-dt pass
1067 00:18:08.174811 <12>[ 70.261350] kselftest: Running tests in dt
1068 00:18:08.203005 TAP version 13
1069 00:18:08.227335 1..1
1070 00:18:08.282092 # timeout set to 45
1071 00:18:08.282593 # selftests: dt: test_unprobed_devices.sh
1072 00:18:09.183633 # TAP version 13
1073 00:18:34.618965 # 1..257
1074 00:18:34.817583 # ok 1 / # SKIP
1075 00:18:34.840059 # ok 2 /clk_mcasp0
1076 00:18:34.912585 # ok 3 /clk_mcasp0_fixed # SKIP
1077 00:18:34.985718 # ok 4 /cpus/cpu@0 # SKIP
1078 00:18:35.061615 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 00:18:35.088169 # ok 6 /fixedregulator0
1080 00:18:35.101680 # ok 7 /leds
1081 00:18:35.124221 # ok 8 /ocp
1082 00:18:35.153383 # ok 9 /ocp/interconnect@44c00000
1083 00:18:35.179127 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 00:18:35.198307 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 00:18:35.227915 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 00:18:35.296471 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 00:18:35.318197 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 00:18:35.343552 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 00:18:35.456169 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 00:18:35.528194 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 00:18:35.601808 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 00:18:35.675017 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 00:18:35.749071 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 00:18:35.822152 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 00:18:35.899197 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 00:18:35.970845 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 00:18:36.044540 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 00:18:36.117329 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 00:18:36.191107 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 00:18:36.265124 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 00:18:36.339212 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 00:18:36.412436 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 00:18:36.485238 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 00:18:36.560104 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 00:18:36.635523 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 00:18:36.713830 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 00:18:36.779845 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 00:18:36.854706 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 00:18:36.927922 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 00:18:37.002334 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 00:18:37.077634 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 00:18:37.149725 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 00:18:37.223591 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 00:18:37.297898 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 00:18:37.372255 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 00:18:37.446267 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 00:18:37.520288 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 00:18:37.594072 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 00:18:37.672950 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 00:18:37.743503 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 00:18:37.819293 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 00:18:37.890738 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 00:18:37.965967 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 00:18:38.040183 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 00:18:38.113644 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 00:18:38.189683 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 00:18:38.261478 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 00:18:38.335493 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 00:18:38.409997 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 00:18:38.483772 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 00:18:38.560138 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 00:18:38.630786 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 00:18:38.705977 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 00:18:38.782106 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 00:18:38.864934 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 00:18:38.932493 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 00:18:39.009985 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 00:18:39.082971 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 00:18:39.158600 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 00:18:39.241457 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 00:18:39.327970 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 00:18:39.402173 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 00:18:39.482561 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 00:18:39.552123 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 00:18:39.628263 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 00:18:39.700610 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 00:18:39.775169 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 00:18:39.849701 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 00:18:39.923294 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 00:18:39.997272 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 00:18:40.070665 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 00:18:40.144854 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 00:18:40.221295 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 00:18:40.295091 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 00:18:40.373435 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 00:18:40.446126 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 00:18:40.520925 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 00:18:40.590810 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 00:18:40.664939 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 00:18:40.738841 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 00:18:40.812371 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 00:18:40.894111 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 00:18:40.964167 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 00:18:41.037182 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 00:18:41.111590 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 00:18:41.185774 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 00:18:41.260689 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 00:18:41.284141 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 00:18:41.307345 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 00:18:41.332429 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 00:18:41.360767 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 00:18:41.384590 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 00:18:41.410786 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 00:18:41.434756 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 00:18:41.459740 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 00:18:41.565531 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 00:18:41.593556 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 00:18:41.615737 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 00:18:41.638353 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 00:18:41.746542 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 00:18:41.823920 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 00:18:41.898580 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 00:18:41.971397 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 00:18:42.046315 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 00:18:42.120720 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 00:18:42.193873 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 00:18:42.276233 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 00:18:42.343719 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 00:18:42.421235 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 00:18:42.750827 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 00:18:42.751650 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 00:18:42.752761 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 00:18:42.754272 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 00:18:42.794282 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 00:18:42.871110 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 00:18:42.891922 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 00:18:42.964596 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 00:18:43.040633 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 00:18:43.114936 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 00:18:43.138811 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 00:18:43.212194 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 00:18:43.233568 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 00:18:43.304077 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 00:18:43.331702 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 00:18:43.354117 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 00:18:43.375781 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 00:18:43.400325 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 00:18:43.428760 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 00:18:43.449265 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 00:18:43.476897 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 00:18:43.556541 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 00:18:43.576209 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 00:18:43.600307 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 00:18:43.674217 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 00:18:43.747307 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 00:18:43.769065 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 00:18:43.876771 # not ok 144 /ocp/interconnect@47c00000
1218 00:18:43.951106 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 00:18:43.968130 # ok 146 /ocp/interconnect@48000000
1220 00:18:43.996397 # ok 147 /ocp/interconnect@48000000/segment@0
1221 00:18:44.021986 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 00:18:44.043470 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 00:18:44.065101 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 00:18:44.088535 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 00:18:44.113253 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 00:18:44.137024 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 00:18:44.161006 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 00:18:44.237912 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 00:18:44.308726 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 00:18:44.330958 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 00:18:44.356302 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 00:18:44.379026 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 00:18:44.407082 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 00:18:44.427350 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 00:18:44.451951 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 00:18:44.475282 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 00:18:44.499662 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 00:18:44.522568 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 00:18:44.552010 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 00:18:44.573178 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 00:18:44.595586 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 00:18:44.618600 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 00:18:44.643106 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 00:18:44.670748 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 00:18:44.694169 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 00:18:44.714972 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 00:18:44.740105 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 00:18:44.761116 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 00:18:44.791163 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 00:18:44.814063 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 00:18:44.891372 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 00:18:44.967232 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 00:18:45.034925 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 00:18:45.111016 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 00:18:45.181444 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 00:18:45.263774 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 00:18:45.335807 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 00:18:45.416083 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 00:18:45.429494 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 00:18:45.458023 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 00:18:45.478168 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 00:18:45.502243 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 00:18:45.531014 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 00:18:45.554288 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 00:18:45.582715 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 00:18:45.604059 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 00:18:45.629882 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 00:18:45.653377 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 00:18:45.675928 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 00:18:45.698605 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 00:18:45.719542 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 00:18:45.749363 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 00:18:45.824255 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 00:18:45.841259 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 00:18:45.866436 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 00:18:45.890596 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 00:18:45.915732 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 00:18:45.943442 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 00:18:45.964550 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 00:18:45.987602 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 00:18:46.061912 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 00:18:46.080945 # ok 209 /ocp/interconnect@4a000000
1283 00:18:46.109183 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 00:18:46.133289 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 00:18:46.156102 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 00:18:46.181309 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 00:18:46.204388 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 00:18:46.283106 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 00:18:46.387173 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 00:18:46.465666 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 00:18:46.572064 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 00:18:46.645222 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 00:18:46.713808 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 00:18:46.816244 # not ok 221 /ocp/interconnect@4b140000
1295 00:18:46.888846 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 00:18:46.963573 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 00:18:46.989435 # ok 224 /ocp/target-module@40300000
1298 00:18:47.011142 # ok 225 /ocp/target-module@40300000/sram@0
1299 00:18:47.088459 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 00:18:47.163293 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 00:18:47.180103 # ok 228 /ocp/target-module@47400000
1302 00:18:47.205073 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 00:18:47.229231 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 00:18:47.252554 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 00:18:47.279603 # ok 232 /ocp/target-module@47400000/usb@1400
1306 00:18:47.301277 # ok 233 /ocp/target-module@47400000/usb@1800
1307 00:18:47.324931 # ok 234 /ocp/target-module@47810000
1308 00:18:47.348310 # ok 235 /ocp/target-module@49000000
1309 00:18:47.371251 # ok 236 /ocp/target-module@49000000/dma@0
1310 00:18:47.390051 # ok 237 /ocp/target-module@49800000
1311 00:18:47.418055 # ok 238 /ocp/target-module@49800000/dma@0
1312 00:18:47.435934 # ok 239 /ocp/target-module@49900000
1313 00:18:47.461076 # ok 240 /ocp/target-module@49900000/dma@0
1314 00:18:47.486416 # ok 241 /ocp/target-module@49a00000
1315 00:18:47.505665 # ok 242 /ocp/target-module@49a00000/dma@0
1316 00:18:47.530608 # ok 243 /ocp/target-module@4c000000
1317 00:18:47.606248 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 00:18:47.627685 # ok 245 /ocp/target-module@50000000
1319 00:18:47.649745 # ok 246 /ocp/target-module@53100000
1320 00:18:47.728451 # not ok 247 /ocp/target-module@53100000/sham@0
1321 00:18:47.744370 # ok 248 /ocp/target-module@53500000
1322 00:18:47.821404 # not ok 249 /ocp/target-module@53500000/aes@0
1323 00:18:47.839520 # ok 250 /ocp/target-module@56000000
1324 00:18:47.947467 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 00:18:48.019809 # ok 252 /opp-table # SKIP
1326 00:18:48.090601 # ok 253 /soc # SKIP
1327 00:18:48.116635 # ok 254 /sound
1328 00:18:48.135332 # ok 255 /target-module@4b000000
1329 00:18:48.160602 # ok 256 /target-module@4b000000/target-module@140000
1330 00:18:48.183218 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 00:18:48.191491 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 00:18:48.200077 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 00:18:50.364995 dt_test_unprobed_devices_sh_ skip
1334 00:18:50.370549 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 00:18:50.376197 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 00:18:50.376677 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 00:18:50.385012 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 00:18:50.385475 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 00:18:50.390584 dt_test_unprobed_devices_sh_leds pass
1340 00:18:50.396217 dt_test_unprobed_devices_sh_ocp pass
1341 00:18:50.399723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 00:18:50.405198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 00:18:50.410727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 00:18:50.419926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 00:18:50.425703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 00:18:50.436787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 00:18:50.442339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 00:18:50.453684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 00:18:50.459373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 00:18:50.470375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 00:18:50.481689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 00:18:50.492802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 00:18:50.498469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 00:18:50.509707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 00:18:50.520874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 00:18:50.532108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 00:18:50.543243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 00:18:50.548900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 00:18:50.560052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 00:18:50.571256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 00:18:50.582449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 00:18:50.588076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 00:18:50.599241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 00:18:50.610452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 00:18:50.621621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 00:18:50.627232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 00:18:50.638359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 00:18:50.649662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 00:18:50.660795 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 00:18:50.672047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 00:18:50.683246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 00:18:50.688854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 00:18:50.700024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 00:18:50.711140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 00:18:50.722373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 00:18:50.733632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 00:18:50.744775 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 00:18:50.755948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 00:18:50.767444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 00:18:50.778232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 00:18:50.789509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 00:18:50.800743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 00:18:50.811885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 00:18:50.823099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 00:18:50.834265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 00:18:50.845444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 00:18:50.856788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 00:18:50.867851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 00:18:50.879037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 00:18:50.890229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 00:18:50.901433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 00:18:50.912657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 00:18:50.923837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 00:18:50.934986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 00:18:50.946217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 00:18:50.957393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 00:18:50.968658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 00:18:50.974206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 00:18:50.990970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 00:18:50.996649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 00:18:51.007947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 00:18:51.019115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 00:18:51.030266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 00:18:51.041407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 00:18:51.052636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 00:18:51.063823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 00:18:51.074983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 00:18:51.086194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 00:18:51.097374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 00:18:51.108580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 00:18:51.119852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 00:18:51.130977 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 00:18:51.142164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 00:18:51.153335 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 00:18:51.164579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 00:18:51.170186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 00:18:51.181318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 00:18:51.192533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 00:18:51.203686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 00:18:51.214894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 00:18:51.226089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 00:18:51.237297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 00:18:51.248484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 00:18:51.259699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 00:18:51.270882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 00:18:51.282045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 00:18:51.293253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 00:18:51.298895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 00:18:51.310050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 00:18:51.321225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 00:18:51.326872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 00:18:51.338003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 00:18:51.349226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 00:18:51.354918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 00:18:51.365989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 00:18:51.371651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 00:18:51.382887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 00:18:51.393962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 00:18:51.405205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 00:18:51.416351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 00:18:51.427593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 00:18:51.438825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 00:18:51.449931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 00:18:51.461204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 00:18:51.472277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 00:18:51.489024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 00:18:51.500239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 00:18:51.511450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 00:18:51.522671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 00:18:51.533845 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 00:18:51.545039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 00:18:51.561812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 00:18:51.572999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 00:18:51.584201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 00:18:51.595370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 00:18:51.606542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 00:18:51.617824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 00:18:51.623408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 00:18:51.634582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 00:18:51.640190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 00:18:51.651398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 00:18:51.656978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 00:18:51.668155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 00:18:51.673829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 00:18:51.684961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 00:18:51.690598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 00:18:51.701825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 00:18:51.713081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 00:18:51.718807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 00:18:51.729838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 00:18:51.741037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 00:18:51.752303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 00:18:51.763585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 00:18:51.774839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 00:18:51.780356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 00:18:51.785968 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 00:18:51.791543 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 00:18:51.797206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 00:18:51.802721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 00:18:51.808363 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 00:18:51.819595 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 00:18:51.825144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 00:18:51.836404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 00:18:51.842034 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 00:18:51.853156 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 00:18:51.858766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 00:18:51.864437 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 00:18:51.875483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 00:18:51.881074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 00:18:51.892220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 00:18:51.897907 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 00:18:51.909048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 00:18:51.914626 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 00:18:51.925756 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 00:18:51.931390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 00:18:51.942550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 00:18:51.948166 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 00:18:51.959341 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 00:18:51.964939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 00:18:51.976234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 00:18:51.981916 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 00:18:51.987348 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 00:18:51.998405 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 00:18:52.004061 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 00:18:52.015224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 00:18:52.020827 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 00:18:52.032060 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 00:18:52.037703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 00:18:52.048827 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 00:18:52.054410 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 00:18:52.071224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 00:18:52.076863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 00:18:52.088061 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 00:18:52.099243 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 00:18:52.110378 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 00:18:52.121697 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 00:18:52.132949 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 00:18:52.144088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 00:18:52.149668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 00:18:52.160932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 00:18:52.166460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 00:18:52.178025 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 00:18:52.183219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 00:18:52.194528 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 00:18:52.200075 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 00:18:52.211241 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 00:18:52.216823 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 00:18:52.228036 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 00:18:52.233605 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 00:18:52.239208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 00:18:52.250402 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 00:18:52.256050 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 00:18:52.261586 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 00:18:52.272839 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 00:18:52.278427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 00:18:52.289591 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 00:18:52.295196 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 00:18:52.306391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 00:18:52.312023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 00:18:52.323181 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 00:18:52.328746 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 00:18:52.334320 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 00:18:52.339934 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 00:18:52.351117 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 00:18:52.362304 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 00:18:52.367957 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 00:18:52.379128 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 00:18:52.384768 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 00:18:52.396079 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 00:18:52.407111 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 00:18:52.418355 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 00:18:52.423948 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 00:18:52.429579 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 00:18:52.440879 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 00:18:52.446426 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 00:18:52.452061 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 00:18:52.457616 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 00:18:52.463296 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 00:18:52.468864 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 00:18:52.474427 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 00:18:52.480121 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 00:18:52.491273 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 00:18:52.496837 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 00:18:52.502487 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 00:18:52.508131 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 00:18:52.513773 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 00:18:52.519343 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 00:18:52.525030 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 00:18:52.530540 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 00:18:52.536165 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 00:18:52.541725 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 00:18:52.547401 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 00:18:52.553006 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 00:18:52.558561 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 00:18:52.564240 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 00:18:52.569830 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 00:18:52.575365 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 00:18:52.581003 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 00:18:52.586553 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 00:18:52.592246 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 00:18:52.597810 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 00:18:52.603355 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 00:18:52.609041 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 00:18:52.614561 dt_test_unprobed_devices_sh_opp-table skip
1585 00:18:52.615091 dt_test_unprobed_devices_sh_soc skip
1586 00:18:52.620288 dt_test_unprobed_devices_sh_sound pass
1587 00:18:52.625760 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 00:18:52.631394 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 00:18:52.637047 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 00:18:52.642491 dt_test_unprobed_devices_sh fail
1591 00:18:52.648113 + ../../utils/send-to-lava.sh ./output/result.txt
1592 00:18:52.649117 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1594 00:18:52.653808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 00:18:52.658170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 00:18:52.658974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 00:18:52.747835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 00:18:52.748859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 00:18:52.843646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 00:18:52.844627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 00:18:52.940435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 00:18:52.941310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 00:18:53.035658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 00:18:53.036662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 00:18:53.123391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 00:18:53.124371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 00:18:53.217049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 00:18:53.218047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 00:18:53.314442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 00:18:53.315357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 00:18:53.410999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 00:18:53.411905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 00:18:53.507659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 00:18:53.508582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 00:18:53.601703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 00:18:53.602776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 00:18:53.696829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 00:18:53.697762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 00:18:53.786432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 00:18:53.787348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 00:18:53.872635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 00:18:53.873549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 00:18:53.969147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 00:18:53.969985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 00:18:54.056264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 00:18:54.057095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 00:18:54.145706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 00:18:54.146564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 00:18:54.240081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 00:18:54.241089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 00:18:54.329337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 00:18:54.330279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 00:18:54.418183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 00:18:54.419076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 00:18:54.511968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 00:18:54.513016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 00:18:54.600404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 00:18:54.601401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 00:18:54.688898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 00:18:54.689906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 00:18:54.785879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 00:18:54.786794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 00:18:54.881190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 00:18:54.882115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 00:18:54.968978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 00:18:54.969879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 00:18:55.065034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 00:18:55.065974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 00:18:55.155507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 00:18:55.156437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 00:18:55.250331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 00:18:55.251191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 00:18:55.346801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 00:18:55.347792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 00:18:55.468026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 00:18:55.468940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 00:18:55.564259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 00:18:55.565186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 00:18:55.653785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 00:18:55.654682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 00:18:55.742587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 00:18:55.743496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 00:18:55.839100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 00:18:55.840031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 00:18:55.927574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 00:18:55.928501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 00:18:56.023023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 00:18:56.023921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 00:18:56.112109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 00:18:56.113018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 00:18:56.207739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 00:18:56.208671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 00:18:56.297173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 00:18:56.298055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 00:18:56.393331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 00:18:56.394210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 00:18:56.488569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 00:18:56.489414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 00:18:56.583782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 00:18:56.584630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 00:18:56.678973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 00:18:56.679809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 00:18:56.776870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 00:18:56.777753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 00:18:56.868839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 00:18:56.869705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 00:18:56.956364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 00:18:56.957271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 00:18:57.050356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 00:18:57.051283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 00:18:57.145872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 00:18:57.146771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 00:18:57.239606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 00:18:57.240560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 00:18:57.330328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 00:18:57.331283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 00:18:57.418686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 00:18:57.419604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 00:18:57.515046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 00:18:57.515960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 00:18:57.605333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 00:18:57.606304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 00:18:57.699909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 00:18:57.700901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 00:18:57.789188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 00:18:57.790129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 00:18:57.880586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 00:18:57.881504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 00:18:57.975156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 00:18:57.976170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 00:18:58.069629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 00:18:58.070554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 00:18:58.158323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 00:18:58.159233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 00:18:58.247467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 00:18:58.248437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 00:18:58.342688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 00:18:58.343585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 00:18:58.436930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 00:18:58.437810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 00:18:58.533107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 00:18:58.533998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 00:18:58.625765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 00:18:58.626611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 00:18:58.721037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 00:18:58.721926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 00:18:58.810936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 00:18:58.811799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 00:18:58.900251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 00:18:58.901132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 00:18:58.996407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 00:18:58.997224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 00:18:59.090962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 00:18:59.091821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 00:18:59.179498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 00:18:59.180352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 00:18:59.267749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 00:18:59.268653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 00:18:59.364146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 00:18:59.364984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 00:18:59.457268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 00:18:59.458113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 00:18:59.551494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 00:18:59.552375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 00:18:59.640586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 00:18:59.641448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 00:18:59.728932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 00:18:59.729792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 00:18:59.822294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 00:18:59.823155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 00:18:59.912440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 00:18:59.913265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 00:19:00.007089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 00:19:00.007936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 00:19:00.096516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 00:19:00.097307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 00:19:00.185105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 00:19:00.185967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 00:19:00.278103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 00:19:00.278958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 00:19:00.367235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 00:19:00.368081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 00:19:00.468487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 00:19:00.469417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 00:19:00.564647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 00:19:00.565500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 00:19:00.652506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 00:19:00.653332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 00:19:00.741095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 00:19:00.742050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 00:19:00.843556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 00:19:00.844514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 00:19:00.942600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 00:19:00.943252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 00:19:01.039370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 00:19:01.040065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 00:19:01.140499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 00:19:01.141149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 00:19:01.249551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 00:19:01.250219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 00:19:01.358168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 00:19:01.359036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 00:19:01.467315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 00:19:01.468206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 00:19:01.578884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 00:19:01.579799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 00:19:01.701874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 00:19:01.702755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 00:19:01.794624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 00:19:01.795414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 00:19:01.884550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 00:19:01.885481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 00:19:01.979199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 00:19:01.980105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 00:19:02.075743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 00:19:02.076677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 00:19:02.169488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 00:19:02.170351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 00:19:02.265617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 00:19:02.266426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 00:19:02.356584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 00:19:02.357441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 00:19:02.452034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 00:19:02.454263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 00:19:02.547344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 00:19:02.548222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 00:19:02.643289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 00:19:02.644154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 00:19:02.741010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 00:19:02.741668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 00:19:02.835284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 00:19:02.835934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 00:19:02.931265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 00:19:02.932062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 00:19:03.027610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 00:19:03.028322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 00:19:03.123081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 00:19:03.123669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 00:19:03.219776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 00:19:03.220455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 00:19:03.314516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 00:19:03.315114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 00:19:03.410654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 00:19:03.411260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 00:19:03.507280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 00:19:03.507883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 00:19:03.602133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 00:19:03.602730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 00:19:03.698271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 00:19:03.698869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 00:19:03.792681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 00:19:03.793302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 00:19:03.886825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 00:19:03.889983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 00:19:03.977276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 00:19:03.980353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 00:19:04.067418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 00:19:04.070587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 00:19:04.165649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 00:19:04.166254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 00:19:04.255022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 00:19:04.255638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 00:19:04.347968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 00:19:04.348580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 00:19:04.445100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 00:19:04.445695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 00:19:04.539805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 00:19:04.540430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 00:19:04.634887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 00:19:04.635489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 00:19:04.723515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 00:19:04.724129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 00:19:04.813904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 00:19:04.814498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 00:19:04.908870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 00:19:04.909502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 00:19:05.004877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 00:19:05.005523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 00:19:05.094104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 00:19:05.094739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 00:19:05.190297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 00:19:05.190917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 00:19:05.285938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 00:19:05.286548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 00:19:05.384696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 00:19:05.385298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 00:19:05.476352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 00:19:05.476944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 00:19:05.572281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 00:19:05.572896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 00:19:05.667214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 00:19:05.667833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 00:19:05.763437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 00:19:05.764002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 00:19:05.857640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 00:19:05.858494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 00:19:05.947977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 00:19:05.948886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 00:19:06.035072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 00:19:06.036095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 00:19:06.128056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 00:19:06.128910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 00:19:06.221228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 00:19:06.221897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 00:19:06.315126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 00:19:06.316052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 00:19:06.405155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 00:19:06.406003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 00:19:06.501773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 00:19:06.502512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 00:19:06.590283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 00:19:06.591076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 00:19:06.684821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 00:19:06.686287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 00:19:06.774390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 00:19:06.775322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 00:19:06.863410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 00:19:06.864351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 00:19:06.958290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 00:19:06.959322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 00:19:07.045228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 00:19:07.046341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 00:19:07.136108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 00:19:07.137023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 00:19:07.232938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 00:19:07.233892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 00:19:07.320998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 00:19:07.321931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 00:19:07.417357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 00:19:07.418311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 00:19:07.512512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 00:19:07.513438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 00:19:07.609564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 00:19:07.610482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 00:19:07.704123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 00:19:07.705133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 00:19:07.792861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 00:19:07.793784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 00:19:07.880842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 00:19:07.881748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 00:19:07.979475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 00:19:07.980478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 00:19:08.073897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 00:19:08.074774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 00:19:08.162994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 00:19:08.163864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 00:19:08.250951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 00:19:08.251787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 00:19:08.345829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 00:19:08.346720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 00:19:08.433745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 00:19:08.434641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 00:19:08.521999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 00:19:08.522914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 00:19:08.610005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 00:19:08.610875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 00:19:08.704068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 00:19:08.704946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 00:19:08.792932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 00:19:08.793804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 00:19:08.886555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 00:19:08.887492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 00:19:08.972158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 00:19:08.973083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 00:19:09.061703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 00:19:09.062571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 00:19:09.155534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 00:19:09.156344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 00:19:09.245529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 00:19:09.246297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 00:19:09.334889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 00:19:09.335693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 00:19:09.426009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 00:19:09.426752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 00:19:09.518031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 00:19:09.518826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 00:19:09.605297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 00:19:09.605972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 00:19:09.700293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 00:19:09.700936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 00:19:09.793886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 00:19:09.794551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 00:19:09.888969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 00:19:09.889987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 00:19:09.981503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 00:19:09.982417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 00:19:10.076835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 00:19:10.077699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 00:19:10.171422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 00:19:10.172119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 00:19:10.267439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 00:19:10.268064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 00:19:10.357023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 00:19:10.357663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 00:19:10.454700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 00:19:10.455598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 00:19:10.544285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 00:19:10.545119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 00:19:10.640214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 00:19:10.641052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 00:19:10.729469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 00:19:10.730385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 00:19:10.825797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 00:19:10.826711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 00:19:10.924193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 00:19:10.925116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 00:19:11.016474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 00:19:11.017282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 00:19:11.104210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 00:19:11.105022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 00:19:11.200050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 00:19:11.200930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 00:19:11.289390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 00:19:11.290263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 00:19:11.382676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 00:19:11.383626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 00:19:11.474203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 00:19:11.475073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 00:19:11.570466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 00:19:11.571401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 00:19:11.677177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 00:19:11.678142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 00:19:11.765991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 00:19:11.766888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 00:19:11.857227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 00:19:11.858081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 00:19:11.950865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 00:19:11.951839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 00:19:12.040654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 00:19:12.041504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 00:19:12.131060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 00:19:12.131962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 00:19:12.221254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 00:19:12.222095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 00:19:12.329962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 00:19:12.330854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 00:19:12.428118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 00:19:12.428983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 00:19:12.523844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 00:19:12.524675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 00:19:12.611409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 00:19:12.612315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 00:19:12.705720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 00:19:12.706291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 00:19:12.796295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 00:19:12.796899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 00:19:12.894246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 00:19:12.894817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 00:19:12.980919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 00:19:12.981493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 00:19:13.068382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 00:19:13.068939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 00:19:13.157670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 00:19:13.158233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 00:19:13.247297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 00:19:13.247852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 00:19:13.338784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 00:19:13.339344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 00:19:13.431552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 00:19:13.432109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 00:19:13.524512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 00:19:13.525076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 00:19:13.619663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 00:19:13.620252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 00:19:13.714231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 00:19:13.714817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 00:19:13.810807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 00:19:13.817011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 00:19:13.903249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 00:19:13.903884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 00:19:14.015726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 00:19:14.016386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 00:19:14.117144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 00:19:14.117760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 00:19:14.223529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 00:19:14.224157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 00:19:14.317647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 00:19:14.318259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 00:19:14.406974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 00:19:14.407540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 00:19:14.499221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 00:19:14.499767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 00:19:14.587010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 00:19:14.587547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 00:19:14.675741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 00:19:14.676296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 00:19:14.763593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 00:19:14.764185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 00:19:14.858147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 00:19:14.858718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 00:19:14.946153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 00:19:14.946689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 00:19:15.040571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 00:19:15.041111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 00:19:15.127454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 00:19:15.128022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 00:19:15.214178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 00:19:15.214738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 00:19:15.301548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 00:19:15.302095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 00:19:15.397449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 00:19:15.397984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 00:19:15.485577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 00:19:15.486443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 00:19:15.580419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 00:19:15.581011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 00:19:15.670112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 00:19:15.670913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 00:19:15.757884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 00:19:15.758629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 00:19:15.852567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 00:19:15.853361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 00:19:15.941219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 00:19:15.942122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 00:19:16.039750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 00:19:16.040619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 00:19:16.131292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 00:19:16.132101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 00:19:16.224519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 00:19:16.225340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 00:19:16.312839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 00:19:16.313583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 00:19:16.409175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 00:19:16.410080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 00:19:16.500564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 00:19:16.501376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 00:19:16.590205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 00:19:16.590990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 00:19:16.682814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 00:19:16.683339 + set +x
2368 00:19:16.684044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 00:19:16.687104 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 915354_1.6.2.4.5>
2371 00:19:16.687812 Received signal: <ENDRUN> 1_kselftest-dt 915354_1.6.2.4.5
2372 00:19:16.688309 Ending use of test pattern.
2373 00:19:16.688735 Ending test lava.1_kselftest-dt (915354_1.6.2.4.5), duration 83.11
2375 00:19:16.693797 <LAVA_TEST_RUNNER EXIT>
2376 00:19:16.694497 ok: lava_test_shell seems to have completed
2377 00:19:16.707284 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 00:19:16.709188 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2379 00:19:16.709792 end: 3 lava-test-retry (duration 00:01:25) [common]
2380 00:19:16.710397 start: 4 finalize (timeout 00:05:29) [common]
2381 00:19:16.710994 start: 4.1 power-off (timeout 00:00:30) [common]
2382 00:19:16.712071 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2383 00:19:16.747457 >> OK - accepted request
2384 00:19:16.749563 Returned 0 in 0 seconds
2385 00:19:16.850727 end: 4.1 power-off (duration 00:00:00) [common]
2387 00:19:16.852509 start: 4.2 read-feedback (timeout 00:05:29) [common]
2388 00:19:16.853691 Listened to connection for namespace 'common' for up to 1s
2389 00:19:16.854816 Listened to connection for namespace 'common' for up to 1s
2390 00:19:17.853613 Finalising connection for namespace 'common'
2391 00:19:17.854315 Disconnecting from shell: Finalise
2392 00:19:17.854834 / #
2393 00:19:17.955792 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 00:19:17.956518 end: 4 finalize (duration 00:00:01) [common]
2395 00:19:17.957186 Cleaning after the job
2396 00:19:17.957838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/ramdisk
2397 00:19:17.960303 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/kernel
2398 00:19:17.962150 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/dtb
2399 00:19:17.963389 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/nfsrootfs
2400 00:19:18.011714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915354/tftp-deploy-5s3mhpbf/modules
2401 00:19:18.013787 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915354
2402 00:19:20.916350 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915354
2403 00:19:20.916917 Job finished correctly