Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 27
- Errors: 0
- Boot result: PASS
- Kernel Errors: 59
1 01:29:28.278647 lava-dispatcher, installed at version: 2024.01
2 01:29:28.279479 start: 0 validate
3 01:29:28.279972 Start time: 2024-10-31 01:29:28.279943+00:00 (UTC)
4 01:29:28.280550 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:29:28.281105 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 01:29:28.323628 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:29:28.324208 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 01:29:28.355559 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:29:28.356235 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 01:29:28.388152 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:29:28.388645 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 01:29:28.420826 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:29:28.421316 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:29:28.457332 validate duration: 0.18
16 01:29:28.458248 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:29:28.458590 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:29:28.458892 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:29:28.459457 Not decompressing ramdisk as can be used compressed.
20 01:29:28.459881 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 01:29:28.460171 saving as /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/ramdisk/initrd.cpio.gz
22 01:29:28.460439 total size: 4775763 (4 MB)
23 01:29:28.497056 progress 0 % (0 MB)
24 01:29:28.501019 progress 5 % (0 MB)
25 01:29:28.504657 progress 10 % (0 MB)
26 01:29:28.508160 progress 15 % (0 MB)
27 01:29:28.513678 progress 20 % (0 MB)
28 01:29:28.516971 progress 25 % (1 MB)
29 01:29:28.520261 progress 30 % (1 MB)
30 01:29:28.523858 progress 35 % (1 MB)
31 01:29:28.527184 progress 40 % (1 MB)
32 01:29:28.530417 progress 45 % (2 MB)
33 01:29:28.533816 progress 50 % (2 MB)
34 01:29:28.537460 progress 55 % (2 MB)
35 01:29:28.540737 progress 60 % (2 MB)
36 01:29:28.543940 progress 65 % (2 MB)
37 01:29:28.547568 progress 70 % (3 MB)
38 01:29:28.550758 progress 75 % (3 MB)
39 01:29:28.553963 progress 80 % (3 MB)
40 01:29:28.557220 progress 85 % (3 MB)
41 01:29:28.560827 progress 90 % (4 MB)
42 01:29:28.563951 progress 95 % (4 MB)
43 01:29:28.566876 progress 100 % (4 MB)
44 01:29:28.567530 4 MB downloaded in 0.11 s (42.54 MB/s)
45 01:29:28.568074 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:29:28.568967 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:29:28.569260 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:29:28.569526 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:29:28.569984 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 01:29:28.570229 saving as /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/kernel/zImage
52 01:29:28.570436 total size: 11440640 (10 MB)
53 01:29:28.570647 No compression specified
54 01:29:28.608912 progress 0 % (0 MB)
55 01:29:28.617129 progress 5 % (0 MB)
56 01:29:28.624288 progress 10 % (1 MB)
57 01:29:28.631845 progress 15 % (1 MB)
58 01:29:28.639608 progress 20 % (2 MB)
59 01:29:28.647647 progress 25 % (2 MB)
60 01:29:28.655234 progress 30 % (3 MB)
61 01:29:28.662750 progress 35 % (3 MB)
62 01:29:28.670429 progress 40 % (4 MB)
63 01:29:28.678681 progress 45 % (4 MB)
64 01:29:28.685806 progress 50 % (5 MB)
65 01:29:28.693360 progress 55 % (6 MB)
66 01:29:28.700455 progress 60 % (6 MB)
67 01:29:28.707539 progress 65 % (7 MB)
68 01:29:28.715059 progress 70 % (7 MB)
69 01:29:28.722161 progress 75 % (8 MB)
70 01:29:28.729653 progress 80 % (8 MB)
71 01:29:28.736769 progress 85 % (9 MB)
72 01:29:28.744242 progress 90 % (9 MB)
73 01:29:28.751358 progress 95 % (10 MB)
74 01:29:28.758540 progress 100 % (10 MB)
75 01:29:28.759057 10 MB downloaded in 0.19 s (57.85 MB/s)
76 01:29:28.759524 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:29:28.760361 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:29:28.760637 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:29:28.760900 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:29:28.761357 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 01:29:28.761623 saving as /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/dtb/am335x-boneblack.dtb
83 01:29:28.761828 total size: 70568 (0 MB)
84 01:29:28.762035 No compression specified
85 01:29:28.799122 progress 46 % (0 MB)
86 01:29:28.799961 progress 92 % (0 MB)
87 01:29:28.800704 progress 100 % (0 MB)
88 01:29:28.801123 0 MB downloaded in 0.04 s (1.71 MB/s)
89 01:29:28.801605 end: 1.3.1 http-download (duration 00:00:00) [common]
91 01:29:28.802436 end: 1.3 download-retry (duration 00:00:00) [common]
92 01:29:28.802711 start: 1.4 download-retry (timeout 00:10:00) [common]
93 01:29:28.802979 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 01:29:28.803441 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 01:29:28.803689 saving as /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/nfsrootfs/full.rootfs.tar
96 01:29:28.803900 total size: 117747780 (112 MB)
97 01:29:28.804149 Using unxz to decompress xz
98 01:29:28.840666 progress 0 % (0 MB)
99 01:29:29.560521 progress 5 % (5 MB)
100 01:29:30.298921 progress 10 % (11 MB)
101 01:29:31.067487 progress 15 % (16 MB)
102 01:29:31.779556 progress 20 % (22 MB)
103 01:29:32.360016 progress 25 % (28 MB)
104 01:29:33.162508 progress 30 % (33 MB)
105 01:29:33.962070 progress 35 % (39 MB)
106 01:29:34.290899 progress 40 % (44 MB)
107 01:29:34.637039 progress 45 % (50 MB)
108 01:29:35.287540 progress 50 % (56 MB)
109 01:29:36.091786 progress 55 % (61 MB)
110 01:29:36.812647 progress 60 % (67 MB)
111 01:29:37.518512 progress 65 % (73 MB)
112 01:29:38.273327 progress 70 % (78 MB)
113 01:29:39.022566 progress 75 % (84 MB)
114 01:29:39.746707 progress 80 % (89 MB)
115 01:29:40.444903 progress 85 % (95 MB)
116 01:29:41.228164 progress 90 % (101 MB)
117 01:29:41.988989 progress 95 % (106 MB)
118 01:29:42.798235 progress 100 % (112 MB)
119 01:29:42.810500 112 MB downloaded in 14.01 s (8.02 MB/s)
120 01:29:42.811276 end: 1.4.1 http-download (duration 00:00:14) [common]
122 01:29:42.813179 end: 1.4 download-retry (duration 00:00:14) [common]
123 01:29:42.813763 start: 1.5 download-retry (timeout 00:09:46) [common]
124 01:29:42.814337 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 01:29:42.815324 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 01:29:42.815853 saving as /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/modules/modules.tar
127 01:29:42.816362 total size: 6606040 (6 MB)
128 01:29:42.816834 Using unxz to decompress xz
129 01:29:42.859412 progress 0 % (0 MB)
130 01:29:42.894850 progress 5 % (0 MB)
131 01:29:42.937698 progress 10 % (0 MB)
132 01:29:42.980736 progress 15 % (0 MB)
133 01:29:43.024391 progress 20 % (1 MB)
134 01:29:43.066568 progress 25 % (1 MB)
135 01:29:43.109008 progress 30 % (1 MB)
136 01:29:43.152327 progress 35 % (2 MB)
137 01:29:43.197540 progress 40 % (2 MB)
138 01:29:43.241812 progress 45 % (2 MB)
139 01:29:43.284468 progress 50 % (3 MB)
140 01:29:43.326783 progress 55 % (3 MB)
141 01:29:43.369566 progress 60 % (3 MB)
142 01:29:43.415837 progress 65 % (4 MB)
143 01:29:43.458885 progress 70 % (4 MB)
144 01:29:43.503281 progress 75 % (4 MB)
145 01:29:43.549442 progress 80 % (5 MB)
146 01:29:43.592874 progress 85 % (5 MB)
147 01:29:43.636434 progress 90 % (5 MB)
148 01:29:43.682795 progress 95 % (6 MB)
149 01:29:43.725388 progress 100 % (6 MB)
150 01:29:43.738013 6 MB downloaded in 0.92 s (6.84 MB/s)
151 01:29:43.738602 end: 1.5.1 http-download (duration 00:00:01) [common]
153 01:29:43.739437 end: 1.5 download-retry (duration 00:00:01) [common]
154 01:29:43.739708 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 01:29:43.739973 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 01:29:59.994068 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg
157 01:29:59.994674 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 01:29:59.994956 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 01:29:59.995654 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu
160 01:29:59.996142 makedir: /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin
161 01:29:59.996485 makedir: /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/tests
162 01:29:59.996798 makedir: /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/results
163 01:29:59.997133 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-add-keys
164 01:29:59.997674 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-add-sources
165 01:29:59.998199 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-background-process-start
166 01:29:59.998712 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-background-process-stop
167 01:29:59.999251 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-common-functions
168 01:29:59.999864 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-echo-ipv4
169 01:30:00.000475 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-install-packages
170 01:30:00.001010 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-installed-packages
171 01:30:00.001502 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-os-build
172 01:30:00.001986 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-probe-channel
173 01:30:00.002467 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-probe-ip
174 01:30:00.002948 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-target-ip
175 01:30:00.003429 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-target-mac
176 01:30:00.003937 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-target-storage
177 01:30:00.004492 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-case
178 01:30:00.004989 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-event
179 01:30:00.005478 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-feedback
180 01:30:00.005994 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-raise
181 01:30:00.006517 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-reference
182 01:30:00.007013 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-runner
183 01:30:00.007514 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-set
184 01:30:00.008027 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-test-shell
185 01:30:00.008648 Updating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-add-keys (debian)
186 01:30:00.009217 Updating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-add-sources (debian)
187 01:30:00.009732 Updating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-install-packages (debian)
188 01:30:00.010243 Updating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-installed-packages (debian)
189 01:30:00.010746 Updating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/bin/lava-os-build (debian)
190 01:30:00.011192 Creating /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/environment
191 01:30:00.011570 LAVA metadata
192 01:30:00.011835 - LAVA_JOB_ID=915610
193 01:30:00.012078 - LAVA_DISPATCHER_IP=192.168.6.2
194 01:30:00.012463 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 01:30:00.013449 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 01:30:00.013776 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 01:30:00.013981 skipped lava-vland-overlay
198 01:30:00.014219 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 01:30:00.014473 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 01:30:00.014692 skipped lava-multinode-overlay
201 01:30:00.014931 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 01:30:00.015177 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 01:30:00.015422 Loading test definitions
204 01:30:00.015695 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 01:30:00.015912 Using /lava-915610 at stage 0
206 01:30:00.017048 uuid=915610_1.6.2.4.1 testdef=None
207 01:30:00.017363 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 01:30:00.017622 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 01:30:00.019206 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 01:30:00.020037 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 01:30:00.021994 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 01:30:00.022815 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 01:30:00.024776 runner path: /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/0/tests/0_timesync-off test_uuid 915610_1.6.2.4.1
216 01:30:00.025356 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 01:30:00.026166 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 01:30:00.026389 Using /lava-915610 at stage 0
220 01:30:00.026742 Fetching tests from https://github.com/kernelci/test-definitions.git
221 01:30:00.027034 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/0/tests/1_kselftest-dt'
222 01:30:03.458416 Running '/usr/bin/git checkout kernelci.org
223 01:30:03.831075 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 01:30:03.832575 uuid=915610_1.6.2.4.5 testdef=None
225 01:30:03.832936 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 01:30:03.833679 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 01:30:03.836722 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 01:30:03.837558 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 01:30:03.841336 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 01:30:03.842201 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 01:30:03.845837 runner path: /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/0/tests/1_kselftest-dt test_uuid 915610_1.6.2.4.5
235 01:30:03.846129 BOARD='beaglebone-black'
236 01:30:03.846332 BRANCH='mainline'
237 01:30:03.846527 SKIPFILE='/dev/null'
238 01:30:03.846723 SKIP_INSTALL='True'
239 01:30:03.846917 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 01:30:03.847115 TST_CASENAME=''
241 01:30:03.847310 TST_CMDFILES='dt'
242 01:30:03.847873 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 01:30:03.848685 Creating lava-test-runner.conf files
245 01:30:03.848888 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915610/lava-overlay-jwxwhlvu/lava-915610/0 for stage 0
246 01:30:03.849243 - 0_timesync-off
247 01:30:03.849484 - 1_kselftest-dt
248 01:30:03.849817 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 01:30:03.850095 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 01:30:27.037238 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 01:30:27.037687 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 01:30:27.037948 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 01:30:27.038218 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 01:30:27.038477 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 01:30:27.399628 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 01:30:27.400130 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 01:30:27.400387 extracting modules file /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg
258 01:30:28.286897 extracting modules file /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915610/extract-overlay-ramdisk-8pkjaqh_/ramdisk
259 01:30:29.187131 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 01:30:29.187597 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 01:30:29.187873 [common] Applying overlay to NFS
262 01:30:29.188115 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915610/compress-overlay-rc9uqbro/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg
263 01:30:31.900239 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 01:30:31.900722 start: 1.6.6 prepare-kernel (timeout 00:08:57) [common]
265 01:30:31.901026 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:57) [common]
266 01:30:31.901315 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 01:30:31.901583 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 01:30:31.901851 start: 1.6.7 configure-preseed-file (timeout 00:08:57) [common]
269 01:30:31.902111 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 01:30:31.902378 start: 1.6.8 compress-ramdisk (timeout 00:08:57) [common]
271 01:30:31.902638 Building ramdisk /var/lib/lava/dispatcher/tmp/915610/extract-overlay-ramdisk-8pkjaqh_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915610/extract-overlay-ramdisk-8pkjaqh_/ramdisk
272 01:30:32.932614 >> 74899 blocks
273 01:30:37.472727 Adding RAMdisk u-boot header.
274 01:30:37.473222 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915610/extract-overlay-ramdisk-8pkjaqh_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915610/extract-overlay-ramdisk-8pkjaqh_/ramdisk.cpio.gz.uboot
275 01:30:37.638718 output: Image Name:
276 01:30:37.639149 output: Created: Thu Oct 31 01:30:37 2024
277 01:30:37.639575 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 01:30:37.640041 output: Data Size: 14794997 Bytes = 14448.24 KiB = 14.11 MiB
279 01:30:37.640464 output: Load Address: 00000000
280 01:30:37.640868 output: Entry Point: 00000000
281 01:30:37.641272 output:
282 01:30:37.642308 rename /var/lib/lava/dispatcher/tmp/915610/extract-overlay-ramdisk-8pkjaqh_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot
283 01:30:37.643027 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 01:30:37.643580 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 01:30:37.644141 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 01:30:37.644604 No LXC device requested
287 01:30:37.645118 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 01:30:37.645636 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 01:30:37.646132 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 01:30:37.646725 Checking files for TFTP limit of 4294967296 bytes.
291 01:30:37.649446 end: 1 tftp-deploy (duration 00:01:09) [common]
292 01:30:37.650032 start: 2 uboot-action (timeout 00:05:00) [common]
293 01:30:37.650565 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 01:30:37.651075 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 01:30:37.651707 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 01:30:37.652520 substitutions:
297 01:30:37.652952 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 01:30:37.653363 - {DTB_ADDR}: 0x88000000
299 01:30:37.653762 - {DTB}: 915610/tftp-deploy-wdz2iw73/dtb/am335x-boneblack.dtb
300 01:30:37.654161 - {INITRD}: 915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot
301 01:30:37.654559 - {KERNEL_ADDR}: 0x82000000
302 01:30:37.654955 - {KERNEL}: 915610/tftp-deploy-wdz2iw73/kernel/zImage
303 01:30:37.655351 - {LAVA_MAC}: None
304 01:30:37.655789 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg
305 01:30:37.656229 - {NFS_SERVER_IP}: 192.168.6.2
306 01:30:37.656629 - {PRESEED_CONFIG}: None
307 01:30:37.657028 - {PRESEED_LOCAL}: None
308 01:30:37.657422 - {RAMDISK_ADDR}: 0x83000000
309 01:30:37.657814 - {RAMDISK}: 915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot
310 01:30:37.658212 - {ROOT_PART}: None
311 01:30:37.658602 - {ROOT}: None
312 01:30:37.658992 - {SERVER_IP}: 192.168.6.2
313 01:30:37.659382 - {TEE_ADDR}: 0x83000000
314 01:30:37.659886 - {TEE}: None
315 01:30:37.660328 Parsed boot commands:
316 01:30:37.660822 - setenv autoload no
317 01:30:37.661359 - setenv initrd_high 0xffffffff
318 01:30:37.661796 - setenv fdt_high 0xffffffff
319 01:30:37.662200 - dhcp
320 01:30:37.662590 - setenv serverip 192.168.6.2
321 01:30:37.662978 - tftp 0x82000000 915610/tftp-deploy-wdz2iw73/kernel/zImage
322 01:30:37.663366 - tftp 0x83000000 915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot
323 01:30:37.663755 - setenv initrd_size ${filesize}
324 01:30:37.664210 - tftp 0x88000000 915610/tftp-deploy-wdz2iw73/dtb/am335x-boneblack.dtb
325 01:30:37.664607 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 01:30:37.665011 - bootz 0x82000000 0x83000000 0x88000000
327 01:30:37.665513 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 01:30:37.667003 start: 2.3 connect-device (timeout 00:05:00) [common]
330 01:30:37.667423 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 01:30:37.682742 Setting prompt string to ['lava-test: # ']
332 01:30:37.684252 end: 2.3 connect-device (duration 00:00:00) [common]
333 01:30:37.684880 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 01:30:37.685439 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 01:30:37.685992 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 01:30:37.687202 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 01:30:37.726511 >> OK - accepted request
338 01:30:37.728618 Returned 0 in 0 seconds
339 01:30:37.829729 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 01:30:37.831347 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 01:30:37.831922 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 01:30:37.832495 Setting prompt string to ['Hit any key to stop autoboot']
344 01:30:37.832958 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 01:30:37.834480 Trying 192.168.56.22...
346 01:30:37.834968 Connected to conserv3.
347 01:30:37.835376 Escape character is '^]'.
348 01:30:37.835784
349 01:30:37.836232 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 01:30:37.836654
351 01:31:14.558918
352 01:31:14.565831 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 01:31:14.566281 Trying to boot from MMC1
354 01:31:15.141368
355 01:31:15.141945
356 01:31:15.146686 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 01:31:15.147125
358 01:31:15.147527 CPU : AM335X-GP rev 2.0
359 01:31:15.151936 Model: TI AM335x BeagleBone Black
360 01:31:15.152401 DRAM: 512 MiB
361 01:31:15.236439 Core: 160 devices, 18 uclasses, devicetree: separate
362 01:31:15.250347 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 01:31:15.651013 NAND: 0 MiB
364 01:31:15.661065 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 01:31:15.735822 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 01:31:15.757109 <ethaddr> not set. Validating first E-fuse MAC
367 01:31:15.786004 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 01:31:15.844867 Hit any key to stop autoboot: 2
370 01:31:15.845685 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
371 01:31:15.846271 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
372 01:31:15.846743 Setting prompt string to ['=>']
373 01:31:15.847221 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
374 01:31:15.854578 0
375 01:31:15.855421 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 01:31:15.855908 Sending with 10 millisecond of delay
378 01:31:16.990453 => setenv autoload no
379 01:31:17.001196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
380 01:31:17.005986 setenv autoload no
381 01:31:17.006709 Sending with 10 millisecond of delay
383 01:31:18.803066 => setenv initrd_high 0xffffffff
384 01:31:18.813757 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
385 01:31:18.814534 setenv initrd_high 0xffffffff
386 01:31:18.815227 Sending with 10 millisecond of delay
388 01:31:20.431003 => setenv fdt_high 0xffffffff
389 01:31:20.441708 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
390 01:31:20.442540 setenv fdt_high 0xffffffff
391 01:31:20.443223 Sending with 10 millisecond of delay
393 01:31:20.734976 => dhcp
394 01:31:20.745724 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
395 01:31:20.746482 dhcp
396 01:31:20.747708 link up on port 0, speed 100, full duplex
397 01:31:20.748183 BOOTP broadcast 1
398 01:31:20.856689 DHCP client bound to address 192.168.6.16 (105 ms)
399 01:31:20.857416 Sending with 10 millisecond of delay
401 01:31:22.533464 => setenv serverip 192.168.6.2
402 01:31:22.544161 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
403 01:31:22.544962 setenv serverip 192.168.6.2
404 01:31:22.545663 Sending with 10 millisecond of delay
406 01:31:26.027594 => tftp 0x82000000 915610/tftp-deploy-wdz2iw73/kernel/zImage
407 01:31:26.038368 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
408 01:31:26.039209 tftp 0x82000000 915610/tftp-deploy-wdz2iw73/kernel/zImage
409 01:31:26.039632 link up on port 0, speed 100, full duplex
410 01:31:26.043034 Using ethernet@4a100000 device
411 01:31:26.048641 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 01:31:26.056038 Filename '915610/tftp-deploy-wdz2iw73/kernel/zImage'.
413 01:31:26.056496 Load address: 0x82000000
414 01:31:28.202600 Loading: *################################################## 10.9 MiB
415 01:31:28.203189 5.1 MiB/s
416 01:31:28.203595 done
417 01:31:28.206719 Bytes transferred = 11440640 (ae9200 hex)
418 01:31:28.207420 Sending with 10 millisecond of delay
420 01:31:32.652031 => tftp 0x83000000 915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot
421 01:31:32.662798 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
422 01:31:32.663760 tftp 0x83000000 915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot
423 01:31:32.664251 link up on port 0, speed 100, full duplex
424 01:31:32.667835 Using ethernet@4a100000 device
425 01:31:32.673248 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 01:31:32.681863 Filename '915610/tftp-deploy-wdz2iw73/ramdisk/ramdisk.cpio.gz.uboot'.
427 01:31:32.682287 Load address: 0x83000000
428 01:31:35.540999 Loading: *################################################## 14.1 MiB
429 01:31:35.541587 4.9 MiB/s
430 01:31:35.542013 done
431 01:31:35.545316 Bytes transferred = 14795061 (e1c135 hex)
432 01:31:35.546140 Sending with 10 millisecond of delay
434 01:31:37.403028 => setenv initrd_size ${filesize}
435 01:31:37.413763 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
436 01:31:37.414528 setenv initrd_size ${filesize}
437 01:31:37.415216 Sending with 10 millisecond of delay
439 01:31:41.559436 => tftp 0x88000000 915610/tftp-deploy-wdz2iw73/dtb/am335x-boneblack.dtb
440 01:31:41.570197 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:56)
441 01:31:41.571002 tftp 0x88000000 915610/tftp-deploy-wdz2iw73/dtb/am335x-boneblack.dtb
442 01:31:41.571431 link up on port 0, speed 100, full duplex
443 01:31:41.575231 Using ethernet@4a100000 device
444 01:31:41.580745 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 01:31:41.592119 Filename '915610/tftp-deploy-wdz2iw73/dtb/am335x-boneblack.dtb'.
446 01:31:41.592430 Load address: 0x88000000
447 01:31:41.602011 Loading: *################################################## 68.9 KiB
448 01:31:41.602486 4.5 MiB/s
449 01:31:41.610669 done
450 01:31:41.611096 Bytes transferred = 70568 (113a8 hex)
451 01:31:41.611747 Sending with 10 millisecond of delay
453 01:31:54.783420 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 01:31:54.794223 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
455 01:31:54.795050 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 01:31:54.795748 Sending with 10 millisecond of delay
458 01:31:57.133804 => bootz 0x82000000 0x83000000 0x88000000
459 01:31:57.144519 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 01:31:57.145019 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
461 01:31:57.145972 bootz 0x82000000 0x83000000 0x88000000
462 01:31:57.146400 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
463 01:31:57.146878 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 01:31:57.152380 Image Name:
465 01:31:57.152828 Created: 2024-10-31 1:30:37 UTC
466 01:31:57.157858 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 01:31:57.163321 Data Size: 14794997 Bytes = 14.1 MiB
468 01:31:57.163773 Load Address: 00000000
469 01:31:57.169391 Entry Point: 00000000
470 01:31:57.337839 Verifying Checksum ... OK
471 01:31:57.338331 ## Flattened Device Tree blob at 88000000
472 01:31:57.344434 Booting using the fdt blob at 0x88000000
473 01:31:57.344893 Working FDT set to 88000000
474 01:31:57.350000 Using Device Tree in place at 88000000, end 880143a7
475 01:31:57.354319 Working FDT set to 88000000
476 01:31:57.367499
477 01:31:57.367972 Starting kernel ...
478 01:31:57.368433
479 01:31:57.369309 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 01:31:57.369914 start: 2.4.4 auto-login-action (timeout 00:03:40) [common]
481 01:31:57.370405 Setting prompt string to ['Linux version [0-9]']
482 01:31:57.370871 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 01:31:57.371334 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 01:31:58.208884 [ 0.000000] Booting Linux on physical CPU 0x0
485 01:31:58.214877 start: 2.4.4.1 login-action (timeout 00:03:39) [common]
486 01:31:58.215409 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 01:31:58.215867 Setting prompt string to []
488 01:31:58.216402 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 01:31:58.216854 Using line separator: #'\n'#
490 01:31:58.217255 No login prompt set.
491 01:31:58.217679 Parsing kernel messages
492 01:31:58.218068 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 01:31:58.218820 [login-action] Waiting for messages, (timeout 00:03:39)
494 01:31:58.219263 Waiting using forced prompt support (timeout 00:01:50)
495 01:31:58.231489 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j357818-arm-gcc-12-multi-v7-defconfig-df9q8) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Oct 31 00:13:20 UTC 2024
496 01:31:58.237299 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 01:31:58.242826 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 01:31:58.254453 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 01:31:58.260159 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 01:31:58.265915 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 01:31:58.266341 [ 0.000000] Memory policy: Data cache writeback
502 01:31:58.272506 [ 0.000000] efi: UEFI not found.
503 01:31:58.281258 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 01:31:58.281687 [ 0.000000] Zone ranges:
505 01:31:58.287126 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 01:31:58.292808 [ 0.000000] Normal empty
507 01:31:58.298538 [ 0.000000] HighMem empty
508 01:31:58.298973 [ 0.000000] Movable zone start for each node
509 01:31:58.304333 [ 0.000000] Early memory node ranges
510 01:31:58.309910 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 01:31:58.317624 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 01:31:58.343057 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 01:31:58.348620 [ 0.000000] AM335X ES2.0 (sgx neon)
514 01:31:58.360350 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
515 01:31:58.378003 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 01:31:58.389605 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 01:31:58.395272 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 01:31:58.401020 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 01:31:58.411092 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 01:31:58.440086 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 01:31:58.446053 <6>[ 0.000000] trace event string verifier disabled
522 01:31:58.446476 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 01:31:58.451888 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 01:31:58.463263 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 01:31:58.468970 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 01:31:58.476279 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 01:31:58.491277 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 01:31:58.508652 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 01:31:58.515344 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 01:31:58.608667 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 01:31:58.617308 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 01:31:58.629749 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 01:31:58.637958 <6>[ 0.019169] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 01:31:58.647369 <6>[ 0.034071] Console: colour dummy device 80x30
535 01:31:58.653768 Matched prompt #6: WARNING:
536 01:31:58.654249 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 01:31:58.658918 <3>[ 0.038970] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 01:31:58.661753 <3>[ 0.046043] This ensures that you still see kernel messages. Please
539 01:31:58.667891 <3>[ 0.052770] update your kernel commandline.
540 01:31:58.708467 <6>[ 0.057381] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 01:31:58.714266 <6>[ 0.096177] CPU: Testing write buffer coherency: ok
542 01:31:58.720262 <6>[ 0.101543] CPU0: Spectre v2: using BPIALL workaround
543 01:31:58.720686 <6>[ 0.107011] pid_max: default: 32768 minimum: 301
544 01:31:58.731636 <6>[ 0.112206] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 01:31:58.738487 <6>[ 0.120028] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 01:31:58.745500 <6>[ 0.129375] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 01:31:58.821276 <6>[ 0.199557] Setting up static identity map for 0x80300000 - 0x803000ac
548 01:31:58.827037 <6>[ 0.209175] rcu: Hierarchical SRCU implementation.
549 01:31:58.830656 <6>[ 0.214464] rcu: Max phase no-delay instances is 1000.
550 01:31:58.839367 <6>[ 0.225557] EFI services will not be available.
551 01:31:58.845023 <6>[ 0.230930] smp: Bringing up secondary CPUs ...
552 01:31:58.850792 <6>[ 0.235901] smp: Brought up 1 node, 1 CPU
553 01:31:58.858936 <6>[ 0.240372] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 01:31:58.864883 <6>[ 0.247089] CPU: All CPU(s) started in SVC mode.
555 01:31:58.877033 <6>[ 0.252288] Memory: 405992K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49056K reserved, 65536K cma-reserved, 0K highmem)
556 01:31:58.882801 <6>[ 0.268561] devtmpfs: initialized
557 01:31:58.905296 <6>[ 0.285886] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 01:31:58.916787 <6>[ 0.294479] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 01:31:58.922768 <6>[ 0.304919] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 01:31:58.933512 <6>[ 0.317191] pinctrl core: initialized pinctrl subsystem
561 01:31:58.942814 <6>[ 0.327871] DMI not present or invalid.
562 01:31:58.951108 <6>[ 0.333721] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 01:31:58.960573 <6>[ 0.342679] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 01:31:58.975648 <6>[ 0.354116] thermal_sys: Registered thermal governor 'step_wise'
565 01:31:58.976120 <6>[ 0.354289] cpuidle: using governor menu
566 01:31:59.003484 <6>[ 0.390132] No ATAGs?
567 01:31:59.009582 <6>[ 0.392773] hw-breakpoint: debug architecture 0x4 unsupported.
568 01:31:59.019821 <6>[ 0.404732] Serial: AMBA PL011 UART driver
569 01:31:59.049328 <6>[ 0.435864] iommu: Default domain type: Translated
570 01:31:59.058378 <6>[ 0.441210] iommu: DMA domain TLB invalidation policy: strict mode
571 01:31:59.085834 <5>[ 0.471130] SCSI subsystem initialized
572 01:31:59.099554 <6>[ 0.480537] usbcore: registered new interface driver usbfs
573 01:31:59.106442 <6>[ 0.486497] usbcore: registered new interface driver hub
574 01:31:59.106866 <6>[ 0.492342] usbcore: registered new device driver usb
575 01:31:59.112322 <6>[ 0.498841] pps_core: LinuxPPS API ver. 1 registered
576 01:31:59.123718 <6>[ 0.504291] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 01:31:59.132516 <6>[ 0.513993] PTP clock support registered
578 01:31:59.132934 <6>[ 0.518442] EDAC MC: Ver: 3.0.0
579 01:31:59.179623 <6>[ 0.563774] scmi_core: SCMI protocol bus registered
580 01:31:59.204406 <6>[ 0.590278] vgaarb: loaded
581 01:31:59.210545 <6>[ 0.594054] clocksource: Switched to clocksource dmtimer
582 01:31:59.234715 <6>[ 0.621017] NET: Registered PF_INET protocol family
583 01:31:59.247347 <6>[ 0.626721] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 01:31:59.253091 <6>[ 0.635571] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 01:31:59.264498 <6>[ 0.644497] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 01:31:59.270352 <6>[ 0.652738] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 01:31:59.281863 <6>[ 0.661031] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 01:31:59.287721 <6>[ 0.668749] TCP: Hash tables configured (established 4096 bind 4096)
589 01:31:59.293552 <6>[ 0.675672] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 01:31:59.299401 <6>[ 0.682684] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 01:31:59.306073 <6>[ 0.690295] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 01:31:59.393033 <6>[ 0.773946] RPC: Registered named UNIX socket transport module.
593 01:31:59.393484 <6>[ 0.780380] RPC: Registered udp transport module.
594 01:31:59.398729 <6>[ 0.785505] RPC: Registered tcp transport module.
595 01:31:59.404447 <6>[ 0.790612] RPC: Registered tcp-with-tls transport module.
596 01:31:59.417418 <6>[ 0.796533] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 01:31:59.417844 <6>[ 0.803439] PCI: CLS 0 bytes, default 64
598 01:31:59.424591 <5>[ 0.809205] Initialise system trusted keyrings
599 01:31:59.445671 <6>[ 0.829302] Trying to unpack rootfs image as initramfs...
600 01:31:59.523898 <6>[ 0.904340] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 01:31:59.528692 <6>[ 0.911854] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 01:31:59.568047 <5>[ 0.954586] NFS: Registering the id_resolver key type
603 01:31:59.573883 <5>[ 0.960281] Key type id_resolver registered
604 01:31:59.579657 <5>[ 0.964973] Key type id_legacy registered
605 01:31:59.585428 <6>[ 0.969418] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 01:31:59.595024 <6>[ 0.976631] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 01:31:59.667800 <5>[ 1.054457] Key type asymmetric registered
608 01:31:59.673619 <5>[ 1.058983] Asymmetric key parser 'x509' registered
609 01:31:59.685236 <6>[ 1.064456] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 01:31:59.685737 <6>[ 1.072343] io scheduler mq-deadline registered
611 01:31:59.690987 <6>[ 1.077321] io scheduler kyber registered
612 01:31:59.696543 <6>[ 1.081779] io scheduler bfq registered
613 01:31:59.812547 <6>[ 1.195525] ledtrig-cpu: registered to indicate activity on CPUs
614 01:32:00.083584 <6>[ 1.466381] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 01:32:00.121845 <6>[ 1.508384] msm_serial: driver initialized
616 01:32:00.128030 <6>[ 1.513167] SuperH (H)SCI(F) driver initialized
617 01:32:00.133950 <6>[ 1.518548] STMicroelectronics ASC driver initialized
618 01:32:00.139207 <6>[ 1.524232] STM32 USART driver initialized
619 01:32:00.250383 <6>[ 1.636380] brd: module loaded
620 01:32:00.289650 <6>[ 1.675671] loop: module loaded
621 01:32:00.325793 <6>[ 1.711663] CAN device driver interface
622 01:32:00.332423 <6>[ 1.716849] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 01:32:00.338164 <6>[ 1.723785] e1000e: Intel(R) PRO/1000 Network Driver
624 01:32:00.343974 <6>[ 1.729247] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 01:32:00.349697 <6>[ 1.735705] igb: Intel(R) Gigabit Ethernet Network Driver
626 01:32:00.357956 <6>[ 1.741530] igb: Copyright (c) 2007-2014 Intel Corporation.
627 01:32:00.369904 <6>[ 1.750867] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 01:32:00.375639 <6>[ 1.757018] usbcore: registered new interface driver pegasus
629 01:32:00.381482 <6>[ 1.763144] usbcore: registered new interface driver asix
630 01:32:00.387243 <6>[ 1.769025] usbcore: registered new interface driver ax88179_178a
631 01:32:00.392982 <6>[ 1.775613] usbcore: registered new interface driver cdc_ether
632 01:32:00.398815 <6>[ 1.781909] usbcore: registered new interface driver smsc75xx
633 01:32:00.404575 <6>[ 1.788149] usbcore: registered new interface driver smsc95xx
634 01:32:00.410515 <6>[ 1.794392] usbcore: registered new interface driver net1080
635 01:32:00.416203 <6>[ 1.800511] usbcore: registered new interface driver cdc_subset
636 01:32:00.421924 <6>[ 1.806925] usbcore: registered new interface driver zaurus
637 01:32:00.429587 <6>[ 1.812968] usbcore: registered new interface driver cdc_ncm
638 01:32:00.439584 <6>[ 1.822474] usbcore: registered new interface driver usb-storage
639 01:32:00.721472 <6>[ 2.106235] i2c_dev: i2c /dev entries driver
640 01:32:00.781529 <5>[ 2.160241] cpuidle: enable-method property 'ti,am3352' found operations
641 01:32:00.787487 <6>[ 2.169860] sdhci: Secure Digital Host Controller Interface driver
642 01:32:00.794806 <6>[ 2.176661] sdhci: Copyright(c) Pierre Ossman
643 01:32:00.802158 <6>[ 2.183068] Synopsys Designware Multimedia Card Interface Driver
644 01:32:00.807564 <6>[ 2.191040] sdhci-pltfm: SDHCI platform and OF driver helper
645 01:32:00.926121 <6>[ 2.305427] usbcore: registered new interface driver usbhid
646 01:32:00.926571 <6>[ 2.311468] usbhid: USB HID core driver
647 01:32:00.976183 <6>[ 2.360297] NET: Registered PF_INET6 protocol family
648 01:32:01.023002 <6>[ 2.409729] Segment Routing with IPv6
649 01:32:01.028860 <6>[ 2.413872] In-situ OAM (IOAM) with IPv6
650 01:32:01.035579 <6>[ 2.418383] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 01:32:01.042977 <6>[ 2.425684] NET: Registered PF_PACKET protocol family
652 01:32:01.048876 <6>[ 2.431169] can: controller area network core
653 01:32:01.049300 <6>[ 2.436053] NET: Registered PF_CAN protocol family
654 01:32:01.054734 <6>[ 2.441257] can: raw protocol
655 01:32:01.060615 <6>[ 2.444608] can: broadcast manager protocol
656 01:32:01.067350 <6>[ 2.449186] can: netlink gateway - max_hops=1
657 01:32:01.067776 <5>[ 2.454708] Key type dns_resolver registered
658 01:32:01.073147 <6>[ 2.459701] ThumbEE CPU extension supported.
659 01:32:01.079341 <5>[ 2.464468] Registering SWP/SWPB emulation handler
660 01:32:01.087434 <3>[ 2.470120] omap_voltage_late_init: Voltage driver support not added
661 01:32:01.280983 <5>[ 2.665106] Loading compiled-in X.509 certificates
662 01:32:01.429715 <6>[ 2.803447] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 01:32:01.436885 <6>[ 2.820115] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 01:32:01.463182 <3>[ 2.843804] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 01:32:01.672787 <3>[ 3.053364] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 01:32:01.869971 <6>[ 3.254771] OMAP GPIO hardware version 0.1
667 01:32:01.890423 <6>[ 3.273398] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 01:32:01.972995 <4>[ 3.355678] at24 2-0054: supply vcc not found, using dummy regulator
669 01:32:02.008791 <4>[ 3.391518] at24 2-0055: supply vcc not found, using dummy regulator
670 01:32:02.049624 <4>[ 3.432296] at24 2-0056: supply vcc not found, using dummy regulator
671 01:32:02.085562 <4>[ 3.468194] at24 2-0057: supply vcc not found, using dummy regulator
672 01:32:02.125569 <6>[ 3.509026] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 01:32:02.187291 <3>[ 3.566779] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 01:32:02.211921 <6>[ 3.587728] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 01:32:02.232276 <4>[ 3.613741] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 01:32:02.244448 <4>[ 3.625939] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 01:32:02.362015 <6>[ 3.744884] omap_rng 48310000.rng: Random Number Generator ver. 20
678 01:32:02.385517 <5>[ 3.771266] random: crng init done
679 01:32:02.433070 <6>[ 3.814420] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
680 01:32:02.483130 <6>[ 3.868237] Freeing initrd memory: 14452K
681 01:32:02.536039 <6>[ 3.916497] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 01:32:02.541863 <6>[ 3.926824] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 01:32:02.553547 <6>[ 3.934173] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 01:32:02.559368 <6>[ 3.941621] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 01:32:02.570914 <6>[ 3.949757] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 01:32:02.578270 <6>[ 3.961388] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 01:32:02.591452 <5>[ 3.970427] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 01:32:02.619143 <3>[ 4.000135] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 01:32:02.624897 <6>[ 4.008724] edma 49000000.dma: TI EDMA DMA engine driver
690 01:32:02.695975 <3>[ 4.076275] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 01:32:02.710719 <6>[ 4.090593] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 01:32:02.723525 <3>[ 4.107689] l3-aon-clkctrl:0000:0: failed to disable
693 01:32:02.774223 <6>[ 4.155190] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 01:32:02.779883 <6>[ 4.164651] printk: legacy console [ttyS0] enabled
695 01:32:02.785578 <6>[ 4.164651] printk: legacy console [ttyS0] enabled
696 01:32:02.791221 <6>[ 4.174987] printk: legacy bootconsole [omap8250] disabled
697 01:32:02.797098 <6>[ 4.174987] printk: legacy bootconsole [omap8250] disabled
698 01:32:02.834837 <4>[ 4.214820] tps65217-pmic: Failed to locate of_node [id: -1]
699 01:32:02.838446 <4>[ 4.222212] tps65217-bl: Failed to locate of_node [id: -1]
700 01:32:02.854837 <6>[ 4.241754] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 01:32:02.873254 <6>[ 4.248684] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 01:32:02.884948 <6>[ 4.262370] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 01:32:02.890557 <6>[ 4.274270] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 01:32:02.912492 <6>[ 4.293767] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 01:32:02.918389 <6>[ 4.302944] sdhci-omap 48060000.mmc: Got CD GPIO
706 01:32:02.926426 <4>[ 4.308129] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 01:32:02.940906 <4>[ 4.321584] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 01:32:02.947319 <4>[ 4.330215] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 01:32:02.957203 <4>[ 4.338903] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 01:32:03.055958 <6>[ 4.438224] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 01:32:03.104010 <6>[ 4.484321] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
712 01:32:03.110578 <6>[ 4.493464] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
713 01:32:03.119714 <6>[ 4.502446] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 01:32:03.178736 <6>[ 4.554792] mmc0: new high speed SDHC card at address 0001
715 01:32:03.179176 <6>[ 4.563320] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 01:32:03.186768 <4>[ 4.570532] mmc1: unexpected status 0x2000980 after switch
717 01:32:03.200679 <4>[ 4.580825] mmc1: unexpected status 0x2000900 after switch
718 01:32:03.208502 <4>[ 4.587887] mmc1: unexpected status 0x2000900 after switch
719 01:32:03.214159 <4>[ 4.595881] mmc1: unexpected status 0x2000900 after switch
720 01:32:03.221215 <6>[ 4.601731] mmc1: new high speed MMC card at address 0001
721 01:32:03.233759 <6>[ 4.608834] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
722 01:32:03.234190 <6>[ 4.620024] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
723 01:32:03.239032 <6>[ 4.625775] mmcblk0: p1
724 01:32:04.847891 <4>[ 6.227335] mmc1: unexpected status 0x2000980 after switch
725 01:32:04.853977 <4>[ 6.235022] mmc1: unexpected status 0x2000900 after switch
726 01:32:04.860746 <4>[ 6.241309] mmc1: unexpected status 0x2000900 after switch
727 01:32:04.864519 <4>[ 6.248256] mmc1: unexpected status 0x2000900 after switch
728 01:32:05.374362 <6>[ 6.755134] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 01:32:05.477560 <5>[ 6.784074] Sending DHCP requests ., OK
730 01:32:05.488964 <6>[ 6.868496] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
731 01:32:05.489414 <6>[ 6.876677] IP-Config: Complete:
732 01:32:05.500190 <6>[ 6.880218] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
733 01:32:05.506007 <6>[ 6.890740] host=192.168.6.16, domain=, nis-domain=(none)
734 01:32:05.518460 <6>[ 6.896955] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
735 01:32:05.518893 <6>[ 6.896989] nameserver0=10.255.253.1
736 01:32:05.524356 <6>[ 6.909564] clk: Disabling unused clocks
737 01:32:05.530340 <6>[ 6.914365] PM: genpd: Disabling unused power domains
738 01:32:05.550106 <6>[ 6.933371] Freeing unused kernel image (initmem) memory: 2048K
739 01:32:05.557414 <6>[ 6.943045] Run /init as init process
740 01:32:05.624475 <3>[ 7.005066] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
741 01:32:05.642653 Loading, please wait...
742 01:32:05.717864 Starting systemd-udevd version 252.22-1~deb12u1
743 01:32:06.406601 <3>[ 7.787507] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
744 01:32:07.166952 <3>[ 8.547902] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 01:32:07.944598 <3>[ 9.325585] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 01:32:08.715511 <3>[ 10.096565] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 01:32:09.131303 <4>[ 10.511071] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 01:32:09.283824 <4>[ 10.664436] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 01:32:09.507296 <3>[ 10.888374] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
750 01:32:09.521493 <6>[ 10.908803] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
751 01:32:09.532528 <6>[ 10.914656] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
752 01:32:09.648467 <6>[ 11.034232] hub 1-0:1.0: USB hub found
753 01:32:09.656068 <6>[ 11.041563] tda998x 0-0070: found TDA19988
754 01:32:09.728935 <6>[ 11.114331] hub 1-0:1.0: 1 port detected
755 01:32:10.354274 <3>[ 11.735361] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 01:32:10.741186 <6>[ 12.124233] usb 1-1: new low-speed USB device number 2 using musb-hdrc
757 01:32:10.889190 <3>[ 12.274254] usb 1-1: device descriptor read/64, error -71
758 01:32:11.119216 <3>[ 12.500830] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
759 01:32:11.127296 <3>[ 12.509768] Buffer I/O error on dev mmcblk1, logical block 0, async page read
760 01:32:11.240475 <3>[ 12.624355] usb 1-1: device descriptor read/64, error -71
761 01:32:11.481449 <6>[ 12.864423] usb 1-1: new low-speed USB device number 3 using musb-hdrc
762 01:32:11.660362 <3>[ 13.044342] usb 1-1: device descriptor read/64, error -71
763 01:32:11.989814 <3>[ 13.374305] usb 1-1: device descriptor read/64, error -71
764 01:32:12.099633 <6>[ 13.484434] usb usb1-port1: attempt power cycle
765 01:32:12.291413 <6>[ 13.674382] usb 1-1: new low-speed USB device number 4 using musb-hdrc
766 01:32:12.891281 <6>[ 14.274102] usb 1-1: new low-speed USB device number 5 using musb-hdrc
767 01:32:13.456244 Begin: Loading essential drivers ... done.
768 01:32:13.456748 Begin: Running /scripts/init-premount ... done.
769 01:32:13.457162 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 01:32:13.459532 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 01:32:13.459961 Device /sys/class/net/eth0 found
772 01:32:13.460410 done.
773 01:32:13.589191 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 01:32:13.680244 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
775 01:32:13.792085 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 01:32:13.797618 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 01:32:13.803169 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 01:32:13.814365 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 01:32:13.814800 rootserver: 192.168.6.1 rootpath:
780 01:32:13.817860 filename :
781 01:32:13.931741 done.
782 01:32:13.941315 Begin: Running /scripts/nfs-bottom ... done.
783 01:32:14.004308 Begin: Running /scripts/init-bottom ... done.
784 01:32:14.309071 <3>[ 15.690887] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
785 01:32:15.069921 <3>[ 16.450979] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
786 01:32:17.667174 <3>[ 19.048314] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
787 01:32:17.683724 <30>[ 19.066623] systemd[1]: System time before build time, advancing clock.
788 01:32:17.909311 <30>[ 19.266057] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
789 01:32:17.918115 <30>[ 19.302726] systemd[1]: Detected architecture arm.
790 01:32:17.932075
791 01:32:17.932503 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
792 01:32:17.932913
793 01:32:17.960943 <30>[ 19.344397] systemd[1]: Hostname set to <debian-bookworm-armhf>.
794 01:32:18.430794 <3>[ 19.811980] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 01:32:19.189486 <3>[ 20.570739] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 01:32:19.947885 <3>[ 21.329199] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
797 01:32:20.297175 <30>[ 21.679682] systemd[1]: Queued start job for default target graphical.target.
798 01:32:20.313827 <30>[ 21.694549] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
799 01:32:20.321426 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
800 01:32:20.346811 <30>[ 21.726516] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
801 01:32:20.354409 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
802 01:32:20.379441 <30>[ 21.760253] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
803 01:32:20.392424 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
804 01:32:20.414519 <30>[ 21.795892] systemd[1]: Created slice user.slice - User and Session Slice.
805 01:32:20.421221 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
806 01:32:20.451176 <30>[ 21.825462] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
807 01:32:20.457123 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
808 01:32:20.485863 <30>[ 21.866157] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
809 01:32:20.496872 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
810 01:32:20.534771 <30>[ 21.904933] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
811 01:32:20.541179 <30>[ 21.925393] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
812 01:32:20.549646 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
813 01:32:20.573158 <30>[ 21.954491] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
814 01:32:20.581334 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
815 01:32:20.603839 <30>[ 21.984856] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
816 01:32:20.612318 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
817 01:32:20.633754 <30>[ 22.015005] systemd[1]: Reached target paths.target - Path Units.
818 01:32:20.638856 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
819 01:32:20.709307 <3>[ 22.090248] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
820 01:32:20.716658 <30>[ 22.100111] systemd[1]: Reached target remote-fs.target - Remote File Systems.
821 01:32:20.727149 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
822 01:32:20.753487 <30>[ 22.134695] systemd[1]: Reached target slices.target - Slice Units.
823 01:32:20.758940 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
824 01:32:20.783578 <30>[ 22.164849] systemd[1]: Reached target swap.target - Swaps.
825 01:32:20.787672 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
826 01:32:20.814051 <30>[ 22.194967] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
827 01:32:20.821916 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
828 01:32:20.844755 <30>[ 22.225696] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
829 01:32:20.853051 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
830 01:32:20.932361 <30>[ 22.308563] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
831 01:32:20.944998 <30>[ 22.326132] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
832 01:32:20.953461 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
833 01:32:20.976462 <30>[ 22.356713] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
834 01:32:20.983860 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
835 01:32:21.006008 <30>[ 22.387072] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
836 01:32:21.014322 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
837 01:32:21.039126 <30>[ 22.419020] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
838 01:32:21.044709 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
839 01:32:21.076040 <30>[ 22.455806] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
840 01:32:21.083567 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
841 01:32:21.110727 <30>[ 22.485806] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
842 01:32:21.129388 <30>[ 22.504374] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
843 01:32:21.177454 <30>[ 22.559363] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
844 01:32:21.208123 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
845 01:32:21.267226 <30>[ 22.648938] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
846 01:32:21.283625 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
847 01:32:21.334585 <30>[ 22.715425] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
848 01:32:21.351722 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
849 01:32:21.405427 <30>[ 22.786802] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
850 01:32:21.578390 Starting [0;1;39mmodprobe@configfs…m - Load Kernel M<3>[ 22.955583] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
851 01:32:21.578847 odule configfs...
852 01:32:21.590231 <3>[ 22.969405] Buffer I/O error on dev mmcblk1, logical block 0, async page read
853 01:32:21.594026 <6>[ 22.978949] mmcblk1: unable to read partition table
854 01:32:21.611729 <6>[ 22.996612] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
855 01:32:21.625553 <6>[ 23.010436] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
856 01:32:21.645568 <6>[ 23.029273] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
857 01:32:21.663546 <30>[ 23.045346] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
858 01:32:21.674190 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
859 01:32:21.706655 <30>[ 23.089029] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
860 01:32:21.753046 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
861 01:32:21.814156 <30>[ 23.195269] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
862 01:32:21.841564 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
863 01:32:21.893340 <30>[ 23.275396] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
864 01:32:21.910958 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
865 01:32:21.975452 <30>[ 23.357581] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
866 01:32:22.003598 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
867 01:32:22.031685 <28>[ 23.406347] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
868 01:32:22.040229 <28>[ 23.421519] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
869 01:32:22.082853 <30>[ 23.465479] systemd[1]: Starting systemd-journald.service - Journal Service...
870 01:32:22.101526 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
871 01:32:22.183338 <30>[ 23.565239] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
872 01:32:22.197932 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
873 01:32:22.255087 <30>[ 23.637207] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
874 01:32:22.303611 Starting [0;1;39msystemd-network-g… units from Kernel command line...
875 01:32:22.368819 <30>[ 23.749450] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
876 01:32:22.422516 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
877 01:32:22.493902 <30>[ 23.875346] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
878 01:32:22.526797 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
879 01:32:22.597588 <30>[ 23.979721] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
880 01:32:22.634214 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
881 01:32:22.653725 <30>[ 24.035850] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
882 01:32:22.693272 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
883 01:32:22.717566 <30>[ 24.098616] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
884 01:32:22.742572 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
885 01:32:22.885618 <30>[ 24.268427] systemd[1]: modprobe@configfs.service: Deactivated successfully.
886 01:32:22.923507 <30>[ 24.304681] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
887 01:32:22.932204 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
888 01:32:22.953895 <30>[ 24.336898] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
889 01:32:22.983841 <30>[ 24.365908] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
890 01:32:23.007141 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
891 01:32:23.024373 <30>[ 24.405800] systemd[1]: Started systemd-journald.service - Journal Service.
892 01:32:23.031209 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
893 01:32:23.063115 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
894 01:32:23.097955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
895 01:32:23.128938 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
896 01:32:23.163185 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
897 01:32:23.195614 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
898 01:32:23.215621 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
899 01:32:23.236503 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
900 01:32:23.267732 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
901 01:32:23.333895 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
902 01:32:23.405147 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
903 01:32:23.475123 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
904 01:32:23.524806 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
905 01:32:23.603048 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
906 01:32:23.766360 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
907 01:32:23.804071 <46>[ 25.186168] systemd-journald[164]: Received client request to flush runtime journal.
908 01:32:23.931393 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
909 01:32:24.050404 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
910 01:32:24.802978 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
911 01:32:24.867555 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
912 01:32:25.624562 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
913 01:32:25.796523 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
914 01:32:25.825319 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
915 01:32:25.843184 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
916 01:32:25.916186 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
917 01:32:25.986442 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
918 01:32:26.867617 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
919 01:32:26.974267 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
920 01:32:27.047584 <4>[ 28.431984] mmc1: unexpected status 0x2000980 after switch
921 01:32:27.060788 <4>[ 28.445291] mmc1: unexpected status 0x2000900 after switch
922 01:32:27.090548 <4>[ 28.474928] mmc1: unexpected status 0x2000900 after switch
923 01:32:27.110314 <4>[ 28.494807] mmc1: unexpected status 0x2000900 after switch
924 01:32:27.279968 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
925 01:32:27.408079 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
926 01:32:27.483064 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
927 01:32:29.180191 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
928 01:32:29.404677 <5>[ 30.787004] cfg80211: Loading compiled-in X.509 certificates for regulatory database
929 01:32:29.553918 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
930 01:32:30.343670 <3>[ 31.724369] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
931 01:32:30.975333 <5>[ 32.355402] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
932 01:32:30.982127 <5>[ 32.363499] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
933 01:32:30.993447 <4>[ 32.373359] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
934 01:32:30.997083 <6>[ 32.382488] cfg80211: failed to load regulatory.db
935 01:32:31.134379 <3>[ 32.515181] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
936 01:32:31.775080 [[0m[0;31m* [0m] (1 of 3) Job dev-ttyS0.device/start running (11s / 1min 30s)
937 01:32:31.910141 <3>[ 33.290925] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
938 01:32:32.130545 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
939 01:32:32.303726 [K<46>[ 33.676009] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
940 01:32:32.376538 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
941 01:32:32.458062 <46>[ 33.833560] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
942 01:32:32.703454 <3>[ 34.084269] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
943 01:32:33.483387 <3>[ 34.863961] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
944 01:32:34.275248 <3>[ 35.656042] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
945 01:32:34.487074 [[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
946 01:32:34.957016 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
947 01:32:35.053486 <3>[ 36.434258] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
948 01:32:35.389253 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
949 01:32:35.815081 <3>[ 37.196044] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
950 01:32:36.068093 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
951 01:32:36.567935 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
952 01:32:37.025109 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
953 01:32:37.558608 M
[K[ [0;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
954 01:32:37.902216 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
955 01:32:38.285556 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
956 01:32:38.630132 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
957 01:32:39.022193 <3>[ 40.403628] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
958 01:32:39.035029 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
959 01:32:39.409170 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (19s / 1min 30s)
960 01:32:39.437918 M
[K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
961 01:32:39.464084 [K[[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
962 01:32:39.488430 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
963 01:32:39.563655 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
964 01:32:39.613785 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
965 01:32:39.677015 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
966 01:32:39.718051 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
967 01:32:39.782077 <3>[ 41.163378] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
968 01:32:39.821479 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
969 01:32:39.849684 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
970 01:32:39.878962 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
971 01:32:39.920360 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
972 01:32:39.948439 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
973 01:32:39.993186 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
974 01:32:40.016470 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
975 01:32:40.051247 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
976 01:32:40.078758 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
977 01:32:40.146481 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
978 01:32:40.173702 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
979 01:32:40.198521 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
980 01:32:40.234545 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
981 01:32:40.253093 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
982 01:32:40.276154 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
983 01:32:40.353796 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
984 01:32:40.391041 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
985 01:32:40.541324 <3>[ 41.923006] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
986 01:32:40.566581 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
987 01:32:40.602191 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
988 01:32:40.657016 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
989 01:32:40.690194 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
990 01:32:40.722501 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
991 01:32:40.970530 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
992 01:32:41.044335 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
993 01:32:41.145903 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
994 01:32:41.300841 <3>[ 42.682313] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
995 01:32:41.480447 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
996 01:32:41.763066 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
997 01:32:42.069872 <3>[ 43.451220] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
998 01:32:42.838950 <3>[ 44.220279] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
999 01:32:43.607926 <3>[ 44.989308] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1000 01:32:43.900685 [[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (23s / 1min 30s)
1001 01:32:44.375865 <3>[ 45.758323] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1002 01:32:44.384939 <3>[ 45.767825] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1003 01:32:44.682349 M
[K[[0m[0;31m* [0m] Job dev-ttyS0.device/start running (24s / 1min 30s)
1004 01:32:45.841619 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (25s / 1min 30s)
1005 01:32:46.290389 M
[K[[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1006 01:32:47.749815 [K[[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1007 01:32:47.822756 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1008 01:32:47.850537 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1009 01:32:47.878174 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1010 01:32:47.917338 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1011 01:32:48.007122 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1012 01:32:48.123311
1013 01:32:48.127552 Debian GNU/Linux 12 debian-booworm-armhf login: root (automatic login)
1014 01:32:48.128038
1015 01:32:48.477381 <3>[ 49.858599] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1016 01:32:48.588196 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Thu Oct 31 00:13:20 UTC 2024 armv7l
1017 01:32:48.588816
1018 01:32:48.593843 The programs included with the Debian GNU/Linux system are free software;
1019 01:32:48.597220 the exact distribution terms for each program are described in the
1020 01:32:48.602797 individual files in /usr/share/doc/*/copyright.
1021 01:32:48.603323
1022 01:32:48.608316 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1023 01:32:48.612999 permitted by applicable law.
1024 01:32:49.236573 <3>[ 50.617880] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1025 01:32:49.995709 <3>[ 51.376993] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1026 01:32:50.754790 <3>[ 52.136119] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1027 01:32:51.513877 <3>[ 52.895223] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1028 01:32:52.273019 <3>[ 53.654380] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1029 01:32:53.036146 <3>[ 54.417497] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1030 01:32:53.696415 Unable to match end of the kernel message
1032 01:32:53.698056 Setting prompt string to ['/ #']
1033 01:32:53.698673 end: 2.4.4.1 login-action (duration 00:00:55) [common]
1035 01:32:53.700217 end: 2.4.4 auto-login-action (duration 00:00:56) [common]
1036 01:32:53.700814 start: 2.4.5 expect-shell-connection (timeout 00:02:44) [common]
1037 01:32:53.701304 Setting prompt string to ['/ #']
1038 01:32:53.701760 Forcing a shell prompt, looking for ['/ #']
1040 01:32:53.752812 / #
1041 01:32:53.753760 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1042 01:32:53.754314 Waiting using forced prompt support (timeout 00:02:30)
1043 01:32:53.846941 <3>[ 55.227063] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1044 01:32:53.847528
1045 01:32:53.857879 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1046 01:32:53.858546 start: 2.4.6 export-device-env (timeout 00:02:44) [common]
1047 01:32:53.859080 Sending with 10 millisecond of delay
1049 01:32:58.848316 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/915610/extract-nfsrootfs-s5zj25lg'
1050 01:32:58.859377 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/91<3>[ 58.366358] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1051 01:32:58.860046 5610/extract-<3>[ 59.135473] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1052 01:32:58.860557 nfsrootfs-s5z<3>[ 59.904576] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1053 01:32:58.861009 j25lg'
1054 01:32:58.861781 Sending with 10 millisecond of delay
1056 01:33:00.960305 / # export NFS_SERVER_IP='192.168.6.2'
1057 01:33:00.971290 export<3>[ 60.673688] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1058 01:33:00.971838 NFS_SERVER_<3>[ 61.435628] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1059 01:33:00.972376 IP='192.168.6<3>[ 62.204578] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1060 01:33:00.972842 .2'
1061 01:33:00.973766 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1062 01:33:00.974399 end: 2.4 uboot-commands (duration 00:02:23) [common]
1063 01:33:00.975033 end: 2 uboot-action (duration 00:02:23) [common]
1064 01:33:00.975638 start: 3 lava-test-retry (timeout 00:06:27) [common]
1065 01:33:00.976307 start: 3.1 lava-test-shell (timeout 00:06:27) [common]
1066 01:33:00.976821 Using namespace: common
1068 01:33:01.078070 / # #
1069 01:33:01.078979 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1070 01:33:01.082706 #
1071 01:33:01.089502 Using /lava-915610
1073 01:33:01.190738 / # export SHELL=/bin/bash
1074 01:33:01.196409 export SHELL=/bin/bash
1076 01:33:01.303274 / # . /lava-915610/environment
1077 01:33:01.308939 . /lava-915610/environment
1079 01:33:01.421692 / # /lava-915610/bin/lava-test-runner /lava-915610/0
1080 01:33:01.422574 Test shell timeout: 10s (minimum of the action and connection timeout)
1081 01:33:01.427158 /lava-915610/bin/lava-test-runner /lava-915610/0
1082 01:33:01.581664 <3>[ 62.963735] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1083 01:33:01.874655 + export TESTRUN_ID=0_timesync-off
1084 01:33:01.882636 + TESTRUN_ID=0_timesync-off
1085 01:33:01.883156 + cd /lava-915610/0/tests/0_timesync-off
1086 01:33:01.883616 ++ cat uuid
1087 01:33:01.903429 + UUID=915610_1.6.2.4.1
1088 01:33:01.903945 + set +x
1089 01:33:01.912090 <LAVA_SIGNAL_STARTRUN 0_timesync-off 915610_1.6.2.4.1>
1090 01:33:01.912601 + systemctl stop systemd-timesyncd
1091 01:33:01.913355 Received signal: <STARTRUN> 0_timesync-off 915610_1.6.2.4.1
1092 01:33:01.913829 Starting test lava.0_timesync-off (915610_1.6.2.4.1)
1093 01:33:01.914398 Skipping test definition patterns.
1094 01:33:02.190891 + set +x
1095 01:33:02.191455 <LAVA_SIGNAL_ENDRUN 0_timesync-off 915610_1.6.2.4.1>
1096 01:33:02.192180 Received signal: <ENDRUN> 0_timesync-off 915610_1.6.2.4.1
1097 01:33:02.192716 Ending use of test pattern.
1098 01:33:02.193168 Ending test lava.0_timesync-off (915610_1.6.2.4.1), duration 0.28
1100 01:33:02.339516 <3>[ 63.722803] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1101 01:33:02.348635 <3>[ 63.732204] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1102 01:33:02.512614 + export TESTRUN_ID=1_kselftest-dt
1103 01:33:02.520574 + TESTRUN_ID=1_kselftest-dt
1104 01:33:02.521087 + cd /lava-915610/0/tests/1_kselftest-dt
1105 01:33:02.521552 ++ cat uuid
1106 01:33:02.536696 + UUID=915610_1.6.2.4.5
1107 01:33:02.537200 + set +x
1108 01:33:02.542217 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 915610_1.6.2.4.5>
1109 01:33:02.542723 + cd ./automated/linux/kselftest/
1110 01:33:02.543460 Received signal: <STARTRUN> 1_kselftest-dt 915610_1.6.2.4.5
1111 01:33:02.543925 Starting test lava.1_kselftest-dt (915610_1.6.2.4.5)
1112 01:33:02.544666 Skipping test definition patterns.
1113 01:33:02.570298 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1114 01:33:02.669216 INFO: install_deps skipped
1115 01:33:03.309972 --2024-10-31 01:33:03-- http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1116 01:33:03.342522 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1117 01:33:03.488475 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1118 01:33:03.633777 HTTP request sent, awaiting response... 200 OK
1119 01:33:03.634308 Length: 4111724 (3.9M) [application/octet-stream]
1120 01:33:03.639402 Saving to: 'kselftest_armhf.tar.gz'
1121 01:33:03.639857
1122 01:33:05.666351
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 173KB/s
kselftest_armhf.tar 5%[> ] 218.67K 371KB/s
kselftest_armhf.tar 15%[==> ] 640.54K 620KB/s
kselftest_armhf.tar 37%[======> ] 1.47M 1.14MB/s
kselftest_armhf.tar 60%[===========> ] 2.37M 1.50MB/s
kselftest_armhf.tar 84%[===============> ] 3.32M 1.84MB/s
kselftest_armhf.tar 97%[==================> ] 3.82M 1.90MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 1.94MB/s in 2.0s
1123 01:33:05.666964
1124 01:33:06.433349 2024-10-31 01:33:05 (1.94 MB/s) - 'kselftest_armhf.tar.gz' saved [4111724/4111724]
1125 01:33:06.433934
1126 01:33:18.889318 skiplist:
1127 01:33:18.889953 ========================================
1128 01:33:18.894421 ========================================
1129 01:33:18.993640 dt:test_unprobed_devices.sh
1130 01:33:19.024518 ============== Tests to run ===============
1131 01:33:19.033901 dt:test_unprobed_devices.sh
1132 01:33:19.037793 ===========End Tests to run ===============
1133 01:33:19.045802 shardfile-dt pass
1134 01:33:19.266358 <12>[ 80.653867] kselftest: Running tests in dt
1135 01:33:19.294448 TAP version 13
1136 01:33:19.318133 1..1
1137 01:33:19.372339 # timeout set to 45
1138 01:33:19.372778 # selftests: dt: test_unprobed_devices.sh
1139 01:33:20.108089 # TAP version 13
1140 01:33:45.059325 # 1..257
1141 01:33:45.233043 # ok 1 / # SKIP
1142 01:33:45.258865 # ok 2 /clk_mcasp0
1143 01:33:45.330236 # ok 3 /clk_mcasp0_fixed # SKIP
1144 01:33:45.400279 # ok 4 /cpus/cpu@0 # SKIP
1145 01:33:45.466467 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1146 01:33:45.487509 # ok 6 /fixedregulator0
1147 01:33:45.510799 # ok 7 /leds
1148 01:33:45.528012 # ok 8 /ocp
1149 01:33:45.552708 # ok 9 /ocp/interconnect@44c00000
1150 01:33:45.575715 # ok 10 /ocp/interconnect@44c00000/segment@0
1151 01:33:45.603244 # ok 11 /ocp/interconnect@44c00000/segment@100000
1152 01:33:45.623389 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1153 01:33:45.698082 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1154 01:33:45.717730 # ok 14 /ocp/interconnect@44c00000/segment@200000
1155 01:33:45.740487 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1156 01:33:45.845320 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1157 01:33:45.918950 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1158 01:33:45.994885 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1159 01:33:46.061465 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1160 01:33:46.132752 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1161 01:33:46.204480 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1162 01:33:46.276401 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1163 01:33:46.347407 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1164 01:33:46.419791 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1165 01:33:46.491650 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1166 01:33:46.563065 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1167 01:33:46.634386 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1168 01:33:46.706417 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1169 01:33:46.778133 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1170 01:33:46.850128 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1171 01:33:46.920862 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1172 01:33:46.991438 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1173 01:33:47.063249 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1174 01:33:47.134482 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1175 01:33:47.206289 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1176 01:33:47.277297 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1177 01:33:47.352820 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1178 01:33:47.420417 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1179 01:33:47.497641 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1180 01:33:47.568986 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1181 01:33:47.640026 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1182 01:33:47.708919 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1183 01:33:47.784237 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1184 01:33:47.856293 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1185 01:33:47.928380 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1186 01:33:48.000581 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1187 01:33:48.067634 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1188 01:33:48.141298 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1189 01:33:48.211681 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1190 01:33:48.288585 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1191 01:33:48.359616 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1192 01:33:48.427514 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1193 01:33:48.499712 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1194 01:33:48.577480 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1195 01:33:48.649355 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1196 01:33:48.720812 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1197 01:33:48.788778 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1198 01:33:48.860289 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1199 01:33:48.931119 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1200 01:33:49.009648 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1201 01:33:49.080089 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1202 01:33:49.148959 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1203 01:33:49.221112 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1204 01:33:49.294625 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1205 01:33:49.365286 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1206 01:33:49.437616 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1207 01:33:49.511605 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1208 01:33:49.582139 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1209 01:33:49.656744 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1210 01:33:49.729813 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1211 01:33:49.806905 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1212 01:33:49.880351 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1213 01:33:49.949148 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1214 01:33:50.021542 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1215 01:33:50.094478 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1216 01:33:50.166098 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1217 01:33:50.237778 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1218 01:33:50.309498 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1219 01:33:50.381469 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1220 01:33:50.453793 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1221 01:33:50.525413 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1222 01:33:50.596757 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1223 01:33:50.667627 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1224 01:33:50.742645 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1225 01:33:50.809532 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1226 01:33:50.883070 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1227 01:33:50.955055 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1228 01:33:51.026448 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1229 01:33:51.100730 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1230 01:33:51.172840 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1231 01:33:51.241873 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1232 01:33:51.316022 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1233 01:33:51.387485 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1234 01:33:51.459854 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1235 01:33:51.480661 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1236 01:33:51.504242 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1237 01:33:51.529134 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1238 01:33:51.552401 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1239 01:33:51.576021 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1240 01:33:51.600307 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1241 01:33:51.623843 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1242 01:33:51.646062 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1243 01:33:51.750830 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1244 01:33:51.775333 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1245 01:33:51.803756 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1246 01:33:51.823610 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1247 01:33:51.929077 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1248 01:33:52.003353 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1249 01:33:52.075158 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1250 01:33:52.147767 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1251 01:33:52.219758 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1252 01:33:52.296667 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1253 01:33:52.364266 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1254 01:33:52.435824 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1255 01:33:52.507608 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1256 01:33:52.580560 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1257 01:33:52.661292 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1258 01:33:52.726432 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1259 01:33:52.796832 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1260 01:33:52.871212 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1261 01:33:52.947904 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1262 01:33:53.016524 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1263 01:33:53.037606 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1264 01:33:53.108300 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1265 01:33:53.182919 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1266 01:33:53.250908 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1267 01:33:53.272674 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1268 01:33:53.343478 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1269 01:33:53.367181 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1270 01:33:53.436510 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1271 01:33:53.459272 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1272 01:33:53.483270 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1273 01:33:53.505812 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1274 01:33:53.530367 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1275 01:33:53.552441 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1276 01:33:53.577420 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1277 01:33:53.607031 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1278 01:33:53.680982 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1279 01:33:53.702678 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1280 01:33:53.727007 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1281 01:33:53.798196 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1282 01:33:53.868603 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1283 01:33:53.887122 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1284 01:33:53.989247 # not ok 144 /ocp/interconnect@47c00000
1285 01:33:54.060336 # not ok 145 /ocp/interconnect@47c00000/segment@0
1286 01:33:54.081070 # ok 146 /ocp/interconnect@48000000
1287 01:33:54.104282 # ok 147 /ocp/interconnect@48000000/segment@0
1288 01:33:54.124813 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1289 01:33:54.148460 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1290 01:33:54.171312 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1291 01:33:54.196769 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1292 01:33:54.217012 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1293 01:33:54.245846 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1294 01:33:54.266754 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1295 01:33:54.337083 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1296 01:33:54.407449 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1297 01:33:54.429676 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1298 01:33:54.457432 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1299 01:33:54.476507 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1300 01:33:54.500838 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1301 01:33:54.526753 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1302 01:33:54.552563 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1303 01:33:54.570538 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1304 01:33:54.593554 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1305 01:33:54.617452 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1306 01:33:54.641596 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1307 01:33:54.666620 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1308 01:33:54.694446 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1309 01:33:54.716683 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1310 01:33:54.741680 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1311 01:33:54.764678 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1312 01:33:54.787454 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1313 01:33:54.807339 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1314 01:33:54.832241 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1315 01:33:54.852410 # ok 175 /ocp/interconnect@48000000/segment@100000
1316 01:33:54.882016 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1317 01:33:54.906080 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1318 01:33:54.978482 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1319 01:33:55.050729 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1320 01:33:55.116783 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1321 01:33:55.190820 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1322 01:33:55.259560 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1323 01:33:55.338195 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1324 01:33:55.406934 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1325 01:33:55.480708 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1326 01:33:55.495835 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1327 01:33:55.519563 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1328 01:33:55.542716 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1329 01:33:55.565978 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1330 01:33:55.589938 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1331 01:33:55.613996 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1332 01:33:55.639594 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1333 01:33:55.660875 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1334 01:33:55.684312 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1335 01:33:55.712189 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1336 01:33:55.731145 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1337 01:33:55.757586 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1338 01:33:55.780680 # ok 198 /ocp/interconnect@48000000/segment@200000
1339 01:33:55.801863 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1340 01:33:55.877930 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1341 01:33:55.902291 # ok 201 /ocp/interconnect@48000000/segment@300000
1342 01:33:55.924916 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1343 01:33:55.947123 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1344 01:33:55.968652 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1345 01:33:55.991686 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1346 01:33:56.014953 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1347 01:33:56.042897 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1348 01:33:56.115387 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1349 01:33:56.134069 # ok 209 /ocp/interconnect@4a000000
1350 01:33:56.152840 # ok 210 /ocp/interconnect@4a000000/segment@0
1351 01:33:56.178358 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1352 01:33:56.206894 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1353 01:33:56.228471 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1354 01:33:56.253881 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1355 01:33:56.324939 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1356 01:33:56.428766 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1357 01:33:56.497094 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1358 01:33:56.600273 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1359 01:33:56.674938 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1360 01:33:56.745900 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1361 01:33:56.843536 # not ok 221 /ocp/interconnect@4b140000
1362 01:33:56.914728 # not ok 222 /ocp/interconnect@4b140000/segment@0
1363 01:33:56.981089 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1364 01:33:57.004085 # ok 224 /ocp/target-module@40300000
1365 01:33:57.025220 # ok 225 /ocp/target-module@40300000/sram@0
1366 01:33:57.098808 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1367 01:33:57.174978 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1368 01:33:57.193991 # ok 228 /ocp/target-module@47400000
1369 01:33:57.219400 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1370 01:33:57.242410 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1371 01:33:57.260303 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1372 01:33:57.284890 # ok 232 /ocp/target-module@47400000/usb@1400
1373 01:33:57.305426 # ok 233 /ocp/target-module@47400000/usb@1800
1374 01:33:57.326945 # ok 234 /ocp/target-module@47810000
1375 01:33:57.353135 # ok 235 /ocp/target-module@49000000
1376 01:33:57.374520 # ok 236 /ocp/target-module@49000000/dma@0
1377 01:33:57.392790 # ok 237 /ocp/target-module@49800000
1378 01:33:57.421022 # ok 238 /ocp/target-module@49800000/dma@0
1379 01:33:57.442527 # ok 239 /ocp/target-module@49900000
1380 01:33:57.464531 # ok 240 /ocp/target-module@49900000/dma@0
1381 01:33:57.484096 # ok 241 /ocp/target-module@49a00000
1382 01:33:57.510989 # ok 242 /ocp/target-module@49a00000/dma@0
1383 01:33:57.532362 # ok 243 /ocp/target-module@4c000000
1384 01:33:57.604328 # not ok 244 /ocp/target-module@4c000000/emif@0
1385 01:33:57.621448 # ok 245 /ocp/target-module@50000000
1386 01:33:57.648308 # ok 246 /ocp/target-module@53100000
1387 01:33:57.715213 # not ok 247 /ocp/target-module@53100000/sham@0
1388 01:33:57.740985 # ok 248 /ocp/target-module@53500000
1389 01:33:57.812282 # not ok 249 /ocp/target-module@53500000/aes@0
1390 01:33:57.829324 # ok 250 /ocp/target-module@56000000
1391 01:33:57.935312 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1392 01:33:58.002178 # ok 252 /opp-table # SKIP
1393 01:33:58.072650 # ok 253 /soc # SKIP
1394 01:33:58.097855 # ok 254 /sound
1395 01:33:58.116007 # ok 255 /target-module@4b000000
1396 01:33:58.145538 # ok 256 /target-module@4b000000/target-module@140000
1397 01:33:58.161936 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1398 01:33:58.170498 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1399 01:33:58.178365 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1400 01:34:00.586923 dt_test_unprobed_devices_sh_ skip
1401 01:34:00.592288 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1402 01:34:00.597962 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1403 01:34:00.598468 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1404 01:34:00.603392 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1405 01:34:00.609083 dt_test_unprobed_devices_sh_fixedregulator0 pass
1406 01:34:00.614631 dt_test_unprobed_devices_sh_leds pass
1407 01:34:00.615055 dt_test_unprobed_devices_sh_ocp pass
1408 01:34:00.620385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1409 01:34:00.625619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1410 01:34:00.632317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1411 01:34:00.642664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1412 01:34:00.648110 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1413 01:34:00.653702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1414 01:34:00.664951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1415 01:34:00.670493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1416 01:34:00.681828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1417 01:34:00.693061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1418 01:34:00.704218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1419 01:34:00.709893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1420 01:34:00.721193 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1421 01:34:00.732246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1422 01:34:00.743383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1423 01:34:00.754589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1424 01:34:00.760214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1425 01:34:00.771352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1426 01:34:00.782540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1427 01:34:00.793726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1428 01:34:00.804988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1429 01:34:00.810517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1430 01:34:00.821739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1431 01:34:00.832979 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1432 01:34:00.844226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1433 01:34:00.849748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1434 01:34:00.860991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1435 01:34:00.872141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1436 01:34:00.883298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1437 01:34:00.894421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1438 01:34:00.900180 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1439 01:34:00.911264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1440 01:34:00.922493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1441 01:34:00.933662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1442 01:34:00.944873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1443 01:34:00.956144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1444 01:34:00.967284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1445 01:34:00.978421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1446 01:34:00.989632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1447 01:34:01.000787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1448 01:34:01.011962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1449 01:34:01.023145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1450 01:34:01.034377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1451 01:34:01.045589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1452 01:34:01.056773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1453 01:34:01.068032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1454 01:34:01.079143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1455 01:34:01.090313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1456 01:34:01.101477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1457 01:34:01.112635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1458 01:34:01.123851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1459 01:34:01.135145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1460 01:34:01.146271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1461 01:34:01.157485 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1462 01:34:01.168597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1463 01:34:01.179866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1464 01:34:01.185473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1465 01:34:01.196649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1466 01:34:01.207808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1467 01:34:01.219041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1468 01:34:01.230216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1469 01:34:01.241468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1470 01:34:01.252587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1471 01:34:01.263789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1472 01:34:01.275043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1473 01:34:01.286138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1474 01:34:01.297370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1475 01:34:01.308580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1476 01:34:01.319768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1477 01:34:01.330933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1478 01:34:01.342254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1479 01:34:01.353351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1480 01:34:01.364525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1481 01:34:01.375813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1482 01:34:01.381314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1483 01:34:01.392535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1484 01:34:01.403729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1485 01:34:01.414956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1486 01:34:01.426203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1487 01:34:01.431713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1488 01:34:01.448563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1489 01:34:01.459764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1490 01:34:01.465361 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1491 01:34:01.482204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1492 01:34:01.493340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1493 01:34:01.504584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1494 01:34:01.510197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1495 01:34:01.521367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1496 01:34:01.532557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1497 01:34:01.538203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1498 01:34:01.549383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1499 01:34:01.560573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1500 01:34:01.566187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1501 01:34:01.577387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1502 01:34:01.583049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1503 01:34:01.594270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1504 01:34:01.605396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1505 01:34:01.616590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1506 01:34:01.627779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1507 01:34:01.638961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1508 01:34:01.650272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1509 01:34:01.661398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1510 01:34:01.672550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1511 01:34:01.683739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1512 01:34:01.694891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1513 01:34:01.706073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1514 01:34:01.717306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1515 01:34:01.734087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1516 01:34:01.745296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1517 01:34:01.756450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1518 01:34:01.767672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1519 01:34:01.778884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1520 01:34:01.795579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1521 01:34:01.806850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1522 01:34:01.818117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1523 01:34:01.829321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1524 01:34:01.834880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1525 01:34:01.846097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1526 01:34:01.857315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1527 01:34:01.862842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1528 01:34:01.874005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1529 01:34:01.879636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1530 01:34:01.890732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1531 01:34:01.896473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1532 01:34:01.907578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1533 01:34:01.913070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1534 01:34:01.924361 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1535 01:34:01.930025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1536 01:34:01.941142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1537 01:34:01.952367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1538 01:34:01.963552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1539 01:34:01.974736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1540 01:34:01.985906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1541 01:34:01.991478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1542 01:34:02.002740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1543 01:34:02.008347 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1544 01:34:02.013989 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1545 01:34:02.019557 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1546 01:34:02.025125 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1547 01:34:02.030639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1548 01:34:02.041867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1549 01:34:02.047570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1550 01:34:02.053124 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1551 01:34:02.064321 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1552 01:34:02.069901 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1553 01:34:02.081055 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1554 01:34:02.086673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1555 01:34:02.097830 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1556 01:34:02.103511 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1557 01:34:02.114627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1558 01:34:02.120367 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1559 01:34:02.131402 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1560 01:34:02.137118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1561 01:34:02.148296 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1562 01:34:02.153810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1563 01:34:02.164995 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1564 01:34:02.170590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1565 01:34:02.176263 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1566 01:34:02.187317 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1567 01:34:02.193013 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1568 01:34:02.204236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1569 01:34:02.209808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1570 01:34:02.220956 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1571 01:34:02.226591 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1572 01:34:02.237749 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1573 01:34:02.243395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1574 01:34:02.249055 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1575 01:34:02.260247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1576 01:34:02.265824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1577 01:34:02.276907 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1578 01:34:02.288106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1579 01:34:02.299339 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1580 01:34:02.310483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1581 01:34:02.321623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1582 01:34:02.332824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1583 01:34:02.344112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1584 01:34:02.355236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1585 01:34:02.360899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1586 01:34:02.372022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1587 01:34:02.377628 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1588 01:34:02.388795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1589 01:34:02.394421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1590 01:34:02.405599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1591 01:34:02.411250 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1592 01:34:02.422358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1593 01:34:02.427959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1594 01:34:02.439179 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1595 01:34:02.444783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1596 01:34:02.455920 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1597 01:34:02.461561 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1598 01:34:02.472728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1599 01:34:02.478416 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1600 01:34:02.483904 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1601 01:34:02.495071 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1602 01:34:02.500802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1603 01:34:02.511950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1604 01:34:02.517604 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1605 01:34:02.528752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1606 01:34:02.534412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1607 01:34:02.545571 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1608 01:34:02.551278 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1609 01:34:02.556945 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1610 01:34:02.562430 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1611 01:34:02.573654 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1612 01:34:02.584856 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1613 01:34:02.590507 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1614 01:34:02.596160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1615 01:34:02.607403 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1616 01:34:02.618541 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1617 01:34:02.629746 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1618 01:34:02.640957 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1619 01:34:02.646748 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1620 01:34:02.652364 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1621 01:34:02.657888 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1622 01:34:02.663516 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1623 01:34:02.669084 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1624 01:34:02.674745 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1625 01:34:02.685848 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1626 01:34:02.691476 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1627 01:34:02.697035 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1628 01:34:02.702657 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1629 01:34:02.708330 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1630 01:34:02.719458 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1631 01:34:02.725094 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1632 01:34:02.730653 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1633 01:34:02.736277 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1634 01:34:02.741886 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1635 01:34:02.747508 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1636 01:34:02.753099 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1637 01:34:02.758667 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1638 01:34:02.764299 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1639 01:34:02.769853 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1640 01:34:02.775467 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1641 01:34:02.781070 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1642 01:34:02.786662 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1643 01:34:02.792284 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1644 01:34:02.797878 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1645 01:34:02.803471 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1646 01:34:02.809061 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1647 01:34:02.814744 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1648 01:34:02.820329 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1649 01:34:02.825899 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1650 01:34:02.831519 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1651 01:34:02.831972 dt_test_unprobed_devices_sh_opp-table skip
1652 01:34:02.837106 dt_test_unprobed_devices_sh_soc skip
1653 01:34:02.842700 dt_test_unprobed_devices_sh_sound pass
1654 01:34:02.848386 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1655 01:34:02.853919 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1656 01:34:02.859513 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1657 01:34:02.865120 dt_test_unprobed_devices_sh fail
1658 01:34:02.865572 + ../../utils/send-to-lava.sh ./output/result.txt
1659 01:34:02.870739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1660 01:34:02.871581 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1662 01:34:02.879778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1663 01:34:02.880547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1665 01:34:02.958642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1666 01:34:02.959444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1668 01:34:03.047877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1669 01:34:03.048760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1671 01:34:03.131202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1672 01:34:03.132009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1674 01:34:03.215865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1675 01:34:03.216786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1677 01:34:03.298948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1678 01:34:03.299826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1680 01:34:03.387025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1681 01:34:03.387861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1683 01:34:03.479658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1684 01:34:03.480538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1686 01:34:03.572270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1687 01:34:03.573273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1689 01:34:03.658018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1690 01:34:03.658934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1692 01:34:03.743196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1693 01:34:03.744035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1695 01:34:03.829214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1696 01:34:03.830024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1698 01:34:03.915083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1699 01:34:03.915884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1701 01:34:03.997918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1702 01:34:03.998800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1704 01:34:04.083864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1705 01:34:04.084741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1707 01:34:04.175388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1708 01:34:04.176228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1710 01:34:04.265779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1711 01:34:04.266637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1713 01:34:04.356610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1714 01:34:04.357458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1716 01:34:04.446199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1717 01:34:04.447044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1719 01:34:04.530768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1720 01:34:04.531634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1722 01:34:04.620843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1723 01:34:04.621691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1725 01:34:04.711767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1726 01:34:04.712657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1728 01:34:04.795792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1729 01:34:04.796687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1731 01:34:04.880558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1732 01:34:04.881394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1734 01:34:04.965623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1735 01:34:04.966493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1737 01:34:05.055929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1738 01:34:05.056808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1740 01:34:05.145844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1741 01:34:05.146685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1743 01:34:05.237859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1744 01:34:05.238706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1746 01:34:05.327401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1747 01:34:05.328287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1749 01:34:05.410753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1750 01:34:05.411597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1752 01:34:05.497422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1753 01:34:05.498266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1755 01:34:05.584916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1756 01:34:05.585767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1758 01:34:05.670422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1759 01:34:05.671281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1761 01:34:05.753455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1762 01:34:05.754328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1764 01:34:05.839077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1765 01:34:05.839893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1767 01:34:05.924379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1768 01:34:05.925245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1770 01:34:06.015816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1771 01:34:06.016726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1773 01:34:06.106076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1774 01:34:06.106919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1776 01:34:06.197794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1777 01:34:06.198638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1779 01:34:06.281473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1780 01:34:06.282334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1782 01:34:06.366987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1783 01:34:06.367834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1785 01:34:06.452986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1786 01:34:06.453823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1788 01:34:06.543273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1789 01:34:06.544105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1791 01:34:06.633385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1792 01:34:06.634224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1794 01:34:06.717860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1795 01:34:06.718698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1797 01:34:06.803433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1798 01:34:06.804382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1800 01:34:06.887770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1801 01:34:06.888751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1803 01:34:06.977279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1804 01:34:06.978178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1806 01:34:07.066252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1807 01:34:07.067142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1809 01:34:07.149506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1810 01:34:07.150331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1812 01:34:07.234265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1813 01:34:07.235083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1815 01:34:07.322368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1816 01:34:07.323193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1818 01:34:07.413279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1819 01:34:07.414107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1821 01:34:07.504243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1822 01:34:07.505096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1824 01:34:07.587416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1825 01:34:07.588240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1827 01:34:07.673116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1828 01:34:07.673940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1830 01:34:07.757834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1831 01:34:07.758657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1833 01:34:07.841664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1834 01:34:07.842476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1836 01:34:07.927553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1837 01:34:07.928418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1839 01:34:08.017440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1840 01:34:08.018275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1842 01:34:08.102497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1843 01:34:08.103303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1845 01:34:08.192370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1846 01:34:08.193191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1848 01:34:08.276969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1849 01:34:08.277796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1851 01:34:08.366997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1852 01:34:08.367806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1854 01:34:08.450504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1855 01:34:08.451312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1857 01:34:08.541585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1858 01:34:08.542390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1860 01:34:08.633135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1861 01:34:08.633938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1863 01:34:08.717560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1864 01:34:08.718402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1866 01:34:08.802581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1867 01:34:08.803397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1869 01:34:08.888589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1870 01:34:08.889402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1872 01:34:08.978505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1873 01:34:08.979343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1875 01:34:09.063228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1876 01:34:09.064062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1878 01:34:09.153558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1879 01:34:09.154393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1881 01:34:09.239079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1882 01:34:09.239881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1884 01:34:09.323919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1885 01:34:09.324770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1887 01:34:09.408736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1888 01:34:09.409549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1890 01:34:09.498902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1891 01:34:09.499704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1893 01:34:09.582835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1894 01:34:09.583644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1896 01:34:09.673180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1897 01:34:09.673994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1899 01:34:09.758169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1900 01:34:09.758981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1902 01:34:09.842698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1903 01:34:09.843502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1905 01:34:09.927473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1906 01:34:09.928353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1908 01:34:10.016805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1909 01:34:10.017634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1911 01:34:10.101851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1912 01:34:10.102662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1914 01:34:10.191741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1915 01:34:10.192585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1917 01:34:10.276784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1918 01:34:10.277592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1920 01:34:10.361485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1921 01:34:10.362292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1923 01:34:10.446555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1924 01:34:10.447357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1926 01:34:10.532449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1927 01:34:10.533259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1929 01:34:10.618003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1930 01:34:10.618822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1932 01:34:10.700632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1933 01:34:10.701455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1935 01:34:10.787478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1936 01:34:10.788368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1938 01:34:10.871614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1939 01:34:10.872476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1941 01:34:10.964323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1942 01:34:10.965151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1944 01:34:11.052224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1945 01:34:11.053064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1947 01:34:11.136529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1948 01:34:11.137333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1950 01:34:11.221167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1951 01:34:11.221974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1953 01:34:11.305259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1954 01:34:11.306116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1956 01:34:11.389432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1957 01:34:11.390284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1959 01:34:11.474758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1960 01:34:11.475595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1962 01:34:11.564338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1963 01:34:11.565148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1965 01:34:11.653939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1966 01:34:11.654752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1968 01:34:11.738398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1969 01:34:11.739204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1971 01:34:11.824108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1972 01:34:11.824912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1974 01:34:11.910261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1975 01:34:11.911067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1977 01:34:11.995022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1978 01:34:11.995849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1980 01:34:12.085215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1981 01:34:12.086028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1983 01:34:12.178239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1984 01:34:12.179052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1986 01:34:12.262504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1987 01:34:12.263309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1989 01:34:12.347643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1990 01:34:12.348485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1992 01:34:12.432371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1993 01:34:12.433186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1995 01:34:12.517580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1996 01:34:12.518388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1998 01:34:12.600878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1999 01:34:12.601676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2001 01:34:12.686405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2002 01:34:12.687203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2004 01:34:12.771713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2005 01:34:12.772569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2007 01:34:12.857060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2008 01:34:12.857869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2010 01:34:12.947911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2011 01:34:12.948768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2013 01:34:13.037699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2014 01:34:13.038514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2016 01:34:13.120275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2017 01:34:13.121080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2019 01:34:13.204974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2021 01:34:13.208236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2022 01:34:13.296839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2024 01:34:13.300117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2025 01:34:13.386512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2027 01:34:13.389664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2028 01:34:13.472435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2029 01:34:13.473237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2031 01:34:13.562155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2032 01:34:13.562964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2034 01:34:13.644713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2035 01:34:13.645520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2037 01:34:13.730232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2038 01:34:13.731036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2040 01:34:13.816622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2041 01:34:13.817434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2043 01:34:13.905344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2044 01:34:13.906152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2046 01:34:13.995595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2047 01:34:13.996460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2049 01:34:14.080936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2050 01:34:14.081751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2052 01:34:14.172866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2053 01:34:14.173665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2055 01:34:14.263896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2056 01:34:14.264752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2058 01:34:14.347596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2059 01:34:14.348435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2061 01:34:14.438578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2062 01:34:14.439378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2064 01:34:14.528331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2065 01:34:14.529136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2067 01:34:14.614462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2068 01:34:14.615256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2070 01:34:14.708632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2071 01:34:14.709431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2073 01:34:14.803646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2074 01:34:14.804503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2076 01:34:14.892437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2077 01:34:14.893242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2079 01:34:14.976966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2080 01:34:14.978029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2082 01:34:15.068772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2083 01:34:15.069695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2085 01:34:15.153873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2086 01:34:15.154685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2088 01:34:15.241874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2089 01:34:15.242682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2091 01:34:15.323454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2092 01:34:15.324319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2094 01:34:15.413171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2095 01:34:15.413964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2097 01:34:15.497177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2098 01:34:15.497975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2100 01:34:15.590433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2101 01:34:15.591230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2103 01:34:15.676781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2104 01:34:15.677592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2106 01:34:15.767022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2107 01:34:15.767848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2109 01:34:15.857030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2110 01:34:15.857870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2112 01:34:15.940610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2113 01:34:15.941460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2115 01:34:16.025853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2116 01:34:16.026700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2118 01:34:16.110798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2119 01:34:16.111608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2121 01:34:16.195033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2122 01:34:16.195838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2124 01:34:16.279501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2125 01:34:16.280334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2127 01:34:16.365036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2128 01:34:16.365835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2130 01:34:16.448685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2131 01:34:16.449475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2133 01:34:16.534952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2134 01:34:16.535756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2136 01:34:16.618499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2137 01:34:16.619289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2139 01:34:16.703583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2140 01:34:16.704421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2142 01:34:16.793818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2143 01:34:16.794619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2145 01:34:16.883605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2146 01:34:16.884451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2148 01:34:16.973924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2149 01:34:16.974742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2151 01:34:17.064310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2152 01:34:17.065103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2154 01:34:17.147492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2155 01:34:17.148330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2157 01:34:17.237571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2158 01:34:17.238364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2160 01:34:17.322141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2161 01:34:17.322948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2163 01:34:17.407199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2164 01:34:17.408024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2166 01:34:17.491496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2167 01:34:17.492334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2169 01:34:17.576985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2170 01:34:17.577777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2172 01:34:17.660044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2173 01:34:17.660839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2175 01:34:17.745591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2176 01:34:17.746399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2178 01:34:17.828083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2179 01:34:17.828882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2181 01:34:17.915617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2182 01:34:17.916461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2184 01:34:17.997284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2185 01:34:17.998101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2187 01:34:18.083579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2188 01:34:18.084433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2190 01:34:18.169288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2191 01:34:18.170084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2193 01:34:18.255364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2194 01:34:18.256168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2196 01:34:18.347395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2197 01:34:18.348204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2199 01:34:18.436124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2200 01:34:18.436916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2202 01:34:18.526059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2203 01:34:18.526862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2205 01:34:18.615347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2206 01:34:18.616139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2208 01:34:18.700873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2209 01:34:18.701667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2211 01:34:18.784235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2212 01:34:18.785039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2214 01:34:18.870050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2215 01:34:18.870846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2217 01:34:18.956769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2218 01:34:18.957589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2220 01:34:19.046768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2221 01:34:19.047566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2223 01:34:19.131641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2224 01:34:19.132459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2226 01:34:19.222184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2227 01:34:19.222985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2229 01:34:19.306660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2230 01:34:19.307481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2232 01:34:19.400828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2233 01:34:19.401649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2235 01:34:19.484897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2236 01:34:19.485697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2238 01:34:19.570231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2239 01:34:19.571024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2241 01:34:19.654703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2242 01:34:19.655500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2244 01:34:19.744548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2245 01:34:19.745349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2247 01:34:19.828197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2248 01:34:19.828988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2250 01:34:19.919549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2251 01:34:19.920388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2253 01:34:20.000650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2254 01:34:20.001459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2256 01:34:20.087494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2257 01:34:20.088338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2259 01:34:20.172493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2260 01:34:20.173283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2262 01:34:20.253379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2263 01:34:20.254180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2265 01:34:20.345511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2266 01:34:20.346301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2268 01:34:20.429834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2269 01:34:20.430634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2271 01:34:20.520194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2272 01:34:20.521002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2274 01:34:20.604030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2275 01:34:20.604835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2277 01:34:20.688343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2278 01:34:20.689166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2280 01:34:20.773381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2281 01:34:20.774196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2283 01:34:20.858668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2284 01:34:20.859491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2286 01:34:20.939180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2287 01:34:20.939976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2289 01:34:21.024268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2290 01:34:21.025055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2292 01:34:21.117342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2293 01:34:21.118142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2295 01:34:21.207544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2296 01:34:21.208400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2298 01:34:21.292448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2299 01:34:21.293271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2301 01:34:21.380565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2302 01:34:21.381394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2304 01:34:21.465360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2305 01:34:21.466165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2307 01:34:21.550591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2308 01:34:21.551389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2310 01:34:21.636412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2311 01:34:21.637207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2313 01:34:21.937125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2314 01:34:21.937960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2316 01:34:21.939423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2317 01:34:21.940175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2319 01:34:21.941678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2320 01:34:21.942506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2322 01:34:21.968343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2323 01:34:21.969145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2325 01:34:22.053517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2326 01:34:22.054318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2328 01:34:22.142422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2329 01:34:22.143217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2331 01:34:22.225834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2332 01:34:22.226623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2334 01:34:22.316082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2335 01:34:22.316867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2337 01:34:22.401393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2338 01:34:22.402175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2340 01:34:22.482744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2342 01:34:22.485887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2343 01:34:22.566743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2344 01:34:22.567541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2346 01:34:22.652907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2347 01:34:22.653696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2349 01:34:22.736316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2350 01:34:22.737111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2352 01:34:22.819764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2353 01:34:22.820598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2355 01:34:22.903506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2356 01:34:22.904319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2358 01:34:22.987599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2359 01:34:22.988441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2361 01:34:23.070493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2362 01:34:23.071281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2364 01:34:23.154833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2365 01:34:23.155620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2367 01:34:23.245053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2368 01:34:23.245848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2370 01:34:23.334470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2371 01:34:23.335269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2373 01:34:23.419248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2374 01:34:23.420059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2376 01:34:23.503591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2377 01:34:23.504424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2379 01:34:23.588979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2380 01:34:23.589761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2382 01:34:23.673607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2383 01:34:23.674399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2385 01:34:23.758619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2386 01:34:23.759428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2388 01:34:23.842422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2389 01:34:23.843207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2391 01:34:23.932291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2392 01:34:23.933142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2394 01:34:24.021132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2395 01:34:24.021949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2397 01:34:24.112552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2398 01:34:24.113354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2400 01:34:24.197166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2401 01:34:24.197960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2403 01:34:24.280802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2404 01:34:24.281596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2406 01:34:24.365590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2407 01:34:24.366374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2409 01:34:24.454821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2410 01:34:24.455604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2412 01:34:24.544516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2413 01:34:24.545307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2415 01:34:24.625840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2416 01:34:24.626625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2418 01:34:24.710006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2419 01:34:24.710799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2421 01:34:24.794367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2422 01:34:24.795158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2424 01:34:24.880074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2425 01:34:24.880869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2427 01:34:24.966163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2428 01:34:24.966980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2430 01:34:25.051380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2431 01:34:25.052178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2433 01:34:25.132041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2434 01:34:25.132581 + set +x
2435 01:34:25.133300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2437 01:34:25.141420 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 915610_1.6.2.4.5>
2438 01:34:25.141941 <LAVA_TEST_RUNNER EXIT>
2439 01:34:25.142648 Received signal: <ENDRUN> 1_kselftest-dt 915610_1.6.2.4.5
2440 01:34:25.143142 Ending use of test pattern.
2441 01:34:25.143591 Ending test lava.1_kselftest-dt (915610_1.6.2.4.5), duration 82.60
2443 01:34:25.145461 ok: lava_test_shell seems to have completed
2444 01:34:25.159569 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2445 01:34:25.161662 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2446 01:34:25.162300 end: 3 lava-test-retry (duration 00:01:24) [common]
2447 01:34:25.162932 start: 4 finalize (timeout 00:05:03) [common]
2448 01:34:25.163554 start: 4.1 power-off (timeout 00:00:30) [common]
2449 01:34:25.164660 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2450 01:34:25.201076 >> OK - accepted request
2451 01:34:25.203497 Returned 0 in 0 seconds
2452 01:34:25.304881 end: 4.1 power-off (duration 00:00:00) [common]
2454 01:34:25.306899 start: 4.2 read-feedback (timeout 00:05:03) [common]
2455 01:34:25.307674 Listened to connection for namespace 'common' for up to 1s
2456 01:34:25.308524 Listened to connection for namespace 'common' for up to 1s
2457 01:34:26.308723 Finalising connection for namespace 'common'
2458 01:34:26.309505 Disconnecting from shell: Finalise
2459 01:34:26.310116 / #
2460 01:34:26.411228 end: 4.2 read-feedback (duration 00:00:01) [common]
2461 01:34:26.412042 end: 4 finalize (duration 00:00:01) [common]
2462 01:34:26.412744 Cleaning after the job
2463 01:34:26.413390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/ramdisk
2464 01:34:26.424131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/kernel
2465 01:34:26.433138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/dtb
2466 01:34:26.436323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/nfsrootfs
2467 01:34:26.600070 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915610/tftp-deploy-wdz2iw73/modules
2468 01:34:26.610215 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915610
2469 01:34:29.527937 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915610
2470 01:34:29.528541 Job finished correctly