Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:16:25.688350 lava-dispatcher, installed at version: 2024.01
2 00:16:25.689147 start: 0 validate
3 00:16:25.689606 Start time: 2024-10-31 00:16:25.689575+00:00 (UTC)
4 00:16:25.690173 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:16:25.690704 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:16:25.730412 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:16:25.730962 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 00:16:25.764604 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:16:25.765222 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 00:16:26.818806 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:16:26.819333 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 00:16:26.867035 validate duration: 1.18
14 00:16:26.868046 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:16:26.868414 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:16:26.868734 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:16:26.869613 Not decompressing ramdisk as can be used compressed.
18 00:16:26.870465 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:16:26.871013 saving as /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/ramdisk/rootfs.cpio.gz
20 00:16:26.871343 total size: 8181887 (7 MB)
21 00:16:26.907125 progress 0 % (0 MB)
22 00:16:26.912826 progress 5 % (0 MB)
23 00:16:26.918272 progress 10 % (0 MB)
24 00:16:26.924058 progress 15 % (1 MB)
25 00:16:26.929308 progress 20 % (1 MB)
26 00:16:26.934923 progress 25 % (1 MB)
27 00:16:26.940124 progress 30 % (2 MB)
28 00:16:26.945765 progress 35 % (2 MB)
29 00:16:26.950967 progress 40 % (3 MB)
30 00:16:26.956546 progress 45 % (3 MB)
31 00:16:26.961744 progress 50 % (3 MB)
32 00:16:26.967395 progress 55 % (4 MB)
33 00:16:26.972620 progress 60 % (4 MB)
34 00:16:26.978202 progress 65 % (5 MB)
35 00:16:26.983386 progress 70 % (5 MB)
36 00:16:26.989012 progress 75 % (5 MB)
37 00:16:26.994249 progress 80 % (6 MB)
38 00:16:26.999853 progress 85 % (6 MB)
39 00:16:27.005073 progress 90 % (7 MB)
40 00:16:27.010431 progress 95 % (7 MB)
41 00:16:27.015267 progress 100 % (7 MB)
42 00:16:27.015926 7 MB downloaded in 0.14 s (53.98 MB/s)
43 00:16:27.016540 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:16:27.017459 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:16:27.017765 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:16:27.018045 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:16:27.018540 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 00:16:27.018793 saving as /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/kernel/Image
50 00:16:27.019012 total size: 65665536 (62 MB)
51 00:16:27.019343 No compression specified
52 00:16:27.057466 progress 0 % (0 MB)
53 00:16:27.107089 progress 5 % (3 MB)
54 00:16:27.154611 progress 10 % (6 MB)
55 00:16:27.196003 progress 15 % (9 MB)
56 00:16:27.237254 progress 20 % (12 MB)
57 00:16:27.277544 progress 25 % (15 MB)
58 00:16:27.318133 progress 30 % (18 MB)
59 00:16:27.357905 progress 35 % (21 MB)
60 00:16:27.398203 progress 40 % (25 MB)
61 00:16:27.438020 progress 45 % (28 MB)
62 00:16:27.477840 progress 50 % (31 MB)
63 00:16:27.518727 progress 55 % (34 MB)
64 00:16:27.558285 progress 60 % (37 MB)
65 00:16:27.598361 progress 65 % (40 MB)
66 00:16:27.638637 progress 70 % (43 MB)
67 00:16:27.679263 progress 75 % (46 MB)
68 00:16:27.720331 progress 80 % (50 MB)
69 00:16:27.760829 progress 85 % (53 MB)
70 00:16:27.801492 progress 90 % (56 MB)
71 00:16:27.842407 progress 95 % (59 MB)
72 00:16:27.882594 progress 100 % (62 MB)
73 00:16:27.883363 62 MB downloaded in 0.86 s (72.45 MB/s)
74 00:16:27.883848 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:16:27.884692 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:16:27.884968 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:16:27.885228 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:16:27.885726 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 00:16:27.886002 saving as /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 00:16:27.886207 total size: 53209 (0 MB)
82 00:16:27.886417 No compression specified
83 00:16:27.931971 progress 61 % (0 MB)
84 00:16:27.932864 progress 100 % (0 MB)
85 00:16:27.933409 0 MB downloaded in 0.05 s (1.08 MB/s)
86 00:16:27.933872 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:16:27.934709 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:16:27.934989 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:16:27.935258 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:16:27.935734 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 00:16:27.935975 saving as /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/modules/modules.tar
93 00:16:27.936214 total size: 16414716 (15 MB)
94 00:16:27.936427 Using unxz to decompress xz
95 00:16:27.972804 progress 0 % (0 MB)
96 00:16:28.078193 progress 5 % (0 MB)
97 00:16:28.195229 progress 10 % (1 MB)
98 00:16:28.307178 progress 15 % (2 MB)
99 00:16:28.420765 progress 20 % (3 MB)
100 00:16:28.529917 progress 25 % (3 MB)
101 00:16:28.646557 progress 30 % (4 MB)
102 00:16:28.758189 progress 35 % (5 MB)
103 00:16:28.871433 progress 40 % (6 MB)
104 00:16:28.988433 progress 45 % (7 MB)
105 00:16:29.102093 progress 50 % (7 MB)
106 00:16:29.216554 progress 55 % (8 MB)
107 00:16:29.330757 progress 60 % (9 MB)
108 00:16:29.446960 progress 65 % (10 MB)
109 00:16:29.562659 progress 70 % (10 MB)
110 00:16:29.678881 progress 75 % (11 MB)
111 00:16:29.795618 progress 80 % (12 MB)
112 00:16:29.928470 progress 85 % (13 MB)
113 00:16:30.038926 progress 90 % (14 MB)
114 00:16:30.171025 progress 95 % (14 MB)
115 00:16:30.301831 progress 100 % (15 MB)
116 00:16:30.317857 15 MB downloaded in 2.38 s (6.57 MB/s)
117 00:16:30.318465 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:16:30.319279 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:16:30.319549 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 00:16:30.319814 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 00:16:30.320354 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:16:30.321049 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 00:16:30.322216 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m
125 00:16:30.323209 makedir: /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin
126 00:16:30.323940 makedir: /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/tests
127 00:16:30.324882 makedir: /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/results
128 00:16:30.325595 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-add-keys
129 00:16:30.326653 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-add-sources
130 00:16:30.327805 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-background-process-start
131 00:16:30.328926 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-background-process-stop
132 00:16:30.330021 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-common-functions
133 00:16:30.331026 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-echo-ipv4
134 00:16:30.332058 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-install-packages
135 00:16:30.333064 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-installed-packages
136 00:16:30.334072 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-os-build
137 00:16:30.335122 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-probe-channel
138 00:16:30.336169 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-probe-ip
139 00:16:30.337174 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-target-ip
140 00:16:30.338164 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-target-mac
141 00:16:30.339132 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-target-storage
142 00:16:30.340159 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-case
143 00:16:30.341158 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-event
144 00:16:30.342124 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-feedback
145 00:16:30.343103 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-raise
146 00:16:30.344113 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-reference
147 00:16:30.345146 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-runner
148 00:16:30.346183 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-set
149 00:16:30.347157 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-test-shell
150 00:16:30.348174 Updating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-install-packages (oe)
151 00:16:30.349248 Updating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/bin/lava-installed-packages (oe)
152 00:16:30.350155 Creating /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/environment
153 00:16:30.350938 LAVA metadata
154 00:16:30.351483 - LAVA_JOB_ID=915391
155 00:16:30.351956 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:16:30.352728 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:16:30.354746 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:16:30.355427 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:16:30.355884 skipped lava-vland-overlay
160 00:16:30.356490 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:16:30.357002 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:16:30.357446 skipped lava-multinode-overlay
163 00:16:30.357929 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:16:30.358426 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:16:30.358903 Loading test definitions
166 00:16:30.359451 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:16:30.359888 Using /lava-915391 at stage 0
168 00:16:30.362145 uuid=915391_1.5.2.4.1 testdef=None
169 00:16:30.362749 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:16:30.363267 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:16:30.365522 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:16:30.366368 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:16:30.368672 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:16:30.369531 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 00:16:30.371722 runner path: /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/0/tests/0_dmesg test_uuid 915391_1.5.2.4.1
178 00:16:30.372339 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:16:30.373142 Creating lava-test-runner.conf files
181 00:16:30.373347 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915391/lava-overlay-ji_kjx_m/lava-915391/0 for stage 0
182 00:16:30.373672 - 0_dmesg
183 00:16:30.374034 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:16:30.374343 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 00:16:30.398255 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:16:30.398686 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 00:16:30.398957 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:16:30.399226 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:16:30.399491 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 00:16:31.323607 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 00:16:31.324133 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 00:16:31.324608 extracting modules file /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk
193 00:16:32.852856 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 00:16:32.853332 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 00:16:32.853605 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915391/compress-overlay-q1y1wj3r/overlay-1.5.2.5.tar.gz to ramdisk
196 00:16:32.853818 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915391/compress-overlay-q1y1wj3r/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk
197 00:16:32.883782 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:16:32.884220 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 00:16:32.884495 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 00:16:32.884727 Converting downloaded kernel to a uImage
201 00:16:32.885030 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/kernel/Image /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/kernel/uImage
202 00:16:33.587774 output: Image Name:
203 00:16:33.588208 output: Created: Thu Oct 31 00:16:32 2024
204 00:16:33.588417 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:16:33.588620 output: Data Size: 65665536 Bytes = 64126.50 KiB = 62.62 MiB
206 00:16:33.588820 output: Load Address: 01080000
207 00:16:33.589016 output: Entry Point: 01080000
208 00:16:33.589211 output:
209 00:16:33.589538 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 00:16:33.589800 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 00:16:33.590068 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 00:16:33.590320 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:16:33.590588 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 00:16:33.590876 Building ramdisk /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk
215 00:16:36.921119 >> 257680 blocks
216 00:16:48.028415 Adding RAMdisk u-boot header.
217 00:16:48.029153 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk.cpio.gz.uboot
218 00:16:48.440484 output: Image Name:
219 00:16:48.441122 output: Created: Thu Oct 31 00:16:48 2024
220 00:16:48.441585 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:16:48.442034 output: Data Size: 34071917 Bytes = 33273.36 KiB = 32.49 MiB
222 00:16:48.442480 output: Load Address: 00000000
223 00:16:48.442921 output: Entry Point: 00000000
224 00:16:48.443357 output:
225 00:16:48.444565 rename /var/lib/lava/dispatcher/tmp/915391/extract-overlay-ramdisk-b56f9voj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot
226 00:16:48.445361 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 00:16:48.445965 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 00:16:48.446601 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 00:16:48.447111 No LXC device requested
230 00:16:48.447673 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:16:48.448277 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 00:16:48.448835 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:16:48.449296 Checking files for TFTP limit of 4294967296 bytes.
234 00:16:48.452234 end: 1 tftp-deploy (duration 00:00:22) [common]
235 00:16:48.452861 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:16:48.453448 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:16:48.454008 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:16:48.454569 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:16:48.455155 Using kernel file from prepare-kernel: 915391/tftp-deploy-ld3nrofe/kernel/uImage
240 00:16:48.455828 substitutions:
241 00:16:48.456324 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:16:48.456778 - {DTB_ADDR}: 0x01070000
243 00:16:48.457224 - {DTB}: 915391/tftp-deploy-ld3nrofe/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 00:16:48.457669 - {INITRD}: 915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot
245 00:16:48.458111 - {KERNEL_ADDR}: 0x01080000
246 00:16:48.458547 - {KERNEL}: 915391/tftp-deploy-ld3nrofe/kernel/uImage
247 00:16:48.458986 - {LAVA_MAC}: None
248 00:16:48.459472 - {PRESEED_CONFIG}: None
249 00:16:48.459913 - {PRESEED_LOCAL}: None
250 00:16:48.460380 - {RAMDISK_ADDR}: 0x08000000
251 00:16:48.460812 - {RAMDISK}: 915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot
252 00:16:48.461249 - {ROOT_PART}: None
253 00:16:48.461682 - {ROOT}: None
254 00:16:48.462110 - {SERVER_IP}: 192.168.6.2
255 00:16:48.462546 - {TEE_ADDR}: 0x83000000
256 00:16:48.462978 - {TEE}: None
257 00:16:48.463407 Parsed boot commands:
258 00:16:48.463822 - setenv autoload no
259 00:16:48.464285 - setenv initrd_high 0xffffffff
260 00:16:48.464719 - setenv fdt_high 0xffffffff
261 00:16:48.465148 - dhcp
262 00:16:48.465578 - setenv serverip 192.168.6.2
263 00:16:48.466006 - tftpboot 0x01080000 915391/tftp-deploy-ld3nrofe/kernel/uImage
264 00:16:48.466441 - tftpboot 0x08000000 915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot
265 00:16:48.466873 - tftpboot 0x01070000 915391/tftp-deploy-ld3nrofe/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 00:16:48.467304 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:16:48.467742 - bootm 0x01080000 0x08000000 0x01070000
268 00:16:48.468360 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:16:48.470004 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:16:48.470496 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 00:16:48.487135 Setting prompt string to ['lava-test: # ']
273 00:16:48.488752 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:16:48.489426 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:16:48.490593 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:16:48.490990 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:16:48.491658 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 00:16:48.523335 >> OK - accepted request
279 00:16:48.525406 Returned 0 in 0 seconds
280 00:16:48.626256 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:16:48.627289 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:16:48.627641 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:16:48.627957 Setting prompt string to ['Hit any key to stop autoboot']
285 00:16:48.628280 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:16:48.629246 Trying 192.168.56.21...
287 00:16:48.629558 Connected to conserv1.
288 00:16:48.629793 Escape character is '^]'.
289 00:16:48.630023
290 00:16:48.630257 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 00:16:48.630499
292 00:16:56.049317 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 00:16:56.049809 bl2_stage_init 0x01
294 00:16:56.050090 bl2_stage_init 0x81
295 00:16:56.054759 hw id: 0x0000 - pwm id 0x01
296 00:16:56.055341 bl2_stage_init 0xc1
297 00:16:56.060228 bl2_stage_init 0x02
298 00:16:56.060830
299 00:16:56.061234 L0:00000000
300 00:16:56.061524 L1:00000703
301 00:16:56.061752 L2:00008067
302 00:16:56.061977 L3:15000000
303 00:16:56.065762 S1:00000000
304 00:16:56.066310 B2:20282000
305 00:16:56.066715 B1:a0f83180
306 00:16:56.067090
307 00:16:56.067462 TE: 70516
308 00:16:56.067848
309 00:16:56.071342 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 00:16:56.071732
311 00:16:56.077129 Board ID = 1
312 00:16:56.077547 Set cpu clk to 24M
313 00:16:56.077793 Set clk81 to 24M
314 00:16:56.080428 Use GP1_pll as DSU clk.
315 00:16:56.080800 DSU clk: 1200 Mhz
316 00:16:56.086096 CPU clk: 1200 MHz
317 00:16:56.086514 Set clk81 to 166.6M
318 00:16:56.091580 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 00:16:56.092015 board id: 1
320 00:16:56.101125 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 00:16:56.111749 fw parse done
322 00:16:56.117718 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 00:16:56.160343 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 00:16:56.171272 PIEI prepare done
325 00:16:56.171738 fastboot data load
326 00:16:56.172209 fastboot data verify
327 00:16:56.176786 verify result: 266
328 00:16:56.182346 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 00:16:56.182790 LPDDR4 probe
330 00:16:56.183209 ddr clk to 1584MHz
331 00:16:56.190382 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 00:16:56.227613
333 00:16:56.228152 dmc_version 0001
334 00:16:56.234359 Check phy result
335 00:16:56.240283 INFO : End of CA training
336 00:16:56.240724 INFO : End of initialization
337 00:16:56.245767 INFO : Training has run successfully!
338 00:16:56.246200 Check phy result
339 00:16:56.251406 INFO : End of initialization
340 00:16:56.251835 INFO : End of read enable training
341 00:16:56.256974 INFO : End of fine write leveling
342 00:16:56.262591 INFO : End of Write leveling coarse delay
343 00:16:56.263019 INFO : Training has run successfully!
344 00:16:56.263412 Check phy result
345 00:16:56.268409 INFO : End of initialization
346 00:16:56.268845 INFO : End of read dq deskew training
347 00:16:56.273791 INFO : End of MPR read delay center optimization
348 00:16:56.279412 INFO : End of write delay center optimization
349 00:16:56.285002 INFO : End of read delay center optimization
350 00:16:56.285435 INFO : End of max read latency training
351 00:16:56.290634 INFO : Training has run successfully!
352 00:16:56.291060 1D training succeed
353 00:16:56.299757 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 00:16:56.347433 Check phy result
355 00:16:56.347923 INFO : End of initialization
356 00:16:56.369735 INFO : End of 2D read delay Voltage center optimization
357 00:16:56.388993 INFO : End of 2D read delay Voltage center optimization
358 00:16:56.440011 INFO : End of 2D write delay Voltage center optimization
359 00:16:56.489994 INFO : End of 2D write delay Voltage center optimization
360 00:16:56.495553 INFO : Training has run successfully!
361 00:16:56.496009
362 00:16:56.496415 channel==0
363 00:16:56.501138 RxClkDly_Margin_A0==78 ps 8
364 00:16:56.501565 TxDqDly_Margin_A0==98 ps 10
365 00:16:56.506742 RxClkDly_Margin_A1==78 ps 8
366 00:16:56.507169 TxDqDly_Margin_A1==98 ps 10
367 00:16:56.507562 TrainedVREFDQ_A0==74
368 00:16:56.512315 TrainedVREFDQ_A1==74
369 00:16:56.512757 VrefDac_Margin_A0==23
370 00:16:56.513147 DeviceVref_Margin_A0==40
371 00:16:56.517954 VrefDac_Margin_A1==22
372 00:16:56.518374 DeviceVref_Margin_A1==40
373 00:16:56.518767
374 00:16:56.519154
375 00:16:56.523553 channel==1
376 00:16:56.523975 RxClkDly_Margin_A0==78 ps 8
377 00:16:56.524404 TxDqDly_Margin_A0==98 ps 10
378 00:16:56.529135 RxClkDly_Margin_A1==78 ps 8
379 00:16:56.529557 TxDqDly_Margin_A1==78 ps 8
380 00:16:56.534734 TrainedVREFDQ_A0==78
381 00:16:56.535164 TrainedVREFDQ_A1==75
382 00:16:56.535555 VrefDac_Margin_A0==22
383 00:16:56.540322 DeviceVref_Margin_A0==36
384 00:16:56.540747 VrefDac_Margin_A1==22
385 00:16:56.545968 DeviceVref_Margin_A1==39
386 00:16:56.546382
387 00:16:56.546777 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 00:16:56.547167
389 00:16:56.579522 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 00:16:56.580097 2D training succeed
391 00:16:56.585160 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 00:16:56.590719 auto size-- 65535DDR cs0 size: 2048MB
393 00:16:56.591145 DDR cs1 size: 2048MB
394 00:16:56.596429 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 00:16:56.596853 cs0 DataBus test pass
396 00:16:56.602084 cs1 DataBus test pass
397 00:16:56.602529 cs0 AddrBus test pass
398 00:16:56.602917 cs1 AddrBus test pass
399 00:16:56.603300
400 00:16:56.607648 100bdlr_step_size ps== 478
401 00:16:56.608129 result report
402 00:16:56.613237 boot times 0Enable ddr reg access
403 00:16:56.618519 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 00:16:56.632373 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 00:16:57.287426 bl2z: ptr: 05129330, size: 00001e40
406 00:16:57.294083 0.0;M3 CHK:0;cm4_sp_mode 0
407 00:16:57.294575 MVN_1=0x00000000
408 00:16:57.294992 MVN_2=0x00000000
409 00:16:57.305583 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 00:16:57.306051 OPS=0x04
411 00:16:57.306464 ring efuse init
412 00:16:57.308542 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 00:16:57.314150 [0.017319 Inits done]
414 00:16:57.314600 secure task start!
415 00:16:57.315008 high task start!
416 00:16:57.315418 low task start!
417 00:16:57.318498 run into bl31
418 00:16:57.327033 NOTICE: BL31: v1.3(release):4fc40b1
419 00:16:57.334869 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 00:16:57.335334 NOTICE: BL31: G12A normal boot!
421 00:16:57.350389 NOTICE: BL31: BL33 decompress pass
422 00:16:57.356158 ERROR: Error initializing runtime service opteed_fast
423 00:16:58.602618 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 00:16:58.603019 bl2_stage_init 0x01
425 00:16:58.603246 bl2_stage_init 0x81
426 00:16:58.608167 hw id: 0x0000 - pwm id 0x01
427 00:16:58.608496 bl2_stage_init 0xc1
428 00:16:58.608724 bl2_stage_init 0x02
429 00:16:58.608938
430 00:16:58.613804 L0:00000000
431 00:16:58.614233 L1:00000703
432 00:16:58.614592 L2:00008067
433 00:16:58.614941 L3:15000000
434 00:16:58.615285 S1:00000000
435 00:16:58.619589 B2:20282000
436 00:16:58.620133 B1:a0f83180
437 00:16:58.620509
438 00:16:58.620731 TE: 73127
439 00:16:58.620947
440 00:16:58.625112 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 00:16:58.625601
442 00:16:58.630668 Board ID = 1
443 00:16:58.630951 Set cpu clk to 24M
444 00:16:58.631179 Set clk81 to 24M
445 00:16:58.636330 Use GP1_pll as DSU clk.
446 00:16:58.636847 DSU clk: 1200 Mhz
447 00:16:58.637272 CPU clk: 1200 MHz
448 00:16:58.637696 Set clk81 to 166.6M
449 00:16:58.647594 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 00:16:58.648143 board id: 1
451 00:16:58.652965 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 00:16:58.664773 fw parse done
453 00:16:58.669776 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 00:16:58.713976 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 00:16:58.725035 PIEI prepare done
456 00:16:58.725541 fastboot data load
457 00:16:58.725942 fastboot data verify
458 00:16:58.730525 verify result: 266
459 00:16:58.738043 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 00:16:58.738552 LPDDR4 probe
461 00:16:58.738948 ddr clk to 1584MHz
462 00:17:00.102813 Load ddrfw SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 00:17:00.103435 bl2_stage_init 0x01
464 00:17:00.103870 bl2_stage_init 0x81
465 00:17:00.108491 hw id: 0x0000 - pwm id 0x01
466 00:17:00.109022 bl2_stage_init 0xc1
467 00:17:00.113794 bl2_stage_init 0x02
468 00:17:00.114294
469 00:17:00.114722 L0:00000000
470 00:17:00.115132 L1:00000703
471 00:17:00.115537 L2:00008067
472 00:17:00.115937 L3:15000000
473 00:17:00.119391 S1:00000000
474 00:17:00.119872 B2:20282000
475 00:17:00.120327 B1:a0f83180
476 00:17:00.120732
477 00:17:00.121134 TE: 73239
478 00:17:00.121531
479 00:17:00.124960 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 00:17:00.125454
481 00:17:00.130583 Board ID = 1
482 00:17:00.131084 Set cpu clk to 24M
483 00:17:00.131505 Set clk81 to 24M
484 00:17:00.136220 Use GP1_pll as DSU clk.
485 00:17:00.136760 DSU clk: 1200 Mhz
486 00:17:00.137182 CPU clk: 1200 MHz
487 00:17:00.141790 Set clk81 to 166.6M
488 00:17:00.147412 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 00:17:00.147917 board id: 1
490 00:17:00.154833 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 00:17:00.165530 fw parse done
492 00:17:00.171460 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 00:17:00.213099 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 00:17:00.225104 PIEI prepare done
495 00:17:00.225606 fastboot data load
496 00:17:00.226025 fastboot data verify
497 00:17:00.230672 verify result: 266
498 00:17:00.236317 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 00:17:00.236831 LPDDR4 probe
500 00:17:00.237248 ddr clk to 1584MHz
501 00:17:00.244304 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 00:17:00.280622
503 00:17:00.281161 dmc_version 0001
504 00:17:00.288242 Check phy result
505 00:17:00.294141 INFO : End of CA training
506 00:17:00.294812 INFO : End of initialization
507 00:17:00.299747 INFO : Training has run successfully!
508 00:17:00.300290 Check phy result
509 00:17:00.305330 INFO : End of initialization
510 00:17:00.305810 INFO : End of read enable training
511 00:17:00.308606 INFO : End of fine write leveling
512 00:17:00.314091 INFO : End of Write leveling coarse delay
513 00:17:00.319808 INFO : Training has run successfully!
514 00:17:00.320314 Check phy result
515 00:17:00.320723 INFO : End of initialization
516 00:17:00.325360 INFO : End of read dq deskew training
517 00:17:00.330943 INFO : End of MPR read delay center optimization
518 00:17:00.331416 INFO : End of write delay center optimization
519 00:17:00.336540 INFO : End of read delay center optimization
520 00:17:00.342189 INFO : End of max read latency training
521 00:17:00.342705 INFO : Training has run successfully!
522 00:17:00.347785 1D training succeed
523 00:17:00.352866 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 00:17:00.400377 Check phy result
525 00:17:00.400891 INFO : End of initialization
526 00:17:00.423609 INFO : End of 2D read delay Voltage center optimization
527 00:17:00.441786 INFO : End of 2D read delay Voltage center optimization
528 00:17:00.494627 INFO : End of 2D write delay Voltage center optimization
529 00:17:00.543977 INFO : End of 2D write delay Voltage center optimization
530 00:17:00.549404 INFO : Training has run successfully!
531 00:17:00.549896
532 00:17:00.550314 channel==0
533 00:17:00.554975 RxClkDly_Margin_A0==78 ps 8
534 00:17:00.555448 TxDqDly_Margin_A0==88 ps 9
535 00:17:00.560553 RxClkDly_Margin_A1==88 ps 9
536 00:17:00.561009 TxDqDly_Margin_A1==98 ps 10
537 00:17:00.561419 TrainedVREFDQ_A0==74
538 00:17:00.566153 TrainedVREFDQ_A1==75
539 00:17:00.566615 VrefDac_Margin_A0==23
540 00:17:00.567023 DeviceVref_Margin_A0==40
541 00:17:00.571873 VrefDac_Margin_A1==23
542 00:17:00.572361 DeviceVref_Margin_A1==39
543 00:17:00.572771
544 00:17:00.573173
545 00:17:00.573570 channel==1
546 00:17:00.577385 RxClkDly_Margin_A0==78 ps 8
547 00:17:00.577845 TxDqDly_Margin_A0==98 ps 10
548 00:17:00.582951 RxClkDly_Margin_A1==78 ps 8
549 00:17:00.583413 TxDqDly_Margin_A1==88 ps 9
550 00:17:00.588548 TrainedVREFDQ_A0==78
551 00:17:00.589008 TrainedVREFDQ_A1==75
552 00:17:00.589418 VrefDac_Margin_A0==22
553 00:17:00.594140 DeviceVref_Margin_A0==36
554 00:17:00.594598 VrefDac_Margin_A1==22
555 00:17:00.599876 DeviceVref_Margin_A1==39
556 00:17:00.600369
557 00:17:00.600781 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 00:17:00.601181
559 00:17:00.633354 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
560 00:17:00.633896 2D training succeed
561 00:17:00.639018 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 00:17:00.644589 auto size-- 65535DDR cs0 size: 2048MB
563 00:17:00.645068 DDR cs1 size: 2048MB
564 00:17:00.650194 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 00:17:00.650677 cs0 DataBus test pass
566 00:17:00.655926 cs1 DataBus test pass
567 00:17:00.656434 cs0 AddrBus test pass
568 00:17:00.656844 cs1 AddrBus test pass
569 00:17:00.657244
570 00:17:00.661376 100bdlr_step_size ps== 478
571 00:17:00.661854 result report
572 00:17:00.666986 boot times 0Enable ddr reg access
573 00:17:00.672174 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 00:17:00.685957 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 00:17:01.341279 bl2z: ptr: 05129330, size: 00001e40
576 00:17:01.348222 0.0;M3 CHK:0;cm4_sp_mode 0
577 00:17:01.348715 MVN_1=0x00000000
578 00:17:01.349130 MVN_2=0x00000000
579 00:17:01.359620 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 00:17:01.360152 OPS=0x04
581 00:17:01.360572 ring efuse init
582 00:17:01.365291 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 00:17:01.365776 [0.017310 Inits done]
584 00:17:01.366186 secure task start!
585 00:17:01.373193 high task start!
586 00:17:01.373810 low task start!
587 00:17:01.374391 run into bl31
588 00:17:01.381787 NOTICE: BL31: v1.3(release):4fc40b1
589 00:17:01.389764 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 00:17:01.390452 NOTICE: BL31: G12A normal boot!
591 00:17:01.405234 NOTICE: BL31: BL33 decompress pass
592 00:17:01.410918 ERROR: Error initializing runtime service opteed_fast
593 00:17:02.646880 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 00:17:02.647651 bl2_stage_init 0x01
595 00:17:02.648253 bl2_stage_init 0x81
596 00:17:02.652459 hw id: 0x0000 - pwm id 0x01
597 00:17:02.653080 bl2_stage_init 0xc1
598 00:17:02.657986 bl2_stage_init 0x02
599 00:17:02.658587
600 00:17:02.659134 L0:00000000
601 00:17:02.659657 L1:00000703
602 00:17:02.660232 L2:00008067
603 00:17:02.660754 L3:15000000
604 00:17:02.663650 S1:00000000
605 00:17:02.664286 B2:20282000
606 00:17:02.664840 B1:a0f83180
607 00:17:02.665362
608 00:17:02.665883 TE: 67929
609 00:17:02.666405
610 00:17:02.669311 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 00:17:02.669935
612 00:17:02.674805 Board ID = 1
613 00:17:02.675408 Set cpu clk to 24M
614 00:17:02.675949 Set clk81 to 24M
615 00:17:02.680430 Use GP1_pll as DSU clk.
616 00:17:02.681034 DSU clk: 1200 Mhz
617 00:17:02.681577 CPU clk: 1200 MHz
618 00:17:02.685971 Set clk81 to 166.6M
619 00:17:02.691682 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 00:17:02.692316 board id: 1
621 00:17:02.698888 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 00:17:02.709725 fw parse done
623 00:17:02.715644 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 00:17:02.758663 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 00:17:02.769873 PIEI prepare done
626 00:17:02.770482 fastboot data load
627 00:17:02.771012 fastboot data verify
628 00:17:02.775405 verify result: 266
629 00:17:02.781029 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 00:17:02.781624 LPDDR4 probe
631 00:17:02.782149 ddr clk to 1584MHz
632 00:17:02.789006 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 00:17:02.826767
634 00:17:02.827448 dmc_version 0001
635 00:17:02.833785 Check phy result
636 00:17:02.839774 INFO : End of CA training
637 00:17:02.840406 INFO : End of initialization
638 00:17:02.845383 INFO : Training has run successfully!
639 00:17:02.845981 Check phy result
640 00:17:02.850959 INFO : End of initialization
641 00:17:02.851554 INFO : End of read enable training
642 00:17:02.856561 INFO : End of fine write leveling
643 00:17:02.862278 INFO : End of Write leveling coarse delay
644 00:17:02.862873 INFO : Training has run successfully!
645 00:17:02.863406 Check phy result
646 00:17:02.867762 INFO : End of initialization
647 00:17:02.868382 INFO : End of read dq deskew training
648 00:17:02.873373 INFO : End of MPR read delay center optimization
649 00:17:02.878958 INFO : End of write delay center optimization
650 00:17:02.884555 INFO : End of read delay center optimization
651 00:17:02.885149 INFO : End of max read latency training
652 00:17:02.890265 INFO : Training has run successfully!
653 00:17:02.890865 1D training succeed
654 00:17:02.899331 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 00:17:02.947754 Check phy result
656 00:17:02.948545 INFO : End of initialization
657 00:17:02.975170 INFO : End of 2D read delay Voltage center optimization
658 00:17:02.998504 INFO : End of 2D read delay Voltage center optimization
659 00:17:03.056137 INFO : End of 2D write delay Voltage center optimization
660 00:17:03.110075 INFO : End of 2D write delay Voltage center optimization
661 00:17:03.115474 INFO : Training has run successfully!
662 00:17:03.116120
663 00:17:03.116680 channel==0
664 00:17:03.121066 RxClkDly_Margin_A0==88 ps 9
665 00:17:03.121660 TxDqDly_Margin_A0==98 ps 10
666 00:17:03.126676 RxClkDly_Margin_A1==88 ps 9
667 00:17:03.127285 TxDqDly_Margin_A1==88 ps 9
668 00:17:03.127831 TrainedVREFDQ_A0==74
669 00:17:03.132336 TrainedVREFDQ_A1==74
670 00:17:03.132810 VrefDac_Margin_A0==24
671 00:17:03.133224 DeviceVref_Margin_A0==40
672 00:17:03.137950 VrefDac_Margin_A1==23
673 00:17:03.138544 DeviceVref_Margin_A1==40
674 00:17:03.139083
675 00:17:03.139606
676 00:17:03.140178 channel==1
677 00:17:03.143490 RxClkDly_Margin_A0==78 ps 8
678 00:17:03.144104 TxDqDly_Margin_A0==98 ps 10
679 00:17:03.149086 RxClkDly_Margin_A1==78 ps 8
680 00:17:03.149675 TxDqDly_Margin_A1==88 ps 9
681 00:17:03.154681 TrainedVREFDQ_A0==78
682 00:17:03.155285 TrainedVREFDQ_A1==75
683 00:17:03.155815 VrefDac_Margin_A0==22
684 00:17:03.160332 DeviceVref_Margin_A0==36
685 00:17:03.160804 VrefDac_Margin_A1==20
686 00:17:03.165948 DeviceVref_Margin_A1==39
687 00:17:03.166572
688 00:17:03.167116 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 00:17:03.167636
690 00:17:03.199421 soc_vref_reg_value 0x 00000019 00000018 00000017 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
691 00:17:03.200113 2D training succeed
692 00:17:03.205090 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 00:17:03.210681 auto size-- 65535DDR cs0 size: 2048MB
694 00:17:03.211273 DDR cs1 size: 2048MB
695 00:17:03.216343 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 00:17:03.216962 cs0 DataBus test pass
697 00:17:03.221964 cs1 DataBus test pass
698 00:17:03.222553 cs0 AddrBus test pass
699 00:17:03.223080 cs1 AddrBus test pass
700 00:17:03.223607
701 00:17:03.227470 100bdlr_step_size ps== 471
702 00:17:03.228105 result report
703 00:17:03.233099 boot times 0Enable ddr reg access
704 00:17:03.238265 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 00:17:03.252110 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 00:17:03.911147 bl2z: ptr: 05129330, size: 00001e40
707 00:17:03.919853 0.0;M3 CHK:0;cm4_sp_mode 0
708 00:17:03.920551 MVN_1=0x00000000
709 00:17:03.921112 MVN_2=0x00000000
710 00:17:03.931338 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 00:17:03.931975 OPS=0x04
712 00:17:03.932532 ring efuse init
713 00:17:03.936876 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 00:17:03.937473 [0.017354 Inits done]
715 00:17:03.937980 secure task start!
716 00:17:03.943799 high task start!
717 00:17:03.944410 low task start!
718 00:17:03.944915 run into bl31
719 00:17:03.953391 NOTICE: BL31: v1.3(release):4fc40b1
720 00:17:03.960214 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 00:17:03.960812 NOTICE: BL31: G12A normal boot!
722 00:17:03.976670 NOTICE: BL31: BL33 decompress pass
723 00:17:03.981562 ERROR: Error initializing runtime service opteed_fast
724 00:17:04.777826
725 00:17:04.778555
726 00:17:04.783249 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 00:17:04.783863
728 00:17:04.785772 Model: Libre Computer AML-S905D3-CC Solitude
729 00:17:04.933722 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 00:17:04.949136 DRAM: 2 GiB (effective 3.8 GiB)
731 00:17:05.050069 Core: 406 devices, 33 uclasses, devicetree: separate
732 00:17:05.056013 WDT: Not starting watchdog@f0d0
733 00:17:05.081020 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 00:17:05.093216 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 00:17:05.097307 ** Bad device specification mmc 0 **
736 00:17:05.108351 Card did not respond to voltage select! : -110
737 00:17:05.115000 ** Bad device specification mmc 0 **
738 00:17:05.115607 Couldn't find partition mmc 0
739 00:17:05.124340 Card did not respond to voltage select! : -110
740 00:17:05.129827 ** Bad device specification mmc 0 **
741 00:17:05.130415 Couldn't find partition mmc 0
742 00:17:05.133971 Error: could not access storage.
743 00:17:05.431318 Net: eth0: ethernet@ff3f0000
744 00:17:05.432060 starting USB...
745 00:17:05.676081 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 00:17:05.676827 Starting the controller
747 00:17:05.682948 USB XHCI 1.10
748 00:17:07.237085 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 00:17:07.245378 scanning usb for storage devices... 0 Storage Device(s) found
751 00:17:07.297209 Hit any key to stop autoboot: 1
752 00:17:07.298280 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 00:17:07.299081 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 00:17:07.299714 Setting prompt string to ['=>']
755 00:17:07.300418 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 00:17:07.310423 0
757 00:17:07.311324 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 00:17:07.412626 => setenv autoload no
760 00:17:07.413587 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 00:17:07.418400 setenv autoload no
763 00:17:07.519857 => setenv initrd_high 0xffffffff
764 00:17:07.520755 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 00:17:07.524012 setenv initrd_high 0xffffffff
767 00:17:07.625413 => setenv fdt_high 0xffffffff
768 00:17:07.626247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 00:17:07.630543 setenv fdt_high 0xffffffff
771 00:17:07.732047 => dhcp
772 00:17:07.732877 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 00:17:07.736941 dhcp
774 00:17:08.791916 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 00:17:08.792517 Speed: 1000, full duplex
776 00:17:08.792933 BOOTP broadcast 1
777 00:17:08.815748 DHCP client bound to address 192.168.6.21 (23 ms)
779 00:17:08.917199 => setenv serverip 192.168.6.2
780 00:17:08.918030 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
781 00:17:08.922319 setenv serverip 192.168.6.2
783 00:17:09.023748 => tftpboot 0x01080000 915391/tftp-deploy-ld3nrofe/kernel/uImage
784 00:17:09.024490 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
785 00:17:09.031265 tftpboot 0x01080000 915391/tftp-deploy-ld3nrofe/kernel/uImage
786 00:17:09.031722 Speed: 1000, full duplex
787 00:17:09.032151 Using ethernet@ff3f0000 device
788 00:17:09.036749 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 00:17:09.042256 Filename '915391/tftp-deploy-ld3nrofe/kernel/uImage'.
790 00:17:09.046220 Load address: 0x1080000
791 00:17:13.059201 Loading: *################################################## 62.6 MiB
792 00:17:13.059824 15.6 MiB/s
793 00:17:13.060309 done
794 00:17:13.063653 Bytes transferred = 65665600 (3e9fa40 hex)
796 00:17:13.165223 => tftpboot 0x08000000 915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot
797 00:17:13.166185 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
798 00:17:13.172925 tftpboot 0x08000000 915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot
799 00:17:13.173411 Speed: 1000, full duplex
800 00:17:13.173822 Using ethernet@ff3f0000 device
801 00:17:13.178382 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 00:17:13.188161 Filename '915391/tftp-deploy-ld3nrofe/ramdisk/ramdisk.cpio.gz.uboot'.
803 00:17:13.188677 Load address: 0x8000000
804 00:17:15.306974 Loading: *################################################# UDP wrong checksum 00000007 0000f29f
805 00:17:20.308692 T UDP wrong checksum 00000007 0000f29f
806 00:17:25.004316 UDP wrong checksum 00000005 00000493
807 00:17:28.255940 T UDP wrong checksum 000000ff 00009fe8
808 00:17:28.276398 UDP wrong checksum 000000ff 000036db
809 00:17:30.310673 T UDP wrong checksum 00000007 0000f29f
810 00:17:50.312377 T T T UDP wrong checksum 00000007 0000f29f
811 00:18:10.319306 T T T T
812 00:18:10.319907 Retry count exceeded; starting again
814 00:18:10.321591 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
817 00:18:10.323406 end: 2.4 uboot-commands (duration 00:01:22) [common]
819 00:18:10.324958 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
821 00:18:10.325994 end: 2 uboot-action (duration 00:01:22) [common]
823 00:18:10.327692 Cleaning after the job
824 00:18:10.328290 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/ramdisk
825 00:18:10.329767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/kernel
826 00:18:10.339684 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/dtb
827 00:18:10.340857 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915391/tftp-deploy-ld3nrofe/modules
828 00:18:10.349632 start: 4.1 power-off (timeout 00:00:30) [common]
829 00:18:10.350657 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
830 00:18:10.389574 >> OK - accepted request
831 00:18:10.392051 Returned 0 in 0 seconds
832 00:18:10.492977 end: 4.1 power-off (duration 00:00:00) [common]
834 00:18:10.494659 start: 4.2 read-feedback (timeout 00:10:00) [common]
835 00:18:10.495761 Listened to connection for namespace 'common' for up to 1s
836 00:18:11.496576 Finalising connection for namespace 'common'
837 00:18:11.497306 Disconnecting from shell: Finalise
838 00:18:11.497819 =>
839 00:18:11.598836 end: 4.2 read-feedback (duration 00:00:01) [common]
840 00:18:11.599557 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915391
841 00:18:11.911940 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915391
842 00:18:11.912540 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.