Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:43:44.312348 lava-dispatcher, installed at version: 2024.01
2 23:43:44.313117 start: 0 validate
3 23:43:44.313581 Start time: 2024-10-30 23:43:44.313551+00:00 (UTC)
4 23:43:44.314121 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:43:44.314644 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:43:44.355640 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:43:44.356235 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 23:43:44.386992 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:43:44.387621 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 23:43:45.443556 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:43:45.444062 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
12 23:43:45.489055 validate duration: 1.18
14 23:43:45.490570 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:43:45.491180 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:43:45.491754 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:43:45.492769 Not decompressing ramdisk as can be used compressed.
18 23:43:45.493506 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:43:45.494005 saving as /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/ramdisk/rootfs.cpio.gz
20 23:43:45.494515 total size: 8181887 (7 MB)
21 23:43:45.537971 progress 0 % (0 MB)
22 23:43:45.549481 progress 5 % (0 MB)
23 23:43:45.560697 progress 10 % (0 MB)
24 23:43:45.572728 progress 15 % (1 MB)
25 23:43:45.581500 progress 20 % (1 MB)
26 23:43:45.587049 progress 25 % (1 MB)
27 23:43:45.592210 progress 30 % (2 MB)
28 23:43:45.597804 progress 35 % (2 MB)
29 23:43:45.602934 progress 40 % (3 MB)
30 23:43:45.608469 progress 45 % (3 MB)
31 23:43:45.613626 progress 50 % (3 MB)
32 23:43:45.619165 progress 55 % (4 MB)
33 23:43:45.624509 progress 60 % (4 MB)
34 23:43:45.630081 progress 65 % (5 MB)
35 23:43:45.635276 progress 70 % (5 MB)
36 23:43:45.640841 progress 75 % (5 MB)
37 23:43:45.645950 progress 80 % (6 MB)
38 23:43:45.651430 progress 85 % (6 MB)
39 23:43:45.656540 progress 90 % (7 MB)
40 23:43:45.661991 progress 95 % (7 MB)
41 23:43:45.666678 progress 100 % (7 MB)
42 23:43:45.667318 7 MB downloaded in 0.17 s (45.16 MB/s)
43 23:43:45.667863 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:43:45.668781 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:43:45.669071 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:43:45.669336 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:43:45.669798 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/kernel/Image
49 23:43:45.670039 saving as /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/kernel/Image
50 23:43:45.670245 total size: 37878272 (36 MB)
51 23:43:45.670452 No compression specified
52 23:43:45.708359 progress 0 % (0 MB)
53 23:43:45.731406 progress 5 % (1 MB)
54 23:43:45.754729 progress 10 % (3 MB)
55 23:43:45.779291 progress 15 % (5 MB)
56 23:43:45.803101 progress 20 % (7 MB)
57 23:43:45.826782 progress 25 % (9 MB)
58 23:43:45.850180 progress 30 % (10 MB)
59 23:43:45.873676 progress 35 % (12 MB)
60 23:43:45.897239 progress 40 % (14 MB)
61 23:43:45.920495 progress 45 % (16 MB)
62 23:43:45.943404 progress 50 % (18 MB)
63 23:43:45.966501 progress 55 % (19 MB)
64 23:43:45.989760 progress 60 % (21 MB)
65 23:43:46.012830 progress 65 % (23 MB)
66 23:43:46.035535 progress 70 % (25 MB)
67 23:43:46.057998 progress 75 % (27 MB)
68 23:43:46.080905 progress 80 % (28 MB)
69 23:43:46.104464 progress 85 % (30 MB)
70 23:43:46.127697 progress 90 % (32 MB)
71 23:43:46.150785 progress 95 % (34 MB)
72 23:43:46.173167 progress 100 % (36 MB)
73 23:43:46.173917 36 MB downloaded in 0.50 s (71.72 MB/s)
74 23:43:46.174404 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:43:46.175204 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:43:46.175476 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:43:46.175738 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:43:46.176227 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 23:43:46.176507 saving as /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 23:43:46.176715 total size: 53209 (0 MB)
82 23:43:46.176922 No compression specified
83 23:43:46.218283 progress 61 % (0 MB)
84 23:43:46.219124 progress 100 % (0 MB)
85 23:43:46.219651 0 MB downloaded in 0.04 s (1.18 MB/s)
86 23:43:46.220147 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:43:46.220959 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:43:46.221218 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:43:46.221479 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:43:46.221925 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/modules.tar.xz
92 23:43:46.222165 saving as /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/modules/modules.tar
93 23:43:46.222367 total size: 11755844 (11 MB)
94 23:43:46.222573 Using unxz to decompress xz
95 23:43:46.262170 progress 0 % (0 MB)
96 23:43:46.328973 progress 5 % (0 MB)
97 23:43:46.404110 progress 10 % (1 MB)
98 23:43:46.484560 progress 15 % (1 MB)
99 23:43:46.564500 progress 20 % (2 MB)
100 23:43:46.640983 progress 25 % (2 MB)
101 23:43:46.721102 progress 30 % (3 MB)
102 23:43:46.797325 progress 35 % (3 MB)
103 23:43:46.877879 progress 40 % (4 MB)
104 23:43:46.962309 progress 45 % (5 MB)
105 23:43:47.043117 progress 50 % (5 MB)
106 23:43:47.125975 progress 55 % (6 MB)
107 23:43:47.207353 progress 60 % (6 MB)
108 23:43:47.290310 progress 65 % (7 MB)
109 23:43:47.372368 progress 70 % (7 MB)
110 23:43:47.453421 progress 75 % (8 MB)
111 23:43:47.536121 progress 80 % (9 MB)
112 23:43:47.611263 progress 85 % (9 MB)
113 23:43:47.684190 progress 90 % (10 MB)
114 23:43:47.781476 progress 95 % (10 MB)
115 23:43:47.877115 progress 100 % (11 MB)
116 23:43:47.890588 11 MB downloaded in 1.67 s (6.72 MB/s)
117 23:43:47.891163 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:43:47.892106 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:43:47.892813 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 23:43:47.893349 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 23:43:47.893850 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:43:47.894352 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 23:43:47.895337 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o
125 23:43:47.896216 makedir: /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin
126 23:43:47.896863 makedir: /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/tests
127 23:43:47.897472 makedir: /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/results
128 23:43:47.898083 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-add-keys
129 23:43:47.899033 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-add-sources
130 23:43:47.899948 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-background-process-start
131 23:43:47.900928 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-background-process-stop
132 23:43:47.902012 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-common-functions
133 23:43:47.902936 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-echo-ipv4
134 23:43:47.903835 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-install-packages
135 23:43:47.904764 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-installed-packages
136 23:43:47.905644 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-os-build
137 23:43:47.906524 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-probe-channel
138 23:43:47.907413 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-probe-ip
139 23:43:47.908325 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-target-ip
140 23:43:47.909210 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-target-mac
141 23:43:47.910090 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-target-storage
142 23:43:47.910987 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-case
143 23:43:47.911868 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-event
144 23:43:47.912790 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-feedback
145 23:43:47.913700 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-raise
146 23:43:47.914588 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-reference
147 23:43:47.915464 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-runner
148 23:43:47.916380 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-set
149 23:43:47.917269 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-test-shell
150 23:43:47.918158 Updating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-install-packages (oe)
151 23:43:47.919111 Updating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/bin/lava-installed-packages (oe)
152 23:43:47.919928 Creating /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/environment
153 23:43:47.920674 LAVA metadata
154 23:43:47.921166 - LAVA_JOB_ID=915254
155 23:43:47.921587 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:43:47.922221 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 23:43:47.923976 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:43:47.924612 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 23:43:47.925024 skipped lava-vland-overlay
160 23:43:47.925505 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:43:47.926004 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 23:43:47.926424 skipped lava-multinode-overlay
163 23:43:47.926905 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:43:47.927398 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 23:43:47.927869 Loading test definitions
166 23:43:47.928438 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 23:43:47.928875 Using /lava-915254 at stage 0
168 23:43:47.931008 uuid=915254_1.5.2.4.1 testdef=None
169 23:43:47.931590 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:43:47.932119 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 23:43:47.933966 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:43:47.934787 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 23:43:47.937064 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:43:47.937946 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 23:43:47.940147 runner path: /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/0/tests/0_dmesg test_uuid 915254_1.5.2.4.1
178 23:43:47.940726 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:43:47.941524 Creating lava-test-runner.conf files
181 23:43:47.941727 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915254/lava-overlay-v5rtai3o/lava-915254/0 for stage 0
182 23:43:47.942054 - 0_dmesg
183 23:43:47.942414 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:43:47.942697 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 23:43:47.966181 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:43:47.966577 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:58) [common]
187 23:43:47.966845 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:43:47.967112 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:43:47.967377 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
190 23:43:48.872681 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 23:43:48.873157 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 23:43:48.873408 extracting modules file /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk
193 23:43:50.189997 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:43:50.190448 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 23:43:50.190726 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915254/compress-overlay-x6epow_b/overlay-1.5.2.5.tar.gz to ramdisk
196 23:43:50.190938 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915254/compress-overlay-x6epow_b/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk
197 23:43:50.221007 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:43:50.221419 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 23:43:50.221692 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 23:43:50.221918 Converting downloaded kernel to a uImage
201 23:43:50.222221 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/kernel/Image /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/kernel/uImage
202 23:43:50.612843 output: Image Name:
203 23:43:50.613253 output: Created: Wed Oct 30 23:43:50 2024
204 23:43:50.613467 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:43:50.613673 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
206 23:43:50.613873 output: Load Address: 01080000
207 23:43:50.614071 output: Entry Point: 01080000
208 23:43:50.614268 output:
209 23:43:50.614599 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:43:50.614869 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:43:50.615140 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 23:43:50.615394 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:43:50.615652 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 23:43:50.615907 Building ramdisk /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk
215 23:43:53.130506 >> 188204 blocks
216 23:44:01.513202 Adding RAMdisk u-boot header.
217 23:44:01.513648 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk.cpio.gz.uboot
218 23:44:01.814998 output: Image Name:
219 23:44:01.815420 output: Created: Wed Oct 30 23:44:01 2024
220 23:44:01.815629 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:44:01.815831 output: Data Size: 26772745 Bytes = 26145.26 KiB = 25.53 MiB
222 23:44:01.816112 output: Load Address: 00000000
223 23:44:01.816515 output: Entry Point: 00000000
224 23:44:01.816900 output:
225 23:44:01.817939 rename /var/lib/lava/dispatcher/tmp/915254/extract-overlay-ramdisk-3a0_8_ld/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot
226 23:44:01.818647 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 23:44:01.819179 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 23:44:01.819700 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 23:44:01.820182 No LXC device requested
230 23:44:01.820680 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:44:01.821183 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 23:44:01.821667 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:44:01.822074 Checking files for TFTP limit of 4294967296 bytes.
234 23:44:01.824729 end: 1 tftp-deploy (duration 00:00:16) [common]
235 23:44:01.825289 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:44:01.825803 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:44:01.826290 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:44:01.826778 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:44:01.827298 Using kernel file from prepare-kernel: 915254/tftp-deploy-_zisni3g/kernel/uImage
240 23:44:01.827909 substitutions:
241 23:44:01.828371 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:44:01.828769 - {DTB_ADDR}: 0x01070000
243 23:44:01.829160 - {DTB}: 915254/tftp-deploy-_zisni3g/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 23:44:01.829554 - {INITRD}: 915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot
245 23:44:01.829942 - {KERNEL_ADDR}: 0x01080000
246 23:44:01.830326 - {KERNEL}: 915254/tftp-deploy-_zisni3g/kernel/uImage
247 23:44:01.830713 - {LAVA_MAC}: None
248 23:44:01.831134 - {PRESEED_CONFIG}: None
249 23:44:01.831524 - {PRESEED_LOCAL}: None
250 23:44:01.831907 - {RAMDISK_ADDR}: 0x08000000
251 23:44:01.832354 - {RAMDISK}: 915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot
252 23:44:01.832750 - {ROOT_PART}: None
253 23:44:01.833138 - {ROOT}: None
254 23:44:01.833521 - {SERVER_IP}: 192.168.6.2
255 23:44:01.833911 - {TEE_ADDR}: 0x83000000
256 23:44:01.834297 - {TEE}: None
257 23:44:01.834680 Parsed boot commands:
258 23:44:01.835054 - setenv autoload no
259 23:44:01.835437 - setenv initrd_high 0xffffffff
260 23:44:01.835818 - setenv fdt_high 0xffffffff
261 23:44:01.836226 - dhcp
262 23:44:01.836611 - setenv serverip 192.168.6.2
263 23:44:01.836991 - tftpboot 0x01080000 915254/tftp-deploy-_zisni3g/kernel/uImage
264 23:44:01.837371 - tftpboot 0x08000000 915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot
265 23:44:01.837752 - tftpboot 0x01070000 915254/tftp-deploy-_zisni3g/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 23:44:01.838134 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:44:01.838520 - bootm 0x01080000 0x08000000 0x01070000
268 23:44:01.839000 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:44:01.840490 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:44:01.840926 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 23:44:01.855541 Setting prompt string to ['lava-test: # ']
273 23:44:01.857001 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:44:01.857595 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:44:01.858121 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:44:01.858622 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:44:01.859726 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 23:44:01.896243 >> OK - accepted request
279 23:44:01.898330 Returned 0 in 0 seconds
280 23:44:01.999384 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:44:02.000963 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:44:02.001534 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:44:02.002026 Setting prompt string to ['Hit any key to stop autoboot']
285 23:44:02.002473 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:44:02.004056 Trying 192.168.56.21...
287 23:44:02.004529 Connected to conserv1.
288 23:44:02.004946 Escape character is '^]'.
289 23:44:02.005370
290 23:44:02.005795 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 23:44:02.006223
292 23:44:08.944746 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 23:44:08.945342 bl2_stage_init 0x01
294 23:44:08.945767 bl2_stage_init 0x81
295 23:44:08.950330 hw id: 0x0000 - pwm id 0x01
296 23:44:08.950777 bl2_stage_init 0xc1
297 23:44:08.955918 bl2_stage_init 0x02
298 23:44:08.956418
299 23:44:08.956818 L0:00000000
300 23:44:08.957210 L1:00000703
301 23:44:08.957599 L2:00008067
302 23:44:08.957991 L3:15000000
303 23:44:08.961520 S1:00000000
304 23:44:08.961952 B2:20282000
305 23:44:08.962341 B1:a0f83180
306 23:44:08.962729
307 23:44:08.963113 TE: 67704
308 23:44:08.963499
309 23:44:08.967126 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 23:44:08.967551
311 23:44:08.972700 Board ID = 1
312 23:44:08.973126 Set cpu clk to 24M
313 23:44:08.973518 Set clk81 to 24M
314 23:44:08.978320 Use GP1_pll as DSU clk.
315 23:44:08.978738 DSU clk: 1200 Mhz
316 23:44:08.979128 CPU clk: 1200 MHz
317 23:44:08.983877 Set clk81 to 166.6M
318 23:44:08.989492 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 23:44:08.989916 board id: 1
320 23:44:08.996679 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:44:09.007582 fw parse done
322 23:44:09.013556 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:44:09.056687 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:44:09.067776 PIEI prepare done
325 23:44:09.068231 fastboot data load
326 23:44:09.068631 fastboot data verify
327 23:44:09.073460 verify result: 266
328 23:44:09.079045 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 23:44:09.079461 LPDDR4 probe
330 23:44:09.079850 ddr clk to 1584MHz
331 23:44:09.087002 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:44:09.124741
333 23:44:09.125157 dmc_version 0001
334 23:44:09.131782 Check phy result
335 23:44:09.137766 INFO : End of CA training
336 23:44:09.138183 INFO : End of initialization
337 23:44:09.143403 INFO : Training has run successfully!
338 23:44:09.143815 Check phy result
339 23:44:09.148974 INFO : End of initialization
340 23:44:09.149387 INFO : End of read enable training
341 23:44:09.152382 INFO : End of fine write leveling
342 23:44:09.157892 INFO : End of Write leveling coarse delay
343 23:44:09.163491 INFO : Training has run successfully!
344 23:44:09.163903 Check phy result
345 23:44:09.164326 INFO : End of initialization
346 23:44:09.169068 INFO : End of read dq deskew training
347 23:44:09.174690 INFO : End of MPR read delay center optimization
348 23:44:09.175104 INFO : End of write delay center optimization
349 23:44:09.180373 INFO : End of read delay center optimization
350 23:44:09.185905 INFO : End of max read latency training
351 23:44:09.186316 INFO : Training has run successfully!
352 23:44:09.191658 1D training succeed
353 23:44:09.197433 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:44:09.245595 Check phy result
355 23:44:09.246007 INFO : End of initialization
356 23:44:09.272197 INFO : End of 2D read delay Voltage center optimization
357 23:44:09.297241 INFO : End of 2D read delay Voltage center optimization
358 23:44:09.353871 INFO : End of 2D write delay Voltage center optimization
359 23:44:09.407931 INFO : End of 2D write delay Voltage center optimization
360 23:44:09.413507 INFO : Training has run successfully!
361 23:44:09.413936
362 23:44:09.414327 channel==0
363 23:44:09.419087 RxClkDly_Margin_A0==78 ps 8
364 23:44:09.419500 TxDqDly_Margin_A0==88 ps 9
365 23:44:09.422418 RxClkDly_Margin_A1==88 ps 9
366 23:44:09.422830 TxDqDly_Margin_A1==88 ps 9
367 23:44:09.427929 TrainedVREFDQ_A0==74
368 23:44:09.428375 TrainedVREFDQ_A1==74
369 23:44:09.428769 VrefDac_Margin_A0==24
370 23:44:09.433533 DeviceVref_Margin_A0==40
371 23:44:09.433945 VrefDac_Margin_A1==23
372 23:44:09.439157 DeviceVref_Margin_A1==40
373 23:44:09.439570
374 23:44:09.439960
375 23:44:09.440378 channel==1
376 23:44:09.440765 RxClkDly_Margin_A0==78 ps 8
377 23:44:09.444730 TxDqDly_Margin_A0==88 ps 9
378 23:44:09.445169 RxClkDly_Margin_A1==88 ps 9
379 23:44:09.450418 TxDqDly_Margin_A1==78 ps 8
380 23:44:09.450838 TrainedVREFDQ_A0==77
381 23:44:09.451228 TrainedVREFDQ_A1==75
382 23:44:09.455920 VrefDac_Margin_A0==22
383 23:44:09.456362 DeviceVref_Margin_A0==37
384 23:44:09.456749 VrefDac_Margin_A1==21
385 23:44:09.461514 DeviceVref_Margin_A1==39
386 23:44:09.461922
387 23:44:09.467146 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:44:09.467562
389 23:44:09.495125 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 23:44:09.500721 2D training succeed
391 23:44:09.506415 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:44:09.506831 auto size-- 65535DDR cs0 size: 2048MB
393 23:44:09.511930 DDR cs1 size: 2048MB
394 23:44:09.512381 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:44:09.517531 cs0 DataBus test pass
396 23:44:09.517945 cs1 DataBus test pass
397 23:44:09.518332 cs0 AddrBus test pass
398 23:44:09.523141 cs1 AddrBus test pass
399 23:44:09.523552
400 23:44:09.523941 100bdlr_step_size ps== 485
401 23:44:09.524376 result report
402 23:44:09.528730 boot times 0Enable ddr reg access
403 23:44:09.536121 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:44:09.549959 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 23:44:10.209338 bl2z: ptr: 05129330, size: 00001e40
406 23:44:10.218142 0.0;M3 CHK:0;cm4_sp_mode 0
407 23:44:10.218601 MVN_1=0x00000000
408 23:44:10.218994 MVN_2=0x00000000
409 23:44:10.229631 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 23:44:10.230127 OPS=0x04
411 23:44:10.230528 ring efuse init
412 23:44:10.235305 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 23:44:10.235742 [0.017354 Inits done]
414 23:44:10.236170 secure task start!
415 23:44:10.242564 high task start!
416 23:44:10.242980 low task start!
417 23:44:10.243371 run into bl31
418 23:44:10.251175 NOTICE: BL31: v1.3(release):4fc40b1
419 23:44:10.258986 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 23:44:10.259422 NOTICE: BL31: G12A normal boot!
421 23:44:10.274579 NOTICE: BL31: BL33 decompress pass
422 23:44:10.280264 ERROR: Error initializing runtime service opteed_fast
423 23:44:11.500718 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 23:44:11.501278 bl2_stage_init 0x01
425 23:44:11.501692 bl2_stage_init 0x81
426 23:44:11.506236 hw id: 0x0000 - pwm id 0x01
427 23:44:11.506669 bl2_stage_init 0xc1
428 23:44:11.507071 bl2_stage_init 0x02
429 23:44:11.507466
430 23:44:11.511717 L0:00000000
431 23:44:11.512200 L1:00000703
432 23:44:11.512608 L2:00008067
433 23:44:11.513004 L3:15000000
434 23:44:11.513394 S1:00000000
435 23:44:11.517314 B2:20282000
436 23:44:11.517746 B1:a0f83180
437 23:44:11.518144
438 23:44:11.518545 TE: 72487
439 23:44:11.518943
440 23:44:11.522992 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 23:44:11.523416
442 23:44:11.528547 Board ID = 1
443 23:44:11.528975 Set cpu clk to 24M
444 23:44:11.529375 Set clk81 to 24M
445 23:44:11.534140 Use GP1_pll as DSU clk.
446 23:44:11.534557 DSU clk: 1200 Mhz
447 23:44:11.534955 CPU clk: 1200 MHz
448 23:44:11.535348 Set clk81 to 166.6M
449 23:44:11.545413 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 23:44:11.545859 board id: 1
451 23:44:11.550955 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 23:44:11.562713 fw parse done
453 23:44:11.567694 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 23:44:11.611088 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 23:44:11.622882 PIEI prepare done
456 23:44:11.623314 fastboot data load
457 23:44:11.623718 fastboot data verify
458 23:44:11.628453 verify result: 266
459 23:44:11.634056 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 23:44:11.634480 LPDDR4 probe
461 23:44:11.634878 ddr clk to 1584MHz
462 23:44:12.998172 Load ddrfw from SPI, src: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 23:44:12.998806 bl2_stage_init 0x01
464 23:44:12.999285 bl2_stage_init 0x81
465 23:44:13.003790 hw id: 0x0000 - pwm id 0x01
466 23:44:13.004350 bl2_stage_init 0xc1
467 23:44:13.004791 bl2_stage_init 0x02
468 23:44:13.005232
469 23:44:13.009337 L0:00000000
470 23:44:13.009891 L1:00000703
471 23:44:13.010367 L2:00008067
472 23:44:13.011022 L3:15000000
473 23:44:13.011456 S1:00000000
474 23:44:13.012205 B2:20282000
475 23:44:13.016231 B1:a0f83180
476 23:44:13.016733
477 23:44:13.017180 TE: 70398
478 23:44:13.017617
479 23:44:13.021852 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 23:44:13.022351
481 23:44:13.022788 Board ID = 1
482 23:44:13.027388 Set cpu clk to 24M
483 23:44:13.027876 Set clk81 to 24M
484 23:44:13.028344 Use GP1_pll as DSU clk.
485 23:44:13.032983 DSU clk: 1200 Mhz
486 23:44:13.033468 CPU clk: 1200 MHz
487 23:44:13.033904 Set clk81 to 166.6M
488 23:44:13.038619 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 23:44:13.044191 board id: 1
490 23:44:13.049180 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 23:44:13.060222 fw parse done
492 23:44:13.065192 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 23:44:13.109292 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 23:44:13.120414 PIEI prepare done
495 23:44:13.120932 fastboot data load
496 23:44:13.121388 fastboot data verify
497 23:44:13.126037 verify result: 266
498 23:44:13.131614 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 23:44:13.132182 LPDDR4 probe
500 23:44:13.132641 ddr clk to 1584MHz
501 23:44:13.139533 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 23:44:13.177316
503 23:44:13.177833 dmc_version 0001
504 23:44:13.184387 Check phy result
505 23:44:13.190386 INFO : End of CA training
506 23:44:13.190886 INFO : End of initialization
507 23:44:13.196103 INFO : Training has run successfully!
508 23:44:13.196646 Check phy result
509 23:44:13.201586 INFO : End of initialization
510 23:44:13.202098 INFO : End of read enable training
511 23:44:13.204892 INFO : End of fine write leveling
512 23:44:13.210412 INFO : End of Write leveling coarse delay
513 23:44:13.216032 INFO : Training has run successfully!
514 23:44:13.216537 Check phy result
515 23:44:13.216986 INFO : End of initialization
516 23:44:13.221631 INFO : End of read dq deskew training
517 23:44:13.225019 INFO : End of MPR read delay center optimization
518 23:44:13.230543 INFO : End of write delay center optimization
519 23:44:13.236170 INFO : End of read delay center optimization
520 23:44:13.236668 INFO : End of max read latency training
521 23:44:13.241725 INFO : Training has run successfully!
522 23:44:13.242223 1D training succeed
523 23:44:13.250099 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 23:44:13.297350 Check phy result
525 23:44:13.297872 INFO : End of initialization
526 23:44:13.325629 INFO : End of 2D read delay Voltage center optimization
527 23:44:13.349381 INFO : End of 2D read delay Voltage center optimization
528 23:44:13.406510 INFO : End of 2D write delay Voltage center optimization
529 23:44:13.460498 INFO : End of 2D write delay Voltage center optimization
530 23:44:13.466104 INFO : Training has run successfully!
531 23:44:13.466646
532 23:44:13.467104 channel==0
533 23:44:13.471676 RxClkDly_Margin_A0==78 ps 8
534 23:44:13.472232 TxDqDly_Margin_A0==98 ps 10
535 23:44:13.477289 RxClkDly_Margin_A1==88 ps 9
536 23:44:13.477789 TxDqDly_Margin_A1==98 ps 10
537 23:44:13.478241 TrainedVREFDQ_A0==74
538 23:44:13.482930 TrainedVREFDQ_A1==74
539 23:44:13.483430 VrefDac_Margin_A0==23
540 23:44:13.483880 DeviceVref_Margin_A0==40
541 23:44:13.488487 VrefDac_Margin_A1==22
542 23:44:13.488984 DeviceVref_Margin_A1==40
543 23:44:13.489434
544 23:44:13.489878
545 23:44:13.494102 channel==1
546 23:44:13.494594 RxClkDly_Margin_A0==78 ps 8
547 23:44:13.495043 TxDqDly_Margin_A0==98 ps 10
548 23:44:13.499678 RxClkDly_Margin_A1==88 ps 9
549 23:44:13.500206 TxDqDly_Margin_A1==88 ps 9
550 23:44:13.505295 TrainedVREFDQ_A0==78
551 23:44:13.505795 TrainedVREFDQ_A1==75
552 23:44:13.506245 VrefDac_Margin_A0==23
553 23:44:13.510918 DeviceVref_Margin_A0==36
554 23:44:13.511408 VrefDac_Margin_A1==22
555 23:44:13.516474 DeviceVref_Margin_A1==39
556 23:44:13.516975
557 23:44:13.517425 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 23:44:13.517863
559 23:44:13.550100 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000019 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 23:44:13.550632 2D training succeed
561 23:44:13.555682 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 23:44:13.561281 auto size-- 65535DDR cs0 size: 2048MB
563 23:44:13.561782 DDR cs1 size: 2048MB
564 23:44:13.566908 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 23:44:13.567406 cs0 DataBus test pass
566 23:44:13.572486 cs1 DataBus test pass
567 23:44:13.572978 cs0 AddrBus test pass
568 23:44:13.573423 cs1 AddrBus test pass
569 23:44:13.573862
570 23:44:13.578103 100bdlr_step_size ps== 471
571 23:44:13.578616 result report
572 23:44:13.583705 boot times 0Enable ddr reg access
573 23:44:13.588048 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 23:44:13.601960 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 23:44:14.262398 bl2z: ptr: 05129330, size: 00001e40
576 23:44:14.271729 0.0;M3 CHK:0;cm4_sp_mode 0
577 23:44:14.272293 MVN_1=0x00000000
578 23:44:14.272745 MVN_2=0x00000000
579 23:44:14.283177 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 23:44:14.283685 OPS=0x04
581 23:44:14.284172 ring efuse init
582 23:44:14.286153 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 23:44:14.292128 [0.017354 Inits done]
584 23:44:14.292626 secure task start!
585 23:44:14.293074 high task start!
586 23:44:14.293512 low task start!
587 23:44:14.295490 run into bl31
588 23:44:14.305145 NOTICE: BL31: v1.3(release):4fc40b1
589 23:44:14.312830 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 23:44:14.313335 NOTICE: BL31: G12A normal boot!
591 23:44:14.328523 NOTICE: BL31: BL33 decompress pass
592 23:44:14.335588 ERROR: Error initializing runtime service opteed_fast
593 23:44:15.547946 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 23:44:15.548584 bl2_stage_init 0x01
595 23:44:15.549068 bl2_stage_init 0x81
596 23:44:15.553581 hw id: 0x0000 - pwm id 0x01
597 23:44:15.554106 bl2_stage_init 0xc1
598 23:44:15.559195 bl2_stage_init 0x02
599 23:44:15.559695
600 23:44:15.560199 L0:00000000
601 23:44:15.560647 L1:00000703
602 23:44:15.561084 L2:00008067
603 23:44:15.561518 L3:15000000
604 23:44:15.564719 S1:00000000
605 23:44:15.565222 B2:20282000
606 23:44:15.565668 B1:a0f83180
607 23:44:15.566106
608 23:44:15.566542 TE: 70804
609 23:44:15.566976
610 23:44:15.570345 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 23:44:15.570856
612 23:44:15.575924 Board ID = 1
613 23:44:15.576453 Set cpu clk to 24M
614 23:44:15.576901 Set clk81 to 24M
615 23:44:15.581516 Use GP1_pll as DSU clk.
616 23:44:15.582015 DSU clk: 1200 Mhz
617 23:44:15.582469 CPU clk: 1200 MHz
618 23:44:15.587194 Set clk81 to 166.6M
619 23:44:15.592743 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 23:44:15.593247 board id: 1
621 23:44:15.599931 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 23:44:15.610838 fw parse done
623 23:44:15.616771 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 23:44:15.659904 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 23:44:15.671036 PIEI prepare done
626 23:44:15.671544 fastboot data load
627 23:44:15.672033 fastboot data verify
628 23:44:15.676634 verify result: 266
629 23:44:15.682353 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 23:44:15.682859 LPDDR4 probe
631 23:44:15.683308 ddr clk to 1584MHz
632 23:44:15.690230 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 23:44:15.727921
634 23:44:15.728455 dmc_version 0001
635 23:44:15.734978 Check phy result
636 23:44:15.740970 INFO : End of CA training
637 23:44:15.741471 INFO : End of initialization
638 23:44:15.746581 INFO : Training has run successfully!
639 23:44:15.747081 Check phy result
640 23:44:15.752249 INFO : End of initialization
641 23:44:15.752749 INFO : End of read enable training
642 23:44:15.757776 INFO : End of fine write leveling
643 23:44:15.763411 INFO : End of Write leveling coarse delay
644 23:44:15.763908 INFO : Training has run successfully!
645 23:44:15.764407 Check phy result
646 23:44:15.768992 INFO : End of initialization
647 23:44:15.769490 INFO : End of read dq deskew training
648 23:44:15.774573 INFO : End of MPR read delay center optimization
649 23:44:15.780255 INFO : End of write delay center optimization
650 23:44:15.785767 INFO : End of read delay center optimization
651 23:44:15.786263 INFO : End of max read latency training
652 23:44:15.791366 INFO : Training has run successfully!
653 23:44:15.791862 1D training succeed
654 23:44:15.800514 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 23:44:15.848819 Check phy result
656 23:44:15.849317 INFO : End of initialization
657 23:44:15.876211 INFO : End of 2D read delay Voltage center optimization
658 23:44:15.900356 INFO : End of 2D read delay Voltage center optimization
659 23:44:15.956936 INFO : End of 2D write delay Voltage center optimization
660 23:44:16.010885 INFO : End of 2D write delay Voltage center optimization
661 23:44:16.016498 INFO : Training has run successfully!
662 23:44:16.016999
663 23:44:16.017452 channel==0
664 23:44:16.022099 RxClkDly_Margin_A0==78 ps 8
665 23:44:16.022595 TxDqDly_Margin_A0==98 ps 10
666 23:44:16.027687 RxClkDly_Margin_A1==88 ps 9
667 23:44:16.028240 TxDqDly_Margin_A1==98 ps 10
668 23:44:16.028698 TrainedVREFDQ_A0==75
669 23:44:16.033402 TrainedVREFDQ_A1==75
670 23:44:16.033905 VrefDac_Margin_A0==22
671 23:44:16.034358 DeviceVref_Margin_A0==39
672 23:44:16.038905 VrefDac_Margin_A1==22
673 23:44:16.039401 DeviceVref_Margin_A1==39
674 23:44:16.039851
675 23:44:16.040342
676 23:44:16.044506 channel==1
677 23:44:16.045004 RxClkDly_Margin_A0==78 ps 8
678 23:44:16.045454 TxDqDly_Margin_A0==98 ps 10
679 23:44:16.050096 RxClkDly_Margin_A1==88 ps 9
680 23:44:16.050593 TxDqDly_Margin_A1==78 ps 8
681 23:44:16.055700 TrainedVREFDQ_A0==78
682 23:44:16.056232 TrainedVREFDQ_A1==75
683 23:44:16.056686 VrefDac_Margin_A0==22
684 23:44:16.061408 DeviceVref_Margin_A0==36
685 23:44:16.061905 VrefDac_Margin_A1==22
686 23:44:16.066881 DeviceVref_Margin_A1==39
687 23:44:16.067389
688 23:44:16.067843 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 23:44:16.068325
690 23:44:16.100431 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
691 23:44:16.100962 2D training succeed
692 23:44:16.106088 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 23:44:16.111691 auto size-- 65535DDR cs0 size: 2048MB
694 23:44:16.112222 DDR cs1 size: 2048MB
695 23:44:16.117411 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 23:44:16.117910 cs0 DataBus test pass
697 23:44:16.122896 cs1 DataBus test pass
698 23:44:16.123391 cs0 AddrBus test pass
699 23:44:16.123837 cs1 AddrBus test pass
700 23:44:16.124318
701 23:44:16.128507 100bdlr_step_size ps== 471
702 23:44:16.129016 result report
703 23:44:16.134074 boot times 0Enable ddr reg access
704 23:44:16.139344 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 23:44:16.153184 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 23:44:16.812536 bl2z: ptr: 05129330, size: 00001e40
707 23:44:16.821817 0.0;M3 CHK:0;cm4_sp_mode 0
708 23:44:16.822338 MVN_1=0x00000000
709 23:44:16.822792 MVN_2=0x00000000
710 23:44:16.833257 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 23:44:16.833765 OPS=0x04
712 23:44:16.834224 ring efuse init
713 23:44:16.838922 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 23:44:16.839434 [0.017354 Inits done]
715 23:44:16.839885 secure task start!
716 23:44:16.846875 high task start!
717 23:44:16.847384 low task start!
718 23:44:16.847867 run into bl31
719 23:44:16.855576 NOTICE: BL31: v1.3(release):4fc40b1
720 23:44:16.863329 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 23:44:16.863818 NOTICE: BL31: G12A normal boot!
722 23:44:16.878799 NOTICE: BL31: BL33 decompress pass
723 23:44:16.884468 ERROR: Error initializing runtime service opteed_fast
724 23:44:17.678593
725 23:44:17.679100
726 23:44:17.684087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 23:44:17.684588
728 23:44:17.687614 Model: Libre Computer AML-S905D3-CC Solitude
729 23:44:17.834258 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 23:44:17.849799 DRAM: 2 GiB (effective 3.8 GiB)
731 23:44:17.950838 Core: 406 devices, 33 uclasses, devicetree: separate
732 23:44:17.956615 WDT: Not starting watchdog@f0d0
733 23:44:17.981710 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 23:44:17.993988 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 23:44:17.998873 ** Bad device specification mmc 0 **
736 23:44:18.008840 Card did not respond to voltage select! : -110
737 23:44:18.016581 ** Bad device specification mmc 0 **
738 23:44:18.017123 Couldn't find partition mmc 0
739 23:44:18.024887 Card did not respond to voltage select! : -110
740 23:44:18.030409 ** Bad device specification mmc 0 **
741 23:44:18.030882 Couldn't find partition mmc 0
742 23:44:18.035469 Error: could not access storage.
743 23:44:18.332920 Net: eth0: ethernet@ff3f0000
744 23:44:18.333466 starting USB...
745 23:44:18.577543 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 23:44:18.578059 Starting the controller
747 23:44:18.584568 USB XHCI 1.10
748 23:44:20.138076 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 23:44:20.146410 scanning usb for storage devices... 0 Storage Device(s) found
751 23:44:20.197999 Hit any key to stop autoboot: 1
752 23:44:20.198828 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
753 23:44:20.199481 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
754 23:44:20.200063 Setting prompt string to ['=>']
755 23:44:20.200606 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
756 23:44:20.212436 0
757 23:44:20.213372 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 23:44:20.314650 => setenv autoload no
760 23:44:20.315315 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
761 23:44:20.320555 setenv autoload no
763 23:44:20.422151 => setenv initrd_high 0xffffffff
764 23:44:20.422810 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 23:44:20.427349 setenv initrd_high 0xffffffff
767 23:44:20.528871 => setenv fdt_high 0xffffffff
768 23:44:20.529519 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 23:44:20.534225 setenv fdt_high 0xffffffff
771 23:44:20.635764 => dhcp
772 23:44:20.636469 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 23:44:20.640880 dhcp
774 23:44:21.696707 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 23:44:21.697352 Speed: 1000, full duplex
776 23:44:21.697825 BOOTP broadcast 1
777 23:44:21.944521 BOOTP broadcast 2
778 23:44:21.959689 DHCP client bound to address 192.168.6.21 (263 ms)
780 23:44:22.061328 => setenv serverip 192.168.6.2
781 23:44:22.062019 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
782 23:44:22.065774 setenv serverip 192.168.6.2
784 23:44:22.167273 => tftpboot 0x01080000 915254/tftp-deploy-_zisni3g/kernel/uImage
785 23:44:22.167912 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
786 23:44:22.174523 tftpboot 0x01080000 915254/tftp-deploy-_zisni3g/kernel/uImage
787 23:44:22.175040 Speed: 1000, full duplex
788 23:44:22.175499 Using ethernet@ff3f0000 device
789 23:44:22.180191 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 23:44:22.185583 Filename '915254/tftp-deploy-_zisni3g/kernel/uImage'.
791 23:44:22.189549 Load address: 0x1080000
792 23:44:24.523015 Loading: *################################################## 36.1 MiB
793 23:44:24.523667 15.5 MiB/s
794 23:44:24.524199 done
795 23:44:24.530186 Bytes transferred = 37878336 (241fa40 hex)
797 23:44:24.631943 => tftpboot 0x08000000 915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot
798 23:44:24.632803 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
799 23:44:24.639479 tftpboot 0x08000000 915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot
800 23:44:24.639973 Speed: 1000, full duplex
801 23:44:24.640446 Using ethernet@ff3f0000 device
802 23:44:24.644924 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 23:44:24.654761 Filename '915254/tftp-deploy-_zisni3g/ramdisk/ramdisk.cpio.gz.uboot'.
804 23:44:24.655244 Load address: 0x8000000
805 23:44:26.360741 Loading: *################################################# UDP wrong checksum 00000005 0000d4c7
806 23:44:29.528155 UDP wrong checksum 000000ff 0000ad77
807 23:44:29.578112 UDP wrong checksum 000000ff 0000386a
808 23:44:31.361670 T UDP wrong checksum 00000005 0000d4c7
809 23:44:41.363663 T T UDP wrong checksum 00000005 0000d4c7
810 23:44:47.736943 T UDP wrong checksum 00000005 0000767a
811 23:45:01.367708 T T T UDP wrong checksum 00000005 0000d4c7
812 23:45:21.372465 T T T
813 23:45:21.373098 Retry count exceeded; starting again
815 23:45:21.374664 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
818 23:45:21.376777 end: 2.4 uboot-commands (duration 00:01:20) [common]
820 23:45:21.378312 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 23:45:21.379411 end: 2 uboot-action (duration 00:01:20) [common]
824 23:45:21.381102 Cleaning after the job
825 23:45:21.381689 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/ramdisk
826 23:45:21.383037 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/kernel
827 23:45:21.428321 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/dtb
828 23:45:21.429177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915254/tftp-deploy-_zisni3g/modules
829 23:45:21.450938 start: 4.1 power-off (timeout 00:00:30) [common]
830 23:45:21.451613 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
831 23:45:21.485606 >> OK - accepted request
832 23:45:21.487491 Returned 0 in 0 seconds
833 23:45:21.588357 end: 4.1 power-off (duration 00:00:00) [common]
835 23:45:21.589982 start: 4.2 read-feedback (timeout 00:10:00) [common]
836 23:45:21.591064 Listened to connection for namespace 'common' for up to 1s
837 23:45:22.591875 Finalising connection for namespace 'common'
838 23:45:22.592704 Disconnecting from shell: Finalise
839 23:45:22.593278 =>
840 23:45:22.694375 end: 4.2 read-feedback (duration 00:00:01) [common]
841 23:45:22.695150 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915254
842 23:45:23.008846 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915254
843 23:45:23.009460 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.