Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:03:07.246096 lava-dispatcher, installed at version: 2024.01
2 01:03:07.246861 start: 0 validate
3 01:03:07.247341 Start time: 2024-10-31 01:03:07.247311+00:00 (UTC)
4 01:03:07.247881 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:03:07.248488 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:03:07.288980 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:03:07.289519 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 01:03:07.320379 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:03:07.321017 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:03:07.351878 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:03:07.352465 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
12 01:03:07.388942 validate duration: 0.14
14 01:03:07.389769 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:03:07.390095 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:03:07.390387 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:03:07.390957 Not decompressing ramdisk as can be used compressed.
18 01:03:07.391394 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:03:07.391633 saving as /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/ramdisk/rootfs.cpio.gz
20 01:03:07.391886 total size: 47897469 (45 MB)
21 01:03:07.427765 progress 0 % (0 MB)
22 01:03:07.459073 progress 5 % (2 MB)
23 01:03:07.489182 progress 10 % (4 MB)
24 01:03:07.519580 progress 15 % (6 MB)
25 01:03:07.549745 progress 20 % (9 MB)
26 01:03:07.580107 progress 25 % (11 MB)
27 01:03:07.610047 progress 30 % (13 MB)
28 01:03:07.640398 progress 35 % (16 MB)
29 01:03:07.671666 progress 40 % (18 MB)
30 01:03:07.702338 progress 45 % (20 MB)
31 01:03:07.733800 progress 50 % (22 MB)
32 01:03:07.764303 progress 55 % (25 MB)
33 01:03:07.795048 progress 60 % (27 MB)
34 01:03:07.824974 progress 65 % (29 MB)
35 01:03:07.855285 progress 70 % (32 MB)
36 01:03:07.885368 progress 75 % (34 MB)
37 01:03:07.915047 progress 80 % (36 MB)
38 01:03:07.945637 progress 85 % (38 MB)
39 01:03:07.976071 progress 90 % (41 MB)
40 01:03:08.006680 progress 95 % (43 MB)
41 01:03:08.036595 progress 100 % (45 MB)
42 01:03:08.037373 45 MB downloaded in 0.65 s (70.77 MB/s)
43 01:03:08.037929 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:03:08.038806 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:03:08.039098 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:03:08.039370 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:03:08.039844 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/kernel/Image
49 01:03:08.040122 saving as /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/kernel/Image
50 01:03:08.040334 total size: 37878272 (36 MB)
51 01:03:08.040543 No compression specified
52 01:03:08.079654 progress 0 % (0 MB)
53 01:03:08.103122 progress 5 % (1 MB)
54 01:03:08.126733 progress 10 % (3 MB)
55 01:03:08.149969 progress 15 % (5 MB)
56 01:03:08.173104 progress 20 % (7 MB)
57 01:03:08.196105 progress 25 % (9 MB)
58 01:03:08.220008 progress 30 % (10 MB)
59 01:03:08.243055 progress 35 % (12 MB)
60 01:03:08.266162 progress 40 % (14 MB)
61 01:03:08.289407 progress 45 % (16 MB)
62 01:03:08.312463 progress 50 % (18 MB)
63 01:03:08.335569 progress 55 % (19 MB)
64 01:03:08.358767 progress 60 % (21 MB)
65 01:03:08.381835 progress 65 % (23 MB)
66 01:03:08.404962 progress 70 % (25 MB)
67 01:03:08.427921 progress 75 % (27 MB)
68 01:03:08.450960 progress 80 % (28 MB)
69 01:03:08.474130 progress 85 % (30 MB)
70 01:03:08.497274 progress 90 % (32 MB)
71 01:03:08.520698 progress 95 % (34 MB)
72 01:03:08.543111 progress 100 % (36 MB)
73 01:03:08.543878 36 MB downloaded in 0.50 s (71.74 MB/s)
74 01:03:08.544387 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:03:08.545190 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:03:08.545462 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:03:08.545726 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:03:08.546214 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:03:08.546487 saving as /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:03:08.546697 total size: 54703 (0 MB)
82 01:03:08.546906 No compression specified
83 01:03:08.581713 progress 59 % (0 MB)
84 01:03:08.582558 progress 100 % (0 MB)
85 01:03:08.583100 0 MB downloaded in 0.04 s (1.43 MB/s)
86 01:03:08.583554 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:03:08.584398 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:03:08.584661 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:03:08.584924 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:03:08.585378 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/modules.tar.xz
92 01:03:08.585616 saving as /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/modules/modules.tar
93 01:03:08.585819 total size: 11755844 (11 MB)
94 01:03:08.586028 Using unxz to decompress xz
95 01:03:08.619564 progress 0 % (0 MB)
96 01:03:08.686628 progress 5 % (0 MB)
97 01:03:08.762578 progress 10 % (1 MB)
98 01:03:08.843542 progress 15 % (1 MB)
99 01:03:08.926365 progress 20 % (2 MB)
100 01:03:09.003969 progress 25 % (2 MB)
101 01:03:09.085117 progress 30 % (3 MB)
102 01:03:09.162204 progress 35 % (3 MB)
103 01:03:09.244104 progress 40 % (4 MB)
104 01:03:09.330040 progress 45 % (5 MB)
105 01:03:09.411891 progress 50 % (5 MB)
106 01:03:09.495779 progress 55 % (6 MB)
107 01:03:09.579922 progress 60 % (6 MB)
108 01:03:09.663318 progress 65 % (7 MB)
109 01:03:09.745675 progress 70 % (7 MB)
110 01:03:09.827207 progress 75 % (8 MB)
111 01:03:09.910370 progress 80 % (9 MB)
112 01:03:09.986059 progress 85 % (9 MB)
113 01:03:10.059187 progress 90 % (10 MB)
114 01:03:10.157266 progress 95 % (10 MB)
115 01:03:10.253410 progress 100 % (11 MB)
116 01:03:10.267030 11 MB downloaded in 1.68 s (6.67 MB/s)
117 01:03:10.268068 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:03:10.269846 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:03:10.270423 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:03:10.270996 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:03:10.271538 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:03:10.272116 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:03:10.273211 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr
125 01:03:10.274135 makedir: /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin
126 01:03:10.274842 makedir: /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/tests
127 01:03:10.275607 makedir: /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/results
128 01:03:10.276324 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-add-keys
129 01:03:10.277378 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-add-sources
130 01:03:10.278472 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-background-process-start
131 01:03:10.279515 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-background-process-stop
132 01:03:10.280635 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-common-functions
133 01:03:10.281709 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-echo-ipv4
134 01:03:10.282710 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-install-packages
135 01:03:10.283688 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-installed-packages
136 01:03:10.284706 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-os-build
137 01:03:10.285694 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-probe-channel
138 01:03:10.286735 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-probe-ip
139 01:03:10.287726 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-target-ip
140 01:03:10.288796 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-target-mac
141 01:03:10.289789 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-target-storage
142 01:03:10.290787 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-case
143 01:03:10.291773 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-event
144 01:03:10.292836 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-feedback
145 01:03:10.293829 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-raise
146 01:03:10.294881 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-reference
147 01:03:10.295879 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-runner
148 01:03:10.296956 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-set
149 01:03:10.297949 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-test-shell
150 01:03:10.298980 Updating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-install-packages (oe)
151 01:03:10.300171 Updating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/bin/lava-installed-packages (oe)
152 01:03:10.301261 Creating /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/environment
153 01:03:10.302075 LAVA metadata
154 01:03:10.302612 - LAVA_JOB_ID=915239
155 01:03:10.303086 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:03:10.303804 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:03:10.305776 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:03:10.306444 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:03:10.306902 skipped lava-vland-overlay
160 01:03:10.307439 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:03:10.308023 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:03:10.308498 skipped lava-multinode-overlay
163 01:03:10.309034 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:03:10.309589 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:03:10.310113 Loading test definitions
166 01:03:10.310716 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:03:10.311202 Using /lava-915239 at stage 0
168 01:03:10.313520 uuid=915239_1.5.2.4.1 testdef=None
169 01:03:10.314165 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:03:10.314734 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:03:10.318261 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:03:10.319976 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:03:10.324152 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:03:10.325810 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:03:10.329024 runner path: /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/0/tests/0_igt-gpu-panfrost test_uuid 915239_1.5.2.4.1
178 01:03:10.329666 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:03:10.330507 Creating lava-test-runner.conf files
181 01:03:10.330718 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915239/lava-overlay-299u7rkr/lava-915239/0 for stage 0
182 01:03:10.331055 - 0_igt-gpu-panfrost
183 01:03:10.331412 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:03:10.331704 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:03:10.355156 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:03:10.355576 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:03:10.355846 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:03:10.356143 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:03:10.356412 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:03:17.154176 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 01:03:17.154649 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 01:03:17.154898 extracting modules file /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk
193 01:03:18.584429 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:03:18.584907 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 01:03:18.585184 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915239/compress-overlay-91futu00/overlay-1.5.2.5.tar.gz to ramdisk
196 01:03:18.585399 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915239/compress-overlay-91futu00/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk
197 01:03:18.615368 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:03:18.615736 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 01:03:18.616044 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 01:03:18.616280 Converting downloaded kernel to a uImage
201 01:03:18.616579 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/kernel/Image /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/kernel/uImage
202 01:03:19.022620 output: Image Name:
203 01:03:19.023042 output: Created: Thu Oct 31 01:03:18 2024
204 01:03:19.023249 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:03:19.023453 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
206 01:03:19.023656 output: Load Address: 01080000
207 01:03:19.023856 output: Entry Point: 01080000
208 01:03:19.024095 output:
209 01:03:19.024436 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:03:19.024702 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:03:19.024971 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:03:19.025224 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:03:19.025481 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:03:19.025736 Building ramdisk /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk
215 01:03:25.639632 >> 509009 blocks
216 01:03:46.366741 Adding RAMdisk u-boot header.
217 01:03:46.367605 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk.cpio.gz.uboot
218 01:03:47.076824 output: Image Name:
219 01:03:47.077239 output: Created: Thu Oct 31 01:03:46 2024
220 01:03:47.077447 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:03:47.077649 output: Data Size: 66430939 Bytes = 64873.96 KiB = 63.35 MiB
222 01:03:47.077850 output: Load Address: 00000000
223 01:03:47.078052 output: Entry Point: 00000000
224 01:03:47.078247 output:
225 01:03:47.078871 rename /var/lib/lava/dispatcher/tmp/915239/extract-overlay-ramdisk-z8eo7qcx/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot
226 01:03:47.079286 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 01:03:47.079568 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 01:03:47.079837 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 01:03:47.080205 No LXC device requested
230 01:03:47.080766 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:03:47.081326 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 01:03:47.081866 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:03:47.082315 Checking files for TFTP limit of 4294967296 bytes.
234 01:03:47.085239 end: 1 tftp-deploy (duration 00:00:40) [common]
235 01:03:47.085871 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:03:47.086445 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:03:47.086993 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:03:47.087548 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:03:47.088152 Using kernel file from prepare-kernel: 915239/tftp-deploy-f3c6lltj/kernel/uImage
240 01:03:47.088843 substitutions:
241 01:03:47.089298 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:03:47.089746 - {DTB_ADDR}: 0x01070000
243 01:03:47.090189 - {DTB}: 915239/tftp-deploy-f3c6lltj/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:03:47.090632 - {INITRD}: 915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot
245 01:03:47.091074 - {KERNEL_ADDR}: 0x01080000
246 01:03:47.091510 - {KERNEL}: 915239/tftp-deploy-f3c6lltj/kernel/uImage
247 01:03:47.091953 - {LAVA_MAC}: None
248 01:03:47.092462 - {PRESEED_CONFIG}: None
249 01:03:47.092905 - {PRESEED_LOCAL}: None
250 01:03:47.093341 - {RAMDISK_ADDR}: 0x08000000
251 01:03:47.093774 - {RAMDISK}: 915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot
252 01:03:47.094214 - {ROOT_PART}: None
253 01:03:47.094649 - {ROOT}: None
254 01:03:47.095084 - {SERVER_IP}: 192.168.6.2
255 01:03:47.095523 - {TEE_ADDR}: 0x83000000
256 01:03:47.095958 - {TEE}: None
257 01:03:47.096422 Parsed boot commands:
258 01:03:47.096844 - setenv autoload no
259 01:03:47.097274 - setenv initrd_high 0xffffffff
260 01:03:47.097707 - setenv fdt_high 0xffffffff
261 01:03:47.098136 - dhcp
262 01:03:47.098569 - setenv serverip 192.168.6.2
263 01:03:47.098999 - tftpboot 0x01080000 915239/tftp-deploy-f3c6lltj/kernel/uImage
264 01:03:47.099435 - tftpboot 0x08000000 915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot
265 01:03:47.099867 - tftpboot 0x01070000 915239/tftp-deploy-f3c6lltj/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:03:47.100331 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:03:47.100768 - bootm 0x01080000 0x08000000 0x01070000
268 01:03:47.101327 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:03:47.102967 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:03:47.103457 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:03:47.118827 Setting prompt string to ['lava-test: # ']
273 01:03:47.120468 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:03:47.121115 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:03:47.121700 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:03:47.122257 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:03:47.123517 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:03:47.163598 >> OK - accepted request
279 01:03:47.165521 Returned 0 in 0 seconds
280 01:03:47.266760 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:03:47.268671 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:03:47.269306 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:03:47.269862 Setting prompt string to ['Hit any key to stop autoboot']
285 01:03:47.270362 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:03:47.272155 Trying 192.168.56.21...
287 01:03:47.272738 Connected to conserv1.
288 01:03:47.273224 Escape character is '^]'.
289 01:03:47.273683
290 01:03:47.274155 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:03:47.274628
292 01:03:59.381912 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:03:59.382575 bl2_stage_init 0x01
294 01:03:59.383043 bl2_stage_init 0x81
295 01:03:59.387267 hw id: 0x0000 - pwm id 0x01
296 01:03:59.387797 bl2_stage_init 0xc1
297 01:03:59.388310 bl2_stage_init 0x02
298 01:03:59.388760
299 01:03:59.392857 L0:00000000
300 01:03:59.393335 L1:20000703
301 01:03:59.393763 L2:00008067
302 01:03:59.394188 L3:14000000
303 01:03:59.398526 B2:00402000
304 01:03:59.398985 B1:e0f83180
305 01:03:59.399425
306 01:03:59.399854 TE: 58124
307 01:03:59.400321
308 01:03:59.404052 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:03:59.404528
310 01:03:59.404958 Board ID = 1
311 01:03:59.409689 Set A53 clk to 24M
312 01:03:59.410151 Set A73 clk to 24M
313 01:03:59.410578 Set clk81 to 24M
314 01:03:59.415251 A53 clk: 1200 MHz
315 01:03:59.415710 A73 clk: 1200 MHz
316 01:03:59.416175 CLK81: 166.6M
317 01:03:59.416601 smccc: 00012a92
318 01:03:59.420966 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:03:59.426589 board id: 1
320 01:03:59.432372 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:03:59.442847 fw parse done
322 01:03:59.448781 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:03:59.491468 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:03:59.502397 PIEI prepare done
325 01:03:59.502871 fastboot data load
326 01:03:59.503304 fastboot data verify
327 01:03:59.507890 verify result: 266
328 01:03:59.513600 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:03:59.514121 LPDDR4 probe
330 01:03:59.514555 ddr clk to 1584MHz
331 01:03:59.521555 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:03:59.558779
333 01:03:59.559264 dmc_version 0001
334 01:03:59.565487 Check phy result
335 01:03:59.571410 INFO : End of CA training
336 01:03:59.571873 INFO : End of initialization
337 01:03:59.576944 INFO : Training has run successfully!
338 01:03:59.577464 Check phy result
339 01:03:59.582533 INFO : End of initialization
340 01:03:59.582998 INFO : End of read enable training
341 01:03:59.588126 INFO : End of fine write leveling
342 01:03:59.593731 INFO : End of Write leveling coarse delay
343 01:03:59.594198 INFO : Training has run successfully!
344 01:03:59.594634 Check phy result
345 01:03:59.599453 INFO : End of initialization
346 01:03:59.599921 INFO : End of read dq deskew training
347 01:03:59.604927 INFO : End of MPR read delay center optimization
348 01:03:59.610551 INFO : End of write delay center optimization
349 01:03:59.616122 INFO : End of read delay center optimization
350 01:03:59.616585 INFO : End of max read latency training
351 01:03:59.621724 INFO : Training has run successfully!
352 01:03:59.622185 1D training succeed
353 01:03:59.630890 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:03:59.678569 Check phy result
355 01:03:59.678900 INFO : End of initialization
356 01:03:59.700099 INFO : End of 2D read delay Voltage center optimization
357 01:03:59.719425 INFO : End of 2D read delay Voltage center optimization
358 01:03:59.771261 INFO : End of 2D write delay Voltage center optimization
359 01:03:59.820496 INFO : End of 2D write delay Voltage center optimization
360 01:03:59.826072 INFO : Training has run successfully!
361 01:03:59.826539
362 01:03:59.826973 channel==0
363 01:03:59.831655 RxClkDly_Margin_A0==88 ps 9
364 01:03:59.832154 TxDqDly_Margin_A0==98 ps 10
365 01:03:59.837326 RxClkDly_Margin_A1==88 ps 9
366 01:03:59.837784 TxDqDly_Margin_A1==98 ps 10
367 01:03:59.838220 TrainedVREFDQ_A0==74
368 01:03:59.842860 TrainedVREFDQ_A1==75
369 01:03:59.843331 VrefDac_Margin_A0==25
370 01:03:59.843757 DeviceVref_Margin_A0==40
371 01:03:59.848472 VrefDac_Margin_A1==25
372 01:03:59.848932 DeviceVref_Margin_A1==39
373 01:03:59.849360
374 01:03:59.849792
375 01:03:59.854037 channel==1
376 01:03:59.854493 RxClkDly_Margin_A0==98 ps 10
377 01:03:59.854924 TxDqDly_Margin_A0==88 ps 9
378 01:03:59.859664 RxClkDly_Margin_A1==88 ps 9
379 01:03:59.860163 TxDqDly_Margin_A1==88 ps 9
380 01:03:59.865261 TrainedVREFDQ_A0==77
381 01:03:59.865729 TrainedVREFDQ_A1==77
382 01:03:59.866163 VrefDac_Margin_A0==23
383 01:03:59.870861 DeviceVref_Margin_A0==37
384 01:03:59.871319 VrefDac_Margin_A1==24
385 01:03:59.876460 DeviceVref_Margin_A1==37
386 01:03:59.876910
387 01:03:59.877345 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:03:59.877777
389 01:03:59.910009 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 01:03:59.910554 2D training succeed
391 01:03:59.915654 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:03:59.921252 auto size-- 65535DDR cs0 size: 2048MB
393 01:03:59.921717 DDR cs1 size: 2048MB
394 01:03:59.926876 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:03:59.927339 cs0 DataBus test pass
396 01:03:59.932465 cs1 DataBus test pass
397 01:03:59.932929 cs0 AddrBus test pass
398 01:03:59.933361 cs1 AddrBus test pass
399 01:03:59.933787
400 01:03:59.938052 100bdlr_step_size ps== 420
401 01:03:59.938519 result report
402 01:03:59.943664 boot times 0Enable ddr reg access
403 01:03:59.948925 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:03:59.962375 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:04:00.534499 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:04:00.535179 MVN_1=0x00000000
407 01:04:00.539942 MVN_2=0x00000000
408 01:04:00.545699 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:04:00.546219 OPS=0x10
410 01:04:00.546670 ring efuse init
411 01:04:00.547106 chipver efuse init
412 01:04:00.551292 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:04:00.556896 [0.018961 Inits done]
414 01:04:00.557424 secure task start!
415 01:04:00.557862 high task start!
416 01:04:00.561532 low task start!
417 01:04:00.562073 run into bl31
418 01:04:00.568201 NOTICE: BL31: v1.3(release):4fc40b1
419 01:04:00.575928 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:04:00.576487 NOTICE: BL31: G12A normal boot!
421 01:04:00.601507 NOTICE: BL31: BL33 decompress pass
422 01:04:00.607103 ERROR: Error initializing runtime service opteed_fast
423 01:04:01.840049
424 01:04:01.840707
425 01:04:01.848418 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:04:01.848924
427 01:04:01.849387 Model: Libre Computer AML-A311D-CC Alta
428 01:04:02.056996 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:04:02.080258 DRAM: 2 GiB (effective 3.8 GiB)
430 01:04:02.223350 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:04:02.229086 WDT: Not starting watchdog@f0d0
432 01:04:02.261457 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:04:02.273878 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:04:02.278802 ** Bad device specification mmc 0 **
435 01:04:02.289120 Card did not respond to voltage select! : -110
436 01:04:02.296786 ** Bad device specification mmc 0 **
437 01:04:02.297337 Couldn't find partition mmc 0
438 01:04:02.305129 Card did not respond to voltage select! : -110
439 01:04:02.310628 ** Bad device specification mmc 0 **
440 01:04:02.311189 Couldn't find partition mmc 0
441 01:04:02.315626 Error: could not access storage.
442 01:04:03.582340 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 01:04:03.583033 bl2_stage_init 0x01
444 01:04:03.583535 bl2_stage_init 0x81
445 01:04:03.587959 hw id: 0x0000 - pwm id 0x01
446 01:04:03.588550 bl2_stage_init 0xc1
447 01:04:03.589237 bl2_stage_init 0x02
448 01:04:03.589749
449 01:04:03.593451 L0:00000000
450 01:04:03.593933 L1:20000703
451 01:04:03.594417 L2:00008067
452 01:04:03.594870 L3:14000000
453 01:04:03.599078 B2:00402000
454 01:04:03.599623 B1:e0f83180
455 01:04:03.600141
456 01:04:03.600631 TE: 58167
457 01:04:03.601092
458 01:04:03.604828 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 01:04:03.605350
460 01:04:03.605829 Board ID = 1
461 01:04:03.610274 Set A53 clk to 24M
462 01:04:03.610812 Set A73 clk to 24M
463 01:04:03.611292 Set clk81 to 24M
464 01:04:03.616143 A53 clk: 1200 MHz
465 01:04:03.616710 A73 clk: 1200 MHz
466 01:04:03.617215 CLK81: 166.6M
467 01:04:03.617687 smccc: 00012abe
468 01:04:03.621478 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 01:04:03.627088 board id: 1
470 01:04:03.633009 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 01:04:03.643599 fw parse done
472 01:04:03.649551 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 01:04:03.692222 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 01:04:03.703105 PIEI prepare done
475 01:04:03.703595 fastboot data load
476 01:04:03.704084 fastboot data verify
477 01:04:03.708782 verify result: 266
478 01:04:03.714528 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 01:04:03.715013 LPDDR4 probe
480 01:04:03.715460 ddr clk to 1584MHz
481 01:04:03.722350 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 01:04:03.759795
483 01:04:03.760355 dmc_version 0001
484 01:04:03.766272 Check phy result
485 01:04:03.772187 INFO : End of CA training
486 01:04:03.772665 INFO : End of initialization
487 01:04:03.777723 INFO : Training has run successfully!
488 01:04:03.778198 Check phy result
489 01:04:03.783339 INFO : End of initialization
490 01:04:03.783814 INFO : End of read enable training
491 01:04:03.789081 INFO : End of fine write leveling
492 01:04:03.794570 INFO : End of Write leveling coarse delay
493 01:04:03.795049 INFO : Training has run successfully!
494 01:04:03.795502 Check phy result
495 01:04:03.800201 INFO : End of initialization
496 01:04:03.800686 INFO : End of read dq deskew training
497 01:04:03.805762 INFO : End of MPR read delay center optimization
498 01:04:03.811355 INFO : End of write delay center optimization
499 01:04:03.817099 INFO : End of read delay center optimization
500 01:04:03.817581 INFO : End of max read latency training
501 01:04:03.822538 INFO : Training has run successfully!
502 01:04:03.823015 1D training succeed
503 01:04:03.831702 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 01:04:03.879467 Check phy result
505 01:04:03.880016 INFO : End of initialization
506 01:04:03.901211 INFO : End of 2D read delay Voltage center optimization
507 01:04:03.921328 INFO : End of 2D read delay Voltage center optimization
508 01:04:03.973383 INFO : End of 2D write delay Voltage center optimization
509 01:04:04.022733 INFO : End of 2D write delay Voltage center optimization
510 01:04:04.028335 INFO : Training has run successfully!
511 01:04:04.028814
512 01:04:04.029265 channel==0
513 01:04:04.033902 RxClkDly_Margin_A0==88 ps 9
514 01:04:04.034392 TxDqDly_Margin_A0==98 ps 10
515 01:04:04.039500 RxClkDly_Margin_A1==88 ps 9
516 01:04:04.039971 TxDqDly_Margin_A1==88 ps 9
517 01:04:04.040677 TrainedVREFDQ_A0==74
518 01:04:04.045123 TrainedVREFDQ_A1==74
519 01:04:04.045577 VrefDac_Margin_A0==25
520 01:04:04.045996 DeviceVref_Margin_A0==40
521 01:04:04.050697 VrefDac_Margin_A1==25
522 01:04:04.051136 DeviceVref_Margin_A1==40
523 01:04:04.051547
524 01:04:04.051947
525 01:04:04.052394 channel==1
526 01:04:04.056290 RxClkDly_Margin_A0==98 ps 10
527 01:04:04.056728 TxDqDly_Margin_A0==88 ps 9
528 01:04:04.061874 RxClkDly_Margin_A1==88 ps 9
529 01:04:04.062316 TxDqDly_Margin_A1==88 ps 9
530 01:04:04.067480 TrainedVREFDQ_A0==77
531 01:04:04.067919 TrainedVREFDQ_A1==77
532 01:04:04.068368 VrefDac_Margin_A0==22
533 01:04:04.073102 DeviceVref_Margin_A0==37
534 01:04:04.073540 VrefDac_Margin_A1==24
535 01:04:04.078711 DeviceVref_Margin_A1==37
536 01:04:04.079149
537 01:04:04.079559 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 01:04:04.079958
539 01:04:04.112310 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
540 01:04:04.112811 2D training succeed
541 01:04:04.117916 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 01:04:04.123481 auto size-- 65535DDR cs0 size: 2048MB
543 01:04:04.123937 DDR cs1 size: 2048MB
544 01:04:04.129115 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 01:04:04.129570 cs0 DataBus test pass
546 01:04:04.134722 cs1 DataBus test pass
547 01:04:04.135175 cs0 AddrBus test pass
548 01:04:04.135586 cs1 AddrBus test pass
549 01:04:04.136022
550 01:04:04.140286 100bdlr_step_size ps== 420
551 01:04:04.140752 result report
552 01:04:04.145898 boot times 0Enable ddr reg access
553 01:04:04.151180 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 01:04:04.164610 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 01:04:04.737826 0.0;M3 CHK:0;cm4_sp_mode 0
556 01:04:04.738435 MVN_1=0x00000000
557 01:04:04.743353 MVN_2=0x00000000
558 01:04:04.748961 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 01:04:04.749498 OPS=0x10
560 01:04:04.749959 ring efuse init
561 01:04:04.750366 chipver efuse init
562 01:04:04.754672 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 01:04:04.760294 [0.018961 Inits done]
564 01:04:04.760731 secure task start!
565 01:04:04.761117 high task start!
566 01:04:04.764841 low task start!
567 01:04:04.765300 run into bl31
568 01:04:04.771519 NOTICE: BL31: v1.3(release):4fc40b1
569 01:04:04.779331 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 01:04:04.779789 NOTICE: BL31: G12A normal boot!
571 01:04:04.804589 NOTICE: BL31: BL33 decompress pass
572 01:04:04.810301 ERROR: Error initializing runtime service opteed_fast
573 01:04:06.043183
574 01:04:06.043782
575 01:04:06.051644 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 01:04:06.052140
577 01:04:06.052558 Model: Libre Computer AML-A311D-CC Alta
578 01:04:06.260148 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 01:04:06.283498 DRAM: 2 GiB (effective 3.8 GiB)
580 01:04:06.426406 Core: 408 devices, 31 uclasses, devicetree: separate
581 01:04:06.432199 WDT: Not starting watchdog@f0d0
582 01:04:06.464653 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 01:04:06.476980 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 01:04:06.481873 ** Bad device specification mmc 0 **
585 01:04:06.492256 Card did not respond to voltage select! : -110
586 01:04:06.499890 ** Bad device specification mmc 0 **
587 01:04:06.500382 Couldn't find partition mmc 0
588 01:04:06.508157 Card did not respond to voltage select! : -110
589 01:04:06.513608 ** Bad device specification mmc 0 **
590 01:04:06.514050 Couldn't find partition mmc 0
591 01:04:06.518836 Error: could not access storage.
592 01:04:06.862451 Net: eth0: ethernet@ff3f0000
593 01:04:06.863056 starting USB...
594 01:04:07.114089 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 01:04:07.114691 Starting the controller
596 01:04:07.121235 USB XHCI 1.10
597 01:04:08.831014 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 01:04:08.831620 bl2_stage_init 0x01
599 01:04:08.832085 bl2_stage_init 0x81
600 01:04:08.836614 hw id: 0x0000 - pwm id 0x01
601 01:04:08.837056 bl2_stage_init 0xc1
602 01:04:08.837462 bl2_stage_init 0x02
603 01:04:08.837861
604 01:04:08.842279 L0:00000000
605 01:04:08.842711 L1:20000703
606 01:04:08.843113 L2:00008067
607 01:04:08.843507 L3:14000000
608 01:04:08.847878 B2:00402000
609 01:04:08.848347 B1:e0f83180
610 01:04:08.848745
611 01:04:08.849137 TE: 58167
612 01:04:08.849531
613 01:04:08.853372 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 01:04:08.853811
615 01:04:08.854219 Board ID = 1
616 01:04:08.859058 Set A53 clk to 24M
617 01:04:08.859487 Set A73 clk to 24M
618 01:04:08.859886 Set clk81 to 24M
619 01:04:08.864683 A53 clk: 1200 MHz
620 01:04:08.865119 A73 clk: 1200 MHz
621 01:04:08.865519 CLK81: 166.6M
622 01:04:08.865910 smccc: 00012abd
623 01:04:08.870146 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 01:04:08.875939 board id: 1
625 01:04:08.881748 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 01:04:08.892422 fw parse done
627 01:04:08.898318 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 01:04:08.940960 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 01:04:08.951863 PIEI prepare done
630 01:04:08.952375 fastboot data load
631 01:04:08.952790 fastboot data verify
632 01:04:08.957397 verify result: 266
633 01:04:08.962999 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 01:04:08.963483 LPDDR4 probe
635 01:04:08.963890 ddr clk to 1584MHz
636 01:04:08.970979 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 01:04:09.008273
638 01:04:09.008768 dmc_version 0001
639 01:04:09.014908 Check phy result
640 01:04:09.020819 INFO : End of CA training
641 01:04:09.021246 INFO : End of initialization
642 01:04:09.026325 INFO : Training has run successfully!
643 01:04:09.026753 Check phy result
644 01:04:09.031943 INFO : End of initialization
645 01:04:09.032405 INFO : End of read enable training
646 01:04:09.035270 INFO : End of fine write leveling
647 01:04:09.040915 INFO : End of Write leveling coarse delay
648 01:04:09.046486 INFO : Training has run successfully!
649 01:04:09.046913 Check phy result
650 01:04:09.047317 INFO : End of initialization
651 01:04:09.052174 INFO : End of read dq deskew training
652 01:04:09.055436 INFO : End of MPR read delay center optimization
653 01:04:09.060993 INFO : End of write delay center optimization
654 01:04:09.066596 INFO : End of read delay center optimization
655 01:04:09.067020 INFO : End of max read latency training
656 01:04:09.072260 INFO : Training has run successfully!
657 01:04:09.072719 1D training succeed
658 01:04:09.080454 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 01:04:09.128093 Check phy result
660 01:04:09.128597 INFO : End of initialization
661 01:04:09.150460 INFO : End of 2D read delay Voltage center optimization
662 01:04:09.170551 INFO : End of 2D read delay Voltage center optimization
663 01:04:09.222442 INFO : End of 2D write delay Voltage center optimization
664 01:04:09.271888 INFO : End of 2D write delay Voltage center optimization
665 01:04:09.277352 INFO : Training has run successfully!
666 01:04:09.277920
667 01:04:09.278395 channel==0
668 01:04:09.283118 RxClkDly_Margin_A0==88 ps 9
669 01:04:09.283891 TxDqDly_Margin_A0==98 ps 10
670 01:04:09.286313 RxClkDly_Margin_A1==88 ps 9
671 01:04:09.286840 TxDqDly_Margin_A1==98 ps 10
672 01:04:09.291859 TrainedVREFDQ_A0==74
673 01:04:09.292471 TrainedVREFDQ_A1==74
674 01:04:09.297470 VrefDac_Margin_A0==25
675 01:04:09.298035 DeviceVref_Margin_A0==40
676 01:04:09.298516 VrefDac_Margin_A1==25
677 01:04:09.303134 DeviceVref_Margin_A1==40
678 01:04:09.303727
679 01:04:09.304242
680 01:04:09.304701 channel==1
681 01:04:09.305158 RxClkDly_Margin_A0==98 ps 10
682 01:04:09.306487 TxDqDly_Margin_A0==98 ps 10
683 01:04:09.312139 RxClkDly_Margin_A1==98 ps 10
684 01:04:09.312720 TxDqDly_Margin_A1==88 ps 9
685 01:04:09.313183 TrainedVREFDQ_A0==77
686 01:04:09.317776 TrainedVREFDQ_A1==77
687 01:04:09.318352 VrefDac_Margin_A0==22
688 01:04:09.323377 DeviceVref_Margin_A0==37
689 01:04:09.324013 VrefDac_Margin_A1==22
690 01:04:09.324489 DeviceVref_Margin_A1==37
691 01:04:09.324949
692 01:04:09.329021 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 01:04:09.329602
694 01:04:09.362401 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 01:04:09.363092 2D training succeed
696 01:04:09.368038 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 01:04:09.373543 auto size-- 65535DDR cs0 size: 2048MB
698 01:04:09.374001 DDR cs1 size: 2048MB
699 01:04:09.379139 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 01:04:09.379582 cs0 DataBus test pass
701 01:04:09.380014 cs1 DataBus test pass
702 01:04:09.384745 cs0 AddrBus test pass
703 01:04:09.385181 cs1 AddrBus test pass
704 01:04:09.385577
705 01:04:09.390319 100bdlr_step_size ps== 420
706 01:04:09.390783 result report
707 01:04:09.391174 boot times 0Enable ddr reg access
708 01:04:09.400231 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 01:04:09.413669 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 01:04:09.985734 0.0;M3 CHK:0;cm4_sp_mode 0
711 01:04:09.986292 MVN_1=0x00000000
712 01:04:09.991274 MVN_2=0x00000000
713 01:04:09.997012 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 01:04:09.997555 OPS=0x10
715 01:04:09.997949 ring efuse init
716 01:04:09.998336 chipver efuse init
717 01:04:10.002540 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 01:04:10.008178 [0.018961 Inits done]
719 01:04:10.008616 secure task start!
720 01:04:10.009004 high task start!
721 01:04:10.012754 low task start!
722 01:04:10.013186 run into bl31
723 01:04:10.019403 NOTICE: BL31: v1.3(release):4fc40b1
724 01:04:10.027227 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 01:04:10.027666 NOTICE: BL31: G12A normal boot!
726 01:04:10.053163 NOTICE: BL31: BL33 decompress pass
727 01:04:10.058892 ERROR: Error initializing runtime service opteed_fast
728 01:04:11.291756
729 01:04:11.292355
730 01:04:11.300202 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 01:04:11.300659
732 01:04:11.301073 Model: Libre Computer AML-A311D-CC Alta
733 01:04:11.508507 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 01:04:11.531922 DRAM: 2 GiB (effective 3.8 GiB)
735 01:04:11.674921 Core: 408 devices, 31 uclasses, devicetree: separate
736 01:04:11.680773 WDT: Not starting watchdog@f0d0
737 01:04:11.713058 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 01:04:11.725504 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 01:04:11.730443 ** Bad device specification mmc 0 **
740 01:04:11.740811 Card did not respond to voltage select! : -110
741 01:04:11.748443 ** Bad device specification mmc 0 **
742 01:04:11.748888 Couldn't find partition mmc 0
743 01:04:11.756805 Card did not respond to voltage select! : -110
744 01:04:11.762297 ** Bad device specification mmc 0 **
745 01:04:11.762801 Couldn't find partition mmc 0
746 01:04:11.767342 Error: could not access storage.
747 01:04:12.109865 Net: eth0: ethernet@ff3f0000
748 01:04:12.110468 starting USB...
749 01:04:12.361653 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 01:04:12.362207 Starting the controller
751 01:04:12.368621 USB XHCI 1.10
752 01:04:14.531458 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 01:04:14.532103 bl2_stage_init 0x01
754 01:04:14.532543 bl2_stage_init 0x81
755 01:04:14.536952 hw id: 0x0000 - pwm id 0x01
756 01:04:14.537439 bl2_stage_init 0xc1
757 01:04:14.537875 bl2_stage_init 0x02
758 01:04:14.538291
759 01:04:14.542616 L0:00000000
760 01:04:14.543121 L1:20000703
761 01:04:14.543551 L2:00008067
762 01:04:14.543970 L3:14000000
763 01:04:14.548089 B2:00402000
764 01:04:14.548555 B1:e0f83180
765 01:04:14.548981
766 01:04:14.549397 TE: 58159
767 01:04:14.549802
768 01:04:14.553599 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 01:04:14.554073
770 01:04:14.554508 Board ID = 1
771 01:04:14.559288 Set A53 clk to 24M
772 01:04:14.559765 Set A73 clk to 24M
773 01:04:14.560227 Set clk81 to 24M
774 01:04:14.564843 A53 clk: 1200 MHz
775 01:04:14.565319 A73 clk: 1200 MHz
776 01:04:14.565724 CLK81: 166.6M
777 01:04:14.566124 smccc: 00012ab5
778 01:04:14.570472 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 01:04:14.576063 board id: 1
780 01:04:14.581920 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 01:04:14.592643 fw parse done
782 01:04:14.598577 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 01:04:14.641202 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 01:04:14.652056 PIEI prepare done
785 01:04:14.652545 fastboot data load
786 01:04:14.652958 fastboot data verify
787 01:04:14.657629 verify result: 266
788 01:04:14.663231 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 01:04:14.663745 LPDDR4 probe
790 01:04:14.664189 ddr clk to 1584MHz
791 01:04:14.671219 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 01:04:14.708489
793 01:04:14.709003 dmc_version 0001
794 01:04:14.715171 Check phy result
795 01:04:14.721058 INFO : End of CA training
796 01:04:14.721546 INFO : End of initialization
797 01:04:14.726591 INFO : Training has run successfully!
798 01:04:14.727024 Check phy result
799 01:04:14.732225 INFO : End of initialization
800 01:04:14.732657 INFO : End of read enable training
801 01:04:14.735601 INFO : End of fine write leveling
802 01:04:14.741122 INFO : End of Write leveling coarse delay
803 01:04:14.746751 INFO : Training has run successfully!
804 01:04:14.747178 Check phy result
805 01:04:14.747577 INFO : End of initialization
806 01:04:14.752327 INFO : End of read dq deskew training
807 01:04:14.757932 INFO : End of MPR read delay center optimization
808 01:04:14.758373 INFO : End of write delay center optimization
809 01:04:14.763596 INFO : End of read delay center optimization
810 01:04:14.769107 INFO : End of max read latency training
811 01:04:14.769556 INFO : Training has run successfully!
812 01:04:14.774766 1D training succeed
813 01:04:14.780691 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 01:04:14.828199 Check phy result
815 01:04:14.828659 INFO : End of initialization
816 01:04:14.849880 INFO : End of 2D read delay Voltage center optimization
817 01:04:14.869979 INFO : End of 2D read delay Voltage center optimization
818 01:04:14.921918 INFO : End of 2D write delay Voltage center optimization
819 01:04:14.971088 INFO : End of 2D write delay Voltage center optimization
820 01:04:14.976692 INFO : Training has run successfully!
821 01:04:14.977153
822 01:04:14.977586 channel==0
823 01:04:14.982220 RxClkDly_Margin_A0==88 ps 9
824 01:04:14.982687 TxDqDly_Margin_A0==98 ps 10
825 01:04:14.987911 RxClkDly_Margin_A1==88 ps 9
826 01:04:14.988436 TxDqDly_Margin_A1==98 ps 10
827 01:04:14.988934 TrainedVREFDQ_A0==74
828 01:04:14.993514 TrainedVREFDQ_A1==76
829 01:04:14.994003 VrefDac_Margin_A0==25
830 01:04:14.994421 DeviceVref_Margin_A0==40
831 01:04:14.999130 VrefDac_Margin_A1==25
832 01:04:14.999609 DeviceVref_Margin_A1==38
833 01:04:15.000072
834 01:04:15.000475
835 01:04:15.004682 channel==1
836 01:04:15.005125 RxClkDly_Margin_A0==98 ps 10
837 01:04:15.005527 TxDqDly_Margin_A0==88 ps 9
838 01:04:15.010180 RxClkDly_Margin_A1==98 ps 10
839 01:04:15.010627 TxDqDly_Margin_A1==88 ps 9
840 01:04:15.015883 TrainedVREFDQ_A0==77
841 01:04:15.016364 TrainedVREFDQ_A1==77
842 01:04:15.016772 VrefDac_Margin_A0==22
843 01:04:15.021507 DeviceVref_Margin_A0==37
844 01:04:15.021973 VrefDac_Margin_A1==22
845 01:04:15.027087 DeviceVref_Margin_A1==37
846 01:04:15.027558
847 01:04:15.027948 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 01:04:15.028369
849 01:04:15.060600 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 01:04:15.061114 2D training succeed
851 01:04:15.066171 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 01:04:15.071763 auto size-- 65535DDR cs0 size: 2048MB
853 01:04:15.072227 DDR cs1 size: 2048MB
854 01:04:15.077363 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 01:04:15.077790 cs0 DataBus test pass
856 01:04:15.082969 cs1 DataBus test pass
857 01:04:15.083394 cs0 AddrBus test pass
858 01:04:15.083783 cs1 AddrBus test pass
859 01:04:15.084202
860 01:04:15.088578 100bdlr_step_size ps== 420
861 01:04:15.089009 result report
862 01:04:15.094160 boot times 0Enable ddr reg access
863 01:04:15.099521 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 01:04:15.112976 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 01:04:15.685119 0.0;M3 CHK:0;cm4_sp_mode 0
866 01:04:15.685750 MVN_1=0x00000000
867 01:04:15.690572 MVN_2=0x00000000
868 01:04:15.696291 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 01:04:15.696805 OPS=0x10
870 01:04:15.697235 ring efuse init
871 01:04:15.697661 chipver efuse init
872 01:04:15.701916 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 01:04:15.707607 [0.018961 Inits done]
874 01:04:15.708225 secure task start!
875 01:04:15.708698 high task start!
876 01:04:15.712212 low task start!
877 01:04:15.712744 run into bl31
878 01:04:15.718851 NOTICE: BL31: v1.3(release):4fc40b1
879 01:04:15.726629 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 01:04:15.727174 NOTICE: BL31: G12A normal boot!
881 01:04:15.752073 NOTICE: BL31: BL33 decompress pass
882 01:04:15.757751 ERROR: Error initializing runtime service opteed_fast
883 01:04:16.990563
884 01:04:16.991217
885 01:04:16.999073 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 01:04:16.999620
887 01:04:17.000124 Model: Libre Computer AML-A311D-CC Alta
888 01:04:17.207361 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 01:04:17.230821 DRAM: 2 GiB (effective 3.8 GiB)
890 01:04:17.373734 Core: 408 devices, 31 uclasses, devicetree: separate
891 01:04:17.379600 WDT: Not starting watchdog@f0d0
892 01:04:17.411853 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 01:04:17.424285 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 01:04:17.429282 ** Bad device specification mmc 0 **
895 01:04:17.439616 Card did not respond to voltage select! : -110
896 01:04:17.447302 ** Bad device specification mmc 0 **
897 01:04:17.447840 Couldn't find partition mmc 0
898 01:04:17.455618 Card did not respond to voltage select! : -110
899 01:04:17.461157 ** Bad device specification mmc 0 **
900 01:04:17.461689 Couldn't find partition mmc 0
901 01:04:17.466196 Error: could not access storage.
902 01:04:17.809618 Net: eth0: ethernet@ff3f0000
903 01:04:17.810237 starting USB...
904 01:04:18.061452 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 01:04:18.062009 Starting the controller
906 01:04:18.068459 USB XHCI 1.10
907 01:04:19.622512 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 01:04:19.630805 scanning usb for storage devices... 0 Storage Device(s) found
910 01:04:19.682494 Hit any key to stop autoboot: 1
911 01:04:19.683385 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 01:04:19.684238 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
913 01:04:19.684783 Setting prompt string to ['=>']
914 01:04:19.685314 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
915 01:04:19.698379 0
916 01:04:19.699330 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 01:04:19.699878 Sending with 10 millisecond of delay
919 01:04:20.845493 => setenv autoload no
920 01:04:20.857751 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
921 01:04:20.862748 setenv autoload no
922 01:04:20.863503 Sending with 10 millisecond of delay
924 01:04:22.660443 => setenv initrd_high 0xffffffff
925 01:04:22.671185 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
926 01:04:22.672039 setenv initrd_high 0xffffffff
927 01:04:22.672792 Sending with 10 millisecond of delay
929 01:04:24.289183 => setenv fdt_high 0xffffffff
930 01:04:24.299940 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 01:04:24.300779 setenv fdt_high 0xffffffff
932 01:04:24.301503 Sending with 10 millisecond of delay
934 01:04:24.593353 => dhcp
935 01:04:24.604101 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
936 01:04:24.604899 dhcp
937 01:04:24.605348 Speed: 1000, full duplex
938 01:04:24.605766 BOOTP broadcast 1
939 01:04:24.607592 DHCP client bound to address 192.168.6.27 (3 ms)
940 01:04:24.608340 Sending with 10 millisecond of delay
942 01:04:26.284957 => setenv serverip 192.168.6.2
943 01:04:26.295814 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 01:04:26.296856 setenv serverip 192.168.6.2
945 01:04:26.297676 Sending with 10 millisecond of delay
947 01:04:30.021750 => tftpboot 0x01080000 915239/tftp-deploy-f3c6lltj/kernel/uImage
948 01:04:30.032614 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 01:04:30.033554 tftpboot 0x01080000 915239/tftp-deploy-f3c6lltj/kernel/uImage
950 01:04:30.034045 Speed: 1000, full duplex
951 01:04:30.034500 Using ethernet@ff3f0000 device
952 01:04:30.035540 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 01:04:30.041079 Filename '915239/tftp-deploy-f3c6lltj/kernel/uImage'.
954 01:04:30.045095 Load address: 0x1080000
955 01:04:32.500972 Loading: *################################################## 36.1 MiB
956 01:04:32.501710 14.7 MiB/s
957 01:04:32.502172 done
958 01:04:32.505429 Bytes transferred = 37878336 (241fa40 hex)
959 01:04:32.506232 Sending with 10 millisecond of delay
961 01:04:37.193523 => tftpboot 0x08000000 915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot
962 01:04:37.204340 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 01:04:37.205250 tftpboot 0x08000000 915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot
964 01:04:37.205700 Speed: 1000, full duplex
965 01:04:37.206112 Using ethernet@ff3f0000 device
966 01:04:37.207252 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 01:04:37.215853 Filename '915239/tftp-deploy-f3c6lltj/ramdisk/ramdisk.cpio.gz.uboot'.
968 01:04:37.216454 Load address: 0x8000000
969 01:04:48.862346 Loading: *#T ################################################ UDP wrong checksum 0000000f 0000f25d
970 01:04:53.863433 T UDP wrong checksum 0000000f 0000f25d
971 01:05:03.866730 T T UDP wrong checksum 0000000f 0000f25d
972 01:05:16.299838 T T UDP wrong checksum 000000ff 00002834
973 01:05:16.325340 UDP wrong checksum 000000ff 0000bd26
974 01:05:23.870744 T T UDP wrong checksum 0000000f 0000f25d
975 01:05:38.874607 T T
976 01:05:38.876684 Retry count exceeded; starting again
978 01:05:38.878353 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
981 01:05:38.880527 end: 2.4 uboot-commands (duration 00:01:52) [common]
983 01:05:38.881995 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
985 01:05:38.883097 end: 2 uboot-action (duration 00:01:52) [common]
987 01:05:38.889142 Cleaning after the job
988 01:05:38.891614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/ramdisk
989 01:05:38.893084 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/kernel
990 01:05:38.926889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/dtb
991 01:05:38.928086 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915239/tftp-deploy-f3c6lltj/modules
992 01:05:38.951859 start: 4.1 power-off (timeout 00:00:30) [common]
993 01:05:38.953396 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
994 01:05:38.988127 >> OK - accepted request
995 01:05:38.990108 Returned 0 in 0 seconds
996 01:05:39.091215 end: 4.1 power-off (duration 00:00:00) [common]
998 01:05:39.092605 start: 4.2 read-feedback (timeout 00:10:00) [common]
999 01:05:39.093487 Listened to connection for namespace 'common' for up to 1s
1000 01:05:40.101734 Finalising connection for namespace 'common'
1001 01:05:40.102617 Disconnecting from shell: Finalise
1002 01:05:40.102940 =>
1003 01:05:40.203784 end: 4.2 read-feedback (duration 00:00:01) [common]
1004 01:05:40.204643 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915239
1005 01:05:40.883314 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915239
1006 01:05:40.883910 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.